Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 | 41 | #include "drm_crtc_helper.h" |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 47 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 48 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
49 | |
50 | typedef struct { | |
0206e353 AJ |
51 | /* given values */ |
52 | int n; | |
53 | int m1, m2; | |
54 | int p1, p2; | |
55 | /* derived values */ | |
56 | int dot; | |
57 | int vco; | |
58 | int m; | |
59 | int p; | |
79e53945 JB |
60 | } intel_clock_t; |
61 | ||
62 | typedef struct { | |
0206e353 | 63 | int min, max; |
79e53945 JB |
64 | } intel_range_t; |
65 | ||
66 | typedef struct { | |
0206e353 AJ |
67 | int dot_limit; |
68 | int p2_slow, p2_fast; | |
79e53945 JB |
69 | } intel_p2_t; |
70 | ||
71 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
72 | typedef struct intel_limit intel_limit_t; |
73 | struct intel_limit { | |
0206e353 AJ |
74 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
75 | intel_p2_t p2; | |
76 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 77 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 78 | }; |
79e53945 | 79 | |
2377b741 JB |
80 | /* FDI */ |
81 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
82 | ||
d4906093 ML |
83 | static bool |
84 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
85 | int target, int refclk, intel_clock_t *match_clock, |
86 | intel_clock_t *best_clock); | |
d4906093 ML |
87 | static bool |
88 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
89 | int target, int refclk, intel_clock_t *match_clock, |
90 | intel_clock_t *best_clock); | |
79e53945 | 91 | |
a4fc5ed6 KP |
92 | static bool |
93 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
94 | int target, int refclk, intel_clock_t *match_clock, |
95 | intel_clock_t *best_clock); | |
5eb08b69 | 96 | static bool |
f2b115e6 | 97 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
98 | int target, int refclk, intel_clock_t *match_clock, |
99 | intel_clock_t *best_clock); | |
a4fc5ed6 | 100 | |
a0c4da24 JB |
101 | static bool |
102 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
103 | int target, int refclk, intel_clock_t *match_clock, | |
104 | intel_clock_t *best_clock); | |
105 | ||
021357ac CW |
106 | static inline u32 /* units of 100MHz */ |
107 | intel_fdi_link_freq(struct drm_device *dev) | |
108 | { | |
8b99e68c CW |
109 | if (IS_GEN5(dev)) { |
110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
111 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
112 | } else | |
113 | return 27; | |
021357ac CW |
114 | } |
115 | ||
e4b36699 | 116 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
117 | .dot = { .min = 25000, .max = 350000 }, |
118 | .vco = { .min = 930000, .max = 1400000 }, | |
119 | .n = { .min = 3, .max = 16 }, | |
120 | .m = { .min = 96, .max = 140 }, | |
121 | .m1 = { .min = 18, .max = 26 }, | |
122 | .m2 = { .min = 6, .max = 16 }, | |
123 | .p = { .min = 4, .max = 128 }, | |
124 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
125 | .p2 = { .dot_limit = 165000, |
126 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 127 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
128 | }; |
129 | ||
130 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
131 | .dot = { .min = 25000, .max = 350000 }, |
132 | .vco = { .min = 930000, .max = 1400000 }, | |
133 | .n = { .min = 3, .max = 16 }, | |
134 | .m = { .min = 96, .max = 140 }, | |
135 | .m1 = { .min = 18, .max = 26 }, | |
136 | .m2 = { .min = 6, .max = 16 }, | |
137 | .p = { .min = 4, .max = 128 }, | |
138 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 165000, |
140 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 141 | .find_pll = intel_find_best_PLL, |
e4b36699 | 142 | }; |
273e27ca | 143 | |
e4b36699 | 144 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
145 | .dot = { .min = 20000, .max = 400000 }, |
146 | .vco = { .min = 1400000, .max = 2800000 }, | |
147 | .n = { .min = 1, .max = 6 }, | |
148 | .m = { .min = 70, .max = 120 }, | |
149 | .m1 = { .min = 10, .max = 22 }, | |
150 | .m2 = { .min = 5, .max = 9 }, | |
151 | .p = { .min = 5, .max = 80 }, | |
152 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
153 | .p2 = { .dot_limit = 200000, |
154 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 155 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
156 | }; |
157 | ||
158 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
159 | .dot = { .min = 20000, .max = 400000 }, |
160 | .vco = { .min = 1400000, .max = 2800000 }, | |
161 | .n = { .min = 1, .max = 6 }, | |
162 | .m = { .min = 70, .max = 120 }, | |
163 | .m1 = { .min = 10, .max = 22 }, | |
164 | .m2 = { .min = 5, .max = 9 }, | |
165 | .p = { .min = 7, .max = 98 }, | |
166 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
167 | .p2 = { .dot_limit = 112000, |
168 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 169 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
170 | }; |
171 | ||
273e27ca | 172 | |
e4b36699 | 173 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
174 | .dot = { .min = 25000, .max = 270000 }, |
175 | .vco = { .min = 1750000, .max = 3500000}, | |
176 | .n = { .min = 1, .max = 4 }, | |
177 | .m = { .min = 104, .max = 138 }, | |
178 | .m1 = { .min = 17, .max = 23 }, | |
179 | .m2 = { .min = 5, .max = 11 }, | |
180 | .p = { .min = 10, .max = 30 }, | |
181 | .p1 = { .min = 1, .max = 3}, | |
182 | .p2 = { .dot_limit = 270000, | |
183 | .p2_slow = 10, | |
184 | .p2_fast = 10 | |
044c7c41 | 185 | }, |
d4906093 | 186 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
187 | }; |
188 | ||
189 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
190 | .dot = { .min = 22000, .max = 400000 }, |
191 | .vco = { .min = 1750000, .max = 3500000}, | |
192 | .n = { .min = 1, .max = 4 }, | |
193 | .m = { .min = 104, .max = 138 }, | |
194 | .m1 = { .min = 16, .max = 23 }, | |
195 | .m2 = { .min = 5, .max = 11 }, | |
196 | .p = { .min = 5, .max = 80 }, | |
197 | .p1 = { .min = 1, .max = 8}, | |
198 | .p2 = { .dot_limit = 165000, | |
199 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 200 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
201 | }; |
202 | ||
203 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
204 | .dot = { .min = 20000, .max = 115000 }, |
205 | .vco = { .min = 1750000, .max = 3500000 }, | |
206 | .n = { .min = 1, .max = 3 }, | |
207 | .m = { .min = 104, .max = 138 }, | |
208 | .m1 = { .min = 17, .max = 23 }, | |
209 | .m2 = { .min = 5, .max = 11 }, | |
210 | .p = { .min = 28, .max = 112 }, | |
211 | .p1 = { .min = 2, .max = 8 }, | |
212 | .p2 = { .dot_limit = 0, | |
213 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 214 | }, |
d4906093 | 215 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
216 | }; |
217 | ||
218 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
219 | .dot = { .min = 80000, .max = 224000 }, |
220 | .vco = { .min = 1750000, .max = 3500000 }, | |
221 | .n = { .min = 1, .max = 3 }, | |
222 | .m = { .min = 104, .max = 138 }, | |
223 | .m1 = { .min = 17, .max = 23 }, | |
224 | .m2 = { .min = 5, .max = 11 }, | |
225 | .p = { .min = 14, .max = 42 }, | |
226 | .p1 = { .min = 2, .max = 6 }, | |
227 | .p2 = { .dot_limit = 0, | |
228 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 229 | }, |
d4906093 | 230 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
231 | }; |
232 | ||
233 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
234 | .dot = { .min = 161670, .max = 227000 }, |
235 | .vco = { .min = 1750000, .max = 3500000}, | |
236 | .n = { .min = 1, .max = 2 }, | |
237 | .m = { .min = 97, .max = 108 }, | |
238 | .m1 = { .min = 0x10, .max = 0x12 }, | |
239 | .m2 = { .min = 0x05, .max = 0x06 }, | |
240 | .p = { .min = 10, .max = 20 }, | |
241 | .p1 = { .min = 1, .max = 2}, | |
242 | .p2 = { .dot_limit = 0, | |
273e27ca | 243 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 244 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
245 | }; |
246 | ||
f2b115e6 | 247 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
248 | .dot = { .min = 20000, .max = 400000}, |
249 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 250 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
251 | .n = { .min = 3, .max = 6 }, |
252 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 253 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
254 | .m1 = { .min = 0, .max = 0 }, |
255 | .m2 = { .min = 0, .max = 254 }, | |
256 | .p = { .min = 5, .max = 80 }, | |
257 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
258 | .p2 = { .dot_limit = 200000, |
259 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 260 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
261 | }; |
262 | ||
f2b115e6 | 263 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
264 | .dot = { .min = 20000, .max = 400000 }, |
265 | .vco = { .min = 1700000, .max = 3500000 }, | |
266 | .n = { .min = 3, .max = 6 }, | |
267 | .m = { .min = 2, .max = 256 }, | |
268 | .m1 = { .min = 0, .max = 0 }, | |
269 | .m2 = { .min = 0, .max = 254 }, | |
270 | .p = { .min = 7, .max = 112 }, | |
271 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 112000, |
273 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 274 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
275 | }; |
276 | ||
273e27ca EA |
277 | /* Ironlake / Sandybridge |
278 | * | |
279 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
280 | * the range value for them is (actual_value - 2). | |
281 | */ | |
b91ad0ec | 282 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
283 | .dot = { .min = 25000, .max = 350000 }, |
284 | .vco = { .min = 1760000, .max = 3510000 }, | |
285 | .n = { .min = 1, .max = 5 }, | |
286 | .m = { .min = 79, .max = 127 }, | |
287 | .m1 = { .min = 12, .max = 22 }, | |
288 | .m2 = { .min = 5, .max = 9 }, | |
289 | .p = { .min = 5, .max = 80 }, | |
290 | .p1 = { .min = 1, .max = 8 }, | |
291 | .p2 = { .dot_limit = 225000, | |
292 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 293 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
294 | }; |
295 | ||
b91ad0ec | 296 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
297 | .dot = { .min = 25000, .max = 350000 }, |
298 | .vco = { .min = 1760000, .max = 3510000 }, | |
299 | .n = { .min = 1, .max = 3 }, | |
300 | .m = { .min = 79, .max = 118 }, | |
301 | .m1 = { .min = 12, .max = 22 }, | |
302 | .m2 = { .min = 5, .max = 9 }, | |
303 | .p = { .min = 28, .max = 112 }, | |
304 | .p1 = { .min = 2, .max = 8 }, | |
305 | .p2 = { .dot_limit = 225000, | |
306 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
307 | .find_pll = intel_g4x_find_best_PLL, |
308 | }; | |
309 | ||
310 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
311 | .dot = { .min = 25000, .max = 350000 }, |
312 | .vco = { .min = 1760000, .max = 3510000 }, | |
313 | .n = { .min = 1, .max = 3 }, | |
314 | .m = { .min = 79, .max = 127 }, | |
315 | .m1 = { .min = 12, .max = 22 }, | |
316 | .m2 = { .min = 5, .max = 9 }, | |
317 | .p = { .min = 14, .max = 56 }, | |
318 | .p1 = { .min = 2, .max = 8 }, | |
319 | .p2 = { .dot_limit = 225000, | |
320 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
321 | .find_pll = intel_g4x_find_best_PLL, |
322 | }; | |
323 | ||
273e27ca | 324 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 325 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
326 | .dot = { .min = 25000, .max = 350000 }, |
327 | .vco = { .min = 1760000, .max = 3510000 }, | |
328 | .n = { .min = 1, .max = 2 }, | |
329 | .m = { .min = 79, .max = 126 }, | |
330 | .m1 = { .min = 12, .max = 22 }, | |
331 | .m2 = { .min = 5, .max = 9 }, | |
332 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 333 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
334 | .p2 = { .dot_limit = 225000, |
335 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
336 | .find_pll = intel_g4x_find_best_PLL, |
337 | }; | |
338 | ||
339 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
340 | .dot = { .min = 25000, .max = 350000 }, |
341 | .vco = { .min = 1760000, .max = 3510000 }, | |
342 | .n = { .min = 1, .max = 3 }, | |
343 | .m = { .min = 79, .max = 126 }, | |
344 | .m1 = { .min = 12, .max = 22 }, | |
345 | .m2 = { .min = 5, .max = 9 }, | |
346 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 347 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
348 | .p2 = { .dot_limit = 225000, |
349 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
350 | .find_pll = intel_g4x_find_best_PLL, |
351 | }; | |
352 | ||
353 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
354 | .dot = { .min = 25000, .max = 350000 }, |
355 | .vco = { .min = 1760000, .max = 3510000}, | |
356 | .n = { .min = 1, .max = 2 }, | |
357 | .m = { .min = 81, .max = 90 }, | |
358 | .m1 = { .min = 12, .max = 22 }, | |
359 | .m2 = { .min = 5, .max = 9 }, | |
360 | .p = { .min = 10, .max = 20 }, | |
361 | .p1 = { .min = 1, .max = 2}, | |
362 | .p2 = { .dot_limit = 0, | |
273e27ca | 363 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 364 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
365 | }; |
366 | ||
a0c4da24 JB |
367 | static const intel_limit_t intel_limits_vlv_dac = { |
368 | .dot = { .min = 25000, .max = 270000 }, | |
369 | .vco = { .min = 4000000, .max = 6000000 }, | |
370 | .n = { .min = 1, .max = 7 }, | |
371 | .m = { .min = 22, .max = 450 }, /* guess */ | |
372 | .m1 = { .min = 2, .max = 3 }, | |
373 | .m2 = { .min = 11, .max = 156 }, | |
374 | .p = { .min = 10, .max = 30 }, | |
375 | .p1 = { .min = 2, .max = 3 }, | |
376 | .p2 = { .dot_limit = 270000, | |
377 | .p2_slow = 2, .p2_fast = 20 }, | |
378 | .find_pll = intel_vlv_find_best_pll, | |
379 | }; | |
380 | ||
381 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
382 | .dot = { .min = 20000, .max = 165000 }, | |
383 | .vco = { .min = 5994000, .max = 4000000 }, | |
384 | .n = { .min = 1, .max = 7 }, | |
385 | .m = { .min = 60, .max = 300 }, /* guess */ | |
386 | .m1 = { .min = 2, .max = 3 }, | |
387 | .m2 = { .min = 11, .max = 156 }, | |
388 | .p = { .min = 10, .max = 30 }, | |
389 | .p1 = { .min = 2, .max = 3 }, | |
390 | .p2 = { .dot_limit = 270000, | |
391 | .p2_slow = 2, .p2_fast = 20 }, | |
392 | .find_pll = intel_vlv_find_best_pll, | |
393 | }; | |
394 | ||
395 | static const intel_limit_t intel_limits_vlv_dp = { | |
396 | .dot = { .min = 162000, .max = 270000 }, | |
397 | .vco = { .min = 5994000, .max = 4000000 }, | |
398 | .n = { .min = 1, .max = 7 }, | |
399 | .m = { .min = 60, .max = 300 }, /* guess */ | |
400 | .m1 = { .min = 2, .max = 3 }, | |
401 | .m2 = { .min = 11, .max = 156 }, | |
402 | .p = { .min = 10, .max = 30 }, | |
403 | .p1 = { .min = 2, .max = 3 }, | |
404 | .p2 = { .dot_limit = 270000, | |
405 | .p2_slow = 2, .p2_fast = 20 }, | |
406 | .find_pll = intel_vlv_find_best_pll, | |
407 | }; | |
408 | ||
57f350b6 JB |
409 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
410 | { | |
411 | unsigned long flags; | |
412 | u32 val = 0; | |
413 | ||
414 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
415 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
416 | DRM_ERROR("DPIO idle wait timed out\n"); | |
417 | goto out_unlock; | |
418 | } | |
419 | ||
420 | I915_WRITE(DPIO_REG, reg); | |
421 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
422 | DPIO_BYTE); | |
423 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
424 | DRM_ERROR("DPIO read wait timed out\n"); | |
425 | goto out_unlock; | |
426 | } | |
427 | val = I915_READ(DPIO_DATA); | |
428 | ||
429 | out_unlock: | |
430 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
431 | return val; | |
432 | } | |
433 | ||
a0c4da24 JB |
434 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
435 | u32 val) | |
436 | { | |
437 | unsigned long flags; | |
438 | ||
439 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
440 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
441 | DRM_ERROR("DPIO idle wait timed out\n"); | |
442 | goto out_unlock; | |
443 | } | |
444 | ||
445 | I915_WRITE(DPIO_DATA, val); | |
446 | I915_WRITE(DPIO_REG, reg); | |
447 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
448 | DPIO_BYTE); | |
449 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
450 | DRM_ERROR("DPIO write wait timed out\n"); | |
451 | ||
452 | out_unlock: | |
453 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
454 | } | |
455 | ||
57f350b6 JB |
456 | static void vlv_init_dpio(struct drm_device *dev) |
457 | { | |
458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
459 | ||
460 | /* Reset the DPIO config */ | |
461 | I915_WRITE(DPIO_CTL, 0); | |
462 | POSTING_READ(DPIO_CTL); | |
463 | I915_WRITE(DPIO_CTL, 1); | |
464 | POSTING_READ(DPIO_CTL); | |
465 | } | |
466 | ||
618563e3 DV |
467 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
468 | { | |
469 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
470 | return 1; | |
471 | } | |
472 | ||
473 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
474 | { | |
475 | .callback = intel_dual_link_lvds_callback, | |
476 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
477 | .matches = { | |
478 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
479 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
480 | }, | |
481 | }, | |
482 | { } /* terminating entry */ | |
483 | }; | |
484 | ||
b0354385 TI |
485 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
486 | unsigned int reg) | |
487 | { | |
488 | unsigned int val; | |
489 | ||
121d527a TI |
490 | /* use the module option value if specified */ |
491 | if (i915_lvds_channel_mode > 0) | |
492 | return i915_lvds_channel_mode == 2; | |
493 | ||
618563e3 DV |
494 | if (dmi_check_system(intel_dual_link_lvds)) |
495 | return true; | |
496 | ||
b0354385 TI |
497 | if (dev_priv->lvds_val) |
498 | val = dev_priv->lvds_val; | |
499 | else { | |
500 | /* BIOS should set the proper LVDS register value at boot, but | |
501 | * in reality, it doesn't set the value when the lid is closed; | |
502 | * we need to check "the value to be set" in VBT when LVDS | |
503 | * register is uninitialized. | |
504 | */ | |
505 | val = I915_READ(reg); | |
14d94a3d | 506 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
b0354385 TI |
507 | val = dev_priv->bios_lvds_val; |
508 | dev_priv->lvds_val = val; | |
509 | } | |
510 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; | |
511 | } | |
512 | ||
1b894b59 CW |
513 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
514 | int refclk) | |
2c07245f | 515 | { |
b91ad0ec ZW |
516 | struct drm_device *dev = crtc->dev; |
517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 518 | const intel_limit_t *limit; |
b91ad0ec ZW |
519 | |
520 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 521 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
b91ad0ec | 522 | /* LVDS dual channel */ |
1b894b59 | 523 | if (refclk == 100000) |
b91ad0ec ZW |
524 | limit = &intel_limits_ironlake_dual_lvds_100m; |
525 | else | |
526 | limit = &intel_limits_ironlake_dual_lvds; | |
527 | } else { | |
1b894b59 | 528 | if (refclk == 100000) |
b91ad0ec ZW |
529 | limit = &intel_limits_ironlake_single_lvds_100m; |
530 | else | |
531 | limit = &intel_limits_ironlake_single_lvds; | |
532 | } | |
533 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
534 | HAS_eDP) |
535 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 536 | else |
b91ad0ec | 537 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
538 | |
539 | return limit; | |
540 | } | |
541 | ||
044c7c41 ML |
542 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
543 | { | |
544 | struct drm_device *dev = crtc->dev; | |
545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
546 | const intel_limit_t *limit; | |
547 | ||
548 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 549 | if (is_dual_link_lvds(dev_priv, LVDS)) |
044c7c41 | 550 | /* LVDS with dual channel */ |
e4b36699 | 551 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
552 | else |
553 | /* LVDS with dual channel */ | |
e4b36699 | 554 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
555 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
556 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 557 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 558 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 559 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 560 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 561 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 562 | } else /* The option is for other outputs */ |
e4b36699 | 563 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
564 | |
565 | return limit; | |
566 | } | |
567 | ||
1b894b59 | 568 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
569 | { |
570 | struct drm_device *dev = crtc->dev; | |
571 | const intel_limit_t *limit; | |
572 | ||
bad720ff | 573 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 574 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 575 | else if (IS_G4X(dev)) { |
044c7c41 | 576 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 577 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 578 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 579 | limit = &intel_limits_pineview_lvds; |
2177832f | 580 | else |
f2b115e6 | 581 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
582 | } else if (IS_VALLEYVIEW(dev)) { |
583 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
584 | limit = &intel_limits_vlv_dac; | |
585 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
586 | limit = &intel_limits_vlv_hdmi; | |
587 | else | |
588 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
589 | } else if (!IS_GEN2(dev)) { |
590 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
591 | limit = &intel_limits_i9xx_lvds; | |
592 | else | |
593 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
594 | } else { |
595 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 596 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 597 | else |
e4b36699 | 598 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
599 | } |
600 | return limit; | |
601 | } | |
602 | ||
f2b115e6 AJ |
603 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
604 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 605 | { |
2177832f SL |
606 | clock->m = clock->m2 + 2; |
607 | clock->p = clock->p1 * clock->p2; | |
608 | clock->vco = refclk * clock->m / clock->n; | |
609 | clock->dot = clock->vco / clock->p; | |
610 | } | |
611 | ||
612 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
613 | { | |
f2b115e6 AJ |
614 | if (IS_PINEVIEW(dev)) { |
615 | pineview_clock(refclk, clock); | |
2177832f SL |
616 | return; |
617 | } | |
79e53945 JB |
618 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
619 | clock->p = clock->p1 * clock->p2; | |
620 | clock->vco = refclk * clock->m / (clock->n + 2); | |
621 | clock->dot = clock->vco / clock->p; | |
622 | } | |
623 | ||
79e53945 JB |
624 | /** |
625 | * Returns whether any output on the specified pipe is of the specified type | |
626 | */ | |
4ef69c7a | 627 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 628 | { |
4ef69c7a | 629 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
630 | struct intel_encoder *encoder; |
631 | ||
6c2b7c12 DV |
632 | for_each_encoder_on_crtc(dev, crtc, encoder) |
633 | if (encoder->type == type) | |
4ef69c7a CW |
634 | return true; |
635 | ||
636 | return false; | |
79e53945 JB |
637 | } |
638 | ||
7c04d1d9 | 639 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
640 | /** |
641 | * Returns whether the given set of divisors are valid for a given refclk with | |
642 | * the given connectors. | |
643 | */ | |
644 | ||
1b894b59 CW |
645 | static bool intel_PLL_is_valid(struct drm_device *dev, |
646 | const intel_limit_t *limit, | |
647 | const intel_clock_t *clock) | |
79e53945 | 648 | { |
79e53945 | 649 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 650 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 651 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 652 | INTELPllInvalid("p out of range\n"); |
79e53945 | 653 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 654 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 655 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 656 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 657 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 658 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 659 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 660 | INTELPllInvalid("m out of range\n"); |
79e53945 | 661 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 662 | INTELPllInvalid("n out of range\n"); |
79e53945 | 663 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 664 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
665 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
666 | * connector, etc., rather than just a single range. | |
667 | */ | |
668 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 669 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
670 | |
671 | return true; | |
672 | } | |
673 | ||
d4906093 ML |
674 | static bool |
675 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
676 | int target, int refclk, intel_clock_t *match_clock, |
677 | intel_clock_t *best_clock) | |
d4906093 | 678 | |
79e53945 JB |
679 | { |
680 | struct drm_device *dev = crtc->dev; | |
681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
682 | intel_clock_t clock; | |
79e53945 JB |
683 | int err = target; |
684 | ||
bc5e5718 | 685 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 686 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
687 | /* |
688 | * For LVDS, if the panel is on, just rely on its current | |
689 | * settings for dual-channel. We haven't figured out how to | |
690 | * reliably set up different single/dual channel state, if we | |
691 | * even can. | |
692 | */ | |
b0354385 | 693 | if (is_dual_link_lvds(dev_priv, LVDS)) |
79e53945 JB |
694 | clock.p2 = limit->p2.p2_fast; |
695 | else | |
696 | clock.p2 = limit->p2.p2_slow; | |
697 | } else { | |
698 | if (target < limit->p2.dot_limit) | |
699 | clock.p2 = limit->p2.p2_slow; | |
700 | else | |
701 | clock.p2 = limit->p2.p2_fast; | |
702 | } | |
703 | ||
0206e353 | 704 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 705 | |
42158660 ZY |
706 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
707 | clock.m1++) { | |
708 | for (clock.m2 = limit->m2.min; | |
709 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
710 | /* m1 is always 0 in Pineview */ |
711 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
712 | break; |
713 | for (clock.n = limit->n.min; | |
714 | clock.n <= limit->n.max; clock.n++) { | |
715 | for (clock.p1 = limit->p1.min; | |
716 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
717 | int this_err; |
718 | ||
2177832f | 719 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
720 | if (!intel_PLL_is_valid(dev, limit, |
721 | &clock)) | |
79e53945 | 722 | continue; |
cec2f356 SP |
723 | if (match_clock && |
724 | clock.p != match_clock->p) | |
725 | continue; | |
79e53945 JB |
726 | |
727 | this_err = abs(clock.dot - target); | |
728 | if (this_err < err) { | |
729 | *best_clock = clock; | |
730 | err = this_err; | |
731 | } | |
732 | } | |
733 | } | |
734 | } | |
735 | } | |
736 | ||
737 | return (err != target); | |
738 | } | |
739 | ||
d4906093 ML |
740 | static bool |
741 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
742 | int target, int refclk, intel_clock_t *match_clock, |
743 | intel_clock_t *best_clock) | |
d4906093 ML |
744 | { |
745 | struct drm_device *dev = crtc->dev; | |
746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
747 | intel_clock_t clock; | |
748 | int max_n; | |
749 | bool found; | |
6ba770dc AJ |
750 | /* approximately equals target * 0.00585 */ |
751 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
752 | found = false; |
753 | ||
754 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
755 | int lvds_reg; |
756 | ||
c619eed4 | 757 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
758 | lvds_reg = PCH_LVDS; |
759 | else | |
760 | lvds_reg = LVDS; | |
761 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
762 | LVDS_CLKB_POWER_UP) |
763 | clock.p2 = limit->p2.p2_fast; | |
764 | else | |
765 | clock.p2 = limit->p2.p2_slow; | |
766 | } else { | |
767 | if (target < limit->p2.dot_limit) | |
768 | clock.p2 = limit->p2.p2_slow; | |
769 | else | |
770 | clock.p2 = limit->p2.p2_fast; | |
771 | } | |
772 | ||
773 | memset(best_clock, 0, sizeof(*best_clock)); | |
774 | max_n = limit->n.max; | |
f77f13e2 | 775 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 776 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 777 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
778 | for (clock.m1 = limit->m1.max; |
779 | clock.m1 >= limit->m1.min; clock.m1--) { | |
780 | for (clock.m2 = limit->m2.max; | |
781 | clock.m2 >= limit->m2.min; clock.m2--) { | |
782 | for (clock.p1 = limit->p1.max; | |
783 | clock.p1 >= limit->p1.min; clock.p1--) { | |
784 | int this_err; | |
785 | ||
2177832f | 786 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
787 | if (!intel_PLL_is_valid(dev, limit, |
788 | &clock)) | |
d4906093 | 789 | continue; |
cec2f356 SP |
790 | if (match_clock && |
791 | clock.p != match_clock->p) | |
792 | continue; | |
1b894b59 CW |
793 | |
794 | this_err = abs(clock.dot - target); | |
d4906093 ML |
795 | if (this_err < err_most) { |
796 | *best_clock = clock; | |
797 | err_most = this_err; | |
798 | max_n = clock.n; | |
799 | found = true; | |
800 | } | |
801 | } | |
802 | } | |
803 | } | |
804 | } | |
2c07245f ZW |
805 | return found; |
806 | } | |
807 | ||
5eb08b69 | 808 | static bool |
f2b115e6 | 809 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
810 | int target, int refclk, intel_clock_t *match_clock, |
811 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
812 | { |
813 | struct drm_device *dev = crtc->dev; | |
814 | intel_clock_t clock; | |
4547668a | 815 | |
5eb08b69 ZW |
816 | if (target < 200000) { |
817 | clock.n = 1; | |
818 | clock.p1 = 2; | |
819 | clock.p2 = 10; | |
820 | clock.m1 = 12; | |
821 | clock.m2 = 9; | |
822 | } else { | |
823 | clock.n = 2; | |
824 | clock.p1 = 1; | |
825 | clock.p2 = 10; | |
826 | clock.m1 = 14; | |
827 | clock.m2 = 8; | |
828 | } | |
829 | intel_clock(dev, refclk, &clock); | |
830 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
831 | return true; | |
832 | } | |
833 | ||
a4fc5ed6 KP |
834 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
835 | static bool | |
836 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
837 | int target, int refclk, intel_clock_t *match_clock, |
838 | intel_clock_t *best_clock) | |
a4fc5ed6 | 839 | { |
5eddb70b CW |
840 | intel_clock_t clock; |
841 | if (target < 200000) { | |
842 | clock.p1 = 2; | |
843 | clock.p2 = 10; | |
844 | clock.n = 2; | |
845 | clock.m1 = 23; | |
846 | clock.m2 = 8; | |
847 | } else { | |
848 | clock.p1 = 1; | |
849 | clock.p2 = 10; | |
850 | clock.n = 1; | |
851 | clock.m1 = 14; | |
852 | clock.m2 = 2; | |
853 | } | |
854 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
855 | clock.p = (clock.p1 * clock.p2); | |
856 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
857 | clock.vco = 0; | |
858 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
859 | return true; | |
a4fc5ed6 | 860 | } |
a0c4da24 JB |
861 | static bool |
862 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
863 | int target, int refclk, intel_clock_t *match_clock, | |
864 | intel_clock_t *best_clock) | |
865 | { | |
866 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
867 | u32 m, n, fastclk; | |
868 | u32 updrate, minupdate, fracbits, p; | |
869 | unsigned long bestppm, ppm, absppm; | |
870 | int dotclk, flag; | |
871 | ||
af447bd3 | 872 | flag = 0; |
a0c4da24 JB |
873 | dotclk = target * 1000; |
874 | bestppm = 1000000; | |
875 | ppm = absppm = 0; | |
876 | fastclk = dotclk / (2*100); | |
877 | updrate = 0; | |
878 | minupdate = 19200; | |
879 | fracbits = 1; | |
880 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; | |
881 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
882 | ||
883 | /* based on hardware requirement, prefer smaller n to precision */ | |
884 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
885 | updrate = refclk / n; | |
886 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
887 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
888 | if (p2 > 10) | |
889 | p2 = p2 - 1; | |
890 | p = p1 * p2; | |
891 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
892 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
893 | m2 = (((2*(fastclk * p * n / m1 )) + | |
894 | refclk) / (2*refclk)); | |
895 | m = m1 * m2; | |
896 | vco = updrate * m; | |
897 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
898 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
899 | absppm = (ppm > 0) ? ppm : (-ppm); | |
900 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
901 | bestppm = 0; | |
902 | flag = 1; | |
903 | } | |
904 | if (absppm < bestppm - 10) { | |
905 | bestppm = absppm; | |
906 | flag = 1; | |
907 | } | |
908 | if (flag) { | |
909 | bestn = n; | |
910 | bestm1 = m1; | |
911 | bestm2 = m2; | |
912 | bestp1 = p1; | |
913 | bestp2 = p2; | |
914 | flag = 0; | |
915 | } | |
916 | } | |
917 | } | |
918 | } | |
919 | } | |
920 | } | |
921 | best_clock->n = bestn; | |
922 | best_clock->m1 = bestm1; | |
923 | best_clock->m2 = bestm2; | |
924 | best_clock->p1 = bestp1; | |
925 | best_clock->p2 = bestp2; | |
926 | ||
927 | return true; | |
928 | } | |
a4fc5ed6 | 929 | |
a928d536 PZ |
930 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
931 | { | |
932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
933 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
934 | ||
935 | frame = I915_READ(frame_reg); | |
936 | ||
937 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
938 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
939 | } | |
940 | ||
9d0498a2 JB |
941 | /** |
942 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
943 | * @dev: drm device | |
944 | * @pipe: pipe to wait for | |
945 | * | |
946 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
947 | * mode setting code. | |
948 | */ | |
949 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 950 | { |
9d0498a2 | 951 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 952 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 953 | |
a928d536 PZ |
954 | if (INTEL_INFO(dev)->gen >= 5) { |
955 | ironlake_wait_for_vblank(dev, pipe); | |
956 | return; | |
957 | } | |
958 | ||
300387c0 CW |
959 | /* Clear existing vblank status. Note this will clear any other |
960 | * sticky status fields as well. | |
961 | * | |
962 | * This races with i915_driver_irq_handler() with the result | |
963 | * that either function could miss a vblank event. Here it is not | |
964 | * fatal, as we will either wait upon the next vblank interrupt or | |
965 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
966 | * called during modeset at which time the GPU should be idle and | |
967 | * should *not* be performing page flips and thus not waiting on | |
968 | * vblanks... | |
969 | * Currently, the result of us stealing a vblank from the irq | |
970 | * handler is that a single frame will be skipped during swapbuffers. | |
971 | */ | |
972 | I915_WRITE(pipestat_reg, | |
973 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
974 | ||
9d0498a2 | 975 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
976 | if (wait_for(I915_READ(pipestat_reg) & |
977 | PIPE_VBLANK_INTERRUPT_STATUS, | |
978 | 50)) | |
9d0498a2 JB |
979 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
980 | } | |
981 | ||
ab7ad7f6 KP |
982 | /* |
983 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
984 | * @dev: drm device |
985 | * @pipe: pipe to wait for | |
986 | * | |
987 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
988 | * spinning on the vblank interrupt status bit, since we won't actually | |
989 | * see an interrupt when the pipe is disabled. | |
990 | * | |
ab7ad7f6 KP |
991 | * On Gen4 and above: |
992 | * wait for the pipe register state bit to turn off | |
993 | * | |
994 | * Otherwise: | |
995 | * wait for the display line value to settle (it usually | |
996 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 997 | * |
9d0498a2 | 998 | */ |
58e10eb9 | 999 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
1000 | { |
1001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
1002 | |
1003 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 1004 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
1005 | |
1006 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1007 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1008 | 100)) | |
284637d9 | 1009 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1010 | } else { |
837ba00f | 1011 | u32 last_line, line_mask; |
58e10eb9 | 1012 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
1013 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
1014 | ||
837ba00f PZ |
1015 | if (IS_GEN2(dev)) |
1016 | line_mask = DSL_LINEMASK_GEN2; | |
1017 | else | |
1018 | line_mask = DSL_LINEMASK_GEN3; | |
1019 | ||
ab7ad7f6 KP |
1020 | /* Wait for the display line to settle */ |
1021 | do { | |
837ba00f | 1022 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 1023 | mdelay(5); |
837ba00f | 1024 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
1025 | time_after(timeout, jiffies)); |
1026 | if (time_after(jiffies, timeout)) | |
284637d9 | 1027 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1028 | } |
79e53945 JB |
1029 | } |
1030 | ||
b24e7179 JB |
1031 | static const char *state_string(bool enabled) |
1032 | { | |
1033 | return enabled ? "on" : "off"; | |
1034 | } | |
1035 | ||
1036 | /* Only for pre-ILK configs */ | |
1037 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1038 | enum pipe pipe, bool state) | |
1039 | { | |
1040 | int reg; | |
1041 | u32 val; | |
1042 | bool cur_state; | |
1043 | ||
1044 | reg = DPLL(pipe); | |
1045 | val = I915_READ(reg); | |
1046 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1047 | WARN(cur_state != state, | |
1048 | "PLL state assertion failure (expected %s, current %s)\n", | |
1049 | state_string(state), state_string(cur_state)); | |
1050 | } | |
1051 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1052 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1053 | ||
040484af JB |
1054 | /* For ILK+ */ |
1055 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
92b27b08 CW |
1056 | struct intel_pch_pll *pll, |
1057 | struct intel_crtc *crtc, | |
1058 | bool state) | |
040484af | 1059 | { |
040484af JB |
1060 | u32 val; |
1061 | bool cur_state; | |
1062 | ||
9d82aa17 ED |
1063 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1064 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1065 | return; | |
1066 | } | |
1067 | ||
92b27b08 CW |
1068 | if (WARN (!pll, |
1069 | "asserting PCH PLL %s with no PLL\n", state_string(state))) | |
ee7b9f93 | 1070 | return; |
ee7b9f93 | 1071 | |
92b27b08 CW |
1072 | val = I915_READ(pll->pll_reg); |
1073 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1074 | WARN(cur_state != state, | |
1075 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", | |
1076 | pll->pll_reg, state_string(state), state_string(cur_state), val); | |
1077 | ||
1078 | /* Make sure the selected PLL is correctly attached to the transcoder */ | |
1079 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { | |
d3ccbe86 JB |
1080 | u32 pch_dpll; |
1081 | ||
1082 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
92b27b08 CW |
1083 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1084 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, | |
1085 | "PLL[%d] not attached to this transcoder %d: %08x\n", | |
1086 | cur_state, crtc->pipe, pch_dpll)) { | |
1087 | cur_state = !!(val >> (4*crtc->pipe + 3)); | |
1088 | WARN(cur_state != state, | |
1089 | "PLL[%d] not %s on this transcoder %d: %08x\n", | |
1090 | pll->pll_reg == _PCH_DPLL_B, | |
1091 | state_string(state), | |
1092 | crtc->pipe, | |
1093 | val); | |
1094 | } | |
d3ccbe86 | 1095 | } |
040484af | 1096 | } |
92b27b08 CW |
1097 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1098 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) | |
040484af JB |
1099 | |
1100 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1101 | enum pipe pipe, bool state) | |
1102 | { | |
1103 | int reg; | |
1104 | u32 val; | |
1105 | bool cur_state; | |
1106 | ||
bf507ef7 ED |
1107 | if (IS_HASWELL(dev_priv->dev)) { |
1108 | /* On Haswell, DDI is used instead of FDI_TX_CTL */ | |
1109 | reg = DDI_FUNC_CTL(pipe); | |
1110 | val = I915_READ(reg); | |
1111 | cur_state = !!(val & PIPE_DDI_FUNC_ENABLE); | |
1112 | } else { | |
1113 | reg = FDI_TX_CTL(pipe); | |
1114 | val = I915_READ(reg); | |
1115 | cur_state = !!(val & FDI_TX_ENABLE); | |
1116 | } | |
040484af JB |
1117 | WARN(cur_state != state, |
1118 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1119 | state_string(state), state_string(cur_state)); | |
1120 | } | |
1121 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1122 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1123 | ||
1124 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1125 | enum pipe pipe, bool state) | |
1126 | { | |
1127 | int reg; | |
1128 | u32 val; | |
1129 | bool cur_state; | |
1130 | ||
59c859d6 ED |
1131 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1132 | DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n"); | |
1133 | return; | |
1134 | } else { | |
1135 | reg = FDI_RX_CTL(pipe); | |
1136 | val = I915_READ(reg); | |
1137 | cur_state = !!(val & FDI_RX_ENABLE); | |
1138 | } | |
040484af JB |
1139 | WARN(cur_state != state, |
1140 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1141 | state_string(state), state_string(cur_state)); | |
1142 | } | |
1143 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1144 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1145 | ||
1146 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1147 | enum pipe pipe) | |
1148 | { | |
1149 | int reg; | |
1150 | u32 val; | |
1151 | ||
1152 | /* ILK FDI PLL is always enabled */ | |
1153 | if (dev_priv->info->gen == 5) | |
1154 | return; | |
1155 | ||
bf507ef7 ED |
1156 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1157 | if (IS_HASWELL(dev_priv->dev)) | |
1158 | return; | |
1159 | ||
040484af JB |
1160 | reg = FDI_TX_CTL(pipe); |
1161 | val = I915_READ(reg); | |
1162 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1163 | } | |
1164 | ||
1165 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1166 | enum pipe pipe) | |
1167 | { | |
1168 | int reg; | |
1169 | u32 val; | |
1170 | ||
59c859d6 ED |
1171 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1172 | DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n"); | |
1173 | return; | |
1174 | } | |
040484af JB |
1175 | reg = FDI_RX_CTL(pipe); |
1176 | val = I915_READ(reg); | |
1177 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1178 | } | |
1179 | ||
ea0760cf JB |
1180 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1181 | enum pipe pipe) | |
1182 | { | |
1183 | int pp_reg, lvds_reg; | |
1184 | u32 val; | |
1185 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1186 | bool locked = true; |
ea0760cf JB |
1187 | |
1188 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1189 | pp_reg = PCH_PP_CONTROL; | |
1190 | lvds_reg = PCH_LVDS; | |
1191 | } else { | |
1192 | pp_reg = PP_CONTROL; | |
1193 | lvds_reg = LVDS; | |
1194 | } | |
1195 | ||
1196 | val = I915_READ(pp_reg); | |
1197 | if (!(val & PANEL_POWER_ON) || | |
1198 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1199 | locked = false; | |
1200 | ||
1201 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1202 | panel_pipe = PIPE_B; | |
1203 | ||
1204 | WARN(panel_pipe == pipe && locked, | |
1205 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1206 | pipe_name(pipe)); |
ea0760cf JB |
1207 | } |
1208 | ||
b840d907 JB |
1209 | void assert_pipe(struct drm_i915_private *dev_priv, |
1210 | enum pipe pipe, bool state) | |
b24e7179 JB |
1211 | { |
1212 | int reg; | |
1213 | u32 val; | |
63d7bbe9 | 1214 | bool cur_state; |
b24e7179 | 1215 | |
8e636784 DV |
1216 | /* if we need the pipe A quirk it must be always on */ |
1217 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1218 | state = true; | |
1219 | ||
b24e7179 JB |
1220 | reg = PIPECONF(pipe); |
1221 | val = I915_READ(reg); | |
63d7bbe9 JB |
1222 | cur_state = !!(val & PIPECONF_ENABLE); |
1223 | WARN(cur_state != state, | |
1224 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1225 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1226 | } |
1227 | ||
931872fc CW |
1228 | static void assert_plane(struct drm_i915_private *dev_priv, |
1229 | enum plane plane, bool state) | |
b24e7179 JB |
1230 | { |
1231 | int reg; | |
1232 | u32 val; | |
931872fc | 1233 | bool cur_state; |
b24e7179 JB |
1234 | |
1235 | reg = DSPCNTR(plane); | |
1236 | val = I915_READ(reg); | |
931872fc CW |
1237 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1238 | WARN(cur_state != state, | |
1239 | "plane %c assertion failure (expected %s, current %s)\n", | |
1240 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1241 | } |
1242 | ||
931872fc CW |
1243 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1244 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1245 | ||
b24e7179 JB |
1246 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1247 | enum pipe pipe) | |
1248 | { | |
1249 | int reg, i; | |
1250 | u32 val; | |
1251 | int cur_pipe; | |
1252 | ||
19ec1358 | 1253 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
1254 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1255 | reg = DSPCNTR(pipe); | |
1256 | val = I915_READ(reg); | |
1257 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1258 | "plane %c assertion failure, should be disabled but not\n", | |
1259 | plane_name(pipe)); | |
19ec1358 | 1260 | return; |
28c05794 | 1261 | } |
19ec1358 | 1262 | |
b24e7179 JB |
1263 | /* Need to check both planes against the pipe */ |
1264 | for (i = 0; i < 2; i++) { | |
1265 | reg = DSPCNTR(i); | |
1266 | val = I915_READ(reg); | |
1267 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1268 | DISPPLANE_SEL_PIPE_SHIFT; | |
1269 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1270 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1271 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1272 | } |
1273 | } | |
1274 | ||
92f2584a JB |
1275 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1276 | { | |
1277 | u32 val; | |
1278 | bool enabled; | |
1279 | ||
9d82aa17 ED |
1280 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1281 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1282 | return; | |
1283 | } | |
1284 | ||
92f2584a JB |
1285 | val = I915_READ(PCH_DREF_CONTROL); |
1286 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1287 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1288 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1289 | } | |
1290 | ||
1291 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1292 | enum pipe pipe) | |
1293 | { | |
1294 | int reg; | |
1295 | u32 val; | |
1296 | bool enabled; | |
1297 | ||
1298 | reg = TRANSCONF(pipe); | |
1299 | val = I915_READ(reg); | |
1300 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1301 | WARN(enabled, |
1302 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1303 | pipe_name(pipe)); | |
92f2584a JB |
1304 | } |
1305 | ||
4e634389 KP |
1306 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1307 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1308 | { |
1309 | if ((val & DP_PORT_EN) == 0) | |
1310 | return false; | |
1311 | ||
1312 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1313 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1314 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1315 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1316 | return false; | |
1317 | } else { | |
1318 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1319 | return false; | |
1320 | } | |
1321 | return true; | |
1322 | } | |
1323 | ||
1519b995 KP |
1324 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1325 | enum pipe pipe, u32 val) | |
1326 | { | |
1327 | if ((val & PORT_ENABLE) == 0) | |
1328 | return false; | |
1329 | ||
1330 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1331 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1332 | return false; | |
1333 | } else { | |
1334 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1335 | return false; | |
1336 | } | |
1337 | return true; | |
1338 | } | |
1339 | ||
1340 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1341 | enum pipe pipe, u32 val) | |
1342 | { | |
1343 | if ((val & LVDS_PORT_EN) == 0) | |
1344 | return false; | |
1345 | ||
1346 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1347 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1348 | return false; | |
1349 | } else { | |
1350 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1351 | return false; | |
1352 | } | |
1353 | return true; | |
1354 | } | |
1355 | ||
1356 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1357 | enum pipe pipe, u32 val) | |
1358 | { | |
1359 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1360 | return false; | |
1361 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1362 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1363 | return false; | |
1364 | } else { | |
1365 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1366 | return false; | |
1367 | } | |
1368 | return true; | |
1369 | } | |
1370 | ||
291906f1 | 1371 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1372 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1373 | { |
47a05eca | 1374 | u32 val = I915_READ(reg); |
4e634389 | 1375 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1376 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1377 | reg, pipe_name(pipe)); |
de9a35ab DV |
1378 | |
1379 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), | |
1380 | "IBX PCH dp port still using transcoder B\n"); | |
291906f1 JB |
1381 | } |
1382 | ||
1383 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1384 | enum pipe pipe, int reg) | |
1385 | { | |
47a05eca | 1386 | u32 val = I915_READ(reg); |
e9a851ed | 1387 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1388 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1389 | reg, pipe_name(pipe)); |
de9a35ab DV |
1390 | |
1391 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), | |
1392 | "IBX PCH hdmi port still using transcoder B\n"); | |
291906f1 JB |
1393 | } |
1394 | ||
1395 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1396 | enum pipe pipe) | |
1397 | { | |
1398 | int reg; | |
1399 | u32 val; | |
291906f1 | 1400 | |
f0575e92 KP |
1401 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1402 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1403 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1404 | |
1405 | reg = PCH_ADPA; | |
1406 | val = I915_READ(reg); | |
e9a851ed | 1407 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1408 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1409 | pipe_name(pipe)); |
291906f1 JB |
1410 | |
1411 | reg = PCH_LVDS; | |
1412 | val = I915_READ(reg); | |
e9a851ed | 1413 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1414 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1415 | pipe_name(pipe)); |
291906f1 JB |
1416 | |
1417 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1418 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1419 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1420 | } | |
1421 | ||
63d7bbe9 JB |
1422 | /** |
1423 | * intel_enable_pll - enable a PLL | |
1424 | * @dev_priv: i915 private structure | |
1425 | * @pipe: pipe PLL to enable | |
1426 | * | |
1427 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1428 | * make sure the PLL reg is writable first though, since the panel write | |
1429 | * protect mechanism may be enabled. | |
1430 | * | |
1431 | * Note! This is for pre-ILK only. | |
7434a255 TR |
1432 | * |
1433 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. | |
63d7bbe9 | 1434 | */ |
a37b9b34 | 1435 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 JB |
1436 | { |
1437 | int reg; | |
1438 | u32 val; | |
1439 | ||
1440 | /* No really, not for ILK+ */ | |
a0c4da24 | 1441 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1442 | |
1443 | /* PLL is protected by panel, make sure we can write it */ | |
1444 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1445 | assert_panel_unlocked(dev_priv, pipe); | |
1446 | ||
1447 | reg = DPLL(pipe); | |
1448 | val = I915_READ(reg); | |
1449 | val |= DPLL_VCO_ENABLE; | |
1450 | ||
1451 | /* We do this three times for luck */ | |
1452 | I915_WRITE(reg, val); | |
1453 | POSTING_READ(reg); | |
1454 | udelay(150); /* wait for warmup */ | |
1455 | I915_WRITE(reg, val); | |
1456 | POSTING_READ(reg); | |
1457 | udelay(150); /* wait for warmup */ | |
1458 | I915_WRITE(reg, val); | |
1459 | POSTING_READ(reg); | |
1460 | udelay(150); /* wait for warmup */ | |
1461 | } | |
1462 | ||
1463 | /** | |
1464 | * intel_disable_pll - disable a PLL | |
1465 | * @dev_priv: i915 private structure | |
1466 | * @pipe: pipe PLL to disable | |
1467 | * | |
1468 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1469 | * | |
1470 | * Note! This is for pre-ILK only. | |
1471 | */ | |
1472 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1473 | { | |
1474 | int reg; | |
1475 | u32 val; | |
1476 | ||
1477 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1478 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1479 | return; | |
1480 | ||
1481 | /* Make sure the pipe isn't still relying on us */ | |
1482 | assert_pipe_disabled(dev_priv, pipe); | |
1483 | ||
1484 | reg = DPLL(pipe); | |
1485 | val = I915_READ(reg); | |
1486 | val &= ~DPLL_VCO_ENABLE; | |
1487 | I915_WRITE(reg, val); | |
1488 | POSTING_READ(reg); | |
1489 | } | |
1490 | ||
a416edef ED |
1491 | /* SBI access */ |
1492 | static void | |
1493 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value) | |
1494 | { | |
1495 | unsigned long flags; | |
1496 | ||
1497 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
39fb50f6 | 1498 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1499 | 100)) { |
1500 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
1501 | goto out_unlock; | |
1502 | } | |
1503 | ||
1504 | I915_WRITE(SBI_ADDR, | |
1505 | (reg << 16)); | |
1506 | I915_WRITE(SBI_DATA, | |
1507 | value); | |
1508 | I915_WRITE(SBI_CTL_STAT, | |
1509 | SBI_BUSY | | |
1510 | SBI_CTL_OP_CRWR); | |
1511 | ||
39fb50f6 | 1512 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1513 | 100)) { |
1514 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
1515 | goto out_unlock; | |
1516 | } | |
1517 | ||
1518 | out_unlock: | |
1519 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
1520 | } | |
1521 | ||
1522 | static u32 | |
1523 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) | |
1524 | { | |
1525 | unsigned long flags; | |
39fb50f6 | 1526 | u32 value = 0; |
a416edef ED |
1527 | |
1528 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
39fb50f6 | 1529 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1530 | 100)) { |
1531 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
1532 | goto out_unlock; | |
1533 | } | |
1534 | ||
1535 | I915_WRITE(SBI_ADDR, | |
1536 | (reg << 16)); | |
1537 | I915_WRITE(SBI_CTL_STAT, | |
1538 | SBI_BUSY | | |
1539 | SBI_CTL_OP_CRRD); | |
1540 | ||
39fb50f6 | 1541 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1542 | 100)) { |
1543 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
1544 | goto out_unlock; | |
1545 | } | |
1546 | ||
1547 | value = I915_READ(SBI_DATA); | |
1548 | ||
1549 | out_unlock: | |
1550 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
1551 | return value; | |
1552 | } | |
1553 | ||
92f2584a JB |
1554 | /** |
1555 | * intel_enable_pch_pll - enable PCH PLL | |
1556 | * @dev_priv: i915 private structure | |
1557 | * @pipe: pipe PLL to enable | |
1558 | * | |
1559 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1560 | * drives the transcoder clock. | |
1561 | */ | |
ee7b9f93 | 1562 | static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1563 | { |
ee7b9f93 | 1564 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
48da64a8 | 1565 | struct intel_pch_pll *pll; |
92f2584a JB |
1566 | int reg; |
1567 | u32 val; | |
1568 | ||
48da64a8 | 1569 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1570 | BUG_ON(dev_priv->info->gen < 5); |
48da64a8 CW |
1571 | pll = intel_crtc->pch_pll; |
1572 | if (pll == NULL) | |
1573 | return; | |
1574 | ||
1575 | if (WARN_ON(pll->refcount == 0)) | |
1576 | return; | |
ee7b9f93 JB |
1577 | |
1578 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", | |
1579 | pll->pll_reg, pll->active, pll->on, | |
1580 | intel_crtc->base.base.id); | |
92f2584a JB |
1581 | |
1582 | /* PCH refclock must be enabled first */ | |
1583 | assert_pch_refclk_enabled(dev_priv); | |
1584 | ||
ee7b9f93 | 1585 | if (pll->active++ && pll->on) { |
92b27b08 | 1586 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
ee7b9f93 JB |
1587 | return; |
1588 | } | |
1589 | ||
1590 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); | |
1591 | ||
1592 | reg = pll->pll_reg; | |
92f2584a JB |
1593 | val = I915_READ(reg); |
1594 | val |= DPLL_VCO_ENABLE; | |
1595 | I915_WRITE(reg, val); | |
1596 | POSTING_READ(reg); | |
1597 | udelay(200); | |
ee7b9f93 JB |
1598 | |
1599 | pll->on = true; | |
92f2584a JB |
1600 | } |
1601 | ||
ee7b9f93 | 1602 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1603 | { |
ee7b9f93 JB |
1604 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1605 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
92f2584a | 1606 | int reg; |
ee7b9f93 | 1607 | u32 val; |
4c609cb8 | 1608 | |
92f2584a JB |
1609 | /* PCH only available on ILK+ */ |
1610 | BUG_ON(dev_priv->info->gen < 5); | |
ee7b9f93 JB |
1611 | if (pll == NULL) |
1612 | return; | |
92f2584a | 1613 | |
48da64a8 CW |
1614 | if (WARN_ON(pll->refcount == 0)) |
1615 | return; | |
7a419866 | 1616 | |
ee7b9f93 JB |
1617 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1618 | pll->pll_reg, pll->active, pll->on, | |
1619 | intel_crtc->base.base.id); | |
7a419866 | 1620 | |
48da64a8 | 1621 | if (WARN_ON(pll->active == 0)) { |
92b27b08 | 1622 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
48da64a8 CW |
1623 | return; |
1624 | } | |
1625 | ||
ee7b9f93 | 1626 | if (--pll->active) { |
92b27b08 | 1627 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
7a419866 | 1628 | return; |
ee7b9f93 JB |
1629 | } |
1630 | ||
1631 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); | |
1632 | ||
1633 | /* Make sure transcoder isn't still depending on us */ | |
1634 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); | |
7a419866 | 1635 | |
ee7b9f93 | 1636 | reg = pll->pll_reg; |
92f2584a JB |
1637 | val = I915_READ(reg); |
1638 | val &= ~DPLL_VCO_ENABLE; | |
1639 | I915_WRITE(reg, val); | |
1640 | POSTING_READ(reg); | |
1641 | udelay(200); | |
ee7b9f93 JB |
1642 | |
1643 | pll->on = false; | |
92f2584a JB |
1644 | } |
1645 | ||
040484af JB |
1646 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1647 | enum pipe pipe) | |
1648 | { | |
1649 | int reg; | |
5f7f726d | 1650 | u32 val, pipeconf_val; |
7c26e5c6 | 1651 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
040484af JB |
1652 | |
1653 | /* PCH only available on ILK+ */ | |
1654 | BUG_ON(dev_priv->info->gen < 5); | |
1655 | ||
1656 | /* Make sure PCH DPLL is enabled */ | |
92b27b08 CW |
1657 | assert_pch_pll_enabled(dev_priv, |
1658 | to_intel_crtc(crtc)->pch_pll, | |
1659 | to_intel_crtc(crtc)); | |
040484af JB |
1660 | |
1661 | /* FDI must be feeding us bits for PCH ports */ | |
1662 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1663 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1664 | ||
59c859d6 ED |
1665 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1666 | DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n"); | |
1667 | return; | |
1668 | } | |
040484af JB |
1669 | reg = TRANSCONF(pipe); |
1670 | val = I915_READ(reg); | |
5f7f726d | 1671 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1672 | |
1673 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1674 | /* | |
1675 | * make the BPC in transcoder be consistent with | |
1676 | * that in pipeconf reg. | |
1677 | */ | |
1678 | val &= ~PIPE_BPC_MASK; | |
5f7f726d | 1679 | val |= pipeconf_val & PIPE_BPC_MASK; |
e9bcff5c | 1680 | } |
5f7f726d PZ |
1681 | |
1682 | val &= ~TRANS_INTERLACE_MASK; | |
1683 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1684 | if (HAS_PCH_IBX(dev_priv->dev) && |
1685 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1686 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1687 | else | |
1688 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1689 | else |
1690 | val |= TRANS_PROGRESSIVE; | |
1691 | ||
040484af JB |
1692 | I915_WRITE(reg, val | TRANS_ENABLE); |
1693 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1694 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1695 | } | |
1696 | ||
1697 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1698 | enum pipe pipe) | |
1699 | { | |
1700 | int reg; | |
1701 | u32 val; | |
1702 | ||
1703 | /* FDI relies on the transcoder */ | |
1704 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1705 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1706 | ||
291906f1 JB |
1707 | /* Ports must be off as well */ |
1708 | assert_pch_ports_disabled(dev_priv, pipe); | |
1709 | ||
040484af JB |
1710 | reg = TRANSCONF(pipe); |
1711 | val = I915_READ(reg); | |
1712 | val &= ~TRANS_ENABLE; | |
1713 | I915_WRITE(reg, val); | |
1714 | /* wait for PCH transcoder off, transcoder state */ | |
1715 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1716 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
040484af JB |
1717 | } |
1718 | ||
b24e7179 | 1719 | /** |
309cfea8 | 1720 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1721 | * @dev_priv: i915 private structure |
1722 | * @pipe: pipe to enable | |
040484af | 1723 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1724 | * |
1725 | * Enable @pipe, making sure that various hardware specific requirements | |
1726 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1727 | * | |
1728 | * @pipe should be %PIPE_A or %PIPE_B. | |
1729 | * | |
1730 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1731 | * returning. | |
1732 | */ | |
040484af JB |
1733 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1734 | bool pch_port) | |
b24e7179 JB |
1735 | { |
1736 | int reg; | |
1737 | u32 val; | |
1738 | ||
1739 | /* | |
1740 | * A pipe without a PLL won't actually be able to drive bits from | |
1741 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1742 | * need the check. | |
1743 | */ | |
1744 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1745 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1746 | else { |
1747 | if (pch_port) { | |
1748 | /* if driving the PCH, we need FDI enabled */ | |
1749 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1750 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1751 | } | |
1752 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1753 | } | |
b24e7179 JB |
1754 | |
1755 | reg = PIPECONF(pipe); | |
1756 | val = I915_READ(reg); | |
00d70b15 CW |
1757 | if (val & PIPECONF_ENABLE) |
1758 | return; | |
1759 | ||
1760 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1761 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1762 | } | |
1763 | ||
1764 | /** | |
309cfea8 | 1765 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1766 | * @dev_priv: i915 private structure |
1767 | * @pipe: pipe to disable | |
1768 | * | |
1769 | * Disable @pipe, making sure that various hardware specific requirements | |
1770 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1771 | * | |
1772 | * @pipe should be %PIPE_A or %PIPE_B. | |
1773 | * | |
1774 | * Will wait until the pipe has shut down before returning. | |
1775 | */ | |
1776 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1777 | enum pipe pipe) | |
1778 | { | |
1779 | int reg; | |
1780 | u32 val; | |
1781 | ||
1782 | /* | |
1783 | * Make sure planes won't keep trying to pump pixels to us, | |
1784 | * or we might hang the display. | |
1785 | */ | |
1786 | assert_planes_disabled(dev_priv, pipe); | |
1787 | ||
1788 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1789 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1790 | return; | |
1791 | ||
1792 | reg = PIPECONF(pipe); | |
1793 | val = I915_READ(reg); | |
00d70b15 CW |
1794 | if ((val & PIPECONF_ENABLE) == 0) |
1795 | return; | |
1796 | ||
1797 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1798 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1799 | } | |
1800 | ||
d74362c9 KP |
1801 | /* |
1802 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1803 | * trigger in order to latch. The display address reg provides this. | |
1804 | */ | |
6f1d69b0 | 1805 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1806 | enum plane plane) |
1807 | { | |
1808 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1809 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1810 | } | |
1811 | ||
b24e7179 JB |
1812 | /** |
1813 | * intel_enable_plane - enable a display plane on a given pipe | |
1814 | * @dev_priv: i915 private structure | |
1815 | * @plane: plane to enable | |
1816 | * @pipe: pipe being fed | |
1817 | * | |
1818 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1819 | */ | |
1820 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1821 | enum plane plane, enum pipe pipe) | |
1822 | { | |
1823 | int reg; | |
1824 | u32 val; | |
1825 | ||
1826 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1827 | assert_pipe_enabled(dev_priv, pipe); | |
1828 | ||
1829 | reg = DSPCNTR(plane); | |
1830 | val = I915_READ(reg); | |
00d70b15 CW |
1831 | if (val & DISPLAY_PLANE_ENABLE) |
1832 | return; | |
1833 | ||
1834 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1835 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1836 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1837 | } | |
1838 | ||
b24e7179 JB |
1839 | /** |
1840 | * intel_disable_plane - disable a display plane | |
1841 | * @dev_priv: i915 private structure | |
1842 | * @plane: plane to disable | |
1843 | * @pipe: pipe consuming the data | |
1844 | * | |
1845 | * Disable @plane; should be an independent operation. | |
1846 | */ | |
1847 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1848 | enum plane plane, enum pipe pipe) | |
1849 | { | |
1850 | int reg; | |
1851 | u32 val; | |
1852 | ||
1853 | reg = DSPCNTR(plane); | |
1854 | val = I915_READ(reg); | |
00d70b15 CW |
1855 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1856 | return; | |
1857 | ||
1858 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1859 | intel_flush_display_plane(dev_priv, plane); |
1860 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1861 | } | |
1862 | ||
47a05eca | 1863 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1864 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1865 | { |
1866 | u32 val = I915_READ(reg); | |
4e634389 | 1867 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1868 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1869 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1870 | } |
47a05eca JB |
1871 | } |
1872 | ||
1873 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1874 | enum pipe pipe, int reg) | |
1875 | { | |
1876 | u32 val = I915_READ(reg); | |
e9a851ed | 1877 | if (hdmi_pipe_enabled(dev_priv, pipe, val)) { |
f0575e92 KP |
1878 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1879 | reg, pipe); | |
47a05eca | 1880 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1881 | } |
47a05eca JB |
1882 | } |
1883 | ||
1884 | /* Disable any ports connected to this transcoder */ | |
1885 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1886 | enum pipe pipe) | |
1887 | { | |
1888 | u32 reg, val; | |
1889 | ||
1890 | val = I915_READ(PCH_PP_CONTROL); | |
1891 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1892 | ||
f0575e92 KP |
1893 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1894 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1895 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1896 | |
1897 | reg = PCH_ADPA; | |
1898 | val = I915_READ(reg); | |
e9a851ed | 1899 | if (adpa_pipe_enabled(dev_priv, pipe, val)) |
47a05eca JB |
1900 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1901 | ||
1902 | reg = PCH_LVDS; | |
1903 | val = I915_READ(reg); | |
e9a851ed | 1904 | if (lvds_pipe_enabled(dev_priv, pipe, val)) { |
1519b995 | 1905 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); |
47a05eca JB |
1906 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1907 | POSTING_READ(reg); | |
1908 | udelay(100); | |
1909 | } | |
1910 | ||
1911 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1912 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1913 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1914 | } | |
1915 | ||
127bd2ac | 1916 | int |
48b956c5 | 1917 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1918 | struct drm_i915_gem_object *obj, |
919926ae | 1919 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1920 | { |
ce453d81 | 1921 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1922 | u32 alignment; |
1923 | int ret; | |
1924 | ||
05394f39 | 1925 | switch (obj->tiling_mode) { |
6b95a207 | 1926 | case I915_TILING_NONE: |
534843da CW |
1927 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1928 | alignment = 128 * 1024; | |
a6c45cf0 | 1929 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1930 | alignment = 4 * 1024; |
1931 | else | |
1932 | alignment = 64 * 1024; | |
6b95a207 KH |
1933 | break; |
1934 | case I915_TILING_X: | |
1935 | /* pin() will align the object as required by fence */ | |
1936 | alignment = 0; | |
1937 | break; | |
1938 | case I915_TILING_Y: | |
1939 | /* FIXME: Is this true? */ | |
1940 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1941 | return -EINVAL; | |
1942 | default: | |
1943 | BUG(); | |
1944 | } | |
1945 | ||
ce453d81 | 1946 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1947 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1948 | if (ret) |
ce453d81 | 1949 | goto err_interruptible; |
6b95a207 KH |
1950 | |
1951 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1952 | * fence, whereas 965+ only requires a fence if using | |
1953 | * framebuffer compression. For simplicity, we always install | |
1954 | * a fence as the cost is not that onerous. | |
1955 | */ | |
06d98131 | 1956 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1957 | if (ret) |
1958 | goto err_unpin; | |
1690e1eb | 1959 | |
9a5a53b3 | 1960 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1961 | |
ce453d81 | 1962 | dev_priv->mm.interruptible = true; |
6b95a207 | 1963 | return 0; |
48b956c5 CW |
1964 | |
1965 | err_unpin: | |
1966 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1967 | err_interruptible: |
1968 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1969 | return ret; |
6b95a207 KH |
1970 | } |
1971 | ||
1690e1eb CW |
1972 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1973 | { | |
1974 | i915_gem_object_unpin_fence(obj); | |
1975 | i915_gem_object_unpin(obj); | |
1976 | } | |
1977 | ||
c2c75131 DV |
1978 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1979 | * is assumed to be a power-of-two. */ | |
1980 | static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y, | |
1981 | unsigned int bpp, | |
1982 | unsigned int pitch) | |
1983 | { | |
1984 | int tile_rows, tiles; | |
1985 | ||
1986 | tile_rows = *y / 8; | |
1987 | *y %= 8; | |
1988 | tiles = *x / (512/bpp); | |
1989 | *x %= 512/bpp; | |
1990 | ||
1991 | return tile_rows * pitch * 8 + tiles * 4096; | |
1992 | } | |
1993 | ||
17638cd6 JB |
1994 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1995 | int x, int y) | |
81255565 JB |
1996 | { |
1997 | struct drm_device *dev = crtc->dev; | |
1998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1999 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2000 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2001 | struct drm_i915_gem_object *obj; |
81255565 | 2002 | int plane = intel_crtc->plane; |
e506a0c6 | 2003 | unsigned long linear_offset; |
81255565 | 2004 | u32 dspcntr; |
5eddb70b | 2005 | u32 reg; |
81255565 JB |
2006 | |
2007 | switch (plane) { | |
2008 | case 0: | |
2009 | case 1: | |
2010 | break; | |
2011 | default: | |
2012 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2013 | return -EINVAL; | |
2014 | } | |
2015 | ||
2016 | intel_fb = to_intel_framebuffer(fb); | |
2017 | obj = intel_fb->obj; | |
81255565 | 2018 | |
5eddb70b CW |
2019 | reg = DSPCNTR(plane); |
2020 | dspcntr = I915_READ(reg); | |
81255565 JB |
2021 | /* Mask out pixel format bits in case we change it */ |
2022 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2023 | switch (fb->bits_per_pixel) { | |
2024 | case 8: | |
2025 | dspcntr |= DISPPLANE_8BPP; | |
2026 | break; | |
2027 | case 16: | |
2028 | if (fb->depth == 15) | |
2029 | dspcntr |= DISPPLANE_15_16BPP; | |
2030 | else | |
2031 | dspcntr |= DISPPLANE_16BPP; | |
2032 | break; | |
2033 | case 24: | |
2034 | case 32: | |
2035 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2036 | break; | |
2037 | default: | |
17638cd6 | 2038 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2039 | return -EINVAL; |
2040 | } | |
a6c45cf0 | 2041 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2042 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2043 | dspcntr |= DISPPLANE_TILED; |
2044 | else | |
2045 | dspcntr &= ~DISPPLANE_TILED; | |
2046 | } | |
2047 | ||
5eddb70b | 2048 | I915_WRITE(reg, dspcntr); |
81255565 | 2049 | |
e506a0c6 | 2050 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2051 | |
c2c75131 DV |
2052 | if (INTEL_INFO(dev)->gen >= 4) { |
2053 | intel_crtc->dspaddr_offset = | |
2054 | gen4_compute_dspaddr_offset_xtiled(&x, &y, | |
2055 | fb->bits_per_pixel / 8, | |
2056 | fb->pitches[0]); | |
2057 | linear_offset -= intel_crtc->dspaddr_offset; | |
2058 | } else { | |
e506a0c6 | 2059 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2060 | } |
e506a0c6 DV |
2061 | |
2062 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | |
2063 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2064 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2065 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 DV |
2066 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2067 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
5eddb70b | 2068 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2069 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2070 | } else |
e506a0c6 | 2071 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
5eddb70b | 2072 | POSTING_READ(reg); |
81255565 | 2073 | |
17638cd6 JB |
2074 | return 0; |
2075 | } | |
2076 | ||
2077 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2078 | struct drm_framebuffer *fb, int x, int y) | |
2079 | { | |
2080 | struct drm_device *dev = crtc->dev; | |
2081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2083 | struct intel_framebuffer *intel_fb; | |
2084 | struct drm_i915_gem_object *obj; | |
2085 | int plane = intel_crtc->plane; | |
e506a0c6 | 2086 | unsigned long linear_offset; |
17638cd6 JB |
2087 | u32 dspcntr; |
2088 | u32 reg; | |
2089 | ||
2090 | switch (plane) { | |
2091 | case 0: | |
2092 | case 1: | |
27f8227b | 2093 | case 2: |
17638cd6 JB |
2094 | break; |
2095 | default: | |
2096 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2097 | return -EINVAL; | |
2098 | } | |
2099 | ||
2100 | intel_fb = to_intel_framebuffer(fb); | |
2101 | obj = intel_fb->obj; | |
2102 | ||
2103 | reg = DSPCNTR(plane); | |
2104 | dspcntr = I915_READ(reg); | |
2105 | /* Mask out pixel format bits in case we change it */ | |
2106 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2107 | switch (fb->bits_per_pixel) { | |
2108 | case 8: | |
2109 | dspcntr |= DISPPLANE_8BPP; | |
2110 | break; | |
2111 | case 16: | |
2112 | if (fb->depth != 16) | |
2113 | return -EINVAL; | |
2114 | ||
2115 | dspcntr |= DISPPLANE_16BPP; | |
2116 | break; | |
2117 | case 24: | |
2118 | case 32: | |
2119 | if (fb->depth == 24) | |
2120 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2121 | else if (fb->depth == 30) | |
2122 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2123 | else | |
2124 | return -EINVAL; | |
2125 | break; | |
2126 | default: | |
2127 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2128 | return -EINVAL; | |
2129 | } | |
2130 | ||
2131 | if (obj->tiling_mode != I915_TILING_NONE) | |
2132 | dspcntr |= DISPPLANE_TILED; | |
2133 | else | |
2134 | dspcntr &= ~DISPPLANE_TILED; | |
2135 | ||
2136 | /* must disable */ | |
2137 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2138 | ||
2139 | I915_WRITE(reg, dspcntr); | |
2140 | ||
e506a0c6 | 2141 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 DV |
2142 | intel_crtc->dspaddr_offset = |
2143 | gen4_compute_dspaddr_offset_xtiled(&x, &y, | |
2144 | fb->bits_per_pixel / 8, | |
2145 | fb->pitches[0]); | |
2146 | linear_offset -= intel_crtc->dspaddr_offset; | |
17638cd6 | 2147 | |
e506a0c6 DV |
2148 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2149 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2150 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 DV |
2151 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2152 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
17638cd6 | 2153 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2154 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
17638cd6 JB |
2155 | POSTING_READ(reg); |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
2160 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2161 | static int | |
2162 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2163 | int x, int y, enum mode_set_atomic state) | |
2164 | { | |
2165 | struct drm_device *dev = crtc->dev; | |
2166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2167 | |
6b8e6ed0 CW |
2168 | if (dev_priv->display.disable_fbc) |
2169 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2170 | intel_increase_pllclock(crtc); |
81255565 | 2171 | |
6b8e6ed0 | 2172 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2173 | } |
2174 | ||
14667a4b CW |
2175 | static int |
2176 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2177 | { | |
2178 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2179 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2180 | bool was_interruptible = dev_priv->mm.interruptible; | |
2181 | int ret; | |
2182 | ||
2183 | wait_event(dev_priv->pending_flip_queue, | |
2184 | atomic_read(&dev_priv->mm.wedged) || | |
2185 | atomic_read(&obj->pending_flip) == 0); | |
2186 | ||
2187 | /* Big Hammer, we also need to ensure that any pending | |
2188 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2189 | * current scanout is retired before unpinning the old | |
2190 | * framebuffer. | |
2191 | * | |
2192 | * This should only fail upon a hung GPU, in which case we | |
2193 | * can safely continue. | |
2194 | */ | |
2195 | dev_priv->mm.interruptible = false; | |
2196 | ret = i915_gem_object_finish_gpu(obj); | |
2197 | dev_priv->mm.interruptible = was_interruptible; | |
2198 | ||
2199 | return ret; | |
2200 | } | |
2201 | ||
5c3b82e2 | 2202 | static int |
3c4fdcfb | 2203 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2204 | struct drm_framebuffer *fb) |
79e53945 JB |
2205 | { |
2206 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2207 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
2208 | struct drm_i915_master_private *master_priv; |
2209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
94352cf9 | 2210 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2211 | int ret; |
79e53945 JB |
2212 | |
2213 | /* no fb bound */ | |
94352cf9 | 2214 | if (!fb) { |
a5071c2f | 2215 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2216 | return 0; |
2217 | } | |
2218 | ||
5826eca5 ED |
2219 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2220 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", | |
2221 | intel_crtc->plane, | |
2222 | dev_priv->num_pipe); | |
5c3b82e2 | 2223 | return -EINVAL; |
79e53945 JB |
2224 | } |
2225 | ||
5c3b82e2 | 2226 | mutex_lock(&dev->struct_mutex); |
265db958 | 2227 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2228 | to_intel_framebuffer(fb)->obj, |
919926ae | 2229 | NULL); |
5c3b82e2 CW |
2230 | if (ret != 0) { |
2231 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2232 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2233 | return ret; |
2234 | } | |
79e53945 | 2235 | |
94352cf9 DV |
2236 | if (crtc->fb) |
2237 | intel_finish_fb(crtc->fb); | |
265db958 | 2238 | |
94352cf9 | 2239 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2240 | if (ret) { |
94352cf9 | 2241 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2242 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2243 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2244 | return ret; |
79e53945 | 2245 | } |
3c4fdcfb | 2246 | |
94352cf9 DV |
2247 | old_fb = crtc->fb; |
2248 | crtc->fb = fb; | |
2249 | ||
b7f1de28 CW |
2250 | if (old_fb) { |
2251 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2252 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2253 | } |
652c393a | 2254 | |
6b8e6ed0 | 2255 | intel_update_fbc(dev); |
5c3b82e2 | 2256 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2257 | |
2258 | if (!dev->primary->master) | |
5c3b82e2 | 2259 | return 0; |
79e53945 JB |
2260 | |
2261 | master_priv = dev->primary->master->driver_priv; | |
2262 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2263 | return 0; |
79e53945 | 2264 | |
265db958 | 2265 | if (intel_crtc->pipe) { |
79e53945 JB |
2266 | master_priv->sarea_priv->pipeB_x = x; |
2267 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2268 | } else { |
2269 | master_priv->sarea_priv->pipeA_x = x; | |
2270 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2271 | } |
5c3b82e2 CW |
2272 | |
2273 | return 0; | |
79e53945 JB |
2274 | } |
2275 | ||
5eddb70b | 2276 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2277 | { |
2278 | struct drm_device *dev = crtc->dev; | |
2279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2280 | u32 dpa_ctl; | |
2281 | ||
28c97730 | 2282 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2283 | dpa_ctl = I915_READ(DP_A); |
2284 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2285 | ||
2286 | if (clock < 200000) { | |
2287 | u32 temp; | |
2288 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2289 | /* workaround for 160Mhz: | |
2290 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2291 | 2) program 0x46010 bit 0 = 1 | |
2292 | 3) program 0x46034 bit 24 = 1 | |
2293 | 4) program 0x64000 bit 14 = 1 | |
2294 | */ | |
2295 | temp = I915_READ(0x4600c); | |
2296 | temp &= 0xffff0000; | |
2297 | I915_WRITE(0x4600c, temp | 0x8124); | |
2298 | ||
2299 | temp = I915_READ(0x46010); | |
2300 | I915_WRITE(0x46010, temp | 1); | |
2301 | ||
2302 | temp = I915_READ(0x46034); | |
2303 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2304 | } else { | |
2305 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2306 | } | |
2307 | I915_WRITE(DP_A, dpa_ctl); | |
2308 | ||
5eddb70b | 2309 | POSTING_READ(DP_A); |
32f9d658 ZW |
2310 | udelay(500); |
2311 | } | |
2312 | ||
5e84e1a4 ZW |
2313 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2314 | { | |
2315 | struct drm_device *dev = crtc->dev; | |
2316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2318 | int pipe = intel_crtc->pipe; | |
2319 | u32 reg, temp; | |
2320 | ||
2321 | /* enable normal train */ | |
2322 | reg = FDI_TX_CTL(pipe); | |
2323 | temp = I915_READ(reg); | |
61e499bf | 2324 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2325 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2326 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2327 | } else { |
2328 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2329 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2330 | } |
5e84e1a4 ZW |
2331 | I915_WRITE(reg, temp); |
2332 | ||
2333 | reg = FDI_RX_CTL(pipe); | |
2334 | temp = I915_READ(reg); | |
2335 | if (HAS_PCH_CPT(dev)) { | |
2336 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2337 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2338 | } else { | |
2339 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2340 | temp |= FDI_LINK_TRAIN_NONE; | |
2341 | } | |
2342 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2343 | ||
2344 | /* wait one idle pattern time */ | |
2345 | POSTING_READ(reg); | |
2346 | udelay(1000); | |
357555c0 JB |
2347 | |
2348 | /* IVB wants error correction enabled */ | |
2349 | if (IS_IVYBRIDGE(dev)) | |
2350 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2351 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2352 | } |
2353 | ||
291427f5 JB |
2354 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2355 | { | |
2356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2357 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2358 | ||
2359 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2360 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2361 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2362 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2363 | POSTING_READ(SOUTH_CHICKEN1); | |
2364 | } | |
2365 | ||
8db9d77b ZW |
2366 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2367 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2368 | { | |
2369 | struct drm_device *dev = crtc->dev; | |
2370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2372 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2373 | int plane = intel_crtc->plane; |
5eddb70b | 2374 | u32 reg, temp, tries; |
8db9d77b | 2375 | |
0fc932b8 JB |
2376 | /* FDI needs bits from pipe & plane first */ |
2377 | assert_pipe_enabled(dev_priv, pipe); | |
2378 | assert_plane_enabled(dev_priv, plane); | |
2379 | ||
e1a44743 AJ |
2380 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2381 | for train result */ | |
5eddb70b CW |
2382 | reg = FDI_RX_IMR(pipe); |
2383 | temp = I915_READ(reg); | |
e1a44743 AJ |
2384 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2385 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2386 | I915_WRITE(reg, temp); |
2387 | I915_READ(reg); | |
e1a44743 AJ |
2388 | udelay(150); |
2389 | ||
8db9d77b | 2390 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2391 | reg = FDI_TX_CTL(pipe); |
2392 | temp = I915_READ(reg); | |
77ffb597 AJ |
2393 | temp &= ~(7 << 19); |
2394 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2395 | temp &= ~FDI_LINK_TRAIN_NONE; |
2396 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2397 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2398 | |
5eddb70b CW |
2399 | reg = FDI_RX_CTL(pipe); |
2400 | temp = I915_READ(reg); | |
8db9d77b ZW |
2401 | temp &= ~FDI_LINK_TRAIN_NONE; |
2402 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2403 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2404 | ||
2405 | POSTING_READ(reg); | |
8db9d77b ZW |
2406 | udelay(150); |
2407 | ||
5b2adf89 | 2408 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2409 | if (HAS_PCH_IBX(dev)) { |
2410 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2411 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2412 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2413 | } | |
5b2adf89 | 2414 | |
5eddb70b | 2415 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2416 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2417 | temp = I915_READ(reg); |
8db9d77b ZW |
2418 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2419 | ||
2420 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2421 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2422 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2423 | break; |
2424 | } | |
8db9d77b | 2425 | } |
e1a44743 | 2426 | if (tries == 5) |
5eddb70b | 2427 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2428 | |
2429 | /* Train 2 */ | |
5eddb70b CW |
2430 | reg = FDI_TX_CTL(pipe); |
2431 | temp = I915_READ(reg); | |
8db9d77b ZW |
2432 | temp &= ~FDI_LINK_TRAIN_NONE; |
2433 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2434 | I915_WRITE(reg, temp); |
8db9d77b | 2435 | |
5eddb70b CW |
2436 | reg = FDI_RX_CTL(pipe); |
2437 | temp = I915_READ(reg); | |
8db9d77b ZW |
2438 | temp &= ~FDI_LINK_TRAIN_NONE; |
2439 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2440 | I915_WRITE(reg, temp); |
8db9d77b | 2441 | |
5eddb70b CW |
2442 | POSTING_READ(reg); |
2443 | udelay(150); | |
8db9d77b | 2444 | |
5eddb70b | 2445 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2446 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2447 | temp = I915_READ(reg); |
8db9d77b ZW |
2448 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2449 | ||
2450 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2451 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2452 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2453 | break; | |
2454 | } | |
8db9d77b | 2455 | } |
e1a44743 | 2456 | if (tries == 5) |
5eddb70b | 2457 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2458 | |
2459 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2460 | |
8db9d77b ZW |
2461 | } |
2462 | ||
0206e353 | 2463 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2464 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2465 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2466 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2467 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2468 | }; | |
2469 | ||
2470 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2471 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2472 | { | |
2473 | struct drm_device *dev = crtc->dev; | |
2474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2476 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2477 | u32 reg, temp, i, retry; |
8db9d77b | 2478 | |
e1a44743 AJ |
2479 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2480 | for train result */ | |
5eddb70b CW |
2481 | reg = FDI_RX_IMR(pipe); |
2482 | temp = I915_READ(reg); | |
e1a44743 AJ |
2483 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2484 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2485 | I915_WRITE(reg, temp); |
2486 | ||
2487 | POSTING_READ(reg); | |
e1a44743 AJ |
2488 | udelay(150); |
2489 | ||
8db9d77b | 2490 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2491 | reg = FDI_TX_CTL(pipe); |
2492 | temp = I915_READ(reg); | |
77ffb597 AJ |
2493 | temp &= ~(7 << 19); |
2494 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2495 | temp &= ~FDI_LINK_TRAIN_NONE; |
2496 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2497 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2498 | /* SNB-B */ | |
2499 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2500 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2501 | |
5eddb70b CW |
2502 | reg = FDI_RX_CTL(pipe); |
2503 | temp = I915_READ(reg); | |
8db9d77b ZW |
2504 | if (HAS_PCH_CPT(dev)) { |
2505 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2506 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2507 | } else { | |
2508 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2509 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2510 | } | |
5eddb70b CW |
2511 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2512 | ||
2513 | POSTING_READ(reg); | |
8db9d77b ZW |
2514 | udelay(150); |
2515 | ||
291427f5 JB |
2516 | if (HAS_PCH_CPT(dev)) |
2517 | cpt_phase_pointer_enable(dev, pipe); | |
2518 | ||
0206e353 | 2519 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2520 | reg = FDI_TX_CTL(pipe); |
2521 | temp = I915_READ(reg); | |
8db9d77b ZW |
2522 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2523 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2524 | I915_WRITE(reg, temp); |
2525 | ||
2526 | POSTING_READ(reg); | |
8db9d77b ZW |
2527 | udelay(500); |
2528 | ||
fa37d39e SP |
2529 | for (retry = 0; retry < 5; retry++) { |
2530 | reg = FDI_RX_IIR(pipe); | |
2531 | temp = I915_READ(reg); | |
2532 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2533 | if (temp & FDI_RX_BIT_LOCK) { | |
2534 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2535 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2536 | break; | |
2537 | } | |
2538 | udelay(50); | |
8db9d77b | 2539 | } |
fa37d39e SP |
2540 | if (retry < 5) |
2541 | break; | |
8db9d77b ZW |
2542 | } |
2543 | if (i == 4) | |
5eddb70b | 2544 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2545 | |
2546 | /* Train 2 */ | |
5eddb70b CW |
2547 | reg = FDI_TX_CTL(pipe); |
2548 | temp = I915_READ(reg); | |
8db9d77b ZW |
2549 | temp &= ~FDI_LINK_TRAIN_NONE; |
2550 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2551 | if (IS_GEN6(dev)) { | |
2552 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2553 | /* SNB-B */ | |
2554 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2555 | } | |
5eddb70b | 2556 | I915_WRITE(reg, temp); |
8db9d77b | 2557 | |
5eddb70b CW |
2558 | reg = FDI_RX_CTL(pipe); |
2559 | temp = I915_READ(reg); | |
8db9d77b ZW |
2560 | if (HAS_PCH_CPT(dev)) { |
2561 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2562 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2563 | } else { | |
2564 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2565 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2566 | } | |
5eddb70b CW |
2567 | I915_WRITE(reg, temp); |
2568 | ||
2569 | POSTING_READ(reg); | |
8db9d77b ZW |
2570 | udelay(150); |
2571 | ||
0206e353 | 2572 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2573 | reg = FDI_TX_CTL(pipe); |
2574 | temp = I915_READ(reg); | |
8db9d77b ZW |
2575 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2576 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2577 | I915_WRITE(reg, temp); |
2578 | ||
2579 | POSTING_READ(reg); | |
8db9d77b ZW |
2580 | udelay(500); |
2581 | ||
fa37d39e SP |
2582 | for (retry = 0; retry < 5; retry++) { |
2583 | reg = FDI_RX_IIR(pipe); | |
2584 | temp = I915_READ(reg); | |
2585 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2586 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2587 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2588 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2589 | break; | |
2590 | } | |
2591 | udelay(50); | |
8db9d77b | 2592 | } |
fa37d39e SP |
2593 | if (retry < 5) |
2594 | break; | |
8db9d77b ZW |
2595 | } |
2596 | if (i == 4) | |
5eddb70b | 2597 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2598 | |
2599 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2600 | } | |
2601 | ||
357555c0 JB |
2602 | /* Manual link training for Ivy Bridge A0 parts */ |
2603 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2604 | { | |
2605 | struct drm_device *dev = crtc->dev; | |
2606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2607 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2608 | int pipe = intel_crtc->pipe; | |
2609 | u32 reg, temp, i; | |
2610 | ||
2611 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2612 | for train result */ | |
2613 | reg = FDI_RX_IMR(pipe); | |
2614 | temp = I915_READ(reg); | |
2615 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2616 | temp &= ~FDI_RX_BIT_LOCK; | |
2617 | I915_WRITE(reg, temp); | |
2618 | ||
2619 | POSTING_READ(reg); | |
2620 | udelay(150); | |
2621 | ||
2622 | /* enable CPU FDI TX and PCH FDI RX */ | |
2623 | reg = FDI_TX_CTL(pipe); | |
2624 | temp = I915_READ(reg); | |
2625 | temp &= ~(7 << 19); | |
2626 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2627 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2628 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2629 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2630 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2631 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2632 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2633 | ||
2634 | reg = FDI_RX_CTL(pipe); | |
2635 | temp = I915_READ(reg); | |
2636 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2637 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2638 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2639 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2640 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2641 | ||
2642 | POSTING_READ(reg); | |
2643 | udelay(150); | |
2644 | ||
291427f5 JB |
2645 | if (HAS_PCH_CPT(dev)) |
2646 | cpt_phase_pointer_enable(dev, pipe); | |
2647 | ||
0206e353 | 2648 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2649 | reg = FDI_TX_CTL(pipe); |
2650 | temp = I915_READ(reg); | |
2651 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2652 | temp |= snb_b_fdi_train_param[i]; | |
2653 | I915_WRITE(reg, temp); | |
2654 | ||
2655 | POSTING_READ(reg); | |
2656 | udelay(500); | |
2657 | ||
2658 | reg = FDI_RX_IIR(pipe); | |
2659 | temp = I915_READ(reg); | |
2660 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2661 | ||
2662 | if (temp & FDI_RX_BIT_LOCK || | |
2663 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2664 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2665 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2666 | break; | |
2667 | } | |
2668 | } | |
2669 | if (i == 4) | |
2670 | DRM_ERROR("FDI train 1 fail!\n"); | |
2671 | ||
2672 | /* Train 2 */ | |
2673 | reg = FDI_TX_CTL(pipe); | |
2674 | temp = I915_READ(reg); | |
2675 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2676 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2677 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2678 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2679 | I915_WRITE(reg, temp); | |
2680 | ||
2681 | reg = FDI_RX_CTL(pipe); | |
2682 | temp = I915_READ(reg); | |
2683 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2684 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2685 | I915_WRITE(reg, temp); | |
2686 | ||
2687 | POSTING_READ(reg); | |
2688 | udelay(150); | |
2689 | ||
0206e353 | 2690 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2691 | reg = FDI_TX_CTL(pipe); |
2692 | temp = I915_READ(reg); | |
2693 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2694 | temp |= snb_b_fdi_train_param[i]; | |
2695 | I915_WRITE(reg, temp); | |
2696 | ||
2697 | POSTING_READ(reg); | |
2698 | udelay(500); | |
2699 | ||
2700 | reg = FDI_RX_IIR(pipe); | |
2701 | temp = I915_READ(reg); | |
2702 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2703 | ||
2704 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2705 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2706 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2707 | break; | |
2708 | } | |
2709 | } | |
2710 | if (i == 4) | |
2711 | DRM_ERROR("FDI train 2 fail!\n"); | |
2712 | ||
2713 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2714 | } | |
2715 | ||
88cefb6c | 2716 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2717 | { |
88cefb6c | 2718 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2719 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2720 | int pipe = intel_crtc->pipe; |
5eddb70b | 2721 | u32 reg, temp; |
79e53945 | 2722 | |
c64e311e | 2723 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2724 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2725 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2726 | |
c98e9dcf | 2727 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2728 | reg = FDI_RX_CTL(pipe); |
2729 | temp = I915_READ(reg); | |
2730 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2731 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2732 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2733 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2734 | ||
2735 | POSTING_READ(reg); | |
c98e9dcf JB |
2736 | udelay(200); |
2737 | ||
2738 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2739 | temp = I915_READ(reg); |
2740 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2741 | ||
2742 | POSTING_READ(reg); | |
c98e9dcf JB |
2743 | udelay(200); |
2744 | ||
bf507ef7 ED |
2745 | /* On Haswell, the PLL configuration for ports and pipes is handled |
2746 | * separately, as part of DDI setup */ | |
2747 | if (!IS_HASWELL(dev)) { | |
2748 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
2749 | reg = FDI_TX_CTL(pipe); | |
2750 | temp = I915_READ(reg); | |
2751 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2752 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2753 | |
bf507ef7 ED |
2754 | POSTING_READ(reg); |
2755 | udelay(100); | |
2756 | } | |
6be4a607 | 2757 | } |
0e23b99d JB |
2758 | } |
2759 | ||
88cefb6c DV |
2760 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2761 | { | |
2762 | struct drm_device *dev = intel_crtc->base.dev; | |
2763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2764 | int pipe = intel_crtc->pipe; | |
2765 | u32 reg, temp; | |
2766 | ||
2767 | /* Switch from PCDclk to Rawclk */ | |
2768 | reg = FDI_RX_CTL(pipe); | |
2769 | temp = I915_READ(reg); | |
2770 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2771 | ||
2772 | /* Disable CPU FDI TX PLL */ | |
2773 | reg = FDI_TX_CTL(pipe); | |
2774 | temp = I915_READ(reg); | |
2775 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2776 | ||
2777 | POSTING_READ(reg); | |
2778 | udelay(100); | |
2779 | ||
2780 | reg = FDI_RX_CTL(pipe); | |
2781 | temp = I915_READ(reg); | |
2782 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2783 | ||
2784 | /* Wait for the clocks to turn off. */ | |
2785 | POSTING_READ(reg); | |
2786 | udelay(100); | |
2787 | } | |
2788 | ||
291427f5 JB |
2789 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2790 | { | |
2791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2792 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2793 | ||
2794 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2795 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2796 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2797 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2798 | POSTING_READ(SOUTH_CHICKEN1); | |
2799 | } | |
0fc932b8 JB |
2800 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2801 | { | |
2802 | struct drm_device *dev = crtc->dev; | |
2803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2804 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2805 | int pipe = intel_crtc->pipe; | |
2806 | u32 reg, temp; | |
2807 | ||
2808 | /* disable CPU FDI tx and PCH FDI rx */ | |
2809 | reg = FDI_TX_CTL(pipe); | |
2810 | temp = I915_READ(reg); | |
2811 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2812 | POSTING_READ(reg); | |
2813 | ||
2814 | reg = FDI_RX_CTL(pipe); | |
2815 | temp = I915_READ(reg); | |
2816 | temp &= ~(0x7 << 16); | |
2817 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2818 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2819 | ||
2820 | POSTING_READ(reg); | |
2821 | udelay(100); | |
2822 | ||
2823 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2824 | if (HAS_PCH_IBX(dev)) { |
2825 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2826 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2827 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2828 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2829 | } else if (HAS_PCH_CPT(dev)) { |
2830 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2831 | } |
0fc932b8 JB |
2832 | |
2833 | /* still set train pattern 1 */ | |
2834 | reg = FDI_TX_CTL(pipe); | |
2835 | temp = I915_READ(reg); | |
2836 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2837 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2838 | I915_WRITE(reg, temp); | |
2839 | ||
2840 | reg = FDI_RX_CTL(pipe); | |
2841 | temp = I915_READ(reg); | |
2842 | if (HAS_PCH_CPT(dev)) { | |
2843 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2844 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2845 | } else { | |
2846 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2847 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2848 | } | |
2849 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2850 | temp &= ~(0x07 << 16); | |
2851 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2852 | I915_WRITE(reg, temp); | |
2853 | ||
2854 | POSTING_READ(reg); | |
2855 | udelay(100); | |
2856 | } | |
2857 | ||
e6c3a2a6 CW |
2858 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2859 | { | |
0f91128d | 2860 | struct drm_device *dev = crtc->dev; |
e6c3a2a6 CW |
2861 | |
2862 | if (crtc->fb == NULL) | |
2863 | return; | |
2864 | ||
0f91128d CW |
2865 | mutex_lock(&dev->struct_mutex); |
2866 | intel_finish_fb(crtc->fb); | |
2867 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2868 | } |
2869 | ||
040484af JB |
2870 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2871 | { | |
2872 | struct drm_device *dev = crtc->dev; | |
228d3e36 | 2873 | struct intel_encoder *intel_encoder; |
040484af JB |
2874 | |
2875 | /* | |
2876 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2877 | * must be driven by its own crtc; no sharing is possible. | |
2878 | */ | |
228d3e36 | 2879 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
040484af | 2880 | |
6ee8bab0 ED |
2881 | /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell |
2882 | * CPU handles all others */ | |
2883 | if (IS_HASWELL(dev)) { | |
2884 | /* It is still unclear how this will work on PPT, so throw up a warning */ | |
2885 | WARN_ON(!HAS_PCH_LPT(dev)); | |
2886 | ||
228d3e36 | 2887 | if (intel_encoder->type == INTEL_OUTPUT_ANALOG) { |
6ee8bab0 ED |
2888 | DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n"); |
2889 | return true; | |
2890 | } else { | |
2891 | DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n", | |
228d3e36 | 2892 | intel_encoder->type); |
6ee8bab0 ED |
2893 | return false; |
2894 | } | |
2895 | } | |
2896 | ||
228d3e36 | 2897 | switch (intel_encoder->type) { |
040484af | 2898 | case INTEL_OUTPUT_EDP: |
228d3e36 | 2899 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
040484af JB |
2900 | return false; |
2901 | continue; | |
2902 | } | |
2903 | } | |
2904 | ||
2905 | return true; | |
2906 | } | |
2907 | ||
e615efe4 ED |
2908 | /* Program iCLKIP clock to the desired frequency */ |
2909 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2910 | { | |
2911 | struct drm_device *dev = crtc->dev; | |
2912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2913 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
2914 | u32 temp; | |
2915 | ||
2916 | /* It is necessary to ungate the pixclk gate prior to programming | |
2917 | * the divisors, and gate it back when it is done. | |
2918 | */ | |
2919 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2920 | ||
2921 | /* Disable SSCCTL */ | |
2922 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
2923 | intel_sbi_read(dev_priv, SBI_SSCCTL6) | | |
2924 | SBI_SSCCTL_DISABLE); | |
2925 | ||
2926 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
2927 | if (crtc->mode.clock == 20000) { | |
2928 | auxdiv = 1; | |
2929 | divsel = 0x41; | |
2930 | phaseinc = 0x20; | |
2931 | } else { | |
2932 | /* The iCLK virtual clock root frequency is in MHz, | |
2933 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
2934 | * it is necessary to divide one by another, so we | |
2935 | * convert the virtual clock precision to KHz here for higher | |
2936 | * precision. | |
2937 | */ | |
2938 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2939 | u32 iclk_pi_range = 64; | |
2940 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2941 | ||
2942 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
2943 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
2944 | pi_value = desired_divisor % iclk_pi_range; | |
2945 | ||
2946 | auxdiv = 0; | |
2947 | divsel = msb_divisor_value - 2; | |
2948 | phaseinc = pi_value; | |
2949 | } | |
2950 | ||
2951 | /* This should not happen with any sane values */ | |
2952 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2953 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2954 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2955 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2956 | ||
2957 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
2958 | crtc->mode.clock, | |
2959 | auxdiv, | |
2960 | divsel, | |
2961 | phasedir, | |
2962 | phaseinc); | |
2963 | ||
2964 | /* Program SSCDIVINTPHASE6 */ | |
2965 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6); | |
2966 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; | |
2967 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2968 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2969 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2970 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
2971 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
2972 | ||
2973 | intel_sbi_write(dev_priv, | |
2974 | SBI_SSCDIVINTPHASE6, | |
2975 | temp); | |
2976 | ||
2977 | /* Program SSCAUXDIV */ | |
2978 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6); | |
2979 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); | |
2980 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
2981 | intel_sbi_write(dev_priv, | |
2982 | SBI_SSCAUXDIV6, | |
2983 | temp); | |
2984 | ||
2985 | ||
2986 | /* Enable modulator and associated divider */ | |
2987 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6); | |
2988 | temp &= ~SBI_SSCCTL_DISABLE; | |
2989 | intel_sbi_write(dev_priv, | |
2990 | SBI_SSCCTL6, | |
2991 | temp); | |
2992 | ||
2993 | /* Wait for initialization time */ | |
2994 | udelay(24); | |
2995 | ||
2996 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
2997 | } | |
2998 | ||
f67a559d JB |
2999 | /* |
3000 | * Enable PCH resources required for PCH ports: | |
3001 | * - PCH PLLs | |
3002 | * - FDI training & RX/TX | |
3003 | * - update transcoder timings | |
3004 | * - DP transcoding bits | |
3005 | * - transcoder | |
3006 | */ | |
3007 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3008 | { |
3009 | struct drm_device *dev = crtc->dev; | |
3010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3012 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3013 | u32 reg, temp; |
2c07245f | 3014 | |
e7e164db CW |
3015 | assert_transcoder_disabled(dev_priv, pipe); |
3016 | ||
c98e9dcf | 3017 | /* For PCH output, training FDI link */ |
674cf967 | 3018 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3019 | |
6f13b7b5 CW |
3020 | intel_enable_pch_pll(intel_crtc); |
3021 | ||
e615efe4 ED |
3022 | if (HAS_PCH_LPT(dev)) { |
3023 | DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); | |
3024 | lpt_program_iclkip(crtc); | |
3025 | } else if (HAS_PCH_CPT(dev)) { | |
ee7b9f93 | 3026 | u32 sel; |
4b645f14 | 3027 | |
c98e9dcf | 3028 | temp = I915_READ(PCH_DPLL_SEL); |
ee7b9f93 JB |
3029 | switch (pipe) { |
3030 | default: | |
3031 | case 0: | |
3032 | temp |= TRANSA_DPLL_ENABLE; | |
3033 | sel = TRANSA_DPLLB_SEL; | |
3034 | break; | |
3035 | case 1: | |
3036 | temp |= TRANSB_DPLL_ENABLE; | |
3037 | sel = TRANSB_DPLLB_SEL; | |
3038 | break; | |
3039 | case 2: | |
3040 | temp |= TRANSC_DPLL_ENABLE; | |
3041 | sel = TRANSC_DPLLB_SEL; | |
3042 | break; | |
d64311ab | 3043 | } |
ee7b9f93 JB |
3044 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3045 | temp |= sel; | |
3046 | else | |
3047 | temp &= ~sel; | |
c98e9dcf | 3048 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3049 | } |
5eddb70b | 3050 | |
d9b6cb56 JB |
3051 | /* set transcoder timing, panel must allow it */ |
3052 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3053 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3054 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3055 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3056 | |
5eddb70b CW |
3057 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3058 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3059 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3060 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3061 | |
f57e1e3a ED |
3062 | if (!IS_HASWELL(dev)) |
3063 | intel_fdi_normal_train(crtc); | |
5e84e1a4 | 3064 | |
c98e9dcf JB |
3065 | /* For PCH DP, enable TRANS_DP_CTL */ |
3066 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3067 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3068 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 3069 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
3070 | reg = TRANS_DP_CTL(pipe); |
3071 | temp = I915_READ(reg); | |
3072 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3073 | TRANS_DP_SYNC_MASK | |
3074 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3075 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3076 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3077 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3078 | |
3079 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3080 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3081 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3082 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3083 | |
3084 | switch (intel_trans_dp_port_sel(crtc)) { | |
3085 | case PCH_DP_B: | |
5eddb70b | 3086 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3087 | break; |
3088 | case PCH_DP_C: | |
5eddb70b | 3089 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3090 | break; |
3091 | case PCH_DP_D: | |
5eddb70b | 3092 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3093 | break; |
3094 | default: | |
3095 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 3096 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 3097 | break; |
32f9d658 | 3098 | } |
2c07245f | 3099 | |
5eddb70b | 3100 | I915_WRITE(reg, temp); |
6be4a607 | 3101 | } |
b52eb4dc | 3102 | |
040484af | 3103 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
3104 | } |
3105 | ||
ee7b9f93 JB |
3106 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3107 | { | |
3108 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
3109 | ||
3110 | if (pll == NULL) | |
3111 | return; | |
3112 | ||
3113 | if (pll->refcount == 0) { | |
3114 | WARN(1, "bad PCH PLL refcount\n"); | |
3115 | return; | |
3116 | } | |
3117 | ||
3118 | --pll->refcount; | |
3119 | intel_crtc->pch_pll = NULL; | |
3120 | } | |
3121 | ||
3122 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) | |
3123 | { | |
3124 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3125 | struct intel_pch_pll *pll; | |
3126 | int i; | |
3127 | ||
3128 | pll = intel_crtc->pch_pll; | |
3129 | if (pll) { | |
3130 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", | |
3131 | intel_crtc->base.base.id, pll->pll_reg); | |
3132 | goto prepare; | |
3133 | } | |
3134 | ||
98b6bd99 DV |
3135 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3136 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
3137 | i = intel_crtc->pipe; | |
3138 | pll = &dev_priv->pch_plls[i]; | |
3139 | ||
3140 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", | |
3141 | intel_crtc->base.base.id, pll->pll_reg); | |
3142 | ||
3143 | goto found; | |
3144 | } | |
3145 | ||
ee7b9f93 JB |
3146 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3147 | pll = &dev_priv->pch_plls[i]; | |
3148 | ||
3149 | /* Only want to check enabled timings first */ | |
3150 | if (pll->refcount == 0) | |
3151 | continue; | |
3152 | ||
3153 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && | |
3154 | fp == I915_READ(pll->fp0_reg)) { | |
3155 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", | |
3156 | intel_crtc->base.base.id, | |
3157 | pll->pll_reg, pll->refcount, pll->active); | |
3158 | ||
3159 | goto found; | |
3160 | } | |
3161 | } | |
3162 | ||
3163 | /* Ok no matching timings, maybe there's a free one? */ | |
3164 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
3165 | pll = &dev_priv->pch_plls[i]; | |
3166 | if (pll->refcount == 0) { | |
3167 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", | |
3168 | intel_crtc->base.base.id, pll->pll_reg); | |
3169 | goto found; | |
3170 | } | |
3171 | } | |
3172 | ||
3173 | return NULL; | |
3174 | ||
3175 | found: | |
3176 | intel_crtc->pch_pll = pll; | |
3177 | pll->refcount++; | |
3178 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); | |
3179 | prepare: /* separate function? */ | |
3180 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); | |
ee7b9f93 | 3181 | |
e04c7350 CW |
3182 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3183 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3184 | POSTING_READ(pll->pll_reg); |
3185 | udelay(150); | |
e04c7350 CW |
3186 | |
3187 | I915_WRITE(pll->fp0_reg, fp); | |
3188 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3189 | pll->on = false; |
3190 | return pll; | |
3191 | } | |
3192 | ||
d4270e57 JB |
3193 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3194 | { | |
3195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3196 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); | |
3197 | u32 temp; | |
3198 | ||
3199 | temp = I915_READ(dslreg); | |
3200 | udelay(500); | |
3201 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
3202 | /* Without this, mode sets may fail silently on FDI */ | |
3203 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
3204 | udelay(250); | |
3205 | I915_WRITE(tc2reg, 0); | |
3206 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
3207 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3208 | } | |
3209 | } | |
3210 | ||
f67a559d JB |
3211 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3212 | { | |
3213 | struct drm_device *dev = crtc->dev; | |
3214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3215 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3216 | struct intel_encoder *encoder; |
f67a559d JB |
3217 | int pipe = intel_crtc->pipe; |
3218 | int plane = intel_crtc->plane; | |
3219 | u32 temp; | |
3220 | bool is_pch_port; | |
3221 | ||
08a48469 DV |
3222 | WARN_ON(!crtc->enabled); |
3223 | ||
f67a559d | 3224 | if (intel_crtc->active) |
ea9d758d | 3225 | return; |
f67a559d JB |
3226 | |
3227 | intel_crtc->active = true; | |
3228 | intel_update_watermarks(dev); | |
3229 | ||
3230 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3231 | temp = I915_READ(PCH_LVDS); | |
3232 | if ((temp & LVDS_PORT_EN) == 0) | |
3233 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3234 | } | |
3235 | ||
3236 | is_pch_port = intel_crtc_driving_pch(crtc); | |
3237 | ||
3238 | if (is_pch_port) | |
88cefb6c | 3239 | ironlake_fdi_pll_enable(intel_crtc); |
f67a559d JB |
3240 | else |
3241 | ironlake_fdi_disable(crtc); | |
3242 | ||
3243 | /* Enable panel fitting for LVDS */ | |
3244 | if (dev_priv->pch_pf_size && | |
3245 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
3246 | /* Force use of hard-coded filter coefficients | |
3247 | * as some pre-programmed values are broken, | |
3248 | * e.g. x201. | |
3249 | */ | |
9db4a9c7 JB |
3250 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3251 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
3252 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3253 | } |
3254 | ||
9c54c0dd JB |
3255 | /* |
3256 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3257 | * clocks enabled | |
3258 | */ | |
3259 | intel_crtc_load_lut(crtc); | |
3260 | ||
f67a559d JB |
3261 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3262 | intel_enable_plane(dev_priv, plane, pipe); | |
3263 | ||
3264 | if (is_pch_port) | |
3265 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3266 | |
d1ebd816 | 3267 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3268 | intel_update_fbc(dev); |
d1ebd816 BW |
3269 | mutex_unlock(&dev->struct_mutex); |
3270 | ||
6b383a7f | 3271 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3272 | |
fa5c73b1 DV |
3273 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3274 | encoder->enable(encoder); | |
61b77ddd DV |
3275 | |
3276 | if (HAS_PCH_CPT(dev)) | |
3277 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
6be4a607 JB |
3278 | } |
3279 | ||
3280 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3281 | { | |
3282 | struct drm_device *dev = crtc->dev; | |
3283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3285 | struct intel_encoder *encoder; |
6be4a607 JB |
3286 | int pipe = intel_crtc->pipe; |
3287 | int plane = intel_crtc->plane; | |
5eddb70b | 3288 | u32 reg, temp; |
b52eb4dc | 3289 | |
ef9c3aee | 3290 | |
f7abfe8b CW |
3291 | if (!intel_crtc->active) |
3292 | return; | |
3293 | ||
ea9d758d DV |
3294 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3295 | encoder->disable(encoder); | |
3296 | ||
e6c3a2a6 | 3297 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3298 | drm_vblank_off(dev, pipe); |
6b383a7f | 3299 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3300 | |
b24e7179 | 3301 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3302 | |
973d04f9 CW |
3303 | if (dev_priv->cfb_plane == plane) |
3304 | intel_disable_fbc(dev); | |
2c07245f | 3305 | |
b24e7179 | 3306 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3307 | |
6be4a607 | 3308 | /* Disable PF */ |
9db4a9c7 JB |
3309 | I915_WRITE(PF_CTL(pipe), 0); |
3310 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3311 | |
0fc932b8 | 3312 | ironlake_fdi_disable(crtc); |
2c07245f | 3313 | |
47a05eca JB |
3314 | /* This is a horrible layering violation; we should be doing this in |
3315 | * the connector/encoder ->prepare instead, but we don't always have | |
3316 | * enough information there about the config to know whether it will | |
3317 | * actually be necessary or just cause undesired flicker. | |
3318 | */ | |
3319 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3320 | |
040484af | 3321 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3322 | |
6be4a607 JB |
3323 | if (HAS_PCH_CPT(dev)) { |
3324 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3325 | reg = TRANS_DP_CTL(pipe); |
3326 | temp = I915_READ(reg); | |
3327 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3328 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3329 | I915_WRITE(reg, temp); |
6be4a607 JB |
3330 | |
3331 | /* disable DPLL_SEL */ | |
3332 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3333 | switch (pipe) { |
3334 | case 0: | |
d64311ab | 3335 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3336 | break; |
3337 | case 1: | |
6be4a607 | 3338 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3339 | break; |
3340 | case 2: | |
4b645f14 | 3341 | /* C shares PLL A or B */ |
d64311ab | 3342 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3343 | break; |
3344 | default: | |
3345 | BUG(); /* wtf */ | |
3346 | } | |
6be4a607 | 3347 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3348 | } |
e3421a18 | 3349 | |
6be4a607 | 3350 | /* disable PCH DPLL */ |
ee7b9f93 | 3351 | intel_disable_pch_pll(intel_crtc); |
8db9d77b | 3352 | |
88cefb6c | 3353 | ironlake_fdi_pll_disable(intel_crtc); |
6b383a7f | 3354 | |
f7abfe8b | 3355 | intel_crtc->active = false; |
6b383a7f | 3356 | intel_update_watermarks(dev); |
d1ebd816 BW |
3357 | |
3358 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3359 | intel_update_fbc(dev); |
d1ebd816 | 3360 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3361 | } |
1b3c7a47 | 3362 | |
ee7b9f93 JB |
3363 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3364 | { | |
3365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3366 | intel_put_pch_pll(intel_crtc); | |
3367 | } | |
3368 | ||
02e792fb DV |
3369 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3370 | { | |
02e792fb | 3371 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3372 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3373 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3374 | |
23f09ce3 | 3375 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3376 | dev_priv->mm.interruptible = false; |
3377 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3378 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3379 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3380 | } |
02e792fb | 3381 | |
5dcdbcb0 CW |
3382 | /* Let userspace switch the overlay on again. In most cases userspace |
3383 | * has to recompute where to put it anyway. | |
3384 | */ | |
02e792fb DV |
3385 | } |
3386 | ||
0b8765c6 | 3387 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3388 | { |
3389 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3390 | struct drm_i915_private *dev_priv = dev->dev_private; |
3391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3392 | struct intel_encoder *encoder; |
79e53945 | 3393 | int pipe = intel_crtc->pipe; |
80824003 | 3394 | int plane = intel_crtc->plane; |
79e53945 | 3395 | |
08a48469 DV |
3396 | WARN_ON(!crtc->enabled); |
3397 | ||
f7abfe8b | 3398 | if (intel_crtc->active) |
ea9d758d | 3399 | return; |
f7abfe8b CW |
3400 | |
3401 | intel_crtc->active = true; | |
6b383a7f CW |
3402 | intel_update_watermarks(dev); |
3403 | ||
63d7bbe9 | 3404 | intel_enable_pll(dev_priv, pipe); |
040484af | 3405 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3406 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3407 | |
0b8765c6 | 3408 | intel_crtc_load_lut(crtc); |
bed4a673 | 3409 | intel_update_fbc(dev); |
79e53945 | 3410 | |
0b8765c6 JB |
3411 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3412 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3413 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3414 | |
fa5c73b1 DV |
3415 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3416 | encoder->enable(encoder); | |
0b8765c6 | 3417 | } |
79e53945 | 3418 | |
0b8765c6 JB |
3419 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3420 | { | |
3421 | struct drm_device *dev = crtc->dev; | |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3424 | struct intel_encoder *encoder; |
0b8765c6 JB |
3425 | int pipe = intel_crtc->pipe; |
3426 | int plane = intel_crtc->plane; | |
b690e96c | 3427 | |
ef9c3aee | 3428 | |
f7abfe8b CW |
3429 | if (!intel_crtc->active) |
3430 | return; | |
3431 | ||
ea9d758d DV |
3432 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3433 | encoder->disable(encoder); | |
3434 | ||
0b8765c6 | 3435 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3436 | intel_crtc_wait_for_pending_flips(crtc); |
3437 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3438 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3439 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3440 | |
973d04f9 CW |
3441 | if (dev_priv->cfb_plane == plane) |
3442 | intel_disable_fbc(dev); | |
79e53945 | 3443 | |
b24e7179 | 3444 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3445 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3446 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3447 | |
f7abfe8b | 3448 | intel_crtc->active = false; |
6b383a7f CW |
3449 | intel_update_fbc(dev); |
3450 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3451 | } |
3452 | ||
ee7b9f93 JB |
3453 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3454 | { | |
3455 | } | |
3456 | ||
976f8a20 DV |
3457 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3458 | bool enabled) | |
2c07245f ZW |
3459 | { |
3460 | struct drm_device *dev = crtc->dev; | |
3461 | struct drm_i915_master_private *master_priv; | |
3462 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3463 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3464 | |
3465 | if (!dev->primary->master) | |
3466 | return; | |
3467 | ||
3468 | master_priv = dev->primary->master->driver_priv; | |
3469 | if (!master_priv->sarea_priv) | |
3470 | return; | |
3471 | ||
79e53945 JB |
3472 | switch (pipe) { |
3473 | case 0: | |
3474 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3475 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3476 | break; | |
3477 | case 1: | |
3478 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3479 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3480 | break; | |
3481 | default: | |
9db4a9c7 | 3482 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3483 | break; |
3484 | } | |
79e53945 JB |
3485 | } |
3486 | ||
976f8a20 DV |
3487 | /** |
3488 | * Sets the power management mode of the pipe and plane. | |
3489 | */ | |
3490 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3491 | { | |
3492 | struct drm_device *dev = crtc->dev; | |
3493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3494 | struct intel_encoder *intel_encoder; | |
3495 | bool enable = false; | |
3496 | ||
3497 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3498 | enable |= intel_encoder->connectors_active; | |
3499 | ||
3500 | if (enable) | |
3501 | dev_priv->display.crtc_enable(crtc); | |
3502 | else | |
3503 | dev_priv->display.crtc_disable(crtc); | |
3504 | ||
3505 | intel_crtc_update_sarea(crtc, enable); | |
3506 | } | |
3507 | ||
3508 | static void intel_crtc_noop(struct drm_crtc *crtc) | |
3509 | { | |
3510 | } | |
3511 | ||
cdd59983 CW |
3512 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3513 | { | |
cdd59983 | 3514 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3515 | struct drm_connector *connector; |
ee7b9f93 | 3516 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 3517 | |
976f8a20 DV |
3518 | /* crtc should still be enabled when we disable it. */ |
3519 | WARN_ON(!crtc->enabled); | |
3520 | ||
3521 | dev_priv->display.crtc_disable(crtc); | |
3522 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
3523 | dev_priv->display.off(crtc); |
3524 | ||
931872fc CW |
3525 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3526 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3527 | |
3528 | if (crtc->fb) { | |
3529 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3530 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3531 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3532 | crtc->fb = NULL; |
3533 | } | |
3534 | ||
3535 | /* Update computed state. */ | |
3536 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3537 | if (!connector->encoder || !connector->encoder->crtc) | |
3538 | continue; | |
3539 | ||
3540 | if (connector->encoder->crtc != crtc) | |
3541 | continue; | |
3542 | ||
3543 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3544 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3545 | } |
3546 | } | |
3547 | ||
1f703855 | 3548 | void intel_encoder_noop(struct drm_encoder *encoder) |
5ab432ef | 3549 | { |
5ab432ef DV |
3550 | } |
3551 | ||
ea5b213a CW |
3552 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3553 | { | |
4ef69c7a | 3554 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3555 | |
ea5b213a CW |
3556 | drm_encoder_cleanup(encoder); |
3557 | kfree(intel_encoder); | |
3558 | } | |
3559 | ||
5ab432ef DV |
3560 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3561 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the | |
3562 | * state of the entire output pipe. */ | |
3563 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) | |
3564 | { | |
3565 | if (mode == DRM_MODE_DPMS_ON) { | |
3566 | encoder->connectors_active = true; | |
3567 | ||
b2cabb0e | 3568 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3569 | } else { |
3570 | encoder->connectors_active = false; | |
3571 | ||
b2cabb0e | 3572 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3573 | } |
3574 | } | |
3575 | ||
0a91ca29 DV |
3576 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3577 | * internal consistency). */ | |
3578 | void intel_connector_check_state(struct intel_connector *connector) | |
3579 | { | |
3580 | if (connector->get_hw_state(connector)) { | |
3581 | struct intel_encoder *encoder = connector->encoder; | |
3582 | struct drm_crtc *crtc; | |
3583 | bool encoder_enabled; | |
3584 | enum pipe pipe; | |
3585 | ||
3586 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3587 | connector->base.base.id, | |
3588 | drm_get_connector_name(&connector->base)); | |
3589 | ||
3590 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3591 | "wrong connector dpms state\n"); | |
3592 | WARN(connector->base.encoder != &encoder->base, | |
3593 | "active connector not linked to encoder\n"); | |
3594 | WARN(!encoder->connectors_active, | |
3595 | "encoder->connectors_active not set\n"); | |
3596 | ||
3597 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3598 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3599 | if (WARN_ON(!encoder->base.crtc)) | |
3600 | return; | |
3601 | ||
3602 | crtc = encoder->base.crtc; | |
3603 | ||
3604 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3605 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3606 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3607 | "encoder active on the wrong pipe\n"); | |
3608 | } | |
3609 | } | |
3610 | ||
5ab432ef DV |
3611 | /* Even simpler default implementation, if there's really no special case to |
3612 | * consider. */ | |
3613 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
3614 | { | |
3615 | struct intel_encoder *encoder = intel_attached_encoder(connector); | |
3616 | ||
3617 | /* All the simple cases only support two dpms states. */ | |
3618 | if (mode != DRM_MODE_DPMS_ON) | |
3619 | mode = DRM_MODE_DPMS_OFF; | |
3620 | ||
3621 | if (mode == connector->dpms) | |
3622 | return; | |
3623 | ||
3624 | connector->dpms = mode; | |
3625 | ||
3626 | /* Only need to change hw state when actually enabled */ | |
3627 | if (encoder->base.crtc) | |
3628 | intel_encoder_dpms(encoder, mode); | |
3629 | else | |
3630 | encoder->connectors_active = false; | |
0a91ca29 DV |
3631 | |
3632 | intel_connector_check_state(to_intel_connector(connector)); | |
5ab432ef DV |
3633 | } |
3634 | ||
f0947c37 DV |
3635 | /* Simple connector->get_hw_state implementation for encoders that support only |
3636 | * one connector and no cloning and hence the encoder state determines the state | |
3637 | * of the connector. */ | |
3638 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
3639 | { | |
24929352 | 3640 | enum pipe pipe = 0; |
f0947c37 DV |
3641 | struct intel_encoder *encoder = connector->encoder; |
3642 | ||
3643 | return encoder->get_hw_state(encoder, &pipe); | |
3644 | } | |
3645 | ||
79e53945 | 3646 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
35313cde | 3647 | const struct drm_display_mode *mode, |
79e53945 JB |
3648 | struct drm_display_mode *adjusted_mode) |
3649 | { | |
2c07245f | 3650 | struct drm_device *dev = crtc->dev; |
89749350 | 3651 | |
bad720ff | 3652 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3653 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3654 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3655 | return false; | |
2c07245f | 3656 | } |
89749350 | 3657 | |
f9bef081 DV |
3658 | /* All interlaced capable intel hw wants timings in frames. Note though |
3659 | * that intel_lvds_mode_fixup does some funny tricks with the crtc | |
3660 | * timings, so we need to be careful not to clobber these.*/ | |
3661 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) | |
3662 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3663 | |
79e53945 JB |
3664 | return true; |
3665 | } | |
3666 | ||
25eb05fc JB |
3667 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3668 | { | |
3669 | return 400000; /* FIXME */ | |
3670 | } | |
3671 | ||
e70236a8 JB |
3672 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3673 | { | |
3674 | return 400000; | |
3675 | } | |
79e53945 | 3676 | |
e70236a8 | 3677 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3678 | { |
e70236a8 JB |
3679 | return 333000; |
3680 | } | |
79e53945 | 3681 | |
e70236a8 JB |
3682 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3683 | { | |
3684 | return 200000; | |
3685 | } | |
79e53945 | 3686 | |
e70236a8 JB |
3687 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3688 | { | |
3689 | u16 gcfgc = 0; | |
79e53945 | 3690 | |
e70236a8 JB |
3691 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3692 | ||
3693 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3694 | return 133000; | |
3695 | else { | |
3696 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3697 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3698 | return 333000; | |
3699 | default: | |
3700 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3701 | return 190000; | |
79e53945 | 3702 | } |
e70236a8 JB |
3703 | } |
3704 | } | |
3705 | ||
3706 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3707 | { | |
3708 | return 266000; | |
3709 | } | |
3710 | ||
3711 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3712 | { | |
3713 | u16 hpllcc = 0; | |
3714 | /* Assume that the hardware is in the high speed state. This | |
3715 | * should be the default. | |
3716 | */ | |
3717 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3718 | case GC_CLOCK_133_200: | |
3719 | case GC_CLOCK_100_200: | |
3720 | return 200000; | |
3721 | case GC_CLOCK_166_250: | |
3722 | return 250000; | |
3723 | case GC_CLOCK_100_133: | |
79e53945 | 3724 | return 133000; |
e70236a8 | 3725 | } |
79e53945 | 3726 | |
e70236a8 JB |
3727 | /* Shouldn't happen */ |
3728 | return 0; | |
3729 | } | |
79e53945 | 3730 | |
e70236a8 JB |
3731 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3732 | { | |
3733 | return 133000; | |
79e53945 JB |
3734 | } |
3735 | ||
2c07245f ZW |
3736 | struct fdi_m_n { |
3737 | u32 tu; | |
3738 | u32 gmch_m; | |
3739 | u32 gmch_n; | |
3740 | u32 link_m; | |
3741 | u32 link_n; | |
3742 | }; | |
3743 | ||
3744 | static void | |
3745 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3746 | { | |
3747 | while (*num > 0xffffff || *den > 0xffffff) { | |
3748 | *num >>= 1; | |
3749 | *den >>= 1; | |
3750 | } | |
3751 | } | |
3752 | ||
2c07245f | 3753 | static void |
f2b115e6 AJ |
3754 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3755 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3756 | { |
2c07245f ZW |
3757 | m_n->tu = 64; /* default size */ |
3758 | ||
22ed1113 CW |
3759 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3760 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3761 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3762 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3763 | ||
22ed1113 CW |
3764 | m_n->link_m = pixel_clock; |
3765 | m_n->link_n = link_clock; | |
2c07245f ZW |
3766 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3767 | } | |
3768 | ||
a7615030 CW |
3769 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3770 | { | |
72bbe58c KP |
3771 | if (i915_panel_use_ssc >= 0) |
3772 | return i915_panel_use_ssc != 0; | |
3773 | return dev_priv->lvds_use_ssc | |
435793df | 3774 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
3775 | } |
3776 | ||
5a354204 JB |
3777 | /** |
3778 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
3779 | * @crtc: CRTC structure | |
3b5c78a3 | 3780 | * @mode: requested mode |
5a354204 JB |
3781 | * |
3782 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
3783 | * attached framebuffer, choose a good color depth to use on the pipe. | |
3784 | * | |
3785 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
3786 | * isn't ideal, because the connected output supports a lesser or restricted | |
3787 | * set of depths. Resolve that here: | |
3788 | * LVDS typically supports only 6bpc, so clamp down in that case | |
3789 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
3790 | * Displays may support a restricted set as well, check EDID and clamp as | |
3791 | * appropriate. | |
3b5c78a3 | 3792 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
3793 | * |
3794 | * RETURNS: | |
3795 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
3796 | * true if they don't match). | |
3797 | */ | |
3798 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
94352cf9 | 3799 | struct drm_framebuffer *fb, |
3b5c78a3 AJ |
3800 | unsigned int *pipe_bpp, |
3801 | struct drm_display_mode *mode) | |
5a354204 JB |
3802 | { |
3803 | struct drm_device *dev = crtc->dev; | |
3804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5a354204 | 3805 | struct drm_connector *connector; |
6c2b7c12 | 3806 | struct intel_encoder *intel_encoder; |
5a354204 JB |
3807 | unsigned int display_bpc = UINT_MAX, bpc; |
3808 | ||
3809 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
6c2b7c12 | 3810 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5a354204 JB |
3811 | |
3812 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
3813 | unsigned int lvds_bpc; | |
3814 | ||
3815 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
3816 | LVDS_A3_POWER_UP) | |
3817 | lvds_bpc = 8; | |
3818 | else | |
3819 | lvds_bpc = 6; | |
3820 | ||
3821 | if (lvds_bpc < display_bpc) { | |
82820490 | 3822 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
3823 | display_bpc = lvds_bpc; |
3824 | } | |
3825 | continue; | |
3826 | } | |
3827 | ||
5a354204 JB |
3828 | /* Not one of the known troublemakers, check the EDID */ |
3829 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
3830 | head) { | |
6c2b7c12 | 3831 | if (connector->encoder != &intel_encoder->base) |
5a354204 JB |
3832 | continue; |
3833 | ||
62ac41a6 JB |
3834 | /* Don't use an invalid EDID bpc value */ |
3835 | if (connector->display_info.bpc && | |
3836 | connector->display_info.bpc < display_bpc) { | |
82820490 | 3837 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
3838 | display_bpc = connector->display_info.bpc; |
3839 | } | |
3840 | } | |
3841 | ||
3842 | /* | |
3843 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
3844 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
3845 | */ | |
3846 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
3847 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 3848 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
3849 | display_bpc = 12; |
3850 | } else { | |
82820490 | 3851 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
3852 | display_bpc = 8; |
3853 | } | |
3854 | } | |
3855 | } | |
3856 | ||
3b5c78a3 AJ |
3857 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
3858 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
3859 | display_bpc = 6; | |
3860 | } | |
3861 | ||
5a354204 JB |
3862 | /* |
3863 | * We could just drive the pipe at the highest bpc all the time and | |
3864 | * enable dithering as needed, but that costs bandwidth. So choose | |
3865 | * the minimum value that expresses the full color range of the fb but | |
3866 | * also stays within the max display bpc discovered above. | |
3867 | */ | |
3868 | ||
94352cf9 | 3869 | switch (fb->depth) { |
5a354204 JB |
3870 | case 8: |
3871 | bpc = 8; /* since we go through a colormap */ | |
3872 | break; | |
3873 | case 15: | |
3874 | case 16: | |
3875 | bpc = 6; /* min is 18bpp */ | |
3876 | break; | |
3877 | case 24: | |
578393cd | 3878 | bpc = 8; |
5a354204 JB |
3879 | break; |
3880 | case 30: | |
578393cd | 3881 | bpc = 10; |
5a354204 JB |
3882 | break; |
3883 | case 48: | |
578393cd | 3884 | bpc = 12; |
5a354204 JB |
3885 | break; |
3886 | default: | |
3887 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
3888 | bpc = min((unsigned int)8, display_bpc); | |
3889 | break; | |
3890 | } | |
3891 | ||
578393cd KP |
3892 | display_bpc = min(display_bpc, bpc); |
3893 | ||
82820490 AJ |
3894 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
3895 | bpc, display_bpc); | |
5a354204 | 3896 | |
578393cd | 3897 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
3898 | |
3899 | return display_bpc != bpc; | |
3900 | } | |
3901 | ||
a0c4da24 JB |
3902 | static int vlv_get_refclk(struct drm_crtc *crtc) |
3903 | { | |
3904 | struct drm_device *dev = crtc->dev; | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3906 | int refclk = 27000; /* for DP & HDMI */ | |
3907 | ||
3908 | return 100000; /* only one validated so far */ | |
3909 | ||
3910 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
3911 | refclk = 96000; | |
3912 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3913 | if (intel_panel_use_ssc(dev_priv)) | |
3914 | refclk = 100000; | |
3915 | else | |
3916 | refclk = 96000; | |
3917 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
3918 | refclk = 100000; | |
3919 | } | |
3920 | ||
3921 | return refclk; | |
3922 | } | |
3923 | ||
c65d77d8 JB |
3924 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
3925 | { | |
3926 | struct drm_device *dev = crtc->dev; | |
3927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3928 | int refclk; | |
3929 | ||
a0c4da24 JB |
3930 | if (IS_VALLEYVIEW(dev)) { |
3931 | refclk = vlv_get_refclk(crtc); | |
3932 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 JB |
3933 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
3934 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
3935 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
3936 | refclk / 1000); | |
3937 | } else if (!IS_GEN2(dev)) { | |
3938 | refclk = 96000; | |
3939 | } else { | |
3940 | refclk = 48000; | |
3941 | } | |
3942 | ||
3943 | return refclk; | |
3944 | } | |
3945 | ||
3946 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
3947 | intel_clock_t *clock) | |
3948 | { | |
3949 | /* SDVO TV has fixed PLL values depend on its clock range, | |
3950 | this mirrors vbios setting. */ | |
3951 | if (adjusted_mode->clock >= 100000 | |
3952 | && adjusted_mode->clock < 140500) { | |
3953 | clock->p1 = 2; | |
3954 | clock->p2 = 10; | |
3955 | clock->n = 3; | |
3956 | clock->m1 = 16; | |
3957 | clock->m2 = 8; | |
3958 | } else if (adjusted_mode->clock >= 140500 | |
3959 | && adjusted_mode->clock <= 200000) { | |
3960 | clock->p1 = 1; | |
3961 | clock->p2 = 10; | |
3962 | clock->n = 6; | |
3963 | clock->m1 = 12; | |
3964 | clock->m2 = 8; | |
3965 | } | |
3966 | } | |
3967 | ||
a7516a05 JB |
3968 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
3969 | intel_clock_t *clock, | |
3970 | intel_clock_t *reduced_clock) | |
3971 | { | |
3972 | struct drm_device *dev = crtc->dev; | |
3973 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3974 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3975 | int pipe = intel_crtc->pipe; | |
3976 | u32 fp, fp2 = 0; | |
3977 | ||
3978 | if (IS_PINEVIEW(dev)) { | |
3979 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
3980 | if (reduced_clock) | |
3981 | fp2 = (1 << reduced_clock->n) << 16 | | |
3982 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
3983 | } else { | |
3984 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
3985 | if (reduced_clock) | |
3986 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
3987 | reduced_clock->m2; | |
3988 | } | |
3989 | ||
3990 | I915_WRITE(FP0(pipe), fp); | |
3991 | ||
3992 | intel_crtc->lowfreq_avail = false; | |
3993 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
3994 | reduced_clock && i915_powersave) { | |
3995 | I915_WRITE(FP1(pipe), fp2); | |
3996 | intel_crtc->lowfreq_avail = true; | |
3997 | } else { | |
3998 | I915_WRITE(FP1(pipe), fp); | |
3999 | } | |
4000 | } | |
4001 | ||
93e537a1 DV |
4002 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
4003 | struct drm_display_mode *adjusted_mode) | |
4004 | { | |
4005 | struct drm_device *dev = crtc->dev; | |
4006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4008 | int pipe = intel_crtc->pipe; | |
284d5df5 | 4009 | u32 temp; |
93e537a1 DV |
4010 | |
4011 | temp = I915_READ(LVDS); | |
4012 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
4013 | if (pipe == 1) { | |
4014 | temp |= LVDS_PIPEB_SELECT; | |
4015 | } else { | |
4016 | temp &= ~LVDS_PIPEB_SELECT; | |
4017 | } | |
4018 | /* set the corresponsding LVDS_BORDER bit */ | |
4019 | temp |= dev_priv->lvds_border_bits; | |
4020 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
4021 | * set the DPLLs for dual-channel mode or not. | |
4022 | */ | |
4023 | if (clock->p2 == 7) | |
4024 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
4025 | else | |
4026 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
4027 | ||
4028 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4029 | * appropriately here, but we need to look more thoroughly into how | |
4030 | * panels behave in the two modes. | |
4031 | */ | |
4032 | /* set the dithering flag on LVDS as needed */ | |
4033 | if (INTEL_INFO(dev)->gen >= 4) { | |
4034 | if (dev_priv->lvds_dither) | |
4035 | temp |= LVDS_ENABLE_DITHER; | |
4036 | else | |
4037 | temp &= ~LVDS_ENABLE_DITHER; | |
4038 | } | |
284d5df5 | 4039 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
93e537a1 | 4040 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
284d5df5 | 4041 | temp |= LVDS_HSYNC_POLARITY; |
93e537a1 | 4042 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
284d5df5 | 4043 | temp |= LVDS_VSYNC_POLARITY; |
93e537a1 DV |
4044 | I915_WRITE(LVDS, temp); |
4045 | } | |
4046 | ||
a0c4da24 JB |
4047 | static void vlv_update_pll(struct drm_crtc *crtc, |
4048 | struct drm_display_mode *mode, | |
4049 | struct drm_display_mode *adjusted_mode, | |
4050 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
4051 | int refclk, int num_connectors) | |
4052 | { | |
4053 | struct drm_device *dev = crtc->dev; | |
4054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4056 | int pipe = intel_crtc->pipe; | |
4057 | u32 dpll, mdiv, pdiv; | |
4058 | u32 bestn, bestm1, bestm2, bestp1, bestp2; | |
4059 | bool is_hdmi; | |
4060 | ||
4061 | is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
4062 | ||
4063 | bestn = clock->n; | |
4064 | bestm1 = clock->m1; | |
4065 | bestm2 = clock->m2; | |
4066 | bestp1 = clock->p1; | |
4067 | bestp2 = clock->p2; | |
4068 | ||
4069 | /* Enable DPIO clock input */ | |
4070 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4071 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
4072 | I915_WRITE(DPLL(pipe), dpll); | |
4073 | POSTING_READ(DPLL(pipe)); | |
4074 | ||
4075 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); | |
4076 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4077 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
4078 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); | |
4079 | mdiv |= (1 << DPIO_K_SHIFT); | |
4080 | mdiv |= DPIO_ENABLE_CALIBRATION; | |
4081 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); | |
4082 | ||
4083 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); | |
4084 | ||
4085 | pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | | |
4086 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | | |
4087 | (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); | |
4088 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); | |
4089 | ||
4090 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); | |
4091 | ||
4092 | dpll |= DPLL_VCO_ENABLE; | |
4093 | I915_WRITE(DPLL(pipe), dpll); | |
4094 | POSTING_READ(DPLL(pipe)); | |
4095 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
4096 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
4097 | ||
4098 | if (is_hdmi) { | |
4099 | u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4100 | ||
4101 | if (temp > 1) | |
4102 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4103 | else | |
4104 | temp = 0; | |
4105 | ||
4106 | I915_WRITE(DPLL_MD(pipe), temp); | |
4107 | POSTING_READ(DPLL_MD(pipe)); | |
4108 | } | |
4109 | ||
4110 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ | |
4111 | } | |
4112 | ||
eb1cbe48 DV |
4113 | static void i9xx_update_pll(struct drm_crtc *crtc, |
4114 | struct drm_display_mode *mode, | |
4115 | struct drm_display_mode *adjusted_mode, | |
4116 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
4117 | int num_connectors) | |
4118 | { | |
4119 | struct drm_device *dev = crtc->dev; | |
4120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4121 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4122 | int pipe = intel_crtc->pipe; | |
4123 | u32 dpll; | |
4124 | bool is_sdvo; | |
4125 | ||
4126 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || | |
4127 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
4128 | ||
4129 | dpll = DPLL_VGA_MODE_DIS; | |
4130 | ||
4131 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4132 | dpll |= DPLLB_MODE_LVDS; | |
4133 | else | |
4134 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4135 | if (is_sdvo) { | |
4136 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4137 | if (pixel_multiplier > 1) { | |
4138 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4139 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4140 | } | |
4141 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4142 | } | |
4143 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4144 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4145 | ||
4146 | /* compute bitmask from p1 value */ | |
4147 | if (IS_PINEVIEW(dev)) | |
4148 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4149 | else { | |
4150 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4151 | if (IS_G4X(dev) && reduced_clock) | |
4152 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4153 | } | |
4154 | switch (clock->p2) { | |
4155 | case 5: | |
4156 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4157 | break; | |
4158 | case 7: | |
4159 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4160 | break; | |
4161 | case 10: | |
4162 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4163 | break; | |
4164 | case 14: | |
4165 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4166 | break; | |
4167 | } | |
4168 | if (INTEL_INFO(dev)->gen >= 4) | |
4169 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4170 | ||
4171 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4172 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4173 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4174 | /* XXX: just matching BIOS for now */ | |
4175 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4176 | dpll |= 3; | |
4177 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4178 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4179 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4180 | else | |
4181 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4182 | ||
4183 | dpll |= DPLL_VCO_ENABLE; | |
4184 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4185 | POSTING_READ(DPLL(pipe)); | |
4186 | udelay(150); | |
4187 | ||
4188 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4189 | * This is an exception to the general rule that mode_set doesn't turn | |
4190 | * things on. | |
4191 | */ | |
4192 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4193 | intel_update_lvds(crtc, clock, adjusted_mode); | |
4194 | ||
4195 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4196 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4197 | ||
4198 | I915_WRITE(DPLL(pipe), dpll); | |
4199 | ||
4200 | /* Wait for the clocks to stabilize. */ | |
4201 | POSTING_READ(DPLL(pipe)); | |
4202 | udelay(150); | |
4203 | ||
4204 | if (INTEL_INFO(dev)->gen >= 4) { | |
4205 | u32 temp = 0; | |
4206 | if (is_sdvo) { | |
4207 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4208 | if (temp > 1) | |
4209 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4210 | else | |
4211 | temp = 0; | |
4212 | } | |
4213 | I915_WRITE(DPLL_MD(pipe), temp); | |
4214 | } else { | |
4215 | /* The pixel multiplier can only be updated once the | |
4216 | * DPLL is enabled and the clocks are stable. | |
4217 | * | |
4218 | * So write it again. | |
4219 | */ | |
4220 | I915_WRITE(DPLL(pipe), dpll); | |
4221 | } | |
4222 | } | |
4223 | ||
4224 | static void i8xx_update_pll(struct drm_crtc *crtc, | |
4225 | struct drm_display_mode *adjusted_mode, | |
4226 | intel_clock_t *clock, | |
4227 | int num_connectors) | |
4228 | { | |
4229 | struct drm_device *dev = crtc->dev; | |
4230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4231 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4232 | int pipe = intel_crtc->pipe; | |
4233 | u32 dpll; | |
4234 | ||
4235 | dpll = DPLL_VGA_MODE_DIS; | |
4236 | ||
4237 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4238 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4239 | } else { | |
4240 | if (clock->p1 == 2) | |
4241 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4242 | else | |
4243 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4244 | if (clock->p2 == 4) | |
4245 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4246 | } | |
4247 | ||
4248 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4249 | /* XXX: just matching BIOS for now */ | |
4250 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4251 | dpll |= 3; | |
4252 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4253 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4254 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4255 | else | |
4256 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4257 | ||
4258 | dpll |= DPLL_VCO_ENABLE; | |
4259 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4260 | POSTING_READ(DPLL(pipe)); | |
4261 | udelay(150); | |
4262 | ||
4263 | I915_WRITE(DPLL(pipe), dpll); | |
4264 | ||
4265 | /* Wait for the clocks to stabilize. */ | |
4266 | POSTING_READ(DPLL(pipe)); | |
4267 | udelay(150); | |
4268 | ||
4269 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4270 | * This is an exception to the general rule that mode_set doesn't turn | |
4271 | * things on. | |
4272 | */ | |
4273 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4274 | intel_update_lvds(crtc, clock, adjusted_mode); | |
4275 | ||
4276 | /* The pixel multiplier can only be updated once the | |
4277 | * DPLL is enabled and the clocks are stable. | |
4278 | * | |
4279 | * So write it again. | |
4280 | */ | |
4281 | I915_WRITE(DPLL(pipe), dpll); | |
4282 | } | |
4283 | ||
f564048e EA |
4284 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4285 | struct drm_display_mode *mode, | |
4286 | struct drm_display_mode *adjusted_mode, | |
4287 | int x, int y, | |
94352cf9 | 4288 | struct drm_framebuffer *fb) |
79e53945 JB |
4289 | { |
4290 | struct drm_device *dev = crtc->dev; | |
4291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4293 | int pipe = intel_crtc->pipe; | |
80824003 | 4294 | int plane = intel_crtc->plane; |
c751ce4f | 4295 | int refclk, num_connectors = 0; |
652c393a | 4296 | intel_clock_t clock, reduced_clock; |
eb1cbe48 DV |
4297 | u32 dspcntr, pipeconf, vsyncshift; |
4298 | bool ok, has_reduced_clock = false, is_sdvo = false; | |
4299 | bool is_lvds = false, is_tv = false, is_dp = false; | |
5eddb70b | 4300 | struct intel_encoder *encoder; |
d4906093 | 4301 | const intel_limit_t *limit; |
5c3b82e2 | 4302 | int ret; |
79e53945 | 4303 | |
6c2b7c12 | 4304 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4305 | switch (encoder->type) { |
79e53945 JB |
4306 | case INTEL_OUTPUT_LVDS: |
4307 | is_lvds = true; | |
4308 | break; | |
4309 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4310 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4311 | is_sdvo = true; |
5eddb70b | 4312 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4313 | is_tv = true; |
79e53945 | 4314 | break; |
79e53945 JB |
4315 | case INTEL_OUTPUT_TVOUT: |
4316 | is_tv = true; | |
4317 | break; | |
a4fc5ed6 KP |
4318 | case INTEL_OUTPUT_DISPLAYPORT: |
4319 | is_dp = true; | |
4320 | break; | |
79e53945 | 4321 | } |
43565a06 | 4322 | |
c751ce4f | 4323 | num_connectors++; |
79e53945 JB |
4324 | } |
4325 | ||
c65d77d8 | 4326 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4327 | |
d4906093 ML |
4328 | /* |
4329 | * Returns a set of divisors for the desired target clock with the given | |
4330 | * refclk, or FALSE. The returned values represent the clock equation: | |
4331 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4332 | */ | |
1b894b59 | 4333 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4334 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4335 | &clock); | |
79e53945 JB |
4336 | if (!ok) { |
4337 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4338 | return -EINVAL; |
79e53945 JB |
4339 | } |
4340 | ||
cda4b7d3 | 4341 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4342 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4343 | |
ddc9003c | 4344 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4345 | /* |
4346 | * Ensure we match the reduced clock's P to the target clock. | |
4347 | * If the clocks don't match, we can't switch the display clock | |
4348 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4349 | * downclock feature. | |
4350 | */ | |
ddc9003c | 4351 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4352 | dev_priv->lvds_downclock, |
4353 | refclk, | |
cec2f356 | 4354 | &clock, |
5eddb70b | 4355 | &reduced_clock); |
7026d4ac ZW |
4356 | } |
4357 | ||
c65d77d8 JB |
4358 | if (is_sdvo && is_tv) |
4359 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 4360 | |
a7516a05 JB |
4361 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
4362 | &reduced_clock : NULL); | |
79e53945 | 4363 | |
eb1cbe48 DV |
4364 | if (IS_GEN2(dev)) |
4365 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); | |
a0c4da24 JB |
4366 | else if (IS_VALLEYVIEW(dev)) |
4367 | vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, | |
4368 | refclk, num_connectors); | |
79e53945 | 4369 | else |
eb1cbe48 DV |
4370 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
4371 | has_reduced_clock ? &reduced_clock : NULL, | |
4372 | num_connectors); | |
79e53945 JB |
4373 | |
4374 | /* setup pipeconf */ | |
5eddb70b | 4375 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4376 | |
4377 | /* Set up the display plane register */ | |
4378 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4379 | ||
929c77fb EA |
4380 | if (pipe == 0) |
4381 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4382 | else | |
4383 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 4384 | |
a6c45cf0 | 4385 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4386 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4387 | * core speed. | |
4388 | * | |
4389 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4390 | * pipe == 0 check? | |
4391 | */ | |
e70236a8 JB |
4392 | if (mode->clock > |
4393 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4394 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4395 | else |
5eddb70b | 4396 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4397 | } |
4398 | ||
3b5c78a3 AJ |
4399 | /* default to 8bpc */ |
4400 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
4401 | if (is_dp) { | |
4402 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
4403 | pipeconf |= PIPECONF_BPP_6 | | |
4404 | PIPECONF_DITHER_EN | | |
4405 | PIPECONF_DITHER_TYPE_SP; | |
4406 | } | |
4407 | } | |
4408 | ||
28c97730 | 4409 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4410 | drm_mode_debug_printmodeline(mode); |
4411 | ||
a7516a05 JB |
4412 | if (HAS_PIPE_CXSR(dev)) { |
4413 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 4414 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 4415 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 4416 | } else { |
28c97730 | 4417 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4418 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4419 | } | |
4420 | } | |
4421 | ||
617cf884 | 4422 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 DV |
4423 | if (!IS_GEN2(dev) && |
4424 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
734b4157 KH |
4425 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4426 | /* the chip adds 2 halflines automatically */ | |
734b4157 | 4427 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 4428 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
4429 | vsyncshift = adjusted_mode->crtc_hsync_start |
4430 | - adjusted_mode->crtc_htotal/2; | |
4431 | } else { | |
617cf884 | 4432 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
4433 | vsyncshift = 0; |
4434 | } | |
4435 | ||
4436 | if (!IS_GEN3(dev)) | |
4437 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); | |
734b4157 | 4438 | |
5eddb70b CW |
4439 | I915_WRITE(HTOTAL(pipe), |
4440 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4441 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4442 | I915_WRITE(HBLANK(pipe), |
4443 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4444 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4445 | I915_WRITE(HSYNC(pipe), |
4446 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4447 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4448 | |
4449 | I915_WRITE(VTOTAL(pipe), | |
4450 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4451 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4452 | I915_WRITE(VBLANK(pipe), |
4453 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4454 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4455 | I915_WRITE(VSYNC(pipe), |
4456 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4457 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
4458 | |
4459 | /* pipesrc and dspsize control the size that is scaled from, | |
4460 | * which should always be the user's requested size. | |
79e53945 | 4461 | */ |
929c77fb EA |
4462 | I915_WRITE(DSPSIZE(plane), |
4463 | ((mode->vdisplay - 1) << 16) | | |
4464 | (mode->hdisplay - 1)); | |
4465 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
4466 | I915_WRITE(PIPESRC(pipe), |
4467 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4468 | |
f564048e EA |
4469 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4470 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 4471 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
4472 | |
4473 | intel_wait_for_vblank(dev, pipe); | |
4474 | ||
f564048e EA |
4475 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4476 | POSTING_READ(DSPCNTR(plane)); | |
4477 | ||
94352cf9 | 4478 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e EA |
4479 | |
4480 | intel_update_watermarks(dev); | |
4481 | ||
f564048e EA |
4482 | return ret; |
4483 | } | |
4484 | ||
9fb526db KP |
4485 | /* |
4486 | * Initialize reference clocks when the driver loads | |
4487 | */ | |
4488 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
4489 | { |
4490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4491 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 4492 | struct intel_encoder *encoder; |
13d83a67 JB |
4493 | u32 temp; |
4494 | bool has_lvds = false; | |
199e5d79 KP |
4495 | bool has_cpu_edp = false; |
4496 | bool has_pch_edp = false; | |
4497 | bool has_panel = false; | |
99eb6a01 KP |
4498 | bool has_ck505 = false; |
4499 | bool can_ssc = false; | |
13d83a67 JB |
4500 | |
4501 | /* We need to take the global config into account */ | |
199e5d79 KP |
4502 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4503 | base.head) { | |
4504 | switch (encoder->type) { | |
4505 | case INTEL_OUTPUT_LVDS: | |
4506 | has_panel = true; | |
4507 | has_lvds = true; | |
4508 | break; | |
4509 | case INTEL_OUTPUT_EDP: | |
4510 | has_panel = true; | |
4511 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4512 | has_pch_edp = true; | |
4513 | else | |
4514 | has_cpu_edp = true; | |
4515 | break; | |
13d83a67 JB |
4516 | } |
4517 | } | |
4518 | ||
99eb6a01 KP |
4519 | if (HAS_PCH_IBX(dev)) { |
4520 | has_ck505 = dev_priv->display_clock_mode; | |
4521 | can_ssc = has_ck505; | |
4522 | } else { | |
4523 | has_ck505 = false; | |
4524 | can_ssc = true; | |
4525 | } | |
4526 | ||
4527 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
4528 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
4529 | has_ck505); | |
13d83a67 JB |
4530 | |
4531 | /* Ironlake: try to setup display ref clock before DPLL | |
4532 | * enabling. This is only under driver's control after | |
4533 | * PCH B stepping, previous chipset stepping should be | |
4534 | * ignoring this setting. | |
4535 | */ | |
4536 | temp = I915_READ(PCH_DREF_CONTROL); | |
4537 | /* Always enable nonspread source */ | |
4538 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 4539 | |
99eb6a01 KP |
4540 | if (has_ck505) |
4541 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
4542 | else | |
4543 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 4544 | |
199e5d79 KP |
4545 | if (has_panel) { |
4546 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4547 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 4548 | |
199e5d79 | 4549 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 4550 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4551 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 4552 | temp |= DREF_SSC1_ENABLE; |
e77166b5 DV |
4553 | } else |
4554 | temp &= ~DREF_SSC1_ENABLE; | |
199e5d79 KP |
4555 | |
4556 | /* Get SSC going before enabling the outputs */ | |
4557 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4558 | POSTING_READ(PCH_DREF_CONTROL); | |
4559 | udelay(200); | |
4560 | ||
13d83a67 JB |
4561 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4562 | ||
4563 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 4564 | if (has_cpu_edp) { |
99eb6a01 | 4565 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4566 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 4567 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 4568 | } |
13d83a67 JB |
4569 | else |
4570 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
4571 | } else |
4572 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4573 | ||
4574 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4575 | POSTING_READ(PCH_DREF_CONTROL); | |
4576 | udelay(200); | |
4577 | } else { | |
4578 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
4579 | ||
4580 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4581 | ||
4582 | /* Turn off CPU output */ | |
4583 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4584 | ||
4585 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4586 | POSTING_READ(PCH_DREF_CONTROL); | |
4587 | udelay(200); | |
4588 | ||
4589 | /* Turn off the SSC source */ | |
4590 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4591 | temp |= DREF_SSC_SOURCE_DISABLE; | |
4592 | ||
4593 | /* Turn off SSC1 */ | |
4594 | temp &= ~ DREF_SSC1_ENABLE; | |
4595 | ||
13d83a67 JB |
4596 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4597 | POSTING_READ(PCH_DREF_CONTROL); | |
4598 | udelay(200); | |
4599 | } | |
4600 | } | |
4601 | ||
d9d444cb JB |
4602 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
4603 | { | |
4604 | struct drm_device *dev = crtc->dev; | |
4605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4606 | struct intel_encoder *encoder; | |
d9d444cb JB |
4607 | struct intel_encoder *edp_encoder = NULL; |
4608 | int num_connectors = 0; | |
4609 | bool is_lvds = false; | |
4610 | ||
6c2b7c12 | 4611 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
4612 | switch (encoder->type) { |
4613 | case INTEL_OUTPUT_LVDS: | |
4614 | is_lvds = true; | |
4615 | break; | |
4616 | case INTEL_OUTPUT_EDP: | |
4617 | edp_encoder = encoder; | |
4618 | break; | |
4619 | } | |
4620 | num_connectors++; | |
4621 | } | |
4622 | ||
4623 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
4624 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4625 | dev_priv->lvds_ssc_freq); | |
4626 | return dev_priv->lvds_ssc_freq * 1000; | |
4627 | } | |
4628 | ||
4629 | return 120000; | |
4630 | } | |
4631 | ||
f564048e EA |
4632 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
4633 | struct drm_display_mode *mode, | |
4634 | struct drm_display_mode *adjusted_mode, | |
4635 | int x, int y, | |
94352cf9 | 4636 | struct drm_framebuffer *fb) |
79e53945 JB |
4637 | { |
4638 | struct drm_device *dev = crtc->dev; | |
4639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4640 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4641 | int pipe = intel_crtc->pipe; | |
80824003 | 4642 | int plane = intel_crtc->plane; |
c751ce4f | 4643 | int refclk, num_connectors = 0; |
652c393a | 4644 | intel_clock_t clock, reduced_clock; |
5eddb70b | 4645 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 4646 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 4647 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
e3aef172 | 4648 | struct intel_encoder *encoder, *edp_encoder = NULL; |
d4906093 | 4649 | const intel_limit_t *limit; |
5c3b82e2 | 4650 | int ret; |
2c07245f | 4651 | struct fdi_m_n m_n = {0}; |
fae14981 | 4652 | u32 temp; |
5a354204 JB |
4653 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
4654 | unsigned int pipe_bpp; | |
4655 | bool dither; | |
e3aef172 | 4656 | bool is_cpu_edp = false, is_pch_edp = false; |
79e53945 | 4657 | |
6c2b7c12 | 4658 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4659 | switch (encoder->type) { |
79e53945 JB |
4660 | case INTEL_OUTPUT_LVDS: |
4661 | is_lvds = true; | |
4662 | break; | |
4663 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4664 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4665 | is_sdvo = true; |
5eddb70b | 4666 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4667 | is_tv = true; |
79e53945 | 4668 | break; |
79e53945 JB |
4669 | case INTEL_OUTPUT_TVOUT: |
4670 | is_tv = true; | |
4671 | break; | |
4672 | case INTEL_OUTPUT_ANALOG: | |
4673 | is_crt = true; | |
4674 | break; | |
a4fc5ed6 KP |
4675 | case INTEL_OUTPUT_DISPLAYPORT: |
4676 | is_dp = true; | |
4677 | break; | |
32f9d658 | 4678 | case INTEL_OUTPUT_EDP: |
e3aef172 JB |
4679 | is_dp = true; |
4680 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4681 | is_pch_edp = true; | |
4682 | else | |
4683 | is_cpu_edp = true; | |
4684 | edp_encoder = encoder; | |
32f9d658 | 4685 | break; |
79e53945 | 4686 | } |
43565a06 | 4687 | |
c751ce4f | 4688 | num_connectors++; |
79e53945 JB |
4689 | } |
4690 | ||
d9d444cb | 4691 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 4692 | |
d4906093 ML |
4693 | /* |
4694 | * Returns a set of divisors for the desired target clock with the given | |
4695 | * refclk, or FALSE. The returned values represent the clock equation: | |
4696 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4697 | */ | |
1b894b59 | 4698 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4699 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4700 | &clock); | |
79e53945 JB |
4701 | if (!ok) { |
4702 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4703 | return -EINVAL; |
79e53945 JB |
4704 | } |
4705 | ||
cda4b7d3 | 4706 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4707 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4708 | |
ddc9003c | 4709 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4710 | /* |
4711 | * Ensure we match the reduced clock's P to the target clock. | |
4712 | * If the clocks don't match, we can't switch the display clock | |
4713 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4714 | * downclock feature. | |
4715 | */ | |
ddc9003c | 4716 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4717 | dev_priv->lvds_downclock, |
4718 | refclk, | |
cec2f356 | 4719 | &clock, |
5eddb70b | 4720 | &reduced_clock); |
652c393a | 4721 | } |
61e9653f DV |
4722 | |
4723 | if (is_sdvo && is_tv) | |
4724 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
4725 | ||
7026d4ac | 4726 | |
2c07245f | 4727 | /* FDI link */ |
8febb297 EA |
4728 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4729 | lane = 0; | |
4730 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
4731 | according to current link config */ | |
e3aef172 | 4732 | if (is_cpu_edp) { |
e3aef172 | 4733 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
8febb297 | 4734 | } else { |
8febb297 EA |
4735 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4736 | * each output octet as 10 bits. The actual frequency | |
4737 | * is stored as a divider into a 100MHz clock, and the | |
4738 | * mode pixel clock is stored in units of 1KHz. | |
4739 | * Hence the bw of each lane in terms of the mode signal | |
4740 | * is: | |
4741 | */ | |
4742 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4743 | } | |
58a27471 | 4744 | |
94bf2ced DV |
4745 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
4746 | if (edp_encoder) | |
4747 | target_clock = intel_edp_target_clock(edp_encoder, mode); | |
4748 | else if (is_dp) | |
4749 | target_clock = mode->clock; | |
4750 | else | |
4751 | target_clock = adjusted_mode->clock; | |
4752 | ||
8febb297 EA |
4753 | /* determine panel color depth */ |
4754 | temp = I915_READ(PIPECONF(pipe)); | |
4755 | temp &= ~PIPE_BPC_MASK; | |
94352cf9 | 4756 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode); |
5a354204 JB |
4757 | switch (pipe_bpp) { |
4758 | case 18: | |
4759 | temp |= PIPE_6BPC; | |
8febb297 | 4760 | break; |
5a354204 JB |
4761 | case 24: |
4762 | temp |= PIPE_8BPC; | |
8febb297 | 4763 | break; |
5a354204 JB |
4764 | case 30: |
4765 | temp |= PIPE_10BPC; | |
8febb297 | 4766 | break; |
5a354204 JB |
4767 | case 36: |
4768 | temp |= PIPE_12BPC; | |
8febb297 EA |
4769 | break; |
4770 | default: | |
62ac41a6 JB |
4771 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
4772 | pipe_bpp); | |
5a354204 JB |
4773 | temp |= PIPE_8BPC; |
4774 | pipe_bpp = 24; | |
4775 | break; | |
8febb297 | 4776 | } |
77ffb597 | 4777 | |
5a354204 JB |
4778 | intel_crtc->bpp = pipe_bpp; |
4779 | I915_WRITE(PIPECONF(pipe), temp); | |
4780 | ||
8febb297 EA |
4781 | if (!lane) { |
4782 | /* | |
4783 | * Account for spread spectrum to avoid | |
4784 | * oversubscribing the link. Max center spread | |
4785 | * is 2.5%; use 5% for safety's sake. | |
4786 | */ | |
5a354204 | 4787 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 4788 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 4789 | } |
2c07245f | 4790 | |
8febb297 EA |
4791 | intel_crtc->fdi_lanes = lane; |
4792 | ||
4793 | if (pixel_multiplier > 1) | |
4794 | link_bw *= pixel_multiplier; | |
5a354204 JB |
4795 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
4796 | &m_n); | |
8febb297 | 4797 | |
a07d6787 EA |
4798 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
4799 | if (has_reduced_clock) | |
4800 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4801 | reduced_clock.m2; | |
79e53945 | 4802 | |
c1858123 | 4803 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
4804 | factor = 21; |
4805 | if (is_lvds) { | |
4806 | if ((intel_panel_use_ssc(dev_priv) && | |
4807 | dev_priv->lvds_ssc_freq == 100) || | |
4808 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
4809 | factor = 25; | |
4810 | } else if (is_sdvo && is_tv) | |
4811 | factor = 20; | |
c1858123 | 4812 | |
cb0e0931 | 4813 | if (clock.m < factor * clock.n) |
8febb297 | 4814 | fp |= FP_CB_TUNE; |
2c07245f | 4815 | |
5eddb70b | 4816 | dpll = 0; |
2c07245f | 4817 | |
a07d6787 EA |
4818 | if (is_lvds) |
4819 | dpll |= DPLLB_MODE_LVDS; | |
4820 | else | |
4821 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4822 | if (is_sdvo) { | |
4823 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4824 | if (pixel_multiplier > 1) { | |
4825 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 4826 | } |
a07d6787 EA |
4827 | dpll |= DPLL_DVO_HIGH_SPEED; |
4828 | } | |
e3aef172 | 4829 | if (is_dp && !is_cpu_edp) |
a07d6787 | 4830 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 4831 | |
a07d6787 EA |
4832 | /* compute bitmask from p1 value */ |
4833 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4834 | /* also FPA1 */ | |
4835 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4836 | ||
4837 | switch (clock.p2) { | |
4838 | case 5: | |
4839 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4840 | break; | |
4841 | case 7: | |
4842 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4843 | break; | |
4844 | case 10: | |
4845 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4846 | break; | |
4847 | case 14: | |
4848 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4849 | break; | |
79e53945 JB |
4850 | } |
4851 | ||
43565a06 KH |
4852 | if (is_sdvo && is_tv) |
4853 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4854 | else if (is_tv) | |
79e53945 | 4855 | /* XXX: just matching BIOS for now */ |
43565a06 | 4856 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 4857 | dpll |= 3; |
a7615030 | 4858 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 4859 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
4860 | else |
4861 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4862 | ||
4863 | /* setup pipeconf */ | |
5eddb70b | 4864 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4865 | |
4866 | /* Set up the display plane register */ | |
4867 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4868 | ||
f7cb34d4 | 4869 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
4870 | drm_mode_debug_printmodeline(mode); |
4871 | ||
9d82aa17 ED |
4872 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own on |
4873 | * pre-Haswell/LPT generation */ | |
4874 | if (HAS_PCH_LPT(dev)) { | |
4875 | DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n", | |
4876 | pipe); | |
4877 | } else if (!is_cpu_edp) { | |
ee7b9f93 | 4878 | struct intel_pch_pll *pll; |
4b645f14 | 4879 | |
ee7b9f93 JB |
4880 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
4881 | if (pll == NULL) { | |
4882 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", | |
4883 | pipe); | |
4b645f14 JB |
4884 | return -EINVAL; |
4885 | } | |
ee7b9f93 JB |
4886 | } else |
4887 | intel_put_pch_pll(intel_crtc); | |
79e53945 JB |
4888 | |
4889 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4890 | * This is an exception to the general rule that mode_set doesn't turn | |
4891 | * things on. | |
4892 | */ | |
4893 | if (is_lvds) { | |
fae14981 | 4894 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 4895 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
7885d205 JB |
4896 | if (HAS_PCH_CPT(dev)) { |
4897 | temp &= ~PORT_TRANS_SEL_MASK; | |
4b645f14 | 4898 | temp |= PORT_TRANS_SEL_CPT(pipe); |
7885d205 JB |
4899 | } else { |
4900 | if (pipe == 1) | |
4901 | temp |= LVDS_PIPEB_SELECT; | |
4902 | else | |
4903 | temp &= ~LVDS_PIPEB_SELECT; | |
4904 | } | |
4b645f14 | 4905 | |
a3e17eb8 | 4906 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 4907 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
4908 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4909 | * set the DPLLs for dual-channel mode or not. | |
4910 | */ | |
4911 | if (clock.p2 == 7) | |
5eddb70b | 4912 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 4913 | else |
5eddb70b | 4914 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
4915 | |
4916 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4917 | * appropriately here, but we need to look more thoroughly into how | |
4918 | * panels behave in the two modes. | |
4919 | */ | |
284d5df5 | 4920 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
aa9b500d | 4921 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
284d5df5 | 4922 | temp |= LVDS_HSYNC_POLARITY; |
aa9b500d | 4923 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
284d5df5 | 4924 | temp |= LVDS_VSYNC_POLARITY; |
fae14981 | 4925 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 4926 | } |
434ed097 | 4927 | |
8febb297 EA |
4928 | pipeconf &= ~PIPECONF_DITHER_EN; |
4929 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 4930 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 | 4931 | pipeconf |= PIPECONF_DITHER_EN; |
f74974c7 | 4932 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
434ed097 | 4933 | } |
e3aef172 | 4934 | if (is_dp && !is_cpu_edp) { |
a4fc5ed6 | 4935 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 4936 | } else { |
8db9d77b | 4937 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
4938 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
4939 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
4940 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
4941 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 4942 | } |
79e53945 | 4943 | |
ee7b9f93 JB |
4944 | if (intel_crtc->pch_pll) { |
4945 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); | |
5eddb70b | 4946 | |
32f9d658 | 4947 | /* Wait for the clocks to stabilize. */ |
ee7b9f93 | 4948 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
32f9d658 ZW |
4949 | udelay(150); |
4950 | ||
8febb297 EA |
4951 | /* The pixel multiplier can only be updated once the |
4952 | * DPLL is enabled and the clocks are stable. | |
4953 | * | |
4954 | * So write it again. | |
4955 | */ | |
ee7b9f93 | 4956 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
79e53945 | 4957 | } |
79e53945 | 4958 | |
5eddb70b | 4959 | intel_crtc->lowfreq_avail = false; |
ee7b9f93 | 4960 | if (intel_crtc->pch_pll) { |
4b645f14 | 4961 | if (is_lvds && has_reduced_clock && i915_powersave) { |
ee7b9f93 | 4962 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
4b645f14 | 4963 | intel_crtc->lowfreq_avail = true; |
4b645f14 | 4964 | } else { |
ee7b9f93 | 4965 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
652c393a JB |
4966 | } |
4967 | } | |
4968 | ||
617cf884 | 4969 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
734b4157 | 4970 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5def474e | 4971 | pipeconf |= PIPECONF_INTERLACED_ILK; |
734b4157 | 4972 | /* the chip adds 2 halflines automatically */ |
734b4157 | 4973 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 4974 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
4975 | I915_WRITE(VSYNCSHIFT(pipe), |
4976 | adjusted_mode->crtc_hsync_start | |
4977 | - adjusted_mode->crtc_htotal/2); | |
4978 | } else { | |
617cf884 | 4979 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
4980 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
4981 | } | |
734b4157 | 4982 | |
5eddb70b CW |
4983 | I915_WRITE(HTOTAL(pipe), |
4984 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4985 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4986 | I915_WRITE(HBLANK(pipe), |
4987 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4988 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4989 | I915_WRITE(HSYNC(pipe), |
4990 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4991 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4992 | |
4993 | I915_WRITE(VTOTAL(pipe), | |
4994 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4995 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4996 | I915_WRITE(VBLANK(pipe), |
4997 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4998 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4999 | I915_WRITE(VSYNC(pipe), |
5000 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5001 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 5002 | |
8febb297 EA |
5003 | /* pipesrc controls the size that is scaled from, which should |
5004 | * always be the user's requested size. | |
79e53945 | 5005 | */ |
5eddb70b CW |
5006 | I915_WRITE(PIPESRC(pipe), |
5007 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5008 | |
8febb297 EA |
5009 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5010 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
5011 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
5012 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 5013 | |
e3aef172 | 5014 | if (is_cpu_edp) |
8febb297 | 5015 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
2c07245f | 5016 | |
5eddb70b CW |
5017 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5018 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 5019 | |
9d0498a2 | 5020 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5021 | |
5eddb70b | 5022 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 5023 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5024 | |
94352cf9 | 5025 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd SL |
5026 | |
5027 | intel_update_watermarks(dev); | |
5028 | ||
1f8eeabf ED |
5029 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5030 | ||
1f803ee5 | 5031 | return ret; |
79e53945 JB |
5032 | } |
5033 | ||
f564048e EA |
5034 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5035 | struct drm_display_mode *mode, | |
5036 | struct drm_display_mode *adjusted_mode, | |
5037 | int x, int y, | |
94352cf9 | 5038 | struct drm_framebuffer *fb) |
f564048e EA |
5039 | { |
5040 | struct drm_device *dev = crtc->dev; | |
5041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
5042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5043 | int pipe = intel_crtc->pipe; | |
f564048e EA |
5044 | int ret; |
5045 | ||
0b701d27 | 5046 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 5047 | |
f564048e | 5048 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
94352cf9 | 5049 | x, y, fb); |
79e53945 | 5050 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 5051 | |
1f803ee5 | 5052 | return ret; |
79e53945 JB |
5053 | } |
5054 | ||
3a9627f4 WF |
5055 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5056 | int reg_eldv, uint32_t bits_eldv, | |
5057 | int reg_elda, uint32_t bits_elda, | |
5058 | int reg_edid) | |
5059 | { | |
5060 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5061 | uint8_t *eld = connector->eld; | |
5062 | uint32_t i; | |
5063 | ||
5064 | i = I915_READ(reg_eldv); | |
5065 | i &= bits_eldv; | |
5066 | ||
5067 | if (!eld[0]) | |
5068 | return !i; | |
5069 | ||
5070 | if (!i) | |
5071 | return false; | |
5072 | ||
5073 | i = I915_READ(reg_elda); | |
5074 | i &= ~bits_elda; | |
5075 | I915_WRITE(reg_elda, i); | |
5076 | ||
5077 | for (i = 0; i < eld[2]; i++) | |
5078 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
5079 | return false; | |
5080 | ||
5081 | return true; | |
5082 | } | |
5083 | ||
e0dac65e WF |
5084 | static void g4x_write_eld(struct drm_connector *connector, |
5085 | struct drm_crtc *crtc) | |
5086 | { | |
5087 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5088 | uint8_t *eld = connector->eld; | |
5089 | uint32_t eldv; | |
5090 | uint32_t len; | |
5091 | uint32_t i; | |
5092 | ||
5093 | i = I915_READ(G4X_AUD_VID_DID); | |
5094 | ||
5095 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5096 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5097 | else | |
5098 | eldv = G4X_ELDV_DEVCTG; | |
5099 | ||
3a9627f4 WF |
5100 | if (intel_eld_uptodate(connector, |
5101 | G4X_AUD_CNTL_ST, eldv, | |
5102 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
5103 | G4X_HDMIW_HDMIEDID)) | |
5104 | return; | |
5105 | ||
e0dac65e WF |
5106 | i = I915_READ(G4X_AUD_CNTL_ST); |
5107 | i &= ~(eldv | G4X_ELD_ADDR); | |
5108 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5109 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5110 | ||
5111 | if (!eld[0]) | |
5112 | return; | |
5113 | ||
5114 | len = min_t(uint8_t, eld[2], len); | |
5115 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5116 | for (i = 0; i < len; i++) | |
5117 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5118 | ||
5119 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5120 | i |= eldv; | |
5121 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5122 | } | |
5123 | ||
83358c85 WX |
5124 | static void haswell_write_eld(struct drm_connector *connector, |
5125 | struct drm_crtc *crtc) | |
5126 | { | |
5127 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5128 | uint8_t *eld = connector->eld; | |
5129 | struct drm_device *dev = crtc->dev; | |
5130 | uint32_t eldv; | |
5131 | uint32_t i; | |
5132 | int len; | |
5133 | int pipe = to_intel_crtc(crtc)->pipe; | |
5134 | int tmp; | |
5135 | ||
5136 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
5137 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
5138 | int aud_config = HSW_AUD_CFG(pipe); | |
5139 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
5140 | ||
5141 | ||
5142 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
5143 | ||
5144 | /* Audio output enable */ | |
5145 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
5146 | tmp = I915_READ(aud_cntrl_st2); | |
5147 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
5148 | I915_WRITE(aud_cntrl_st2, tmp); | |
5149 | ||
5150 | /* Wait for 1 vertical blank */ | |
5151 | intel_wait_for_vblank(dev, pipe); | |
5152 | ||
5153 | /* Set ELD valid state */ | |
5154 | tmp = I915_READ(aud_cntrl_st2); | |
5155 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); | |
5156 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); | |
5157 | I915_WRITE(aud_cntrl_st2, tmp); | |
5158 | tmp = I915_READ(aud_cntrl_st2); | |
5159 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); | |
5160 | ||
5161 | /* Enable HDMI mode */ | |
5162 | tmp = I915_READ(aud_config); | |
5163 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); | |
5164 | /* clear N_programing_enable and N_value_index */ | |
5165 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
5166 | I915_WRITE(aud_config, tmp); | |
5167 | ||
5168 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
5169 | ||
5170 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
5171 | ||
5172 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5173 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5174 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
5175 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
5176 | } else | |
5177 | I915_WRITE(aud_config, 0); | |
5178 | ||
5179 | if (intel_eld_uptodate(connector, | |
5180 | aud_cntrl_st2, eldv, | |
5181 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5182 | hdmiw_hdmiedid)) | |
5183 | return; | |
5184 | ||
5185 | i = I915_READ(aud_cntrl_st2); | |
5186 | i &= ~eldv; | |
5187 | I915_WRITE(aud_cntrl_st2, i); | |
5188 | ||
5189 | if (!eld[0]) | |
5190 | return; | |
5191 | ||
5192 | i = I915_READ(aud_cntl_st); | |
5193 | i &= ~IBX_ELD_ADDRESS; | |
5194 | I915_WRITE(aud_cntl_st, i); | |
5195 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
5196 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
5197 | ||
5198 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5199 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5200 | for (i = 0; i < len; i++) | |
5201 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5202 | ||
5203 | i = I915_READ(aud_cntrl_st2); | |
5204 | i |= eldv; | |
5205 | I915_WRITE(aud_cntrl_st2, i); | |
5206 | ||
5207 | } | |
5208 | ||
e0dac65e WF |
5209 | static void ironlake_write_eld(struct drm_connector *connector, |
5210 | struct drm_crtc *crtc) | |
5211 | { | |
5212 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5213 | uint8_t *eld = connector->eld; | |
5214 | uint32_t eldv; | |
5215 | uint32_t i; | |
5216 | int len; | |
5217 | int hdmiw_hdmiedid; | |
b6daa025 | 5218 | int aud_config; |
e0dac65e WF |
5219 | int aud_cntl_st; |
5220 | int aud_cntrl_st2; | |
9b138a83 | 5221 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 5222 | |
b3f33cbf | 5223 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
5224 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
5225 | aud_config = IBX_AUD_CFG(pipe); | |
5226 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5227 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 5228 | } else { |
9b138a83 WX |
5229 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
5230 | aud_config = CPT_AUD_CFG(pipe); | |
5231 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5232 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
5233 | } |
5234 | ||
9b138a83 | 5235 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
5236 | |
5237 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 5238 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
5239 | if (!i) { |
5240 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
5241 | /* operate blindly on all ports */ | |
1202b4c6 WF |
5242 | eldv = IBX_ELD_VALIDB; |
5243 | eldv |= IBX_ELD_VALIDB << 4; | |
5244 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
5245 | } else { |
5246 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 5247 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
5248 | } |
5249 | ||
3a9627f4 WF |
5250 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5251 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5252 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
5253 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5254 | } else | |
5255 | I915_WRITE(aud_config, 0); | |
e0dac65e | 5256 | |
3a9627f4 WF |
5257 | if (intel_eld_uptodate(connector, |
5258 | aud_cntrl_st2, eldv, | |
5259 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5260 | hdmiw_hdmiedid)) | |
5261 | return; | |
5262 | ||
e0dac65e WF |
5263 | i = I915_READ(aud_cntrl_st2); |
5264 | i &= ~eldv; | |
5265 | I915_WRITE(aud_cntrl_st2, i); | |
5266 | ||
5267 | if (!eld[0]) | |
5268 | return; | |
5269 | ||
e0dac65e | 5270 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 5271 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
5272 | I915_WRITE(aud_cntl_st, i); |
5273 | ||
5274 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5275 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5276 | for (i = 0; i < len; i++) | |
5277 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5278 | ||
5279 | i = I915_READ(aud_cntrl_st2); | |
5280 | i |= eldv; | |
5281 | I915_WRITE(aud_cntrl_st2, i); | |
5282 | } | |
5283 | ||
5284 | void intel_write_eld(struct drm_encoder *encoder, | |
5285 | struct drm_display_mode *mode) | |
5286 | { | |
5287 | struct drm_crtc *crtc = encoder->crtc; | |
5288 | struct drm_connector *connector; | |
5289 | struct drm_device *dev = encoder->dev; | |
5290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5291 | ||
5292 | connector = drm_select_eld(encoder, mode); | |
5293 | if (!connector) | |
5294 | return; | |
5295 | ||
5296 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
5297 | connector->base.id, | |
5298 | drm_get_connector_name(connector), | |
5299 | connector->encoder->base.id, | |
5300 | drm_get_encoder_name(connector->encoder)); | |
5301 | ||
5302 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
5303 | ||
5304 | if (dev_priv->display.write_eld) | |
5305 | dev_priv->display.write_eld(connector, crtc); | |
5306 | } | |
5307 | ||
79e53945 JB |
5308 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5309 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
5310 | { | |
5311 | struct drm_device *dev = crtc->dev; | |
5312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 5314 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
5315 | int i; |
5316 | ||
5317 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 5318 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
5319 | return; |
5320 | ||
f2b115e6 | 5321 | /* use legacy palette for Ironlake */ |
bad720ff | 5322 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 5323 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 5324 | |
79e53945 JB |
5325 | for (i = 0; i < 256; i++) { |
5326 | I915_WRITE(palreg + 4 * i, | |
5327 | (intel_crtc->lut_r[i] << 16) | | |
5328 | (intel_crtc->lut_g[i] << 8) | | |
5329 | intel_crtc->lut_b[i]); | |
5330 | } | |
5331 | } | |
5332 | ||
560b85bb CW |
5333 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5334 | { | |
5335 | struct drm_device *dev = crtc->dev; | |
5336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5338 | bool visible = base != 0; | |
5339 | u32 cntl; | |
5340 | ||
5341 | if (intel_crtc->cursor_visible == visible) | |
5342 | return; | |
5343 | ||
9db4a9c7 | 5344 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
5345 | if (visible) { |
5346 | /* On these chipsets we can only modify the base whilst | |
5347 | * the cursor is disabled. | |
5348 | */ | |
9db4a9c7 | 5349 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
5350 | |
5351 | cntl &= ~(CURSOR_FORMAT_MASK); | |
5352 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
5353 | cntl |= CURSOR_ENABLE | | |
5354 | CURSOR_GAMMA_ENABLE | | |
5355 | CURSOR_FORMAT_ARGB; | |
5356 | } else | |
5357 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 5358 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
5359 | |
5360 | intel_crtc->cursor_visible = visible; | |
5361 | } | |
5362 | ||
5363 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
5364 | { | |
5365 | struct drm_device *dev = crtc->dev; | |
5366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5368 | int pipe = intel_crtc->pipe; | |
5369 | bool visible = base != 0; | |
5370 | ||
5371 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 5372 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
5373 | if (base) { |
5374 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
5375 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5376 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
5377 | } else { | |
5378 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5379 | cntl |= CURSOR_MODE_DISABLE; | |
5380 | } | |
9db4a9c7 | 5381 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
5382 | |
5383 | intel_crtc->cursor_visible = visible; | |
5384 | } | |
5385 | /* and commit changes on next vblank */ | |
9db4a9c7 | 5386 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
5387 | } |
5388 | ||
65a21cd6 JB |
5389 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
5390 | { | |
5391 | struct drm_device *dev = crtc->dev; | |
5392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5394 | int pipe = intel_crtc->pipe; | |
5395 | bool visible = base != 0; | |
5396 | ||
5397 | if (intel_crtc->cursor_visible != visible) { | |
5398 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
5399 | if (base) { | |
5400 | cntl &= ~CURSOR_MODE; | |
5401 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5402 | } else { | |
5403 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5404 | cntl |= CURSOR_MODE_DISABLE; | |
5405 | } | |
5406 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
5407 | ||
5408 | intel_crtc->cursor_visible = visible; | |
5409 | } | |
5410 | /* and commit changes on next vblank */ | |
5411 | I915_WRITE(CURBASE_IVB(pipe), base); | |
5412 | } | |
5413 | ||
cda4b7d3 | 5414 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
5415 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
5416 | bool on) | |
cda4b7d3 CW |
5417 | { |
5418 | struct drm_device *dev = crtc->dev; | |
5419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5421 | int pipe = intel_crtc->pipe; | |
5422 | int x = intel_crtc->cursor_x; | |
5423 | int y = intel_crtc->cursor_y; | |
560b85bb | 5424 | u32 base, pos; |
cda4b7d3 CW |
5425 | bool visible; |
5426 | ||
5427 | pos = 0; | |
5428 | ||
6b383a7f | 5429 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
5430 | base = intel_crtc->cursor_addr; |
5431 | if (x > (int) crtc->fb->width) | |
5432 | base = 0; | |
5433 | ||
5434 | if (y > (int) crtc->fb->height) | |
5435 | base = 0; | |
5436 | } else | |
5437 | base = 0; | |
5438 | ||
5439 | if (x < 0) { | |
5440 | if (x + intel_crtc->cursor_width < 0) | |
5441 | base = 0; | |
5442 | ||
5443 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
5444 | x = -x; | |
5445 | } | |
5446 | pos |= x << CURSOR_X_SHIFT; | |
5447 | ||
5448 | if (y < 0) { | |
5449 | if (y + intel_crtc->cursor_height < 0) | |
5450 | base = 0; | |
5451 | ||
5452 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
5453 | y = -y; | |
5454 | } | |
5455 | pos |= y << CURSOR_Y_SHIFT; | |
5456 | ||
5457 | visible = base != 0; | |
560b85bb | 5458 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
5459 | return; |
5460 | ||
0cd83aa9 | 5461 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
5462 | I915_WRITE(CURPOS_IVB(pipe), pos); |
5463 | ivb_update_cursor(crtc, base); | |
5464 | } else { | |
5465 | I915_WRITE(CURPOS(pipe), pos); | |
5466 | if (IS_845G(dev) || IS_I865G(dev)) | |
5467 | i845_update_cursor(crtc, base); | |
5468 | else | |
5469 | i9xx_update_cursor(crtc, base); | |
5470 | } | |
cda4b7d3 CW |
5471 | } |
5472 | ||
79e53945 | 5473 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 5474 | struct drm_file *file, |
79e53945 JB |
5475 | uint32_t handle, |
5476 | uint32_t width, uint32_t height) | |
5477 | { | |
5478 | struct drm_device *dev = crtc->dev; | |
5479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 5481 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 5482 | uint32_t addr; |
3f8bc370 | 5483 | int ret; |
79e53945 | 5484 | |
79e53945 JB |
5485 | /* if we want to turn off the cursor ignore width and height */ |
5486 | if (!handle) { | |
28c97730 | 5487 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 5488 | addr = 0; |
05394f39 | 5489 | obj = NULL; |
5004417d | 5490 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 5491 | goto finish; |
79e53945 JB |
5492 | } |
5493 | ||
5494 | /* Currently we only support 64x64 cursors */ | |
5495 | if (width != 64 || height != 64) { | |
5496 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
5497 | return -EINVAL; | |
5498 | } | |
5499 | ||
05394f39 | 5500 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 5501 | if (&obj->base == NULL) |
79e53945 JB |
5502 | return -ENOENT; |
5503 | ||
05394f39 | 5504 | if (obj->base.size < width * height * 4) { |
79e53945 | 5505 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
5506 | ret = -ENOMEM; |
5507 | goto fail; | |
79e53945 JB |
5508 | } |
5509 | ||
71acb5eb | 5510 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 5511 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 5512 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
5513 | if (obj->tiling_mode) { |
5514 | DRM_ERROR("cursor cannot be tiled\n"); | |
5515 | ret = -EINVAL; | |
5516 | goto fail_locked; | |
5517 | } | |
5518 | ||
2da3b9b9 | 5519 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
5520 | if (ret) { |
5521 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 5522 | goto fail_locked; |
e7b526bb CW |
5523 | } |
5524 | ||
d9e86c0e CW |
5525 | ret = i915_gem_object_put_fence(obj); |
5526 | if (ret) { | |
2da3b9b9 | 5527 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
5528 | goto fail_unpin; |
5529 | } | |
5530 | ||
05394f39 | 5531 | addr = obj->gtt_offset; |
71acb5eb | 5532 | } else { |
6eeefaf3 | 5533 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 5534 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
5535 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
5536 | align); | |
71acb5eb DA |
5537 | if (ret) { |
5538 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 5539 | goto fail_locked; |
71acb5eb | 5540 | } |
05394f39 | 5541 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
5542 | } |
5543 | ||
a6c45cf0 | 5544 | if (IS_GEN2(dev)) |
14b60391 JB |
5545 | I915_WRITE(CURSIZE, (height << 12) | width); |
5546 | ||
3f8bc370 | 5547 | finish: |
3f8bc370 | 5548 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 5549 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 5550 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
5551 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
5552 | } else | |
5553 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 5554 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 5555 | } |
80824003 | 5556 | |
7f9872e0 | 5557 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
5558 | |
5559 | intel_crtc->cursor_addr = addr; | |
05394f39 | 5560 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
5561 | intel_crtc->cursor_width = width; |
5562 | intel_crtc->cursor_height = height; | |
5563 | ||
6b383a7f | 5564 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 5565 | |
79e53945 | 5566 | return 0; |
e7b526bb | 5567 | fail_unpin: |
05394f39 | 5568 | i915_gem_object_unpin(obj); |
7f9872e0 | 5569 | fail_locked: |
34b8686e | 5570 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 5571 | fail: |
05394f39 | 5572 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 5573 | return ret; |
79e53945 JB |
5574 | } |
5575 | ||
5576 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
5577 | { | |
79e53945 | 5578 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 5579 | |
cda4b7d3 CW |
5580 | intel_crtc->cursor_x = x; |
5581 | intel_crtc->cursor_y = y; | |
652c393a | 5582 | |
6b383a7f | 5583 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
5584 | |
5585 | return 0; | |
5586 | } | |
5587 | ||
5588 | /** Sets the color ramps on behalf of RandR */ | |
5589 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
5590 | u16 blue, int regno) | |
5591 | { | |
5592 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5593 | ||
5594 | intel_crtc->lut_r[regno] = red >> 8; | |
5595 | intel_crtc->lut_g[regno] = green >> 8; | |
5596 | intel_crtc->lut_b[regno] = blue >> 8; | |
5597 | } | |
5598 | ||
b8c00ac5 DA |
5599 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
5600 | u16 *blue, int regno) | |
5601 | { | |
5602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5603 | ||
5604 | *red = intel_crtc->lut_r[regno] << 8; | |
5605 | *green = intel_crtc->lut_g[regno] << 8; | |
5606 | *blue = intel_crtc->lut_b[regno] << 8; | |
5607 | } | |
5608 | ||
79e53945 | 5609 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 5610 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 5611 | { |
7203425a | 5612 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 5613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 5614 | |
7203425a | 5615 | for (i = start; i < end; i++) { |
79e53945 JB |
5616 | intel_crtc->lut_r[i] = red[i] >> 8; |
5617 | intel_crtc->lut_g[i] = green[i] >> 8; | |
5618 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
5619 | } | |
5620 | ||
5621 | intel_crtc_load_lut(crtc); | |
5622 | } | |
5623 | ||
5624 | /** | |
5625 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
5626 | * detection. | |
5627 | * | |
5628 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 5629 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 5630 | * |
c751ce4f | 5631 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
5632 | * configured for it. In the future, it could choose to temporarily disable |
5633 | * some outputs to free up a pipe for its use. | |
5634 | * | |
5635 | * \return crtc, or NULL if no pipes are available. | |
5636 | */ | |
5637 | ||
5638 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
5639 | static struct drm_display_mode load_detect_mode = { | |
5640 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
5641 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
5642 | }; | |
5643 | ||
d2dff872 CW |
5644 | static struct drm_framebuffer * |
5645 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 5646 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
5647 | struct drm_i915_gem_object *obj) |
5648 | { | |
5649 | struct intel_framebuffer *intel_fb; | |
5650 | int ret; | |
5651 | ||
5652 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
5653 | if (!intel_fb) { | |
5654 | drm_gem_object_unreference_unlocked(&obj->base); | |
5655 | return ERR_PTR(-ENOMEM); | |
5656 | } | |
5657 | ||
5658 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
5659 | if (ret) { | |
5660 | drm_gem_object_unreference_unlocked(&obj->base); | |
5661 | kfree(intel_fb); | |
5662 | return ERR_PTR(ret); | |
5663 | } | |
5664 | ||
5665 | return &intel_fb->base; | |
5666 | } | |
5667 | ||
5668 | static u32 | |
5669 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
5670 | { | |
5671 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
5672 | return ALIGN(pitch, 64); | |
5673 | } | |
5674 | ||
5675 | static u32 | |
5676 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
5677 | { | |
5678 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
5679 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
5680 | } | |
5681 | ||
5682 | static struct drm_framebuffer * | |
5683 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
5684 | struct drm_display_mode *mode, | |
5685 | int depth, int bpp) | |
5686 | { | |
5687 | struct drm_i915_gem_object *obj; | |
308e5bcb | 5688 | struct drm_mode_fb_cmd2 mode_cmd; |
d2dff872 CW |
5689 | |
5690 | obj = i915_gem_alloc_object(dev, | |
5691 | intel_framebuffer_size_for_mode(mode, bpp)); | |
5692 | if (obj == NULL) | |
5693 | return ERR_PTR(-ENOMEM); | |
5694 | ||
5695 | mode_cmd.width = mode->hdisplay; | |
5696 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
5697 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
5698 | bpp); | |
5ca0c34a | 5699 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
5700 | |
5701 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
5702 | } | |
5703 | ||
5704 | static struct drm_framebuffer * | |
5705 | mode_fits_in_fbdev(struct drm_device *dev, | |
5706 | struct drm_display_mode *mode) | |
5707 | { | |
5708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5709 | struct drm_i915_gem_object *obj; | |
5710 | struct drm_framebuffer *fb; | |
5711 | ||
5712 | if (dev_priv->fbdev == NULL) | |
5713 | return NULL; | |
5714 | ||
5715 | obj = dev_priv->fbdev->ifb.obj; | |
5716 | if (obj == NULL) | |
5717 | return NULL; | |
5718 | ||
5719 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
5720 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
5721 | fb->bits_per_pixel)) | |
d2dff872 CW |
5722 | return NULL; |
5723 | ||
01f2c773 | 5724 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
5725 | return NULL; |
5726 | ||
5727 | return fb; | |
5728 | } | |
5729 | ||
d2434ab7 | 5730 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 5731 | struct drm_display_mode *mode, |
8261b191 | 5732 | struct intel_load_detect_pipe *old) |
79e53945 JB |
5733 | { |
5734 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
5735 | struct intel_encoder *intel_encoder = |
5736 | intel_attached_encoder(connector); | |
79e53945 | 5737 | struct drm_crtc *possible_crtc; |
4ef69c7a | 5738 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
5739 | struct drm_crtc *crtc = NULL; |
5740 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 5741 | struct drm_framebuffer *fb; |
79e53945 JB |
5742 | int i = -1; |
5743 | ||
d2dff872 CW |
5744 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5745 | connector->base.id, drm_get_connector_name(connector), | |
5746 | encoder->base.id, drm_get_encoder_name(encoder)); | |
5747 | ||
79e53945 JB |
5748 | /* |
5749 | * Algorithm gets a little messy: | |
7a5e4805 | 5750 | * |
79e53945 JB |
5751 | * - if the connector already has an assigned crtc, use it (but make |
5752 | * sure it's on first) | |
7a5e4805 | 5753 | * |
79e53945 JB |
5754 | * - try to find the first unused crtc that can drive this connector, |
5755 | * and use that if we find one | |
79e53945 JB |
5756 | */ |
5757 | ||
5758 | /* See if we already have a CRTC for this connector */ | |
5759 | if (encoder->crtc) { | |
5760 | crtc = encoder->crtc; | |
8261b191 | 5761 | |
24218aac | 5762 | old->dpms_mode = connector->dpms; |
8261b191 CW |
5763 | old->load_detect_temp = false; |
5764 | ||
5765 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
5766 | if (connector->dpms != DRM_MODE_DPMS_ON) |
5767 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 5768 | |
7173188d | 5769 | return true; |
79e53945 JB |
5770 | } |
5771 | ||
5772 | /* Find an unused one (if possible) */ | |
5773 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
5774 | i++; | |
5775 | if (!(encoder->possible_crtcs & (1 << i))) | |
5776 | continue; | |
5777 | if (!possible_crtc->enabled) { | |
5778 | crtc = possible_crtc; | |
5779 | break; | |
5780 | } | |
79e53945 JB |
5781 | } |
5782 | ||
5783 | /* | |
5784 | * If we didn't find an unused CRTC, don't use any. | |
5785 | */ | |
5786 | if (!crtc) { | |
7173188d CW |
5787 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
5788 | return false; | |
79e53945 JB |
5789 | } |
5790 | ||
fc303101 DV |
5791 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
5792 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
5793 | |
5794 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 5795 | old->dpms_mode = connector->dpms; |
8261b191 | 5796 | old->load_detect_temp = true; |
d2dff872 | 5797 | old->release_fb = NULL; |
79e53945 | 5798 | |
6492711d CW |
5799 | if (!mode) |
5800 | mode = &load_detect_mode; | |
79e53945 | 5801 | |
d2dff872 CW |
5802 | /* We need a framebuffer large enough to accommodate all accesses |
5803 | * that the plane may generate whilst we perform load detection. | |
5804 | * We can not rely on the fbcon either being present (we get called | |
5805 | * during its initialisation to detect all boot displays, or it may | |
5806 | * not even exist) or that it is large enough to satisfy the | |
5807 | * requested mode. | |
5808 | */ | |
94352cf9 DV |
5809 | fb = mode_fits_in_fbdev(dev, mode); |
5810 | if (fb == NULL) { | |
d2dff872 | 5811 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
5812 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
5813 | old->release_fb = fb; | |
d2dff872 CW |
5814 | } else |
5815 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 5816 | if (IS_ERR(fb)) { |
d2dff872 | 5817 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
24218aac | 5818 | goto fail; |
79e53945 | 5819 | } |
79e53945 | 5820 | |
94352cf9 | 5821 | if (!intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 5822 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
5823 | if (old->release_fb) |
5824 | old->release_fb->funcs->destroy(old->release_fb); | |
24218aac | 5825 | goto fail; |
79e53945 | 5826 | } |
7173188d | 5827 | |
79e53945 | 5828 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 5829 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 5830 | |
7173188d | 5831 | return true; |
24218aac DV |
5832 | fail: |
5833 | connector->encoder = NULL; | |
5834 | encoder->crtc = NULL; | |
24218aac | 5835 | return false; |
79e53945 JB |
5836 | } |
5837 | ||
d2434ab7 | 5838 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 5839 | struct intel_load_detect_pipe *old) |
79e53945 | 5840 | { |
d2434ab7 DV |
5841 | struct intel_encoder *intel_encoder = |
5842 | intel_attached_encoder(connector); | |
4ef69c7a | 5843 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 | 5844 | |
d2dff872 CW |
5845 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5846 | connector->base.id, drm_get_connector_name(connector), | |
5847 | encoder->base.id, drm_get_encoder_name(encoder)); | |
5848 | ||
8261b191 | 5849 | if (old->load_detect_temp) { |
fc303101 DV |
5850 | struct drm_crtc *crtc = encoder->crtc; |
5851 | ||
5852 | to_intel_connector(connector)->new_encoder = NULL; | |
5853 | intel_encoder->new_crtc = NULL; | |
5854 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 CW |
5855 | |
5856 | if (old->release_fb) | |
5857 | old->release_fb->funcs->destroy(old->release_fb); | |
5858 | ||
0622a53c | 5859 | return; |
79e53945 JB |
5860 | } |
5861 | ||
c751ce4f | 5862 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
5863 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
5864 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
5865 | } |
5866 | ||
5867 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
5868 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
5869 | { | |
5870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5872 | int pipe = intel_crtc->pipe; | |
548f245b | 5873 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
5874 | u32 fp; |
5875 | intel_clock_t clock; | |
5876 | ||
5877 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 5878 | fp = I915_READ(FP0(pipe)); |
79e53945 | 5879 | else |
39adb7a5 | 5880 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
5881 | |
5882 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
5883 | if (IS_PINEVIEW(dev)) { |
5884 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
5885 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
5886 | } else { |
5887 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
5888 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
5889 | } | |
5890 | ||
a6c45cf0 | 5891 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
5892 | if (IS_PINEVIEW(dev)) |
5893 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
5894 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
5895 | else |
5896 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
5897 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5898 | ||
5899 | switch (dpll & DPLL_MODE_MASK) { | |
5900 | case DPLLB_MODE_DAC_SERIAL: | |
5901 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
5902 | 5 : 10; | |
5903 | break; | |
5904 | case DPLLB_MODE_LVDS: | |
5905 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
5906 | 7 : 14; | |
5907 | break; | |
5908 | default: | |
28c97730 | 5909 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
5910 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
5911 | return 0; | |
5912 | } | |
5913 | ||
5914 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 5915 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
5916 | } else { |
5917 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
5918 | ||
5919 | if (is_lvds) { | |
5920 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
5921 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
5922 | clock.p2 = 14; | |
5923 | ||
5924 | if ((dpll & PLL_REF_INPUT_MASK) == | |
5925 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
5926 | /* XXX: might not be 66MHz */ | |
2177832f | 5927 | intel_clock(dev, 66000, &clock); |
79e53945 | 5928 | } else |
2177832f | 5929 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5930 | } else { |
5931 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
5932 | clock.p1 = 2; | |
5933 | else { | |
5934 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
5935 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
5936 | } | |
5937 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
5938 | clock.p2 = 4; | |
5939 | else | |
5940 | clock.p2 = 2; | |
5941 | ||
2177832f | 5942 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5943 | } |
5944 | } | |
5945 | ||
5946 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
5947 | * i830PllIsValid() because it relies on the xf86_config connector | |
5948 | * configuration being accurate, which it isn't necessarily. | |
5949 | */ | |
5950 | ||
5951 | return clock.dot; | |
5952 | } | |
5953 | ||
5954 | /** Returns the currently programmed mode of the given pipe. */ | |
5955 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
5956 | struct drm_crtc *crtc) | |
5957 | { | |
548f245b | 5958 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
5959 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5960 | int pipe = intel_crtc->pipe; | |
5961 | struct drm_display_mode *mode; | |
548f245b JB |
5962 | int htot = I915_READ(HTOTAL(pipe)); |
5963 | int hsync = I915_READ(HSYNC(pipe)); | |
5964 | int vtot = I915_READ(VTOTAL(pipe)); | |
5965 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
5966 | |
5967 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
5968 | if (!mode) | |
5969 | return NULL; | |
5970 | ||
5971 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
5972 | mode->hdisplay = (htot & 0xffff) + 1; | |
5973 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
5974 | mode->hsync_start = (hsync & 0xffff) + 1; | |
5975 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
5976 | mode->vdisplay = (vtot & 0xffff) + 1; | |
5977 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
5978 | mode->vsync_start = (vsync & 0xffff) + 1; | |
5979 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
5980 | ||
5981 | drm_mode_set_name(mode); | |
79e53945 JB |
5982 | |
5983 | return mode; | |
5984 | } | |
5985 | ||
3dec0095 | 5986 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
5987 | { |
5988 | struct drm_device *dev = crtc->dev; | |
5989 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5991 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
5992 | int dpll_reg = DPLL(pipe); |
5993 | int dpll; | |
652c393a | 5994 | |
bad720ff | 5995 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5996 | return; |
5997 | ||
5998 | if (!dev_priv->lvds_downclock_avail) | |
5999 | return; | |
6000 | ||
dbdc6479 | 6001 | dpll = I915_READ(dpll_reg); |
652c393a | 6002 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6003 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 6004 | |
8ac5a6d5 | 6005 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
6006 | |
6007 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6008 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6009 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6010 | |
652c393a JB |
6011 | dpll = I915_READ(dpll_reg); |
6012 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6013 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 6014 | } |
652c393a JB |
6015 | } |
6016 | ||
6017 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6018 | { | |
6019 | struct drm_device *dev = crtc->dev; | |
6020 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6021 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 6022 | |
bad720ff | 6023 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6024 | return; |
6025 | ||
6026 | if (!dev_priv->lvds_downclock_avail) | |
6027 | return; | |
6028 | ||
6029 | /* | |
6030 | * Since this is called by a timer, we should never get here in | |
6031 | * the manual case. | |
6032 | */ | |
6033 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
6034 | int pipe = intel_crtc->pipe; |
6035 | int dpll_reg = DPLL(pipe); | |
6036 | int dpll; | |
f6e5b160 | 6037 | |
44d98a61 | 6038 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 6039 | |
8ac5a6d5 | 6040 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 6041 | |
dc257cf1 | 6042 | dpll = I915_READ(dpll_reg); |
652c393a JB |
6043 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
6044 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6045 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6046 | dpll = I915_READ(dpll_reg); |
6047 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6048 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6049 | } |
6050 | ||
6051 | } | |
6052 | ||
f047e395 CW |
6053 | void intel_mark_busy(struct drm_device *dev) |
6054 | { | |
f047e395 CW |
6055 | i915_update_gfx_val(dev->dev_private); |
6056 | } | |
6057 | ||
6058 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 6059 | { |
f047e395 CW |
6060 | } |
6061 | ||
6062 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) | |
6063 | { | |
6064 | struct drm_device *dev = obj->base.dev; | |
652c393a | 6065 | struct drm_crtc *crtc; |
652c393a JB |
6066 | |
6067 | if (!i915_powersave) | |
6068 | return; | |
6069 | ||
652c393a | 6070 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
6071 | if (!crtc->fb) |
6072 | continue; | |
6073 | ||
f047e395 CW |
6074 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6075 | intel_increase_pllclock(crtc); | |
652c393a | 6076 | } |
652c393a JB |
6077 | } |
6078 | ||
f047e395 | 6079 | void intel_mark_fb_idle(struct drm_i915_gem_object *obj) |
652c393a | 6080 | { |
f047e395 CW |
6081 | struct drm_device *dev = obj->base.dev; |
6082 | struct drm_crtc *crtc; | |
652c393a | 6083 | |
f047e395 | 6084 | if (!i915_powersave) |
acb87dfb CW |
6085 | return; |
6086 | ||
652c393a JB |
6087 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6088 | if (!crtc->fb) | |
6089 | continue; | |
6090 | ||
f047e395 CW |
6091 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6092 | intel_decrease_pllclock(crtc); | |
652c393a JB |
6093 | } |
6094 | } | |
6095 | ||
79e53945 JB |
6096 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6097 | { | |
6098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6099 | struct drm_device *dev = crtc->dev; |
6100 | struct intel_unpin_work *work; | |
6101 | unsigned long flags; | |
6102 | ||
6103 | spin_lock_irqsave(&dev->event_lock, flags); | |
6104 | work = intel_crtc->unpin_work; | |
6105 | intel_crtc->unpin_work = NULL; | |
6106 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6107 | ||
6108 | if (work) { | |
6109 | cancel_work_sync(&work->work); | |
6110 | kfree(work); | |
6111 | } | |
79e53945 JB |
6112 | |
6113 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6114 | |
79e53945 JB |
6115 | kfree(intel_crtc); |
6116 | } | |
6117 | ||
6b95a207 KH |
6118 | static void intel_unpin_work_fn(struct work_struct *__work) |
6119 | { | |
6120 | struct intel_unpin_work *work = | |
6121 | container_of(__work, struct intel_unpin_work, work); | |
6122 | ||
6123 | mutex_lock(&work->dev->struct_mutex); | |
1690e1eb | 6124 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
6125 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6126 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6127 | |
7782de3b | 6128 | intel_update_fbc(work->dev); |
6b95a207 KH |
6129 | mutex_unlock(&work->dev->struct_mutex); |
6130 | kfree(work); | |
6131 | } | |
6132 | ||
1afe3e9d | 6133 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6134 | struct drm_crtc *crtc) |
6b95a207 KH |
6135 | { |
6136 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6137 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6138 | struct intel_unpin_work *work; | |
05394f39 | 6139 | struct drm_i915_gem_object *obj; |
6b95a207 | 6140 | struct drm_pending_vblank_event *e; |
49b14a5c | 6141 | struct timeval tnow, tvbl; |
6b95a207 KH |
6142 | unsigned long flags; |
6143 | ||
6144 | /* Ignore early vblank irqs */ | |
6145 | if (intel_crtc == NULL) | |
6146 | return; | |
6147 | ||
49b14a5c MK |
6148 | do_gettimeofday(&tnow); |
6149 | ||
6b95a207 KH |
6150 | spin_lock_irqsave(&dev->event_lock, flags); |
6151 | work = intel_crtc->unpin_work; | |
6152 | if (work == NULL || !work->pending) { | |
6153 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6154 | return; | |
6155 | } | |
6156 | ||
6157 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
6158 | |
6159 | if (work->event) { | |
6160 | e = work->event; | |
49b14a5c | 6161 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
6162 | |
6163 | /* Called before vblank count and timestamps have | |
6164 | * been updated for the vblank interval of flip | |
6165 | * completion? Need to increment vblank count and | |
6166 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
6167 | * to account for this. We assume this happened if we |
6168 | * get called over 0.9 frame durations after the last | |
6169 | * timestamped vblank. | |
6170 | * | |
6171 | * This calculation can not be used with vrefresh rates | |
6172 | * below 5Hz (10Hz to be on the safe side) without | |
6173 | * promoting to 64 integers. | |
0af7e4df | 6174 | */ |
49b14a5c MK |
6175 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
6176 | 9 * crtc->framedur_ns) { | |
0af7e4df | 6177 | e->event.sequence++; |
49b14a5c MK |
6178 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
6179 | crtc->framedur_ns); | |
0af7e4df MK |
6180 | } |
6181 | ||
49b14a5c MK |
6182 | e->event.tv_sec = tvbl.tv_sec; |
6183 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 6184 | |
6b95a207 KH |
6185 | list_add_tail(&e->base.link, |
6186 | &e->base.file_priv->event_list); | |
6187 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
6188 | } | |
6189 | ||
0af7e4df MK |
6190 | drm_vblank_put(dev, intel_crtc->pipe); |
6191 | ||
6b95a207 KH |
6192 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6193 | ||
05394f39 | 6194 | obj = work->old_fb_obj; |
d9e86c0e | 6195 | |
e59f2bac | 6196 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
6197 | &obj->pending_flip.counter); |
6198 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 6199 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 6200 | |
6b95a207 | 6201 | schedule_work(&work->work); |
e5510fac JB |
6202 | |
6203 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6204 | } |
6205 | ||
1afe3e9d JB |
6206 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6207 | { | |
6208 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6209 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6210 | ||
49b14a5c | 6211 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6212 | } |
6213 | ||
6214 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6215 | { | |
6216 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6217 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6218 | ||
49b14a5c | 6219 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6220 | } |
6221 | ||
6b95a207 KH |
6222 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6223 | { | |
6224 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6225 | struct intel_crtc *intel_crtc = | |
6226 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6227 | unsigned long flags; | |
6228 | ||
6229 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 6230 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
6231 | if ((++intel_crtc->unpin_work->pending) > 1) |
6232 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
6233 | } else { |
6234 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
6235 | } | |
6b95a207 KH |
6236 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6237 | } | |
6238 | ||
8c9f3aaf JB |
6239 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6240 | struct drm_crtc *crtc, | |
6241 | struct drm_framebuffer *fb, | |
6242 | struct drm_i915_gem_object *obj) | |
6243 | { | |
6244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6245 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6246 | u32 flip_mask; |
6d90c952 | 6247 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6248 | int ret; |
6249 | ||
6d90c952 | 6250 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6251 | if (ret) |
83d4092b | 6252 | goto err; |
8c9f3aaf | 6253 | |
6d90c952 | 6254 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6255 | if (ret) |
83d4092b | 6256 | goto err_unpin; |
8c9f3aaf JB |
6257 | |
6258 | /* Can't queue multiple flips, so wait for the previous | |
6259 | * one to finish before executing the next. | |
6260 | */ | |
6261 | if (intel_crtc->plane) | |
6262 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6263 | else | |
6264 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6265 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6266 | intel_ring_emit(ring, MI_NOOP); | |
6267 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
6268 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6269 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6270 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6271 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
6272 | intel_ring_advance(ring); | |
83d4092b CW |
6273 | return 0; |
6274 | ||
6275 | err_unpin: | |
6276 | intel_unpin_fb_obj(obj); | |
6277 | err: | |
8c9f3aaf JB |
6278 | return ret; |
6279 | } | |
6280 | ||
6281 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
6282 | struct drm_crtc *crtc, | |
6283 | struct drm_framebuffer *fb, | |
6284 | struct drm_i915_gem_object *obj) | |
6285 | { | |
6286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6287 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6288 | u32 flip_mask; |
6d90c952 | 6289 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6290 | int ret; |
6291 | ||
6d90c952 | 6292 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6293 | if (ret) |
83d4092b | 6294 | goto err; |
8c9f3aaf | 6295 | |
6d90c952 | 6296 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6297 | if (ret) |
83d4092b | 6298 | goto err_unpin; |
8c9f3aaf JB |
6299 | |
6300 | if (intel_crtc->plane) | |
6301 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6302 | else | |
6303 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6304 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6305 | intel_ring_emit(ring, MI_NOOP); | |
6306 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
6307 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6308 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6309 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6310 | intel_ring_emit(ring, MI_NOOP); |
6311 | ||
6312 | intel_ring_advance(ring); | |
83d4092b CW |
6313 | return 0; |
6314 | ||
6315 | err_unpin: | |
6316 | intel_unpin_fb_obj(obj); | |
6317 | err: | |
8c9f3aaf JB |
6318 | return ret; |
6319 | } | |
6320 | ||
6321 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
6322 | struct drm_crtc *crtc, | |
6323 | struct drm_framebuffer *fb, | |
6324 | struct drm_i915_gem_object *obj) | |
6325 | { | |
6326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6328 | uint32_t pf, pipesrc; | |
6d90c952 | 6329 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6330 | int ret; |
6331 | ||
6d90c952 | 6332 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6333 | if (ret) |
83d4092b | 6334 | goto err; |
8c9f3aaf | 6335 | |
6d90c952 | 6336 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 6337 | if (ret) |
83d4092b | 6338 | goto err_unpin; |
8c9f3aaf JB |
6339 | |
6340 | /* i965+ uses the linear or tiled offsets from the | |
6341 | * Display Registers (which do not change across a page-flip) | |
6342 | * so we need only reprogram the base address. | |
6343 | */ | |
6d90c952 DV |
6344 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6345 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6346 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 DV |
6347 | intel_ring_emit(ring, |
6348 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | | |
6349 | obj->tiling_mode); | |
8c9f3aaf JB |
6350 | |
6351 | /* XXX Enabling the panel-fitter across page-flip is so far | |
6352 | * untested on non-native modes, so ignore it for now. | |
6353 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
6354 | */ | |
6355 | pf = 0; | |
6356 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 DV |
6357 | intel_ring_emit(ring, pf | pipesrc); |
6358 | intel_ring_advance(ring); | |
83d4092b CW |
6359 | return 0; |
6360 | ||
6361 | err_unpin: | |
6362 | intel_unpin_fb_obj(obj); | |
6363 | err: | |
8c9f3aaf JB |
6364 | return ret; |
6365 | } | |
6366 | ||
6367 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
6368 | struct drm_crtc *crtc, | |
6369 | struct drm_framebuffer *fb, | |
6370 | struct drm_i915_gem_object *obj) | |
6371 | { | |
6372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 6374 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6375 | uint32_t pf, pipesrc; |
6376 | int ret; | |
6377 | ||
6d90c952 | 6378 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6379 | if (ret) |
83d4092b | 6380 | goto err; |
8c9f3aaf | 6381 | |
6d90c952 | 6382 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 6383 | if (ret) |
83d4092b | 6384 | goto err_unpin; |
8c9f3aaf | 6385 | |
6d90c952 DV |
6386 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6387 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6388 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
c2c75131 | 6389 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
8c9f3aaf | 6390 | |
dc257cf1 DV |
6391 | /* Contrary to the suggestions in the documentation, |
6392 | * "Enable Panel Fitter" does not seem to be required when page | |
6393 | * flipping with a non-native mode, and worse causes a normal | |
6394 | * modeset to fail. | |
6395 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
6396 | */ | |
6397 | pf = 0; | |
8c9f3aaf | 6398 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 DV |
6399 | intel_ring_emit(ring, pf | pipesrc); |
6400 | intel_ring_advance(ring); | |
83d4092b CW |
6401 | return 0; |
6402 | ||
6403 | err_unpin: | |
6404 | intel_unpin_fb_obj(obj); | |
6405 | err: | |
8c9f3aaf JB |
6406 | return ret; |
6407 | } | |
6408 | ||
7c9017e5 JB |
6409 | /* |
6410 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
6411 | * the render ring doesn't give us interrpts for page flip completion, which | |
6412 | * means clients will hang after the first flip is queued. Fortunately the | |
6413 | * blit ring generates interrupts properly, so use it instead. | |
6414 | */ | |
6415 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
6416 | struct drm_crtc *crtc, | |
6417 | struct drm_framebuffer *fb, | |
6418 | struct drm_i915_gem_object *obj) | |
6419 | { | |
6420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6422 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
cb05d8de | 6423 | uint32_t plane_bit = 0; |
7c9017e5 JB |
6424 | int ret; |
6425 | ||
6426 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
6427 | if (ret) | |
83d4092b | 6428 | goto err; |
7c9017e5 | 6429 | |
cb05d8de DV |
6430 | switch(intel_crtc->plane) { |
6431 | case PLANE_A: | |
6432 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
6433 | break; | |
6434 | case PLANE_B: | |
6435 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
6436 | break; | |
6437 | case PLANE_C: | |
6438 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
6439 | break; | |
6440 | default: | |
6441 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
6442 | ret = -ENODEV; | |
ab3951eb | 6443 | goto err_unpin; |
cb05d8de DV |
6444 | } |
6445 | ||
7c9017e5 JB |
6446 | ret = intel_ring_begin(ring, 4); |
6447 | if (ret) | |
83d4092b | 6448 | goto err_unpin; |
7c9017e5 | 6449 | |
cb05d8de | 6450 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 6451 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
c2c75131 | 6452 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
7c9017e5 JB |
6453 | intel_ring_emit(ring, (MI_NOOP)); |
6454 | intel_ring_advance(ring); | |
83d4092b CW |
6455 | return 0; |
6456 | ||
6457 | err_unpin: | |
6458 | intel_unpin_fb_obj(obj); | |
6459 | err: | |
7c9017e5 JB |
6460 | return ret; |
6461 | } | |
6462 | ||
8c9f3aaf JB |
6463 | static int intel_default_queue_flip(struct drm_device *dev, |
6464 | struct drm_crtc *crtc, | |
6465 | struct drm_framebuffer *fb, | |
6466 | struct drm_i915_gem_object *obj) | |
6467 | { | |
6468 | return -ENODEV; | |
6469 | } | |
6470 | ||
6b95a207 KH |
6471 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
6472 | struct drm_framebuffer *fb, | |
6473 | struct drm_pending_vblank_event *event) | |
6474 | { | |
6475 | struct drm_device *dev = crtc->dev; | |
6476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6477 | struct intel_framebuffer *intel_fb; | |
05394f39 | 6478 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
6479 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6480 | struct intel_unpin_work *work; | |
8c9f3aaf | 6481 | unsigned long flags; |
52e68630 | 6482 | int ret; |
6b95a207 | 6483 | |
e6a595d2 VS |
6484 | /* Can't change pixel format via MI display flips. */ |
6485 | if (fb->pixel_format != crtc->fb->pixel_format) | |
6486 | return -EINVAL; | |
6487 | ||
6488 | /* | |
6489 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
6490 | * Note that pitch changes could also affect these register. | |
6491 | */ | |
6492 | if (INTEL_INFO(dev)->gen > 3 && | |
6493 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
6494 | fb->pitches[0] != crtc->fb->pitches[0])) | |
6495 | return -EINVAL; | |
6496 | ||
6b95a207 KH |
6497 | work = kzalloc(sizeof *work, GFP_KERNEL); |
6498 | if (work == NULL) | |
6499 | return -ENOMEM; | |
6500 | ||
6b95a207 KH |
6501 | work->event = event; |
6502 | work->dev = crtc->dev; | |
6503 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 6504 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
6505 | INIT_WORK(&work->work, intel_unpin_work_fn); |
6506 | ||
7317c75e JB |
6507 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
6508 | if (ret) | |
6509 | goto free_work; | |
6510 | ||
6b95a207 KH |
6511 | /* We borrow the event spin lock for protecting unpin_work */ |
6512 | spin_lock_irqsave(&dev->event_lock, flags); | |
6513 | if (intel_crtc->unpin_work) { | |
6514 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6515 | kfree(work); | |
7317c75e | 6516 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
6517 | |
6518 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
6519 | return -EBUSY; |
6520 | } | |
6521 | intel_crtc->unpin_work = work; | |
6522 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6523 | ||
6524 | intel_fb = to_intel_framebuffer(fb); | |
6525 | obj = intel_fb->obj; | |
6526 | ||
79158103 CW |
6527 | ret = i915_mutex_lock_interruptible(dev); |
6528 | if (ret) | |
6529 | goto cleanup; | |
6b95a207 | 6530 | |
75dfca80 | 6531 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
6532 | drm_gem_object_reference(&work->old_fb_obj->base); |
6533 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
6534 | |
6535 | crtc->fb = fb; | |
96b099fd | 6536 | |
e1f99ce6 | 6537 | work->pending_flip_obj = obj; |
e1f99ce6 | 6538 | |
4e5359cd SF |
6539 | work->enable_stall_check = true; |
6540 | ||
e1f99ce6 CW |
6541 | /* Block clients from rendering to the new back buffer until |
6542 | * the flip occurs and the object is no longer visible. | |
6543 | */ | |
05394f39 | 6544 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 6545 | |
8c9f3aaf JB |
6546 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
6547 | if (ret) | |
6548 | goto cleanup_pending; | |
6b95a207 | 6549 | |
7782de3b | 6550 | intel_disable_fbc(dev); |
f047e395 | 6551 | intel_mark_fb_busy(obj); |
6b95a207 KH |
6552 | mutex_unlock(&dev->struct_mutex); |
6553 | ||
e5510fac JB |
6554 | trace_i915_flip_request(intel_crtc->plane, obj); |
6555 | ||
6b95a207 | 6556 | return 0; |
96b099fd | 6557 | |
8c9f3aaf JB |
6558 | cleanup_pending: |
6559 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
05394f39 CW |
6560 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6561 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
6562 | mutex_unlock(&dev->struct_mutex); |
6563 | ||
79158103 | 6564 | cleanup: |
96b099fd CW |
6565 | spin_lock_irqsave(&dev->event_lock, flags); |
6566 | intel_crtc->unpin_work = NULL; | |
6567 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6568 | ||
7317c75e JB |
6569 | drm_vblank_put(dev, intel_crtc->pipe); |
6570 | free_work: | |
96b099fd CW |
6571 | kfree(work); |
6572 | ||
6573 | return ret; | |
6b95a207 KH |
6574 | } |
6575 | ||
f6e5b160 | 6576 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
6577 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
6578 | .load_lut = intel_crtc_load_lut, | |
976f8a20 | 6579 | .disable = intel_crtc_noop, |
f6e5b160 CW |
6580 | }; |
6581 | ||
6ed0f796 DV |
6582 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
6583 | { | |
6584 | struct intel_encoder *other_encoder; | |
6585 | struct drm_crtc *crtc = &encoder->new_crtc->base; | |
6586 | ||
6587 | if (WARN_ON(!crtc)) | |
6588 | return false; | |
6589 | ||
6590 | list_for_each_entry(other_encoder, | |
6591 | &crtc->dev->mode_config.encoder_list, | |
6592 | base.head) { | |
6593 | ||
6594 | if (&other_encoder->new_crtc->base != crtc || | |
6595 | encoder == other_encoder) | |
6596 | continue; | |
6597 | else | |
6598 | return true; | |
6599 | } | |
6600 | ||
6601 | return false; | |
6602 | } | |
6603 | ||
50f56119 DV |
6604 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
6605 | struct drm_crtc *crtc) | |
6606 | { | |
6607 | struct drm_device *dev; | |
6608 | struct drm_crtc *tmp; | |
6609 | int crtc_mask = 1; | |
6610 | ||
6611 | WARN(!crtc, "checking null crtc?\n"); | |
6612 | ||
6613 | dev = crtc->dev; | |
6614 | ||
6615 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { | |
6616 | if (tmp == crtc) | |
6617 | break; | |
6618 | crtc_mask <<= 1; | |
6619 | } | |
6620 | ||
6621 | if (encoder->possible_crtcs & crtc_mask) | |
6622 | return true; | |
6623 | return false; | |
6624 | } | |
6625 | ||
9a935856 DV |
6626 | /** |
6627 | * intel_modeset_update_staged_output_state | |
6628 | * | |
6629 | * Updates the staged output configuration state, e.g. after we've read out the | |
6630 | * current hw state. | |
6631 | */ | |
6632 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
6633 | { | |
6634 | struct intel_encoder *encoder; | |
6635 | struct intel_connector *connector; | |
6636 | ||
6637 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
6638 | base.head) { | |
6639 | connector->new_encoder = | |
6640 | to_intel_encoder(connector->base.encoder); | |
6641 | } | |
6642 | ||
6643 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
6644 | base.head) { | |
6645 | encoder->new_crtc = | |
6646 | to_intel_crtc(encoder->base.crtc); | |
6647 | } | |
6648 | } | |
6649 | ||
6650 | /** | |
6651 | * intel_modeset_commit_output_state | |
6652 | * | |
6653 | * This function copies the stage display pipe configuration to the real one. | |
6654 | */ | |
6655 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
6656 | { | |
6657 | struct intel_encoder *encoder; | |
6658 | struct intel_connector *connector; | |
6659 | ||
6660 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
6661 | base.head) { | |
6662 | connector->base.encoder = &connector->new_encoder->base; | |
6663 | } | |
6664 | ||
6665 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
6666 | base.head) { | |
6667 | encoder->base.crtc = &encoder->new_crtc->base; | |
6668 | } | |
6669 | } | |
6670 | ||
7758a113 DV |
6671 | static struct drm_display_mode * |
6672 | intel_modeset_adjusted_mode(struct drm_crtc *crtc, | |
6673 | struct drm_display_mode *mode) | |
6674 | { | |
6675 | struct drm_device *dev = crtc->dev; | |
6676 | struct drm_display_mode *adjusted_mode; | |
6677 | struct drm_encoder_helper_funcs *encoder_funcs; | |
6678 | struct intel_encoder *encoder; | |
6679 | ||
6680 | adjusted_mode = drm_mode_duplicate(dev, mode); | |
6681 | if (!adjusted_mode) | |
6682 | return ERR_PTR(-ENOMEM); | |
6683 | ||
6684 | /* Pass our mode to the connectors and the CRTC to give them a chance to | |
6685 | * adjust it according to limitations or connector properties, and also | |
6686 | * a chance to reject the mode entirely. | |
6687 | */ | |
6688 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
6689 | base.head) { | |
6690 | ||
6691 | if (&encoder->new_crtc->base != crtc) | |
6692 | continue; | |
6693 | encoder_funcs = encoder->base.helper_private; | |
6694 | if (!(encoder_funcs->mode_fixup(&encoder->base, mode, | |
6695 | adjusted_mode))) { | |
6696 | DRM_DEBUG_KMS("Encoder fixup failed\n"); | |
6697 | goto fail; | |
6698 | } | |
6699 | } | |
6700 | ||
6701 | if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { | |
6702 | DRM_DEBUG_KMS("CRTC fixup failed\n"); | |
6703 | goto fail; | |
6704 | } | |
6705 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); | |
6706 | ||
6707 | return adjusted_mode; | |
6708 | fail: | |
6709 | drm_mode_destroy(dev, adjusted_mode); | |
6710 | return ERR_PTR(-EINVAL); | |
6711 | } | |
6712 | ||
e2e1ed41 DV |
6713 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
6714 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
6715 | static void | |
6716 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
6717 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
6718 | { | |
6719 | struct intel_crtc *intel_crtc; | |
6720 | struct drm_device *dev = crtc->dev; | |
6721 | struct intel_encoder *encoder; | |
6722 | struct intel_connector *connector; | |
6723 | struct drm_crtc *tmp_crtc; | |
6724 | ||
6725 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; | |
6726 | ||
6727 | /* Check which crtcs have changed outputs connected to them, these need | |
6728 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
6729 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
6730 | * bit set at most. */ | |
6731 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
6732 | base.head) { | |
6733 | if (connector->base.encoder == &connector->new_encoder->base) | |
6734 | continue; | |
6735 | ||
6736 | if (connector->base.encoder) { | |
6737 | tmp_crtc = connector->base.encoder->crtc; | |
6738 | ||
6739 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
6740 | } | |
6741 | ||
6742 | if (connector->new_encoder) | |
6743 | *prepare_pipes |= | |
6744 | 1 << connector->new_encoder->new_crtc->pipe; | |
6745 | } | |
6746 | ||
6747 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
6748 | base.head) { | |
6749 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
6750 | continue; | |
6751 | ||
6752 | if (encoder->base.crtc) { | |
6753 | tmp_crtc = encoder->base.crtc; | |
6754 | ||
6755 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
6756 | } | |
6757 | ||
6758 | if (encoder->new_crtc) | |
6759 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
6760 | } | |
6761 | ||
6762 | /* Check for any pipes that will be fully disabled ... */ | |
6763 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
6764 | base.head) { | |
6765 | bool used = false; | |
6766 | ||
6767 | /* Don't try to disable disabled crtcs. */ | |
6768 | if (!intel_crtc->base.enabled) | |
6769 | continue; | |
6770 | ||
6771 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
6772 | base.head) { | |
6773 | if (encoder->new_crtc == intel_crtc) | |
6774 | used = true; | |
6775 | } | |
6776 | ||
6777 | if (!used) | |
6778 | *disable_pipes |= 1 << intel_crtc->pipe; | |
6779 | } | |
6780 | ||
6781 | ||
6782 | /* set_mode is also used to update properties on life display pipes. */ | |
6783 | intel_crtc = to_intel_crtc(crtc); | |
6784 | if (crtc->enabled) | |
6785 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
6786 | ||
6787 | /* We only support modeset on one single crtc, hence we need to do that | |
6788 | * only for the passed in crtc iff we change anything else than just | |
6789 | * disable crtcs. | |
6790 | * | |
6791 | * This is actually not true, to be fully compatible with the old crtc | |
6792 | * helper we automatically disable _any_ output (i.e. doesn't need to be | |
6793 | * connected to the crtc we're modesetting on) if it's disconnected. | |
6794 | * Which is a rather nutty api (since changed the output configuration | |
6795 | * without userspace's explicit request can lead to confusion), but | |
6796 | * alas. Hence we currently need to modeset on all pipes we prepare. */ | |
6797 | if (*prepare_pipes) | |
6798 | *modeset_pipes = *prepare_pipes; | |
6799 | ||
6800 | /* ... and mask these out. */ | |
6801 | *modeset_pipes &= ~(*disable_pipes); | |
6802 | *prepare_pipes &= ~(*disable_pipes); | |
6803 | } | |
6804 | ||
ea9d758d DV |
6805 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
6806 | { | |
6807 | struct drm_encoder *encoder; | |
6808 | struct drm_device *dev = crtc->dev; | |
6809 | ||
6810 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) | |
6811 | if (encoder->crtc == crtc) | |
6812 | return true; | |
6813 | ||
6814 | return false; | |
6815 | } | |
6816 | ||
6817 | static void | |
6818 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
6819 | { | |
6820 | struct intel_encoder *intel_encoder; | |
6821 | struct intel_crtc *intel_crtc; | |
6822 | struct drm_connector *connector; | |
6823 | ||
6824 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
6825 | base.head) { | |
6826 | if (!intel_encoder->base.crtc) | |
6827 | continue; | |
6828 | ||
6829 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
6830 | ||
6831 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
6832 | intel_encoder->connectors_active = false; | |
6833 | } | |
6834 | ||
6835 | intel_modeset_commit_output_state(dev); | |
6836 | ||
6837 | /* Update computed state. */ | |
6838 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
6839 | base.head) { | |
6840 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
6841 | } | |
6842 | ||
6843 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6844 | if (!connector->encoder || !connector->encoder->crtc) | |
6845 | continue; | |
6846 | ||
6847 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
6848 | ||
6849 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
6850 | connector->dpms = DRM_MODE_DPMS_ON; | |
6851 | ||
6852 | intel_encoder = to_intel_encoder(connector->encoder); | |
6853 | intel_encoder->connectors_active = true; | |
6854 | } | |
6855 | } | |
6856 | ||
6857 | } | |
6858 | ||
25c5b266 DV |
6859 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
6860 | list_for_each_entry((intel_crtc), \ | |
6861 | &(dev)->mode_config.crtc_list, \ | |
6862 | base.head) \ | |
6863 | if (mask & (1 <<(intel_crtc)->pipe)) \ | |
6864 | ||
a6778b3c DV |
6865 | bool intel_set_mode(struct drm_crtc *crtc, |
6866 | struct drm_display_mode *mode, | |
94352cf9 | 6867 | int x, int y, struct drm_framebuffer *fb) |
a6778b3c DV |
6868 | { |
6869 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 6870 | drm_i915_private_t *dev_priv = dev->dev_private; |
a6778b3c | 6871 | struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode; |
a6778b3c | 6872 | struct drm_encoder_helper_funcs *encoder_funcs; |
a6778b3c | 6873 | struct drm_encoder *encoder; |
25c5b266 DV |
6874 | struct intel_crtc *intel_crtc; |
6875 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
a6778b3c DV |
6876 | bool ret = true; |
6877 | ||
e2e1ed41 | 6878 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
6879 | &prepare_pipes, &disable_pipes); |
6880 | ||
6881 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
6882 | modeset_pipes, prepare_pipes, disable_pipes); | |
e2e1ed41 | 6883 | |
976f8a20 DV |
6884 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
6885 | intel_crtc_disable(&intel_crtc->base); | |
87f1faa6 | 6886 | |
a6778b3c DV |
6887 | saved_hwmode = crtc->hwmode; |
6888 | saved_mode = crtc->mode; | |
a6778b3c | 6889 | |
25c5b266 DV |
6890 | /* Hack: Because we don't (yet) support global modeset on multiple |
6891 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
6892 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
6893 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
6894 | * changing their mode at the same time. */ | |
6895 | adjusted_mode = NULL; | |
6896 | if (modeset_pipes) { | |
6897 | adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); | |
6898 | if (IS_ERR(adjusted_mode)) { | |
6899 | return false; | |
6900 | } | |
25c5b266 | 6901 | } |
a6778b3c | 6902 | |
ea9d758d DV |
6903 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
6904 | if (intel_crtc->base.enabled) | |
6905 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
6906 | } | |
a6778b3c | 6907 | |
25c5b266 DV |
6908 | if (modeset_pipes) { |
6909 | crtc->mode = *mode; | |
6910 | crtc->x = x; | |
6911 | crtc->y = y; | |
6912 | } | |
7758a113 | 6913 | |
ea9d758d DV |
6914 | /* Only after disabling all output pipelines that will be changed can we |
6915 | * update the the output configuration. */ | |
6916 | intel_modeset_update_state(dev, prepare_pipes); | |
6917 | ||
a6778b3c DV |
6918 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
6919 | * on the DPLL. | |
6920 | */ | |
25c5b266 DV |
6921 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
6922 | ret = !intel_crtc_mode_set(&intel_crtc->base, | |
6923 | mode, adjusted_mode, | |
6924 | x, y, fb); | |
6925 | if (!ret) | |
6926 | goto done; | |
a6778b3c | 6927 | |
25c5b266 | 6928 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
a6778b3c | 6929 | |
25c5b266 DV |
6930 | if (encoder->crtc != &intel_crtc->base) |
6931 | continue; | |
a6778b3c | 6932 | |
25c5b266 DV |
6933 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
6934 | encoder->base.id, drm_get_encoder_name(encoder), | |
6935 | mode->base.id, mode->name); | |
6936 | encoder_funcs = encoder->helper_private; | |
6937 | encoder_funcs->mode_set(encoder, mode, adjusted_mode); | |
6938 | } | |
a6778b3c DV |
6939 | } |
6940 | ||
6941 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
6942 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
6943 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 6944 | |
25c5b266 DV |
6945 | if (modeset_pipes) { |
6946 | /* Store real post-adjustment hardware mode. */ | |
6947 | crtc->hwmode = *adjusted_mode; | |
a6778b3c | 6948 | |
25c5b266 DV |
6949 | /* Calculate and store various constants which |
6950 | * are later needed by vblank and swap-completion | |
6951 | * timestamping. They are derived from true hwmode. | |
6952 | */ | |
6953 | drm_calc_timestamping_constants(crtc); | |
6954 | } | |
a6778b3c DV |
6955 | |
6956 | /* FIXME: add subpixel order */ | |
6957 | done: | |
6958 | drm_mode_destroy(dev, adjusted_mode); | |
25c5b266 | 6959 | if (!ret && crtc->enabled) { |
a6778b3c DV |
6960 | crtc->hwmode = saved_hwmode; |
6961 | crtc->mode = saved_mode; | |
a6778b3c DV |
6962 | } |
6963 | ||
6964 | return ret; | |
6965 | } | |
6966 | ||
25c5b266 DV |
6967 | #undef for_each_intel_crtc_masked |
6968 | ||
d9e55608 DV |
6969 | static void intel_set_config_free(struct intel_set_config *config) |
6970 | { | |
6971 | if (!config) | |
6972 | return; | |
6973 | ||
1aa4b628 DV |
6974 | kfree(config->save_connector_encoders); |
6975 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
6976 | kfree(config); |
6977 | } | |
6978 | ||
85f9eb71 DV |
6979 | static int intel_set_config_save_state(struct drm_device *dev, |
6980 | struct intel_set_config *config) | |
6981 | { | |
85f9eb71 DV |
6982 | struct drm_encoder *encoder; |
6983 | struct drm_connector *connector; | |
6984 | int count; | |
6985 | ||
1aa4b628 DV |
6986 | config->save_encoder_crtcs = |
6987 | kcalloc(dev->mode_config.num_encoder, | |
6988 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
6989 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
6990 | return -ENOMEM; |
6991 | ||
1aa4b628 DV |
6992 | config->save_connector_encoders = |
6993 | kcalloc(dev->mode_config.num_connector, | |
6994 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
6995 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
6996 | return -ENOMEM; |
6997 | ||
6998 | /* Copy data. Note that driver private data is not affected. | |
6999 | * Should anything bad happen only the expected state is | |
7000 | * restored, not the drivers personal bookkeeping. | |
7001 | */ | |
85f9eb71 DV |
7002 | count = 0; |
7003 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 7004 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
7005 | } |
7006 | ||
7007 | count = 0; | |
7008 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 7009 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
7010 | } |
7011 | ||
7012 | return 0; | |
7013 | } | |
7014 | ||
7015 | static void intel_set_config_restore_state(struct drm_device *dev, | |
7016 | struct intel_set_config *config) | |
7017 | { | |
9a935856 DV |
7018 | struct intel_encoder *encoder; |
7019 | struct intel_connector *connector; | |
85f9eb71 DV |
7020 | int count; |
7021 | ||
85f9eb71 | 7022 | count = 0; |
9a935856 DV |
7023 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7024 | encoder->new_crtc = | |
7025 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
7026 | } |
7027 | ||
7028 | count = 0; | |
9a935856 DV |
7029 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
7030 | connector->new_encoder = | |
7031 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
7032 | } |
7033 | } | |
7034 | ||
5e2b584e DV |
7035 | static void |
7036 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
7037 | struct intel_set_config *config) | |
7038 | { | |
7039 | ||
7040 | /* We should be able to check here if the fb has the same properties | |
7041 | * and then just flip_or_move it */ | |
7042 | if (set->crtc->fb != set->fb) { | |
7043 | /* If we have no fb then treat it as a full mode set */ | |
7044 | if (set->crtc->fb == NULL) { | |
7045 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); | |
7046 | config->mode_changed = true; | |
7047 | } else if (set->fb == NULL) { | |
7048 | config->mode_changed = true; | |
7049 | } else if (set->fb->depth != set->crtc->fb->depth) { | |
7050 | config->mode_changed = true; | |
7051 | } else if (set->fb->bits_per_pixel != | |
7052 | set->crtc->fb->bits_per_pixel) { | |
7053 | config->mode_changed = true; | |
7054 | } else | |
7055 | config->fb_changed = true; | |
7056 | } | |
7057 | ||
835c5873 | 7058 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
7059 | config->fb_changed = true; |
7060 | ||
7061 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
7062 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
7063 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
7064 | drm_mode_debug_printmodeline(set->mode); | |
7065 | config->mode_changed = true; | |
7066 | } | |
7067 | } | |
7068 | ||
2e431051 | 7069 | static int |
9a935856 DV |
7070 | intel_modeset_stage_output_state(struct drm_device *dev, |
7071 | struct drm_mode_set *set, | |
7072 | struct intel_set_config *config) | |
50f56119 | 7073 | { |
85f9eb71 | 7074 | struct drm_crtc *new_crtc; |
9a935856 DV |
7075 | struct intel_connector *connector; |
7076 | struct intel_encoder *encoder; | |
2e431051 | 7077 | int count, ro; |
50f56119 | 7078 | |
9a935856 DV |
7079 | /* The upper layers ensure that we either disabl a crtc or have a list |
7080 | * of connectors. For paranoia, double-check this. */ | |
7081 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
7082 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
7083 | ||
50f56119 | 7084 | count = 0; |
9a935856 DV |
7085 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7086 | base.head) { | |
7087 | /* Otherwise traverse passed in connector list and get encoders | |
7088 | * for them. */ | |
50f56119 | 7089 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
7090 | if (set->connectors[ro] == &connector->base) { |
7091 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
7092 | break; |
7093 | } | |
7094 | } | |
7095 | ||
9a935856 DV |
7096 | /* If we disable the crtc, disable all its connectors. Also, if |
7097 | * the connector is on the changing crtc but not on the new | |
7098 | * connector list, disable it. */ | |
7099 | if ((!set->fb || ro == set->num_connectors) && | |
7100 | connector->base.encoder && | |
7101 | connector->base.encoder->crtc == set->crtc) { | |
7102 | connector->new_encoder = NULL; | |
7103 | ||
7104 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
7105 | connector->base.base.id, | |
7106 | drm_get_connector_name(&connector->base)); | |
7107 | } | |
7108 | ||
7109 | ||
7110 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 7111 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 7112 | config->mode_changed = true; |
50f56119 | 7113 | } |
9a935856 DV |
7114 | |
7115 | /* Disable all disconnected encoders. */ | |
7116 | if (connector->base.status == connector_status_disconnected) | |
7117 | connector->new_encoder = NULL; | |
50f56119 | 7118 | } |
9a935856 | 7119 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 7120 | |
9a935856 | 7121 | /* Update crtc of enabled connectors. */ |
50f56119 | 7122 | count = 0; |
9a935856 DV |
7123 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7124 | base.head) { | |
7125 | if (!connector->new_encoder) | |
50f56119 DV |
7126 | continue; |
7127 | ||
9a935856 | 7128 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
7129 | |
7130 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 7131 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
7132 | new_crtc = set->crtc; |
7133 | } | |
7134 | ||
7135 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
7136 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
7137 | new_crtc)) { | |
5e2b584e | 7138 | return -EINVAL; |
50f56119 | 7139 | } |
9a935856 DV |
7140 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
7141 | ||
7142 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
7143 | connector->base.base.id, | |
7144 | drm_get_connector_name(&connector->base), | |
7145 | new_crtc->base.id); | |
7146 | } | |
7147 | ||
7148 | /* Check for any encoders that needs to be disabled. */ | |
7149 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7150 | base.head) { | |
7151 | list_for_each_entry(connector, | |
7152 | &dev->mode_config.connector_list, | |
7153 | base.head) { | |
7154 | if (connector->new_encoder == encoder) { | |
7155 | WARN_ON(!connector->new_encoder->new_crtc); | |
7156 | ||
7157 | goto next_encoder; | |
7158 | } | |
7159 | } | |
7160 | encoder->new_crtc = NULL; | |
7161 | next_encoder: | |
7162 | /* Only now check for crtc changes so we don't miss encoders | |
7163 | * that will be disabled. */ | |
7164 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 7165 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 7166 | config->mode_changed = true; |
50f56119 DV |
7167 | } |
7168 | } | |
9a935856 | 7169 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 7170 | |
2e431051 DV |
7171 | return 0; |
7172 | } | |
7173 | ||
7174 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
7175 | { | |
7176 | struct drm_device *dev; | |
2e431051 DV |
7177 | struct drm_mode_set save_set; |
7178 | struct intel_set_config *config; | |
7179 | int ret; | |
7180 | int i; | |
7181 | ||
8d3e375e DV |
7182 | BUG_ON(!set); |
7183 | BUG_ON(!set->crtc); | |
7184 | BUG_ON(!set->crtc->helper_private); | |
2e431051 DV |
7185 | |
7186 | if (!set->mode) | |
7187 | set->fb = NULL; | |
7188 | ||
431e50f7 DV |
7189 | /* The fb helper likes to play gross jokes with ->mode_set_config. |
7190 | * Unfortunately the crtc helper doesn't do much at all for this case, | |
7191 | * so we have to cope with this madness until the fb helper is fixed up. */ | |
7192 | if (set->fb && set->num_connectors == 0) | |
7193 | return 0; | |
7194 | ||
2e431051 DV |
7195 | if (set->fb) { |
7196 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
7197 | set->crtc->base.id, set->fb->base.id, | |
7198 | (int)set->num_connectors, set->x, set->y); | |
7199 | } else { | |
7200 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
7201 | } |
7202 | ||
7203 | dev = set->crtc->dev; | |
7204 | ||
7205 | ret = -ENOMEM; | |
7206 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
7207 | if (!config) | |
7208 | goto out_config; | |
7209 | ||
7210 | ret = intel_set_config_save_state(dev, config); | |
7211 | if (ret) | |
7212 | goto out_config; | |
7213 | ||
7214 | save_set.crtc = set->crtc; | |
7215 | save_set.mode = &set->crtc->mode; | |
7216 | save_set.x = set->crtc->x; | |
7217 | save_set.y = set->crtc->y; | |
7218 | save_set.fb = set->crtc->fb; | |
7219 | ||
7220 | /* Compute whether we need a full modeset, only an fb base update or no | |
7221 | * change at all. In the future we might also check whether only the | |
7222 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
7223 | * such cases. */ | |
7224 | intel_set_config_compute_mode_changes(set, config); | |
7225 | ||
9a935856 | 7226 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
7227 | if (ret) |
7228 | goto fail; | |
7229 | ||
5e2b584e | 7230 | if (config->mode_changed) { |
87f1faa6 | 7231 | if (set->mode) { |
50f56119 DV |
7232 | DRM_DEBUG_KMS("attempting to set mode from" |
7233 | " userspace\n"); | |
7234 | drm_mode_debug_printmodeline(set->mode); | |
87f1faa6 DV |
7235 | } |
7236 | ||
7237 | if (!intel_set_mode(set->crtc, set->mode, | |
7238 | set->x, set->y, set->fb)) { | |
7239 | DRM_ERROR("failed to set mode on [CRTC:%d]\n", | |
7240 | set->crtc->base.id); | |
7241 | ret = -EINVAL; | |
7242 | goto fail; | |
7243 | } | |
7244 | ||
7245 | if (set->crtc->enabled) { | |
50f56119 DV |
7246 | DRM_DEBUG_KMS("Setting connector DPMS state to on\n"); |
7247 | for (i = 0; i < set->num_connectors; i++) { | |
7248 | DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id, | |
7249 | drm_get_connector_name(set->connectors[i])); | |
7250 | set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON); | |
7251 | } | |
7252 | } | |
5e2b584e | 7253 | } else if (config->fb_changed) { |
4f660f49 | 7254 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 7255 | set->x, set->y, set->fb); |
50f56119 DV |
7256 | } |
7257 | ||
d9e55608 DV |
7258 | intel_set_config_free(config); |
7259 | ||
50f56119 DV |
7260 | return 0; |
7261 | ||
7262 | fail: | |
85f9eb71 | 7263 | intel_set_config_restore_state(dev, config); |
50f56119 DV |
7264 | |
7265 | /* Try to restore the config */ | |
5e2b584e | 7266 | if (config->mode_changed && |
a6778b3c DV |
7267 | !intel_set_mode(save_set.crtc, save_set.mode, |
7268 | save_set.x, save_set.y, save_set.fb)) | |
50f56119 DV |
7269 | DRM_ERROR("failed to restore config after modeset failure\n"); |
7270 | ||
d9e55608 DV |
7271 | out_config: |
7272 | intel_set_config_free(config); | |
50f56119 DV |
7273 | return ret; |
7274 | } | |
7275 | ||
f6e5b160 | 7276 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 CW |
7277 | .cursor_set = intel_crtc_cursor_set, |
7278 | .cursor_move = intel_crtc_cursor_move, | |
7279 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 7280 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
7281 | .destroy = intel_crtc_destroy, |
7282 | .page_flip = intel_crtc_page_flip, | |
7283 | }; | |
7284 | ||
ee7b9f93 JB |
7285 | static void intel_pch_pll_init(struct drm_device *dev) |
7286 | { | |
7287 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7288 | int i; | |
7289 | ||
7290 | if (dev_priv->num_pch_pll == 0) { | |
7291 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); | |
7292 | return; | |
7293 | } | |
7294 | ||
7295 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
7296 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); | |
7297 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); | |
7298 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); | |
7299 | } | |
7300 | } | |
7301 | ||
b358d0a6 | 7302 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7303 | { |
22fd0fab | 7304 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7305 | struct intel_crtc *intel_crtc; |
7306 | int i; | |
7307 | ||
7308 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7309 | if (intel_crtc == NULL) | |
7310 | return; | |
7311 | ||
7312 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7313 | ||
7314 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7315 | for (i = 0; i < 256; i++) { |
7316 | intel_crtc->lut_r[i] = i; | |
7317 | intel_crtc->lut_g[i] = i; | |
7318 | intel_crtc->lut_b[i] = i; | |
7319 | } | |
7320 | ||
80824003 JB |
7321 | /* Swap pipes & planes for FBC on pre-965 */ |
7322 | intel_crtc->pipe = pipe; | |
7323 | intel_crtc->plane = pipe; | |
e2e767ab | 7324 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7325 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7326 | intel_crtc->plane = !pipe; |
80824003 JB |
7327 | } |
7328 | ||
22fd0fab JB |
7329 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7330 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7331 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7332 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7333 | ||
5a354204 | 7334 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 | 7335 | |
79e53945 | 7336 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
7337 | } |
7338 | ||
08d7b3d1 | 7339 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7340 | struct drm_file *file) |
08d7b3d1 | 7341 | { |
08d7b3d1 | 7342 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
7343 | struct drm_mode_object *drmmode_obj; |
7344 | struct intel_crtc *crtc; | |
08d7b3d1 | 7345 | |
1cff8f6b DV |
7346 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
7347 | return -ENODEV; | |
08d7b3d1 | 7348 | |
c05422d5 DV |
7349 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7350 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7351 | |
c05422d5 | 7352 | if (!drmmode_obj) { |
08d7b3d1 CW |
7353 | DRM_ERROR("no such CRTC id\n"); |
7354 | return -EINVAL; | |
7355 | } | |
7356 | ||
c05422d5 DV |
7357 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7358 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7359 | |
c05422d5 | 7360 | return 0; |
08d7b3d1 CW |
7361 | } |
7362 | ||
66a9278e | 7363 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 7364 | { |
66a9278e DV |
7365 | struct drm_device *dev = encoder->base.dev; |
7366 | struct intel_encoder *source_encoder; | |
79e53945 | 7367 | int index_mask = 0; |
79e53945 JB |
7368 | int entry = 0; |
7369 | ||
66a9278e DV |
7370 | list_for_each_entry(source_encoder, |
7371 | &dev->mode_config.encoder_list, base.head) { | |
7372 | ||
7373 | if (encoder == source_encoder) | |
79e53945 | 7374 | index_mask |= (1 << entry); |
66a9278e DV |
7375 | |
7376 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
7377 | if (encoder->cloneable && source_encoder->cloneable) | |
7378 | index_mask |= (1 << entry); | |
7379 | ||
79e53945 JB |
7380 | entry++; |
7381 | } | |
4ef69c7a | 7382 | |
79e53945 JB |
7383 | return index_mask; |
7384 | } | |
7385 | ||
4d302442 CW |
7386 | static bool has_edp_a(struct drm_device *dev) |
7387 | { | |
7388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7389 | ||
7390 | if (!IS_MOBILE(dev)) | |
7391 | return false; | |
7392 | ||
7393 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7394 | return false; | |
7395 | ||
7396 | if (IS_GEN5(dev) && | |
7397 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7398 | return false; | |
7399 | ||
7400 | return true; | |
7401 | } | |
7402 | ||
79e53945 JB |
7403 | static void intel_setup_outputs(struct drm_device *dev) |
7404 | { | |
725e30ad | 7405 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7406 | struct intel_encoder *encoder; |
cb0953d7 | 7407 | bool dpd_is_edp = false; |
f3cfcba6 | 7408 | bool has_lvds; |
79e53945 | 7409 | |
f3cfcba6 | 7410 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
7411 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
7412 | /* disable the panel fitter on everything but LVDS */ | |
7413 | I915_WRITE(PFIT_CONTROL, 0); | |
7414 | } | |
79e53945 | 7415 | |
bad720ff | 7416 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 7417 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 7418 | |
4d302442 | 7419 | if (has_edp_a(dev)) |
ab9d7c30 | 7420 | intel_dp_init(dev, DP_A, PORT_A); |
32f9d658 | 7421 | |
cb0953d7 | 7422 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
ab9d7c30 | 7423 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
cb0953d7 AJ |
7424 | } |
7425 | ||
7426 | intel_crt_init(dev); | |
7427 | ||
0e72a5b5 ED |
7428 | if (IS_HASWELL(dev)) { |
7429 | int found; | |
7430 | ||
7431 | /* Haswell uses DDI functions to detect digital outputs */ | |
7432 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
7433 | /* DDI A only supports eDP */ | |
7434 | if (found) | |
7435 | intel_ddi_init(dev, PORT_A); | |
7436 | ||
7437 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
7438 | * register */ | |
7439 | found = I915_READ(SFUSE_STRAP); | |
7440 | ||
7441 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
7442 | intel_ddi_init(dev, PORT_B); | |
7443 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
7444 | intel_ddi_init(dev, PORT_C); | |
7445 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
7446 | intel_ddi_init(dev, PORT_D); | |
7447 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 AJ |
7448 | int found; |
7449 | ||
30ad48b7 | 7450 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 7451 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 7452 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 7453 | if (!found) |
08d644ad | 7454 | intel_hdmi_init(dev, HDMIB, PORT_B); |
5eb08b69 | 7455 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 7456 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
7457 | } |
7458 | ||
7459 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
08d644ad | 7460 | intel_hdmi_init(dev, HDMIC, PORT_C); |
30ad48b7 | 7461 | |
b708a1d5 | 7462 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
08d644ad | 7463 | intel_hdmi_init(dev, HDMID, PORT_D); |
30ad48b7 | 7464 | |
5eb08b69 | 7465 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 7466 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 7467 | |
cb0953d7 | 7468 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
ab9d7c30 | 7469 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d JB |
7470 | } else if (IS_VALLEYVIEW(dev)) { |
7471 | int found; | |
7472 | ||
7473 | if (I915_READ(SDVOB) & PORT_DETECTED) { | |
7474 | /* SDVOB multiplex with HDMIB */ | |
7475 | found = intel_sdvo_init(dev, SDVOB, true); | |
7476 | if (!found) | |
08d644ad | 7477 | intel_hdmi_init(dev, SDVOB, PORT_B); |
4a87d65d | 7478 | if (!found && (I915_READ(DP_B) & DP_DETECTED)) |
ab9d7c30 | 7479 | intel_dp_init(dev, DP_B, PORT_B); |
4a87d65d JB |
7480 | } |
7481 | ||
7482 | if (I915_READ(SDVOC) & PORT_DETECTED) | |
08d644ad | 7483 | intel_hdmi_init(dev, SDVOC, PORT_C); |
5eb08b69 | 7484 | |
4a87d65d JB |
7485 | /* Shares lanes with HDMI on SDVOC */ |
7486 | if (I915_READ(DP_C) & DP_DETECTED) | |
ab9d7c30 | 7487 | intel_dp_init(dev, DP_C, PORT_C); |
103a196f | 7488 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 7489 | bool found = false; |
7d57382e | 7490 | |
725e30ad | 7491 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 7492 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 7493 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
7494 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7495 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
08d644ad | 7496 | intel_hdmi_init(dev, SDVOB, PORT_B); |
b01f2c3a | 7497 | } |
27185ae1 | 7498 | |
b01f2c3a JB |
7499 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7500 | DRM_DEBUG_KMS("probing DP_B\n"); | |
ab9d7c30 | 7501 | intel_dp_init(dev, DP_B, PORT_B); |
b01f2c3a | 7502 | } |
725e30ad | 7503 | } |
13520b05 KH |
7504 | |
7505 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 7506 | |
b01f2c3a JB |
7507 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7508 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 7509 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 7510 | } |
27185ae1 ML |
7511 | |
7512 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
7513 | ||
b01f2c3a JB |
7514 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7515 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
08d644ad | 7516 | intel_hdmi_init(dev, SDVOC, PORT_C); |
b01f2c3a JB |
7517 | } |
7518 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
7519 | DRM_DEBUG_KMS("probing DP_C\n"); | |
ab9d7c30 | 7520 | intel_dp_init(dev, DP_C, PORT_C); |
b01f2c3a | 7521 | } |
725e30ad | 7522 | } |
27185ae1 | 7523 | |
b01f2c3a JB |
7524 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7525 | (I915_READ(DP_D) & DP_DETECTED)) { | |
7526 | DRM_DEBUG_KMS("probing DP_D\n"); | |
ab9d7c30 | 7527 | intel_dp_init(dev, DP_D, PORT_D); |
b01f2c3a | 7528 | } |
bad720ff | 7529 | } else if (IS_GEN2(dev)) |
79e53945 JB |
7530 | intel_dvo_init(dev); |
7531 | ||
103a196f | 7532 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
7533 | intel_tv_init(dev); |
7534 | ||
4ef69c7a CW |
7535 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7536 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
7537 | encoder->base.possible_clones = | |
66a9278e | 7538 | intel_encoder_clones(encoder); |
79e53945 | 7539 | } |
47356eb6 | 7540 | |
40579abe | 7541 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
9fb526db | 7542 | ironlake_init_pch_refclk(dev); |
79e53945 JB |
7543 | } |
7544 | ||
7545 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
7546 | { | |
7547 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
7548 | |
7549 | drm_framebuffer_cleanup(fb); | |
05394f39 | 7550 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
7551 | |
7552 | kfree(intel_fb); | |
7553 | } | |
7554 | ||
7555 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 7556 | struct drm_file *file, |
79e53945 JB |
7557 | unsigned int *handle) |
7558 | { | |
7559 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 7560 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 7561 | |
05394f39 | 7562 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
7563 | } |
7564 | ||
7565 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
7566 | .destroy = intel_user_framebuffer_destroy, | |
7567 | .create_handle = intel_user_framebuffer_create_handle, | |
7568 | }; | |
7569 | ||
38651674 DA |
7570 | int intel_framebuffer_init(struct drm_device *dev, |
7571 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 7572 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 7573 | struct drm_i915_gem_object *obj) |
79e53945 | 7574 | { |
79e53945 JB |
7575 | int ret; |
7576 | ||
05394f39 | 7577 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
7578 | return -EINVAL; |
7579 | ||
308e5bcb | 7580 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
7581 | return -EINVAL; |
7582 | ||
308e5bcb | 7583 | switch (mode_cmd->pixel_format) { |
04b3924d VS |
7584 | case DRM_FORMAT_RGB332: |
7585 | case DRM_FORMAT_RGB565: | |
7586 | case DRM_FORMAT_XRGB8888: | |
b250da79 | 7587 | case DRM_FORMAT_XBGR8888: |
04b3924d VS |
7588 | case DRM_FORMAT_ARGB8888: |
7589 | case DRM_FORMAT_XRGB2101010: | |
7590 | case DRM_FORMAT_ARGB2101010: | |
308e5bcb | 7591 | /* RGB formats are common across chipsets */ |
b5626747 | 7592 | break; |
04b3924d VS |
7593 | case DRM_FORMAT_YUYV: |
7594 | case DRM_FORMAT_UYVY: | |
7595 | case DRM_FORMAT_YVYU: | |
7596 | case DRM_FORMAT_VYUY: | |
57cd6508 CW |
7597 | break; |
7598 | default: | |
aca25848 ED |
7599 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
7600 | mode_cmd->pixel_format); | |
57cd6508 CW |
7601 | return -EINVAL; |
7602 | } | |
7603 | ||
79e53945 JB |
7604 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7605 | if (ret) { | |
7606 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
7607 | return ret; | |
7608 | } | |
7609 | ||
7610 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 7611 | intel_fb->obj = obj; |
79e53945 JB |
7612 | return 0; |
7613 | } | |
7614 | ||
79e53945 JB |
7615 | static struct drm_framebuffer * |
7616 | intel_user_framebuffer_create(struct drm_device *dev, | |
7617 | struct drm_file *filp, | |
308e5bcb | 7618 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 7619 | { |
05394f39 | 7620 | struct drm_i915_gem_object *obj; |
79e53945 | 7621 | |
308e5bcb JB |
7622 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
7623 | mode_cmd->handles[0])); | |
c8725226 | 7624 | if (&obj->base == NULL) |
cce13ff7 | 7625 | return ERR_PTR(-ENOENT); |
79e53945 | 7626 | |
d2dff872 | 7627 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
7628 | } |
7629 | ||
79e53945 | 7630 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 7631 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 7632 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
7633 | }; |
7634 | ||
e70236a8 JB |
7635 | /* Set up chip specific display functions */ |
7636 | static void intel_init_display(struct drm_device *dev) | |
7637 | { | |
7638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7639 | ||
7640 | /* We always want a DPMS function */ | |
f564048e | 7641 | if (HAS_PCH_SPLIT(dev)) { |
f564048e | 7642 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
7643 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
7644 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 7645 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 7646 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 7647 | } else { |
f564048e | 7648 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
7649 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
7650 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 7651 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 7652 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 7653 | } |
e70236a8 | 7654 | |
e70236a8 | 7655 | /* Returns the core display clock speed */ |
25eb05fc JB |
7656 | if (IS_VALLEYVIEW(dev)) |
7657 | dev_priv->display.get_display_clock_speed = | |
7658 | valleyview_get_display_clock_speed; | |
7659 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
7660 | dev_priv->display.get_display_clock_speed = |
7661 | i945_get_display_clock_speed; | |
7662 | else if (IS_I915G(dev)) | |
7663 | dev_priv->display.get_display_clock_speed = | |
7664 | i915_get_display_clock_speed; | |
f2b115e6 | 7665 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
7666 | dev_priv->display.get_display_clock_speed = |
7667 | i9xx_misc_get_display_clock_speed; | |
7668 | else if (IS_I915GM(dev)) | |
7669 | dev_priv->display.get_display_clock_speed = | |
7670 | i915gm_get_display_clock_speed; | |
7671 | else if (IS_I865G(dev)) | |
7672 | dev_priv->display.get_display_clock_speed = | |
7673 | i865_get_display_clock_speed; | |
f0f8a9ce | 7674 | else if (IS_I85X(dev)) |
e70236a8 JB |
7675 | dev_priv->display.get_display_clock_speed = |
7676 | i855_get_display_clock_speed; | |
7677 | else /* 852, 830 */ | |
7678 | dev_priv->display.get_display_clock_speed = | |
7679 | i830_get_display_clock_speed; | |
7680 | ||
7f8a8569 | 7681 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 7682 | if (IS_GEN5(dev)) { |
674cf967 | 7683 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 7684 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 7685 | } else if (IS_GEN6(dev)) { |
674cf967 | 7686 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 7687 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
7688 | } else if (IS_IVYBRIDGE(dev)) { |
7689 | /* FIXME: detect B0+ stepping and use auto training */ | |
7690 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 7691 | dev_priv->display.write_eld = ironlake_write_eld; |
c82e4d26 ED |
7692 | } else if (IS_HASWELL(dev)) { |
7693 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 7694 | dev_priv->display.write_eld = haswell_write_eld; |
7f8a8569 ZW |
7695 | } else |
7696 | dev_priv->display.update_wm = NULL; | |
6067aaea | 7697 | } else if (IS_G4X(dev)) { |
e0dac65e | 7698 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 7699 | } |
8c9f3aaf JB |
7700 | |
7701 | /* Default just returns -ENODEV to indicate unsupported */ | |
7702 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
7703 | ||
7704 | switch (INTEL_INFO(dev)->gen) { | |
7705 | case 2: | |
7706 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
7707 | break; | |
7708 | ||
7709 | case 3: | |
7710 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
7711 | break; | |
7712 | ||
7713 | case 4: | |
7714 | case 5: | |
7715 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
7716 | break; | |
7717 | ||
7718 | case 6: | |
7719 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
7720 | break; | |
7c9017e5 JB |
7721 | case 7: |
7722 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
7723 | break; | |
8c9f3aaf | 7724 | } |
e70236a8 JB |
7725 | } |
7726 | ||
b690e96c JB |
7727 | /* |
7728 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
7729 | * resume, or other times. This quirk makes sure that's the case for | |
7730 | * affected systems. | |
7731 | */ | |
0206e353 | 7732 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
7733 | { |
7734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7735 | ||
7736 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 7737 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
7738 | } |
7739 | ||
435793df KP |
7740 | /* |
7741 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
7742 | */ | |
7743 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
7744 | { | |
7745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7746 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 7747 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
7748 | } |
7749 | ||
4dca20ef | 7750 | /* |
5a15ab5b CE |
7751 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
7752 | * brightness value | |
4dca20ef CE |
7753 | */ |
7754 | static void quirk_invert_brightness(struct drm_device *dev) | |
7755 | { | |
7756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7757 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 7758 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
7759 | } |
7760 | ||
b690e96c JB |
7761 | struct intel_quirk { |
7762 | int device; | |
7763 | int subsystem_vendor; | |
7764 | int subsystem_device; | |
7765 | void (*hook)(struct drm_device *dev); | |
7766 | }; | |
7767 | ||
c43b5634 | 7768 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 7769 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 7770 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 7771 | |
b690e96c JB |
7772 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
7773 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
7774 | ||
b690e96c JB |
7775 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
7776 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
7777 | ||
7778 | /* 855 & before need to leave pipe A & dpll A up */ | |
7779 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
7780 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
dcdaed6e | 7781 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
7782 | |
7783 | /* Lenovo U160 cannot use SSC on LVDS */ | |
7784 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
7785 | |
7786 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
7787 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
7788 | |
7789 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
7790 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
b690e96c JB |
7791 | }; |
7792 | ||
7793 | static void intel_init_quirks(struct drm_device *dev) | |
7794 | { | |
7795 | struct pci_dev *d = dev->pdev; | |
7796 | int i; | |
7797 | ||
7798 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
7799 | struct intel_quirk *q = &intel_quirks[i]; | |
7800 | ||
7801 | if (d->device == q->device && | |
7802 | (d->subsystem_vendor == q->subsystem_vendor || | |
7803 | q->subsystem_vendor == PCI_ANY_ID) && | |
7804 | (d->subsystem_device == q->subsystem_device || | |
7805 | q->subsystem_device == PCI_ANY_ID)) | |
7806 | q->hook(dev); | |
7807 | } | |
7808 | } | |
7809 | ||
9cce37f4 JB |
7810 | /* Disable the VGA plane that we never use */ |
7811 | static void i915_disable_vga(struct drm_device *dev) | |
7812 | { | |
7813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7814 | u8 sr1; | |
7815 | u32 vga_reg; | |
7816 | ||
7817 | if (HAS_PCH_SPLIT(dev)) | |
7818 | vga_reg = CPU_VGACNTRL; | |
7819 | else | |
7820 | vga_reg = VGACNTRL; | |
7821 | ||
7822 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 7823 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
7824 | sr1 = inb(VGA_SR_DATA); |
7825 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
7826 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
7827 | udelay(300); | |
7828 | ||
7829 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
7830 | POSTING_READ(vga_reg); | |
7831 | } | |
7832 | ||
f817586c DV |
7833 | void intel_modeset_init_hw(struct drm_device *dev) |
7834 | { | |
0232e927 ED |
7835 | /* We attempt to init the necessary power wells early in the initialization |
7836 | * time, so the subsystems that expect power to be enabled can work. | |
7837 | */ | |
7838 | intel_init_power_wells(dev); | |
7839 | ||
a8f78b58 ED |
7840 | intel_prepare_ddi(dev); |
7841 | ||
f817586c DV |
7842 | intel_init_clock_gating(dev); |
7843 | ||
79f5b2c7 | 7844 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 7845 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 7846 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
7847 | } |
7848 | ||
79e53945 JB |
7849 | void intel_modeset_init(struct drm_device *dev) |
7850 | { | |
652c393a | 7851 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 7852 | int i, ret; |
79e53945 JB |
7853 | |
7854 | drm_mode_config_init(dev); | |
7855 | ||
7856 | dev->mode_config.min_width = 0; | |
7857 | dev->mode_config.min_height = 0; | |
7858 | ||
019d96cb DA |
7859 | dev->mode_config.preferred_depth = 24; |
7860 | dev->mode_config.prefer_shadow = 1; | |
7861 | ||
e6ecefaa | 7862 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 7863 | |
b690e96c JB |
7864 | intel_init_quirks(dev); |
7865 | ||
1fa61106 ED |
7866 | intel_init_pm(dev); |
7867 | ||
e70236a8 JB |
7868 | intel_init_display(dev); |
7869 | ||
a6c45cf0 CW |
7870 | if (IS_GEN2(dev)) { |
7871 | dev->mode_config.max_width = 2048; | |
7872 | dev->mode_config.max_height = 2048; | |
7873 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
7874 | dev->mode_config.max_width = 4096; |
7875 | dev->mode_config.max_height = 4096; | |
79e53945 | 7876 | } else { |
a6c45cf0 CW |
7877 | dev->mode_config.max_width = 8192; |
7878 | dev->mode_config.max_height = 8192; | |
79e53945 | 7879 | } |
dd2757f8 | 7880 | dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr; |
79e53945 | 7881 | |
28c97730 | 7882 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 7883 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 7884 | |
a3524f1b | 7885 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 7886 | intel_crtc_init(dev, i); |
00c2064b JB |
7887 | ret = intel_plane_init(dev, i); |
7888 | if (ret) | |
7889 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
7890 | } |
7891 | ||
ee7b9f93 JB |
7892 | intel_pch_pll_init(dev); |
7893 | ||
9cce37f4 JB |
7894 | /* Just disable it once at startup */ |
7895 | i915_disable_vga(dev); | |
79e53945 | 7896 | intel_setup_outputs(dev); |
2c7111db CW |
7897 | } |
7898 | ||
24929352 DV |
7899 | static void |
7900 | intel_connector_break_all_links(struct intel_connector *connector) | |
7901 | { | |
7902 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
7903 | connector->base.encoder = NULL; | |
7904 | connector->encoder->connectors_active = false; | |
7905 | connector->encoder->base.crtc = NULL; | |
7906 | } | |
7907 | ||
7fad798e DV |
7908 | static void intel_enable_pipe_a(struct drm_device *dev) |
7909 | { | |
7910 | struct intel_connector *connector; | |
7911 | struct drm_connector *crt = NULL; | |
7912 | struct intel_load_detect_pipe load_detect_temp; | |
7913 | ||
7914 | /* We can't just switch on the pipe A, we need to set things up with a | |
7915 | * proper mode and output configuration. As a gross hack, enable pipe A | |
7916 | * by enabling the load detect pipe once. */ | |
7917 | list_for_each_entry(connector, | |
7918 | &dev->mode_config.connector_list, | |
7919 | base.head) { | |
7920 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
7921 | crt = &connector->base; | |
7922 | break; | |
7923 | } | |
7924 | } | |
7925 | ||
7926 | if (!crt) | |
7927 | return; | |
7928 | ||
7929 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
7930 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7931 | ||
7932 | ||
7933 | } | |
7934 | ||
24929352 DV |
7935 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
7936 | { | |
7937 | struct drm_device *dev = crtc->base.dev; | |
7938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7939 | u32 reg, val; | |
7940 | ||
24929352 DV |
7941 | /* Clear any frame start delays used for debugging left by the BIOS */ |
7942 | reg = PIPECONF(crtc->pipe); | |
7943 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
7944 | ||
7945 | /* We need to sanitize the plane -> pipe mapping first because this will | |
7946 | * disable the crtc (and hence change the state) if it is wrong. */ | |
7947 | if (!HAS_PCH_SPLIT(dev)) { | |
7948 | struct intel_connector *connector; | |
7949 | bool plane; | |
7950 | ||
7951 | reg = DSPCNTR(crtc->plane); | |
7952 | val = I915_READ(reg); | |
7953 | ||
7954 | if ((val & DISPLAY_PLANE_ENABLE) == 0 && | |
7955 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
7956 | goto ok; | |
7957 | ||
7958 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", | |
7959 | crtc->base.base.id); | |
7960 | ||
7961 | /* Pipe has the wrong plane attached and the plane is active. | |
7962 | * Temporarily change the plane mapping and disable everything | |
7963 | * ... */ | |
7964 | plane = crtc->plane; | |
7965 | crtc->plane = !plane; | |
7966 | dev_priv->display.crtc_disable(&crtc->base); | |
7967 | crtc->plane = plane; | |
7968 | ||
7969 | /* ... and break all links. */ | |
7970 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7971 | base.head) { | |
7972 | if (connector->encoder->base.crtc != &crtc->base) | |
7973 | continue; | |
7974 | ||
7975 | intel_connector_break_all_links(connector); | |
7976 | } | |
7977 | ||
7978 | WARN_ON(crtc->active); | |
7979 | crtc->base.enabled = false; | |
7980 | } | |
7981 | ok: | |
7982 | ||
7fad798e DV |
7983 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
7984 | crtc->pipe == PIPE_A && !crtc->active) { | |
7985 | /* BIOS forgot to enable pipe A, this mostly happens after | |
7986 | * resume. Force-enable the pipe to fix this, the update_dpms | |
7987 | * call below we restore the pipe to the right state, but leave | |
7988 | * the required bits on. */ | |
7989 | intel_enable_pipe_a(dev); | |
7990 | } | |
7991 | ||
24929352 DV |
7992 | /* Adjust the state of the output pipe according to whether we |
7993 | * have active connectors/encoders. */ | |
7994 | intel_crtc_update_dpms(&crtc->base); | |
7995 | ||
7996 | if (crtc->active != crtc->base.enabled) { | |
7997 | struct intel_encoder *encoder; | |
7998 | ||
7999 | /* This can happen either due to bugs in the get_hw_state | |
8000 | * functions or because the pipe is force-enabled due to the | |
8001 | * pipe A quirk. */ | |
8002 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
8003 | crtc->base.base.id, | |
8004 | crtc->base.enabled ? "enabled" : "disabled", | |
8005 | crtc->active ? "enabled" : "disabled"); | |
8006 | ||
8007 | crtc->base.enabled = crtc->active; | |
8008 | ||
8009 | /* Because we only establish the connector -> encoder -> | |
8010 | * crtc links if something is active, this means the | |
8011 | * crtc is now deactivated. Break the links. connector | |
8012 | * -> encoder links are only establish when things are | |
8013 | * actually up, hence no need to break them. */ | |
8014 | WARN_ON(crtc->active); | |
8015 | ||
8016 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
8017 | WARN_ON(encoder->connectors_active); | |
8018 | encoder->base.crtc = NULL; | |
8019 | } | |
8020 | } | |
8021 | } | |
8022 | ||
8023 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
8024 | { | |
8025 | struct intel_connector *connector; | |
8026 | struct drm_device *dev = encoder->base.dev; | |
8027 | ||
8028 | /* We need to check both for a crtc link (meaning that the | |
8029 | * encoder is active and trying to read from a pipe) and the | |
8030 | * pipe itself being active. */ | |
8031 | bool has_active_crtc = encoder->base.crtc && | |
8032 | to_intel_crtc(encoder->base.crtc)->active; | |
8033 | ||
8034 | if (encoder->connectors_active && !has_active_crtc) { | |
8035 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
8036 | encoder->base.base.id, | |
8037 | drm_get_encoder_name(&encoder->base)); | |
8038 | ||
8039 | /* Connector is active, but has no active pipe. This is | |
8040 | * fallout from our resume register restoring. Disable | |
8041 | * the encoder manually again. */ | |
8042 | if (encoder->base.crtc) { | |
8043 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
8044 | encoder->base.base.id, | |
8045 | drm_get_encoder_name(&encoder->base)); | |
8046 | encoder->disable(encoder); | |
8047 | } | |
8048 | ||
8049 | /* Inconsistent output/port/pipe state happens presumably due to | |
8050 | * a bug in one of the get_hw_state functions. Or someplace else | |
8051 | * in our code, like the register restore mess on resume. Clamp | |
8052 | * things to off as a safer default. */ | |
8053 | list_for_each_entry(connector, | |
8054 | &dev->mode_config.connector_list, | |
8055 | base.head) { | |
8056 | if (connector->encoder != encoder) | |
8057 | continue; | |
8058 | ||
8059 | intel_connector_break_all_links(connector); | |
8060 | } | |
8061 | } | |
8062 | /* Enabled encoders without active connectors will be fixed in | |
8063 | * the crtc fixup. */ | |
8064 | } | |
8065 | ||
8066 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
8067 | * and i915 state tracking structures. */ | |
8068 | void intel_modeset_setup_hw_state(struct drm_device *dev) | |
8069 | { | |
8070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8071 | enum pipe pipe; | |
8072 | u32 tmp; | |
8073 | struct intel_crtc *crtc; | |
8074 | struct intel_encoder *encoder; | |
8075 | struct intel_connector *connector; | |
8076 | ||
8077 | for_each_pipe(pipe) { | |
8078 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8079 | ||
8080 | tmp = I915_READ(PIPECONF(pipe)); | |
8081 | if (tmp & PIPECONF_ENABLE) | |
8082 | crtc->active = true; | |
8083 | else | |
8084 | crtc->active = false; | |
8085 | ||
8086 | crtc->base.enabled = crtc->active; | |
8087 | ||
8088 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
8089 | crtc->base.base.id, | |
8090 | crtc->active ? "enabled" : "disabled"); | |
8091 | } | |
8092 | ||
8093 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8094 | base.head) { | |
8095 | pipe = 0; | |
8096 | ||
8097 | if (encoder->get_hw_state(encoder, &pipe)) { | |
8098 | encoder->base.crtc = | |
8099 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
8100 | } else { | |
8101 | encoder->base.crtc = NULL; | |
8102 | } | |
8103 | ||
8104 | encoder->connectors_active = false; | |
8105 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
8106 | encoder->base.base.id, | |
8107 | drm_get_encoder_name(&encoder->base), | |
8108 | encoder->base.crtc ? "enabled" : "disabled", | |
8109 | pipe); | |
8110 | } | |
8111 | ||
8112 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8113 | base.head) { | |
8114 | if (connector->get_hw_state(connector)) { | |
8115 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
8116 | connector->encoder->connectors_active = true; | |
8117 | connector->base.encoder = &connector->encoder->base; | |
8118 | } else { | |
8119 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
8120 | connector->base.encoder = NULL; | |
8121 | } | |
8122 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
8123 | connector->base.base.id, | |
8124 | drm_get_connector_name(&connector->base), | |
8125 | connector->base.encoder ? "enabled" : "disabled"); | |
8126 | } | |
8127 | ||
8128 | /* HW state is read out, now we need to sanitize this mess. */ | |
8129 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8130 | base.head) { | |
8131 | intel_sanitize_encoder(encoder); | |
8132 | } | |
8133 | ||
8134 | for_each_pipe(pipe) { | |
8135 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8136 | intel_sanitize_crtc(crtc); | |
8137 | } | |
9a935856 DV |
8138 | |
8139 | intel_modeset_update_staged_output_state(dev); | |
24929352 DV |
8140 | } |
8141 | ||
2c7111db CW |
8142 | void intel_modeset_gem_init(struct drm_device *dev) |
8143 | { | |
1833b134 | 8144 | intel_modeset_init_hw(dev); |
02e792fb DV |
8145 | |
8146 | intel_setup_overlay(dev); | |
24929352 DV |
8147 | |
8148 | intel_modeset_setup_hw_state(dev); | |
79e53945 JB |
8149 | } |
8150 | ||
8151 | void intel_modeset_cleanup(struct drm_device *dev) | |
8152 | { | |
652c393a JB |
8153 | struct drm_i915_private *dev_priv = dev->dev_private; |
8154 | struct drm_crtc *crtc; | |
8155 | struct intel_crtc *intel_crtc; | |
8156 | ||
f87ea761 | 8157 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
8158 | mutex_lock(&dev->struct_mutex); |
8159 | ||
723bfd70 JB |
8160 | intel_unregister_dsm_handler(); |
8161 | ||
8162 | ||
652c393a JB |
8163 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8164 | /* Skip inactive CRTCs */ | |
8165 | if (!crtc->fb) | |
8166 | continue; | |
8167 | ||
8168 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 8169 | intel_increase_pllclock(crtc); |
652c393a JB |
8170 | } |
8171 | ||
973d04f9 | 8172 | intel_disable_fbc(dev); |
e70236a8 | 8173 | |
8090c6b9 | 8174 | intel_disable_gt_powersave(dev); |
0cdab21f | 8175 | |
930ebb46 DV |
8176 | ironlake_teardown_rc6(dev); |
8177 | ||
57f350b6 JB |
8178 | if (IS_VALLEYVIEW(dev)) |
8179 | vlv_init_dpio(dev); | |
8180 | ||
69341a5e KH |
8181 | mutex_unlock(&dev->struct_mutex); |
8182 | ||
6c0d9350 DV |
8183 | /* Disable the irq before mode object teardown, for the irq might |
8184 | * enqueue unpin/hotplug work. */ | |
8185 | drm_irq_uninstall(dev); | |
8186 | cancel_work_sync(&dev_priv->hotplug_work); | |
c6a828d3 | 8187 | cancel_work_sync(&dev_priv->rps.work); |
6c0d9350 | 8188 | |
1630fe75 CW |
8189 | /* flush any delayed tasks or pending work */ |
8190 | flush_scheduled_work(); | |
8191 | ||
79e53945 JB |
8192 | drm_mode_config_cleanup(dev); |
8193 | } | |
8194 | ||
f1c79df3 ZW |
8195 | /* |
8196 | * Return which encoder is currently attached for connector. | |
8197 | */ | |
df0e9248 | 8198 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 8199 | { |
df0e9248 CW |
8200 | return &intel_attached_encoder(connector)->base; |
8201 | } | |
f1c79df3 | 8202 | |
df0e9248 CW |
8203 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8204 | struct intel_encoder *encoder) | |
8205 | { | |
8206 | connector->encoder = encoder; | |
8207 | drm_mode_connector_attach_encoder(&connector->base, | |
8208 | &encoder->base); | |
79e53945 | 8209 | } |
28d52043 DA |
8210 | |
8211 | /* | |
8212 | * set vga decode state - true == enable VGA decode | |
8213 | */ | |
8214 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
8215 | { | |
8216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8217 | u16 gmch_ctrl; | |
8218 | ||
8219 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
8220 | if (state) | |
8221 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
8222 | else | |
8223 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
8224 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
8225 | return 0; | |
8226 | } | |
c4a1d9e4 CW |
8227 | |
8228 | #ifdef CONFIG_DEBUG_FS | |
8229 | #include <linux/seq_file.h> | |
8230 | ||
8231 | struct intel_display_error_state { | |
8232 | struct intel_cursor_error_state { | |
8233 | u32 control; | |
8234 | u32 position; | |
8235 | u32 base; | |
8236 | u32 size; | |
52331309 | 8237 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
8238 | |
8239 | struct intel_pipe_error_state { | |
8240 | u32 conf; | |
8241 | u32 source; | |
8242 | ||
8243 | u32 htotal; | |
8244 | u32 hblank; | |
8245 | u32 hsync; | |
8246 | u32 vtotal; | |
8247 | u32 vblank; | |
8248 | u32 vsync; | |
52331309 | 8249 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
8250 | |
8251 | struct intel_plane_error_state { | |
8252 | u32 control; | |
8253 | u32 stride; | |
8254 | u32 size; | |
8255 | u32 pos; | |
8256 | u32 addr; | |
8257 | u32 surface; | |
8258 | u32 tile_offset; | |
52331309 | 8259 | } plane[I915_MAX_PIPES]; |
c4a1d9e4 CW |
8260 | }; |
8261 | ||
8262 | struct intel_display_error_state * | |
8263 | intel_display_capture_error_state(struct drm_device *dev) | |
8264 | { | |
0206e353 | 8265 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
8266 | struct intel_display_error_state *error; |
8267 | int i; | |
8268 | ||
8269 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
8270 | if (error == NULL) | |
8271 | return NULL; | |
8272 | ||
52331309 | 8273 | for_each_pipe(i) { |
c4a1d9e4 CW |
8274 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
8275 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
8276 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
8277 | ||
8278 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
8279 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
8280 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 8281 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
8282 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
8283 | if (INTEL_INFO(dev)->gen >= 4) { | |
8284 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
8285 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
8286 | } | |
8287 | ||
8288 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
8289 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
8290 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
8291 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
8292 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
8293 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
8294 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
8295 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
8296 | } | |
8297 | ||
8298 | return error; | |
8299 | } | |
8300 | ||
8301 | void | |
8302 | intel_display_print_error_state(struct seq_file *m, | |
8303 | struct drm_device *dev, | |
8304 | struct intel_display_error_state *error) | |
8305 | { | |
52331309 | 8306 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
8307 | int i; |
8308 | ||
52331309 DL |
8309 | seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); |
8310 | for_each_pipe(i) { | |
c4a1d9e4 CW |
8311 | seq_printf(m, "Pipe [%d]:\n", i); |
8312 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
8313 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
8314 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
8315 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
8316 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
8317 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
8318 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
8319 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
8320 | ||
8321 | seq_printf(m, "Plane [%d]:\n", i); | |
8322 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
8323 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
8324 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
8325 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
8326 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
8327 | if (INTEL_INFO(dev)->gen >= 4) { | |
8328 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
8329 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
8330 | } | |
8331 | ||
8332 | seq_printf(m, "Cursor [%d]:\n", i); | |
8333 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
8334 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
8335 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
8336 | } | |
8337 | } | |
8338 | #endif |