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drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
bfa7df01
VS		 135/* returns HPLL frequency in kHz */
136static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137{
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147}
148
149static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151{
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169}
170
d2acd215
DV		 171int
172intel_pch_rawclk(struct drm_device *dev)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179}
180
79e50a4f
JN		 181/* hrawclock is 1/4 the FSB frequency */
182int intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
bfa7df01
VS		 214static void intel_update_czclk(struct drm_i915_private *dev_priv)
215{
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223}
224
021357ac
CW		 225static inline u32 /* units of 100MHz */
226intel_fdi_link_freq(struct drm_device *dev)
227{
8b99e68c
CW		 228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
021357ac
CW		 233}
234
5d536e28 235static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 236 .dot = { .min = 25000, .max = 350000 },
9c333719 237 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 238 .n = { .min = 2, .max = 16 },
0206e353
AJ		 239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 246};
247
5d536e28
DV		 248static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
9c333719 250 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 251 .n = { .min = 2, .max = 16 },
5d536e28
DV		 252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259};
260
e4b36699 261static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 262 .dot = { .min = 25000, .max = 350000 },
9c333719 263 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 264 .n = { .min = 2, .max = 16 },
0206e353
AJ		 265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
e4b36699 272};
273e27ca 273
e4b36699 274static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
287static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 298};
299
273e27ca 300
e4b36699 301static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
044c7c41 313 },
e4b36699
KP		 314};
315
316static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 327};
328
329static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
044c7c41 340 },
e4b36699
KP		 341};
342
343static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
044c7c41 354 },
e4b36699
KP		 355};
356
f2b115e6 357static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 360 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
273e27ca 363 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 370};
371
f2b115e6 372static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 383};
384
273e27ca
EA		 385/* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
b91ad0ec 390static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 401};
402
b91ad0ec 403static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 414};
415
416static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 427};
428
273e27ca 429/* LVDS 100mhz refclk limits. */
b91ad0ec 430static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
0206e353 438 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 441};
442
443static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
0206e353 451 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 454};
455
dc730512 456static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 464 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 465 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
b99ab663 468 .p1 = { .min = 2, .max = 3 },
5fdc9c49 469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 470};
471
ef9348c8
CML		 472static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 480 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486};
487
5ab7b0b7
ID		 488static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
e6292556 491 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498};
499
cdba954e
ACO		 500static bool
501needs_modeset(struct drm_crtc_state *state)
502{
fc596660 503 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 504}
505
e0638cdf
PZ		 506/**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
4093561b 509bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 510{
409ee761 511 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 512 struct intel_encoder *encoder;
513
409ee761 514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 515 if (encoder->type == type)
516 return true;
517
518 return false;
519}
520
d0737e1d
ACO		 521/**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
a93e255f
ACO		 527static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
d0737e1d 529{
a93e255f 530 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 531 struct drm_connector *connector;
a93e255f 532 struct drm_connector_state *connector_state;
d0737e1d 533 struct intel_encoder *encoder;
a93e255f
ACO		 534 int i, num_connectors = 0;
535
da3ced29 536 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
d0737e1d 541
a93e255f
ACO		 542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
d0737e1d 544 return true;
a93e255f
ACO		 545 }
546
547 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 548
549 return false;
550}
551
a93e255f
ACO		 552static const intel_limit_t *
553intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 554{
a93e255f 555 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 556 const intel_limit_t *limit;
b91ad0ec 557
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 559 if (intel_is_dual_link_lvds(dev)) {
1b894b59 560 if (refclk == 100000)
b91ad0ec
ZW		 561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
1b894b59 565 if (refclk == 100000)
b91ad0ec
ZW		 566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
c6bb3538 570 } else
b91ad0ec 571 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 572
573 return limit;
574}
575
a93e255f
ACO		 576static const intel_limit_t *
577intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 578{
a93e255f 579 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 580 const intel_limit_t *limit;
581
a93e255f 582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 583 if (intel_is_dual_link_lvds(dev))
e4b36699 584 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 585 else
e4b36699 586 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 589 limit = &intel_limits_g4x_hdmi;
a93e255f 590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 591 limit = &intel_limits_g4x_sdvo;
044c7c41 592 } else /* The option is for other outputs */
e4b36699 593 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 594
595 return limit;
596}
597
a93e255f
ACO		 598static const intel_limit_t *
599intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 600{
a93e255f 601 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 602 const intel_limit_t *limit;
603
5ab7b0b7
ID		 604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
a93e255f 607 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 608 else if (IS_G4X(dev)) {
a93e255f 609 limit = intel_g4x_limit(crtc_state);
f2b115e6 610 } else if (IS_PINEVIEW(dev)) {
a93e255f 611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 612 limit = &intel_limits_pineview_lvds;
2177832f 613 else
f2b115e6 614 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
a0c4da24 617 } else if (IS_VALLEYVIEW(dev)) {
dc730512 618 limit = &intel_limits_vlv;
a6c45cf0 619 } else if (!IS_GEN2(dev)) {
a93e255f 620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
79e53945 624 } else {
a93e255f 625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 626 limit = &intel_limits_i8xx_lvds;
a93e255f 627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 628 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 629 else
630 limit = &intel_limits_i8xx_dac;
79e53945
JB		 631 }
632 return limit;
633}
634
dccbea3b
ID		 635/*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
f2b115e6 643/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 644static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 645{
2177832f
SL		 646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
ed5ca77e 648 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 649 return 0;
fb03ac01
VS		 650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 652
653 return clock->dot;
2177832f
SL		 654}
655
7429e9d4
DV		 656static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657{
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659}
660
dccbea3b 661static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 662{
7429e9d4 663 clock->m = i9xx_dpll_compute_m(clock);
79e53945 664 clock->p = clock->p1 * clock->p2;
ed5ca77e 665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 666 return 0;
fb03ac01
VS		 667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 669
670 return clock->dot;
79e53945
JB		 671}
672
dccbea3b 673static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 674{
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 678 return 0;
589eca67
ID		 679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 681
682 return clock->dot / 5;
589eca67
ID		 683}
684
dccbea3b 685int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 686{
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 690 return 0;
ef9348c8
CML		 691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 694
695 return clock->dot / 5;
ef9348c8
CML		 696}
697
7c04d1d9 698#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 699/**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
1b894b59
CW		 704static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
79e53945 707{
f01b7962
VS		 708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
79e53945 710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 711 INTELPllInvalid("p1 out of range\n");
79e53945 712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 713 INTELPllInvalid("m2 out of range\n");
79e53945 714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 715 INTELPllInvalid("m1 out of range\n");
f01b7962 716
5ab7b0b7 717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
5ab7b0b7 721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
79e53945 728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 729 INTELPllInvalid("vco out of range\n");
79e53945
JB		 730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 734 INTELPllInvalid("dot out of range\n");
79e53945
JB		 735
736 return true;
737}
738
3b1429d9
VS		 739static int
740i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
79e53945 743{
3b1429d9 744 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 745
a93e255f 746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 747 /*
a210b028
DV		 748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
79e53945 751 */
1974cad0 752 if (intel_is_dual_link_lvds(dev))
3b1429d9 753 return limit->p2.p2_fast;
79e53945 754 else
3b1429d9 755 return limit->p2.p2_slow;
79e53945
JB		 756 } else {
757 if (target < limit->p2.dot_limit)
3b1429d9 758 return limit->p2.p2_slow;
79e53945 759 else
3b1429d9 760 return limit->p2.p2_fast;
79e53945 761 }
3b1429d9
VS		 762}
763
764static bool
765i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769{
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
79e53945 773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 782 if (clock.m2 >= clock.m1)
42158660
ZY		 783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 788 int this_err;
789
dccbea3b 790 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809}
810
811static bool
a93e255f
ACO		 812pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
79e53945 816{
3b1429d9 817 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 818 intel_clock_t clock;
79e53945
JB		 819 int err = target;
820
0206e353 821 memset(best_clock, 0, sizeof(*best_clock));
79e53945 822
3b1429d9
VS		 823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
42158660
ZY		 825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 833 int this_err;
834
dccbea3b 835 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
79e53945 838 continue;
cec2f356
SP		 839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
79e53945
JB		 842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
d4906093 856static bool
a93e255f
ACO		 857g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
d4906093 861{
3b1429d9 862 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 863 intel_clock_t clock;
864 int max_n;
3b1429d9 865 bool found = false;
6ba770dc
AJ		 866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 868
869 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
d4906093 873 max_n = limit->n.max;
f77f13e2 874 /* based on hardware requirement, prefer smaller n to precision */
d4906093 875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 876 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
dccbea3b 885 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
d4906093 888 continue;
1b894b59
CW		 889
890 this_err = abs(clock.dot - target);
d4906093
ML		 891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
2c07245f
ZW		 901 return found;
902}
903
d5dd62bd
ID		 904/*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913{
9ca3ba01
ID		 914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
24be4e46
ID		 924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
d5dd62bd
ID		 927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942}
943
a0c4da24 944static bool
a93e255f
ACO		 945vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
a0c4da24 949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 952 intel_clock_t clock;
69e4f900 953 unsigned int bestppm = 1000000;
27e639bf
VS		 954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 956 bool found = false;
a0c4da24 957
6b4bf1c4
VS		 958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 961
962 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 967 clock.p = clock.p1 * clock.p2;
a0c4da24 968 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 970 unsigned int ppm;
69e4f900 971
6b4bf1c4
VS		 972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
dccbea3b 975 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 976
f01b7962
VS		 977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
43b0ac53
VS		 979 continue;
980
d5dd62bd
ID		 981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
6b4bf1c4 986
d5dd62bd
ID		 987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
a0c4da24
JB		 990 }
991 }
992 }
993 }
a0c4da24 994
49e497ef 995 return found;
a0c4da24 996}
a4fc5ed6 997
ef9348c8 998static bool
a93e255f
ACO		 999chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003{
a93e255f 1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 1005 struct drm_device *dev = crtc->base.dev;
9ca3ba01 1006 unsigned int best_error_ppm;
ef9348c8
CML		 1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 1012 best_error_ppm = 1000000;
ef9348c8
CML		 1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1026 unsigned int error_ppm;
ef9348c8
CML		 1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
dccbea3b 1038 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
9ca3ba01
ID		 1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
ef9348c8
CML		 1050 }
1051 }
1052
1053 return found;
1054}
1055
5ab7b0b7
ID		 1056bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058{
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063}
1064
20ddf665
VS		 1065bool intel_crtc_active(struct drm_crtc *crtc)
1066{
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
241bfc38 1072 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1073 * as Haswell has gained clock readout/fastboot support.
1074 *
66e514c1 1075 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1076 * properly reconstruct framebuffers.
c3d1f436
MR		 1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
20ddf665 1081 */
c3d1f436 1082 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1084}
1085
a5c961d1
PZ		 1086enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
6e3c9717 1092 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1093}
1094
fbf49ea2
VS		 1095static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096{
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1108 msleep(5);
fbf49ea2
VS		 1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112}
1113
ab7ad7f6
KP		 1114/*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1116 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
ab7ad7f6
KP		 1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
58e10eb9 1128 *
9d0498a2 1129 */
575f7ab7 1130static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1131{
575f7ab7 1132 struct drm_device *dev = crtc->base.dev;
9d0498a2 1133 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1135 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1138 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1139
1140 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
284637d9 1143 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1144 } else {
ab7ad7f6 1145 /* Wait for the display line to settle */
fbf49ea2 1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1147 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1148 }
79e53945
JB		 1149}
1150
b24e7179
JB		 1151static const char *state_string(bool enabled)
1152{
1153 return enabled ? "on" : "off";
1154}
1155
1156/* Only for pre-ILK configs */
55607e8a
DV		 1157void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
b24e7179 1159{
b24e7179
JB		 1160 u32 val;
1161 bool cur_state;
1162
649636ef 1163 val = I915_READ(DPLL(pipe));
b24e7179 1164 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1165 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168}
b24e7179 1169
23538ef1
JN		 1170/* XXX: the dsi pll is shared between MIPI DSI ports */
1171static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172{
1173 u32 val;
1174 bool cur_state;
1175
a580516d 1176 mutex_lock(&dev_priv->sb_lock);
23538ef1 1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1178 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1179
1180 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1181 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184}
1185#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
55607e8a 1188struct intel_shared_dpll *
e2b78267
DV		 1189intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190{
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
6e3c9717 1193 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1194 return NULL;
1195
6e3c9717 1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1197}
1198
040484af 1199/* For ILK+ */
55607e8a
DV		 1200void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
040484af 1203{
040484af 1204 bool cur_state;
5358901f 1205 struct intel_dpll_hw_state hw_state;
040484af 1206
92b27b08 1207 if (WARN (!pll,
46edb027 1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1209 return;
ee7b9f93 1210
5358901f 1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1212 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
040484af 1215}
040484af
JB		 1216
1217static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219{
040484af 1220 bool cur_state;
ad80a810
PZ		 1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
040484af 1223
affa9354
PZ		 1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
649636ef 1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1228 } else {
649636ef 1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED		 1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
e2c719b7 1232 I915_STATE_WARN(cur_state != state,
040484af
JB		 1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235}
1236#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241{
040484af
JB		 1242 u32 val;
1243 bool cur_state;
1244
649636ef 1245 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1246 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1247 I915_STATE_WARN(cur_state != state,
040484af
JB		 1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250}
1251#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
040484af
JB		 1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
3d13ef2e 1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1261 return;
1262
bf507ef7 1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1264 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1265 return;
1266
649636ef 1267 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1269}
1270
55607e8a
DV		 1271void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
040484af 1273{
040484af 1274 u32 val;
55607e8a 1275 bool cur_state;
040484af 1276
649636ef 1277 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1279 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
040484af
JB		 1282}
1283
b680c37a
DV		 1284void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
ea0760cf 1286{
bedd4dba
JN		 1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
ea0760cf
JB		 1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
0de3b485 1291 bool locked = true;
ea0760cf 1292
bedd4dba
JN		 1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
ea0760cf 1299 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
ea0760cf
JB		 1310 } else {
1311 pp_reg = PP_CONTROL;
bedd4dba
JN		 1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
ea0760cf
JB		 1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1319 locked = false;
1320
e2c719b7 1321 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1322 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1323 pipe_name(pipe));
ea0760cf
JB		 1324}
1325
93ce0ba6
JN		 1326static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328{
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
d9d82081 1332 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1334 else
5efb3e28 1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340}
1341#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
b840d907
JB		 1344void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
b24e7179 1346{
63d7bbe9 1347 bool cur_state;
702e7a56
PZ		 1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
b24e7179 1350
b6b5d049
VS		 1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1354 state = true;
1355
f458ebbc 1356 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1358 cur_state = false;
1359 } else {
649636ef 1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161
PZ		 1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
e2c719b7 1364 I915_STATE_WARN(cur_state != state,
63d7bbe9 1365 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1366 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1367}
1368
931872fc
CW		 1369static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
b24e7179 1371{
b24e7179 1372 u32 val;
931872fc 1373 bool cur_state;
b24e7179 1374
649636ef 1375 val = I915_READ(DSPCNTR(plane));
931872fc 1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1377 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1380}
1381
931872fc
CW		 1382#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
b24e7179
JB		 1385static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387{
653e1026 1388 struct drm_device *dev = dev_priv->dev;
649636ef 1389 int i;
b24e7179 1390
653e1026
VS		 1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
649636ef 1393 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
19ec1358 1397 return;
28c05794 1398 }
19ec1358 1399
b24e7179 1400 /* Need to check both planes against the pipe */
055e393f 1401 for_each_pipe(dev_priv, i) {
649636ef
VS		 1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1404 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1408 }
1409}
1410
19332d7a
JB		 1411static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
20674eef 1414 struct drm_device *dev = dev_priv->dev;
649636ef 1415 int sprite;
19332d7a 1416
7feb8b88 1417 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1418 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1425 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
e2c719b7 1427 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1429 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
649636ef 1432 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1433 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
649636ef 1437 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1438 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1440 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1441 }
1442}
1443
08c71e5e
VS		 1444static void assert_vblank_disabled(struct drm_crtc *crtc)
1445{
e2c719b7 1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1447 drm_crtc_vblank_put(crtc);
1448}
1449
89eff4be 1450static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1451{
1452 u32 val;
1453 bool enabled;
1454
e2c719b7 1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1456
92f2584a
JB		 1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1461}
1462
ab9412ba
DV		 1463static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
92f2584a 1465{
92f2584a
JB		 1466 u32 val;
1467 bool enabled;
1468
649636ef 1469 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1470 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1471 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
92f2584a
JB		 1474}
1475
4e634389
KP		 1476static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1478{
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
44f37d1f
CML		 1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
f0575e92
KP		 1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495}
1496
1519b995
KP		 1497static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
dc0fa718 1500 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1505 return false;
44f37d1f
CML		 1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1519b995 1509 } else {
dc0fa718 1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1511 return false;
1512 }
1513 return true;
1514}
1515
1516static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518{
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
1532static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534{
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545}
1546
291906f1 1547static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1548 enum pipe pipe, int reg, u32 port_sel)
291906f1 1549{
47a05eca 1550 u32 val = I915_READ(reg);
e2c719b7 1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1553 reg, pipe_name(pipe));
de9a35ab 1554
e2c719b7 1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1556 && (val & DP_PIPEB_SELECT),
de9a35ab 1557 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1558}
1559
1560static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562{
47a05eca 1563 u32 val = I915_READ(reg);
e2c719b7 1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1566 reg, pipe_name(pipe));
de9a35ab 1567
e2c719b7 1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1569 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1570 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1571}
1572
1573static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575{
291906f1 1576 u32 val;
291906f1 1577
f0575e92
KP		 1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1581
649636ef 1582 val = I915_READ(PCH_ADPA);
e2c719b7 1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
649636ef 1587 val = I915_READ(PCH_LVDS);
e2c719b7 1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1590 pipe_name(pipe));
291906f1 1591
e2debe91
PZ		 1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1595}
1596
d288f65f 1597static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1598 const struct intel_crtc_state *pipe_config)
87442f73 1599{
426115cf
DV		 1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
d288f65f 1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1604
426115cf 1605 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1611 if (IS_MOBILE(dev_priv->dev))
426115cf 1612 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1613
426115cf
DV		 1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
d288f65f 1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1622 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1623
1624 /* We do this three times for luck */
426115cf 1625 I915_WRITE(reg, dpll);
87442f73
DV		 1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
426115cf 1628 I915_WRITE(reg, dpll);
87442f73
DV		 1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
426115cf 1631 I915_WRITE(reg, dpll);
87442f73
DV		 1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634}
1635
d288f65f 1636static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1637 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1638{
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
a580516d 1649 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
54433e91
VS		 1656 mutex_unlock(&dev_priv->sb_lock);
1657
9d556c99
CML		 1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
d288f65f 1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1665
1666 /* Check PLL is locked */
a11b0703 1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
a11b0703 1670 /* not sure when this should be written */
d288f65f 1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1672 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1673}
1674
1c4e0274
VS		 1675static int intel_num_dvo_pipes(struct drm_device *dev)
1676{
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
3538b9df 1681 count += crtc->base.state->active &&
409ee761 1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1683
1684 return count;
1685}
1686
66e3d5c0 1687static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1688{
66e3d5c0
DV		 1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
6e3c9717 1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1693
66e3d5c0 1694 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1695
63d7bbe9 1696 /* No really, not for ILK+ */
3d13ef2e 1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1698
1699 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1702
1c4e0274
VS		 1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
66e3d5c0
DV		 1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1722 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
63d7bbe9
JB		 1731
1732 /* We do this three times for luck */
66e3d5c0 1733 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
66e3d5c0 1736 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
66e3d5c0 1739 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742}
1743
1744/**
50b44a44 1745 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1c4e0274 1753static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1754{
1c4e0274
VS		 1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
409ee761 1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1762 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
b6b5d049
VS		 1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
b8afb911 1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1778 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1779}
1780
f6071166
JB		 1781static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782{
b8afb911 1783 u32 val;
f6071166
JB		 1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
e5cbfbfb
ID		 1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
b8afb911 1792 val = DPLL_VGA_MODE_DIS;
f6071166 1793 if (pipe == PIPE_B)
60bfe44f 1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1797
1798}
1799
1800static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801{
d752048d 1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1803 u32 val;
1804
a11b0703
VS		 1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1807
a11b0703 1808 /* Set PLL en = 0 */
60bfe44f
VS		 1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
d752048d 1815
a580516d 1816 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
a580516d 1823 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1824}
1825
e4607fcf 1826void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
89b667f8
JB		 1829{
1830 u32 port_mask;
00fc31b7 1831 int dpll_reg;
89b667f8 1832
e4607fcf
CML		 1833 switch (dport->port) {
1834 case PORT_B:
89b667f8 1835 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1836 dpll_reg = DPLL(0);
e4607fcf
CML		 1837 break;
1838 case PORT_C:
89b667f8 1839 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1840 dpll_reg = DPLL(0);
9b6de0a1 1841 expected_mask <<= 4;
00fc31b7
CML		 1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1846 break;
1847 default:
1848 BUG();
1849 }
89b667f8 1850
9b6de0a1
VS		 1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1854}
1855
b14b1055
DV		 1856static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857{
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
be19f0ff
CW		 1862 if (WARN_ON(pll == NULL))
1863 return;
1864
3e369b76 1865 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873}
1874
92f2584a 1875/**
85b3894f 1876 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
85b3894f 1883static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1884{
3d13ef2e
DL		 1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1888
87a875bb 1889 if (WARN_ON(pll == NULL))
48da64a8
CW		 1890 return;
1891
3e369b76 1892 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1893 return;
ee7b9f93 1894
74dd6928 1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1896 pll->name, pll->active, pll->on,
e2b78267 1897 crtc->base.base.id);
92f2584a 1898
cdbd2316
DV		 1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
e9d6944e 1901 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1902 return;
1903 }
f4a091c7 1904 WARN_ON(pll->on);
ee7b9f93 1905
bd2bb1b9
PZ		 1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
46edb027 1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1909 pll->enable(dev_priv, pll);
ee7b9f93 1910 pll->on = true;
92f2584a
JB		 1911}
1912
f6daaec2 1913static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1918
92f2584a 1919 /* PCH only available on ILK+ */
80aa9312
JB		 1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
eddfcbcd
ML		 1923 if (pll == NULL)
1924 return;
92f2584a 1925
eddfcbcd 1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1927 return;
7a419866 1928
46edb027
DV		 1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
e2b78267 1931 crtc->base.base.id);
7a419866 1932
48da64a8 1933 if (WARN_ON(pll->active == 0)) {
e9d6944e 1934 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1935 return;
1936 }
1937
e9d6944e 1938 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1939 WARN_ON(!pll->on);
cdbd2316 1940 if (--pll->active)
7a419866 1941 return;
ee7b9f93 1942
46edb027 1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1944 pll->disable(dev_priv, pll);
ee7b9f93 1945 pll->on = false;
bd2bb1b9
PZ		 1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1948}
1949
b8a4f404
PZ		 1950static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
040484af 1952{
23670b32 1953 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1956 uint32_t reg, val, pipeconf_val;
040484af
JB		 1957
1958 /* PCH only available on ILK+ */
55522f37 1959 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1960
1961 /* Make sure PCH DPLL is enabled */
e72f9fbf 1962 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1963 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1964
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1968
23670b32
DV		 1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
59c859d6 1976 }
23670b32 1977
ab9412ba 1978 reg = PCH_TRANSCONF(pipe);
040484af 1979 val = I915_READ(reg);
5f7f726d 1980 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1981
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1983 /*
c5de7c6f
VS		 1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
e9bcff5c 1987 */
dfd07d72 1988 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1991 else
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1993 }
5f7f726d
PZ		 1994
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1997 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2000 else
2001 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2002 else
2003 val |= TRANS_PROGRESSIVE;
2004
040484af
JB		 2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2008}
2009
8fb033d7 2010static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2011 enum transcoder cpu_transcoder)
040484af 2012{
8fb033d7 2013 u32 val, pipeconf_val;
8fb033d7
PZ		 2014
2015 /* PCH only available on ILK+ */
55522f37 2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2017
8fb033d7 2018 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2021
223a6fdf 2022 /* Workaround: set timing override bit. */
36c0d0cf 2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 2026
25f3ef11 2027 val = TRANS_ENABLE;
937bb610 2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2029
9a76b1c6
PZ		 2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
a35f2679 2032 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2033 else
2034 val |= TRANS_PROGRESSIVE;
2035
ab9412ba
DV		 2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2038 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2039}
2040
b8a4f404
PZ		 2041static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042 enum pipe pipe)
040484af 2043{
23670b32
DV		 2044 struct drm_device *dev = dev_priv->dev;
2045 uint32_t reg, val;
040484af
JB		 2046
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2050
291906f1
JB		 2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2053
ab9412ba 2054 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32 2061
c465613b 2062 if (HAS_PCH_CPT(dev)) {
23670b32
DV		 2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2068 }
040484af
JB		 2069}
2070
ab4d966c 2071static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2072{
8fb033d7
PZ		 2073 u32 val;
2074
ab9412ba 2075 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2076 val &= ~TRANS_ENABLE;
ab9412ba 2077 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2078 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2080 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2081
2082 /* Workaround: clear timing override bit. */
36c0d0cf 2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 2086}
2087
b24e7179 2088/**
309cfea8 2089 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2090 * @crtc: crtc responsible for the pipe
b24e7179 2091 *
0372264a 2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2094 */
e1fdc473 2095static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2096{
0372264a
PZ		 2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
1a70a728 2100 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1a240d4d 2101 enum pipe pch_transcoder;
b24e7179
JB		 2102 int reg;
2103 u32 val;
2104
9e2ee2dd
VS		 2105 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2106
58c6eaa2 2107 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2108 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2109 assert_sprites_disabled(dev_priv, pipe);
2110
681e5811 2111 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2112 pch_transcoder = TRANSCODER_A;
2113 else
2114 pch_transcoder = pipe;
2115
b24e7179
JB		 2116 /*
2117 * A pipe without a PLL won't actually be able to drive bits from
2118 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2119 * need the check.
2120 */
50360403 2121 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2122 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2123 assert_dsi_pll_enabled(dev_priv);
2124 else
2125 assert_pll_enabled(dev_priv, pipe);
040484af 2126 else {
6e3c9717 2127 if (crtc->config->has_pch_encoder) {
040484af 2128 /* if driving the PCH, we need FDI enabled */
cc391bbb 2129 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2130 assert_fdi_tx_pll_enabled(dev_priv,
2131 (enum pipe) cpu_transcoder);
040484af
JB		 2132 }
2133 /* FIXME: assert CPU port conditions for SNB+ */
2134 }
b24e7179 2135
702e7a56 2136 reg = PIPECONF(cpu_transcoder);
b24e7179 2137 val = I915_READ(reg);
7ad25d48 2138 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2139 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2140 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2141 return;
7ad25d48 2142 }
00d70b15
CW		 2143
2144 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2145 POSTING_READ(reg);
b24e7179
JB		 2146}
2147
2148/**
309cfea8 2149 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2150 * @crtc: crtc whose pipes is to be disabled
b24e7179 2151 *
575f7ab7
VS		 2152 * Disable the pipe of @crtc, making sure that various hardware
2153 * specific requirements are met, if applicable, e.g. plane
2154 * disabled, panel fitter off, etc.
b24e7179
JB		 2155 *
2156 * Will wait until the pipe has shut down before returning.
2157 */
575f7ab7 2158static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2159{
575f7ab7 2160 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2161 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2162 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2163 int reg;
2164 u32 val;
2165
9e2ee2dd
VS		 2166 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2167
b24e7179
JB		 2168 /*
2169 * Make sure planes won't keep trying to pump pixels to us,
2170 * or we might hang the display.
2171 */
2172 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2173 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2174 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2175
702e7a56 2176 reg = PIPECONF(cpu_transcoder);
b24e7179 2177 val = I915_READ(reg);
00d70b15
CW		 2178 if ((val & PIPECONF_ENABLE) == 0)
2179 return;
2180
67adc644
VS		 2181 /*
2182 * Double wide has implications for planes
2183 * so best keep it disabled when not needed.
2184 */
6e3c9717 2185 if (crtc->config->double_wide)
67adc644
VS		 2186 val &= ~PIPECONF_DOUBLE_WIDE;
2187
2188 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2189 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2190 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2191 val &= ~PIPECONF_ENABLE;
2192
2193 I915_WRITE(reg, val);
2194 if ((val & PIPECONF_ENABLE) == 0)
2195 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2196}
2197
693db184
CW		 2198static bool need_vtd_wa(struct drm_device *dev)
2199{
2200#ifdef CONFIG_INTEL_IOMMU
2201 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2202 return true;
2203#endif
2204 return false;
2205}
2206
50470bb0 2207unsigned int
6761dd31 2208intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
fe47ea0c 2209 uint64_t fb_format_modifier, unsigned int plane)
a57ce0b2 2210{
6761dd31
TU		 2211 unsigned int tile_height;
2212 uint32_t pixel_bytes;
a57ce0b2 2213
b5d0e9bf
DL		 2214 switch (fb_format_modifier) {
2215 case DRM_FORMAT_MOD_NONE:
2216 tile_height = 1;
2217 break;
2218 case I915_FORMAT_MOD_X_TILED:
2219 tile_height = IS_GEN2(dev) ? 16 : 8;
2220 break;
2221 case I915_FORMAT_MOD_Y_TILED:
2222 tile_height = 32;
2223 break;
2224 case I915_FORMAT_MOD_Yf_TILED:
fe47ea0c 2225 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
6761dd31 2226 switch (pixel_bytes) {
b5d0e9bf 2227 default:
6761dd31 2228 case 1:
b5d0e9bf
DL		 2229 tile_height = 64;
2230 break;
6761dd31
TU		 2231 case 2:
2232 case 4:
b5d0e9bf
DL		 2233 tile_height = 32;
2234 break;
6761dd31 2235 case 8:
b5d0e9bf
DL		 2236 tile_height = 16;
2237 break;
6761dd31 2238 case 16:
b5d0e9bf
DL		 2239 WARN_ONCE(1,
2240 "128-bit pixels are not supported for display!");
2241 tile_height = 16;
2242 break;
2243 }
2244 break;
2245 default:
2246 MISSING_CASE(fb_format_modifier);
2247 tile_height = 1;
2248 break;
2249 }
091df6cb 2250
6761dd31
TU		 2251 return tile_height;
2252}
2253
2254unsigned int
2255intel_fb_align_height(struct drm_device *dev, unsigned int height,
2256 uint32_t pixel_format, uint64_t fb_format_modifier)
2257{
2258 return ALIGN(height, intel_tile_height(dev, pixel_format,
fe47ea0c 2259 fb_format_modifier, 0));
a57ce0b2
JB		 2260}
2261
f64b98cd
TU		 2262static int
2263intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2264 const struct drm_plane_state *plane_state)
2265{
50470bb0 2266 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2267 unsigned int tile_height, tile_pitch;
50470bb0 2268
f64b98cd
TU		 2269 *view = i915_ggtt_view_normal;
2270
50470bb0
TU		 2271 if (!plane_state)
2272 return 0;
2273
121920fa 2274 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2275 return 0;
2276
9abc4648 2277 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2278
2279 info->height = fb->height;
2280 info->pixel_format = fb->pixel_format;
2281 info->pitch = fb->pitches[0];
89e3e142 2282 info->uv_offset = fb->offsets[1];
50470bb0
TU		 2283 info->fb_modifier = fb->modifier[0];
2284
84fe03f7 2285 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
fe47ea0c 2286 fb->modifier[0], 0);
84fe03f7
TU		 2287 tile_pitch = PAGE_SIZE / tile_height;
2288 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2289 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2290 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2291
89e3e142
TU		 2292 if (info->pixel_format == DRM_FORMAT_NV12) {
2293 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2294 fb->modifier[0], 1);
2295 tile_pitch = PAGE_SIZE / tile_height;
2296 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2297 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2298 tile_height);
2299 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2300 PAGE_SIZE;
2301 }
2302
f64b98cd
TU		 2303 return 0;
2304}
2305
4e9a86b6
VS		 2306static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2307{
2308 if (INTEL_INFO(dev_priv)->gen >= 9)
2309 return 256 * 1024;
985b8bb4
VS		 2310 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2311 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2312 return 128 * 1024;
2313 else if (INTEL_INFO(dev_priv)->gen >= 4)
2314 return 4 * 1024;
2315 else
44c5905e 2316 return 0;
4e9a86b6
VS		 2317}
2318
127bd2ac 2319int
850c4cdc
TU		 2320intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2321 struct drm_framebuffer *fb,
7580d774 2322 const struct drm_plane_state *plane_state)
6b95a207 2323{
850c4cdc 2324 struct drm_device *dev = fb->dev;
ce453d81 2325 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2326 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2327 struct i915_ggtt_view view;
6b95a207
KH		 2328 u32 alignment;
2329 int ret;
2330
ebcdd39e
MR		 2331 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2332
7b911adc
TU		 2333 switch (fb->modifier[0]) {
2334 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2335 alignment = intel_linear_alignment(dev_priv);
6b95a207 2336 break;
7b911adc 2337 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2338 if (INTEL_INFO(dev)->gen >= 9)
2339 alignment = 256 * 1024;
2340 else {
2341 /* pin() will align the object as required by fence */
2342 alignment = 0;
2343 }
6b95a207 2344 break;
7b911adc 2345 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2346 case I915_FORMAT_MOD_Yf_TILED:
2347 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2348 "Y tiling bo slipped through, driver bug!\n"))
2349 return -EINVAL;
2350 alignment = 1 * 1024 * 1024;
2351 break;
6b95a207 2352 default:
7b911adc
TU		 2353 MISSING_CASE(fb->modifier[0]);
2354 return -EINVAL;
6b95a207
KH		 2355 }
2356
f64b98cd
TU		 2357 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2358 if (ret)
2359 return ret;
2360
693db184
CW		 2361 /* Note that the w/a also requires 64 PTE of padding following the
2362 * bo. We currently fill all unused PTE with the shadow page and so
2363 * we should always have valid PTE following the scanout preventing
2364 * the VT-d warning.
2365 */
2366 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2367 alignment = 256 * 1024;
2368
d6dd6843
PZ		 2369 /*
2370 * Global gtt pte registers are special registers which actually forward
2371 * writes to a chunk of system memory. Which means that there is no risk
2372 * that the register values disappear as soon as we call
2373 * intel_runtime_pm_put(), so it is correct to wrap only the
2374 * pin/unpin/fence and not more.
2375 */
2376 intel_runtime_pm_get(dev_priv);
2377
7580d774
ML		 2378 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2379 &view);
48b956c5 2380 if (ret)
b26a6b35 2381 goto err_pm;
6b95a207
KH		 2382
2383 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2384 * fence, whereas 965+ only requires a fence if using
2385 * framebuffer compression. For simplicity, we always install
2386 * a fence as the cost is not that onerous.
2387 */
06d98131 2388 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2389 if (ret == -EDEADLK) {
2390 /*
2391 * -EDEADLK means there are no free fences
2392 * no pending flips.
2393 *
2394 * This is propagated to atomic, but it uses
2395 * -EDEADLK to force a locking recovery, so
2396 * change the returned error to -EBUSY.
2397 */
2398 ret = -EBUSY;
2399 goto err_unpin;
2400 } else if (ret)
9a5a53b3 2401 goto err_unpin;
1690e1eb 2402
9a5a53b3 2403 i915_gem_object_pin_fence(obj);
6b95a207 2404
d6dd6843 2405 intel_runtime_pm_put(dev_priv);
6b95a207 2406 return 0;
48b956c5
CW		 2407
2408err_unpin:
f64b98cd 2409 i915_gem_object_unpin_from_display_plane(obj, &view);
b26a6b35 2410err_pm:
d6dd6843 2411 intel_runtime_pm_put(dev_priv);
48b956c5 2412 return ret;
6b95a207
KH		 2413}
2414
82bc3b2d
TU		 2415static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2416 const struct drm_plane_state *plane_state)
1690e1eb 2417{
82bc3b2d 2418 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2419 struct i915_ggtt_view view;
2420 int ret;
82bc3b2d 2421
ebcdd39e
MR		 2422 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2423
f64b98cd
TU		 2424 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2425 WARN_ONCE(ret, "Couldn't get view from plane state!");
2426
1690e1eb 2427 i915_gem_object_unpin_fence(obj);
f64b98cd 2428 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2429}
2430
c2c75131
DV		 2431/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2432 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2433unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2434 int *x, int *y,
bc752862
CW		 2435 unsigned int tiling_mode,
2436 unsigned int cpp,
2437 unsigned int pitch)
c2c75131 2438{
bc752862
CW		 2439 if (tiling_mode != I915_TILING_NONE) {
2440 unsigned int tile_rows, tiles;
c2c75131 2441
bc752862
CW		 2442 tile_rows = *y / 8;
2443 *y %= 8;
c2c75131 2444
bc752862
CW		 2445 tiles = *x / (512/cpp);
2446 *x %= 512/cpp;
2447
2448 return tile_rows * pitch * 8 + tiles * 4096;
2449 } else {
4e9a86b6 2450 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2451 unsigned int offset;
2452
2453 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2454 *y = (offset & alignment) / pitch;
2455 *x = ((offset & alignment) - *y * pitch) / cpp;
2456 return offset & ~alignment;
bc752862 2457 }
c2c75131
DV		 2458}
2459
b35d63fa 2460static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2461{
2462 switch (format) {
2463 case DISPPLANE_8BPP:
2464 return DRM_FORMAT_C8;
2465 case DISPPLANE_BGRX555:
2466 return DRM_FORMAT_XRGB1555;
2467 case DISPPLANE_BGRX565:
2468 return DRM_FORMAT_RGB565;
2469 default:
2470 case DISPPLANE_BGRX888:
2471 return DRM_FORMAT_XRGB8888;
2472 case DISPPLANE_RGBX888:
2473 return DRM_FORMAT_XBGR8888;
2474 case DISPPLANE_BGRX101010:
2475 return DRM_FORMAT_XRGB2101010;
2476 case DISPPLANE_RGBX101010:
2477 return DRM_FORMAT_XBGR2101010;
2478 }
2479}
2480
bc8d7dff
DL		 2481static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2482{
2483 switch (format) {
2484 case PLANE_CTL_FORMAT_RGB_565:
2485 return DRM_FORMAT_RGB565;
2486 default:
2487 case PLANE_CTL_FORMAT_XRGB_8888:
2488 if (rgb_order) {
2489 if (alpha)
2490 return DRM_FORMAT_ABGR8888;
2491 else
2492 return DRM_FORMAT_XBGR8888;
2493 } else {
2494 if (alpha)
2495 return DRM_FORMAT_ARGB8888;
2496 else
2497 return DRM_FORMAT_XRGB8888;
2498 }
2499 case PLANE_CTL_FORMAT_XRGB_2101010:
2500 if (rgb_order)
2501 return DRM_FORMAT_XBGR2101010;
2502 else
2503 return DRM_FORMAT_XRGB2101010;
2504 }
2505}
2506
5724dbd1 2507static bool
f6936e29
DV		 2508intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2509 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2510{
2511 struct drm_device *dev = crtc->base.dev;
3badb49f 2512 struct drm_i915_private *dev_priv = to_i915(dev);
46f297fb
JB		 2513 struct drm_i915_gem_object *obj = NULL;
2514 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2515 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2516 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2517 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2518 PAGE_SIZE);
2519
2520 size_aligned -= base_aligned;
46f297fb 2521
ff2652ea
CW		 2522 if (plane_config->size == 0)
2523 return false;
2524
3badb49f
PZ		 2525 /* If the FB is too big, just don't use it since fbdev is not very
2526 * important and we should probably use that space with FBC or other
2527 * features. */
2528 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2529 return false;
2530
f37b5c2b
DV		 2531 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2532 base_aligned,
2533 base_aligned,
2534 size_aligned);
46f297fb 2535 if (!obj)
484b41dd 2536 return false;
46f297fb 2537
49af449b
DL		 2538 obj->tiling_mode = plane_config->tiling;
2539 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2540 obj->stride = fb->pitches[0];
46f297fb 2541
6bf129df
DL		 2542 mode_cmd.pixel_format = fb->pixel_format;
2543 mode_cmd.width = fb->width;
2544 mode_cmd.height = fb->height;
2545 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2546 mode_cmd.modifier[0] = fb->modifier[0];
2547 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2548
2549 mutex_lock(&dev->struct_mutex);
6bf129df 2550 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2551 &mode_cmd, obj)) {
46f297fb
JB		 2552 DRM_DEBUG_KMS("intel fb init failed\n");
2553 goto out_unref_obj;
2554 }
46f297fb 2555 mutex_unlock(&dev->struct_mutex);
484b41dd 2556
f6936e29 2557 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2558 return true;
46f297fb
JB		 2559
2560out_unref_obj:
2561 drm_gem_object_unreference(&obj->base);
2562 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2563 return false;
2564}
2565
afd65eb4
MR		 2566/* Update plane->state->fb to match plane->fb after driver-internal updates */
2567static void
2568update_state_fb(struct drm_plane *plane)
2569{
2570 if (plane->fb == plane->state->fb)
2571 return;
2572
2573 if (plane->state->fb)
2574 drm_framebuffer_unreference(plane->state->fb);
2575 plane->state->fb = plane->fb;
2576 if (plane->state->fb)
2577 drm_framebuffer_reference(plane->state->fb);
2578}
2579
5724dbd1 2580static void
f6936e29
DV		 2581intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2582 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2583{
2584 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2585 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2586 struct drm_crtc *c;
2587 struct intel_crtc *i;
2ff8fde1 2588 struct drm_i915_gem_object *obj;
88595ac9 2589 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2590 struct drm_plane_state *plane_state = primary->state;
88595ac9 2591 struct drm_framebuffer *fb;
484b41dd 2592
2d14030b 2593 if (!plane_config->fb)
484b41dd
JB		 2594 return;
2595
f6936e29 2596 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2597 fb = &plane_config->fb->base;
2598 goto valid_fb;
f55548b5 2599 }
484b41dd 2600
2d14030b 2601 kfree(plane_config->fb);
484b41dd
JB		 2602
2603 /*
2604 * Failed to alloc the obj, check to see if we should share
2605 * an fb with another CRTC instead
2606 */
70e1e0ec 2607 for_each_crtc(dev, c) {
484b41dd
JB		 2608 i = to_intel_crtc(c);
2609
2610 if (c == &intel_crtc->base)
2611 continue;
2612
2ff8fde1
MR		 2613 if (!i->active)
2614 continue;
2615
88595ac9
DV		 2616 fb = c->primary->fb;
2617 if (!fb)
484b41dd
JB		 2618 continue;
2619
88595ac9 2620 obj = intel_fb_obj(fb);
2ff8fde1 2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2622 drm_framebuffer_reference(fb);
2623 goto valid_fb;
484b41dd
JB		 2624 }
2625 }
88595ac9
DV		 2626
2627 return;
2628
2629valid_fb:
be5651f2
ML		 2630 plane_state->src_x = plane_state->src_y = 0;
2631 plane_state->src_w = fb->width << 16;
2632 plane_state->src_h = fb->height << 16;
2633
2634 plane_state->crtc_x = plane_state->src_y = 0;
2635 plane_state->crtc_w = fb->width;
2636 plane_state->crtc_h = fb->height;
2637
88595ac9
DV		 2638 obj = intel_fb_obj(fb);
2639 if (obj->tiling_mode != I915_TILING_NONE)
2640 dev_priv->preserve_bios_swizzle = true;
2641
be5651f2
ML		 2642 drm_framebuffer_reference(fb);
2643 primary->fb = primary->state->fb = fb;
36750f28 2644 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2645 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2646 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2647}
2648
29b9bde6
DV		 2649static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650 struct drm_framebuffer *fb,
2651 int x, int y)
81255565
JB		 2652{
2653 struct drm_device *dev = crtc->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2656 struct drm_plane *primary = crtc->primary;
2657 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2658 struct drm_i915_gem_object *obj;
81255565 2659 int plane = intel_crtc->plane;
e506a0c6 2660 unsigned long linear_offset;
81255565 2661 u32 dspcntr;
f45651ba 2662 u32 reg = DSPCNTR(plane);
48404c1e 2663 int pixel_size;
f45651ba 2664
b70709a6 2665 if (!visible || !fb) {
fdd508a6
VS		 2666 I915_WRITE(reg, 0);
2667 if (INTEL_INFO(dev)->gen >= 4)
2668 I915_WRITE(DSPSURF(plane), 0);
2669 else
2670 I915_WRITE(DSPADDR(plane), 0);
2671 POSTING_READ(reg);
2672 return;
2673 }
2674
c9ba6fad
VS		 2675 obj = intel_fb_obj(fb);
2676 if (WARN_ON(obj == NULL))
2677 return;
2678
2679 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
f45651ba
VS		 2681 dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
fdd508a6 2683 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2684
2685 if (INTEL_INFO(dev)->gen < 4) {
2686 if (intel_crtc->pipe == PIPE_B)
2687 dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689 /* pipesrc and dspsize control the size that is scaled from,
2690 * which should always be the user's requested size.
2691 */
2692 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2695 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2696 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2698 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2700 I915_WRITE(PRIMPOS(plane), 0);
2701 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2702 }
81255565 2703
57779d06
VS		 2704 switch (fb->pixel_format) {
2705 case DRM_FORMAT_C8:
81255565
JB		 2706 dspcntr |= DISPPLANE_8BPP;
2707 break;
57779d06 2708 case DRM_FORMAT_XRGB1555:
57779d06 2709 dspcntr |= DISPPLANE_BGRX555;
81255565 2710 break;
57779d06
VS		 2711 case DRM_FORMAT_RGB565:
2712 dspcntr |= DISPPLANE_BGRX565;
2713 break;
2714 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
57779d06 2724 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2725 break;
2726 default:
baba133a 2727 BUG();
81255565 2728 }
57779d06 2729
f45651ba
VS		 2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
81255565 2733
de1aa629
VS		 2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
b9897127 2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2738
c2c75131
DV		 2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2741 intel_gen4_compute_page_offset(dev_priv,
2742 &x, &y, obj->tiling_mode,
b9897127 2743 pixel_size,
bc752862 2744 fb->pitches[0]);
c2c75131
DV		 2745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
e506a0c6 2747 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2748 }
e506a0c6 2749
8e7d688b 2750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2751 dspcntr |= DISPPLANE_ROTATE_180;
2752
6e3c9717
ACO		 2753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
6e3c9717
ACO		 2759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2761 }
2762
2db3366b
PZ		 2763 intel_crtc->adjusted_x = x;
2764 intel_crtc->adjusted_y = y;
2765
48404c1e
SJ		 2766 I915_WRITE(reg, dspcntr);
2767
01f2c773 2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2769 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2770 I915_WRITE(DSPSURF(plane),
2771 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2772 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2773 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2774 } else
f343c5f6 2775 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2776 POSTING_READ(reg);
17638cd6
JB		 2777}
2778
29b9bde6
DV		 2779static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2781 int x, int y)
17638cd6
JB		 2782{
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2786 struct drm_plane *primary = crtc->primary;
2787 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2788 struct drm_i915_gem_object *obj;
17638cd6 2789 int plane = intel_crtc->plane;
e506a0c6 2790 unsigned long linear_offset;
17638cd6 2791 u32 dspcntr;
f45651ba 2792 u32 reg = DSPCNTR(plane);
48404c1e 2793 int pixel_size;
f45651ba 2794
b70709a6 2795 if (!visible || !fb) {
fdd508a6
VS		 2796 I915_WRITE(reg, 0);
2797 I915_WRITE(DSPSURF(plane), 0);
2798 POSTING_READ(reg);
2799 return;
2800 }
2801
c9ba6fad
VS		 2802 obj = intel_fb_obj(fb);
2803 if (WARN_ON(obj == NULL))
2804 return;
2805
2806 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2807
f45651ba
VS		 2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2809
fdd508a6 2810 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2811
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2814
57779d06
VS		 2815 switch (fb->pixel_format) {
2816 case DRM_FORMAT_C8:
17638cd6
JB		 2817 dspcntr |= DISPPLANE_8BPP;
2818 break;
57779d06
VS		 2819 case DRM_FORMAT_RGB565:
2820 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2821 break;
57779d06 2822 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2823 dspcntr |= DISPPLANE_BGRX888;
2824 break;
2825 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2826 dspcntr |= DISPPLANE_RGBX888;
2827 break;
2828 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
57779d06 2832 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2833 break;
2834 default:
baba133a 2835 BUG();
17638cd6
JB		 2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
17638cd6 2840
f45651ba 2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2843
b9897127 2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2845 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2846 intel_gen4_compute_page_offset(dev_priv,
2847 &x, &y, obj->tiling_mode,
b9897127 2848 pixel_size,
bc752862 2849 fb->pitches[0]);
c2c75131 2850 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
6e3c9717
ACO		 2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2863 }
2864 }
2865
2db3366b
PZ		 2866 intel_crtc->adjusted_x = x;
2867 intel_crtc->adjusted_y = y;
2868
48404c1e 2869 I915_WRITE(reg, dspcntr);
17638cd6 2870
01f2c773 2871 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2872 I915_WRITE(DSPSURF(plane),
2873 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2874 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2875 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2876 } else {
2877 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2878 I915_WRITE(DSPLINOFF(plane), linear_offset);
2879 }
17638cd6 2880 POSTING_READ(reg);
17638cd6
JB		 2881}
2882
b321803d
DL		 2883u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2884 uint32_t pixel_format)
2885{
2886 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2887
2888 /*
2889 * The stride is either expressed as a multiple of 64 bytes
2890 * chunks for linear buffers or in number of tiles for tiled
2891 * buffers.
2892 */
2893 switch (fb_modifier) {
2894 case DRM_FORMAT_MOD_NONE:
2895 return 64;
2896 case I915_FORMAT_MOD_X_TILED:
2897 if (INTEL_INFO(dev)->gen == 2)
2898 return 128;
2899 return 512;
2900 case I915_FORMAT_MOD_Y_TILED:
2901 /* No need to check for old gens and Y tiling since this is
2902 * about the display engine and those will be blocked before
2903 * we get here.
2904 */
2905 return 128;
2906 case I915_FORMAT_MOD_Yf_TILED:
2907 if (bits_per_pixel == 8)
2908 return 64;
2909 else
2910 return 128;
2911 default:
2912 MISSING_CASE(fb_modifier);
2913 return 64;
2914 }
2915}
2916
44eb0cb9
MK		 2917u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2918 struct drm_i915_gem_object *obj,
2919 unsigned int plane)
121920fa 2920{
9abc4648 2921 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
dedf278c 2922 struct i915_vma *vma;
44eb0cb9 2923 u64 offset;
121920fa
TU		 2924
2925 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2926 view = &i915_ggtt_view_rotated;
121920fa 2927
dedf278c
TU		 2928 vma = i915_gem_obj_to_ggtt_view(obj, view);
2929 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2930 view->type))
2931 return -1;
2932
44eb0cb9 2933 offset = vma->node.start;
dedf278c
TU		 2934
2935 if (plane == 1) {
2936 offset += vma->ggtt_view.rotation_info.uv_start_page *
2937 PAGE_SIZE;
2938 }
2939
44eb0cb9
MK		 2940 WARN_ON(upper_32_bits(offset));
2941
2942 return lower_32_bits(offset);
121920fa
TU		 2943}
2944
e435d6e5
ML		 2945static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2946{
2947 struct drm_device *dev = intel_crtc->base.dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949
2950 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2951 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2952 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2953}
2954
a1b2278e
CK		 2955/*
2956 * This function detaches (aka. unbinds) unused scalers in hardware
2957 */
0583236e 2958static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2959{
a1b2278e
CK		 2960 struct intel_crtc_scaler_state *scaler_state;
2961 int i;
2962
a1b2278e
CK		 2963 scaler_state = &intel_crtc->config->scaler_state;
2964
2965 /* loop through and disable scalers that aren't in use */
2966 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2967 if (!scaler_state->scalers[i].in_use)
2968 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2969 }
2970}
2971
6156a456 2972u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2973{
6156a456 2974 switch (pixel_format) {
d161cf7a 2975 case DRM_FORMAT_C8:
c34ce3d1 2976 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2977 case DRM_FORMAT_RGB565:
c34ce3d1 2978 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2979 case DRM_FORMAT_XBGR8888:
c34ce3d1 2980 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2981 case DRM_FORMAT_XRGB8888:
c34ce3d1 2982 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2983 /*
2984 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2985 * to be already pre-multiplied. We need to add a knob (or a different
2986 * DRM_FORMAT) for user-space to configure that.
2987 */
f75fb42a 2988 case DRM_FORMAT_ABGR8888:
c34ce3d1 2989 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2990 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2991 case DRM_FORMAT_ARGB8888:
c34ce3d1 2992 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2993 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2994 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2995 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2996 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2997 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2998 case DRM_FORMAT_YUYV:
c34ce3d1 2999 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 3000 case DRM_FORMAT_YVYU:
c34ce3d1 3001 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3002 case DRM_FORMAT_UYVY:
c34ce3d1 3003 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3004 case DRM_FORMAT_VYUY:
c34ce3d1 3005 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3006 default:
4249eeef 3007 MISSING_CASE(pixel_format);
70d21f0e 3008 }
8cfcba41 3009
c34ce3d1 3010 return 0;
6156a456 3011}
70d21f0e 3012
6156a456
CK		 3013u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3014{
6156a456 3015 switch (fb_modifier) {
30af77c4 3016 case DRM_FORMAT_MOD_NONE:
70d21f0e 3017 break;
30af77c4 3018 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3019 return PLANE_CTL_TILED_X;
b321803d 3020 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3021 return PLANE_CTL_TILED_Y;
b321803d 3022 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3023 return PLANE_CTL_TILED_YF;
70d21f0e 3024 default:
6156a456 3025 MISSING_CASE(fb_modifier);
70d21f0e 3026 }
8cfcba41 3027
c34ce3d1 3028 return 0;
6156a456 3029}
70d21f0e 3030
6156a456
CK		 3031u32 skl_plane_ctl_rotation(unsigned int rotation)
3032{
3b7a5119 3033 switch (rotation) {
6156a456
CK		 3034 case BIT(DRM_ROTATE_0):
3035 break;
1e8df167
SJ		 3036 /*
3037 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3038 * while i915 HW rotation is clockwise, thats why this swapping.
3039 */
3b7a5119 3040 case BIT(DRM_ROTATE_90):
1e8df167 3041 return PLANE_CTL_ROTATE_270;
3b7a5119 3042 case BIT(DRM_ROTATE_180):
c34ce3d1 3043 return PLANE_CTL_ROTATE_180;
3b7a5119 3044 case BIT(DRM_ROTATE_270):
1e8df167 3045 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3046 default:
3047 MISSING_CASE(rotation);
3048 }
3049
c34ce3d1 3050 return 0;
6156a456
CK		 3051}
3052
3053static void skylake_update_primary_plane(struct drm_crtc *crtc,
3054 struct drm_framebuffer *fb,
3055 int x, int y)
3056{
3057 struct drm_device *dev = crtc->dev;
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3060 struct drm_plane *plane = crtc->primary;
3061 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3062 struct drm_i915_gem_object *obj;
3063 int pipe = intel_crtc->pipe;
3064 u32 plane_ctl, stride_div, stride;
3065 u32 tile_height, plane_offset, plane_size;
3066 unsigned int rotation;
3067 int x_offset, y_offset;
44eb0cb9 3068 u32 surf_addr;
6156a456
CK		 3069 struct intel_crtc_state *crtc_state = intel_crtc->config;
3070 struct intel_plane_state *plane_state;
3071 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3072 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3073 int scaler_id = -1;
3074
6156a456
CK		 3075 plane_state = to_intel_plane_state(plane->state);
3076
b70709a6 3077 if (!visible || !fb) {
6156a456
CK		 3078 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3079 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3080 POSTING_READ(PLANE_CTL(pipe, 0));
3081 return;
3b7a5119 3082 }
70d21f0e 3083
6156a456
CK		 3084 plane_ctl = PLANE_CTL_ENABLE |
3085 PLANE_CTL_PIPE_GAMMA_ENABLE |
3086 PLANE_CTL_PIPE_CSC_ENABLE;
3087
3088 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3089 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3090 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3091
3092 rotation = plane->state->rotation;
3093 plane_ctl |= skl_plane_ctl_rotation(rotation);
3094
b321803d
DL		 3095 obj = intel_fb_obj(fb);
3096 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3097 fb->pixel_format);
dedf278c 3098 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3099
a42e5a23
PZ		 3100 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3101
3102 scaler_id = plane_state->scaler_id;
3103 src_x = plane_state->src.x1 >> 16;
3104 src_y = plane_state->src.y1 >> 16;
3105 src_w = drm_rect_width(&plane_state->src) >> 16;
3106 src_h = drm_rect_height(&plane_state->src) >> 16;
3107 dst_x = plane_state->dst.x1;
3108 dst_y = plane_state->dst.y1;
3109 dst_w = drm_rect_width(&plane_state->dst);
3110 dst_h = drm_rect_height(&plane_state->dst);
3111
3112 WARN_ON(x != src_x || y != src_y);
6156a456 3113
3b7a5119
SJ		 3114 if (intel_rotation_90_or_270(rotation)) {
3115 /* stride = Surface height in tiles */
2614f17d 3116 tile_height = intel_tile_height(dev, fb->pixel_format,
fe47ea0c 3117 fb->modifier[0], 0);
3b7a5119 3118 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3119 x_offset = stride * tile_height - y - src_h;
3b7a5119 3120 y_offset = x;
6156a456 3121 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3122 } else {
3123 stride = fb->pitches[0] / stride_div;
3124 x_offset = x;
3125 y_offset = y;
6156a456 3126 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3127 }
3128 plane_offset = y_offset << 16 | x_offset;
b321803d 3129
2db3366b
PZ		 3130 intel_crtc->adjusted_x = x_offset;
3131 intel_crtc->adjusted_y = y_offset;
3132
70d21f0e 3133 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3134 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3135 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3136 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3137
3138 if (scaler_id >= 0) {
3139 uint32_t ps_ctrl = 0;
3140
3141 WARN_ON(!dst_w || !dst_h);
3142 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3143 crtc_state->scaler_state.scalers[scaler_id].mode;
3144 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3145 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3146 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3147 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3148 I915_WRITE(PLANE_POS(pipe, 0), 0);
3149 } else {
3150 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3151 }
3152
121920fa 3153 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3154
3155 POSTING_READ(PLANE_SURF(pipe, 0));
3156}
3157
17638cd6
JB		 3158/* Assume fb object is pinned & idle & fenced and just update base pointers */
3159static int
3160intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3161 int x, int y, enum mode_set_atomic state)
3162{
3163 struct drm_device *dev = crtc->dev;
3164 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3165
ff2a3117 3166 if (dev_priv->fbc.disable_fbc)
7733b49b 3167 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3168
29b9bde6
DV		 3169 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3170
3171 return 0;
81255565
JB		 3172}
3173
7514747d 3174static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3175{
96a02917
VS		 3176 struct drm_crtc *crtc;
3177
70e1e0ec 3178 for_each_crtc(dev, crtc) {
96a02917
VS		 3179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3180 enum plane plane = intel_crtc->plane;
3181
3182 intel_prepare_page_flip(dev, plane);
3183 intel_finish_page_flip_plane(dev, plane);
3184 }
7514747d
VS		 3185}
3186
3187static void intel_update_primary_planes(struct drm_device *dev)
3188{
7514747d 3189 struct drm_crtc *crtc;
96a02917 3190
70e1e0ec 3191 for_each_crtc(dev, crtc) {
11c22da6
ML		 3192 struct intel_plane *plane = to_intel_plane(crtc->primary);
3193 struct intel_plane_state *plane_state;
96a02917 3194
11c22da6 3195 drm_modeset_lock_crtc(crtc, &plane->base);
11c22da6
ML		 3196 plane_state = to_intel_plane_state(plane->base.state);
3197
f029ee82 3198 if (crtc->state->active && plane_state->base.fb)
11c22da6
ML		 3199 plane->commit_plane(&plane->base, plane_state);
3200
3201 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3202 }
3203}
3204
7514747d
VS		 3205void intel_prepare_reset(struct drm_device *dev)
3206{
3207 /* no reset support for gen2 */
3208 if (IS_GEN2(dev))
3209 return;
3210
3211 /* reset doesn't touch the display */
3212 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3213 return;
3214
3215 drm_modeset_lock_all(dev);
f98ce92f
VS		 3216 /*
3217 * Disabling the crtcs gracefully seems nicer. Also the
3218 * g33 docs say we should at least disable all the planes.
3219 */
6b72d486 3220 intel_display_suspend(dev);
7514747d
VS		 3221}
3222
3223void intel_finish_reset(struct drm_device *dev)
3224{
3225 struct drm_i915_private *dev_priv = to_i915(dev);
3226
3227 /*
3228 * Flips in the rings will be nuked by the reset,
3229 * so complete all pending flips so that user space
3230 * will get its events and not get stuck.
3231 */
3232 intel_complete_page_flips(dev);
3233
3234 /* no reset support for gen2 */
3235 if (IS_GEN2(dev))
3236 return;
3237
3238 /* reset doesn't touch the display */
3239 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3240 /*
3241 * Flips in the rings have been nuked by the reset,
3242 * so update the base address of all primary
3243 * planes to the the last fb to make sure we're
3244 * showing the correct fb after a reset.
11c22da6
ML		 3245 *
3246 * FIXME: Atomic will make this obsolete since we won't schedule
3247 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3248 */
3249 intel_update_primary_planes(dev);
3250 return;
3251 }
3252
3253 /*
3254 * The display has been reset as well,
3255 * so need a full re-initialization.
3256 */
3257 intel_runtime_pm_disable_interrupts(dev_priv);
3258 intel_runtime_pm_enable_interrupts(dev_priv);
3259
3260 intel_modeset_init_hw(dev);
3261
3262 spin_lock_irq(&dev_priv->irq_lock);
3263 if (dev_priv->display.hpd_irq_setup)
3264 dev_priv->display.hpd_irq_setup(dev);
3265 spin_unlock_irq(&dev_priv->irq_lock);
3266
043e9bda 3267 intel_display_resume(dev);
7514747d
VS		 3268
3269 intel_hpd_init(dev_priv);
3270
3271 drm_modeset_unlock_all(dev);
3272}
3273
7d5e3799
CW		 3274static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3275{
3276 struct drm_device *dev = crtc->dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3279 bool pending;
3280
3281 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3282 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3283 return false;
3284
5e2d7afc 3285 spin_lock_irq(&dev->event_lock);
7d5e3799 3286 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3287 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3288
3289 return pending;
3290}
3291
bfd16b2a
ML		 3292static void intel_update_pipe_config(struct intel_crtc *crtc,
3293 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3294{
3295 struct drm_device *dev = crtc->base.dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3297 struct intel_crtc_state *pipe_config =
3298 to_intel_crtc_state(crtc->base.state);
e30e8f75 3299
bfd16b2a
ML		 3300 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3301 crtc->base.mode = crtc->base.state->mode;
3302
3303 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3304 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3305 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3306
44522d85
ML		 3307 if (HAS_DDI(dev))
3308 intel_set_pipe_csc(&crtc->base);
3309
e30e8f75
GP		 3310 /*
3311 * Update pipe size and adjust fitter if needed: the reason for this is
3312 * that in compute_mode_changes we check the native mode (not the pfit
3313 * mode) to see if we can flip rather than do a full mode set. In the
3314 * fastboot case, we'll flip, but if we don't update the pipesrc and
3315 * pfit state, we'll end up with a big fb scanned out into the wrong
3316 * sized surface.
e30e8f75
GP		 3317 */
3318
e30e8f75 3319 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3320 ((pipe_config->pipe_src_w - 1) << 16) |
3321 (pipe_config->pipe_src_h - 1));
3322
3323 /* on skylake this is done by detaching scalers */
3324 if (INTEL_INFO(dev)->gen >= 9) {
3325 skl_detach_scalers(crtc);
3326
3327 if (pipe_config->pch_pfit.enabled)
3328 skylake_pfit_enable(crtc);
3329 } else if (HAS_PCH_SPLIT(dev)) {
3330 if (pipe_config->pch_pfit.enabled)
3331 ironlake_pfit_enable(crtc);
3332 else if (old_crtc_state->pch_pfit.enabled)
3333 ironlake_pfit_disable(crtc, true);
e30e8f75 3334 }
e30e8f75
GP		 3335}
3336
5e84e1a4
ZW		 3337static void intel_fdi_normal_train(struct drm_crtc *crtc)
3338{
3339 struct drm_device *dev = crtc->dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3342 int pipe = intel_crtc->pipe;
3343 u32 reg, temp;
3344
3345 /* enable normal train */
3346 reg = FDI_TX_CTL(pipe);
3347 temp = I915_READ(reg);
61e499bf 3348 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3349 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3351 } else {
3352 temp &= ~FDI_LINK_TRAIN_NONE;
3353 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3354 }
5e84e1a4
ZW		 3355 I915_WRITE(reg, temp);
3356
3357 reg = FDI_RX_CTL(pipe);
3358 temp = I915_READ(reg);
3359 if (HAS_PCH_CPT(dev)) {
3360 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3361 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3362 } else {
3363 temp &= ~FDI_LINK_TRAIN_NONE;
3364 temp |= FDI_LINK_TRAIN_NONE;
3365 }
3366 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3367
3368 /* wait one idle pattern time */
3369 POSTING_READ(reg);
3370 udelay(1000);
357555c0
JB		 3371
3372 /* IVB wants error correction enabled */
3373 if (IS_IVYBRIDGE(dev))
3374 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3375 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3376}
3377
8db9d77b
ZW		 3378/* The FDI link training functions for ILK/Ibexpeak. */
3379static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3384 int pipe = intel_crtc->pipe;
5eddb70b 3385 u32 reg, temp, tries;
8db9d77b 3386
1c8562f6 3387 /* FDI needs bits from pipe first */
0fc932b8 3388 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3389
e1a44743
AJ		 3390 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3391 for train result */
5eddb70b
CW		 3392 reg = FDI_RX_IMR(pipe);
3393 temp = I915_READ(reg);
e1a44743
AJ		 3394 temp &= ~FDI_RX_SYMBOL_LOCK;
3395 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3396 I915_WRITE(reg, temp);
3397 I915_READ(reg);
e1a44743
AJ		 3398 udelay(150);
3399
8db9d77b 3400 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3401 reg = FDI_TX_CTL(pipe);
3402 temp = I915_READ(reg);
627eb5a3 3403 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3404 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3405 temp &= ~FDI_LINK_TRAIN_NONE;
3406 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3407 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3408
5eddb70b
CW		 3409 reg = FDI_RX_CTL(pipe);
3410 temp = I915_READ(reg);
8db9d77b
ZW		 3411 temp &= ~FDI_LINK_TRAIN_NONE;
3412 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3413 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3414
3415 POSTING_READ(reg);
8db9d77b
ZW		 3416 udelay(150);
3417
5b2adf89 3418 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3420 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3421 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3422
5eddb70b 3423 reg = FDI_RX_IIR(pipe);
e1a44743 3424 for (tries = 0; tries < 5; tries++) {
5eddb70b 3425 temp = I915_READ(reg);
8db9d77b
ZW		 3426 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3427
3428 if ((temp & FDI_RX_BIT_LOCK)) {
3429 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3430 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3431 break;
3432 }
8db9d77b 3433 }
e1a44743 3434 if (tries == 5)
5eddb70b 3435 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3436
3437 /* Train 2 */
5eddb70b
CW		 3438 reg = FDI_TX_CTL(pipe);
3439 temp = I915_READ(reg);
8db9d77b
ZW		 3440 temp &= ~FDI_LINK_TRAIN_NONE;
3441 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3442 I915_WRITE(reg, temp);
8db9d77b 3443
5eddb70b
CW		 3444 reg = FDI_RX_CTL(pipe);
3445 temp = I915_READ(reg);
8db9d77b
ZW		 3446 temp &= ~FDI_LINK_TRAIN_NONE;
3447 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3448 I915_WRITE(reg, temp);
8db9d77b 3449
5eddb70b
CW		 3450 POSTING_READ(reg);
3451 udelay(150);
8db9d77b 3452
5eddb70b 3453 reg = FDI_RX_IIR(pipe);
e1a44743 3454 for (tries = 0; tries < 5; tries++) {
5eddb70b 3455 temp = I915_READ(reg);
8db9d77b
ZW		 3456 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3457
3458 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3459 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3460 DRM_DEBUG_KMS("FDI train 2 done.\n");
3461 break;
3462 }
8db9d77b 3463 }
e1a44743 3464 if (tries == 5)
5eddb70b 3465 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3466
3467 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3468
8db9d77b
ZW		 3469}
3470
0206e353 3471static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3472 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3473 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3474 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3475 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3476};
3477
3478/* The FDI link training functions for SNB/Cougarpoint. */
3479static void gen6_fdi_link_train(struct drm_crtc *crtc)
3480{
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484 int pipe = intel_crtc->pipe;
fa37d39e 3485 u32 reg, temp, i, retry;
8db9d77b 3486
e1a44743
AJ		 3487 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3488 for train result */
5eddb70b
CW		 3489 reg = FDI_RX_IMR(pipe);
3490 temp = I915_READ(reg);
e1a44743
AJ		 3491 temp &= ~FDI_RX_SYMBOL_LOCK;
3492 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3493 I915_WRITE(reg, temp);
3494
3495 POSTING_READ(reg);
e1a44743
AJ		 3496 udelay(150);
3497
8db9d77b 3498 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3499 reg = FDI_TX_CTL(pipe);
3500 temp = I915_READ(reg);
627eb5a3 3501 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3502 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3503 temp &= ~FDI_LINK_TRAIN_NONE;
3504 temp |= FDI_LINK_TRAIN_PATTERN_1;
3505 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3506 /* SNB-B */
3507 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3508 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3509
d74cf324
DV		 3510 I915_WRITE(FDI_RX_MISC(pipe),
3511 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3512
5eddb70b
CW		 3513 reg = FDI_RX_CTL(pipe);
3514 temp = I915_READ(reg);
8db9d77b
ZW		 3515 if (HAS_PCH_CPT(dev)) {
3516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3518 } else {
3519 temp &= ~FDI_LINK_TRAIN_NONE;
3520 temp |= FDI_LINK_TRAIN_PATTERN_1;
3521 }
5eddb70b
CW		 3522 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3523
3524 POSTING_READ(reg);
8db9d77b
ZW		 3525 udelay(150);
3526
0206e353 3527 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3531 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3532 I915_WRITE(reg, temp);
3533
3534 POSTING_READ(reg);
8db9d77b
ZW		 3535 udelay(500);
3536
fa37d39e
SP		 3537 for (retry = 0; retry < 5; retry++) {
3538 reg = FDI_RX_IIR(pipe);
3539 temp = I915_READ(reg);
3540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3541 if (temp & FDI_RX_BIT_LOCK) {
3542 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3543 DRM_DEBUG_KMS("FDI train 1 done.\n");
3544 break;
3545 }
3546 udelay(50);
8db9d77b 3547 }
fa37d39e
SP		 3548 if (retry < 5)
3549 break;
8db9d77b
ZW		 3550 }
3551 if (i == 4)
5eddb70b 3552 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3553
3554 /* Train 2 */
5eddb70b
CW		 3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
8db9d77b
ZW		 3557 temp &= ~FDI_LINK_TRAIN_NONE;
3558 temp |= FDI_LINK_TRAIN_PATTERN_2;
3559 if (IS_GEN6(dev)) {
3560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561 /* SNB-B */
3562 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3563 }
5eddb70b 3564 I915_WRITE(reg, temp);
8db9d77b 3565
5eddb70b
CW		 3566 reg = FDI_RX_CTL(pipe);
3567 temp = I915_READ(reg);
8db9d77b
ZW		 3568 if (HAS_PCH_CPT(dev)) {
3569 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3570 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3571 } else {
3572 temp &= ~FDI_LINK_TRAIN_NONE;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2;
3574 }
5eddb70b
CW		 3575 I915_WRITE(reg, temp);
3576
3577 POSTING_READ(reg);
8db9d77b
ZW		 3578 udelay(150);
3579
0206e353 3580 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3581 reg = FDI_TX_CTL(pipe);
3582 temp = I915_READ(reg);
8db9d77b
ZW		 3583 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3584 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3585 I915_WRITE(reg, temp);
3586
3587 POSTING_READ(reg);
8db9d77b
ZW		 3588 udelay(500);
3589
fa37d39e
SP		 3590 for (retry = 0; retry < 5; retry++) {
3591 reg = FDI_RX_IIR(pipe);
3592 temp = I915_READ(reg);
3593 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3594 if (temp & FDI_RX_SYMBOL_LOCK) {
3595 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3596 DRM_DEBUG_KMS("FDI train 2 done.\n");
3597 break;
3598 }
3599 udelay(50);
8db9d77b 3600 }
fa37d39e
SP		 3601 if (retry < 5)
3602 break;
8db9d77b
ZW		 3603 }
3604 if (i == 4)
5eddb70b 3605 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3606
3607 DRM_DEBUG_KMS("FDI train done.\n");
3608}
3609
357555c0
JB		 3610/* Manual link training for Ivy Bridge A0 parts */
3611static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3612{
3613 struct drm_device *dev = crtc->dev;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616 int pipe = intel_crtc->pipe;
139ccd3f 3617 u32 reg, temp, i, j;
357555c0
JB		 3618
3619 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3620 for train result */
3621 reg = FDI_RX_IMR(pipe);
3622 temp = I915_READ(reg);
3623 temp &= ~FDI_RX_SYMBOL_LOCK;
3624 temp &= ~FDI_RX_BIT_LOCK;
3625 I915_WRITE(reg, temp);
3626
3627 POSTING_READ(reg);
3628 udelay(150);
3629
01a415fd
DV		 3630 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3631 I915_READ(FDI_RX_IIR(pipe)));
3632
139ccd3f
JB		 3633 /* Try each vswing and preemphasis setting twice before moving on */
3634 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3635 /* disable first in case we need to retry */
3636 reg = FDI_TX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3639 temp &= ~FDI_TX_ENABLE;
3640 I915_WRITE(reg, temp);
357555c0 3641
139ccd3f
JB		 3642 reg = FDI_RX_CTL(pipe);
3643 temp = I915_READ(reg);
3644 temp &= ~FDI_LINK_TRAIN_AUTO;
3645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3646 temp &= ~FDI_RX_ENABLE;
3647 I915_WRITE(reg, temp);
357555c0 3648
139ccd3f 3649 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3650 reg = FDI_TX_CTL(pipe);
3651 temp = I915_READ(reg);
139ccd3f 3652 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3653 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3654 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3656 temp |= snb_b_fdi_train_param[j/2];
3657 temp |= FDI_COMPOSITE_SYNC;
3658 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3659
139ccd3f
JB		 3660 I915_WRITE(FDI_RX_MISC(pipe),
3661 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3662
139ccd3f 3663 reg = FDI_RX_CTL(pipe);
357555c0 3664 temp = I915_READ(reg);
139ccd3f
JB		 3665 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3666 temp |= FDI_COMPOSITE_SYNC;
3667 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3668
139ccd3f
JB		 3669 POSTING_READ(reg);
3670 udelay(1); /* should be 0.5us */
357555c0 3671
139ccd3f
JB		 3672 for (i = 0; i < 4; i++) {
3673 reg = FDI_RX_IIR(pipe);
3674 temp = I915_READ(reg);
3675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3676
139ccd3f
JB		 3677 if (temp & FDI_RX_BIT_LOCK ||
3678 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3679 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3680 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3681 i);
3682 break;
3683 }
3684 udelay(1); /* should be 0.5us */
3685 }
3686 if (i == 4) {
3687 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3688 continue;
3689 }
357555c0 3690
139ccd3f 3691 /* Train 2 */
357555c0
JB		 3692 reg = FDI_TX_CTL(pipe);
3693 temp = I915_READ(reg);
139ccd3f
JB		 3694 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3695 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3696 I915_WRITE(reg, temp);
3697
3698 reg = FDI_RX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3701 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3702 I915_WRITE(reg, temp);
3703
3704 POSTING_READ(reg);
139ccd3f 3705 udelay(2); /* should be 1.5us */
357555c0 3706
139ccd3f
JB		 3707 for (i = 0; i < 4; i++) {
3708 reg = FDI_RX_IIR(pipe);
3709 temp = I915_READ(reg);
3710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3711
139ccd3f
JB		 3712 if (temp & FDI_RX_SYMBOL_LOCK ||
3713 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3714 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3715 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3716 i);
3717 goto train_done;
3718 }
3719 udelay(2); /* should be 1.5us */
357555c0 3720 }
139ccd3f
JB		 3721 if (i == 4)
3722 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3723 }
357555c0 3724
139ccd3f 3725train_done:
357555c0
JB		 3726 DRM_DEBUG_KMS("FDI train done.\n");
3727}
3728
88cefb6c 3729static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3730{
88cefb6c 3731 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3732 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3733 int pipe = intel_crtc->pipe;
5eddb70b 3734 u32 reg, temp;
79e53945 3735
c64e311e 3736
c98e9dcf 3737 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3738 reg = FDI_RX_CTL(pipe);
3739 temp = I915_READ(reg);
627eb5a3 3740 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3741 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3742 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3743 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3744
3745 POSTING_READ(reg);
c98e9dcf
JB		 3746 udelay(200);
3747
3748 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3749 temp = I915_READ(reg);
3750 I915_WRITE(reg, temp | FDI_PCDCLK);
3751
3752 POSTING_READ(reg);
c98e9dcf
JB		 3753 udelay(200);
3754
20749730
PZ		 3755 /* Enable CPU FDI TX PLL, always on for Ironlake */
3756 reg = FDI_TX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3759 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3760
20749730
PZ		 3761 POSTING_READ(reg);
3762 udelay(100);
6be4a607 3763 }
0e23b99d
JB		 3764}
3765
88cefb6c
DV		 3766static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3767{
3768 struct drm_device *dev = intel_crtc->base.dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3770 int pipe = intel_crtc->pipe;
3771 u32 reg, temp;
3772
3773 /* Switch from PCDclk to Rawclk */
3774 reg = FDI_RX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3777
3778 /* Disable CPU FDI TX PLL */
3779 reg = FDI_TX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3782
3783 POSTING_READ(reg);
3784 udelay(100);
3785
3786 reg = FDI_RX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3789
3790 /* Wait for the clocks to turn off. */
3791 POSTING_READ(reg);
3792 udelay(100);
3793}
3794
0fc932b8
JB		 3795static void ironlake_fdi_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3800 int pipe = intel_crtc->pipe;
3801 u32 reg, temp;
3802
3803 /* disable CPU FDI tx and PCH FDI rx */
3804 reg = FDI_TX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3807 POSTING_READ(reg);
3808
3809 reg = FDI_RX_CTL(pipe);
3810 temp = I915_READ(reg);
3811 temp &= ~(0x7 << 16);
dfd07d72 3812 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3813 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3814
3815 POSTING_READ(reg);
3816 udelay(100);
3817
3818 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3819 if (HAS_PCH_IBX(dev))
6f06ce18 3820 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3821
3822 /* still set train pattern 1 */
3823 reg = FDI_TX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 temp &= ~FDI_LINK_TRAIN_NONE;
3826 temp |= FDI_LINK_TRAIN_PATTERN_1;
3827 I915_WRITE(reg, temp);
3828
3829 reg = FDI_RX_CTL(pipe);
3830 temp = I915_READ(reg);
3831 if (HAS_PCH_CPT(dev)) {
3832 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3833 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3834 } else {
3835 temp &= ~FDI_LINK_TRAIN_NONE;
3836 temp |= FDI_LINK_TRAIN_PATTERN_1;
3837 }
3838 /* BPC in FDI rx is consistent with that in PIPECONF */
3839 temp &= ~(0x07 << 16);
dfd07d72 3840 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3841 I915_WRITE(reg, temp);
3842
3843 POSTING_READ(reg);
3844 udelay(100);
3845}
3846
5dce5b93
CW		 3847bool intel_has_pending_fb_unpin(struct drm_device *dev)
3848{
3849 struct intel_crtc *crtc;
3850
3851 /* Note that we don't need to be called with mode_config.lock here
3852 * as our list of CRTC objects is static for the lifetime of the
3853 * device and so cannot disappear as we iterate. Similarly, we can
3854 * happily treat the predicates as racy, atomic checks as userspace
3855 * cannot claim and pin a new fb without at least acquring the
3856 * struct_mutex and so serialising with us.
3857 */
d3fcc808 3858 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3859 if (atomic_read(&crtc->unpin_work_count) == 0)
3860 continue;
3861
3862 if (crtc->unpin_work)
3863 intel_wait_for_vblank(dev, crtc->pipe);
3864
3865 return true;
3866 }
3867
3868 return false;
3869}
3870
d6bbafa1
CW		 3871static void page_flip_completed(struct intel_crtc *intel_crtc)
3872{
3873 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3874 struct intel_unpin_work *work = intel_crtc->unpin_work;
3875
3876 /* ensure that the unpin work is consistent wrt ->pending. */
3877 smp_rmb();
3878 intel_crtc->unpin_work = NULL;
3879
3880 if (work->event)
3881 drm_send_vblank_event(intel_crtc->base.dev,
3882 intel_crtc->pipe,
3883 work->event);
3884
3885 drm_crtc_vblank_put(&intel_crtc->base);
3886
3887 wake_up_all(&dev_priv->pending_flip_queue);
3888 queue_work(dev_priv->wq, &work->work);
3889
3890 trace_i915_flip_complete(intel_crtc->plane,
3891 work->pending_flip_obj);
3892}
3893
5008e874 3894static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3895{
0f91128d 3896 struct drm_device *dev = crtc->dev;
5bb61643 3897 struct drm_i915_private *dev_priv = dev->dev_private;
5008e874 3898 long ret;
e6c3a2a6 3899
2c10d571 3900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML		 3901
3902 ret = wait_event_interruptible_timeout(
3903 dev_priv->pending_flip_queue,
3904 !intel_crtc_has_pending_flip(crtc),
3905 60*HZ);
3906
3907 if (ret < 0)
3908 return ret;
3909
3910 if (ret == 0) {
9c787942 3911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3912
5e2d7afc 3913 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3914 if (intel_crtc->unpin_work) {
3915 WARN_ONCE(1, "Removing stuck page flip\n");
3916 page_flip_completed(intel_crtc);
3917 }
5e2d7afc 3918 spin_unlock_irq(&dev->event_lock);
9c787942 3919 }
5bb61643 3920
5008e874 3921 return 0;
e6c3a2a6
CW		 3922}
3923
e615efe4
ED		 3924/* Program iCLKIP clock to the desired frequency */
3925static void lpt_program_iclkip(struct drm_crtc *crtc)
3926{
3927 struct drm_device *dev = crtc->dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3929 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3930 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3931 u32 temp;
3932
a580516d 3933 mutex_lock(&dev_priv->sb_lock);
09153000 3934
e615efe4
ED		 3935 /* It is necessary to ungate the pixclk gate prior to programming
3936 * the divisors, and gate it back when it is done.
3937 */
3938 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3939
3940 /* Disable SSCCTL */
3941 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3942 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3943 SBI_SSCCTL_DISABLE,
3944 SBI_ICLK);
e615efe4
ED		 3945
3946 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3947 if (clock == 20000) {
e615efe4
ED		 3948 auxdiv = 1;
3949 divsel = 0x41;
3950 phaseinc = 0x20;
3951 } else {
3952 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3953 * but the adjusted_mode->crtc_clock in in KHz. To get the
3954 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3955 * convert the virtual clock precision to KHz here for higher
3956 * precision.
3957 */
3958 u32 iclk_virtual_root_freq = 172800 * 1000;
3959 u32 iclk_pi_range = 64;
3960 u32 desired_divisor, msb_divisor_value, pi_value;
3961
12d7ceed 3962 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3963 msb_divisor_value = desired_divisor / iclk_pi_range;
3964 pi_value = desired_divisor % iclk_pi_range;
3965
3966 auxdiv = 0;
3967 divsel = msb_divisor_value - 2;
3968 phaseinc = pi_value;
3969 }
3970
3971 /* This should not happen with any sane values */
3972 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3973 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3974 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3975 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3976
3977 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3978 clock,
e615efe4
ED		 3979 auxdiv,
3980 divsel,
3981 phasedir,
3982 phaseinc);
3983
3984 /* Program SSCDIVINTPHASE6 */
988d6ee8 3985 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3986 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3987 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3988 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3989 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3990 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3991 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3992 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3993
3994 /* Program SSCAUXDIV */
988d6ee8 3995 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3996 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3997 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3998 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3999
4000 /* Enable modulator and associated divider */
988d6ee8 4001 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4002 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4003 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4004
4005 /* Wait for initialization time */
4006 udelay(24);
4007
4008 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4009
a580516d 4010 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4011}
4012
275f01b2
DV		 4013static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4014 enum pipe pch_transcoder)
4015{
4016 struct drm_device *dev = crtc->base.dev;
4017 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4018 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4019
4020 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4021 I915_READ(HTOTAL(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4023 I915_READ(HBLANK(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4025 I915_READ(HSYNC(cpu_transcoder)));
4026
4027 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4028 I915_READ(VTOTAL(cpu_transcoder)));
4029 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4030 I915_READ(VBLANK(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4032 I915_READ(VSYNC(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4034 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4035}
4036
003632d9 4037static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4038{
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 uint32_t temp;
4041
4042 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4043 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4044 return;
4045
4046 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4047 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4048
003632d9
ACO		 4049 temp &= ~FDI_BC_BIFURCATION_SELECT;
4050 if (enable)
4051 temp |= FDI_BC_BIFURCATION_SELECT;
4052
4053 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4054 I915_WRITE(SOUTH_CHICKEN1, temp);
4055 POSTING_READ(SOUTH_CHICKEN1);
4056}
4057
4058static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4059{
4060 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4061
4062 switch (intel_crtc->pipe) {
4063 case PIPE_A:
4064 break;
4065 case PIPE_B:
6e3c9717 4066 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4067 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4068 else
003632d9 4069 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4070
4071 break;
4072 case PIPE_C:
003632d9 4073 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4074
4075 break;
4076 default:
4077 BUG();
4078 }
4079}
4080
f67a559d
JB		 4081/*
4082 * Enable PCH resources required for PCH ports:
4083 * - PCH PLLs
4084 * - FDI training & RX/TX
4085 * - update transcoder timings
4086 * - DP transcoding bits
4087 * - transcoder
4088 */
4089static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4090{
4091 struct drm_device *dev = crtc->dev;
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4094 int pipe = intel_crtc->pipe;
ee7b9f93 4095 u32 reg, temp;
2c07245f 4096
ab9412ba 4097 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4098
1fbc0d78
DV		 4099 if (IS_IVYBRIDGE(dev))
4100 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4101
cd986abb
DV		 4102 /* Write the TU size bits before fdi link training, so that error
4103 * detection works. */
4104 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4105 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4106
c98e9dcf 4107 /* For PCH output, training FDI link */
674cf967 4108 dev_priv->display.fdi_link_train(crtc);
2c07245f 4109
3ad8a208
DV		 4110 /* We need to program the right clock selection before writing the pixel
4111 * mutliplier into the DPLL. */
303b81e0 4112 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4113 u32 sel;
4b645f14 4114
c98e9dcf 4115 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4116 temp |= TRANS_DPLL_ENABLE(pipe);
4117 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4118 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4119 temp |= sel;
4120 else
4121 temp &= ~sel;
c98e9dcf 4122 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4123 }
5eddb70b 4124
3ad8a208
DV		 4125 /* XXX: pch pll's can be enabled any time before we enable the PCH
4126 * transcoder, and we actually should do this to not upset any PCH
4127 * transcoder that already use the clock when we share it.
4128 *
4129 * Note that enable_shared_dpll tries to do the right thing, but
4130 * get_shared_dpll unconditionally resets the pll - we need that to have
4131 * the right LVDS enable sequence. */
85b3894f 4132 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4133
d9b6cb56
JB		 4134 /* set transcoder timing, panel must allow it */
4135 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4136 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4137
303b81e0 4138 intel_fdi_normal_train(crtc);
5e84e1a4 4139
c98e9dcf 4140 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4141 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
9c4edaee
VS		 4142 const struct drm_display_mode *adjusted_mode =
4143 &intel_crtc->config->base.adjusted_mode;
dfd07d72 4144 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4145 reg = TRANS_DP_CTL(pipe);
4146 temp = I915_READ(reg);
4147 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4148 TRANS_DP_SYNC_MASK |
4149 TRANS_DP_BPC_MASK);
e3ef4479 4150 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4151 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf 4152
9c4edaee 4153 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4154 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
9c4edaee 4155 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4156 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4157
4158 switch (intel_trans_dp_port_sel(crtc)) {
4159 case PCH_DP_B:
5eddb70b 4160 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4161 break;
4162 case PCH_DP_C:
5eddb70b 4163 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4164 break;
4165 case PCH_DP_D:
5eddb70b 4166 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4167 break;
4168 default:
e95d41e1 4169 BUG();
32f9d658 4170 }
2c07245f 4171
5eddb70b 4172 I915_WRITE(reg, temp);
6be4a607 4173 }
b52eb4dc 4174
b8a4f404 4175 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4176}
4177
1507e5bd
PZ		 4178static void lpt_pch_enable(struct drm_crtc *crtc)
4179{
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4183 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4184
ab9412ba 4185 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4186
8c52b5e8 4187 lpt_program_iclkip(crtc);
1507e5bd 4188
0540e488 4189 /* Set transcoder timing. */
275f01b2 4190 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4191
937bb610 4192 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4193}
4194
190f68c5
ACO		 4195struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4196 struct intel_crtc_state *crtc_state)
ee7b9f93 4197{
e2b78267 4198 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4199 struct intel_shared_dpll *pll;
de419ab6 4200 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4201 enum intel_dpll_id i;
ee7b9f93 4202
de419ab6
ML		 4203 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4204
98b6bd99
DV		 4205 if (HAS_PCH_IBX(dev_priv->dev)) {
4206 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4207 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4208 pll = &dev_priv->shared_dplls[i];
98b6bd99 4209
46edb027
DV		 4210 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4211 crtc->base.base.id, pll->name);
98b6bd99 4212
de419ab6 4213 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4214
98b6bd99
DV		 4215 goto found;
4216 }
4217
bcddf610
S		 4218 if (IS_BROXTON(dev_priv->dev)) {
4219 /* PLL is attached to port in bxt */
4220 struct intel_encoder *encoder;
4221 struct intel_digital_port *intel_dig_port;
4222
4223 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4224 if (WARN_ON(!encoder))
4225 return NULL;
4226
4227 intel_dig_port = enc_to_dig_port(&encoder->base);
4228 /* 1:1 mapping between ports and PLLs */
4229 i = (enum intel_dpll_id)intel_dig_port->port;
4230 pll = &dev_priv->shared_dplls[i];
4231 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4232 crtc->base.base.id, pll->name);
de419ab6 4233 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4234
4235 goto found;
4236 }
4237
e72f9fbf
DV		 4238 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4239 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4240
4241 /* Only want to check enabled timings first */
de419ab6 4242 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4243 continue;
4244
190f68c5 4245 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4246 &shared_dpll[i].hw_state,
4247 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4248 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4249 crtc->base.base.id, pll->name,
de419ab6 4250 shared_dpll[i].crtc_mask,
8bd31e67 4251 pll->active);
ee7b9f93
JB		 4252 goto found;
4253 }
4254 }
4255
4256 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4257 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4258 pll = &dev_priv->shared_dplls[i];
de419ab6 4259 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4260 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4261 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4262 goto found;
4263 }
4264 }
4265
4266 return NULL;
4267
4268found:
de419ab6
ML		 4269 if (shared_dpll[i].crtc_mask == 0)
4270 shared_dpll[i].hw_state =
4271 crtc_state->dpll_hw_state;
f2a69f44 4272
190f68c5 4273 crtc_state->shared_dpll = i;
46edb027
DV		 4274 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4275 pipe_name(crtc->pipe));
ee7b9f93 4276
de419ab6 4277 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4278
ee7b9f93
JB		 4279 return pll;
4280}
4281
de419ab6 4282static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4283{
de419ab6
ML		 4284 struct drm_i915_private *dev_priv = to_i915(state->dev);
4285 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4286 struct intel_shared_dpll *pll;
4287 enum intel_dpll_id i;
4288
de419ab6
ML		 4289 if (!to_intel_atomic_state(state)->dpll_set)
4290 return;
8bd31e67 4291
de419ab6 4292 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4293 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4294 pll = &dev_priv->shared_dplls[i];
de419ab6 4295 pll->config = shared_dpll[i];
8bd31e67
ACO		 4296 }
4297}
4298
a1520318 4299static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4300{
4301 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4302 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4303 u32 temp;
4304
4305 temp = I915_READ(dslreg);
4306 udelay(500);
4307 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4308 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4309 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4310 }
4311}
4312
86adf9d7
ML		 4313static int
4314skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4315 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4316 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4317{
86adf9d7
ML		 4318 struct intel_crtc_scaler_state *scaler_state =
4319 &crtc_state->scaler_state;
4320 struct intel_crtc *intel_crtc =
4321 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4322 int need_scaling;
6156a456
CK		 4323
4324 need_scaling = intel_rotation_90_or_270(rotation) ?
4325 (src_h != dst_w || src_w != dst_h):
4326 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4327
4328 /*
4329 * if plane is being disabled or scaler is no more required or force detach
4330 * - free scaler binded to this plane/crtc
4331 * - in order to do this, update crtc->scaler_usage
4332 *
4333 * Here scaler state in crtc_state is set free so that
4334 * scaler can be assigned to other user. Actual register
4335 * update to free the scaler is done in plane/panel-fit programming.
4336 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4337 */
86adf9d7 4338 if (force_detach || !need_scaling) {
a1b2278e 4339 if (*scaler_id >= 0) {
86adf9d7 4340 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4341 scaler_state->scalers[*scaler_id].in_use = 0;
4342
86adf9d7
ML		 4343 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4344 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4345 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4346 scaler_state->scaler_users);
4347 *scaler_id = -1;
4348 }
4349 return 0;
4350 }
4351
4352 /* range checks */
4353 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4354 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4355
4356 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4357 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4358 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4359 "size is out of scaler range\n",
86adf9d7 4360 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4361 return -EINVAL;
4362 }
4363
86adf9d7
ML		 4364 /* mark this plane as a scaler user in crtc_state */
4365 scaler_state->scaler_users |= (1 << scaler_user);
4366 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4367 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4368 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4369 scaler_state->scaler_users);
4370
4371 return 0;
4372}
4373
4374/**
4375 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4376 *
4377 * @state: crtc's scaler state
86adf9d7
ML		 4378 *
4379 * Return
4380 * 0 - scaler_usage updated successfully
4381 * error - requested scaling cannot be supported or other error condition
4382 */
e435d6e5 4383int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4384{
4385 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4386 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4387
4388 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4389 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4390
e435d6e5 4391 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4392 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4393 state->pipe_src_w, state->pipe_src_h,
aad941d5 4394 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4395}
4396
4397/**
4398 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4399 *
4400 * @state: crtc's scaler state
86adf9d7
ML		 4401 * @plane_state: atomic plane state to update
4402 *
4403 * Return
4404 * 0 - scaler_usage updated successfully
4405 * error - requested scaling cannot be supported or other error condition
4406 */
da20eabd
ML		 4407static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4408 struct intel_plane_state *plane_state)
86adf9d7
ML		 4409{
4410
4411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4412 struct intel_plane *intel_plane =
4413 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4414 struct drm_framebuffer *fb = plane_state->base.fb;
4415 int ret;
4416
4417 bool force_detach = !fb || !plane_state->visible;
4418
4419 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4420 intel_plane->base.base.id, intel_crtc->pipe,
4421 drm_plane_index(&intel_plane->base));
4422
4423 ret = skl_update_scaler(crtc_state, force_detach,
4424 drm_plane_index(&intel_plane->base),
4425 &plane_state->scaler_id,
4426 plane_state->base.rotation,
4427 drm_rect_width(&plane_state->src) >> 16,
4428 drm_rect_height(&plane_state->src) >> 16,
4429 drm_rect_width(&plane_state->dst),
4430 drm_rect_height(&plane_state->dst));
4431
4432 if (ret || plane_state->scaler_id < 0)
4433 return ret;
4434
a1b2278e 4435 /* check colorkey */
818ed961 4436 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4437 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4438 intel_plane->base.base.id);
a1b2278e
CK		 4439 return -EINVAL;
4440 }
4441
4442 /* Check src format */
86adf9d7
ML		 4443 switch (fb->pixel_format) {
4444 case DRM_FORMAT_RGB565:
4445 case DRM_FORMAT_XBGR8888:
4446 case DRM_FORMAT_XRGB8888:
4447 case DRM_FORMAT_ABGR8888:
4448 case DRM_FORMAT_ARGB8888:
4449 case DRM_FORMAT_XRGB2101010:
4450 case DRM_FORMAT_XBGR2101010:
4451 case DRM_FORMAT_YUYV:
4452 case DRM_FORMAT_YVYU:
4453 case DRM_FORMAT_UYVY:
4454 case DRM_FORMAT_VYUY:
4455 break;
4456 default:
4457 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4458 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4459 return -EINVAL;
a1b2278e
CK		 4460 }
4461
a1b2278e
CK		 4462 return 0;
4463}
4464
e435d6e5
ML		 4465static void skylake_scaler_disable(struct intel_crtc *crtc)
4466{
4467 int i;
4468
4469 for (i = 0; i < crtc->num_scalers; i++)
4470 skl_detach_scaler(crtc, i);
4471}
4472
4473static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4474{
4475 struct drm_device *dev = crtc->base.dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 int pipe = crtc->pipe;
a1b2278e
CK		 4478 struct intel_crtc_scaler_state *scaler_state =
4479 &crtc->config->scaler_state;
4480
4481 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4482
6e3c9717 4483 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4484 int id;
4485
4486 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4487 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4488 return;
4489 }
4490
4491 id = scaler_state->scaler_id;
4492 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4493 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4494 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4495 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4496
4497 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4498 }
4499}
4500
b074cec8
JB		 4501static void ironlake_pfit_enable(struct intel_crtc *crtc)
4502{
4503 struct drm_device *dev = crtc->base.dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 int pipe = crtc->pipe;
4506
6e3c9717 4507 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4508 /* Force use of hard-coded filter coefficients
4509 * as some pre-programmed values are broken,
4510 * e.g. x201.
4511 */
4512 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4513 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4514 PF_PIPE_SEL_IVB(pipe));
4515 else
4516 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4517 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4518 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4519 }
4520}
4521
20bc8673 4522void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4523{
cea165c3
VS		 4524 struct drm_device *dev = crtc->base.dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4526
6e3c9717 4527 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4528 return;
4529
cea165c3
VS		 4530 /* We can only enable IPS after we enable a plane and wait for a vblank */
4531 intel_wait_for_vblank(dev, crtc->pipe);
4532
d77e4531 4533 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4534 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4535 mutex_lock(&dev_priv->rps.hw_lock);
4536 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4537 mutex_unlock(&dev_priv->rps.hw_lock);
4538 /* Quoting Art Runyan: "its not safe to expect any particular
4539 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4540 * mailbox." Moreover, the mailbox may return a bogus state,
4541 * so we need to just enable it and continue on.
2a114cc1
BW		 4542 */
4543 } else {
4544 I915_WRITE(IPS_CTL, IPS_ENABLE);
4545 /* The bit only becomes 1 in the next vblank, so this wait here
4546 * is essentially intel_wait_for_vblank. If we don't have this
4547 * and don't wait for vblanks until the end of crtc_enable, then
4548 * the HW state readout code will complain that the expected
4549 * IPS_CTL value is not the one we read. */
4550 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4551 DRM_ERROR("Timed out waiting for IPS enable\n");
4552 }
d77e4531
PZ		 4553}
4554
20bc8673 4555void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4556{
4557 struct drm_device *dev = crtc->base.dev;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559
6e3c9717 4560 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4561 return;
4562
4563 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4564 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4565 mutex_lock(&dev_priv->rps.hw_lock);
4566 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4567 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4568 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4569 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4570 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4571 } else {
2a114cc1 4572 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4573 POSTING_READ(IPS_CTL);
4574 }
d77e4531
PZ		 4575
4576 /* We need to wait for a vblank before we can disable the plane. */
4577 intel_wait_for_vblank(dev, crtc->pipe);
4578}
4579
4580/** Loads the palette/gamma unit for the CRTC with the prepared values */
4581static void intel_crtc_load_lut(struct drm_crtc *crtc)
4582{
4583 struct drm_device *dev = crtc->dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586 enum pipe pipe = intel_crtc->pipe;
d77e4531
PZ		 4587 int i;
4588 bool reenable_ips = false;
4589
4590 /* The clocks have to be on to load the palette. */
53d9f4e9 4591 if (!crtc->state->active)
d77e4531
PZ		 4592 return;
4593
50360403 4594 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4595 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4596 assert_dsi_pll_enabled(dev_priv);
4597 else
4598 assert_pll_enabled(dev_priv, pipe);
4599 }
4600
d77e4531
PZ		 4601 /* Workaround : Do not read or write the pipe palette/gamma data while
4602 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4603 */
6e3c9717 4604 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4605 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4606 GAMMA_MODE_MODE_SPLIT)) {
4607 hsw_disable_ips(intel_crtc);
4608 reenable_ips = true;
4609 }
4610
4611 for (i = 0; i < 256; i++) {
f65a9c5b
VS		 4612 u32 palreg;
4613
4614 if (HAS_GMCH_DISPLAY(dev))
4615 palreg = PALETTE(pipe, i);
4616 else
4617 palreg = LGC_PALETTE(pipe, i);
4618
4619 I915_WRITE(palreg,
d77e4531
PZ		 4620 (intel_crtc->lut_r[i] << 16) |
4621 (intel_crtc->lut_g[i] << 8) |
4622 intel_crtc->lut_b[i]);
4623 }
4624
4625 if (reenable_ips)
4626 hsw_enable_ips(intel_crtc);
4627}
4628
7cac945f 4629static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4630{
7cac945f 4631 if (intel_crtc->overlay) {
d3eedb1a
VS		 4632 struct drm_device *dev = intel_crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635 mutex_lock(&dev->struct_mutex);
4636 dev_priv->mm.interruptible = false;
4637 (void) intel_overlay_switch_off(intel_crtc->overlay);
4638 dev_priv->mm.interruptible = true;
4639 mutex_unlock(&dev->struct_mutex);
4640 }
4641
4642 /* Let userspace switch the overlay on again. In most cases userspace
4643 * has to recompute where to put it anyway.
4644 */
4645}
4646
87d4300a
ML		 4647/**
4648 * intel_post_enable_primary - Perform operations after enabling primary plane
4649 * @crtc: the CRTC whose primary plane was just enabled
4650 *
4651 * Performs potentially sleeping operations that must be done after the primary
4652 * plane is enabled, such as updating FBC and IPS. Note that this may be
4653 * called due to an explicit primary plane update, or due to an implicit
4654 * re-enable that is caused when a sprite plane is updated to no longer
4655 * completely hide the primary plane.
4656 */
4657static void
4658intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4659{
4660 struct drm_device *dev = crtc->dev;
87d4300a 4661 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4663 int pipe = intel_crtc->pipe;
a5c4d7bc 4664
87d4300a
ML		 4665 /*
4666 * BDW signals flip done immediately if the plane
4667 * is disabled, even if the plane enable is already
4668 * armed to occur at the next vblank :(
4669 */
4670 if (IS_BROADWELL(dev))
4671 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4672
87d4300a
ML		 4673 /*
4674 * FIXME IPS should be fine as long as one plane is
4675 * enabled, but in practice it seems to have problems
4676 * when going from primary only to sprite only and vice
4677 * versa.
4678 */
a5c4d7bc
VS		 4679 hsw_enable_ips(intel_crtc);
4680
f99d7069 4681 /*
87d4300a
ML		 4682 * Gen2 reports pipe underruns whenever all planes are disabled.
4683 * So don't enable underrun reporting before at least some planes
4684 * are enabled.
4685 * FIXME: Need to fix the logic to work when we turn off all planes
4686 * but leave the pipe running.
f99d7069 4687 */
87d4300a
ML		 4688 if (IS_GEN2(dev))
4689 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4690
aca7b684
VS		 4691 /* Underruns don't always raise interrupts, so check manually. */
4692 intel_check_cpu_fifo_underruns(dev_priv);
4693 intel_check_pch_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4694}
4695
87d4300a
ML		 4696/**
4697 * intel_pre_disable_primary - Perform operations before disabling primary plane
4698 * @crtc: the CRTC whose primary plane is to be disabled
4699 *
4700 * Performs potentially sleeping operations that must be done before the
4701 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4702 * be called due to an explicit primary plane update, or due to an implicit
4703 * disable that is caused when a sprite plane completely hides the primary
4704 * plane.
4705 */
4706static void
4707intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4708{
4709 struct drm_device *dev = crtc->dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 int pipe = intel_crtc->pipe;
a5c4d7bc 4713
87d4300a
ML		 4714 /*
4715 * Gen2 reports pipe underruns whenever all planes are disabled.
4716 * So diasble underrun reporting before all the planes get disabled.
4717 * FIXME: Need to fix the logic to work when we turn off all planes
4718 * but leave the pipe running.
4719 */
4720 if (IS_GEN2(dev))
4721 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4722
87d4300a
ML		 4723 /*
4724 * Vblank time updates from the shadow to live plane control register
4725 * are blocked if the memory self-refresh mode is active at that
4726 * moment. So to make sure the plane gets truly disabled, disable
4727 * first the self-refresh mode. The self-refresh enable bit in turn
4728 * will be checked/applied by the HW only at the next frame start
4729 * event which is after the vblank start event, so we need to have a
4730 * wait-for-vblank between disabling the plane and the pipe.
4731 */
262cd2e1 4732 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4733 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4734 dev_priv->wm.vlv.cxsr = false;
4735 intel_wait_for_vblank(dev, pipe);
4736 }
87d4300a 4737
87d4300a
ML		 4738 /*
4739 * FIXME IPS should be fine as long as one plane is
4740 * enabled, but in practice it seems to have problems
4741 * when going from primary only to sprite only and vice
4742 * versa.
4743 */
a5c4d7bc 4744 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4745}
4746
ac21b225
ML		 4747static void intel_post_plane_update(struct intel_crtc *crtc)
4748{
4749 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4750 struct drm_device *dev = crtc->base.dev;
7733b49b 4751 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4752
4753 if (atomic->wait_vblank)
4754 intel_wait_for_vblank(dev, crtc->pipe);
4755
4756 intel_frontbuffer_flip(dev, atomic->fb_bits);
4757
852eb00d
VS		 4758 if (atomic->disable_cxsr)
4759 crtc->wm.cxsr_allowed = true;
4760
f015c551
VS		 4761 if (crtc->atomic.update_wm_post)
4762 intel_update_watermarks(&crtc->base);
4763
c80ac854 4764 if (atomic->update_fbc)
7733b49b 4765 intel_fbc_update(dev_priv);
ac21b225
ML		 4766
4767 if (atomic->post_enable_primary)
4768 intel_post_enable_primary(&crtc->base);
4769
ac21b225
ML		 4770 memset(atomic, 0, sizeof(*atomic));
4771}
4772
4773static void intel_pre_plane_update(struct intel_crtc *crtc)
4774{
4775 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4776 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225 4777 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
ac21b225 4778
c80ac854 4779 if (atomic->disable_fbc)
25ad93fd 4780 intel_fbc_disable_crtc(crtc);
ac21b225 4781
066cf55b
RV		 4782 if (crtc->atomic.disable_ips)
4783 hsw_disable_ips(crtc);
4784
ac21b225
ML		 4785 if (atomic->pre_disable_primary)
4786 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4787
4788 if (atomic->disable_cxsr) {
4789 crtc->wm.cxsr_allowed = false;
4790 intel_set_memory_cxsr(dev_priv, false);
4791 }
ac21b225
ML		 4792}
4793
d032ffa0 4794static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4795{
4796 struct drm_device *dev = crtc->dev;
4797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4798 struct drm_plane *p;
87d4300a
ML		 4799 int pipe = intel_crtc->pipe;
4800
7cac945f 4801 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4802
d032ffa0
ML		 4803 drm_for_each_plane_mask(p, dev, plane_mask)
4804 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4805
f99d7069
DV		 4806 /*
4807 * FIXME: Once we grow proper nuclear flip support out of this we need
4808 * to compute the mask of flip planes precisely. For the time being
4809 * consider this a flip to a NULL plane.
4810 */
4811 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4812}
4813
f67a559d
JB		 4814static void ironlake_crtc_enable(struct drm_crtc *crtc)
4815{
4816 struct drm_device *dev = crtc->dev;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4819 struct intel_encoder *encoder;
f67a559d 4820 int pipe = intel_crtc->pipe;
f67a559d 4821
53d9f4e9 4822 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4823 return;
4824
81b088ca
VS		 4825 if (intel_crtc->config->has_pch_encoder)
4826 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4827
6e3c9717 4828 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4829 intel_prepare_shared_dpll(intel_crtc);
4830
6e3c9717 4831 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4832 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4833
4834 intel_set_pipe_timings(intel_crtc);
4835
6e3c9717 4836 if (intel_crtc->config->has_pch_encoder) {
29407aab 4837 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4838 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4839 }
4840
4841 ironlake_set_pipeconf(crtc);
4842
f67a559d 4843 intel_crtc->active = true;
8664281b 4844
a72e4c9f 4845 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4846
f6736a1a 4847 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4848 if (encoder->pre_enable)
4849 encoder->pre_enable(encoder);
f67a559d 4850
6e3c9717 4851 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4852 /* Note: FDI PLL enabling _must_ be done before we enable the
4853 * cpu pipes, hence this is separate from all the other fdi/pch
4854 * enabling. */
88cefb6c 4855 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4856 } else {
4857 assert_fdi_tx_disabled(dev_priv, pipe);
4858 assert_fdi_rx_disabled(dev_priv, pipe);
4859 }
f67a559d 4860
b074cec8 4861 ironlake_pfit_enable(intel_crtc);
f67a559d 4862
9c54c0dd
JB		 4863 /*
4864 * On ILK+ LUT must be loaded before the pipe is running but with
4865 * clocks enabled
4866 */
4867 intel_crtc_load_lut(crtc);
4868
f37fcc2a 4869 intel_update_watermarks(crtc);
e1fdc473 4870 intel_enable_pipe(intel_crtc);
f67a559d 4871
6e3c9717 4872 if (intel_crtc->config->has_pch_encoder)
f67a559d 4873 ironlake_pch_enable(crtc);
c98e9dcf 4874
f9b61ff6
DV		 4875 assert_vblank_disabled(crtc);
4876 drm_crtc_vblank_on(crtc);
4877
fa5c73b1
DV		 4878 for_each_encoder_on_crtc(dev, crtc, encoder)
4879 encoder->enable(encoder);
61b77ddd
DV		 4880
4881 if (HAS_PCH_CPT(dev))
a1520318 4882 cpt_verify_modeset(dev, intel_crtc->pipe);
37ca8d4c
VS		 4883
4884 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4885 if (intel_crtc->config->has_pch_encoder)
4886 intel_wait_for_vblank(dev, pipe);
4887 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607
JB		 4888}
4889
42db64ef
PZ		 4890/* IPS only exists on ULT machines and is tied to pipe A. */
4891static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4892{
f5adf94e 4893 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4894}
4895
4f771f10
PZ		 4896static void haswell_crtc_enable(struct drm_crtc *crtc)
4897{
4898 struct drm_device *dev = crtc->dev;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901 struct intel_encoder *encoder;
99d736a2
ML		 4902 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4903 struct intel_crtc_state *pipe_config =
4904 to_intel_crtc_state(crtc->state);
7d4aefd0 4905 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4f771f10 4906
53d9f4e9 4907 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4908 return;
4909
81b088ca
VS		 4910 if (intel_crtc->config->has_pch_encoder)
4911 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4912 false);
4913
df8ad70c
DV		 4914 if (intel_crtc_to_shared_dpll(intel_crtc))
4915 intel_enable_shared_dpll(intel_crtc);
4916
6e3c9717 4917 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4918 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4919
4920 intel_set_pipe_timings(intel_crtc);
4921
6e3c9717
ACO		 4922 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4923 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4924 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4925 }
4926
6e3c9717 4927 if (intel_crtc->config->has_pch_encoder) {
229fca97 4928 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4929 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4930 }
4931
4932 haswell_set_pipeconf(crtc);
4933
4934 intel_set_pipe_csc(crtc);
4935
4f771f10 4936 intel_crtc->active = true;
8664281b 4937
a72e4c9f 4938 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7d4aefd0
SS		 4939 for_each_encoder_on_crtc(dev, crtc, encoder) {
4940 if (encoder->pre_pll_enable)
4941 encoder->pre_pll_enable(encoder);
4f771f10
PZ		 4942 if (encoder->pre_enable)
4943 encoder->pre_enable(encoder);
7d4aefd0 4944 }
4f771f10 4945
d2d65408 4946 if (intel_crtc->config->has_pch_encoder)
4fe9467d 4947 dev_priv->display.fdi_link_train(crtc);
4fe9467d 4948
7d4aefd0
SS		 4949 if (!is_dsi)
4950 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4951
1c132b44 4952 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4953 skylake_pfit_enable(intel_crtc);
ff6d9f55 4954 else
1c132b44 4955 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4956
4957 /*
4958 * On ILK+ LUT must be loaded before the pipe is running but with
4959 * clocks enabled
4960 */
4961 intel_crtc_load_lut(crtc);
4962
1f544388 4963 intel_ddi_set_pipe_settings(crtc);
7d4aefd0
SS		 4964 if (!is_dsi)
4965 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4966
f37fcc2a 4967 intel_update_watermarks(crtc);
e1fdc473 4968 intel_enable_pipe(intel_crtc);
42db64ef 4969
6e3c9717 4970 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4971 lpt_pch_enable(crtc);
4f771f10 4972
7d4aefd0 4973 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
0e32b39c
DA		 4974 intel_ddi_set_vc_payload_alloc(crtc, true);
4975
f9b61ff6
DV		 4976 assert_vblank_disabled(crtc);
4977 drm_crtc_vblank_on(crtc);
4978
8807e55b 4979 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4980 encoder->enable(encoder);
8807e55b
JN		 4981 intel_opregion_notify_encoder(encoder, true);
4982 }
4f771f10 4983
d2d65408
VS		 4984 if (intel_crtc->config->has_pch_encoder)
4985 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4986 true);
4987
e4916946
PZ		 4988 /* If we change the relative order between pipe/planes enabling, we need
4989 * to change the workaround. */
99d736a2
ML		 4990 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4991 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4992 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4993 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4994 }
4f771f10
PZ		 4995}
4996
bfd16b2a 4997static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 4998{
4999 struct drm_device *dev = crtc->base.dev;
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 int pipe = crtc->pipe;
5002
5003 /* To avoid upsetting the power well on haswell only disable the pfit if
5004 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 5005 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5006 I915_WRITE(PF_CTL(pipe), 0);
5007 I915_WRITE(PF_WIN_POS(pipe), 0);
5008 I915_WRITE(PF_WIN_SZ(pipe), 0);
5009 }
5010}
5011
6be4a607
JB		 5012static void ironlake_crtc_disable(struct drm_crtc *crtc)
5013{
5014 struct drm_device *dev = crtc->dev;
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5017 struct intel_encoder *encoder;
6be4a607 5018 int pipe = intel_crtc->pipe;
5eddb70b 5019 u32 reg, temp;
b52eb4dc 5020
37ca8d4c
VS		 5021 if (intel_crtc->config->has_pch_encoder)
5022 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5023
ea9d758d
DV		 5024 for_each_encoder_on_crtc(dev, crtc, encoder)
5025 encoder->disable(encoder);
5026
f9b61ff6
DV		 5027 drm_crtc_vblank_off(crtc);
5028 assert_vblank_disabled(crtc);
5029
575f7ab7 5030 intel_disable_pipe(intel_crtc);
32f9d658 5031
bfd16b2a 5032 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5033
5a74f70a
VS		 5034 if (intel_crtc->config->has_pch_encoder)
5035 ironlake_fdi_disable(crtc);
5036
bf49ec8c
DV		 5037 for_each_encoder_on_crtc(dev, crtc, encoder)
5038 if (encoder->post_disable)
5039 encoder->post_disable(encoder);
2c07245f 5040
6e3c9717 5041 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5042 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5043
d925c59a
DV		 5044 if (HAS_PCH_CPT(dev)) {
5045 /* disable TRANS_DP_CTL */
5046 reg = TRANS_DP_CTL(pipe);
5047 temp = I915_READ(reg);
5048 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5049 TRANS_DP_PORT_SEL_MASK);
5050 temp |= TRANS_DP_PORT_SEL_NONE;
5051 I915_WRITE(reg, temp);
5052
5053 /* disable DPLL_SEL */
5054 temp = I915_READ(PCH_DPLL_SEL);
11887397 5055 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5056 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5057 }
e3421a18 5058
d925c59a
DV		 5059 ironlake_fdi_pll_disable(intel_crtc);
5060 }
81b088ca
VS		 5061
5062 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607 5063}
1b3c7a47 5064
4f771f10 5065static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5066{
4f771f10
PZ		 5067 struct drm_device *dev = crtc->dev;
5068 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5070 struct intel_encoder *encoder;
6e3c9717 5071 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7d4aefd0 5072 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
ee7b9f93 5073
d2d65408
VS		 5074 if (intel_crtc->config->has_pch_encoder)
5075 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5076 false);
5077
8807e55b
JN		 5078 for_each_encoder_on_crtc(dev, crtc, encoder) {
5079 intel_opregion_notify_encoder(encoder, false);
4f771f10 5080 encoder->disable(encoder);
8807e55b 5081 }
4f771f10 5082
f9b61ff6
DV		 5083 drm_crtc_vblank_off(crtc);
5084 assert_vblank_disabled(crtc);
5085
575f7ab7 5086 intel_disable_pipe(intel_crtc);
4f771f10 5087
6e3c9717 5088 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5089 intel_ddi_set_vc_payload_alloc(crtc, false);
5090
7d4aefd0
SS		 5091 if (!is_dsi)
5092 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5093
1c132b44 5094 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5095 skylake_scaler_disable(intel_crtc);
ff6d9f55 5096 else
bfd16b2a 5097 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5098
7d4aefd0
SS		 5099 if (!is_dsi)
5100 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5101
6e3c9717 5102 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5103 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5104 intel_ddi_fdi_disable(crtc);
83616634 5105 }
4f771f10 5106
97b040aa
ID		 5107 for_each_encoder_on_crtc(dev, crtc, encoder)
5108 if (encoder->post_disable)
5109 encoder->post_disable(encoder);
81b088ca
VS		 5110
5111 if (intel_crtc->config->has_pch_encoder)
5112 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5113 true);
4f771f10
PZ		 5114}
5115
2dd24552
JB		 5116static void i9xx_pfit_enable(struct intel_crtc *crtc)
5117{
5118 struct drm_device *dev = crtc->base.dev;
5119 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5120 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5121
681a8504 5122 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5123 return;
5124
2dd24552 5125 /*
c0b03411
DV		 5126 * The panel fitter should only be adjusted whilst the pipe is disabled,
5127 * according to register description and PRM.
2dd24552 5128 */
c0b03411
DV		 5129 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5130 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5131
b074cec8
JB		 5132 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5133 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5134
5135 /* Border color in case we don't scale up to the full screen. Black by
5136 * default, change to something else for debugging. */
5137 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5138}
5139
d05410f9
DA		 5140static enum intel_display_power_domain port_to_power_domain(enum port port)
5141{
5142 switch (port) {
5143 case PORT_A:
5144 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5145 case PORT_B:
5146 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5147 case PORT_C:
5148 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5149 case PORT_D:
5150 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5151 case PORT_E:
5152 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5153 default:
5154 WARN_ON_ONCE(1);
5155 return POWER_DOMAIN_PORT_OTHER;
5156 }
5157}
5158
25f78f58
VS		 5159static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5160{
5161 switch (port) {
5162 case PORT_A:
5163 return POWER_DOMAIN_AUX_A;
5164 case PORT_B:
5165 return POWER_DOMAIN_AUX_B;
5166 case PORT_C:
5167 return POWER_DOMAIN_AUX_C;
5168 case PORT_D:
5169 return POWER_DOMAIN_AUX_D;
5170 case PORT_E:
5171 /* FIXME: Check VBT for actual wiring of PORT E */
5172 return POWER_DOMAIN_AUX_D;
5173 default:
5174 WARN_ON_ONCE(1);
5175 return POWER_DOMAIN_AUX_A;
5176 }
5177}
5178
77d22dca
ID		 5179#define for_each_power_domain(domain, mask) \
5180 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5181 if ((1 << (domain)) & (mask))
5182
319be8ae
ID		 5183enum intel_display_power_domain
5184intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5185{
5186 struct drm_device *dev = intel_encoder->base.dev;
5187 struct intel_digital_port *intel_dig_port;
5188
5189 switch (intel_encoder->type) {
5190 case INTEL_OUTPUT_UNKNOWN:
5191 /* Only DDI platforms should ever use this output type */
5192 WARN_ON_ONCE(!HAS_DDI(dev));
5193 case INTEL_OUTPUT_DISPLAYPORT:
5194 case INTEL_OUTPUT_HDMI:
5195 case INTEL_OUTPUT_EDP:
5196 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5197 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5198 case INTEL_OUTPUT_DP_MST:
5199 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5200 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5201 case INTEL_OUTPUT_ANALOG:
5202 return POWER_DOMAIN_PORT_CRT;
5203 case INTEL_OUTPUT_DSI:
5204 return POWER_DOMAIN_PORT_DSI;
5205 default:
5206 return POWER_DOMAIN_PORT_OTHER;
5207 }
5208}
5209
25f78f58
VS		 5210enum intel_display_power_domain
5211intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5212{
5213 struct drm_device *dev = intel_encoder->base.dev;
5214 struct intel_digital_port *intel_dig_port;
5215
5216 switch (intel_encoder->type) {
5217 case INTEL_OUTPUT_UNKNOWN:
5218 /* Only DDI platforms should ever use this output type */
5219 WARN_ON_ONCE(!HAS_DDI(dev));
5220 case INTEL_OUTPUT_DISPLAYPORT:
5221 case INTEL_OUTPUT_EDP:
5222 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5223 return port_to_aux_power_domain(intel_dig_port->port);
5224 case INTEL_OUTPUT_DP_MST:
5225 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5226 return port_to_aux_power_domain(intel_dig_port->port);
5227 default:
5228 WARN_ON_ONCE(1);
5229 return POWER_DOMAIN_AUX_A;
5230 }
5231}
5232
319be8ae 5233static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5234{
319be8ae
ID		 5235 struct drm_device *dev = crtc->dev;
5236 struct intel_encoder *intel_encoder;
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 enum pipe pipe = intel_crtc->pipe;
77d22dca 5239 unsigned long mask;
1a70a728 5240 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
77d22dca 5241
292b990e
ML		 5242 if (!crtc->state->active)
5243 return 0;
5244
77d22dca
ID		 5245 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5246 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5247 if (intel_crtc->config->pch_pfit.enabled ||
5248 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5249 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5250
319be8ae
ID		 5251 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5252 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5253
77d22dca
ID		 5254 return mask;
5255}
5256
292b990e 5257static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5258{
292b990e
ML		 5259 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5261 enum intel_display_power_domain domain;
5262 unsigned long domains, new_domains, old_domains;
77d22dca 5263
292b990e
ML		 5264 old_domains = intel_crtc->enabled_power_domains;
5265 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5266
292b990e
ML		 5267 domains = new_domains & ~old_domains;
5268
5269 for_each_power_domain(domain, domains)
5270 intel_display_power_get(dev_priv, domain);
5271
5272 return old_domains & ~new_domains;
5273}
5274
5275static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5276 unsigned long domains)
5277{
5278 enum intel_display_power_domain domain;
5279
5280 for_each_power_domain(domain, domains)
5281 intel_display_power_put(dev_priv, domain);
5282}
77d22dca 5283
292b990e
ML		 5284static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5285{
5286 struct drm_device *dev = state->dev;
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288 unsigned long put_domains[I915_MAX_PIPES] = {};
5289 struct drm_crtc_state *crtc_state;
5290 struct drm_crtc *crtc;
5291 int i;
77d22dca 5292
292b990e
ML		 5293 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5294 if (needs_modeset(crtc->state))
5295 put_domains[to_intel_crtc(crtc)->pipe] =
5296 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5297 }
5298
27c329ed
ML		 5299 if (dev_priv->display.modeset_commit_cdclk) {
5300 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5301
5302 if (cdclk != dev_priv->cdclk_freq &&
5303 !WARN_ON(!state->allow_modeset))
5304 dev_priv->display.modeset_commit_cdclk(state);
5305 }
50f6e502 5306
292b990e
ML		 5307 for (i = 0; i < I915_MAX_PIPES; i++)
5308 if (put_domains[i])
5309 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5310}
5311
adafdc6f
MK		 5312static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5313{
5314 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5315
5316 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5317 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5318 return max_cdclk_freq;
5319 else if (IS_CHERRYVIEW(dev_priv))
5320 return max_cdclk_freq*95/100;
5321 else if (INTEL_INFO(dev_priv)->gen < 4)
5322 return 2*max_cdclk_freq*90/100;
5323 else
5324 return max_cdclk_freq*90/100;
5325}
5326
560a7ae4
DL		 5327static void intel_update_max_cdclk(struct drm_device *dev)
5328{
5329 struct drm_i915_private *dev_priv = dev->dev_private;
5330
ef11bdb3 5331 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
560a7ae4
DL		 5332 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5333
5334 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5335 dev_priv->max_cdclk_freq = 675000;
5336 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5337 dev_priv->max_cdclk_freq = 540000;
5338 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5339 dev_priv->max_cdclk_freq = 450000;
5340 else
5341 dev_priv->max_cdclk_freq = 337500;
5342 } else if (IS_BROADWELL(dev)) {
5343 /*
5344 * FIXME with extra cooling we can allow
5345 * 540 MHz for ULX and 675 Mhz for ULT.
5346 * How can we know if extra cooling is
5347 * available? PCI ID, VTB, something else?
5348 */
5349 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5350 dev_priv->max_cdclk_freq = 450000;
5351 else if (IS_BDW_ULX(dev))
5352 dev_priv->max_cdclk_freq = 450000;
5353 else if (IS_BDW_ULT(dev))
5354 dev_priv->max_cdclk_freq = 540000;
5355 else
5356 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5357 } else if (IS_CHERRYVIEW(dev)) {
5358 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5359 } else if (IS_VALLEYVIEW(dev)) {
5360 dev_priv->max_cdclk_freq = 400000;
5361 } else {
5362 /* otherwise assume cdclk is fixed */
5363 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5364 }
5365
adafdc6f
MK		 5366 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5367
560a7ae4
DL		 5368 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5369 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5370
5371 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5372 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5373}
5374
5375static void intel_update_cdclk(struct drm_device *dev)
5376{
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378
5379 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5380 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5381 dev_priv->cdclk_freq);
5382
5383 /*
5384 * Program the gmbus_freq based on the cdclk frequency.
5385 * BSpec erroneously claims we should aim for 4MHz, but
5386 * in fact 1MHz is the correct frequency.
5387 */
5388 if (IS_VALLEYVIEW(dev)) {
5389 /*
5390 * Program the gmbus_freq based on the cdclk frequency.
5391 * BSpec erroneously claims we should aim for 4MHz, but
5392 * in fact 1MHz is the correct frequency.
5393 */
5394 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5395 }
5396
5397 if (dev_priv->max_cdclk_freq == 0)
5398 intel_update_max_cdclk(dev);
5399}
5400
70d0c574 5401static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5402{
5403 struct drm_i915_private *dev_priv = dev->dev_private;
5404 uint32_t divider;
5405 uint32_t ratio;
5406 uint32_t current_freq;
5407 int ret;
5408
5409 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5410 switch (frequency) {
5411 case 144000:
5412 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5413 ratio = BXT_DE_PLL_RATIO(60);
5414 break;
5415 case 288000:
5416 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5417 ratio = BXT_DE_PLL_RATIO(60);
5418 break;
5419 case 384000:
5420 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5421 ratio = BXT_DE_PLL_RATIO(60);
5422 break;
5423 case 576000:
5424 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5425 ratio = BXT_DE_PLL_RATIO(60);
5426 break;
5427 case 624000:
5428 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5429 ratio = BXT_DE_PLL_RATIO(65);
5430 break;
5431 case 19200:
5432 /*
5433 * Bypass frequency with DE PLL disabled. Init ratio, divider
5434 * to suppress GCC warning.
5435 */
5436 ratio = 0;
5437 divider = 0;
5438 break;
5439 default:
5440 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5441
5442 return;
5443 }
5444
5445 mutex_lock(&dev_priv->rps.hw_lock);
5446 /* Inform power controller of upcoming frequency change */
5447 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5448 0x80000000);
5449 mutex_unlock(&dev_priv->rps.hw_lock);
5450
5451 if (ret) {
5452 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5453 ret, frequency);
5454 return;
5455 }
5456
5457 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5458 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5459 current_freq = current_freq * 500 + 1000;
5460
5461 /*
5462 * DE PLL has to be disabled when
5463 * - setting to 19.2MHz (bypass, PLL isn't used)
5464 * - before setting to 624MHz (PLL needs toggling)
5465 * - before setting to any frequency from 624MHz (PLL needs toggling)
5466 */
5467 if (frequency == 19200 || frequency == 624000 ||
5468 current_freq == 624000) {
5469 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5470 /* Timeout 200us */
5471 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5472 1))
5473 DRM_ERROR("timout waiting for DE PLL unlock\n");
5474 }
5475
5476 if (frequency != 19200) {
5477 uint32_t val;
5478
5479 val = I915_READ(BXT_DE_PLL_CTL);
5480 val &= ~BXT_DE_PLL_RATIO_MASK;
5481 val |= ratio;
5482 I915_WRITE(BXT_DE_PLL_CTL, val);
5483
5484 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5485 /* Timeout 200us */
5486 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5487 DRM_ERROR("timeout waiting for DE PLL lock\n");
5488
5489 val = I915_READ(CDCLK_CTL);
5490 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5491 val |= divider;
5492 /*
5493 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5494 * enable otherwise.
5495 */
5496 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5497 if (frequency >= 500000)
5498 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5499
5500 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5501 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5502 val |= (frequency - 1000) / 500;
5503 I915_WRITE(CDCLK_CTL, val);
5504 }
5505
5506 mutex_lock(&dev_priv->rps.hw_lock);
5507 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5508 DIV_ROUND_UP(frequency, 25000));
5509 mutex_unlock(&dev_priv->rps.hw_lock);
5510
5511 if (ret) {
5512 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5513 ret, frequency);
5514 return;
5515 }
5516
a47871bd 5517 intel_update_cdclk(dev);
f8437dd1
VK		 5518}
5519
5520void broxton_init_cdclk(struct drm_device *dev)
5521{
5522 struct drm_i915_private *dev_priv = dev->dev_private;
5523 uint32_t val;
5524
5525 /*
5526 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5527 * or else the reset will hang because there is no PCH to respond.
5528 * Move the handshake programming to initialization sequence.
5529 * Previously was left up to BIOS.
5530 */
5531 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5532 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5533 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5534
5535 /* Enable PG1 for cdclk */
5536 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5537
5538 /* check if cd clock is enabled */
5539 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5540 DRM_DEBUG_KMS("Display already initialized\n");
5541 return;
5542 }
5543
5544 /*
5545 * FIXME:
5546 * - The initial CDCLK needs to be read from VBT.
5547 * Need to make this change after VBT has changes for BXT.
5548 * - check if setting the max (or any) cdclk freq is really necessary
5549 * here, it belongs to modeset time
5550 */
5551 broxton_set_cdclk(dev, 624000);
5552
5553 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5554 POSTING_READ(DBUF_CTL);
5555
f8437dd1
VK		 5556 udelay(10);
5557
5558 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5559 DRM_ERROR("DBuf power enable timeout!\n");
5560}
5561
5562void broxton_uninit_cdclk(struct drm_device *dev)
5563{
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5565
5566 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5567 POSTING_READ(DBUF_CTL);
5568
f8437dd1
VK		 5569 udelay(10);
5570
5571 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5572 DRM_ERROR("DBuf power disable timeout!\n");
5573
5574 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5575 broxton_set_cdclk(dev, 19200);
5576
5577 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5578}
5579
5d96d8af
DL		 5580static const struct skl_cdclk_entry {
5581 unsigned int freq;
5582 unsigned int vco;
5583} skl_cdclk_frequencies[] = {
5584 { .freq = 308570, .vco = 8640 },
5585 { .freq = 337500, .vco = 8100 },
5586 { .freq = 432000, .vco = 8640 },
5587 { .freq = 450000, .vco = 8100 },
5588 { .freq = 540000, .vco = 8100 },
5589 { .freq = 617140, .vco = 8640 },
5590 { .freq = 675000, .vco = 8100 },
5591};
5592
5593static unsigned int skl_cdclk_decimal(unsigned int freq)
5594{
5595 return (freq - 1000) / 500;
5596}
5597
5598static unsigned int skl_cdclk_get_vco(unsigned int freq)
5599{
5600 unsigned int i;
5601
5602 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5603 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5604
5605 if (e->freq == freq)
5606 return e->vco;
5607 }
5608
5609 return 8100;
5610}
5611
5612static void
5613skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5614{
5615 unsigned int min_freq;
5616 u32 val;
5617
5618 /* select the minimum CDCLK before enabling DPLL 0 */
5619 val = I915_READ(CDCLK_CTL);
5620 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5621 val |= CDCLK_FREQ_337_308;
5622
5623 if (required_vco == 8640)
5624 min_freq = 308570;
5625 else
5626 min_freq = 337500;
5627
5628 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5629
5630 I915_WRITE(CDCLK_CTL, val);
5631 POSTING_READ(CDCLK_CTL);
5632
5633 /*
5634 * We always enable DPLL0 with the lowest link rate possible, but still
5635 * taking into account the VCO required to operate the eDP panel at the
5636 * desired frequency. The usual DP link rates operate with a VCO of
5637 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5638 * The modeset code is responsible for the selection of the exact link
5639 * rate later on, with the constraint of choosing a frequency that
5640 * works with required_vco.
5641 */
5642 val = I915_READ(DPLL_CTRL1);
5643
5644 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5645 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5646 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5647 if (required_vco == 8640)
5648 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5649 SKL_DPLL0);
5650 else
5651 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5652 SKL_DPLL0);
5653
5654 I915_WRITE(DPLL_CTRL1, val);
5655 POSTING_READ(DPLL_CTRL1);
5656
5657 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5658
5659 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5660 DRM_ERROR("DPLL0 not locked\n");
5661}
5662
5663static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5664{
5665 int ret;
5666 u32 val;
5667
5668 /* inform PCU we want to change CDCLK */
5669 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5670 mutex_lock(&dev_priv->rps.hw_lock);
5671 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5672 mutex_unlock(&dev_priv->rps.hw_lock);
5673
5674 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5675}
5676
5677static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5678{
5679 unsigned int i;
5680
5681 for (i = 0; i < 15; i++) {
5682 if (skl_cdclk_pcu_ready(dev_priv))
5683 return true;
5684 udelay(10);
5685 }
5686
5687 return false;
5688}
5689
5690static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5691{
560a7ae4 5692 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5693 u32 freq_select, pcu_ack;
5694
5695 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5696
5697 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5698 DRM_ERROR("failed to inform PCU about cdclk change\n");
5699 return;
5700 }
5701
5702 /* set CDCLK_CTL */
5703 switch(freq) {
5704 case 450000:
5705 case 432000:
5706 freq_select = CDCLK_FREQ_450_432;
5707 pcu_ack = 1;
5708 break;
5709 case 540000:
5710 freq_select = CDCLK_FREQ_540;
5711 pcu_ack = 2;
5712 break;
5713 case 308570:
5714 case 337500:
5715 default:
5716 freq_select = CDCLK_FREQ_337_308;
5717 pcu_ack = 0;
5718 break;
5719 case 617140:
5720 case 675000:
5721 freq_select = CDCLK_FREQ_675_617;
5722 pcu_ack = 3;
5723 break;
5724 }
5725
5726 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5727 POSTING_READ(CDCLK_CTL);
5728
5729 /* inform PCU of the change */
5730 mutex_lock(&dev_priv->rps.hw_lock);
5731 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5732 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5733
5734 intel_update_cdclk(dev);
5d96d8af
DL		 5735}
5736
5737void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5738{
5739 /* disable DBUF power */
5740 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5741 POSTING_READ(DBUF_CTL);
5742
5743 udelay(10);
5744
5745 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5746 DRM_ERROR("DBuf power disable timeout\n");
5747
ab96c1ee
ID		 5748 /* disable DPLL0 */
5749 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5750 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5751 DRM_ERROR("Couldn't disable DPLL0\n");
5d96d8af
DL		 5752}
5753
5754void skl_init_cdclk(struct drm_i915_private *dev_priv)
5755{
5d96d8af
DL		 5756 unsigned int required_vco;
5757
39d9b85a
GW		 5758 /* DPLL0 not enabled (happens on early BIOS versions) */
5759 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5760 /* enable DPLL0 */
5761 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5762 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5763 }
5764
5d96d8af
DL		 5765 /* set CDCLK to the frequency the BIOS chose */
5766 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5767
5768 /* enable DBUF power */
5769 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5770 POSTING_READ(DBUF_CTL);
5771
5772 udelay(10);
5773
5774 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5775 DRM_ERROR("DBuf power enable timeout\n");
5776}
5777
c73666f3
SK		 5778int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5779{
5780 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5781 uint32_t cdctl = I915_READ(CDCLK_CTL);
5782 int freq = dev_priv->skl_boot_cdclk;
5783
f1b391a5
SK		 5784 /*
5785 * check if the pre-os intialized the display
5786 * There is SWF18 scratchpad register defined which is set by the
5787 * pre-os which can be used by the OS drivers to check the status
5788 */
5789 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5790 goto sanitize;
5791
c73666f3
SK		 5792 /* Is PLL enabled and locked ? */
5793 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5794 goto sanitize;
5795
5796 /* DPLL okay; verify the cdclock
5797 *
5798 * Noticed in some instances that the freq selection is correct but
5799 * decimal part is programmed wrong from BIOS where pre-os does not
5800 * enable display. Verify the same as well.
5801 */
5802 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5803 /* All well; nothing to sanitize */
5804 return false;
5805sanitize:
5806 /*
5807 * As of now initialize with max cdclk till
5808 * we get dynamic cdclk support
5809 * */
5810 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5811 skl_init_cdclk(dev_priv);
5812
5813 /* we did have to sanitize */
5814 return true;
5815}
5816
30a970c6
JB		 5817/* Adjust CDclk dividers to allow high res or save power if possible */
5818static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5819{
5820 struct drm_i915_private *dev_priv = dev->dev_private;
5821 u32 val, cmd;
5822
164dfd28
VK		 5823 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5824 != dev_priv->cdclk_freq);
d60c4473 5825
dfcab17e 5826 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5827 cmd = 2;
dfcab17e 5828 else if (cdclk == 266667)
30a970c6
JB		 5829 cmd = 1;
5830 else
5831 cmd = 0;
5832
5833 mutex_lock(&dev_priv->rps.hw_lock);
5834 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5835 val &= ~DSPFREQGUAR_MASK;
5836 val |= (cmd << DSPFREQGUAR_SHIFT);
5837 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5838 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5839 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5840 50)) {
5841 DRM_ERROR("timed out waiting for CDclk change\n");
5842 }
5843 mutex_unlock(&dev_priv->rps.hw_lock);
5844
54433e91
VS		 5845 mutex_lock(&dev_priv->sb_lock);
5846
dfcab17e 5847 if (cdclk == 400000) {
6bcda4f0 5848 u32 divider;
30a970c6 5849
6bcda4f0 5850 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5851
30a970c6
JB		 5852 /* adjust cdclk divider */
5853 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5854 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5855 val |= divider;
5856 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5857
5858 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5859 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5860 50))
5861 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5862 }
5863
30a970c6
JB		 5864 /* adjust self-refresh exit latency value */
5865 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5866 val &= ~0x7f;
5867
5868 /*
5869 * For high bandwidth configs, we set a higher latency in the bunit
5870 * so that the core display fetch happens in time to avoid underruns.
5871 */
dfcab17e 5872 if (cdclk == 400000)
30a970c6
JB		 5873 val |= 4500 / 250; /* 4.5 usec */
5874 else
5875 val |= 3000 / 250; /* 3.0 usec */
5876 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5877
a580516d 5878 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5879
b6283055 5880 intel_update_cdclk(dev);
30a970c6
JB		 5881}
5882
383c5a6a
VS		 5883static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5884{
5885 struct drm_i915_private *dev_priv = dev->dev_private;
5886 u32 val, cmd;
5887
164dfd28
VK		 5888 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5889 != dev_priv->cdclk_freq);
383c5a6a
VS		 5890
5891 switch (cdclk) {
383c5a6a
VS		 5892 case 333333:
5893 case 320000:
383c5a6a 5894 case 266667:
383c5a6a 5895 case 200000:
383c5a6a
VS		 5896 break;
5897 default:
5f77eeb0 5898 MISSING_CASE(cdclk);
383c5a6a
VS		 5899 return;
5900 }
5901
9d0d3fda
VS		 5902 /*
5903 * Specs are full of misinformation, but testing on actual
5904 * hardware has shown that we just need to write the desired
5905 * CCK divider into the Punit register.
5906 */
5907 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5908
383c5a6a
VS		 5909 mutex_lock(&dev_priv->rps.hw_lock);
5910 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5911 val &= ~DSPFREQGUAR_MASK_CHV;
5912 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5913 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5914 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5915 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5916 50)) {
5917 DRM_ERROR("timed out waiting for CDclk change\n");
5918 }
5919 mutex_unlock(&dev_priv->rps.hw_lock);
5920
b6283055 5921 intel_update_cdclk(dev);
383c5a6a
VS		 5922}
5923
30a970c6
JB		 5924static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5925 int max_pixclk)
5926{
6bcda4f0 5927 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5928 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5929
30a970c6
JB		 5930 /*
5931 * Really only a few cases to deal with, as only 4 CDclks are supported:
5932 * 200MHz
5933 * 267MHz
29dc7ef3 5934 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5935 * 400MHz (VLV only)
5936 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5937 * of the lower bin and adjust if needed.
e37c67a1
VS		 5938 *
5939 * We seem to get an unstable or solid color picture at 200MHz.
5940 * Not sure what's wrong. For now use 200MHz only when all pipes
5941 * are off.
30a970c6 5942 */
6cca3195
VS		 5943 if (!IS_CHERRYVIEW(dev_priv) &&
5944 max_pixclk > freq_320*limit/100)
dfcab17e 5945 return 400000;
6cca3195 5946 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5947 return freq_320;
e37c67a1 5948 else if (max_pixclk > 0)
dfcab17e 5949 return 266667;
e37c67a1
VS		 5950 else
5951 return 200000;
30a970c6
JB		 5952}
5953
f8437dd1
VK		 5954static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5955 int max_pixclk)
5956{
5957 /*
5958 * FIXME:
5959 * - remove the guardband, it's not needed on BXT
5960 * - set 19.2MHz bypass frequency if there are no active pipes
5961 */
5962 if (max_pixclk > 576000*9/10)
5963 return 624000;
5964 else if (max_pixclk > 384000*9/10)
5965 return 576000;
5966 else if (max_pixclk > 288000*9/10)
5967 return 384000;
5968 else if (max_pixclk > 144000*9/10)
5969 return 288000;
5970 else
5971 return 144000;
5972}
5973
a821fc46
ACO		 5974/* Compute the max pixel clock for new configuration. Uses atomic state if
5975 * that's non-NULL, look at current state otherwise. */
5976static int intel_mode_max_pixclk(struct drm_device *dev,
5977 struct drm_atomic_state *state)
30a970c6 5978{
30a970c6 5979 struct intel_crtc *intel_crtc;
304603f4 5980 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5981 int max_pixclk = 0;
5982
d3fcc808 5983 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5984 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5985 if (IS_ERR(crtc_state))
5986 return PTR_ERR(crtc_state);
5987
5988 if (!crtc_state->base.enable)
5989 continue;
5990
5991 max_pixclk = max(max_pixclk,
5992 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5993 }
5994
5995 return max_pixclk;
5996}
5997
27c329ed 5998static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5999{
27c329ed
ML		 6000 struct drm_device *dev = state->dev;
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 6003
304603f4
ACO		 6004 if (max_pixclk < 0)
6005 return max_pixclk;
30a970c6 6006
27c329ed
ML		 6007 to_intel_atomic_state(state)->cdclk =
6008 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 6009
27c329ed
ML		 6010 return 0;
6011}
304603f4 6012
27c329ed
ML		 6013static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6014{
6015 struct drm_device *dev = state->dev;
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 6018
27c329ed
ML		 6019 if (max_pixclk < 0)
6020 return max_pixclk;
85a96e7a 6021
27c329ed
ML		 6022 to_intel_atomic_state(state)->cdclk =
6023 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 6024
27c329ed 6025 return 0;
30a970c6
JB		 6026}
6027
1e69cd74
VS		 6028static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6029{
6030 unsigned int credits, default_credits;
6031
6032 if (IS_CHERRYVIEW(dev_priv))
6033 default_credits = PFI_CREDIT(12);
6034 else
6035 default_credits = PFI_CREDIT(8);
6036
bfa7df01 6037 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 6038 /* CHV suggested value is 31 or 63 */
6039 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 6040 credits = PFI_CREDIT_63;
1e69cd74
VS		 6041 else
6042 credits = PFI_CREDIT(15);
6043 } else {
6044 credits = default_credits;
6045 }
6046
6047 /*
6048 * WA - write default credits before re-programming
6049 * FIXME: should we also set the resend bit here?
6050 */
6051 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6052 default_credits);
6053
6054 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6055 credits | PFI_CREDIT_RESEND);
6056
6057 /*
6058 * FIXME is this guaranteed to clear
6059 * immediately or should we poll for it?
6060 */
6061 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6062}
6063
27c329ed 6064static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6065{
a821fc46 6066 struct drm_device *dev = old_state->dev;
27c329ed 6067 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6068 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6069
27c329ed
ML		 6070 /*
6071 * FIXME: We can end up here with all power domains off, yet
6072 * with a CDCLK frequency other than the minimum. To account
6073 * for this take the PIPE-A power domain, which covers the HW
6074 * blocks needed for the following programming. This can be
6075 * removed once it's guaranteed that we get here either with
6076 * the minimum CDCLK set, or the required power domains
6077 * enabled.
6078 */
6079 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6080
27c329ed
ML		 6081 if (IS_CHERRYVIEW(dev))
6082 cherryview_set_cdclk(dev, req_cdclk);
6083 else
6084 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6085
27c329ed 6086 vlv_program_pfi_credits(dev_priv);
1e69cd74 6087
27c329ed 6088 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6089}
6090
89b667f8
JB		 6091static void valleyview_crtc_enable(struct drm_crtc *crtc)
6092{
6093 struct drm_device *dev = crtc->dev;
a72e4c9f 6094 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096 struct intel_encoder *encoder;
6097 int pipe = intel_crtc->pipe;
23538ef1 6098 bool is_dsi;
89b667f8 6099
53d9f4e9 6100 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6101 return;
6102
409ee761 6103 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6104
6e3c9717 6105 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6106 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6107
6108 intel_set_pipe_timings(intel_crtc);
6109
c14b0485
VS		 6110 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6111 struct drm_i915_private *dev_priv = dev->dev_private;
6112
6113 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6114 I915_WRITE(CHV_CANVAS(pipe), 0);
6115 }
6116
5b18e57c
DV		 6117 i9xx_set_pipeconf(intel_crtc);
6118
89b667f8 6119 intel_crtc->active = true;
89b667f8 6120
a72e4c9f 6121 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6122
89b667f8
JB		 6123 for_each_encoder_on_crtc(dev, crtc, encoder)
6124 if (encoder->pre_pll_enable)
6125 encoder->pre_pll_enable(encoder);
6126
9d556c99 6127 if (!is_dsi) {
c0b4c660
VS		 6128 if (IS_CHERRYVIEW(dev)) {
6129 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6130 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6131 } else {
6132 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6133 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6134 }
9d556c99 6135 }
89b667f8
JB		 6136
6137 for_each_encoder_on_crtc(dev, crtc, encoder)
6138 if (encoder->pre_enable)
6139 encoder->pre_enable(encoder);
6140
2dd24552
JB		 6141 i9xx_pfit_enable(intel_crtc);
6142
63cbb074
VS		 6143 intel_crtc_load_lut(crtc);
6144
e1fdc473 6145 intel_enable_pipe(intel_crtc);
be6a6f8e 6146
4b3a9526
VS		 6147 assert_vblank_disabled(crtc);
6148 drm_crtc_vblank_on(crtc);
6149
f9b61ff6
DV		 6150 for_each_encoder_on_crtc(dev, crtc, encoder)
6151 encoder->enable(encoder);
89b667f8
JB		 6152}
6153
f13c2ef3
DV		 6154static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6155{
6156 struct drm_device *dev = crtc->base.dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158
6e3c9717
ACO		 6159 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6160 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6161}
6162
0b8765c6 6163static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6164{
6165 struct drm_device *dev = crtc->dev;
a72e4c9f 6166 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6168 struct intel_encoder *encoder;
79e53945 6169 int pipe = intel_crtc->pipe;
79e53945 6170
53d9f4e9 6171 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6172 return;
6173
f13c2ef3
DV		 6174 i9xx_set_pll_dividers(intel_crtc);
6175
6e3c9717 6176 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6177 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6178
6179 intel_set_pipe_timings(intel_crtc);
6180
5b18e57c
DV		 6181 i9xx_set_pipeconf(intel_crtc);
6182
f7abfe8b 6183 intel_crtc->active = true;
6b383a7f 6184
4a3436e8 6185 if (!IS_GEN2(dev))
a72e4c9f 6186 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6187
9d6d9f19
MK		 6188 for_each_encoder_on_crtc(dev, crtc, encoder)
6189 if (encoder->pre_enable)
6190 encoder->pre_enable(encoder);
6191
f6736a1a
DV		 6192 i9xx_enable_pll(intel_crtc);
6193
2dd24552
JB		 6194 i9xx_pfit_enable(intel_crtc);
6195
63cbb074
VS		 6196 intel_crtc_load_lut(crtc);
6197
f37fcc2a 6198 intel_update_watermarks(crtc);
e1fdc473 6199 intel_enable_pipe(intel_crtc);
be6a6f8e 6200
4b3a9526
VS		 6201 assert_vblank_disabled(crtc);
6202 drm_crtc_vblank_on(crtc);
6203
f9b61ff6
DV		 6204 for_each_encoder_on_crtc(dev, crtc, encoder)
6205 encoder->enable(encoder);
0b8765c6 6206}
79e53945 6207
87476d63
DV		 6208static void i9xx_pfit_disable(struct intel_crtc *crtc)
6209{
6210 struct drm_device *dev = crtc->base.dev;
6211 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6212
6e3c9717 6213 if (!crtc->config->gmch_pfit.control)
328d8e82 6214 return;
87476d63 6215
328d8e82 6216 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6217
328d8e82
DV		 6218 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6219 I915_READ(PFIT_CONTROL));
6220 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6221}
6222
0b8765c6
JB		 6223static void i9xx_crtc_disable(struct drm_crtc *crtc)
6224{
6225 struct drm_device *dev = crtc->dev;
6226 struct drm_i915_private *dev_priv = dev->dev_private;
6227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6228 struct intel_encoder *encoder;
0b8765c6 6229 int pipe = intel_crtc->pipe;
ef9c3aee 6230
6304cd91
VS		 6231 /*
6232 * On gen2 planes are double buffered but the pipe isn't, so we must
6233 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6234 * We also need to wait on all gmch platforms because of the
6235 * self-refresh mode constraint explained above.
6304cd91 6236 */
564ed191 6237 intel_wait_for_vblank(dev, pipe);
6304cd91 6238
4b3a9526
VS		 6239 for_each_encoder_on_crtc(dev, crtc, encoder)
6240 encoder->disable(encoder);
6241
f9b61ff6
DV		 6242 drm_crtc_vblank_off(crtc);
6243 assert_vblank_disabled(crtc);
6244
575f7ab7 6245 intel_disable_pipe(intel_crtc);
24a1f16d 6246
87476d63 6247 i9xx_pfit_disable(intel_crtc);
24a1f16d 6248
89b667f8
JB		 6249 for_each_encoder_on_crtc(dev, crtc, encoder)
6250 if (encoder->post_disable)
6251 encoder->post_disable(encoder);
6252
409ee761 6253 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6254 if (IS_CHERRYVIEW(dev))
6255 chv_disable_pll(dev_priv, pipe);
6256 else if (IS_VALLEYVIEW(dev))
6257 vlv_disable_pll(dev_priv, pipe);
6258 else
1c4e0274 6259 i9xx_disable_pll(intel_crtc);
076ed3b2 6260 }
0b8765c6 6261
d6db995f
VS		 6262 for_each_encoder_on_crtc(dev, crtc, encoder)
6263 if (encoder->post_pll_disable)
6264 encoder->post_pll_disable(encoder);
6265
4a3436e8 6266 if (!IS_GEN2(dev))
a72e4c9f 6267 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6268}
6269
b17d48e2
ML		 6270static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6271{
6272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6274 enum intel_display_power_domain domain;
6275 unsigned long domains;
6276
6277 if (!intel_crtc->active)
6278 return;
6279
a539205a 6280 if (to_intel_plane_state(crtc->primary->state)->visible) {
fc32b1fd
ML		 6281 WARN_ON(intel_crtc->unpin_work);
6282
a539205a
ML		 6283 intel_pre_disable_primary(crtc);
6284 }
6285
d032ffa0 6286 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6287 dev_priv->display.crtc_disable(crtc);
37d9078b
MR		 6288 intel_crtc->active = false;
6289 intel_update_watermarks(crtc);
1f7457b1 6290 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6291
6292 domains = intel_crtc->enabled_power_domains;
6293 for_each_power_domain(domain, domains)
6294 intel_display_power_put(dev_priv, domain);
6295 intel_crtc->enabled_power_domains = 0;
6296}
6297
6b72d486
ML		 6298/*
6299 * turn all crtc's off, but do not adjust state
6300 * This has to be paired with a call to intel_modeset_setup_hw_state.
6301 */
70e0bd74 6302int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6303{
70e0bd74
ML		 6304 struct drm_mode_config *config = &dev->mode_config;
6305 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6306 struct drm_atomic_state *state;
6b72d486 6307 struct drm_crtc *crtc;
70e0bd74
ML		 6308 unsigned crtc_mask = 0;
6309 int ret = 0;
6310
6311 if (WARN_ON(!ctx))
6312 return 0;
6313
6314 lockdep_assert_held(&ctx->ww_ctx);
6315 state = drm_atomic_state_alloc(dev);
6316 if (WARN_ON(!state))
6317 return -ENOMEM;
6318
6319 state->acquire_ctx = ctx;
6320 state->allow_modeset = true;
6321
6322 for_each_crtc(dev, crtc) {
6323 struct drm_crtc_state *crtc_state =
6324 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6325
70e0bd74
ML		 6326 ret = PTR_ERR_OR_ZERO(crtc_state);
6327 if (ret)
6328 goto free;
6329
6330 if (!crtc_state->active)
6331 continue;
6332
6333 crtc_state->active = false;
6334 crtc_mask |= 1 << drm_crtc_index(crtc);
6335 }
6336
6337 if (crtc_mask) {
74c090b1 6338 ret = drm_atomic_commit(state);
70e0bd74
ML		 6339
6340 if (!ret) {
6341 for_each_crtc(dev, crtc)
6342 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6343 crtc->state->active = true;
6344
6345 return ret;
6346 }
6347 }
6348
6349free:
6350 if (ret)
6351 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6352 drm_atomic_state_free(state);
6353 return ret;
ee7b9f93
JB		 6354}
6355
ea5b213a 6356void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6357{
4ef69c7a 6358 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6359
ea5b213a
CW		 6360 drm_encoder_cleanup(encoder);
6361 kfree(intel_encoder);
7e7d76c3
JB		 6362}
6363
0a91ca29
DV		 6364/* Cross check the actual hw state with our own modeset state tracking (and it's
6365 * internal consistency). */
b980514c 6366static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6367{
35dd3c64
ML		 6368 struct drm_crtc *crtc = connector->base.state->crtc;
6369
6370 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6371 connector->base.base.id,
6372 connector->base.name);
6373
0a91ca29 6374 if (connector->get_hw_state(connector)) {
e85376cb 6375 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6376 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6377
35dd3c64
ML		 6378 I915_STATE_WARN(!crtc,
6379 "connector enabled without attached crtc\n");
0a91ca29 6380
35dd3c64
ML		 6381 if (!crtc)
6382 return;
6383
6384 I915_STATE_WARN(!crtc->state->active,
6385 "connector is active, but attached crtc isn't\n");
6386
e85376cb 6387 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6388 return;
6389
e85376cb 6390 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6391 "atomic encoder doesn't match attached encoder\n");
6392
e85376cb 6393 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6394 "attached encoder crtc differs from connector crtc\n");
6395 } else {
4d688a2a
ML		 6396 I915_STATE_WARN(crtc && crtc->state->active,
6397 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6398 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6399 "best encoder set without crtc!\n");
0a91ca29 6400 }
79e53945
JB		 6401}
6402
08d9bc92
ACO		 6403int intel_connector_init(struct intel_connector *connector)
6404{
6405 struct drm_connector_state *connector_state;
6406
6407 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6408 if (!connector_state)
6409 return -ENOMEM;
6410
6411 connector->base.state = connector_state;
6412 return 0;
6413}
6414
6415struct intel_connector *intel_connector_alloc(void)
6416{
6417 struct intel_connector *connector;
6418
6419 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6420 if (!connector)
6421 return NULL;
6422
6423 if (intel_connector_init(connector) < 0) {
6424 kfree(connector);
6425 return NULL;
6426 }
6427
6428 return connector;
6429}
6430
f0947c37
DV		 6431/* Simple connector->get_hw_state implementation for encoders that support only
6432 * one connector and no cloning and hence the encoder state determines the state
6433 * of the connector. */
6434bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6435{
24929352 6436 enum pipe pipe = 0;
f0947c37 6437 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6438
f0947c37 6439 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6440}
6441
6d293983 6442static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6443{
6d293983
ACO		 6444 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6445 return crtc_state->fdi_lanes;
d272ddfa
VS		 6446
6447 return 0;
6448}
6449
6d293983 6450static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6451 struct intel_crtc_state *pipe_config)
1857e1da 6452{
6d293983
ACO		 6453 struct drm_atomic_state *state = pipe_config->base.state;
6454 struct intel_crtc *other_crtc;
6455 struct intel_crtc_state *other_crtc_state;
6456
1857e1da
DV		 6457 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6458 pipe_name(pipe), pipe_config->fdi_lanes);
6459 if (pipe_config->fdi_lanes > 4) {
6460 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6461 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6462 return -EINVAL;
1857e1da
DV		 6463 }
6464
bafb6553 6465 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6466 if (pipe_config->fdi_lanes > 2) {
6467 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6468 pipe_config->fdi_lanes);
6d293983 6469 return -EINVAL;
1857e1da 6470 } else {
6d293983 6471 return 0;
1857e1da
DV		 6472 }
6473 }
6474
6475 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6476 return 0;
1857e1da
DV		 6477
6478 /* Ivybridge 3 pipe is really complicated */
6479 switch (pipe) {
6480 case PIPE_A:
6d293983 6481 return 0;
1857e1da 6482 case PIPE_B:
6d293983
ACO		 6483 if (pipe_config->fdi_lanes <= 2)
6484 return 0;
6485
6486 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6487 other_crtc_state =
6488 intel_atomic_get_crtc_state(state, other_crtc);
6489 if (IS_ERR(other_crtc_state))
6490 return PTR_ERR(other_crtc_state);
6491
6492 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6493 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6494 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6495 return -EINVAL;
1857e1da 6496 }
6d293983 6497 return 0;
1857e1da 6498 case PIPE_C:
251cc67c
VS		 6499 if (pipe_config->fdi_lanes > 2) {
6500 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6501 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6502 return -EINVAL;
251cc67c 6503 }
6d293983
ACO		 6504
6505 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6506 other_crtc_state =
6507 intel_atomic_get_crtc_state(state, other_crtc);
6508 if (IS_ERR(other_crtc_state))
6509 return PTR_ERR(other_crtc_state);
6510
6511 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6512 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6513 return -EINVAL;
1857e1da 6514 }
6d293983 6515 return 0;
1857e1da
DV		 6516 default:
6517 BUG();
6518 }
6519}
6520
e29c22c0
DV		 6521#define RETRY 1
6522static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6523 struct intel_crtc_state *pipe_config)
877d48d5 6524{
1857e1da 6525 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6526 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6527 int lane, link_bw, fdi_dotclock, ret;
6528 bool needs_recompute = false;
877d48d5 6529
e29c22c0 6530retry:
877d48d5
DV		 6531 /* FDI is a binary signal running at ~2.7GHz, encoding
6532 * each output octet as 10 bits. The actual frequency
6533 * is stored as a divider into a 100MHz clock, and the
6534 * mode pixel clock is stored in units of 1KHz.
6535 * Hence the bw of each lane in terms of the mode signal
6536 * is:
6537 */
6538 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6539
241bfc38 6540 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6541
2bd89a07 6542 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6543 pipe_config->pipe_bpp);
6544
6545 pipe_config->fdi_lanes = lane;
6546
2bd89a07 6547 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6548 link_bw, &pipe_config->fdi_m_n);
1857e1da 6549
6d293983
ACO		 6550 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6551 intel_crtc->pipe, pipe_config);
6552 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6553 pipe_config->pipe_bpp -= 2*3;
6554 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6555 pipe_config->pipe_bpp);
6556 needs_recompute = true;
6557 pipe_config->bw_constrained = true;
6558
6559 goto retry;
6560 }
6561
6562 if (needs_recompute)
6563 return RETRY;
6564
6d293983 6565 return ret;
877d48d5
DV		 6566}
6567
8cfb3407
VS		 6568static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6569 struct intel_crtc_state *pipe_config)
6570{
6571 if (pipe_config->pipe_bpp > 24)
6572 return false;
6573
6574 /* HSW can handle pixel rate up to cdclk? */
6575 if (IS_HASWELL(dev_priv->dev))
6576 return true;
6577
6578 /*
b432e5cf
VS		 6579 * We compare against max which means we must take
6580 * the increased cdclk requirement into account when
6581 * calculating the new cdclk.
6582 *
6583 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6584 */
6585 return ilk_pipe_pixel_rate(pipe_config) <=
6586 dev_priv->max_cdclk_freq * 95 / 100;
6587}
6588
42db64ef 6589static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6590 struct intel_crtc_state *pipe_config)
42db64ef 6591{
8cfb3407
VS		 6592 struct drm_device *dev = crtc->base.dev;
6593 struct drm_i915_private *dev_priv = dev->dev_private;
6594
d330a953 6595 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6596 hsw_crtc_supports_ips(crtc) &&
6597 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6598}
6599
39acb4aa
VS		 6600static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6601{
6602 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6603
6604 /* GDG double wide on either pipe, otherwise pipe A only */
6605 return INTEL_INFO(dev_priv)->gen < 4 &&
6606 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6607}
6608
a43f6e0f 6609static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6610 struct intel_crtc_state *pipe_config)
79e53945 6611{
a43f6e0f 6612 struct drm_device *dev = crtc->base.dev;
8bd31e67 6613 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6614 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6615
ad3a4479 6616 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6617 if (INTEL_INFO(dev)->gen < 4) {
39acb4aa 6618 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
cf532bb2
VS		 6619
6620 /*
39acb4aa 6621 * Enable double wide mode when the dot clock
cf532bb2 6622 * is > 90% of the (display) core speed.
cf532bb2 6623 */
39acb4aa
VS		 6624 if (intel_crtc_supports_double_wide(crtc) &&
6625 adjusted_mode->crtc_clock > clock_limit) {
ad3a4479 6626 clock_limit *= 2;
cf532bb2 6627 pipe_config->double_wide = true;
ad3a4479
VS		 6628 }
6629
39acb4aa
VS		 6630 if (adjusted_mode->crtc_clock > clock_limit) {
6631 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6632 adjusted_mode->crtc_clock, clock_limit,
6633 yesno(pipe_config->double_wide));
e29c22c0 6634 return -EINVAL;
39acb4aa 6635 }
2c07245f 6636 }
89749350 6637
1d1d0e27
VS		 6638 /*
6639 * Pipe horizontal size must be even in:
6640 * - DVO ganged mode
6641 * - LVDS dual channel mode
6642 * - Double wide pipe
6643 */
a93e255f 6644 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6645 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6646 pipe_config->pipe_src_w &= ~1;
6647
8693a824
DL		 6648 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6649 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6650 */
6651 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6652 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6653 return -EINVAL;
44f46b42 6654
f5adf94e 6655 if (HAS_IPS(dev))
a43f6e0f
DV		 6656 hsw_compute_ips_config(crtc, pipe_config);
6657
877d48d5 6658 if (pipe_config->has_pch_encoder)
a43f6e0f 6659 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6660
cf5a15be 6661 return 0;
79e53945
JB		 6662}
6663
1652d19e
VS		 6664static int skylake_get_display_clock_speed(struct drm_device *dev)
6665{
6666 struct drm_i915_private *dev_priv = to_i915(dev);
6667 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6668 uint32_t cdctl = I915_READ(CDCLK_CTL);
6669 uint32_t linkrate;
6670
414355a7 6671 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6672 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6673
6674 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6675 return 540000;
6676
6677 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6678 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6679
71cd8423
DL		 6680 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6681 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6682 /* vco 8640 */
6683 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6684 case CDCLK_FREQ_450_432:
6685 return 432000;
6686 case CDCLK_FREQ_337_308:
6687 return 308570;
6688 case CDCLK_FREQ_675_617:
6689 return 617140;
6690 default:
6691 WARN(1, "Unknown cd freq selection\n");
6692 }
6693 } else {
6694 /* vco 8100 */
6695 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6696 case CDCLK_FREQ_450_432:
6697 return 450000;
6698 case CDCLK_FREQ_337_308:
6699 return 337500;
6700 case CDCLK_FREQ_675_617:
6701 return 675000;
6702 default:
6703 WARN(1, "Unknown cd freq selection\n");
6704 }
6705 }
6706
6707 /* error case, do as if DPLL0 isn't enabled */
6708 return 24000;
6709}
6710
acd3f3d3
BP		 6711static int broxton_get_display_clock_speed(struct drm_device *dev)
6712{
6713 struct drm_i915_private *dev_priv = to_i915(dev);
6714 uint32_t cdctl = I915_READ(CDCLK_CTL);
6715 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6716 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6717 int cdclk;
6718
6719 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6720 return 19200;
6721
6722 cdclk = 19200 * pll_ratio / 2;
6723
6724 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6725 case BXT_CDCLK_CD2X_DIV_SEL_1:
6726 return cdclk; /* 576MHz or 624MHz */
6727 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6728 return cdclk * 2 / 3; /* 384MHz */
6729 case BXT_CDCLK_CD2X_DIV_SEL_2:
6730 return cdclk / 2; /* 288MHz */
6731 case BXT_CDCLK_CD2X_DIV_SEL_4:
6732 return cdclk / 4; /* 144MHz */
6733 }
6734
6735 /* error case, do as if DE PLL isn't enabled */
6736 return 19200;
6737}
6738
1652d19e
VS		 6739static int broadwell_get_display_clock_speed(struct drm_device *dev)
6740{
6741 struct drm_i915_private *dev_priv = dev->dev_private;
6742 uint32_t lcpll = I915_READ(LCPLL_CTL);
6743 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6744
6745 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6746 return 800000;
6747 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6748 return 450000;
6749 else if (freq == LCPLL_CLK_FREQ_450)
6750 return 450000;
6751 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6752 return 540000;
6753 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6754 return 337500;
6755 else
6756 return 675000;
6757}
6758
6759static int haswell_get_display_clock_speed(struct drm_device *dev)
6760{
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 uint32_t lcpll = I915_READ(LCPLL_CTL);
6763 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6764
6765 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6766 return 800000;
6767 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6768 return 450000;
6769 else if (freq == LCPLL_CLK_FREQ_450)
6770 return 450000;
6771 else if (IS_HSW_ULT(dev))
6772 return 337500;
6773 else
6774 return 540000;
79e53945
JB		 6775}
6776
25eb05fc
JB		 6777static int valleyview_get_display_clock_speed(struct drm_device *dev)
6778{
bfa7df01
VS		 6779 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6780 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6781}
6782
b37a6434
VS		 6783static int ilk_get_display_clock_speed(struct drm_device *dev)
6784{
6785 return 450000;
6786}
6787
e70236a8
JB		 6788static int i945_get_display_clock_speed(struct drm_device *dev)
6789{
6790 return 400000;
6791}
79e53945 6792
e70236a8 6793static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6794{
e907f170 6795 return 333333;
e70236a8 6796}
79e53945 6797
e70236a8
JB		 6798static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6799{
6800 return 200000;
6801}
79e53945 6802
257a7ffc
DV		 6803static int pnv_get_display_clock_speed(struct drm_device *dev)
6804{
6805 u16 gcfgc = 0;
6806
6807 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6808
6809 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6810 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6811 return 266667;
257a7ffc 6812 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6813 return 333333;
257a7ffc 6814 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6815 return 444444;
257a7ffc
DV		 6816 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6817 return 200000;
6818 default:
6819 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6820 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6821 return 133333;
257a7ffc 6822 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6823 return 166667;
257a7ffc
DV		 6824 }
6825}
6826
e70236a8
JB		 6827static int i915gm_get_display_clock_speed(struct drm_device *dev)
6828{
6829 u16 gcfgc = 0;
79e53945 6830
e70236a8
JB		 6831 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6832
6833 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6834 return 133333;
e70236a8
JB		 6835 else {
6836 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6837 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6838 return 333333;
e70236a8
JB		 6839 default:
6840 case GC_DISPLAY_CLOCK_190_200_MHZ:
6841 return 190000;
79e53945 6842 }
e70236a8
JB		 6843 }
6844}
6845
6846static int i865_get_display_clock_speed(struct drm_device *dev)
6847{
e907f170 6848 return 266667;
e70236a8
JB		 6849}
6850
1b1d2716 6851static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6852{
6853 u16 hpllcc = 0;
1b1d2716 6854
65cd2b3f
VS		 6855 /*
6856 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6857 * encoding is different :(
6858 * FIXME is this the right way to detect 852GM/852GMV?
6859 */
6860 if (dev->pdev->revision == 0x1)
6861 return 133333;
6862
1b1d2716
VS		 6863 pci_bus_read_config_word(dev->pdev->bus,
6864 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6865
e70236a8
JB		 6866 /* Assume that the hardware is in the high speed state. This
6867 * should be the default.
6868 */
6869 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6870 case GC_CLOCK_133_200:
1b1d2716 6871 case GC_CLOCK_133_200_2:
e70236a8
JB		 6872 case GC_CLOCK_100_200:
6873 return 200000;
6874 case GC_CLOCK_166_250:
6875 return 250000;
6876 case GC_CLOCK_100_133:
e907f170 6877 return 133333;
1b1d2716
VS		 6878 case GC_CLOCK_133_266:
6879 case GC_CLOCK_133_266_2:
6880 case GC_CLOCK_166_266:
6881 return 266667;
e70236a8 6882 }
79e53945 6883
e70236a8
JB		 6884 /* Shouldn't happen */
6885 return 0;
6886}
79e53945 6887
e70236a8
JB		 6888static int i830_get_display_clock_speed(struct drm_device *dev)
6889{
e907f170 6890 return 133333;
79e53945
JB		 6891}
6892
34edce2f
VS		 6893static unsigned int intel_hpll_vco(struct drm_device *dev)
6894{
6895 struct drm_i915_private *dev_priv = dev->dev_private;
6896 static const unsigned int blb_vco[8] = {
6897 [0] = 3200000,
6898 [1] = 4000000,
6899 [2] = 5333333,
6900 [3] = 4800000,
6901 [4] = 6400000,
6902 };
6903 static const unsigned int pnv_vco[8] = {
6904 [0] = 3200000,
6905 [1] = 4000000,
6906 [2] = 5333333,
6907 [3] = 4800000,
6908 [4] = 2666667,
6909 };
6910 static const unsigned int cl_vco[8] = {
6911 [0] = 3200000,
6912 [1] = 4000000,
6913 [2] = 5333333,
6914 [3] = 6400000,
6915 [4] = 3333333,
6916 [5] = 3566667,
6917 [6] = 4266667,
6918 };
6919 static const unsigned int elk_vco[8] = {
6920 [0] = 3200000,
6921 [1] = 4000000,
6922 [2] = 5333333,
6923 [3] = 4800000,
6924 };
6925 static const unsigned int ctg_vco[8] = {
6926 [0] = 3200000,
6927 [1] = 4000000,
6928 [2] = 5333333,
6929 [3] = 6400000,
6930 [4] = 2666667,
6931 [5] = 4266667,
6932 };
6933 const unsigned int *vco_table;
6934 unsigned int vco;
6935 uint8_t tmp = 0;
6936
6937 /* FIXME other chipsets? */
6938 if (IS_GM45(dev))
6939 vco_table = ctg_vco;
6940 else if (IS_G4X(dev))
6941 vco_table = elk_vco;
6942 else if (IS_CRESTLINE(dev))
6943 vco_table = cl_vco;
6944 else if (IS_PINEVIEW(dev))
6945 vco_table = pnv_vco;
6946 else if (IS_G33(dev))
6947 vco_table = blb_vco;
6948 else
6949 return 0;
6950
6951 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6952
6953 vco = vco_table[tmp & 0x7];
6954 if (vco == 0)
6955 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6956 else
6957 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6958
6959 return vco;
6960}
6961
6962static int gm45_get_display_clock_speed(struct drm_device *dev)
6963{
6964 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6965 uint16_t tmp = 0;
6966
6967 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6968
6969 cdclk_sel = (tmp >> 12) & 0x1;
6970
6971 switch (vco) {
6972 case 2666667:
6973 case 4000000:
6974 case 5333333:
6975 return cdclk_sel ? 333333 : 222222;
6976 case 3200000:
6977 return cdclk_sel ? 320000 : 228571;
6978 default:
6979 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6980 return 222222;
6981 }
6982}
6983
6984static int i965gm_get_display_clock_speed(struct drm_device *dev)
6985{
6986 static const uint8_t div_3200[] = { 16, 10, 8 };
6987 static const uint8_t div_4000[] = { 20, 12, 10 };
6988 static const uint8_t div_5333[] = { 24, 16, 14 };
6989 const uint8_t *div_table;
6990 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6991 uint16_t tmp = 0;
6992
6993 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6994
6995 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6996
6997 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6998 goto fail;
6999
7000 switch (vco) {
7001 case 3200000:
7002 div_table = div_3200;
7003 break;
7004 case 4000000:
7005 div_table = div_4000;
7006 break;
7007 case 5333333:
7008 div_table = div_5333;
7009 break;
7010 default:
7011 goto fail;
7012 }
7013
7014 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7015
caf4e252 7016fail:
34edce2f
VS		 7017 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7018 return 200000;
7019}
7020
7021static int g33_get_display_clock_speed(struct drm_device *dev)
7022{
7023 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7024 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7025 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7026 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7027 const uint8_t *div_table;
7028 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7029 uint16_t tmp = 0;
7030
7031 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7032
7033 cdclk_sel = (tmp >> 4) & 0x7;
7034
7035 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7036 goto fail;
7037
7038 switch (vco) {
7039 case 3200000:
7040 div_table = div_3200;
7041 break;
7042 case 4000000:
7043 div_table = div_4000;
7044 break;
7045 case 4800000:
7046 div_table = div_4800;
7047 break;
7048 case 5333333:
7049 div_table = div_5333;
7050 break;
7051 default:
7052 goto fail;
7053 }
7054
7055 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7056
caf4e252 7057fail:
34edce2f
VS		 7058 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7059 return 190476;
7060}
7061
2c07245f 7062static void
a65851af 7063intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7064{
a65851af
VS		 7065 while (*num > DATA_LINK_M_N_MASK ||
7066 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7067 *num >>= 1;
7068 *den >>= 1;
7069 }
7070}
7071
a65851af
VS		 7072static void compute_m_n(unsigned int m, unsigned int n,
7073 uint32_t *ret_m, uint32_t *ret_n)
7074{
7075 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7076 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7077 intel_reduce_m_n_ratio(ret_m, ret_n);
7078}
7079
e69d0bc1
DV		 7080void
7081intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7082 int pixel_clock, int link_clock,
7083 struct intel_link_m_n *m_n)
2c07245f 7084{
e69d0bc1 7085 m_n->tu = 64;
a65851af
VS		 7086
7087 compute_m_n(bits_per_pixel * pixel_clock,
7088 link_clock * nlanes * 8,
7089 &m_n->gmch_m, &m_n->gmch_n);
7090
7091 compute_m_n(pixel_clock, link_clock,
7092 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7093}
7094
a7615030
CW		 7095static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7096{
d330a953
JN		 7097 if (i915.panel_use_ssc >= 0)
7098 return i915.panel_use_ssc != 0;
41aa3448 7099 return dev_priv->vbt.lvds_use_ssc
435793df 7100 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7101}
7102
a93e255f
ACO		 7103static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7104 int num_connectors)
c65d77d8 7105{
a93e255f 7106 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7107 struct drm_i915_private *dev_priv = dev->dev_private;
7108 int refclk;
7109
a93e255f
ACO		 7110 WARN_ON(!crtc_state->base.state);
7111
5ab7b0b7 7112 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7113 refclk = 100000;
a93e255f 7114 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7115 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7116 refclk = dev_priv->vbt.lvds_ssc_freq;
7117 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7118 } else if (!IS_GEN2(dev)) {
7119 refclk = 96000;
7120 } else {
7121 refclk = 48000;
7122 }
7123
7124 return refclk;
7125}
7126
7429e9d4 7127static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7128{
7df00d7a 7129 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7130}
f47709a9 7131
7429e9d4
DV		 7132static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7133{
7134 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7135}
7136
f47709a9 7137static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7138 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7139 intel_clock_t *reduced_clock)
7140{
f47709a9 7141 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7142 u32 fp, fp2 = 0;
7143
7144 if (IS_PINEVIEW(dev)) {
190f68c5 7145 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7146 if (reduced_clock)
7429e9d4 7147 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7148 } else {
190f68c5 7149 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7150 if (reduced_clock)
7429e9d4 7151 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7152 }
7153
190f68c5 7154 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7155
f47709a9 7156 crtc->lowfreq_avail = false;
a93e255f 7157 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7158 reduced_clock) {
190f68c5 7159 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7160 crtc->lowfreq_avail = true;
a7516a05 7161 } else {
190f68c5 7162 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7163 }
7164}
7165
5e69f97f
CML		 7166static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7167 pipe)
89b667f8
JB		 7168{
7169 u32 reg_val;
7170
7171 /*
7172 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7173 * and set it to a reasonable value instead.
7174 */
ab3c759a 7175 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7176 reg_val &= 0xffffff00;
7177 reg_val |= 0x00000030;
ab3c759a 7178 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7179
ab3c759a 7180 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7181 reg_val &= 0x8cffffff;
7182 reg_val = 0x8c000000;
ab3c759a 7183 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7184
ab3c759a 7185 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7186 reg_val &= 0xffffff00;
ab3c759a 7187 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7188
ab3c759a 7189 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7190 reg_val &= 0x00ffffff;
7191 reg_val |= 0xb0000000;
ab3c759a 7192 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7193}
7194
b551842d
DV		 7195static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7196 struct intel_link_m_n *m_n)
7197{
7198 struct drm_device *dev = crtc->base.dev;
7199 struct drm_i915_private *dev_priv = dev->dev_private;
7200 int pipe = crtc->pipe;
7201
e3b95f1e
DV		 7202 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7203 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7204 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7205 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7206}
7207
7208static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7209 struct intel_link_m_n *m_n,
7210 struct intel_link_m_n *m2_n2)
b551842d
DV		 7211{
7212 struct drm_device *dev = crtc->base.dev;
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 int pipe = crtc->pipe;
6e3c9717 7215 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7216
7217 if (INTEL_INFO(dev)->gen >= 5) {
7218 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7219 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7220 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7221 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7222 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7223 * for gen < 8) and if DRRS is supported (to make sure the
7224 * registers are not unnecessarily accessed).
7225 */
44395bfe 7226 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7227 crtc->config->has_drrs) {
f769cd24
VK		 7228 I915_WRITE(PIPE_DATA_M2(transcoder),
7229 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7230 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7231 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7232 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7233 }
b551842d 7234 } else {
e3b95f1e
DV		 7235 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7236 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7237 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7238 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7239 }
7240}
7241
fe3cd48d 7242void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7243{
fe3cd48d
R		 7244 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7245
7246 if (m_n == M1_N1) {
7247 dp_m_n = &crtc->config->dp_m_n;
7248 dp_m2_n2 = &crtc->config->dp_m2_n2;
7249 } else if (m_n == M2_N2) {
7250
7251 /*
7252 * M2_N2 registers are not supported. Hence m2_n2 divider value
7253 * needs to be programmed into M1_N1.
7254 */
7255 dp_m_n = &crtc->config->dp_m2_n2;
7256 } else {
7257 DRM_ERROR("Unsupported divider value\n");
7258 return;
7259 }
7260
6e3c9717
ACO		 7261 if (crtc->config->has_pch_encoder)
7262 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7263 else
fe3cd48d 7264 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7265}
7266
251ac862
DV		 7267static void vlv_compute_dpll(struct intel_crtc *crtc,
7268 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7269{
7270 u32 dpll, dpll_md;
7271
7272 /*
7273 * Enable DPIO clock input. We should never disable the reference
7274 * clock for pipe B, since VGA hotplug / manual detection depends
7275 * on it.
7276 */
60bfe44f
VS		 7277 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7278 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7279 /* We should never disable this, set it here for state tracking */
7280 if (crtc->pipe == PIPE_B)
7281 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7282 dpll |= DPLL_VCO_ENABLE;
d288f65f 7283 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7284
d288f65f 7285 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7286 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7287 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7288}
7289
d288f65f 7290static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7291 const struct intel_crtc_state *pipe_config)
a0c4da24 7292{
f47709a9 7293 struct drm_device *dev = crtc->base.dev;
a0c4da24 7294 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7295 int pipe = crtc->pipe;
bdd4b6a6 7296 u32 mdiv;
a0c4da24 7297 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7298 u32 coreclk, reg_val;
a0c4da24 7299
a580516d 7300 mutex_lock(&dev_priv->sb_lock);
09153000 7301
d288f65f
VS		 7302 bestn = pipe_config->dpll.n;
7303 bestm1 = pipe_config->dpll.m1;
7304 bestm2 = pipe_config->dpll.m2;
7305 bestp1 = pipe_config->dpll.p1;
7306 bestp2 = pipe_config->dpll.p2;
a0c4da24 7307
89b667f8
JB		 7308 /* See eDP HDMI DPIO driver vbios notes doc */
7309
7310 /* PLL B needs special handling */
bdd4b6a6 7311 if (pipe == PIPE_B)
5e69f97f 7312 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7313
7314 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7316
7317 /* Disable target IRef on PLL */
ab3c759a 7318 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7319 reg_val &= 0x00ffffff;
ab3c759a 7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7321
7322 /* Disable fast lock */
ab3c759a 7323 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7324
7325 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7326 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7327 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7328 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7329 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7330
7331 /*
7332 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7333 * but we don't support that).
7334 * Note: don't use the DAC post divider as it seems unstable.
7335 */
7336 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7338
a0c4da24 7339 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7341
89b667f8 7342 /* Set HBR and RBR LPF coefficients */
d288f65f 7343 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7344 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7345 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7347 0x009f0003);
89b667f8 7348 else
ab3c759a 7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7350 0x00d0000f);
7351
681a8504 7352 if (pipe_config->has_dp_encoder) {
89b667f8 7353 /* Use SSC source */
bdd4b6a6 7354 if (pipe == PIPE_A)
ab3c759a 7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7356 0x0df40000);
7357 else
ab3c759a 7358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7359 0x0df70000);
7360 } else { /* HDMI or VGA */
7361 /* Use bend source */
bdd4b6a6 7362 if (pipe == PIPE_A)
ab3c759a 7363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7364 0x0df70000);
7365 else
ab3c759a 7366 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7367 0x0df40000);
7368 }
a0c4da24 7369
ab3c759a 7370 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7371 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7372 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7373 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7374 coreclk |= 0x01000000;
ab3c759a 7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7376
ab3c759a 7377 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7378 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7379}
7380
251ac862
DV		 7381static void chv_compute_dpll(struct intel_crtc *crtc,
7382 struct intel_crtc_state *pipe_config)
1ae0d137 7383{
60bfe44f
VS		 7384 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7385 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7386 DPLL_VCO_ENABLE;
7387 if (crtc->pipe != PIPE_A)
d288f65f 7388 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7389
d288f65f
VS		 7390 pipe_config->dpll_hw_state.dpll_md =
7391 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7392}
7393
d288f65f 7394static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7395 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7396{
7397 struct drm_device *dev = crtc->base.dev;
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 int pipe = crtc->pipe;
7400 int dpll_reg = DPLL(crtc->pipe);
7401 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7402 u32 loopfilter, tribuf_calcntr;
9d556c99 7403 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7404 u32 dpio_val;
9cbe40c1 7405 int vco;
9d556c99 7406
d288f65f
VS		 7407 bestn = pipe_config->dpll.n;
7408 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7409 bestm1 = pipe_config->dpll.m1;
7410 bestm2 = pipe_config->dpll.m2 >> 22;
7411 bestp1 = pipe_config->dpll.p1;
7412 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7413 vco = pipe_config->dpll.vco;
a945ce7e 7414 dpio_val = 0;
9cbe40c1 7415 loopfilter = 0;
9d556c99
CML		 7416
7417 /*
7418 * Enable Refclk and SSC
7419 */
a11b0703 7420 I915_WRITE(dpll_reg,
d288f65f 7421 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7422
a580516d 7423 mutex_lock(&dev_priv->sb_lock);
9d556c99 7424
9d556c99
CML		 7425 /* p1 and p2 divider */
7426 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7427 5 << DPIO_CHV_S1_DIV_SHIFT |
7428 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7429 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7430 1 << DPIO_CHV_K_DIV_SHIFT);
7431
7432 /* Feedback post-divider - m2 */
7433 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7434
7435 /* Feedback refclk divider - n and m1 */
7436 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7437 DPIO_CHV_M1_DIV_BY_2 |
7438 1 << DPIO_CHV_N_DIV_SHIFT);
7439
7440 /* M2 fraction division */
25a25dfc 7441 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7442
7443 /* M2 fraction division enable */
a945ce7e
VP		 7444 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7445 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7446 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7447 if (bestm2_frac)
7448 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7449 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7450
de3a0fde
VP		 7451 /* Program digital lock detect threshold */
7452 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7453 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7454 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7455 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7456 if (!bestm2_frac)
7457 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7459
9d556c99 7460 /* Loop filter */
9cbe40c1
VP		 7461 if (vco == 5400000) {
7462 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7463 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7464 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7465 tribuf_calcntr = 0x9;
7466 } else if (vco <= 6200000) {
7467 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7468 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7469 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7470 tribuf_calcntr = 0x9;
7471 } else if (vco <= 6480000) {
7472 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7473 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7474 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7475 tribuf_calcntr = 0x8;
7476 } else {
7477 /* Not supported. Apply the same limits as in the max case */
7478 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7479 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7480 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7481 tribuf_calcntr = 0;
7482 }
9d556c99
CML		 7483 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7484
968040b2 7485 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7486 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7487 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7488 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7489
9d556c99
CML		 7490 /* AFC Recal */
7491 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7492 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7493 DPIO_AFC_RECAL);
7494
a580516d 7495 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7496}
7497
d288f65f
VS		 7498/**
7499 * vlv_force_pll_on - forcibly enable just the PLL
7500 * @dev_priv: i915 private structure
7501 * @pipe: pipe PLL to enable
7502 * @dpll: PLL configuration
7503 *
7504 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7505 * in cases where we need the PLL enabled even when @pipe is not going to
7506 * be enabled.
7507 */
7508void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7509 const struct dpll *dpll)
7510{
7511 struct intel_crtc *crtc =
7512 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7513 struct intel_crtc_state pipe_config = {
a93e255f 7514 .base.crtc = &crtc->base,
d288f65f
VS		 7515 .pixel_multiplier = 1,
7516 .dpll = *dpll,
7517 };
7518
7519 if (IS_CHERRYVIEW(dev)) {
251ac862 7520 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7521 chv_prepare_pll(crtc, &pipe_config);
7522 chv_enable_pll(crtc, &pipe_config);
7523 } else {
251ac862 7524 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7525 vlv_prepare_pll(crtc, &pipe_config);
7526 vlv_enable_pll(crtc, &pipe_config);
7527 }
7528}
7529
7530/**
7531 * vlv_force_pll_off - forcibly disable just the PLL
7532 * @dev_priv: i915 private structure
7533 * @pipe: pipe PLL to disable
7534 *
7535 * Disable the PLL for @pipe. To be used in cases where we need
7536 * the PLL enabled even when @pipe is not going to be enabled.
7537 */
7538void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7539{
7540 if (IS_CHERRYVIEW(dev))
7541 chv_disable_pll(to_i915(dev), pipe);
7542 else
7543 vlv_disable_pll(to_i915(dev), pipe);
7544}
7545
251ac862
DV		 7546static void i9xx_compute_dpll(struct intel_crtc *crtc,
7547 struct intel_crtc_state *crtc_state,
7548 intel_clock_t *reduced_clock,
7549 int num_connectors)
eb1cbe48 7550{
f47709a9 7551 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7552 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7553 u32 dpll;
7554 bool is_sdvo;
190f68c5 7555 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7556
190f68c5 7557 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7558
a93e255f
ACO		 7559 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7560 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7561
7562 dpll = DPLL_VGA_MODE_DIS;
7563
a93e255f 7564 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7565 dpll |= DPLLB_MODE_LVDS;
7566 else
7567 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7568
ef1b460d 7569 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7570 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7571 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7572 }
198a037f
DV		 7573
7574 if (is_sdvo)
4a33e48d 7575 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7576
190f68c5 7577 if (crtc_state->has_dp_encoder)
4a33e48d 7578 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7579
7580 /* compute bitmask from p1 value */
7581 if (IS_PINEVIEW(dev))
7582 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7583 else {
7584 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7585 if (IS_G4X(dev) && reduced_clock)
7586 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7587 }
7588 switch (clock->p2) {
7589 case 5:
7590 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7591 break;
7592 case 7:
7593 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7594 break;
7595 case 10:
7596 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7597 break;
7598 case 14:
7599 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7600 break;
7601 }
7602 if (INTEL_INFO(dev)->gen >= 4)
7603 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7604
190f68c5 7605 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7606 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7607 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7608 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7609 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7610 else
7611 dpll |= PLL_REF_INPUT_DREFCLK;
7612
7613 dpll |= DPLL_VCO_ENABLE;
190f68c5 7614 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7615
eb1cbe48 7616 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7617 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7618 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7619 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7620 }
7621}
7622
251ac862
DV		 7623static void i8xx_compute_dpll(struct intel_crtc *crtc,
7624 struct intel_crtc_state *crtc_state,
7625 intel_clock_t *reduced_clock,
7626 int num_connectors)
eb1cbe48 7627{
f47709a9 7628 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7629 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7630 u32 dpll;
190f68c5 7631 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7632
190f68c5 7633 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7634
eb1cbe48
DV		 7635 dpll = DPLL_VGA_MODE_DIS;
7636
a93e255f 7637 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7638 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7639 } else {
7640 if (clock->p1 == 2)
7641 dpll |= PLL_P1_DIVIDE_BY_TWO;
7642 else
7643 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7644 if (clock->p2 == 4)
7645 dpll |= PLL_P2_DIVIDE_BY_4;
7646 }
7647
a93e255f 7648 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7649 dpll |= DPLL_DVO_2X_MODE;
7650
a93e255f 7651 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7652 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7653 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7654 else
7655 dpll |= PLL_REF_INPUT_DREFCLK;
7656
7657 dpll |= DPLL_VCO_ENABLE;
190f68c5 7658 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7659}
7660
8a654f3b 7661static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7662{
7663 struct drm_device *dev = intel_crtc->base.dev;
7664 struct drm_i915_private *dev_priv = dev->dev_private;
7665 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7666 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7667 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7668 uint32_t crtc_vtotal, crtc_vblank_end;
7669 int vsyncshift = 0;
4d8a62ea
DV		 7670
7671 /* We need to be careful not to changed the adjusted mode, for otherwise
7672 * the hw state checker will get angry at the mismatch. */
7673 crtc_vtotal = adjusted_mode->crtc_vtotal;
7674 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7675
609aeaca 7676 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7677 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7678 crtc_vtotal -= 1;
7679 crtc_vblank_end -= 1;
609aeaca 7680
409ee761 7681 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7682 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7683 else
7684 vsyncshift = adjusted_mode->crtc_hsync_start -
7685 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7686 if (vsyncshift < 0)
7687 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7688 }
7689
7690 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7691 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7692
fe2b8f9d 7693 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7694 (adjusted_mode->crtc_hdisplay - 1) |
7695 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7696 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7697 (adjusted_mode->crtc_hblank_start - 1) |
7698 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7699 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7700 (adjusted_mode->crtc_hsync_start - 1) |
7701 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7702
fe2b8f9d 7703 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7704 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7705 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7706 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7707 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7708 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7709 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7710 (adjusted_mode->crtc_vsync_start - 1) |
7711 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7712
b5e508d4
PZ		 7713 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7714 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7715 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7716 * bits. */
7717 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7718 (pipe == PIPE_B || pipe == PIPE_C))
7719 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7720
b0e77b9c
PZ		 7721 /* pipesrc controls the size that is scaled from, which should
7722 * always be the user's requested size.
7723 */
7724 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7725 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7726 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7727}
7728
1bd1bd80 7729static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7730 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7731{
7732 struct drm_device *dev = crtc->base.dev;
7733 struct drm_i915_private *dev_priv = dev->dev_private;
7734 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7735 uint32_t tmp;
7736
7737 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7738 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7739 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7740 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7741 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7742 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7743 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7744 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7745 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7746
7747 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7748 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7749 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7750 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7751 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7752 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7753 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7754 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7755 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7756
7757 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7758 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7759 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7760 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7761 }
7762
7763 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7764 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7765 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7766
2d112de7
ACO		 7767 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7768 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7769}
7770
f6a83288 7771void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7772 struct intel_crtc_state *pipe_config)
babea61d 7773{
2d112de7
ACO		 7774 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7775 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7776 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7777 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7778
2d112de7
ACO		 7779 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7780 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7781 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7782 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7783
2d112de7 7784 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7785 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7786
2d112de7
ACO		 7787 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7788 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7789
7790 mode->hsync = drm_mode_hsync(mode);
7791 mode->vrefresh = drm_mode_vrefresh(mode);
7792 drm_mode_set_name(mode);
babea61d
JB		 7793}
7794
84b046f3
DV		 7795static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7796{
7797 struct drm_device *dev = intel_crtc->base.dev;
7798 struct drm_i915_private *dev_priv = dev->dev_private;
7799 uint32_t pipeconf;
7800
9f11a9e4 7801 pipeconf = 0;
84b046f3 7802
b6b5d049
VS		 7803 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7804 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7805 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7806
6e3c9717 7807 if (intel_crtc->config->double_wide)
cf532bb2 7808 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7809
ff9ce46e
DV		 7810 /* only g4x and later have fancy bpc/dither controls */
7811 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7812 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7813 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7814 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7815 PIPECONF_DITHER_TYPE_SP;
84b046f3 7816
6e3c9717 7817 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7818 case 18:
7819 pipeconf |= PIPECONF_6BPC;
7820 break;
7821 case 24:
7822 pipeconf |= PIPECONF_8BPC;
7823 break;
7824 case 30:
7825 pipeconf |= PIPECONF_10BPC;
7826 break;
7827 default:
7828 /* Case prevented by intel_choose_pipe_bpp_dither. */
7829 BUG();
84b046f3
DV		 7830 }
7831 }
7832
7833 if (HAS_PIPE_CXSR(dev)) {
7834 if (intel_crtc->lowfreq_avail) {
7835 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7836 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7837 } else {
7838 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7839 }
7840 }
7841
6e3c9717 7842 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7843 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7844 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7845 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7846 else
7847 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7848 } else
84b046f3
DV		 7849 pipeconf |= PIPECONF_PROGRESSIVE;
7850
6e3c9717 7851 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7852 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7853
84b046f3
DV		 7854 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7855 POSTING_READ(PIPECONF(intel_crtc->pipe));
7856}
7857
190f68c5
ACO		 7858static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7859 struct intel_crtc_state *crtc_state)
79e53945 7860{
c7653199 7861 struct drm_device *dev = crtc->base.dev;
79e53945 7862 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7863 int refclk, num_connectors = 0;
c329a4ec
DV		 7864 intel_clock_t clock;
7865 bool ok;
7866 bool is_dsi = false;
5eddb70b 7867 struct intel_encoder *encoder;
d4906093 7868 const intel_limit_t *limit;
55bb9992 7869 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7870 struct drm_connector *connector;
55bb9992
ACO		 7871 struct drm_connector_state *connector_state;
7872 int i;
79e53945 7873
dd3cd74a
ACO		 7874 memset(&crtc_state->dpll_hw_state, 0,
7875 sizeof(crtc_state->dpll_hw_state));
7876
da3ced29 7877 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7878 if (connector_state->crtc != &crtc->base)
7879 continue;
7880
7881 encoder = to_intel_encoder(connector_state->best_encoder);
7882
5eddb70b 7883 switch (encoder->type) {
e9fd1c02
JN		 7884 case INTEL_OUTPUT_DSI:
7885 is_dsi = true;
7886 break;
6847d71b
PZ		 7887 default:
7888 break;
79e53945 7889 }
43565a06 7890
c751ce4f 7891 num_connectors++;
79e53945
JB		 7892 }
7893
f2335330 7894 if (is_dsi)
5b18e57c 7895 return 0;
f2335330 7896
190f68c5 7897 if (!crtc_state->clock_set) {
a93e255f 7898 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7899
e9fd1c02
JN		 7900 /*
7901 * Returns a set of divisors for the desired target clock with
7902 * the given refclk, or FALSE. The returned values represent
7903 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7904 * 2) / p1 / p2.
7905 */
a93e255f
ACO		 7906 limit = intel_limit(crtc_state, refclk);
7907 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7908 crtc_state->port_clock,
e9fd1c02 7909 refclk, NULL, &clock);
f2335330 7910 if (!ok) {
e9fd1c02
JN		 7911 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7912 return -EINVAL;
7913 }
79e53945 7914
f2335330 7915 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7916 crtc_state->dpll.n = clock.n;
7917 crtc_state->dpll.m1 = clock.m1;
7918 crtc_state->dpll.m2 = clock.m2;
7919 crtc_state->dpll.p1 = clock.p1;
7920 crtc_state->dpll.p2 = clock.p2;
f47709a9 7921 }
7026d4ac 7922
e9fd1c02 7923 if (IS_GEN2(dev)) {
c329a4ec 7924 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7925 num_connectors);
9d556c99 7926 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7927 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7928 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7929 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7930 } else {
c329a4ec 7931 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7932 num_connectors);
e9fd1c02 7933 }
79e53945 7934
c8f7a0db 7935 return 0;
f564048e
EA		 7936}
7937
2fa2fe9a 7938static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7939 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7940{
7941 struct drm_device *dev = crtc->base.dev;
7942 struct drm_i915_private *dev_priv = dev->dev_private;
7943 uint32_t tmp;
7944
dc9e7dec
VS		 7945 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7946 return;
7947
2fa2fe9a 7948 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7949 if (!(tmp & PFIT_ENABLE))
7950 return;
2fa2fe9a 7951
06922821 7952 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7953 if (INTEL_INFO(dev)->gen < 4) {
7954 if (crtc->pipe != PIPE_B)
7955 return;
2fa2fe9a
DV		 7956 } else {
7957 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7958 return;
7959 }
7960
06922821 7961 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7962 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7963 if (INTEL_INFO(dev)->gen < 5)
7964 pipe_config->gmch_pfit.lvds_border_bits =
7965 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7966}
7967
acbec814 7968static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7969 struct intel_crtc_state *pipe_config)
acbec814
JB		 7970{
7971 struct drm_device *dev = crtc->base.dev;
7972 struct drm_i915_private *dev_priv = dev->dev_private;
7973 int pipe = pipe_config->cpu_transcoder;
7974 intel_clock_t clock;
7975 u32 mdiv;
662c6ecb 7976 int refclk = 100000;
acbec814 7977
f573de5a
SK		 7978 /* In case of MIPI DPLL will not even be used */
7979 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7980 return;
7981
a580516d 7982 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7983 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7984 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7985
7986 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7987 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7988 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7989 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7990 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7991
dccbea3b 7992 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7993}
7994
5724dbd1
DL		 7995static void
7996i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7997 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7998{
7999 struct drm_device *dev = crtc->base.dev;
8000 struct drm_i915_private *dev_priv = dev->dev_private;
8001 u32 val, base, offset;
8002 int pipe = crtc->pipe, plane = crtc->plane;
8003 int fourcc, pixel_format;
6761dd31 8004 unsigned int aligned_height;
b113d5ee 8005 struct drm_framebuffer *fb;
1b842c89 8006 struct intel_framebuffer *intel_fb;
1ad292b5 8007
42a7b088
DL		 8008 val = I915_READ(DSPCNTR(plane));
8009 if (!(val & DISPLAY_PLANE_ENABLE))
8010 return;
8011
d9806c9f 8012 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8013 if (!intel_fb) {
1ad292b5
JB		 8014 DRM_DEBUG_KMS("failed to alloc fb\n");
8015 return;
8016 }
8017
1b842c89
DL		 8018 fb = &intel_fb->base;
8019
18c5247e
DV		 8020 if (INTEL_INFO(dev)->gen >= 4) {
8021 if (val & DISPPLANE_TILED) {
49af449b 8022 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8023 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8024 }
8025 }
1ad292b5
JB		 8026
8027 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8028 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8029 fb->pixel_format = fourcc;
8030 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8031
8032 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8033 if (plane_config->tiling)
1ad292b5
JB		 8034 offset = I915_READ(DSPTILEOFF(plane));
8035 else
8036 offset = I915_READ(DSPLINOFF(plane));
8037 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8038 } else {
8039 base = I915_READ(DSPADDR(plane));
8040 }
8041 plane_config->base = base;
8042
8043 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8044 fb->width = ((val >> 16) & 0xfff) + 1;
8045 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8046
8047 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8048 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8049
b113d5ee 8050 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8051 fb->pixel_format,
8052 fb->modifier[0]);
1ad292b5 8053
f37b5c2b 8054 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8055
2844a921
DL		 8056 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8057 pipe_name(pipe), plane, fb->width, fb->height,
8058 fb->bits_per_pixel, base, fb->pitches[0],
8059 plane_config->size);
1ad292b5 8060
2d14030b 8061 plane_config->fb = intel_fb;
1ad292b5
JB		 8062}
8063
70b23a98 8064static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8065 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8066{
8067 struct drm_device *dev = crtc->base.dev;
8068 struct drm_i915_private *dev_priv = dev->dev_private;
8069 int pipe = pipe_config->cpu_transcoder;
8070 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8071 intel_clock_t clock;
0d7b6b11 8072 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8073 int refclk = 100000;
8074
a580516d 8075 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8076 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8077 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8078 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8079 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8080 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8081 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8082
8083 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8084 clock.m2 = (pll_dw0 & 0xff) << 22;
8085 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8086 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8087 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8088 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8089 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8090
dccbea3b 8091 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8092}
8093
0e8ffe1b 8094static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8095 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8096{
8097 struct drm_device *dev = crtc->base.dev;
8098 struct drm_i915_private *dev_priv = dev->dev_private;
8099 uint32_t tmp;
8100
f458ebbc
DV		 8101 if (!intel_display_power_is_enabled(dev_priv,
8102 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8103 return false;
8104
e143a21c 8105 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8106 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8107
0e8ffe1b
DV		 8108 tmp = I915_READ(PIPECONF(crtc->pipe));
8109 if (!(tmp & PIPECONF_ENABLE))
8110 return false;
8111
42571aef
VS		 8112 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8113 switch (tmp & PIPECONF_BPC_MASK) {
8114 case PIPECONF_6BPC:
8115 pipe_config->pipe_bpp = 18;
8116 break;
8117 case PIPECONF_8BPC:
8118 pipe_config->pipe_bpp = 24;
8119 break;
8120 case PIPECONF_10BPC:
8121 pipe_config->pipe_bpp = 30;
8122 break;
8123 default:
8124 break;
8125 }
8126 }
8127
b5a9fa09
DV		 8128 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8129 pipe_config->limited_color_range = true;
8130
282740f7
VS		 8131 if (INTEL_INFO(dev)->gen < 4)
8132 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8133
1bd1bd80
DV		 8134 intel_get_pipe_timings(crtc, pipe_config);
8135
2fa2fe9a
DV		 8136 i9xx_get_pfit_config(crtc, pipe_config);
8137
6c49f241
DV		 8138 if (INTEL_INFO(dev)->gen >= 4) {
8139 tmp = I915_READ(DPLL_MD(crtc->pipe));
8140 pipe_config->pixel_multiplier =
8141 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8142 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8143 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8144 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8145 tmp = I915_READ(DPLL(crtc->pipe));
8146 pipe_config->pixel_multiplier =
8147 ((tmp & SDVO_MULTIPLIER_MASK)
8148 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8149 } else {
8150 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8151 * port and will be fixed up in the encoder->get_config
8152 * function. */
8153 pipe_config->pixel_multiplier = 1;
8154 }
8bcc2795
DV		 8155 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8156 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8157 /*
8158 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8159 * on 830. Filter it out here so that we don't
8160 * report errors due to that.
8161 */
8162 if (IS_I830(dev))
8163 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8164
8bcc2795
DV		 8165 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8166 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8167 } else {
8168 /* Mask out read-only status bits. */
8169 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8170 DPLL_PORTC_READY_MASK |
8171 DPLL_PORTB_READY_MASK);
8bcc2795 8172 }
6c49f241 8173
70b23a98
VS		 8174 if (IS_CHERRYVIEW(dev))
8175 chv_crtc_clock_get(crtc, pipe_config);
8176 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8177 vlv_crtc_clock_get(crtc, pipe_config);
8178 else
8179 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8180
0f64614d
VS		 8181 /*
8182 * Normally the dotclock is filled in by the encoder .get_config()
8183 * but in case the pipe is enabled w/o any ports we need a sane
8184 * default.
8185 */
8186 pipe_config->base.adjusted_mode.crtc_clock =
8187 pipe_config->port_clock / pipe_config->pixel_multiplier;
8188
0e8ffe1b
DV		 8189 return true;
8190}
8191
dde86e2d 8192static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8193{
8194 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8195 struct intel_encoder *encoder;
74cfd7ac 8196 u32 val, final;
13d83a67 8197 bool has_lvds = false;
199e5d79 8198 bool has_cpu_edp = false;
199e5d79 8199 bool has_panel = false;
99eb6a01
KP		 8200 bool has_ck505 = false;
8201 bool can_ssc = false;
13d83a67
JB		 8202
8203 /* We need to take the global config into account */
b2784e15 8204 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8205 switch (encoder->type) {
8206 case INTEL_OUTPUT_LVDS:
8207 has_panel = true;
8208 has_lvds = true;
8209 break;
8210 case INTEL_OUTPUT_EDP:
8211 has_panel = true;
2de6905f 8212 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8213 has_cpu_edp = true;
8214 break;
6847d71b
PZ		 8215 default:
8216 break;
13d83a67
JB		 8217 }
8218 }
8219
99eb6a01 8220 if (HAS_PCH_IBX(dev)) {
41aa3448 8221 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8222 can_ssc = has_ck505;
8223 } else {
8224 has_ck505 = false;
8225 can_ssc = true;
8226 }
8227
2de6905f
ID		 8228 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8229 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8230
8231 /* Ironlake: try to setup display ref clock before DPLL
8232 * enabling. This is only under driver's control after
8233 * PCH B stepping, previous chipset stepping should be
8234 * ignoring this setting.
8235 */
74cfd7ac
CW		 8236 val = I915_READ(PCH_DREF_CONTROL);
8237
8238 /* As we must carefully and slowly disable/enable each source in turn,
8239 * compute the final state we want first and check if we need to
8240 * make any changes at all.
8241 */
8242 final = val;
8243 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8244 if (has_ck505)
8245 final |= DREF_NONSPREAD_CK505_ENABLE;
8246 else
8247 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8248
8249 final &= ~DREF_SSC_SOURCE_MASK;
8250 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8251 final &= ~DREF_SSC1_ENABLE;
8252
8253 if (has_panel) {
8254 final |= DREF_SSC_SOURCE_ENABLE;
8255
8256 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8257 final |= DREF_SSC1_ENABLE;
8258
8259 if (has_cpu_edp) {
8260 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8261 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8262 else
8263 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8264 } else
8265 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8266 } else {
8267 final |= DREF_SSC_SOURCE_DISABLE;
8268 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8269 }
8270
8271 if (final == val)
8272 return;
8273
13d83a67 8274 /* Always enable nonspread source */
74cfd7ac 8275 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8276
99eb6a01 8277 if (has_ck505)
74cfd7ac 8278 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8279 else
74cfd7ac 8280 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8281
199e5d79 8282 if (has_panel) {
74cfd7ac
CW		 8283 val &= ~DREF_SSC_SOURCE_MASK;
8284 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8285
199e5d79 8286 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8287 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8288 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8289 val |= DREF_SSC1_ENABLE;
e77166b5 8290 } else
74cfd7ac 8291 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8292
8293 /* Get SSC going before enabling the outputs */
74cfd7ac 8294 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8295 POSTING_READ(PCH_DREF_CONTROL);
8296 udelay(200);
8297
74cfd7ac 8298 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8299
8300 /* Enable CPU source on CPU attached eDP */
199e5d79 8301 if (has_cpu_edp) {
99eb6a01 8302 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8303 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8304 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8305 } else
74cfd7ac 8306 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8307 } else
74cfd7ac 8308 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8309
74cfd7ac 8310 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8311 POSTING_READ(PCH_DREF_CONTROL);
8312 udelay(200);
8313 } else {
8314 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8315
74cfd7ac 8316 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8317
8318 /* Turn off CPU output */
74cfd7ac 8319 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8320
74cfd7ac 8321 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8322 POSTING_READ(PCH_DREF_CONTROL);
8323 udelay(200);
8324
8325 /* Turn off the SSC source */
74cfd7ac
CW		 8326 val &= ~DREF_SSC_SOURCE_MASK;
8327 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8328
8329 /* Turn off SSC1 */
74cfd7ac 8330 val &= ~DREF_SSC1_ENABLE;
199e5d79 8331
74cfd7ac 8332 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8333 POSTING_READ(PCH_DREF_CONTROL);
8334 udelay(200);
8335 }
74cfd7ac
CW		 8336
8337 BUG_ON(val != final);
13d83a67
JB		 8338}
8339
f31f2d55 8340static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8341{
f31f2d55 8342 uint32_t tmp;
dde86e2d 8343
0ff066a9
PZ		 8344 tmp = I915_READ(SOUTH_CHICKEN2);
8345 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8346 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8347
0ff066a9
PZ		 8348 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8349 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8350 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8351
0ff066a9
PZ		 8352 tmp = I915_READ(SOUTH_CHICKEN2);
8353 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8354 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8355
0ff066a9
PZ		 8356 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8357 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8358 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8359}
8360
8361/* WaMPhyProgramming:hsw */
8362static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8363{
8364 uint32_t tmp;
dde86e2d
PZ		 8365
8366 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8367 tmp &= ~(0xFF << 24);
8368 tmp |= (0x12 << 24);
8369 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8370
dde86e2d
PZ		 8371 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8372 tmp |= (1 << 11);
8373 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8374
8375 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8376 tmp |= (1 << 11);
8377 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8378
dde86e2d
PZ		 8379 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8380 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8381 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8382
8383 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8384 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8385 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8386
0ff066a9
PZ		 8387 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8388 tmp &= ~(7 << 13);
8389 tmp |= (5 << 13);
8390 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8391
0ff066a9
PZ		 8392 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8393 tmp &= ~(7 << 13);
8394 tmp |= (5 << 13);
8395 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8396
8397 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8398 tmp &= ~0xFF;
8399 tmp |= 0x1C;
8400 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8401
8402 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8403 tmp &= ~0xFF;
8404 tmp |= 0x1C;
8405 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8406
8407 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8408 tmp &= ~(0xFF << 16);
8409 tmp |= (0x1C << 16);
8410 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8411
8412 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8413 tmp &= ~(0xFF << 16);
8414 tmp |= (0x1C << 16);
8415 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8416
0ff066a9
PZ		 8417 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8418 tmp |= (1 << 27);
8419 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8420
0ff066a9
PZ		 8421 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8422 tmp |= (1 << 27);
8423 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8424
0ff066a9
PZ		 8425 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8426 tmp &= ~(0xF << 28);
8427 tmp |= (4 << 28);
8428 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8429
0ff066a9
PZ		 8430 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8431 tmp &= ~(0xF << 28);
8432 tmp |= (4 << 28);
8433 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8434}
8435
2fa86a1f
PZ		 8436/* Implements 3 different sequences from BSpec chapter "Display iCLK
8437 * Programming" based on the parameters passed:
8438 * - Sequence to enable CLKOUT_DP
8439 * - Sequence to enable CLKOUT_DP without spread
8440 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8441 */
8442static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8443 bool with_fdi)
f31f2d55
PZ		 8444{
8445 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8446 uint32_t reg, tmp;
8447
8448 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8449 with_spread = true;
c2699524 8450 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8451 with_fdi = false;
f31f2d55 8452
a580516d 8453 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8454
8455 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8456 tmp &= ~SBI_SSCCTL_DISABLE;
8457 tmp |= SBI_SSCCTL_PATHALT;
8458 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8459
8460 udelay(24);
8461
2fa86a1f
PZ		 8462 if (with_spread) {
8463 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8464 tmp &= ~SBI_SSCCTL_PATHALT;
8465 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8466
2fa86a1f
PZ		 8467 if (with_fdi) {
8468 lpt_reset_fdi_mphy(dev_priv);
8469 lpt_program_fdi_mphy(dev_priv);
8470 }
8471 }
dde86e2d 8472
c2699524 8473 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8474 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8475 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8476 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8477
a580516d 8478 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8479}
8480
47701c3b
PZ		 8481/* Sequence to disable CLKOUT_DP */
8482static void lpt_disable_clkout_dp(struct drm_device *dev)
8483{
8484 struct drm_i915_private *dev_priv = dev->dev_private;
8485 uint32_t reg, tmp;
8486
a580516d 8487 mutex_lock(&dev_priv->sb_lock);
47701c3b 8488
c2699524 8489 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8490 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8491 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8492 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8493
8494 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8495 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8496 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8497 tmp |= SBI_SSCCTL_PATHALT;
8498 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8499 udelay(32);
8500 }
8501 tmp |= SBI_SSCCTL_DISABLE;
8502 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8503 }
8504
a580516d 8505 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8506}
8507
bf8fa3d3
PZ		 8508static void lpt_init_pch_refclk(struct drm_device *dev)
8509{
bf8fa3d3
PZ		 8510 struct intel_encoder *encoder;
8511 bool has_vga = false;
8512
b2784e15 8513 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8514 switch (encoder->type) {
8515 case INTEL_OUTPUT_ANALOG:
8516 has_vga = true;
8517 break;
6847d71b
PZ		 8518 default:
8519 break;
bf8fa3d3
PZ		 8520 }
8521 }
8522
47701c3b
PZ		 8523 if (has_vga)
8524 lpt_enable_clkout_dp(dev, true, true);
8525 else
8526 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8527}
8528
dde86e2d
PZ		 8529/*
8530 * Initialize reference clocks when the driver loads
8531 */
8532void intel_init_pch_refclk(struct drm_device *dev)
8533{
8534 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8535 ironlake_init_pch_refclk(dev);
8536 else if (HAS_PCH_LPT(dev))
8537 lpt_init_pch_refclk(dev);
8538}
8539
55bb9992 8540static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8541{
55bb9992 8542 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8543 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8544 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8545 struct drm_connector *connector;
55bb9992 8546 struct drm_connector_state *connector_state;
d9d444cb 8547 struct intel_encoder *encoder;
55bb9992 8548 int num_connectors = 0, i;
d9d444cb
JB		 8549 bool is_lvds = false;
8550
da3ced29 8551 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8552 if (connector_state->crtc != crtc_state->base.crtc)
8553 continue;
8554
8555 encoder = to_intel_encoder(connector_state->best_encoder);
8556
d9d444cb
JB		 8557 switch (encoder->type) {
8558 case INTEL_OUTPUT_LVDS:
8559 is_lvds = true;
8560 break;
6847d71b
PZ		 8561 default:
8562 break;
d9d444cb
JB		 8563 }
8564 num_connectors++;
8565 }
8566
8567 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8568 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8569 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8570 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8571 }
8572
8573 return 120000;
8574}
8575
6ff93609 8576static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8577{
c8203565 8578 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8580 int pipe = intel_crtc->pipe;
c8203565
PZ		 8581 uint32_t val;
8582
78114071 8583 val = 0;
c8203565 8584
6e3c9717 8585 switch (intel_crtc->config->pipe_bpp) {
c8203565 8586 case 18:
dfd07d72 8587 val |= PIPECONF_6BPC;
c8203565
PZ		 8588 break;
8589 case 24:
dfd07d72 8590 val |= PIPECONF_8BPC;
c8203565
PZ		 8591 break;
8592 case 30:
dfd07d72 8593 val |= PIPECONF_10BPC;
c8203565
PZ		 8594 break;
8595 case 36:
dfd07d72 8596 val |= PIPECONF_12BPC;
c8203565
PZ		 8597 break;
8598 default:
cc769b62
PZ		 8599 /* Case prevented by intel_choose_pipe_bpp_dither. */
8600 BUG();
c8203565
PZ		 8601 }
8602
6e3c9717 8603 if (intel_crtc->config->dither)
c8203565
PZ		 8604 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8605
6e3c9717 8606 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8607 val |= PIPECONF_INTERLACED_ILK;
8608 else
8609 val |= PIPECONF_PROGRESSIVE;
8610
6e3c9717 8611 if (intel_crtc->config->limited_color_range)
3685a8f3 8612 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8613
c8203565
PZ		 8614 I915_WRITE(PIPECONF(pipe), val);
8615 POSTING_READ(PIPECONF(pipe));
8616}
8617
86d3efce
VS		 8618/*
8619 * Set up the pipe CSC unit.
8620 *
8621 * Currently only full range RGB to limited range RGB conversion
8622 * is supported, but eventually this should handle various
8623 * RGB<->YCbCr scenarios as well.
8624 */
50f3b016 8625static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8626{
8627 struct drm_device *dev = crtc->dev;
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8630 int pipe = intel_crtc->pipe;
8631 uint16_t coeff = 0x7800; /* 1.0 */
8632
8633 /*
8634 * TODO: Check what kind of values actually come out of the pipe
8635 * with these coeff/postoff values and adjust to get the best
8636 * accuracy. Perhaps we even need to take the bpc value into
8637 * consideration.
8638 */
8639
6e3c9717 8640 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8641 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8642
8643 /*
8644 * GY/GU and RY/RU should be the other way around according
8645 * to BSpec, but reality doesn't agree. Just set them up in
8646 * a way that results in the correct picture.
8647 */
8648 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8649 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8650
8651 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8652 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8653
8654 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8655 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8656
8657 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8658 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8659 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8660
8661 if (INTEL_INFO(dev)->gen > 6) {
8662 uint16_t postoff = 0;
8663
6e3c9717 8664 if (intel_crtc->config->limited_color_range)
32cf0cb0 8665 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8666
8667 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8668 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8669 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8670
8671 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8672 } else {
8673 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8674
6e3c9717 8675 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8676 mode |= CSC_BLACK_SCREEN_OFFSET;
8677
8678 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8679 }
8680}
8681
6ff93609 8682static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8683{
756f85cf
PZ		 8684 struct drm_device *dev = crtc->dev;
8685 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8687 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8688 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8689 uint32_t val;
8690
3eff4faa 8691 val = 0;
ee2b0b38 8692
6e3c9717 8693 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8694 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8695
6e3c9717 8696 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8697 val |= PIPECONF_INTERLACED_ILK;
8698 else
8699 val |= PIPECONF_PROGRESSIVE;
8700
702e7a56
PZ		 8701 I915_WRITE(PIPECONF(cpu_transcoder), val);
8702 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8703
8704 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8705 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8706
3cdf122c 8707 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8708 val = 0;
8709
6e3c9717 8710 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8711 case 18:
8712 val |= PIPEMISC_DITHER_6_BPC;
8713 break;
8714 case 24:
8715 val |= PIPEMISC_DITHER_8_BPC;
8716 break;
8717 case 30:
8718 val |= PIPEMISC_DITHER_10_BPC;
8719 break;
8720 case 36:
8721 val |= PIPEMISC_DITHER_12_BPC;
8722 break;
8723 default:
8724 /* Case prevented by pipe_config_set_bpp. */
8725 BUG();
8726 }
8727
6e3c9717 8728 if (intel_crtc->config->dither)
756f85cf
PZ		 8729 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8730
8731 I915_WRITE(PIPEMISC(pipe), val);
8732 }
ee2b0b38
PZ		 8733}
8734
6591c6e4 8735static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8736 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8737 intel_clock_t *clock,
8738 bool *has_reduced_clock,
8739 intel_clock_t *reduced_clock)
8740{
8741 struct drm_device *dev = crtc->dev;
8742 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8743 int refclk;
d4906093 8744 const intel_limit_t *limit;
c329a4ec 8745 bool ret;
79e53945 8746
55bb9992 8747 refclk = ironlake_get_refclk(crtc_state);
79e53945 8748
d4906093
ML		 8749 /*
8750 * Returns a set of divisors for the desired target clock with the given
8751 * refclk, or FALSE. The returned values represent the clock equation:
8752 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8753 */
a93e255f
ACO		 8754 limit = intel_limit(crtc_state, refclk);
8755 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8756 crtc_state->port_clock,
ee9300bb 8757 refclk, NULL, clock);
6591c6e4
PZ		 8758 if (!ret)
8759 return false;
cda4b7d3 8760
6591c6e4
PZ		 8761 return true;
8762}
8763
d4b1931c
PZ		 8764int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8765{
8766 /*
8767 * Account for spread spectrum to avoid
8768 * oversubscribing the link. Max center spread
8769 * is 2.5%; use 5% for safety's sake.
8770 */
8771 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8772 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8773}
8774
7429e9d4 8775static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8776{
7429e9d4 8777 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8778}
8779
de13a2e3 8780static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8781 struct intel_crtc_state *crtc_state,
7429e9d4 8782 u32 *fp,
9a7c7890 8783 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8784{
de13a2e3 8785 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8786 struct drm_device *dev = crtc->dev;
8787 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8788 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8789 struct drm_connector *connector;
55bb9992
ACO		 8790 struct drm_connector_state *connector_state;
8791 struct intel_encoder *encoder;
de13a2e3 8792 uint32_t dpll;
55bb9992 8793 int factor, num_connectors = 0, i;
09ede541 8794 bool is_lvds = false, is_sdvo = false;
79e53945 8795
da3ced29 8796 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8797 if (connector_state->crtc != crtc_state->base.crtc)
8798 continue;
8799
8800 encoder = to_intel_encoder(connector_state->best_encoder);
8801
8802 switch (encoder->type) {
79e53945
JB		 8803 case INTEL_OUTPUT_LVDS:
8804 is_lvds = true;
8805 break;
8806 case INTEL_OUTPUT_SDVO:
7d57382e 8807 case INTEL_OUTPUT_HDMI:
79e53945 8808 is_sdvo = true;
79e53945 8809 break;
6847d71b
PZ		 8810 default:
8811 break;
79e53945 8812 }
43565a06 8813
c751ce4f 8814 num_connectors++;
79e53945 8815 }
79e53945 8816
c1858123 8817 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8818 factor = 21;
8819 if (is_lvds) {
8820 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8821 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8822 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8823 factor = 25;
190f68c5 8824 } else if (crtc_state->sdvo_tv_clock)
8febb297 8825 factor = 20;
c1858123 8826
190f68c5 8827 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8828 *fp |= FP_CB_TUNE;
2c07245f 8829
9a7c7890
DV		 8830 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8831 *fp2 |= FP_CB_TUNE;
8832
5eddb70b 8833 dpll = 0;
2c07245f 8834
a07d6787
EA		 8835 if (is_lvds)
8836 dpll |= DPLLB_MODE_LVDS;
8837 else
8838 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8839
190f68c5 8840 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8841 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8842
8843 if (is_sdvo)
4a33e48d 8844 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8845 if (crtc_state->has_dp_encoder)
4a33e48d 8846 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8847
a07d6787 8848 /* compute bitmask from p1 value */
190f68c5 8849 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8850 /* also FPA1 */
190f68c5 8851 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8852
190f68c5 8853 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8854 case 5:
8855 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8856 break;
8857 case 7:
8858 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8859 break;
8860 case 10:
8861 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8862 break;
8863 case 14:
8864 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8865 break;
79e53945
JB		 8866 }
8867
b4c09f3b 8868 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8869 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8870 else
8871 dpll |= PLL_REF_INPUT_DREFCLK;
8872
959e16d6 8873 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8874}
8875
190f68c5
ACO		 8876static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8877 struct intel_crtc_state *crtc_state)
de13a2e3 8878{
c7653199 8879 struct drm_device *dev = crtc->base.dev;
de13a2e3 8880 intel_clock_t clock, reduced_clock;
cbbab5bd 8881 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8882 bool ok, has_reduced_clock = false;
8b47047b 8883 bool is_lvds = false;
e2b78267 8884 struct intel_shared_dpll *pll;
de13a2e3 8885
dd3cd74a
ACO		 8886 memset(&crtc_state->dpll_hw_state, 0,
8887 sizeof(crtc_state->dpll_hw_state));
8888
409ee761 8889 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8890
5dc5298b
PZ		 8891 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8892 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8893
190f68c5 8894 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8895 &has_reduced_clock, &reduced_clock);
190f68c5 8896 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8897 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8898 return -EINVAL;
79e53945 8899 }
f47709a9 8900 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8901 if (!crtc_state->clock_set) {
8902 crtc_state->dpll.n = clock.n;
8903 crtc_state->dpll.m1 = clock.m1;
8904 crtc_state->dpll.m2 = clock.m2;
8905 crtc_state->dpll.p1 = clock.p1;
8906 crtc_state->dpll.p2 = clock.p2;
f47709a9 8907 }
79e53945 8908
5dc5298b 8909 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8910 if (crtc_state->has_pch_encoder) {
8911 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8912 if (has_reduced_clock)
7429e9d4 8913 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8914
190f68c5 8915 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8916 &fp, &reduced_clock,
8917 has_reduced_clock ? &fp2 : NULL);
8918
190f68c5
ACO		 8919 crtc_state->dpll_hw_state.dpll = dpll;
8920 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8921 if (has_reduced_clock)
190f68c5 8922 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8923 else
190f68c5 8924 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8925
190f68c5 8926 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8927 if (pll == NULL) {
84f44ce7 8928 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8929 pipe_name(crtc->pipe));
4b645f14
JB		 8930 return -EINVAL;
8931 }
3fb37703 8932 }
79e53945 8933
ab585dea 8934 if (is_lvds && has_reduced_clock)
c7653199 8935 crtc->lowfreq_avail = true;
bcd644e0 8936 else
c7653199 8937 crtc->lowfreq_avail = false;
e2b78267 8938
c8f7a0db 8939 return 0;
79e53945
JB		 8940}
8941
eb14cb74
VS		 8942static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8943 struct intel_link_m_n *m_n)
8944{
8945 struct drm_device *dev = crtc->base.dev;
8946 struct drm_i915_private *dev_priv = dev->dev_private;
8947 enum pipe pipe = crtc->pipe;
8948
8949 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8950 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8951 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8952 & ~TU_SIZE_MASK;
8953 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8954 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8955 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8956}
8957
8958static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8959 enum transcoder transcoder,
b95af8be
VK		 8960 struct intel_link_m_n *m_n,
8961 struct intel_link_m_n *m2_n2)
72419203
DV		 8962{
8963 struct drm_device *dev = crtc->base.dev;
8964 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8965 enum pipe pipe = crtc->pipe;
72419203 8966
eb14cb74
VS		 8967 if (INTEL_INFO(dev)->gen >= 5) {
8968 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8969 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8970 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8971 & ~TU_SIZE_MASK;
8972 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8973 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8974 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8975 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8976 * gen < 8) and if DRRS is supported (to make sure the
8977 * registers are not unnecessarily read).
8978 */
8979 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8980 crtc->config->has_drrs) {
b95af8be
VK		 8981 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8982 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8983 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8984 & ~TU_SIZE_MASK;
8985 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8986 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8987 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8988 }
eb14cb74
VS		 8989 } else {
8990 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8991 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8992 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8993 & ~TU_SIZE_MASK;
8994 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8995 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8996 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8997 }
8998}
8999
9000void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9001 struct intel_crtc_state *pipe_config)
eb14cb74 9002{
681a8504 9003 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9004 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9005 else
9006 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9007 &pipe_config->dp_m_n,
9008 &pipe_config->dp_m2_n2);
eb14cb74 9009}
72419203 9010
eb14cb74 9011static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9012 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9013{
9014 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9015 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9016}
9017
bd2e244f 9018static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9019 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9020{
9021 struct drm_device *dev = crtc->base.dev;
9022 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9023 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9024 uint32_t ps_ctrl = 0;
9025 int id = -1;
9026 int i;
bd2e244f 9027
a1b2278e
CK		 9028 /* find scaler attached to this pipe */
9029 for (i = 0; i < crtc->num_scalers; i++) {
9030 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9031 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9032 id = i;
9033 pipe_config->pch_pfit.enabled = true;
9034 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9035 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9036 break;
9037 }
9038 }
bd2e244f 9039
a1b2278e
CK		 9040 scaler_state->scaler_id = id;
9041 if (id >= 0) {
9042 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9043 } else {
9044 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9045 }
9046}
9047
5724dbd1
DL		 9048static void
9049skylake_get_initial_plane_config(struct intel_crtc *crtc,
9050 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9051{
9052 struct drm_device *dev = crtc->base.dev;
9053 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9054 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9055 int pipe = crtc->pipe;
9056 int fourcc, pixel_format;
6761dd31 9057 unsigned int aligned_height;
bc8d7dff 9058 struct drm_framebuffer *fb;
1b842c89 9059 struct intel_framebuffer *intel_fb;
bc8d7dff 9060
d9806c9f 9061 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9062 if (!intel_fb) {
bc8d7dff
DL		 9063 DRM_DEBUG_KMS("failed to alloc fb\n");
9064 return;
9065 }
9066
1b842c89
DL		 9067 fb = &intel_fb->base;
9068
bc8d7dff 9069 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9070 if (!(val & PLANE_CTL_ENABLE))
9071 goto error;
9072
bc8d7dff
DL		 9073 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9074 fourcc = skl_format_to_fourcc(pixel_format,
9075 val & PLANE_CTL_ORDER_RGBX,
9076 val & PLANE_CTL_ALPHA_MASK);
9077 fb->pixel_format = fourcc;
9078 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9079
40f46283
DL		 9080 tiling = val & PLANE_CTL_TILED_MASK;
9081 switch (tiling) {
9082 case PLANE_CTL_TILED_LINEAR:
9083 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9084 break;
9085 case PLANE_CTL_TILED_X:
9086 plane_config->tiling = I915_TILING_X;
9087 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9088 break;
9089 case PLANE_CTL_TILED_Y:
9090 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9091 break;
9092 case PLANE_CTL_TILED_YF:
9093 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9094 break;
9095 default:
9096 MISSING_CASE(tiling);
9097 goto error;
9098 }
9099
bc8d7dff
DL		 9100 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9101 plane_config->base = base;
9102
9103 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9104
9105 val = I915_READ(PLANE_SIZE(pipe, 0));
9106 fb->height = ((val >> 16) & 0xfff) + 1;
9107 fb->width = ((val >> 0) & 0x1fff) + 1;
9108
9109 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9110 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9111 fb->pixel_format);
bc8d7dff
DL		 9112 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9113
9114 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9115 fb->pixel_format,
9116 fb->modifier[0]);
bc8d7dff 9117
f37b5c2b 9118 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9119
9120 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9121 pipe_name(pipe), fb->width, fb->height,
9122 fb->bits_per_pixel, base, fb->pitches[0],
9123 plane_config->size);
9124
2d14030b 9125 plane_config->fb = intel_fb;
bc8d7dff
DL		 9126 return;
9127
9128error:
9129 kfree(fb);
9130}
9131
2fa2fe9a 9132static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9133 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9134{
9135 struct drm_device *dev = crtc->base.dev;
9136 struct drm_i915_private *dev_priv = dev->dev_private;
9137 uint32_t tmp;
9138
9139 tmp = I915_READ(PF_CTL(crtc->pipe));
9140
9141 if (tmp & PF_ENABLE) {
fd4daa9c 9142 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9143 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9144 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9145
9146 /* We currently do not free assignements of panel fitters on
9147 * ivb/hsw (since we don't use the higher upscaling modes which
9148 * differentiates them) so just WARN about this case for now. */
9149 if (IS_GEN7(dev)) {
9150 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9151 PF_PIPE_SEL_IVB(crtc->pipe));
9152 }
2fa2fe9a 9153 }
79e53945
JB		 9154}
9155
5724dbd1
DL		 9156static void
9157ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9158 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9159{
9160 struct drm_device *dev = crtc->base.dev;
9161 struct drm_i915_private *dev_priv = dev->dev_private;
9162 u32 val, base, offset;
aeee5a49 9163 int pipe = crtc->pipe;
4c6baa59 9164 int fourcc, pixel_format;
6761dd31 9165 unsigned int aligned_height;
b113d5ee 9166 struct drm_framebuffer *fb;
1b842c89 9167 struct intel_framebuffer *intel_fb;
4c6baa59 9168
42a7b088
DL		 9169 val = I915_READ(DSPCNTR(pipe));
9170 if (!(val & DISPLAY_PLANE_ENABLE))
9171 return;
9172
d9806c9f 9173 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9174 if (!intel_fb) {
4c6baa59
JB		 9175 DRM_DEBUG_KMS("failed to alloc fb\n");
9176 return;
9177 }
9178
1b842c89
DL		 9179 fb = &intel_fb->base;
9180
18c5247e
DV		 9181 if (INTEL_INFO(dev)->gen >= 4) {
9182 if (val & DISPPLANE_TILED) {
49af449b 9183 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9184 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9185 }
9186 }
4c6baa59
JB		 9187
9188 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9189 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9190 fb->pixel_format = fourcc;
9191 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9192
aeee5a49 9193 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9194 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9195 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9196 } else {
49af449b 9197 if (plane_config->tiling)
aeee5a49 9198 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9199 else
aeee5a49 9200 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9201 }
9202 plane_config->base = base;
9203
9204 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9205 fb->width = ((val >> 16) & 0xfff) + 1;
9206 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9207
9208 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9209 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9210
b113d5ee 9211 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9212 fb->pixel_format,
9213 fb->modifier[0]);
4c6baa59 9214
f37b5c2b 9215 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9216
2844a921
DL		 9217 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9218 pipe_name(pipe), fb->width, fb->height,
9219 fb->bits_per_pixel, base, fb->pitches[0],
9220 plane_config->size);
b113d5ee 9221
2d14030b 9222 plane_config->fb = intel_fb;
4c6baa59
JB		 9223}
9224
0e8ffe1b 9225static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9226 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9227{
9228 struct drm_device *dev = crtc->base.dev;
9229 struct drm_i915_private *dev_priv = dev->dev_private;
9230 uint32_t tmp;
9231
f458ebbc
DV		 9232 if (!intel_display_power_is_enabled(dev_priv,
9233 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9234 return false;
9235
e143a21c 9236 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9237 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9238
0e8ffe1b
DV		 9239 tmp = I915_READ(PIPECONF(crtc->pipe));
9240 if (!(tmp & PIPECONF_ENABLE))
9241 return false;
9242
42571aef
VS		 9243 switch (tmp & PIPECONF_BPC_MASK) {
9244 case PIPECONF_6BPC:
9245 pipe_config->pipe_bpp = 18;
9246 break;
9247 case PIPECONF_8BPC:
9248 pipe_config->pipe_bpp = 24;
9249 break;
9250 case PIPECONF_10BPC:
9251 pipe_config->pipe_bpp = 30;
9252 break;
9253 case PIPECONF_12BPC:
9254 pipe_config->pipe_bpp = 36;
9255 break;
9256 default:
9257 break;
9258 }
9259
b5a9fa09
DV		 9260 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9261 pipe_config->limited_color_range = true;
9262
ab9412ba 9263 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9264 struct intel_shared_dpll *pll;
9265
88adfff1
DV		 9266 pipe_config->has_pch_encoder = true;
9267
627eb5a3
DV		 9268 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9269 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9270 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9271
9272 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9273
c0d43d62 9274 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9275 pipe_config->shared_dpll =
9276 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9277 } else {
9278 tmp = I915_READ(PCH_DPLL_SEL);
9279 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9280 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9281 else
9282 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9283 }
66e985c0
DV		 9284
9285 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9286
9287 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9288 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9289
9290 tmp = pipe_config->dpll_hw_state.dpll;
9291 pipe_config->pixel_multiplier =
9292 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9293 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9294
9295 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9296 } else {
9297 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9298 }
9299
1bd1bd80
DV		 9300 intel_get_pipe_timings(crtc, pipe_config);
9301
2fa2fe9a
DV		 9302 ironlake_get_pfit_config(crtc, pipe_config);
9303
0e8ffe1b
DV		 9304 return true;
9305}
9306
be256dc7
PZ		 9307static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9308{
9309 struct drm_device *dev = dev_priv->dev;
be256dc7 9310 struct intel_crtc *crtc;
be256dc7 9311
d3fcc808 9312 for_each_intel_crtc(dev, crtc)
e2c719b7 9313 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9314 pipe_name(crtc->pipe));
9315
e2c719b7
RC		 9316 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9317 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS		 9318 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9319 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
e2c719b7
RC		 9320 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9321 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9322 "CPU PWM1 enabled\n");
c5107b87 9323 if (IS_HASWELL(dev))
e2c719b7 9324 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9325 "CPU PWM2 enabled\n");
e2c719b7 9326 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9327 "PCH PWM1 enabled\n");
e2c719b7 9328 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9329 "Utility pin enabled\n");
e2c719b7 9330 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9331
9926ada1
PZ		 9332 /*
9333 * In theory we can still leave IRQs enabled, as long as only the HPD
9334 * interrupts remain enabled. We used to check for that, but since it's
9335 * gen-specific and since we only disable LCPLL after we fully disable
9336 * the interrupts, the check below should be enough.
9337 */
e2c719b7 9338 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9339}
9340
9ccd5aeb
PZ		 9341static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9342{
9343 struct drm_device *dev = dev_priv->dev;
9344
9345 if (IS_HASWELL(dev))
9346 return I915_READ(D_COMP_HSW);
9347 else
9348 return I915_READ(D_COMP_BDW);
9349}
9350
3c4c9b81
PZ		 9351static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9352{
9353 struct drm_device *dev = dev_priv->dev;
9354
9355 if (IS_HASWELL(dev)) {
9356 mutex_lock(&dev_priv->rps.hw_lock);
9357 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9358 val))
f475dadf 9359 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9360 mutex_unlock(&dev_priv->rps.hw_lock);
9361 } else {
9ccd5aeb
PZ		 9362 I915_WRITE(D_COMP_BDW, val);
9363 POSTING_READ(D_COMP_BDW);
3c4c9b81 9364 }
be256dc7
PZ		 9365}
9366
9367/*
9368 * This function implements pieces of two sequences from BSpec:
9369 * - Sequence for display software to disable LCPLL
9370 * - Sequence for display software to allow package C8+
9371 * The steps implemented here are just the steps that actually touch the LCPLL
9372 * register. Callers should take care of disabling all the display engine
9373 * functions, doing the mode unset, fixing interrupts, etc.
9374 */
6ff58d53
PZ		 9375static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9376 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9377{
9378 uint32_t val;
9379
9380 assert_can_disable_lcpll(dev_priv);
9381
9382 val = I915_READ(LCPLL_CTL);
9383
9384 if (switch_to_fclk) {
9385 val |= LCPLL_CD_SOURCE_FCLK;
9386 I915_WRITE(LCPLL_CTL, val);
9387
9388 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9389 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9390 DRM_ERROR("Switching to FCLK failed\n");
9391
9392 val = I915_READ(LCPLL_CTL);
9393 }
9394
9395 val |= LCPLL_PLL_DISABLE;
9396 I915_WRITE(LCPLL_CTL, val);
9397 POSTING_READ(LCPLL_CTL);
9398
9399 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9400 DRM_ERROR("LCPLL still locked\n");
9401
9ccd5aeb 9402 val = hsw_read_dcomp(dev_priv);
be256dc7 9403 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9404 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9405 ndelay(100);
9406
9ccd5aeb
PZ		 9407 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9408 1))
be256dc7
PZ		 9409 DRM_ERROR("D_COMP RCOMP still in progress\n");
9410
9411 if (allow_power_down) {
9412 val = I915_READ(LCPLL_CTL);
9413 val |= LCPLL_POWER_DOWN_ALLOW;
9414 I915_WRITE(LCPLL_CTL, val);
9415 POSTING_READ(LCPLL_CTL);
9416 }
9417}
9418
9419/*
9420 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9421 * source.
9422 */
6ff58d53 9423static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9424{
9425 uint32_t val;
9426
9427 val = I915_READ(LCPLL_CTL);
9428
9429 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9430 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9431 return;
9432
a8a8bd54
PZ		 9433 /*
9434 * Make sure we're not on PC8 state before disabling PC8, otherwise
9435 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9436 */
59bad947 9437 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9438
be256dc7
PZ		 9439 if (val & LCPLL_POWER_DOWN_ALLOW) {
9440 val &= ~LCPLL_POWER_DOWN_ALLOW;
9441 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9442 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9443 }
9444
9ccd5aeb 9445 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9446 val |= D_COMP_COMP_FORCE;
9447 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9448 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9449
9450 val = I915_READ(LCPLL_CTL);
9451 val &= ~LCPLL_PLL_DISABLE;
9452 I915_WRITE(LCPLL_CTL, val);
9453
9454 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9455 DRM_ERROR("LCPLL not locked yet\n");
9456
9457 if (val & LCPLL_CD_SOURCE_FCLK) {
9458 val = I915_READ(LCPLL_CTL);
9459 val &= ~LCPLL_CD_SOURCE_FCLK;
9460 I915_WRITE(LCPLL_CTL, val);
9461
9462 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9463 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9464 DRM_ERROR("Switching back to LCPLL failed\n");
9465 }
215733fa 9466
59bad947 9467 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9468 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9469}
9470
765dab67
PZ		 9471/*
9472 * Package states C8 and deeper are really deep PC states that can only be
9473 * reached when all the devices on the system allow it, so even if the graphics
9474 * device allows PC8+, it doesn't mean the system will actually get to these
9475 * states. Our driver only allows PC8+ when going into runtime PM.
9476 *
9477 * The requirements for PC8+ are that all the outputs are disabled, the power
9478 * well is disabled and most interrupts are disabled, and these are also
9479 * requirements for runtime PM. When these conditions are met, we manually do
9480 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9481 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9482 * hang the machine.
9483 *
9484 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9485 * the state of some registers, so when we come back from PC8+ we need to
9486 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9487 * need to take care of the registers kept by RC6. Notice that this happens even
9488 * if we don't put the device in PCI D3 state (which is what currently happens
9489 * because of the runtime PM support).
9490 *
9491 * For more, read "Display Sequences for Package C8" on the hardware
9492 * documentation.
9493 */
a14cb6fc 9494void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9495{
c67a470b
PZ		 9496 struct drm_device *dev = dev_priv->dev;
9497 uint32_t val;
9498
c67a470b
PZ		 9499 DRM_DEBUG_KMS("Enabling package C8+\n");
9500
c2699524 9501 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9502 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9503 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9504 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9505 }
9506
9507 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9508 hsw_disable_lcpll(dev_priv, true, true);
9509}
9510
a14cb6fc 9511void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9512{
9513 struct drm_device *dev = dev_priv->dev;
9514 uint32_t val;
9515
c67a470b
PZ		 9516 DRM_DEBUG_KMS("Disabling package C8+\n");
9517
9518 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9519 lpt_init_pch_refclk(dev);
9520
c2699524 9521 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9522 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9523 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9524 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9525 }
9526
9527 intel_prepare_ddi(dev);
c67a470b
PZ		 9528}
9529
27c329ed 9530static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9531{
a821fc46 9532 struct drm_device *dev = old_state->dev;
27c329ed 9533 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9534
27c329ed 9535 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9536}
9537
b432e5cf 9538/* compute the max rate for new configuration */
27c329ed 9539static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9540{
b432e5cf 9541 struct intel_crtc *intel_crtc;
27c329ed 9542 struct intel_crtc_state *crtc_state;
b432e5cf 9543 int max_pixel_rate = 0;
b432e5cf 9544
27c329ed
ML		 9545 for_each_intel_crtc(state->dev, intel_crtc) {
9546 int pixel_rate;
9547
9548 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9549 if (IS_ERR(crtc_state))
9550 return PTR_ERR(crtc_state);
9551
9552 if (!crtc_state->base.enable)
b432e5cf
VS		 9553 continue;
9554
27c329ed 9555 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9556
9557 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9558 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9559 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9560
9561 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9562 }
9563
9564 return max_pixel_rate;
9565}
9566
9567static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9568{
9569 struct drm_i915_private *dev_priv = dev->dev_private;
9570 uint32_t val, data;
9571 int ret;
9572
9573 if (WARN((I915_READ(LCPLL_CTL) &
9574 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9575 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9576 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9577 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9578 "trying to change cdclk frequency with cdclk not enabled\n"))
9579 return;
9580
9581 mutex_lock(&dev_priv->rps.hw_lock);
9582 ret = sandybridge_pcode_write(dev_priv,
9583 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9584 mutex_unlock(&dev_priv->rps.hw_lock);
9585 if (ret) {
9586 DRM_ERROR("failed to inform pcode about cdclk change\n");
9587 return;
9588 }
9589
9590 val = I915_READ(LCPLL_CTL);
9591 val |= LCPLL_CD_SOURCE_FCLK;
9592 I915_WRITE(LCPLL_CTL, val);
9593
9594 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9595 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9596 DRM_ERROR("Switching to FCLK failed\n");
9597
9598 val = I915_READ(LCPLL_CTL);
9599 val &= ~LCPLL_CLK_FREQ_MASK;
9600
9601 switch (cdclk) {
9602 case 450000:
9603 val |= LCPLL_CLK_FREQ_450;
9604 data = 0;
9605 break;
9606 case 540000:
9607 val |= LCPLL_CLK_FREQ_54O_BDW;
9608 data = 1;
9609 break;
9610 case 337500:
9611 val |= LCPLL_CLK_FREQ_337_5_BDW;
9612 data = 2;
9613 break;
9614 case 675000:
9615 val |= LCPLL_CLK_FREQ_675_BDW;
9616 data = 3;
9617 break;
9618 default:
9619 WARN(1, "invalid cdclk frequency\n");
9620 return;
9621 }
9622
9623 I915_WRITE(LCPLL_CTL, val);
9624
9625 val = I915_READ(LCPLL_CTL);
9626 val &= ~LCPLL_CD_SOURCE_FCLK;
9627 I915_WRITE(LCPLL_CTL, val);
9628
9629 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9630 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9631 DRM_ERROR("Switching back to LCPLL failed\n");
9632
9633 mutex_lock(&dev_priv->rps.hw_lock);
9634 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9635 mutex_unlock(&dev_priv->rps.hw_lock);
9636
9637 intel_update_cdclk(dev);
9638
9639 WARN(cdclk != dev_priv->cdclk_freq,
9640 "cdclk requested %d kHz but got %d kHz\n",
9641 cdclk, dev_priv->cdclk_freq);
9642}
9643
27c329ed 9644static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9645{
27c329ed
ML		 9646 struct drm_i915_private *dev_priv = to_i915(state->dev);
9647 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9648 int cdclk;
9649
9650 /*
9651 * FIXME should also account for plane ratio
9652 * once 64bpp pixel formats are supported.
9653 */
27c329ed 9654 if (max_pixclk > 540000)
b432e5cf 9655 cdclk = 675000;
27c329ed 9656 else if (max_pixclk > 450000)
b432e5cf 9657 cdclk = 540000;
27c329ed 9658 else if (max_pixclk > 337500)
b432e5cf
VS		 9659 cdclk = 450000;
9660 else
9661 cdclk = 337500;
9662
9663 /*
9664 * FIXME move the cdclk caclulation to
9665 * compute_config() so we can fail gracegully.
9666 */
9667 if (cdclk > dev_priv->max_cdclk_freq) {
9668 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9669 cdclk, dev_priv->max_cdclk_freq);
9670 cdclk = dev_priv->max_cdclk_freq;
9671 }
9672
27c329ed 9673 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9674
9675 return 0;
9676}
9677
27c329ed 9678static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9679{
27c329ed
ML		 9680 struct drm_device *dev = old_state->dev;
9681 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9682
27c329ed 9683 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9684}
9685
190f68c5
ACO		 9686static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9687 struct intel_crtc_state *crtc_state)
09b4ddf9 9688{
190f68c5 9689 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9690 return -EINVAL;
716c2e55 9691
c7653199 9692 crtc->lowfreq_avail = false;
644cef34 9693
c8f7a0db 9694 return 0;
79e53945
JB		 9695}
9696
3760b59c
S		 9697static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9698 enum port port,
9699 struct intel_crtc_state *pipe_config)
9700{
9701 switch (port) {
9702 case PORT_A:
9703 pipe_config->ddi_pll_sel = SKL_DPLL0;
9704 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9705 break;
9706 case PORT_B:
9707 pipe_config->ddi_pll_sel = SKL_DPLL1;
9708 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9709 break;
9710 case PORT_C:
9711 pipe_config->ddi_pll_sel = SKL_DPLL2;
9712 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9713 break;
9714 default:
9715 DRM_ERROR("Incorrect port type\n");
9716 }
9717}
9718
96b7dfb7
S		 9719static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9720 enum port port,
5cec258b 9721 struct intel_crtc_state *pipe_config)
96b7dfb7 9722{
3148ade7 9723 u32 temp, dpll_ctl1;
96b7dfb7
S		 9724
9725 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9726 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9727
9728 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9729 case SKL_DPLL0:
9730 /*
9731 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9732 * of the shared DPLL framework and thus needs to be read out
9733 * separately
9734 */
9735 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9736 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9737 break;
96b7dfb7
S		 9738 case SKL_DPLL1:
9739 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9740 break;
9741 case SKL_DPLL2:
9742 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9743 break;
9744 case SKL_DPLL3:
9745 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9746 break;
96b7dfb7
S		 9747 }
9748}
9749
7d2c8175
DL		 9750static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9751 enum port port,
5cec258b 9752 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9753{
9754 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9755
9756 switch (pipe_config->ddi_pll_sel) {
9757 case PORT_CLK_SEL_WRPLL1:
9758 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9759 break;
9760 case PORT_CLK_SEL_WRPLL2:
9761 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9762 break;
9763 }
9764}
9765
26804afd 9766static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9767 struct intel_crtc_state *pipe_config)
26804afd
DV		 9768{
9769 struct drm_device *dev = crtc->base.dev;
9770 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9771 struct intel_shared_dpll *pll;
26804afd
DV		 9772 enum port port;
9773 uint32_t tmp;
9774
9775 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9776
9777 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9778
ef11bdb3 9779 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
96b7dfb7 9780 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9781 else if (IS_BROXTON(dev))
9782 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9783 else
9784 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9785
d452c5b6
DV		 9786 if (pipe_config->shared_dpll >= 0) {
9787 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9788
9789 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9790 &pipe_config->dpll_hw_state));
9791 }
9792
26804afd
DV		 9793 /*
9794 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9795 * DDI E. So just check whether this pipe is wired to DDI E and whether
9796 * the PCH transcoder is on.
9797 */
ca370455
DL		 9798 if (INTEL_INFO(dev)->gen < 9 &&
9799 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9800 pipe_config->has_pch_encoder = true;
9801
9802 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9803 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9804 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9805
9806 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9807 }
9808}
9809
0e8ffe1b 9810static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9811 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9812{
9813 struct drm_device *dev = crtc->base.dev;
9814 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9815 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9816 uint32_t tmp;
9817
f458ebbc 9818 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9819 POWER_DOMAIN_PIPE(crtc->pipe)))
9820 return false;
9821
e143a21c 9822 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9823 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9824
eccb140b
DV		 9825 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9826 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9827 enum pipe trans_edp_pipe;
9828 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9829 default:
9830 WARN(1, "unknown pipe linked to edp transcoder\n");
9831 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9832 case TRANS_DDI_EDP_INPUT_A_ON:
9833 trans_edp_pipe = PIPE_A;
9834 break;
9835 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9836 trans_edp_pipe = PIPE_B;
9837 break;
9838 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9839 trans_edp_pipe = PIPE_C;
9840 break;
9841 }
9842
9843 if (trans_edp_pipe == crtc->pipe)
9844 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9845 }
9846
f458ebbc 9847 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9848 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9849 return false;
9850
eccb140b 9851 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9852 if (!(tmp & PIPECONF_ENABLE))
9853 return false;
9854
26804afd 9855 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9856
1bd1bd80
DV		 9857 intel_get_pipe_timings(crtc, pipe_config);
9858
a1b2278e
CK		 9859 if (INTEL_INFO(dev)->gen >= 9) {
9860 skl_init_scalers(dev, crtc, pipe_config);
9861 }
9862
2fa2fe9a 9863 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9864
9865 if (INTEL_INFO(dev)->gen >= 9) {
9866 pipe_config->scaler_state.scaler_id = -1;
9867 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9868 }
9869
bd2e244f 9870 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9871 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9872 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9873 else
1c132b44 9874 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9875 }
88adfff1 9876
e59150dc
JB		 9877 if (IS_HASWELL(dev))
9878 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9879 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9880
ebb69c95
CT		 9881 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9882 pipe_config->pixel_multiplier =
9883 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9884 } else {
9885 pipe_config->pixel_multiplier = 1;
9886 }
6c49f241 9887
0e8ffe1b
DV		 9888 return true;
9889}
9890
560b85bb
CW		 9891static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9892{
9893 struct drm_device *dev = crtc->dev;
9894 struct drm_i915_private *dev_priv = dev->dev_private;
9895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9896 uint32_t cntl = 0, size = 0;
560b85bb 9897
dc41c154 9898 if (base) {
3dd512fb
MR		 9899 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9900 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9901 unsigned int stride = roundup_pow_of_two(width) * 4;
9902
9903 switch (stride) {
9904 default:
9905 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9906 width, stride);
9907 stride = 256;
9908 /* fallthrough */
9909 case 256:
9910 case 512:
9911 case 1024:
9912 case 2048:
9913 break;
4b0e333e
CW		 9914 }
9915
dc41c154
VS		 9916 cntl |= CURSOR_ENABLE |
9917 CURSOR_GAMMA_ENABLE |
9918 CURSOR_FORMAT_ARGB |
9919 CURSOR_STRIDE(stride);
9920
9921 size = (height << 12) | width;
4b0e333e 9922 }
560b85bb 9923
dc41c154
VS		 9924 if (intel_crtc->cursor_cntl != 0 &&
9925 (intel_crtc->cursor_base != base ||
9926 intel_crtc->cursor_size != size ||
9927 intel_crtc->cursor_cntl != cntl)) {
9928 /* On these chipsets we can only modify the base/size/stride
9929 * whilst the cursor is disabled.
9930 */
0b87c24e
VS		 9931 I915_WRITE(CURCNTR(PIPE_A), 0);
9932 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 9933 intel_crtc->cursor_cntl = 0;
4b0e333e 9934 }
560b85bb 9935
99d1f387 9936 if (intel_crtc->cursor_base != base) {
0b87c24e 9937 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 9938 intel_crtc->cursor_base = base;
9939 }
4726e0b0 9940
dc41c154
VS		 9941 if (intel_crtc->cursor_size != size) {
9942 I915_WRITE(CURSIZE, size);
9943 intel_crtc->cursor_size = size;
4b0e333e 9944 }
560b85bb 9945
4b0e333e 9946 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 9947 I915_WRITE(CURCNTR(PIPE_A), cntl);
9948 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 9949 intel_crtc->cursor_cntl = cntl;
560b85bb 9950 }
560b85bb
CW		 9951}
9952
560b85bb 9953static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9954{
9955 struct drm_device *dev = crtc->dev;
9956 struct drm_i915_private *dev_priv = dev->dev_private;
9957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9958 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9959 uint32_t cntl;
9960
9961 cntl = 0;
9962 if (base) {
9963 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9964 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9965 case 64:
9966 cntl |= CURSOR_MODE_64_ARGB_AX;
9967 break;
9968 case 128:
9969 cntl |= CURSOR_MODE_128_ARGB_AX;
9970 break;
9971 case 256:
9972 cntl |= CURSOR_MODE_256_ARGB_AX;
9973 break;
9974 default:
3dd512fb 9975 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9976 return;
65a21cd6 9977 }
4b0e333e 9978 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7 9979
fc6f93bc 9980 if (HAS_DDI(dev))
47bf17a7 9981 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9982 }
65a21cd6 9983
8e7d688b 9984 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9985 cntl |= CURSOR_ROTATE_180;
9986
4b0e333e
CW		 9987 if (intel_crtc->cursor_cntl != cntl) {
9988 I915_WRITE(CURCNTR(pipe), cntl);
9989 POSTING_READ(CURCNTR(pipe));
9990 intel_crtc->cursor_cntl = cntl;
65a21cd6 9991 }
4b0e333e 9992
65a21cd6 9993 /* and commit changes on next vblank */
5efb3e28
VS		 9994 I915_WRITE(CURBASE(pipe), base);
9995 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9996
9997 intel_crtc->cursor_base = base;
65a21cd6
JB		 9998}
9999
cda4b7d3 10000/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10001static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10002 bool on)
cda4b7d3
CW		 10003{
10004 struct drm_device *dev = crtc->dev;
10005 struct drm_i915_private *dev_priv = dev->dev_private;
10006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10007 int pipe = intel_crtc->pipe;
9b4101be
ML		 10008 struct drm_plane_state *cursor_state = crtc->cursor->state;
10009 int x = cursor_state->crtc_x;
10010 int y = cursor_state->crtc_y;
d6e4db15 10011 u32 base = 0, pos = 0;
cda4b7d3 10012
d6e4db15 10013 if (on)
cda4b7d3 10014 base = intel_crtc->cursor_addr;
cda4b7d3 10015
6e3c9717 10016 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10017 base = 0;
10018
6e3c9717 10019 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10020 base = 0;
10021
10022 if (x < 0) {
9b4101be 10023 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 10024 base = 0;
10025
10026 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10027 x = -x;
10028 }
10029 pos |= x << CURSOR_X_SHIFT;
10030
10031 if (y < 0) {
9b4101be 10032 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 10033 base = 0;
10034
10035 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10036 y = -y;
10037 }
10038 pos |= y << CURSOR_Y_SHIFT;
10039
4b0e333e 10040 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10041 return;
10042
5efb3e28
VS		 10043 I915_WRITE(CURPOS(pipe), pos);
10044
4398ad45
VS		 10045 /* ILK+ do this automagically */
10046 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10047 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 10048 base += (cursor_state->crtc_h *
10049 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 10050 }
10051
8ac54669 10052 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10053 i845_update_cursor(crtc, base);
10054 else
10055 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10056}
10057
dc41c154
VS		 10058static bool cursor_size_ok(struct drm_device *dev,
10059 uint32_t width, uint32_t height)
10060{
10061 if (width == 0 || height == 0)
10062 return false;
10063
10064 /*
10065 * 845g/865g are special in that they are only limited by
10066 * the width of their cursors, the height is arbitrary up to
10067 * the precision of the register. Everything else requires
10068 * square cursors, limited to a few power-of-two sizes.
10069 */
10070 if (IS_845G(dev) || IS_I865G(dev)) {
10071 if ((width & 63) != 0)
10072 return false;
10073
10074 if (width > (IS_845G(dev) ? 64 : 512))
10075 return false;
10076
10077 if (height > 1023)
10078 return false;
10079 } else {
10080 switch (width | height) {
10081 case 256:
10082 case 128:
10083 if (IS_GEN2(dev))
10084 return false;
10085 case 64:
10086 break;
10087 default:
10088 return false;
10089 }
10090 }
10091
10092 return true;
10093}
10094
79e53945 10095static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10096 u16 *blue, uint32_t start, uint32_t size)
79e53945 10097{
7203425a 10098 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10100
7203425a 10101 for (i = start; i < end; i++) {
79e53945
JB		 10102 intel_crtc->lut_r[i] = red[i] >> 8;
10103 intel_crtc->lut_g[i] = green[i] >> 8;
10104 intel_crtc->lut_b[i] = blue[i] >> 8;
10105 }
10106
10107 intel_crtc_load_lut(crtc);
10108}
10109
79e53945
JB		 10110/* VESA 640x480x72Hz mode to set on the pipe */
10111static struct drm_display_mode load_detect_mode = {
10112 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10113 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10114};
10115
a8bb6818
DV		 10116struct drm_framebuffer *
10117__intel_framebuffer_create(struct drm_device *dev,
10118 struct drm_mode_fb_cmd2 *mode_cmd,
10119 struct drm_i915_gem_object *obj)
d2dff872
CW		 10120{
10121 struct intel_framebuffer *intel_fb;
10122 int ret;
10123
10124 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
dcb1394e 10125 if (!intel_fb)
d2dff872 10126 return ERR_PTR(-ENOMEM);
d2dff872
CW		 10127
10128 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10129 if (ret)
10130 goto err;
d2dff872
CW		 10131
10132 return &intel_fb->base;
dcb1394e 10133
dd4916c5 10134err:
dd4916c5 10135 kfree(intel_fb);
dd4916c5 10136 return ERR_PTR(ret);
d2dff872
CW		 10137}
10138
b5ea642a 10139static struct drm_framebuffer *
a8bb6818
DV		 10140intel_framebuffer_create(struct drm_device *dev,
10141 struct drm_mode_fb_cmd2 *mode_cmd,
10142 struct drm_i915_gem_object *obj)
10143{
10144 struct drm_framebuffer *fb;
10145 int ret;
10146
10147 ret = i915_mutex_lock_interruptible(dev);
10148 if (ret)
10149 return ERR_PTR(ret);
10150 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10151 mutex_unlock(&dev->struct_mutex);
10152
10153 return fb;
10154}
10155
d2dff872
CW		 10156static u32
10157intel_framebuffer_pitch_for_width(int width, int bpp)
10158{
10159 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10160 return ALIGN(pitch, 64);
10161}
10162
10163static u32
10164intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10165{
10166 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10167 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10168}
10169
10170static struct drm_framebuffer *
10171intel_framebuffer_create_for_mode(struct drm_device *dev,
10172 struct drm_display_mode *mode,
10173 int depth, int bpp)
10174{
dcb1394e 10175 struct drm_framebuffer *fb;
d2dff872 10176 struct drm_i915_gem_object *obj;
0fed39bd 10177 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10178
10179 obj = i915_gem_alloc_object(dev,
10180 intel_framebuffer_size_for_mode(mode, bpp));
10181 if (obj == NULL)
10182 return ERR_PTR(-ENOMEM);
10183
10184 mode_cmd.width = mode->hdisplay;
10185 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10186 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10187 bpp);
5ca0c34a 10188 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872 10189
dcb1394e
LW		 10190 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10191 if (IS_ERR(fb))
10192 drm_gem_object_unreference_unlocked(&obj->base);
10193
10194 return fb;
d2dff872
CW		 10195}
10196
10197static struct drm_framebuffer *
10198mode_fits_in_fbdev(struct drm_device *dev,
10199 struct drm_display_mode *mode)
10200{
0695726e 10201#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10202 struct drm_i915_private *dev_priv = dev->dev_private;
10203 struct drm_i915_gem_object *obj;
10204 struct drm_framebuffer *fb;
10205
4c0e5528 10206 if (!dev_priv->fbdev)
d2dff872
CW		 10207 return NULL;
10208
4c0e5528 10209 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10210 return NULL;
10211
4c0e5528
DV		 10212 obj = dev_priv->fbdev->fb->obj;
10213 BUG_ON(!obj);
10214
8bcd4553 10215 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10216 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10217 fb->bits_per_pixel))
d2dff872
CW		 10218 return NULL;
10219
01f2c773 10220 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10221 return NULL;
10222
10223 return fb;
4520f53a
DV		 10224#else
10225 return NULL;
10226#endif
d2dff872
CW		 10227}
10228
d3a40d1b
ACO		 10229static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10230 struct drm_crtc *crtc,
10231 struct drm_display_mode *mode,
10232 struct drm_framebuffer *fb,
10233 int x, int y)
10234{
10235 struct drm_plane_state *plane_state;
10236 int hdisplay, vdisplay;
10237 int ret;
10238
10239 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10240 if (IS_ERR(plane_state))
10241 return PTR_ERR(plane_state);
10242
10243 if (mode)
10244 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10245 else
10246 hdisplay = vdisplay = 0;
10247
10248 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10249 if (ret)
10250 return ret;
10251 drm_atomic_set_fb_for_plane(plane_state, fb);
10252 plane_state->crtc_x = 0;
10253 plane_state->crtc_y = 0;
10254 plane_state->crtc_w = hdisplay;
10255 plane_state->crtc_h = vdisplay;
10256 plane_state->src_x = x << 16;
10257 plane_state->src_y = y << 16;
10258 plane_state->src_w = hdisplay << 16;
10259 plane_state->src_h = vdisplay << 16;
10260
10261 return 0;
10262}
10263
d2434ab7 10264bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10265 struct drm_display_mode *mode,
51fd371b
RC		 10266 struct intel_load_detect_pipe *old,
10267 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10268{
10269 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10270 struct intel_encoder *intel_encoder =
10271 intel_attached_encoder(connector);
79e53945 10272 struct drm_crtc *possible_crtc;
4ef69c7a 10273 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10274 struct drm_crtc *crtc = NULL;
10275 struct drm_device *dev = encoder->dev;
94352cf9 10276 struct drm_framebuffer *fb;
51fd371b 10277 struct drm_mode_config *config = &dev->mode_config;
83a57153 10278 struct drm_atomic_state *state = NULL;
944b0c76 10279 struct drm_connector_state *connector_state;
4be07317 10280 struct intel_crtc_state *crtc_state;
51fd371b 10281 int ret, i = -1;
79e53945 10282
d2dff872 10283 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10284 connector->base.id, connector->name,
8e329a03 10285 encoder->base.id, encoder->name);
d2dff872 10286
51fd371b
RC		 10287retry:
10288 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10289 if (ret)
ad3c558f 10290 goto fail;
6e9f798d 10291
79e53945
JB		 10292 /*
10293 * Algorithm gets a little messy:
7a5e4805 10294 *
79e53945
JB		 10295 * - if the connector already has an assigned crtc, use it (but make
10296 * sure it's on first)
7a5e4805 10297 *
79e53945
JB		 10298 * - try to find the first unused crtc that can drive this connector,
10299 * and use that if we find one
79e53945
JB		 10300 */
10301
10302 /* See if we already have a CRTC for this connector */
10303 if (encoder->crtc) {
10304 crtc = encoder->crtc;
8261b191 10305
51fd371b 10306 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10307 if (ret)
ad3c558f 10308 goto fail;
4d02e2de 10309 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10310 if (ret)
ad3c558f 10311 goto fail;
7b24056b 10312
24218aac 10313 old->dpms_mode = connector->dpms;
8261b191
CW		 10314 old->load_detect_temp = false;
10315
10316 /* Make sure the crtc and connector are running */
24218aac
DV		 10317 if (connector->dpms != DRM_MODE_DPMS_ON)
10318 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10319
7173188d 10320 return true;
79e53945
JB		 10321 }
10322
10323 /* Find an unused one (if possible) */
70e1e0ec 10324 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10325 i++;
10326 if (!(encoder->possible_crtcs & (1 << i)))
10327 continue;
83d65738 10328 if (possible_crtc->state->enable)
a459249c 10329 continue;
a459249c
VS		 10330
10331 crtc = possible_crtc;
10332 break;
79e53945
JB		 10333 }
10334
10335 /*
10336 * If we didn't find an unused CRTC, don't use any.
10337 */
10338 if (!crtc) {
7173188d 10339 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10340 goto fail;
79e53945
JB		 10341 }
10342
51fd371b
RC		 10343 ret = drm_modeset_lock(&crtc->mutex, ctx);
10344 if (ret)
ad3c558f 10345 goto fail;
4d02e2de
DV		 10346 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10347 if (ret)
ad3c558f 10348 goto fail;
79e53945
JB		 10349
10350 intel_crtc = to_intel_crtc(crtc);
24218aac 10351 old->dpms_mode = connector->dpms;
8261b191 10352 old->load_detect_temp = true;
d2dff872 10353 old->release_fb = NULL;
79e53945 10354
83a57153
ACO		 10355 state = drm_atomic_state_alloc(dev);
10356 if (!state)
10357 return false;
10358
10359 state->acquire_ctx = ctx;
10360
944b0c76
ACO		 10361 connector_state = drm_atomic_get_connector_state(state, connector);
10362 if (IS_ERR(connector_state)) {
10363 ret = PTR_ERR(connector_state);
10364 goto fail;
10365 }
10366
10367 connector_state->crtc = crtc;
10368 connector_state->best_encoder = &intel_encoder->base;
10369
4be07317
ACO		 10370 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10371 if (IS_ERR(crtc_state)) {
10372 ret = PTR_ERR(crtc_state);
10373 goto fail;
10374 }
10375
49d6fa21 10376 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10377
6492711d
CW		 10378 if (!mode)
10379 mode = &load_detect_mode;
79e53945 10380
d2dff872
CW		 10381 /* We need a framebuffer large enough to accommodate all accesses
10382 * that the plane may generate whilst we perform load detection.
10383 * We can not rely on the fbcon either being present (we get called
10384 * during its initialisation to detect all boot displays, or it may
10385 * not even exist) or that it is large enough to satisfy the
10386 * requested mode.
10387 */
94352cf9
DV		 10388 fb = mode_fits_in_fbdev(dev, mode);
10389 if (fb == NULL) {
d2dff872 10390 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10391 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10392 old->release_fb = fb;
d2dff872
CW		 10393 } else
10394 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10395 if (IS_ERR(fb)) {
d2dff872 10396 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10397 goto fail;
79e53945 10398 }
79e53945 10399
d3a40d1b
ACO		 10400 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10401 if (ret)
10402 goto fail;
10403
8c7b5ccb
ACO		 10404 drm_mode_copy(&crtc_state->base.mode, mode);
10405
74c090b1 10406 if (drm_atomic_commit(state)) {
6492711d 10407 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10408 if (old->release_fb)
10409 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10410 goto fail;
79e53945 10411 }
9128b040 10412 crtc->primary->crtc = crtc;
7173188d 10413
79e53945 10414 /* let the connector get through one full cycle before testing */
9d0498a2 10415 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10416 return true;
412b61d8 10417
ad3c558f 10418fail:
e5d958ef
ACO		 10419 drm_atomic_state_free(state);
10420 state = NULL;
83a57153 10421
51fd371b
RC		 10422 if (ret == -EDEADLK) {
10423 drm_modeset_backoff(ctx);
10424 goto retry;
10425 }
10426
412b61d8 10427 return false;
79e53945
JB		 10428}
10429
d2434ab7 10430void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10431 struct intel_load_detect_pipe *old,
10432 struct drm_modeset_acquire_ctx *ctx)
79e53945 10433{
83a57153 10434 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10435 struct intel_encoder *intel_encoder =
10436 intel_attached_encoder(connector);
4ef69c7a 10437 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10438 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10440 struct drm_atomic_state *state;
944b0c76 10441 struct drm_connector_state *connector_state;
4be07317 10442 struct intel_crtc_state *crtc_state;
d3a40d1b 10443 int ret;
79e53945 10444
d2dff872 10445 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10446 connector->base.id, connector->name,
8e329a03 10447 encoder->base.id, encoder->name);
d2dff872 10448
8261b191 10449 if (old->load_detect_temp) {
83a57153 10450 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10451 if (!state)
10452 goto fail;
83a57153
ACO		 10453
10454 state->acquire_ctx = ctx;
10455
944b0c76
ACO		 10456 connector_state = drm_atomic_get_connector_state(state, connector);
10457 if (IS_ERR(connector_state))
10458 goto fail;
10459
4be07317
ACO		 10460 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10461 if (IS_ERR(crtc_state))
10462 goto fail;
10463
944b0c76
ACO		 10464 connector_state->best_encoder = NULL;
10465 connector_state->crtc = NULL;
10466
49d6fa21 10467 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10468
d3a40d1b
ACO		 10469 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10470 0, 0);
10471 if (ret)
10472 goto fail;
10473
74c090b1 10474 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10475 if (ret)
10476 goto fail;
d2dff872 10477
36206361
DV		 10478 if (old->release_fb) {
10479 drm_framebuffer_unregister_private(old->release_fb);
10480 drm_framebuffer_unreference(old->release_fb);
10481 }
d2dff872 10482
0622a53c 10483 return;
79e53945
JB		 10484 }
10485
c751ce4f 10486 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10487 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10488 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10489
10490 return;
10491fail:
10492 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10493 drm_atomic_state_free(state);
79e53945
JB		 10494}
10495
da4a1efa 10496static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10497 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10498{
10499 struct drm_i915_private *dev_priv = dev->dev_private;
10500 u32 dpll = pipe_config->dpll_hw_state.dpll;
10501
10502 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10503 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10504 else if (HAS_PCH_SPLIT(dev))
10505 return 120000;
10506 else if (!IS_GEN2(dev))
10507 return 96000;
10508 else
10509 return 48000;
10510}
10511
79e53945 10512/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10513static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10514 struct intel_crtc_state *pipe_config)
79e53945 10515{
f1f644dc 10516 struct drm_device *dev = crtc->base.dev;
79e53945 10517 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10518 int pipe = pipe_config->cpu_transcoder;
293623f7 10519 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10520 u32 fp;
10521 intel_clock_t clock;
dccbea3b 10522 int port_clock;
da4a1efa 10523 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10524
10525 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10526 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10527 else
293623f7 10528 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10529
10530 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10531 if (IS_PINEVIEW(dev)) {
10532 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10533 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10534 } else {
10535 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10536 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10537 }
10538
a6c45cf0 10539 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10540 if (IS_PINEVIEW(dev))
10541 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10542 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10543 else
10544 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10545 DPLL_FPA01_P1_POST_DIV_SHIFT);
10546
10547 switch (dpll & DPLL_MODE_MASK) {
10548 case DPLLB_MODE_DAC_SERIAL:
10549 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10550 5 : 10;
10551 break;
10552 case DPLLB_MODE_LVDS:
10553 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10554 7 : 14;
10555 break;
10556 default:
28c97730 10557 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10558 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10559 return;
79e53945
JB		 10560 }
10561
ac58c3f0 10562 if (IS_PINEVIEW(dev))
dccbea3b 10563 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10564 else
dccbea3b 10565 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10566 } else {
0fb58223 10567 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10568 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10569
10570 if (is_lvds) {
10571 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10572 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10573
10574 if (lvds & LVDS_CLKB_POWER_UP)
10575 clock.p2 = 7;
10576 else
10577 clock.p2 = 14;
79e53945
JB		 10578 } else {
10579 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10580 clock.p1 = 2;
10581 else {
10582 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10583 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10584 }
10585 if (dpll & PLL_P2_DIVIDE_BY_4)
10586 clock.p2 = 4;
10587 else
10588 clock.p2 = 2;
79e53945 10589 }
da4a1efa 10590
dccbea3b 10591 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10592 }
10593
18442d08
VS		 10594 /*
10595 * This value includes pixel_multiplier. We will use
241bfc38 10596 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10597 * encoder's get_config() function.
10598 */
dccbea3b 10599 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10600}
10601
6878da05
VS		 10602int intel_dotclock_calculate(int link_freq,
10603 const struct intel_link_m_n *m_n)
f1f644dc 10604{
f1f644dc
JB		 10605 /*
10606 * The calculation for the data clock is:
1041a02f 10607 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10608 * But we want to avoid losing precison if possible, so:
1041a02f 10609 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10610 *
10611 * and the link clock is simpler:
1041a02f 10612 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10613 */
10614
6878da05
VS		 10615 if (!m_n->link_n)
10616 return 0;
f1f644dc 10617
6878da05
VS		 10618 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10619}
f1f644dc 10620
18442d08 10621static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10622 struct intel_crtc_state *pipe_config)
6878da05
VS		 10623{
10624 struct drm_device *dev = crtc->base.dev;
79e53945 10625
18442d08
VS		 10626 /* read out port_clock from the DPLL */
10627 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10628
f1f644dc 10629 /*
18442d08 10630 * This value does not include pixel_multiplier.
241bfc38 10631 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10632 * agree once we know their relationship in the encoder's
10633 * get_config() function.
79e53945 10634 */
2d112de7 10635 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10636 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10637 &pipe_config->fdi_m_n);
79e53945
JB		 10638}
10639
10640/** Returns the currently programmed mode of the given pipe. */
10641struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10642 struct drm_crtc *crtc)
10643{
548f245b 10644 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10646 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10647 struct drm_display_mode *mode;
5cec258b 10648 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10649 int htot = I915_READ(HTOTAL(cpu_transcoder));
10650 int hsync = I915_READ(HSYNC(cpu_transcoder));
10651 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10652 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10653 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10654
10655 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10656 if (!mode)
10657 return NULL;
10658
f1f644dc
JB		 10659 /*
10660 * Construct a pipe_config sufficient for getting the clock info
10661 * back out of crtc_clock_get.
10662 *
10663 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10664 * to use a real value here instead.
10665 */
293623f7 10666 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10667 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10668 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10669 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10670 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10671 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10672
773ae034 10673 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10674 mode->hdisplay = (htot & 0xffff) + 1;
10675 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10676 mode->hsync_start = (hsync & 0xffff) + 1;
10677 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10678 mode->vdisplay = (vtot & 0xffff) + 1;
10679 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10680 mode->vsync_start = (vsync & 0xffff) + 1;
10681 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10682
10683 drm_mode_set_name(mode);
79e53945
JB		 10684
10685 return mode;
10686}
10687
f047e395
CW		 10688void intel_mark_busy(struct drm_device *dev)
10689{
c67a470b
PZ		 10690 struct drm_i915_private *dev_priv = dev->dev_private;
10691
f62a0076
CW		 10692 if (dev_priv->mm.busy)
10693 return;
10694
43694d69 10695 intel_runtime_pm_get(dev_priv);
c67a470b 10696 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10697 if (INTEL_INFO(dev)->gen >= 6)
10698 gen6_rps_busy(dev_priv);
f62a0076 10699 dev_priv->mm.busy = true;
f047e395
CW		 10700}
10701
10702void intel_mark_idle(struct drm_device *dev)
652c393a 10703{
c67a470b 10704 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10705
f62a0076
CW		 10706 if (!dev_priv->mm.busy)
10707 return;
10708
10709 dev_priv->mm.busy = false;
10710
3d13ef2e 10711 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10712 gen6_rps_idle(dev->dev_private);
bb4cdd53 10713
43694d69 10714 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10715}
10716
79e53945
JB		 10717static void intel_crtc_destroy(struct drm_crtc *crtc)
10718{
10719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10720 struct drm_device *dev = crtc->dev;
10721 struct intel_unpin_work *work;
67e77c5a 10722
5e2d7afc 10723 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10724 work = intel_crtc->unpin_work;
10725 intel_crtc->unpin_work = NULL;
5e2d7afc 10726 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10727
10728 if (work) {
10729 cancel_work_sync(&work->work);
10730 kfree(work);
10731 }
79e53945
JB		 10732
10733 drm_crtc_cleanup(crtc);
67e77c5a 10734
79e53945
JB		 10735 kfree(intel_crtc);
10736}
10737
6b95a207
KH		 10738static void intel_unpin_work_fn(struct work_struct *__work)
10739{
10740 struct intel_unpin_work *work =
10741 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10742 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10743 struct drm_device *dev = crtc->base.dev;
10744 struct drm_plane *primary = crtc->base.primary;
6b95a207 10745
b4a98e57 10746 mutex_lock(&dev->struct_mutex);
a9ff8714 10747 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10748 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10749
f06cc1b9 10750 if (work->flip_queued_req)
146d84f0 10751 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10752 mutex_unlock(&dev->struct_mutex);
10753
a9ff8714 10754 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10755 drm_framebuffer_unreference(work->old_fb);
f99d7069 10756
a9ff8714
VS		 10757 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10758 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10759
6b95a207
KH		 10760 kfree(work);
10761}
10762
1afe3e9d 10763static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10764 struct drm_crtc *crtc)
6b95a207 10765{
6b95a207
KH		 10766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10767 struct intel_unpin_work *work;
6b95a207
KH		 10768 unsigned long flags;
10769
10770 /* Ignore early vblank irqs */
10771 if (intel_crtc == NULL)
10772 return;
10773
f326038a
DV		 10774 /*
10775 * This is called both by irq handlers and the reset code (to complete
10776 * lost pageflips) so needs the full irqsave spinlocks.
10777 */
6b95a207
KH		 10778 spin_lock_irqsave(&dev->event_lock, flags);
10779 work = intel_crtc->unpin_work;
e7d841ca
CW		 10780
10781 /* Ensure we don't miss a work->pending update ... */
10782 smp_rmb();
10783
10784 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10785 spin_unlock_irqrestore(&dev->event_lock, flags);
10786 return;
10787 }
10788
d6bbafa1 10789 page_flip_completed(intel_crtc);
0af7e4df 10790
6b95a207 10791 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10792}
10793
1afe3e9d
JB		 10794void intel_finish_page_flip(struct drm_device *dev, int pipe)
10795{
fbee40df 10796 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10797 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10798
49b14a5c 10799 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10800}
10801
10802void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10803{
fbee40df 10804 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10805 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10806
49b14a5c 10807 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10808}
10809
75f7f3ec
VS		 10810/* Is 'a' after or equal to 'b'? */
10811static bool g4x_flip_count_after_eq(u32 a, u32 b)
10812{
10813 return !((a - b) & 0x80000000);
10814}
10815
10816static bool page_flip_finished(struct intel_crtc *crtc)
10817{
10818 struct drm_device *dev = crtc->base.dev;
10819 struct drm_i915_private *dev_priv = dev->dev_private;
10820
bdfa7542
VS		 10821 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10822 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10823 return true;
10824
75f7f3ec
VS		 10825 /*
10826 * The relevant registers doen't exist on pre-ctg.
10827 * As the flip done interrupt doesn't trigger for mmio
10828 * flips on gmch platforms, a flip count check isn't
10829 * really needed there. But since ctg has the registers,
10830 * include it in the check anyway.
10831 */
10832 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10833 return true;
10834
10835 /*
10836 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10837 * used the same base address. In that case the mmio flip might
10838 * have completed, but the CS hasn't even executed the flip yet.
10839 *
10840 * A flip count check isn't enough as the CS might have updated
10841 * the base address just after start of vblank, but before we
10842 * managed to process the interrupt. This means we'd complete the
10843 * CS flip too soon.
10844 *
10845 * Combining both checks should get us a good enough result. It may
10846 * still happen that the CS flip has been executed, but has not
10847 * yet actually completed. But in case the base address is the same
10848 * anyway, we don't really care.
10849 */
10850 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10851 crtc->unpin_work->gtt_offset &&
fd8f507c 10852 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
75f7f3ec
VS		 10853 crtc->unpin_work->flip_count);
10854}
10855
6b95a207
KH		 10856void intel_prepare_page_flip(struct drm_device *dev, int plane)
10857{
fbee40df 10858 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10859 struct intel_crtc *intel_crtc =
10860 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10861 unsigned long flags;
10862
f326038a
DV		 10863
10864 /*
10865 * This is called both by irq handlers and the reset code (to complete
10866 * lost pageflips) so needs the full irqsave spinlocks.
10867 *
10868 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10869 * generate a page-flip completion irq, i.e. every modeset
10870 * is also accompanied by a spurious intel_prepare_page_flip().
10871 */
6b95a207 10872 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10873 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10874 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10875 spin_unlock_irqrestore(&dev->event_lock, flags);
10876}
10877
6042639c 10878static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
e7d841ca
CW		 10879{
10880 /* Ensure that the work item is consistent when activating it ... */
10881 smp_wmb();
6042639c 10882 atomic_set(&work->pending, INTEL_FLIP_PENDING);
e7d841ca
CW		 10883 /* and that it is marked active as soon as the irq could fire. */
10884 smp_wmb();
10885}
10886
8c9f3aaf
JB		 10887static int intel_gen2_queue_flip(struct drm_device *dev,
10888 struct drm_crtc *crtc,
10889 struct drm_framebuffer *fb,
ed8d1975 10890 struct drm_i915_gem_object *obj,
6258fbe2 10891 struct drm_i915_gem_request *req,
ed8d1975 10892 uint32_t flags)
8c9f3aaf 10893{
6258fbe2 10894 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10896 u32 flip_mask;
10897 int ret;
10898
5fb9de1a 10899 ret = intel_ring_begin(req, 6);
8c9f3aaf 10900 if (ret)
4fa62c89 10901 return ret;
8c9f3aaf
JB		 10902
10903 /* Can't queue multiple flips, so wait for the previous
10904 * one to finish before executing the next.
10905 */
10906 if (intel_crtc->plane)
10907 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10908 else
10909 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10910 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10911 intel_ring_emit(ring, MI_NOOP);
10912 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10913 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10914 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10915 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10916 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca 10917
6042639c 10918 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10919 return 0;
8c9f3aaf
JB		 10920}
10921
10922static int intel_gen3_queue_flip(struct drm_device *dev,
10923 struct drm_crtc *crtc,
10924 struct drm_framebuffer *fb,
ed8d1975 10925 struct drm_i915_gem_object *obj,
6258fbe2 10926 struct drm_i915_gem_request *req,
ed8d1975 10927 uint32_t flags)
8c9f3aaf 10928{
6258fbe2 10929 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10931 u32 flip_mask;
10932 int ret;
10933
5fb9de1a 10934 ret = intel_ring_begin(req, 6);
8c9f3aaf 10935 if (ret)
4fa62c89 10936 return ret;
8c9f3aaf
JB		 10937
10938 if (intel_crtc->plane)
10939 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10940 else
10941 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10942 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10943 intel_ring_emit(ring, MI_NOOP);
10944 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10945 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10946 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10947 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10948 intel_ring_emit(ring, MI_NOOP);
10949
6042639c 10950 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10951 return 0;
8c9f3aaf
JB		 10952}
10953
10954static int intel_gen4_queue_flip(struct drm_device *dev,
10955 struct drm_crtc *crtc,
10956 struct drm_framebuffer *fb,
ed8d1975 10957 struct drm_i915_gem_object *obj,
6258fbe2 10958 struct drm_i915_gem_request *req,
ed8d1975 10959 uint32_t flags)
8c9f3aaf 10960{
6258fbe2 10961 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10962 struct drm_i915_private *dev_priv = dev->dev_private;
10963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10964 uint32_t pf, pipesrc;
10965 int ret;
10966
5fb9de1a 10967 ret = intel_ring_begin(req, 4);
8c9f3aaf 10968 if (ret)
4fa62c89 10969 return ret;
8c9f3aaf
JB		 10970
10971 /* i965+ uses the linear or tiled offsets from the
10972 * Display Registers (which do not change across a page-flip)
10973 * so we need only reprogram the base address.
10974 */
6d90c952
DV		 10975 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10976 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10977 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10978 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10979 obj->tiling_mode);
8c9f3aaf
JB		 10980
10981 /* XXX Enabling the panel-fitter across page-flip is so far
10982 * untested on non-native modes, so ignore it for now.
10983 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10984 */
10985 pf = 0;
10986 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10987 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10988
6042639c 10989 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10990 return 0;
8c9f3aaf
JB		 10991}
10992
10993static int intel_gen6_queue_flip(struct drm_device *dev,
10994 struct drm_crtc *crtc,
10995 struct drm_framebuffer *fb,
ed8d1975 10996 struct drm_i915_gem_object *obj,
6258fbe2 10997 struct drm_i915_gem_request *req,
ed8d1975 10998 uint32_t flags)
8c9f3aaf 10999{
6258fbe2 11000 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 11001 struct drm_i915_private *dev_priv = dev->dev_private;
11002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11003 uint32_t pf, pipesrc;
11004 int ret;
11005
5fb9de1a 11006 ret = intel_ring_begin(req, 4);
8c9f3aaf 11007 if (ret)
4fa62c89 11008 return ret;
8c9f3aaf 11009
6d90c952
DV		 11010 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11011 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11012 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11013 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11014
dc257cf1
DV		 11015 /* Contrary to the suggestions in the documentation,
11016 * "Enable Panel Fitter" does not seem to be required when page
11017 * flipping with a non-native mode, and worse causes a normal
11018 * modeset to fail.
11019 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11020 */
11021 pf = 0;
8c9f3aaf 11022 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11023 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 11024
6042639c 11025 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11026 return 0;
8c9f3aaf
JB		 11027}
11028
7c9017e5
JB		 11029static int intel_gen7_queue_flip(struct drm_device *dev,
11030 struct drm_crtc *crtc,
11031 struct drm_framebuffer *fb,
ed8d1975 11032 struct drm_i915_gem_object *obj,
6258fbe2 11033 struct drm_i915_gem_request *req,
ed8d1975 11034 uint32_t flags)
7c9017e5 11035{
6258fbe2 11036 struct intel_engine_cs *ring = req->ring;
7c9017e5 11037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11038 uint32_t plane_bit = 0;
ffe74d75
CW		 11039 int len, ret;
11040
eba905b2 11041 switch (intel_crtc->plane) {
cb05d8de
DV		 11042 case PLANE_A:
11043 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11044 break;
11045 case PLANE_B:
11046 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11047 break;
11048 case PLANE_C:
11049 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11050 break;
11051 default:
11052 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11053 return -ENODEV;
cb05d8de
DV		 11054 }
11055
ffe74d75 11056 len = 4;
f476828a 11057 if (ring->id == RCS) {
ffe74d75 11058 len += 6;
f476828a
DL		 11059 /*
11060 * On Gen 8, SRM is now taking an extra dword to accommodate
11061 * 48bits addresses, and we need a NOOP for the batch size to
11062 * stay even.
11063 */
11064 if (IS_GEN8(dev))
11065 len += 2;
11066 }
ffe74d75 11067
f66fab8e
VS		 11068 /*
11069 * BSpec MI_DISPLAY_FLIP for IVB:
11070 * "The full packet must be contained within the same cache line."
11071 *
11072 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11073 * cacheline, if we ever start emitting more commands before
11074 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11075 * then do the cacheline alignment, and finally emit the
11076 * MI_DISPLAY_FLIP.
11077 */
bba09b12 11078 ret = intel_ring_cacheline_align(req);
f66fab8e 11079 if (ret)
4fa62c89 11080 return ret;
f66fab8e 11081
5fb9de1a 11082 ret = intel_ring_begin(req, len);
7c9017e5 11083 if (ret)
4fa62c89 11084 return ret;
7c9017e5 11085
ffe74d75
CW		 11086 /* Unmask the flip-done completion message. Note that the bspec says that
11087 * we should do this for both the BCS and RCS, and that we must not unmask
11088 * more than one flip event at any time (or ensure that one flip message
11089 * can be sent by waiting for flip-done prior to queueing new flips).
11090 * Experimentation says that BCS works despite DERRMR masking all
11091 * flip-done completion events and that unmasking all planes at once
11092 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11093 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11094 */
11095 if (ring->id == RCS) {
11096 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11097 intel_ring_emit(ring, DERRMR);
11098 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11099 DERRMR_PIPEB_PRI_FLIP_DONE |
11100 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11101 if (IS_GEN8(dev))
f1afe24f 11102 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11103 MI_SRM_LRM_GLOBAL_GTT);
11104 else
f1afe24f 11105 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11106 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11107 intel_ring_emit(ring, DERRMR);
11108 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11109 if (IS_GEN8(dev)) {
11110 intel_ring_emit(ring, 0);
11111 intel_ring_emit(ring, MI_NOOP);
11112 }
ffe74d75
CW		 11113 }
11114
cb05d8de 11115 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11116 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11117 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11118 intel_ring_emit(ring, (MI_NOOP));
e7d841ca 11119
6042639c 11120 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11121 return 0;
7c9017e5
JB		 11122}
11123
84c33a64
SG		 11124static bool use_mmio_flip(struct intel_engine_cs *ring,
11125 struct drm_i915_gem_object *obj)
11126{
11127 /*
11128 * This is not being used for older platforms, because
11129 * non-availability of flip done interrupt forces us to use
11130 * CS flips. Older platforms derive flip done using some clever
11131 * tricks involving the flip_pending status bits and vblank irqs.
11132 * So using MMIO flips there would disrupt this mechanism.
11133 */
11134
8e09bf83
CW		 11135 if (ring == NULL)
11136 return true;
11137
84c33a64
SG		 11138 if (INTEL_INFO(ring->dev)->gen < 5)
11139 return false;
11140
11141 if (i915.use_mmio_flip < 0)
11142 return false;
11143 else if (i915.use_mmio_flip > 0)
11144 return true;
14bf993e
OM		 11145 else if (i915.enable_execlists)
11146 return true;
84c33a64 11147 else
b4716185 11148 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11149}
11150
6042639c 11151static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
86efe24a 11152 unsigned int rotation,
6042639c 11153 struct intel_unpin_work *work)
ff944564
DL		 11154{
11155 struct drm_device *dev = intel_crtc->base.dev;
11156 struct drm_i915_private *dev_priv = dev->dev_private;
11157 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564 11158 const enum pipe pipe = intel_crtc->pipe;
86efe24a 11159 u32 ctl, stride, tile_height;
ff944564
DL		 11160
11161 ctl = I915_READ(PLANE_CTL(pipe, 0));
11162 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11163 switch (fb->modifier[0]) {
11164 case DRM_FORMAT_MOD_NONE:
11165 break;
11166 case I915_FORMAT_MOD_X_TILED:
ff944564 11167 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11168 break;
11169 case I915_FORMAT_MOD_Y_TILED:
11170 ctl |= PLANE_CTL_TILED_Y;
11171 break;
11172 case I915_FORMAT_MOD_Yf_TILED:
11173 ctl |= PLANE_CTL_TILED_YF;
11174 break;
11175 default:
11176 MISSING_CASE(fb->modifier[0]);
11177 }
ff944564
DL		 11178
11179 /*
11180 * The stride is either expressed as a multiple of 64 bytes chunks for
11181 * linear buffers or in number of tiles for tiled buffers.
11182 */
86efe24a
TU		 11183 if (intel_rotation_90_or_270(rotation)) {
11184 /* stride = Surface height in tiles */
11185 tile_height = intel_tile_height(dev, fb->pixel_format,
11186 fb->modifier[0], 0);
11187 stride = DIV_ROUND_UP(fb->height, tile_height);
11188 } else {
11189 stride = fb->pitches[0] /
11190 intel_fb_stride_alignment(dev, fb->modifier[0],
11191 fb->pixel_format);
11192 }
ff944564
DL		 11193
11194 /*
11195 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11196 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11197 */
11198 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11199 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11200
6042639c 11201 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
ff944564
DL		 11202 POSTING_READ(PLANE_SURF(pipe, 0));
11203}
11204
6042639c
CW		 11205static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11206 struct intel_unpin_work *work)
84c33a64
SG		 11207{
11208 struct drm_device *dev = intel_crtc->base.dev;
11209 struct drm_i915_private *dev_priv = dev->dev_private;
11210 struct intel_framebuffer *intel_fb =
11211 to_intel_framebuffer(intel_crtc->base.primary->fb);
11212 struct drm_i915_gem_object *obj = intel_fb->obj;
11213 u32 dspcntr;
11214 u32 reg;
11215
84c33a64
SG		 11216 reg = DSPCNTR(intel_crtc->plane);
11217 dspcntr = I915_READ(reg);
11218
c5d97472
DL		 11219 if (obj->tiling_mode != I915_TILING_NONE)
11220 dspcntr |= DISPPLANE_TILED;
11221 else
11222 dspcntr &= ~DISPPLANE_TILED;
11223
84c33a64
SG		 11224 I915_WRITE(reg, dspcntr);
11225
6042639c 11226 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
84c33a64 11227 POSTING_READ(DSPSURF(intel_crtc->plane));
ff944564
DL		 11228}
11229
11230/*
11231 * XXX: This is the temporary way to update the plane registers until we get
11232 * around to using the usual plane update functions for MMIO flips
11233 */
6042639c 11234static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
ff944564 11235{
6042639c
CW		 11236 struct intel_crtc *crtc = mmio_flip->crtc;
11237 struct intel_unpin_work *work;
11238
11239 spin_lock_irq(&crtc->base.dev->event_lock);
11240 work = crtc->unpin_work;
11241 spin_unlock_irq(&crtc->base.dev->event_lock);
11242 if (work == NULL)
11243 return;
ff944564 11244
6042639c 11245 intel_mark_page_flip_active(work);
ff944564 11246
6042639c 11247 intel_pipe_update_start(crtc);
ff944564 11248
6042639c 11249 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
86efe24a 11250 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
ff944564
DL		 11251 else
11252 /* use_mmio_flip() retricts MMIO flips to ilk+ */
6042639c 11253 ilk_do_mmio_flip(crtc, work);
ff944564 11254
6042639c 11255 intel_pipe_update_end(crtc);
84c33a64
SG		 11256}
11257
9362c7c5 11258static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11259{
b2cfe0ab
CW		 11260 struct intel_mmio_flip *mmio_flip =
11261 container_of(work, struct intel_mmio_flip, work);
84c33a64 11262
6042639c 11263 if (mmio_flip->req) {
eed29a5b 11264 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11265 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11266 false, NULL,
11267 &mmio_flip->i915->rps.mmioflips));
6042639c
CW		 11268 i915_gem_request_unreference__unlocked(mmio_flip->req);
11269 }
84c33a64 11270
6042639c 11271 intel_do_mmio_flip(mmio_flip);
b2cfe0ab 11272 kfree(mmio_flip);
84c33a64
SG		 11273}
11274
11275static int intel_queue_mmio_flip(struct drm_device *dev,
11276 struct drm_crtc *crtc,
86efe24a 11277 struct drm_i915_gem_object *obj)
84c33a64 11278{
b2cfe0ab
CW		 11279 struct intel_mmio_flip *mmio_flip;
11280
11281 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11282 if (mmio_flip == NULL)
11283 return -ENOMEM;
84c33a64 11284
bcafc4e3 11285 mmio_flip->i915 = to_i915(dev);
eed29a5b 11286 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11287 mmio_flip->crtc = to_intel_crtc(crtc);
86efe24a 11288 mmio_flip->rotation = crtc->primary->state->rotation;
536f5b5e 11289
b2cfe0ab
CW		 11290 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11291 schedule_work(&mmio_flip->work);
84c33a64 11292
84c33a64
SG		 11293 return 0;
11294}
11295
8c9f3aaf
JB		 11296static int intel_default_queue_flip(struct drm_device *dev,
11297 struct drm_crtc *crtc,
11298 struct drm_framebuffer *fb,
ed8d1975 11299 struct drm_i915_gem_object *obj,
6258fbe2 11300 struct drm_i915_gem_request *req,
ed8d1975 11301 uint32_t flags)
8c9f3aaf
JB		 11302{
11303 return -ENODEV;
11304}
11305
d6bbafa1
CW		 11306static bool __intel_pageflip_stall_check(struct drm_device *dev,
11307 struct drm_crtc *crtc)
11308{
11309 struct drm_i915_private *dev_priv = dev->dev_private;
11310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11311 struct intel_unpin_work *work = intel_crtc->unpin_work;
11312 u32 addr;
11313
11314 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11315 return true;
11316
908565c2
CW		 11317 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11318 return false;
11319
d6bbafa1
CW		 11320 if (!work->enable_stall_check)
11321 return false;
11322
11323 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11324 if (work->flip_queued_req &&
11325 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11326 return false;
11327
1e3feefd 11328 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11329 }
11330
1e3feefd 11331 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11332 return false;
11333
11334 /* Potential stall - if we see that the flip has happened,
11335 * assume a missed interrupt. */
11336 if (INTEL_INFO(dev)->gen >= 4)
11337 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11338 else
11339 addr = I915_READ(DSPADDR(intel_crtc->plane));
11340
11341 /* There is a potential issue here with a false positive after a flip
11342 * to the same address. We could address this by checking for a
11343 * non-incrementing frame counter.
11344 */
11345 return addr == work->gtt_offset;
11346}
11347
11348void intel_check_page_flip(struct drm_device *dev, int pipe)
11349{
11350 struct drm_i915_private *dev_priv = dev->dev_private;
11351 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11353 struct intel_unpin_work *work;
f326038a 11354
6c51d46f 11355 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11356
11357 if (crtc == NULL)
11358 return;
11359
f326038a 11360 spin_lock(&dev->event_lock);
6ad790c0
CW		 11361 work = intel_crtc->unpin_work;
11362 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11363 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11364 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11365 page_flip_completed(intel_crtc);
6ad790c0 11366 work = NULL;
d6bbafa1 11367 }
6ad790c0
CW		 11368 if (work != NULL &&
11369 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11370 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11371 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11372}
11373
6b95a207
KH		 11374static int intel_crtc_page_flip(struct drm_crtc *crtc,
11375 struct drm_framebuffer *fb,
ed8d1975
KP		 11376 struct drm_pending_vblank_event *event,
11377 uint32_t page_flip_flags)
6b95a207
KH		 11378{
11379 struct drm_device *dev = crtc->dev;
11380 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11381 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11382 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11384 struct drm_plane *primary = crtc->primary;
a071fa00 11385 enum pipe pipe = intel_crtc->pipe;
6b95a207 11386 struct intel_unpin_work *work;
a4872ba6 11387 struct intel_engine_cs *ring;
cf5d8a46 11388 bool mmio_flip;
91af127f 11389 struct drm_i915_gem_request *request = NULL;
52e68630 11390 int ret;
6b95a207 11391
2ff8fde1
MR		 11392 /*
11393 * drm_mode_page_flip_ioctl() should already catch this, but double
11394 * check to be safe. In the future we may enable pageflipping from
11395 * a disabled primary plane.
11396 */
11397 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11398 return -EBUSY;
11399
e6a595d2 11400 /* Can't change pixel format via MI display flips. */
f4510a27 11401 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11402 return -EINVAL;
11403
11404 /*
11405 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11406 * Note that pitch changes could also affect these register.
11407 */
11408 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11409 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11410 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11411 return -EINVAL;
11412
f900db47
CW		 11413 if (i915_terminally_wedged(&dev_priv->gpu_error))
11414 goto out_hang;
11415
b14c5679 11416 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11417 if (work == NULL)
11418 return -ENOMEM;
11419
6b95a207 11420 work->event = event;
b4a98e57 11421 work->crtc = crtc;
ab8d6675 11422 work->old_fb = old_fb;
6b95a207
KH		 11423 INIT_WORK(&work->work, intel_unpin_work_fn);
11424
87b6b101 11425 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11426 if (ret)
11427 goto free_work;
11428
6b95a207 11429 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11430 spin_lock_irq(&dev->event_lock);
6b95a207 11431 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11432 /* Before declaring the flip queue wedged, check if
11433 * the hardware completed the operation behind our backs.
11434 */
11435 if (__intel_pageflip_stall_check(dev, crtc)) {
11436 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11437 page_flip_completed(intel_crtc);
11438 } else {
11439 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11440 spin_unlock_irq(&dev->event_lock);
468f0b44 11441
d6bbafa1
CW		 11442 drm_crtc_vblank_put(crtc);
11443 kfree(work);
11444 return -EBUSY;
11445 }
6b95a207
KH		 11446 }
11447 intel_crtc->unpin_work = work;
5e2d7afc 11448 spin_unlock_irq(&dev->event_lock);
6b95a207 11449
b4a98e57
CW		 11450 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11451 flush_workqueue(dev_priv->wq);
11452
75dfca80 11453 /* Reference the objects for the scheduled work. */
ab8d6675 11454 drm_framebuffer_reference(work->old_fb);
05394f39 11455 drm_gem_object_reference(&obj->base);
6b95a207 11456
f4510a27 11457 crtc->primary->fb = fb;
afd65eb4 11458 update_state_fb(crtc->primary);
1ed1f968 11459
e1f99ce6 11460 work->pending_flip_obj = obj;
e1f99ce6 11461
89ed88ba
CW		 11462 ret = i915_mutex_lock_interruptible(dev);
11463 if (ret)
11464 goto cleanup;
11465
b4a98e57 11466 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11467 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11468
75f7f3ec 11469 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
fd8f507c 11470 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
75f7f3ec 11471
4fa62c89
VS		 11472 if (IS_VALLEYVIEW(dev)) {
11473 ring = &dev_priv->ring[BCS];
ab8d6675 11474 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11475 /* vlv: DISPLAY_FLIP fails to change tiling */
11476 ring = NULL;
48bf5b2d 11477 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11478 ring = &dev_priv->ring[BCS];
4fa62c89 11479 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11480 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11481 if (ring == NULL || ring->id != RCS)
11482 ring = &dev_priv->ring[BCS];
11483 } else {
11484 ring = &dev_priv->ring[RCS];
11485 }
11486
cf5d8a46
CW		 11487 mmio_flip = use_mmio_flip(ring, obj);
11488
11489 /* When using CS flips, we want to emit semaphores between rings.
11490 * However, when using mmio flips we will create a task to do the
11491 * synchronisation, so all we want here is to pin the framebuffer
11492 * into the display plane and skip any waits.
11493 */
7580d774
ML		 11494 if (!mmio_flip) {
11495 ret = i915_gem_object_sync(obj, ring, &request);
11496 if (ret)
11497 goto cleanup_pending;
11498 }
11499
82bc3b2d 11500 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
7580d774 11501 crtc->primary->state);
8c9f3aaf
JB		 11502 if (ret)
11503 goto cleanup_pending;
6b95a207 11504
dedf278c
TU		 11505 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11506 obj, 0);
11507 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11508
cf5d8a46 11509 if (mmio_flip) {
86efe24a 11510 ret = intel_queue_mmio_flip(dev, crtc, obj);
d6bbafa1
CW		 11511 if (ret)
11512 goto cleanup_unpin;
11513
f06cc1b9
JH		 11514 i915_gem_request_assign(&work->flip_queued_req,
11515 obj->last_write_req);
d6bbafa1 11516 } else {
6258fbe2
JH		 11517 if (!request) {
11518 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11519 if (ret)
11520 goto cleanup_unpin;
11521 }
11522
11523 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11524 page_flip_flags);
11525 if (ret)
11526 goto cleanup_unpin;
11527
6258fbe2 11528 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11529 }
11530
91af127f 11531 if (request)
75289874 11532 i915_add_request_no_flush(request);
91af127f 11533
1e3feefd 11534 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11535 work->enable_stall_check = true;
4fa62c89 11536
ab8d6675 11537 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11538 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11539 mutex_unlock(&dev->struct_mutex);
a071fa00 11540
4e1e26f1 11541 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11542 intel_frontbuffer_flip_prepare(dev,
11543 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11544
e5510fac
JB		 11545 trace_i915_flip_request(intel_crtc->plane, obj);
11546
6b95a207 11547 return 0;
96b099fd 11548
4fa62c89 11549cleanup_unpin:
82bc3b2d 11550 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11551cleanup_pending:
91af127f
JH		 11552 if (request)
11553 i915_gem_request_cancel(request);
b4a98e57 11554 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11555 mutex_unlock(&dev->struct_mutex);
11556cleanup:
f4510a27 11557 crtc->primary->fb = old_fb;
afd65eb4 11558 update_state_fb(crtc->primary);
89ed88ba
CW		 11559
11560 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11561 drm_framebuffer_unreference(work->old_fb);
96b099fd 11562
5e2d7afc 11563 spin_lock_irq(&dev->event_lock);
96b099fd 11564 intel_crtc->unpin_work = NULL;
5e2d7afc 11565 spin_unlock_irq(&dev->event_lock);
96b099fd 11566
87b6b101 11567 drm_crtc_vblank_put(crtc);
7317c75e 11568free_work:
96b099fd
CW		 11569 kfree(work);
11570
f900db47 11571 if (ret == -EIO) {
02e0efb5
ML		 11572 struct drm_atomic_state *state;
11573 struct drm_plane_state *plane_state;
11574
f900db47 11575out_hang:
02e0efb5
ML		 11576 state = drm_atomic_state_alloc(dev);
11577 if (!state)
11578 return -ENOMEM;
11579 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11580
11581retry:
11582 plane_state = drm_atomic_get_plane_state(state, primary);
11583 ret = PTR_ERR_OR_ZERO(plane_state);
11584 if (!ret) {
11585 drm_atomic_set_fb_for_plane(plane_state, fb);
11586
11587 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11588 if (!ret)
11589 ret = drm_atomic_commit(state);
11590 }
11591
11592 if (ret == -EDEADLK) {
11593 drm_modeset_backoff(state->acquire_ctx);
11594 drm_atomic_state_clear(state);
11595 goto retry;
11596 }
11597
11598 if (ret)
11599 drm_atomic_state_free(state);
11600
f0d3dad3 11601 if (ret == 0 && event) {
5e2d7afc 11602 spin_lock_irq(&dev->event_lock);
a071fa00 11603 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11604 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11605 }
f900db47 11606 }
96b099fd 11607 return ret;
6b95a207
KH		 11608}
11609
da20eabd
ML		 11610
11611/**
11612 * intel_wm_need_update - Check whether watermarks need updating
11613 * @plane: drm plane
11614 * @state: new plane state
11615 *
11616 * Check current plane state versus the new one to determine whether
11617 * watermarks need to be recalculated.
11618 *
11619 * Returns true or false.
11620 */
11621static bool intel_wm_need_update(struct drm_plane *plane,
11622 struct drm_plane_state *state)
11623{
d21fbe87
MR		 11624 struct intel_plane_state *new = to_intel_plane_state(state);
11625 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11626
11627 /* Update watermarks on tiling or size changes. */
da20eabd
ML		 11628 if (!plane->state->fb || !state->fb ||
11629 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
d21fbe87
MR		 11630 plane->state->rotation != state->rotation ||
11631 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11632 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11633 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11634 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
2791a16c 11635 return true;
7809e5ae 11636
2791a16c 11637 return false;
7809e5ae
MR		 11638}
11639
d21fbe87
MR		 11640static bool needs_scaling(struct intel_plane_state *state)
11641{
11642 int src_w = drm_rect_width(&state->src) >> 16;
11643 int src_h = drm_rect_height(&state->src) >> 16;
11644 int dst_w = drm_rect_width(&state->dst);
11645 int dst_h = drm_rect_height(&state->dst);
11646
11647 return (src_w != dst_w || src_h != dst_h);
11648}
11649
da20eabd
ML		 11650int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11651 struct drm_plane_state *plane_state)
11652{
11653 struct drm_crtc *crtc = crtc_state->crtc;
11654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11655 struct drm_plane *plane = plane_state->plane;
11656 struct drm_device *dev = crtc->dev;
11657 struct drm_i915_private *dev_priv = dev->dev_private;
11658 struct intel_plane_state *old_plane_state =
11659 to_intel_plane_state(plane->state);
11660 int idx = intel_crtc->base.base.id, ret;
11661 int i = drm_plane_index(plane);
11662 bool mode_changed = needs_modeset(crtc_state);
11663 bool was_crtc_enabled = crtc->state->active;
11664 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML		 11665 bool turn_off, turn_on, visible, was_visible;
11666 struct drm_framebuffer *fb = plane_state->fb;
11667
11668 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11669 plane->type != DRM_PLANE_TYPE_CURSOR) {
11670 ret = skl_update_scaler_plane(
11671 to_intel_crtc_state(crtc_state),
11672 to_intel_plane_state(plane_state));
11673 if (ret)
11674 return ret;
11675 }
11676
da20eabd
ML		 11677 was_visible = old_plane_state->visible;
11678 visible = to_intel_plane_state(plane_state)->visible;
11679
11680 if (!was_crtc_enabled && WARN_ON(was_visible))
11681 was_visible = false;
11682
11683 if (!is_crtc_enabled && WARN_ON(visible))
11684 visible = false;
11685
11686 if (!was_visible && !visible)
11687 return 0;
11688
11689 turn_off = was_visible && (!visible || mode_changed);
11690 turn_on = visible && (!was_visible || mode_changed);
11691
11692 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11693 plane->base.id, fb ? fb->base.id : -1);
11694
11695 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11696 plane->base.id, was_visible, visible,
11697 turn_off, turn_on, mode_changed);
11698
852eb00d 11699 if (turn_on) {
f015c551 11700 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11701 /* must disable cxsr around plane enable/disable */
11702 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11703 intel_crtc->atomic.disable_cxsr = true;
11704 /* to potentially re-enable cxsr */
11705 intel_crtc->atomic.wait_vblank = true;
11706 intel_crtc->atomic.update_wm_post = true;
11707 }
11708 } else if (turn_off) {
f015c551 11709 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11710 /* must disable cxsr around plane enable/disable */
11711 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11712 if (is_crtc_enabled)
11713 intel_crtc->atomic.wait_vblank = true;
11714 intel_crtc->atomic.disable_cxsr = true;
11715 }
11716 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11717 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11718 }
da20eabd 11719
8be6ca85 11720 if (visible || was_visible)
a9ff8714
VS		 11721 intel_crtc->atomic.fb_bits |=
11722 to_intel_plane(plane)->frontbuffer_bit;
11723
da20eabd
ML		 11724 switch (plane->type) {
11725 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11726 intel_crtc->atomic.pre_disable_primary = turn_off;
11727 intel_crtc->atomic.post_enable_primary = turn_on;
11728
066cf55b
RV		 11729 if (turn_off) {
11730 /*
11731 * FIXME: Actually if we will still have any other
11732 * plane enabled on the pipe we could let IPS enabled
11733 * still, but for now lets consider that when we make
11734 * primary invisible by setting DSPCNTR to 0 on
11735 * update_primary_plane function IPS needs to be
11736 * disable.
11737 */
11738 intel_crtc->atomic.disable_ips = true;
11739
da20eabd 11740 intel_crtc->atomic.disable_fbc = true;
066cf55b 11741 }
da20eabd
ML		 11742
11743 /*
11744 * FBC does not work on some platforms for rotated
11745 * planes, so disable it when rotation is not 0 and
11746 * update it when rotation is set back to 0.
11747 *
11748 * FIXME: This is redundant with the fbc update done in
11749 * the primary plane enable function except that that
11750 * one is done too late. We eventually need to unify
11751 * this.
11752 */
11753
11754 if (visible &&
11755 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11756 dev_priv->fbc.crtc == intel_crtc &&
11757 plane_state->rotation != BIT(DRM_ROTATE_0))
11758 intel_crtc->atomic.disable_fbc = true;
11759
11760 /*
11761 * BDW signals flip done immediately if the plane
11762 * is disabled, even if the plane enable is already
11763 * armed to occur at the next vblank :(
11764 */
11765 if (turn_on && IS_BROADWELL(dev))
11766 intel_crtc->atomic.wait_vblank = true;
11767
11768 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11769 break;
11770 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11771 break;
11772 case DRM_PLANE_TYPE_OVERLAY:
d21fbe87
MR		 11773 /*
11774 * WaCxSRDisabledForSpriteScaling:ivb
11775 *
11776 * cstate->update_wm was already set above, so this flag will
11777 * take effect when we commit and program watermarks.
11778 */
11779 if (IS_IVYBRIDGE(dev) &&
11780 needs_scaling(to_intel_plane_state(plane_state)) &&
11781 !needs_scaling(old_plane_state)) {
11782 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11783 } else if (turn_off && !mode_changed) {
da20eabd
ML		 11784 intel_crtc->atomic.wait_vblank = true;
11785 intel_crtc->atomic.update_sprite_watermarks |=
11786 1 << i;
11787 }
d21fbe87
MR		 11788
11789 break;
da20eabd
ML		 11790 }
11791 return 0;
11792}
11793
6d3a1ce7
ML		 11794static bool encoders_cloneable(const struct intel_encoder *a,
11795 const struct intel_encoder *b)
11796{
11797 /* masks could be asymmetric, so check both ways */
11798 return a == b || (a->cloneable & (1 << b->type) &&
11799 b->cloneable & (1 << a->type));
11800}
11801
11802static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11803 struct intel_crtc *crtc,
11804 struct intel_encoder *encoder)
11805{
11806 struct intel_encoder *source_encoder;
11807 struct drm_connector *connector;
11808 struct drm_connector_state *connector_state;
11809 int i;
11810
11811 for_each_connector_in_state(state, connector, connector_state, i) {
11812 if (connector_state->crtc != &crtc->base)
11813 continue;
11814
11815 source_encoder =
11816 to_intel_encoder(connector_state->best_encoder);
11817 if (!encoders_cloneable(encoder, source_encoder))
11818 return false;
11819 }
11820
11821 return true;
11822}
11823
11824static bool check_encoder_cloning(struct drm_atomic_state *state,
11825 struct intel_crtc *crtc)
11826{
11827 struct intel_encoder *encoder;
11828 struct drm_connector *connector;
11829 struct drm_connector_state *connector_state;
11830 int i;
11831
11832 for_each_connector_in_state(state, connector, connector_state, i) {
11833 if (connector_state->crtc != &crtc->base)
11834 continue;
11835
11836 encoder = to_intel_encoder(connector_state->best_encoder);
11837 if (!check_single_encoder_cloning(state, crtc, encoder))
11838 return false;
11839 }
11840
11841 return true;
11842}
11843
11844static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11845 struct drm_crtc_state *crtc_state)
11846{
cf5a15be 11847 struct drm_device *dev = crtc->dev;
ad421372 11848 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11850 struct intel_crtc_state *pipe_config =
11851 to_intel_crtc_state(crtc_state);
6d3a1ce7 11852 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11853 int ret;
6d3a1ce7
ML		 11854 bool mode_changed = needs_modeset(crtc_state);
11855
11856 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11857 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11858 return -EINVAL;
11859 }
11860
852eb00d
VS		 11861 if (mode_changed && !crtc_state->active)
11862 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11863
ad421372
ML		 11864 if (mode_changed && crtc_state->enable &&
11865 dev_priv->display.crtc_compute_clock &&
11866 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11867 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11868 pipe_config);
11869 if (ret)
11870 return ret;
11871 }
11872
e435d6e5 11873 ret = 0;
86c8bbbe
MR		 11874 if (dev_priv->display.compute_pipe_wm) {
11875 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11876 if (ret)
11877 return ret;
11878 }
11879
e435d6e5
ML		 11880 if (INTEL_INFO(dev)->gen >= 9) {
11881 if (mode_changed)
11882 ret = skl_update_scaler_crtc(pipe_config);
11883
11884 if (!ret)
11885 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11886 pipe_config);
11887 }
11888
11889 return ret;
6d3a1ce7
ML		 11890}
11891
65b38e0d 11892static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11893 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11894 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11895 .atomic_begin = intel_begin_crtc_commit,
11896 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11897 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11898};
11899
d29b2f9d
ACO		 11900static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11901{
11902 struct intel_connector *connector;
11903
11904 for_each_intel_connector(dev, connector) {
11905 if (connector->base.encoder) {
11906 connector->base.state->best_encoder =
11907 connector->base.encoder;
11908 connector->base.state->crtc =
11909 connector->base.encoder->crtc;
11910 } else {
11911 connector->base.state->best_encoder = NULL;
11912 connector->base.state->crtc = NULL;
11913 }
11914 }
11915}
11916
050f7aeb 11917static void
eba905b2 11918connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11919 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11920{
11921 int bpp = pipe_config->pipe_bpp;
11922
11923 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11924 connector->base.base.id,
c23cc417 11925 connector->base.name);
050f7aeb
DV		 11926
11927 /* Don't use an invalid EDID bpc value */
11928 if (connector->base.display_info.bpc &&
11929 connector->base.display_info.bpc * 3 < bpp) {
11930 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11931 bpp, connector->base.display_info.bpc*3);
11932 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11933 }
11934
11935 /* Clamp bpp to 8 on screens without EDID 1.4 */
11936 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11937 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11938 bpp);
11939 pipe_config->pipe_bpp = 24;
11940 }
11941}
11942
4e53c2e0 11943static int
050f7aeb 11944compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11945 struct intel_crtc_state *pipe_config)
4e53c2e0 11946{
050f7aeb 11947 struct drm_device *dev = crtc->base.dev;
1486017f 11948 struct drm_atomic_state *state;
da3ced29
ACO		 11949 struct drm_connector *connector;
11950 struct drm_connector_state *connector_state;
1486017f 11951 int bpp, i;
4e53c2e0 11952
d328c9d7 11953 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11954 bpp = 10*3;
d328c9d7
DV		 11955 else if (INTEL_INFO(dev)->gen >= 5)
11956 bpp = 12*3;
11957 else
11958 bpp = 8*3;
11959
4e53c2e0 11960
4e53c2e0
DV		 11961 pipe_config->pipe_bpp = bpp;
11962
1486017f
ACO		 11963 state = pipe_config->base.state;
11964
4e53c2e0 11965 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11966 for_each_connector_in_state(state, connector, connector_state, i) {
11967 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11968 continue;
11969
da3ced29
ACO		 11970 connected_sink_compute_bpp(to_intel_connector(connector),
11971 pipe_config);
4e53c2e0
DV		 11972 }
11973
11974 return bpp;
11975}
11976
644db711
DV		 11977static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11978{
11979 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11980 "type: 0x%x flags: 0x%x\n",
1342830c 11981 mode->crtc_clock,
644db711
DV		 11982 mode->crtc_hdisplay, mode->crtc_hsync_start,
11983 mode->crtc_hsync_end, mode->crtc_htotal,
11984 mode->crtc_vdisplay, mode->crtc_vsync_start,
11985 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11986}
11987
c0b03411 11988static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11989 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11990 const char *context)
11991{
6a60cd87
CK		 11992 struct drm_device *dev = crtc->base.dev;
11993 struct drm_plane *plane;
11994 struct intel_plane *intel_plane;
11995 struct intel_plane_state *state;
11996 struct drm_framebuffer *fb;
11997
11998 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11999 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 12000
12001 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12002 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12003 pipe_config->pipe_bpp, pipe_config->dither);
12004 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12005 pipe_config->has_pch_encoder,
12006 pipe_config->fdi_lanes,
12007 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12008 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12009 pipe_config->fdi_m_n.tu);
90a6b7b0 12010 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 12011 pipe_config->has_dp_encoder,
90a6b7b0 12012 pipe_config->lane_count,
eb14cb74
VS		 12013 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12014 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12015 pipe_config->dp_m_n.tu);
b95af8be 12016
90a6b7b0 12017 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 12018 pipe_config->has_dp_encoder,
90a6b7b0 12019 pipe_config->lane_count,
b95af8be
VK		 12020 pipe_config->dp_m2_n2.gmch_m,
12021 pipe_config->dp_m2_n2.gmch_n,
12022 pipe_config->dp_m2_n2.link_m,
12023 pipe_config->dp_m2_n2.link_n,
12024 pipe_config->dp_m2_n2.tu);
12025
55072d19
DV		 12026 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12027 pipe_config->has_audio,
12028 pipe_config->has_infoframe);
12029
c0b03411 12030 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12031 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12032 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12033 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12034 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12035 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12036 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12037 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12038 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12039 crtc->num_scalers,
12040 pipe_config->scaler_state.scaler_users,
12041 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12042 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12043 pipe_config->gmch_pfit.control,
12044 pipe_config->gmch_pfit.pgm_ratios,
12045 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12046 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12047 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12048 pipe_config->pch_pfit.size,
12049 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12050 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12051 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12052
415ff0f6 12053 if (IS_BROXTON(dev)) {
05712c15 12054 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12055 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12056 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12057 pipe_config->ddi_pll_sel,
12058 pipe_config->dpll_hw_state.ebb0,
05712c15 12059 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12060 pipe_config->dpll_hw_state.pll0,
12061 pipe_config->dpll_hw_state.pll1,
12062 pipe_config->dpll_hw_state.pll2,
12063 pipe_config->dpll_hw_state.pll3,
12064 pipe_config->dpll_hw_state.pll6,
12065 pipe_config->dpll_hw_state.pll8,
05712c15 12066 pipe_config->dpll_hw_state.pll9,
c8453338 12067 pipe_config->dpll_hw_state.pll10,
415ff0f6 12068 pipe_config->dpll_hw_state.pcsdw12);
ef11bdb3 12069 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
415ff0f6
TU		 12070 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12071 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12072 pipe_config->ddi_pll_sel,
12073 pipe_config->dpll_hw_state.ctrl1,
12074 pipe_config->dpll_hw_state.cfgcr1,
12075 pipe_config->dpll_hw_state.cfgcr2);
12076 } else if (HAS_DDI(dev)) {
12077 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12078 pipe_config->ddi_pll_sel,
12079 pipe_config->dpll_hw_state.wrpll);
12080 } else {
12081 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12082 "fp0: 0x%x, fp1: 0x%x\n",
12083 pipe_config->dpll_hw_state.dpll,
12084 pipe_config->dpll_hw_state.dpll_md,
12085 pipe_config->dpll_hw_state.fp0,
12086 pipe_config->dpll_hw_state.fp1);
12087 }
12088
6a60cd87
CK		 12089 DRM_DEBUG_KMS("planes on this crtc\n");
12090 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12091 intel_plane = to_intel_plane(plane);
12092 if (intel_plane->pipe != crtc->pipe)
12093 continue;
12094
12095 state = to_intel_plane_state(plane->state);
12096 fb = state->base.fb;
12097 if (!fb) {
12098 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12099 "disabled, scaler_id = %d\n",
12100 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12101 plane->base.id, intel_plane->pipe,
12102 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12103 drm_plane_index(plane), state->scaler_id);
12104 continue;
12105 }
12106
12107 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12108 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12109 plane->base.id, intel_plane->pipe,
12110 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12111 drm_plane_index(plane));
12112 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12113 fb->base.id, fb->width, fb->height, fb->pixel_format);
12114 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12115 state->scaler_id,
12116 state->src.x1 >> 16, state->src.y1 >> 16,
12117 drm_rect_width(&state->src) >> 16,
12118 drm_rect_height(&state->src) >> 16,
12119 state->dst.x1, state->dst.y1,
12120 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12121 }
c0b03411
DV		 12122}
12123
5448a00d 12124static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12125{
5448a00d
ACO		 12126 struct drm_device *dev = state->dev;
12127 struct intel_encoder *encoder;
da3ced29 12128 struct drm_connector *connector;
5448a00d 12129 struct drm_connector_state *connector_state;
00f0b378 12130 unsigned int used_ports = 0;
5448a00d 12131 int i;
00f0b378
VS		 12132
12133 /*
12134 * Walk the connector list instead of the encoder
12135 * list to detect the problem on ddi platforms
12136 * where there's just one encoder per digital port.
12137 */
da3ced29 12138 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12139 if (!connector_state->best_encoder)
00f0b378
VS		 12140 continue;
12141
5448a00d
ACO		 12142 encoder = to_intel_encoder(connector_state->best_encoder);
12143
12144 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12145
12146 switch (encoder->type) {
12147 unsigned int port_mask;
12148 case INTEL_OUTPUT_UNKNOWN:
12149 if (WARN_ON(!HAS_DDI(dev)))
12150 break;
12151 case INTEL_OUTPUT_DISPLAYPORT:
12152 case INTEL_OUTPUT_HDMI:
12153 case INTEL_OUTPUT_EDP:
12154 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12155
12156 /* the same port mustn't appear more than once */
12157 if (used_ports & port_mask)
12158 return false;
12159
12160 used_ports |= port_mask;
12161 default:
12162 break;
12163 }
12164 }
12165
12166 return true;
12167}
12168
83a57153
ACO		 12169static void
12170clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12171{
12172 struct drm_crtc_state tmp_state;
663a3640 12173 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12174 struct intel_dpll_hw_state dpll_hw_state;
12175 enum intel_dpll_id shared_dpll;
8504c74c 12176 uint32_t ddi_pll_sel;
c4e2d043 12177 bool force_thru;
83a57153 12178
7546a384
ACO		 12179 /* FIXME: before the switch to atomic started, a new pipe_config was
12180 * kzalloc'd. Code that depends on any field being zero should be
12181 * fixed, so that the crtc_state can be safely duplicated. For now,
12182 * only fields that are know to not cause problems are preserved. */
12183
83a57153 12184 tmp_state = crtc_state->base;
663a3640 12185 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12186 shared_dpll = crtc_state->shared_dpll;
12187 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12188 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12189 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12190
83a57153 12191 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12192
83a57153 12193 crtc_state->base = tmp_state;
663a3640 12194 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12195 crtc_state->shared_dpll = shared_dpll;
12196 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12197 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12198 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12199}
12200
548ee15b 12201static int
b8cecdf5 12202intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12203 struct intel_crtc_state *pipe_config)
ee7b9f93 12204{
b359283a 12205 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12206 struct intel_encoder *encoder;
da3ced29 12207 struct drm_connector *connector;
0b901879 12208 struct drm_connector_state *connector_state;
d328c9d7 12209 int base_bpp, ret = -EINVAL;
0b901879 12210 int i;
e29c22c0 12211 bool retry = true;
ee7b9f93 12212
83a57153 12213 clear_intel_crtc_state(pipe_config);
7758a113 12214
e143a21c
DV		 12215 pipe_config->cpu_transcoder =
12216 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12217
2960bc9c
ID		 12218 /*
12219 * Sanitize sync polarity flags based on requested ones. If neither
12220 * positive or negative polarity is requested, treat this as meaning
12221 * negative polarity.
12222 */
2d112de7 12223 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12224 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12225 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12226
2d112de7 12227 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12228 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12229 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12230
d328c9d7
DV		 12231 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12232 pipe_config);
12233 if (base_bpp < 0)
4e53c2e0
DV		 12234 goto fail;
12235
e41a56be
VS		 12236 /*
12237 * Determine the real pipe dimensions. Note that stereo modes can
12238 * increase the actual pipe size due to the frame doubling and
12239 * insertion of additional space for blanks between the frame. This
12240 * is stored in the crtc timings. We use the requested mode to do this
12241 * computation to clearly distinguish it from the adjusted mode, which
12242 * can be changed by the connectors in the below retry loop.
12243 */
2d112de7 12244 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12245 &pipe_config->pipe_src_w,
12246 &pipe_config->pipe_src_h);
e41a56be 12247
e29c22c0 12248encoder_retry:
ef1b460d 12249 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12250 pipe_config->port_clock = 0;
ef1b460d 12251 pipe_config->pixel_multiplier = 1;
ff9a6750 12252
135c81b8 12253 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12254 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12255 CRTC_STEREO_DOUBLE);
135c81b8 12256
7758a113
DV		 12257 /* Pass our mode to the connectors and the CRTC to give them a chance to
12258 * adjust it according to limitations or connector properties, and also
12259 * a chance to reject the mode entirely.
47f1c6c9 12260 */
da3ced29 12261 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12262 if (connector_state->crtc != crtc)
7758a113 12263 continue;
7ae89233 12264
0b901879
ACO		 12265 encoder = to_intel_encoder(connector_state->best_encoder);
12266
efea6e8e
DV		 12267 if (!(encoder->compute_config(encoder, pipe_config))) {
12268 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12269 goto fail;
12270 }
ee7b9f93 12271 }
47f1c6c9 12272
ff9a6750
DV		 12273 /* Set default port clock if not overwritten by the encoder. Needs to be
12274 * done afterwards in case the encoder adjusts the mode. */
12275 if (!pipe_config->port_clock)
2d112de7 12276 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12277 * pipe_config->pixel_multiplier;
ff9a6750 12278
a43f6e0f 12279 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12280 if (ret < 0) {
7758a113
DV		 12281 DRM_DEBUG_KMS("CRTC fixup failed\n");
12282 goto fail;
ee7b9f93 12283 }
e29c22c0
DV		 12284
12285 if (ret == RETRY) {
12286 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12287 ret = -EINVAL;
12288 goto fail;
12289 }
12290
12291 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12292 retry = false;
12293 goto encoder_retry;
12294 }
12295
e8fa4270
DV		 12296 /* Dithering seems to not pass-through bits correctly when it should, so
12297 * only enable it on 6bpc panels. */
12298 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12299 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12300 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12301
7758a113 12302fail:
548ee15b 12303 return ret;
ee7b9f93 12304}
47f1c6c9 12305
ea9d758d 12306static void
4740b0f2 12307intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12308{
0a9ab303
ACO		 12309 struct drm_crtc *crtc;
12310 struct drm_crtc_state *crtc_state;
8a75d157 12311 int i;
ea9d758d 12312
7668851f 12313 /* Double check state. */
8a75d157 12314 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12315 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12316
12317 /* Update hwmode for vblank functions */
12318 if (crtc->state->active)
12319 crtc->hwmode = crtc->state->adjusted_mode;
12320 else
12321 crtc->hwmode.crtc_clock = 0;
61067a5e
ML		 12322
12323 /*
12324 * Update legacy state to satisfy fbc code. This can
12325 * be removed when fbc uses the atomic state.
12326 */
12327 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12328 struct drm_plane_state *plane_state = crtc->primary->state;
12329
12330 crtc->primary->fb = plane_state->fb;
12331 crtc->x = plane_state->src_x >> 16;
12332 crtc->y = plane_state->src_y >> 16;
12333 }
ea9d758d 12334 }
ea9d758d
DV		 12335}
12336
3bd26263 12337static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12338{
3bd26263 12339 int diff;
f1f644dc
JB		 12340
12341 if (clock1 == clock2)
12342 return true;
12343
12344 if (!clock1 || !clock2)
12345 return false;
12346
12347 diff = abs(clock1 - clock2);
12348
12349 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12350 return true;
12351
12352 return false;
12353}
12354
25c5b266
DV		 12355#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12356 list_for_each_entry((intel_crtc), \
12357 &(dev)->mode_config.crtc_list, \
12358 base.head) \
0973f18f 12359 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12360
cfb23ed6
ML		 12361static bool
12362intel_compare_m_n(unsigned int m, unsigned int n,
12363 unsigned int m2, unsigned int n2,
12364 bool exact)
12365{
12366 if (m == m2 && n == n2)
12367 return true;
12368
12369 if (exact || !m || !n || !m2 || !n2)
12370 return false;
12371
12372 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12373
12374 if (m > m2) {
12375 while (m > m2) {
12376 m2 <<= 1;
12377 n2 <<= 1;
12378 }
12379 } else if (m < m2) {
12380 while (m < m2) {
12381 m <<= 1;
12382 n <<= 1;
12383 }
12384 }
12385
12386 return m == m2 && n == n2;
12387}
12388
12389static bool
12390intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12391 struct intel_link_m_n *m2_n2,
12392 bool adjust)
12393{
12394 if (m_n->tu == m2_n2->tu &&
12395 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12396 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12397 intel_compare_m_n(m_n->link_m, m_n->link_n,
12398 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12399 if (adjust)
12400 *m2_n2 = *m_n;
12401
12402 return true;
12403 }
12404
12405 return false;
12406}
12407
0e8ffe1b 12408static bool
2fa2fe9a 12409intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12410 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12411 struct intel_crtc_state *pipe_config,
12412 bool adjust)
0e8ffe1b 12413{
cfb23ed6
ML		 12414 bool ret = true;
12415
12416#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12417 do { \
12418 if (!adjust) \
12419 DRM_ERROR(fmt, ##__VA_ARGS__); \
12420 else \
12421 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12422 } while (0)
12423
66e985c0
DV		 12424#define PIPE_CONF_CHECK_X(name) \
12425 if (current_config->name != pipe_config->name) { \
cfb23ed6 12426 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12427 "(expected 0x%08x, found 0x%08x)\n", \
12428 current_config->name, \
12429 pipe_config->name); \
cfb23ed6 12430 ret = false; \
66e985c0
DV		 12431 }
12432
08a24034
DV		 12433#define PIPE_CONF_CHECK_I(name) \
12434 if (current_config->name != pipe_config->name) { \
cfb23ed6 12435 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12436 "(expected %i, found %i)\n", \
12437 current_config->name, \
12438 pipe_config->name); \
cfb23ed6
ML		 12439 ret = false; \
12440 }
12441
12442#define PIPE_CONF_CHECK_M_N(name) \
12443 if (!intel_compare_link_m_n(&current_config->name, \
12444 &pipe_config->name,\
12445 adjust)) { \
12446 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12447 "(expected tu %i gmch %i/%i link %i/%i, " \
12448 "found tu %i, gmch %i/%i link %i/%i)\n", \
12449 current_config->name.tu, \
12450 current_config->name.gmch_m, \
12451 current_config->name.gmch_n, \
12452 current_config->name.link_m, \
12453 current_config->name.link_n, \
12454 pipe_config->name.tu, \
12455 pipe_config->name.gmch_m, \
12456 pipe_config->name.gmch_n, \
12457 pipe_config->name.link_m, \
12458 pipe_config->name.link_n); \
12459 ret = false; \
12460 }
12461
12462#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12463 if (!intel_compare_link_m_n(&current_config->name, \
12464 &pipe_config->name, adjust) && \
12465 !intel_compare_link_m_n(&current_config->alt_name, \
12466 &pipe_config->name, adjust)) { \
12467 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12468 "(expected tu %i gmch %i/%i link %i/%i, " \
12469 "or tu %i gmch %i/%i link %i/%i, " \
12470 "found tu %i, gmch %i/%i link %i/%i)\n", \
12471 current_config->name.tu, \
12472 current_config->name.gmch_m, \
12473 current_config->name.gmch_n, \
12474 current_config->name.link_m, \
12475 current_config->name.link_n, \
12476 current_config->alt_name.tu, \
12477 current_config->alt_name.gmch_m, \
12478 current_config->alt_name.gmch_n, \
12479 current_config->alt_name.link_m, \
12480 current_config->alt_name.link_n, \
12481 pipe_config->name.tu, \
12482 pipe_config->name.gmch_m, \
12483 pipe_config->name.gmch_n, \
12484 pipe_config->name.link_m, \
12485 pipe_config->name.link_n); \
12486 ret = false; \
88adfff1
DV		 12487 }
12488
b95af8be
VK		 12489/* This is required for BDW+ where there is only one set of registers for
12490 * switching between high and low RR.
12491 * This macro can be used whenever a comparison has to be made between one
12492 * hw state and multiple sw state variables.
12493 */
12494#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12495 if ((current_config->name != pipe_config->name) && \
12496 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12497 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12498 "(expected %i or %i, found %i)\n", \
12499 current_config->name, \
12500 current_config->alt_name, \
12501 pipe_config->name); \
cfb23ed6 12502 ret = false; \
b95af8be
VK		 12503 }
12504
1bd1bd80
DV		 12505#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12506 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12507 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12508 "(expected %i, found %i)\n", \
12509 current_config->name & (mask), \
12510 pipe_config->name & (mask)); \
cfb23ed6 12511 ret = false; \
1bd1bd80
DV		 12512 }
12513
5e550656
VS		 12514#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12515 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12516 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12517 "(expected %i, found %i)\n", \
12518 current_config->name, \
12519 pipe_config->name); \
cfb23ed6 12520 ret = false; \
5e550656
VS		 12521 }
12522
bb760063
DV		 12523#define PIPE_CONF_QUIRK(quirk) \
12524 ((current_config->quirks | pipe_config->quirks) & (quirk))
12525
eccb140b
DV		 12526 PIPE_CONF_CHECK_I(cpu_transcoder);
12527
08a24034
DV		 12528 PIPE_CONF_CHECK_I(has_pch_encoder);
12529 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12530 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12531
eb14cb74 12532 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12533 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12534
12535 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12536 PIPE_CONF_CHECK_M_N(dp_m_n);
12537
12538 PIPE_CONF_CHECK_I(has_drrs);
12539 if (current_config->has_drrs)
12540 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12541 } else
12542 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12543
2d112de7
ACO		 12544 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12545 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12546 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12547 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12548 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12549 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12550
2d112de7
ACO		 12551 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12552 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12553 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12554 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12555 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12556 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12557
c93f54cf 12558 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12559 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12560 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12561 IS_VALLEYVIEW(dev))
12562 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12563 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12564
9ed109a7
DV		 12565 PIPE_CONF_CHECK_I(has_audio);
12566
2d112de7 12567 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12568 DRM_MODE_FLAG_INTERLACE);
12569
bb760063 12570 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12571 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12572 DRM_MODE_FLAG_PHSYNC);
2d112de7 12573 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12574 DRM_MODE_FLAG_NHSYNC);
2d112de7 12575 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12576 DRM_MODE_FLAG_PVSYNC);
2d112de7 12577 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12578 DRM_MODE_FLAG_NVSYNC);
12579 }
045ac3b5 12580
333b8ca8 12581 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12582 /* pfit ratios are autocomputed by the hw on gen4+ */
12583 if (INTEL_INFO(dev)->gen < 4)
12584 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12585 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12586
bfd16b2a
ML		 12587 if (!adjust) {
12588 PIPE_CONF_CHECK_I(pipe_src_w);
12589 PIPE_CONF_CHECK_I(pipe_src_h);
12590
12591 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12592 if (current_config->pch_pfit.enabled) {
12593 PIPE_CONF_CHECK_X(pch_pfit.pos);
12594 PIPE_CONF_CHECK_X(pch_pfit.size);
12595 }
2fa2fe9a 12596
7aefe2b5
ML		 12597 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12598 }
a1b2278e 12599
e59150dc
JB		 12600 /* BDW+ don't expose a synchronous way to read the state */
12601 if (IS_HASWELL(dev))
12602 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12603
282740f7
VS		 12604 PIPE_CONF_CHECK_I(double_wide);
12605
26804afd
DV		 12606 PIPE_CONF_CHECK_X(ddi_pll_sel);
12607
c0d43d62 12608 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12609 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12610 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12611 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12612 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12613 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12614 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12615 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12616 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12617
42571aef
VS		 12618 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12619 PIPE_CONF_CHECK_I(pipe_bpp);
12620
2d112de7 12621 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12622 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12623
66e985c0 12624#undef PIPE_CONF_CHECK_X
08a24034 12625#undef PIPE_CONF_CHECK_I
b95af8be 12626#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12627#undef PIPE_CONF_CHECK_FLAGS
5e550656 12628#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12629#undef PIPE_CONF_QUIRK
cfb23ed6 12630#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12631
cfb23ed6 12632 return ret;
0e8ffe1b
DV		 12633}
12634
08db6652
DL		 12635static void check_wm_state(struct drm_device *dev)
12636{
12637 struct drm_i915_private *dev_priv = dev->dev_private;
12638 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12639 struct intel_crtc *intel_crtc;
12640 int plane;
12641
12642 if (INTEL_INFO(dev)->gen < 9)
12643 return;
12644
12645 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12646 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12647
12648 for_each_intel_crtc(dev, intel_crtc) {
12649 struct skl_ddb_entry *hw_entry, *sw_entry;
12650 const enum pipe pipe = intel_crtc->pipe;
12651
12652 if (!intel_crtc->active)
12653 continue;
12654
12655 /* planes */
dd740780 12656 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12657 hw_entry = &hw_ddb.plane[pipe][plane];
12658 sw_entry = &sw_ddb->plane[pipe][plane];
12659
12660 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12661 continue;
12662
12663 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12664 "(expected (%u,%u), found (%u,%u))\n",
12665 pipe_name(pipe), plane + 1,
12666 sw_entry->start, sw_entry->end,
12667 hw_entry->start, hw_entry->end);
12668 }
12669
12670 /* cursor */
4969d33e
MR		 12671 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12672 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652
DL		 12673
12674 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12675 continue;
12676
12677 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12678 "(expected (%u,%u), found (%u,%u))\n",
12679 pipe_name(pipe),
12680 sw_entry->start, sw_entry->end,
12681 hw_entry->start, hw_entry->end);
12682 }
12683}
12684
91d1b4bd 12685static void
35dd3c64
ML		 12686check_connector_state(struct drm_device *dev,
12687 struct drm_atomic_state *old_state)
8af6cf88 12688{
35dd3c64
ML		 12689 struct drm_connector_state *old_conn_state;
12690 struct drm_connector *connector;
12691 int i;
8af6cf88 12692
35dd3c64
ML		 12693 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12694 struct drm_encoder *encoder = connector->encoder;
12695 struct drm_connector_state *state = connector->state;
ad3c558f 12696
8af6cf88
DV		 12697 /* This also checks the encoder/connector hw state with the
12698 * ->get_hw_state callbacks. */
35dd3c64 12699 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12700
ad3c558f 12701 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12702 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12703 }
91d1b4bd
DV		 12704}
12705
12706static void
12707check_encoder_state(struct drm_device *dev)
12708{
12709 struct intel_encoder *encoder;
12710 struct intel_connector *connector;
8af6cf88 12711
b2784e15 12712 for_each_intel_encoder(dev, encoder) {
8af6cf88 12713 bool enabled = false;
4d20cd86 12714 enum pipe pipe;
8af6cf88
DV		 12715
12716 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12717 encoder->base.base.id,
8e329a03 12718 encoder->base.name);
8af6cf88 12719
3a3371ff 12720 for_each_intel_connector(dev, connector) {
4d20cd86 12721 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12722 continue;
12723 enabled = true;
ad3c558f
ML		 12724
12725 I915_STATE_WARN(connector->base.state->crtc !=
12726 encoder->base.crtc,
12727 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12728 }
0e32b39c 12729
e2c719b7 12730 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12731 "encoder's enabled state mismatch "
12732 "(expected %i, found %i)\n",
12733 !!encoder->base.crtc, enabled);
7c60d198
ML		 12734
12735 if (!encoder->base.crtc) {
4d20cd86 12736 bool active;
7c60d198 12737
4d20cd86
ML		 12738 active = encoder->get_hw_state(encoder, &pipe);
12739 I915_STATE_WARN(active,
12740 "encoder detached but still enabled on pipe %c.\n",
12741 pipe_name(pipe));
7c60d198 12742 }
8af6cf88 12743 }
91d1b4bd
DV		 12744}
12745
12746static void
4d20cd86 12747check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12748{
fbee40df 12749 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12750 struct intel_encoder *encoder;
4d20cd86
ML		 12751 struct drm_crtc_state *old_crtc_state;
12752 struct drm_crtc *crtc;
12753 int i;
8af6cf88 12754
4d20cd86
ML		 12755 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12757 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12758 bool active;
8af6cf88 12759
bfd16b2a
ML		 12760 if (!needs_modeset(crtc->state) &&
12761 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12762 continue;
045ac3b5 12763
4d20cd86
ML		 12764 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12765 pipe_config = to_intel_crtc_state(old_crtc_state);
12766 memset(pipe_config, 0, sizeof(*pipe_config));
12767 pipe_config->base.crtc = crtc;
12768 pipe_config->base.state = old_state;
8af6cf88 12769
4d20cd86
ML		 12770 DRM_DEBUG_KMS("[CRTC:%d]\n",
12771 crtc->base.id);
8af6cf88 12772
4d20cd86
ML		 12773 active = dev_priv->display.get_pipe_config(intel_crtc,
12774 pipe_config);
d62cf62a 12775
b6b5d049 12776 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12777 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12778 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12779 active = crtc->state->active;
6c49f241 12780
4d20cd86 12781 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12782 "crtc active state doesn't match with hw state "
4d20cd86 12783 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12784
4d20cd86 12785 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12786 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12787 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12788
12789 for_each_encoder_on_crtc(dev, crtc, encoder) {
12790 enum pipe pipe;
12791
12792 active = encoder->get_hw_state(encoder, &pipe);
12793 I915_STATE_WARN(active != crtc->state->active,
12794 "[ENCODER:%i] active %i with crtc active %i\n",
12795 encoder->base.base.id, active, crtc->state->active);
12796
12797 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12798 "Encoder connected to wrong pipe %c\n",
12799 pipe_name(pipe));
12800
12801 if (active)
12802 encoder->get_config(encoder, pipe_config);
12803 }
53d9f4e9 12804
4d20cd86 12805 if (!crtc->state->active)
cfb23ed6
ML		 12806 continue;
12807
4d20cd86
ML		 12808 sw_config = to_intel_crtc_state(crtc->state);
12809 if (!intel_pipe_config_compare(dev, sw_config,
12810 pipe_config, false)) {
e2c719b7 12811 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12812 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12813 "[hw state]");
4d20cd86 12814 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12815 "[sw state]");
12816 }
8af6cf88
DV		 12817 }
12818}
12819
91d1b4bd
DV		 12820static void
12821check_shared_dpll_state(struct drm_device *dev)
12822{
fbee40df 12823 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12824 struct intel_crtc *crtc;
12825 struct intel_dpll_hw_state dpll_hw_state;
12826 int i;
5358901f
DV		 12827
12828 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12829 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12830 int enabled_crtcs = 0, active_crtcs = 0;
12831 bool active;
12832
12833 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12834
12835 DRM_DEBUG_KMS("%s\n", pll->name);
12836
12837 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12838
e2c719b7 12839 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12840 "more active pll users than references: %i vs %i\n",
3e369b76 12841 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12842 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12843 "pll in active use but not on in sw tracking\n");
e2c719b7 12844 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12845 "pll in on but not on in use in sw tracking\n");
e2c719b7 12846 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12847 "pll on state mismatch (expected %i, found %i)\n",
12848 pll->on, active);
12849
d3fcc808 12850 for_each_intel_crtc(dev, crtc) {
83d65738 12851 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12852 enabled_crtcs++;
12853 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12854 active_crtcs++;
12855 }
e2c719b7 12856 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12857 "pll active crtcs mismatch (expected %i, found %i)\n",
12858 pll->active, active_crtcs);
e2c719b7 12859 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12860 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12861 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12862
e2c719b7 12863 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12864 sizeof(dpll_hw_state)),
12865 "pll hw state mismatch\n");
5358901f 12866 }
8af6cf88
DV		 12867}
12868
ee165b1a
ML		 12869static void
12870intel_modeset_check_state(struct drm_device *dev,
12871 struct drm_atomic_state *old_state)
91d1b4bd 12872{
08db6652 12873 check_wm_state(dev);
35dd3c64 12874 check_connector_state(dev, old_state);
91d1b4bd 12875 check_encoder_state(dev);
4d20cd86 12876 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12877 check_shared_dpll_state(dev);
12878}
12879
5cec258b 12880void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12881 int dotclock)
12882{
12883 /*
12884 * FDI already provided one idea for the dotclock.
12885 * Yell if the encoder disagrees.
12886 */
2d112de7 12887 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12888 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12889 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12890}
12891
80715b2f
VS		 12892static void update_scanline_offset(struct intel_crtc *crtc)
12893{
12894 struct drm_device *dev = crtc->base.dev;
12895
12896 /*
12897 * The scanline counter increments at the leading edge of hsync.
12898 *
12899 * On most platforms it starts counting from vtotal-1 on the
12900 * first active line. That means the scanline counter value is
12901 * always one less than what we would expect. Ie. just after
12902 * start of vblank, which also occurs at start of hsync (on the
12903 * last active line), the scanline counter will read vblank_start-1.
12904 *
12905 * On gen2 the scanline counter starts counting from 1 instead
12906 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12907 * to keep the value positive), instead of adding one.
12908 *
12909 * On HSW+ the behaviour of the scanline counter depends on the output
12910 * type. For DP ports it behaves like most other platforms, but on HDMI
12911 * there's an extra 1 line difference. So we need to add two instead of
12912 * one to the value.
12913 */
12914 if (IS_GEN2(dev)) {
124abe07 12915 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12916 int vtotal;
12917
124abe07
VS		 12918 vtotal = adjusted_mode->crtc_vtotal;
12919 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 12920 vtotal /= 2;
12921
12922 crtc->scanline_offset = vtotal - 1;
12923 } else if (HAS_DDI(dev) &&
409ee761 12924 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12925 crtc->scanline_offset = 2;
12926 } else
12927 crtc->scanline_offset = 1;
12928}
12929
ad421372 12930static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12931{
225da59b 12932 struct drm_device *dev = state->dev;
ed6739ef 12933 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12934 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12935 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12936 struct intel_crtc_state *intel_crtc_state;
12937 struct drm_crtc *crtc;
12938 struct drm_crtc_state *crtc_state;
0a9ab303 12939 int i;
ed6739ef
ACO		 12940
12941 if (!dev_priv->display.crtc_compute_clock)
ad421372 12942 return;
ed6739ef 12943
0a9ab303 12944 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12945 int dpll;
12946
0a9ab303 12947 intel_crtc = to_intel_crtc(crtc);
4978cc93 12948 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12949 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12950
ad421372 12951 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12952 continue;
12953
ad421372 12954 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12955
ad421372
ML		 12956 if (!shared_dpll)
12957 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12958
ad421372
ML		 12959 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12960 }
ed6739ef
ACO		 12961}
12962
99d736a2
ML		 12963/*
12964 * This implements the workaround described in the "notes" section of the mode
12965 * set sequence documentation. When going from no pipes or single pipe to
12966 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12967 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12968 */
12969static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12970{
12971 struct drm_crtc_state *crtc_state;
12972 struct intel_crtc *intel_crtc;
12973 struct drm_crtc *crtc;
12974 struct intel_crtc_state *first_crtc_state = NULL;
12975 struct intel_crtc_state *other_crtc_state = NULL;
12976 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12977 int i;
12978
12979 /* look at all crtc's that are going to be enabled in during modeset */
12980 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12981 intel_crtc = to_intel_crtc(crtc);
12982
12983 if (!crtc_state->active || !needs_modeset(crtc_state))
12984 continue;
12985
12986 if (first_crtc_state) {
12987 other_crtc_state = to_intel_crtc_state(crtc_state);
12988 break;
12989 } else {
12990 first_crtc_state = to_intel_crtc_state(crtc_state);
12991 first_pipe = intel_crtc->pipe;
12992 }
12993 }
12994
12995 /* No workaround needed? */
12996 if (!first_crtc_state)
12997 return 0;
12998
12999 /* w/a possibly needed, check how many crtc's are already enabled. */
13000 for_each_intel_crtc(state->dev, intel_crtc) {
13001 struct intel_crtc_state *pipe_config;
13002
13003 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13004 if (IS_ERR(pipe_config))
13005 return PTR_ERR(pipe_config);
13006
13007 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13008
13009 if (!pipe_config->base.active ||
13010 needs_modeset(&pipe_config->base))
13011 continue;
13012
13013 /* 2 or more enabled crtcs means no need for w/a */
13014 if (enabled_pipe != INVALID_PIPE)
13015 return 0;
13016
13017 enabled_pipe = intel_crtc->pipe;
13018 }
13019
13020 if (enabled_pipe != INVALID_PIPE)
13021 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13022 else if (other_crtc_state)
13023 other_crtc_state->hsw_workaround_pipe = first_pipe;
13024
13025 return 0;
13026}
13027
27c329ed
ML		 13028static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13029{
13030 struct drm_crtc *crtc;
13031 struct drm_crtc_state *crtc_state;
13032 int ret = 0;
13033
13034 /* add all active pipes to the state */
13035 for_each_crtc(state->dev, crtc) {
13036 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13037 if (IS_ERR(crtc_state))
13038 return PTR_ERR(crtc_state);
13039
13040 if (!crtc_state->active || needs_modeset(crtc_state))
13041 continue;
13042
13043 crtc_state->mode_changed = true;
13044
13045 ret = drm_atomic_add_affected_connectors(state, crtc);
13046 if (ret)
13047 break;
13048
13049 ret = drm_atomic_add_affected_planes(state, crtc);
13050 if (ret)
13051 break;
13052 }
13053
13054 return ret;
13055}
13056
c347a676 13057static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13058{
13059 struct drm_device *dev = state->dev;
27c329ed 13060 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13061 int ret;
13062
b359283a
ML		 13063 if (!check_digital_port_conflicts(state)) {
13064 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13065 return -EINVAL;
13066 }
13067
054518dd
ACO		 13068 /*
13069 * See if the config requires any additional preparation, e.g.
13070 * to adjust global state with pipes off. We need to do this
13071 * here so we can get the modeset_pipe updated config for the new
13072 * mode set on this crtc. For other crtcs we need to use the
13073 * adjusted_mode bits in the crtc directly.
13074 */
27c329ed
ML		 13075 if (dev_priv->display.modeset_calc_cdclk) {
13076 unsigned int cdclk;
b432e5cf 13077
27c329ed
ML		 13078 ret = dev_priv->display.modeset_calc_cdclk(state);
13079
13080 cdclk = to_intel_atomic_state(state)->cdclk;
13081 if (!ret && cdclk != dev_priv->cdclk_freq)
13082 ret = intel_modeset_all_pipes(state);
13083
13084 if (ret < 0)
054518dd 13085 return ret;
27c329ed
ML		 13086 } else
13087 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13088
ad421372 13089 intel_modeset_clear_plls(state);
054518dd 13090
99d736a2 13091 if (IS_HASWELL(dev))
ad421372 13092 return haswell_mode_set_planes_workaround(state);
99d736a2 13093
ad421372 13094 return 0;
c347a676
ACO		 13095}
13096
aa363136
MR		 13097/*
13098 * Handle calculation of various watermark data at the end of the atomic check
13099 * phase. The code here should be run after the per-crtc and per-plane 'check'
13100 * handlers to ensure that all derived state has been updated.
13101 */
13102static void calc_watermark_data(struct drm_atomic_state *state)
13103{
13104 struct drm_device *dev = state->dev;
13105 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13106 struct drm_crtc *crtc;
13107 struct drm_crtc_state *cstate;
13108 struct drm_plane *plane;
13109 struct drm_plane_state *pstate;
13110
13111 /*
13112 * Calculate watermark configuration details now that derived
13113 * plane/crtc state is all properly updated.
13114 */
13115 drm_for_each_crtc(crtc, dev) {
13116 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13117 crtc->state;
13118
13119 if (cstate->active)
13120 intel_state->wm_config.num_pipes_active++;
13121 }
13122 drm_for_each_legacy_plane(plane, dev) {
13123 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13124 plane->state;
13125
13126 if (!to_intel_plane_state(pstate)->visible)
13127 continue;
13128
13129 intel_state->wm_config.sprites_enabled = true;
13130 if (pstate->crtc_w != pstate->src_w >> 16 ||
13131 pstate->crtc_h != pstate->src_h >> 16)
13132 intel_state->wm_config.sprites_scaled = true;
13133 }
13134}
13135
74c090b1
ML		 13136/**
13137 * intel_atomic_check - validate state object
13138 * @dev: drm device
13139 * @state: state to validate
13140 */
13141static int intel_atomic_check(struct drm_device *dev,
13142 struct drm_atomic_state *state)
c347a676 13143{
aa363136 13144 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO		 13145 struct drm_crtc *crtc;
13146 struct drm_crtc_state *crtc_state;
13147 int ret, i;
61333b60 13148 bool any_ms = false;
c347a676 13149
74c090b1 13150 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13151 if (ret)
13152 return ret;
13153
c347a676 13154 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13155 struct intel_crtc_state *pipe_config =
13156 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13157
13158 /* Catch I915_MODE_FLAG_INHERITED */
13159 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13160 crtc_state->mode_changed = true;
cfb23ed6 13161
61333b60
ML		 13162 if (!crtc_state->enable) {
13163 if (needs_modeset(crtc_state))
13164 any_ms = true;
c347a676 13165 continue;
61333b60 13166 }
c347a676 13167
26495481 13168 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13169 continue;
13170
26495481
DV		 13171 /* FIXME: For only active_changed we shouldn't need to do any
13172 * state recomputation at all. */
13173
1ed51de9
DV		 13174 ret = drm_atomic_add_affected_connectors(state, crtc);
13175 if (ret)
13176 return ret;
b359283a 13177
cfb23ed6 13178 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13179 if (ret)
13180 return ret;
13181
6764e9f8 13182 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13183 to_intel_crtc_state(crtc->state),
1ed51de9 13184 pipe_config, true)) {
26495481 13185 crtc_state->mode_changed = false;
bfd16b2a 13186 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13187 }
13188
13189 if (needs_modeset(crtc_state)) {
13190 any_ms = true;
cfb23ed6
ML		 13191
13192 ret = drm_atomic_add_affected_planes(state, crtc);
13193 if (ret)
13194 return ret;
13195 }
61333b60 13196
26495481
DV		 13197 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13198 needs_modeset(crtc_state) ?
13199 "[modeset]" : "[fastset]");
c347a676
ACO		 13200 }
13201
61333b60
ML		 13202 if (any_ms) {
13203 ret = intel_modeset_checks(state);
13204
13205 if (ret)
13206 return ret;
27c329ed 13207 } else
aa363136 13208 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
76305b1a 13209
aa363136
MR		 13210 ret = drm_atomic_helper_check_planes(state->dev, state);
13211 if (ret)
13212 return ret;
13213
13214 calc_watermark_data(state);
13215
13216 return 0;
054518dd
ACO		 13217}
13218
5008e874
ML		 13219static int intel_atomic_prepare_commit(struct drm_device *dev,
13220 struct drm_atomic_state *state,
13221 bool async)
13222{
7580d774
ML		 13223 struct drm_i915_private *dev_priv = dev->dev_private;
13224 struct drm_plane_state *plane_state;
5008e874 13225 struct drm_crtc_state *crtc_state;
7580d774 13226 struct drm_plane *plane;
5008e874
ML		 13227 struct drm_crtc *crtc;
13228 int i, ret;
13229
13230 if (async) {
13231 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13232 return -EINVAL;
13233 }
13234
13235 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13236 ret = intel_crtc_wait_for_pending_flips(crtc);
13237 if (ret)
13238 return ret;
7580d774
ML		 13239
13240 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13241 flush_workqueue(dev_priv->wq);
5008e874
ML		 13242 }
13243
f935675f
ML		 13244 ret = mutex_lock_interruptible(&dev->struct_mutex);
13245 if (ret)
13246 return ret;
13247
5008e874 13248 ret = drm_atomic_helper_prepare_planes(dev, state);
7580d774
ML		 13249 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13250 u32 reset_counter;
13251
13252 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13253 mutex_unlock(&dev->struct_mutex);
13254
13255 for_each_plane_in_state(state, plane, plane_state, i) {
13256 struct intel_plane_state *intel_plane_state =
13257 to_intel_plane_state(plane_state);
13258
13259 if (!intel_plane_state->wait_req)
13260 continue;
13261
13262 ret = __i915_wait_request(intel_plane_state->wait_req,
13263 reset_counter, true,
13264 NULL, NULL);
13265
13266 /* Swallow -EIO errors to allow updates during hw lockup. */
13267 if (ret == -EIO)
13268 ret = 0;
13269
13270 if (ret)
13271 break;
13272 }
13273
13274 if (!ret)
13275 return 0;
13276
13277 mutex_lock(&dev->struct_mutex);
13278 drm_atomic_helper_cleanup_planes(dev, state);
13279 }
5008e874 13280
f935675f 13281 mutex_unlock(&dev->struct_mutex);
5008e874
ML		 13282 return ret;
13283}
13284
74c090b1
ML		 13285/**
13286 * intel_atomic_commit - commit validated state object
13287 * @dev: DRM device
13288 * @state: the top-level driver state object
13289 * @async: asynchronous commit
13290 *
13291 * This function commits a top-level state object that has been validated
13292 * with drm_atomic_helper_check().
13293 *
13294 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13295 * we can only handle plane-related operations and do not yet support
13296 * asynchronous commit.
13297 *
13298 * RETURNS
13299 * Zero for success or -errno.
13300 */
13301static int intel_atomic_commit(struct drm_device *dev,
13302 struct drm_atomic_state *state,
13303 bool async)
a6778b3c 13304{
fbee40df 13305 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303 13306 struct drm_crtc_state *crtc_state;
7580d774 13307 struct drm_crtc *crtc;
c0c36b94 13308 int ret = 0;
0a9ab303 13309 int i;
61333b60 13310 bool any_ms = false;
a6778b3c 13311
5008e874 13312 ret = intel_atomic_prepare_commit(dev, state, async);
7580d774
ML		 13313 if (ret) {
13314 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
d4afb8cc 13315 return ret;
7580d774 13316 }
d4afb8cc 13317
1c5e19f8 13318 drm_atomic_helper_swap_state(dev, state);
aa363136 13319 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
1c5e19f8 13320
0a9ab303 13321 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13323
61333b60
ML		 13324 if (!needs_modeset(crtc->state))
13325 continue;
13326
13327 any_ms = true;
a539205a 13328 intel_pre_plane_update(intel_crtc);
460da916 13329
a539205a
ML		 13330 if (crtc_state->active) {
13331 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13332 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13333 intel_crtc->active = false;
13334 intel_disable_shared_dpll(intel_crtc);
a539205a 13335 }
b8cecdf5 13336 }
7758a113 13337
ea9d758d
DV		 13338 /* Only after disabling all output pipelines that will be changed can we
13339 * update the the output configuration. */
4740b0f2 13340 intel_modeset_update_crtc_state(state);
f6e5b160 13341
4740b0f2
ML		 13342 if (any_ms) {
13343 intel_shared_dpll_commit(state);
13344
13345 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13346 modeset_update_crtc_power_domains(state);
4740b0f2 13347 }
47fab737 13348
a6778b3c 13349 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13350 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13352 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13353 bool update_pipe = !modeset &&
13354 to_intel_crtc_state(crtc->state)->update_pipe;
13355 unsigned long put_domains = 0;
f6ac4b2a
ML		 13356
13357 if (modeset && crtc->state->active) {
a539205a
ML		 13358 update_scanline_offset(to_intel_crtc(crtc));
13359 dev_priv->display.crtc_enable(crtc);
13360 }
80715b2f 13361
bfd16b2a
ML		 13362 if (update_pipe) {
13363 put_domains = modeset_get_crtc_power_domains(crtc);
13364
13365 /* make sure intel_modeset_check_state runs */
13366 any_ms = true;
13367 }
13368
f6ac4b2a
ML		 13369 if (!modeset)
13370 intel_pre_plane_update(intel_crtc);
13371
6173ee28
ML		 13372 if (crtc->state->active &&
13373 (crtc->state->planes_changed || update_pipe))
62852622 13374 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13375
13376 if (put_domains)
13377 modeset_put_power_domains(dev_priv, put_domains);
13378
f6ac4b2a 13379 intel_post_plane_update(intel_crtc);
80715b2f 13380 }
a6778b3c 13381
a6778b3c 13382 /* FIXME: add subpixel order */
83a57153 13383
74c090b1 13384 drm_atomic_helper_wait_for_vblanks(dev, state);
f935675f
ML		 13385
13386 mutex_lock(&dev->struct_mutex);
d4afb8cc 13387 drm_atomic_helper_cleanup_planes(dev, state);
f935675f 13388 mutex_unlock(&dev->struct_mutex);
2bfb4627 13389
74c090b1 13390 if (any_ms)
ee165b1a
ML		 13391 intel_modeset_check_state(dev, state);
13392
13393 drm_atomic_state_free(state);
f30da187 13394
74c090b1 13395 return 0;
7f27126e
JB		 13396}
13397
c0c36b94
CW		 13398void intel_crtc_restore_mode(struct drm_crtc *crtc)
13399{
83a57153
ACO		 13400 struct drm_device *dev = crtc->dev;
13401 struct drm_atomic_state *state;
e694eb02 13402 struct drm_crtc_state *crtc_state;
2bfb4627 13403 int ret;
83a57153
ACO		 13404
13405 state = drm_atomic_state_alloc(dev);
13406 if (!state) {
e694eb02 13407 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13408 crtc->base.id);
13409 return;
13410 }
13411
e694eb02 13412 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13413
e694eb02
ML		 13414retry:
13415 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13416 ret = PTR_ERR_OR_ZERO(crtc_state);
13417 if (!ret) {
13418 if (!crtc_state->active)
13419 goto out;
83a57153 13420
e694eb02 13421 crtc_state->mode_changed = true;
74c090b1 13422 ret = drm_atomic_commit(state);
83a57153
ACO		 13423 }
13424
e694eb02
ML		 13425 if (ret == -EDEADLK) {
13426 drm_atomic_state_clear(state);
13427 drm_modeset_backoff(state->acquire_ctx);
13428 goto retry;
4ed9fb37 13429 }
4be07317 13430
2bfb4627 13431 if (ret)
e694eb02 13432out:
2bfb4627 13433 drm_atomic_state_free(state);
c0c36b94
CW		 13434}
13435
25c5b266
DV		 13436#undef for_each_intel_crtc_masked
13437
f6e5b160 13438static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13439 .gamma_set = intel_crtc_gamma_set,
74c090b1 13440 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13441 .destroy = intel_crtc_destroy,
13442 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13443 .atomic_duplicate_state = intel_crtc_duplicate_state,
13444 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13445};
13446
5358901f
DV		 13447static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13448 struct intel_shared_dpll *pll,
13449 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13450{
5358901f 13451 uint32_t val;
ee7b9f93 13452
f458ebbc 13453 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13454 return false;
13455
5358901f 13456 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13457 hw_state->dpll = val;
13458 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13459 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13460
13461 return val & DPLL_VCO_ENABLE;
13462}
13463
15bdd4cf
DV		 13464static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13465 struct intel_shared_dpll *pll)
13466{
3e369b76
ACO		 13467 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13468 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13469}
13470
e7b903d2
DV		 13471static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13472 struct intel_shared_dpll *pll)
13473{
e7b903d2 13474 /* PCH refclock must be enabled first */
89eff4be 13475 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13476
3e369b76 13477 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13478
13479 /* Wait for the clocks to stabilize. */
13480 POSTING_READ(PCH_DPLL(pll->id));
13481 udelay(150);
13482
13483 /* The pixel multiplier can only be updated once the
13484 * DPLL is enabled and the clocks are stable.
13485 *
13486 * So write it again.
13487 */
3e369b76 13488 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13489 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13490 udelay(200);
13491}
13492
13493static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13494 struct intel_shared_dpll *pll)
13495{
13496 struct drm_device *dev = dev_priv->dev;
13497 struct intel_crtc *crtc;
e7b903d2
DV		 13498
13499 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13500 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13501 if (intel_crtc_to_shared_dpll(crtc) == pll)
13502 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13503 }
13504
15bdd4cf
DV		 13505 I915_WRITE(PCH_DPLL(pll->id), 0);
13506 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13507 udelay(200);
13508}
13509
46edb027
DV		 13510static char *ibx_pch_dpll_names[] = {
13511 "PCH DPLL A",
13512 "PCH DPLL B",
13513};
13514
7c74ade1 13515static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13516{
e7b903d2 13517 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13518 int i;
13519
7c74ade1 13520 dev_priv->num_shared_dpll = 2;
ee7b9f93 13521
e72f9fbf 13522 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13523 dev_priv->shared_dplls[i].id = i;
13524 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13525 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13526 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13527 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13528 dev_priv->shared_dplls[i].get_hw_state =
13529 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13530 }
13531}
13532
7c74ade1
DV		 13533static void intel_shared_dpll_init(struct drm_device *dev)
13534{
e7b903d2 13535 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13536
9cd86933
DV		 13537 if (HAS_DDI(dev))
13538 intel_ddi_pll_init(dev);
13539 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13540 ibx_pch_dpll_init(dev);
13541 else
13542 dev_priv->num_shared_dpll = 0;
13543
13544 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13545}
13546
6beb8c23
MR		 13547/**
13548 * intel_prepare_plane_fb - Prepare fb for usage on plane
13549 * @plane: drm plane to prepare for
13550 * @fb: framebuffer to prepare for presentation
13551 *
13552 * Prepares a framebuffer for usage on a display plane. Generally this
13553 * involves pinning the underlying object and updating the frontbuffer tracking
13554 * bits. Some older platforms need special physical address handling for
13555 * cursor planes.
13556 *
f935675f
ML		 13557 * Must be called with struct_mutex held.
13558 *
6beb8c23
MR		 13559 * Returns 0 on success, negative error code on failure.
13560 */
13561int
13562intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13563 const struct drm_plane_state *new_state)
465c120c
MR		 13564{
13565 struct drm_device *dev = plane->dev;
844f9111 13566 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13567 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23 13568 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 13569 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
6beb8c23 13570 int ret = 0;
465c120c 13571
1ee49399 13572 if (!obj && !old_obj)
465c120c
MR		 13573 return 0;
13574
5008e874
ML		 13575 if (old_obj) {
13576 struct drm_crtc_state *crtc_state =
13577 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13578
13579 /* Big Hammer, we also need to ensure that any pending
13580 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13581 * current scanout is retired before unpinning the old
13582 * framebuffer. Note that we rely on userspace rendering
13583 * into the buffer attached to the pipe they are waiting
13584 * on. If not, userspace generates a GPU hang with IPEHR
13585 * point to the MI_WAIT_FOR_EVENT.
13586 *
13587 * This should only fail upon a hung GPU, in which case we
13588 * can safely continue.
13589 */
13590 if (needs_modeset(crtc_state))
13591 ret = i915_gem_object_wait_rendering(old_obj, true);
13592
13593 /* Swallow -EIO errors to allow updates during hw lockup. */
13594 if (ret && ret != -EIO)
f935675f 13595 return ret;
5008e874
ML		 13596 }
13597
1ee49399
ML		 13598 if (!obj) {
13599 ret = 0;
13600 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
6beb8c23
MR		 13601 INTEL_INFO(dev)->cursor_needs_physical) {
13602 int align = IS_I830(dev) ? 16 * 1024 : 256;
13603 ret = i915_gem_object_attach_phys(obj, align);
13604 if (ret)
13605 DRM_DEBUG_KMS("failed to attach phys object\n");
13606 } else {
7580d774 13607 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
6beb8c23 13608 }
465c120c 13609
7580d774
ML		 13610 if (ret == 0) {
13611 if (obj) {
13612 struct intel_plane_state *plane_state =
13613 to_intel_plane_state(new_state);
13614
13615 i915_gem_request_assign(&plane_state->wait_req,
13616 obj->last_write_req);
13617 }
13618
a9ff8714 13619 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774 13620 }
fdd508a6 13621
6beb8c23
MR		 13622 return ret;
13623}
13624
38f3ce3a
MR		 13625/**
13626 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13627 * @plane: drm plane to clean up for
13628 * @fb: old framebuffer that was on plane
13629 *
13630 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML		 13631 *
13632 * Must be called with struct_mutex held.
38f3ce3a
MR		 13633 */
13634void
13635intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13636 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13637{
13638 struct drm_device *dev = plane->dev;
1ee49399 13639 struct intel_plane *intel_plane = to_intel_plane(plane);
7580d774 13640 struct intel_plane_state *old_intel_state;
1ee49399
ML		 13641 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13642 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
38f3ce3a 13643
7580d774
ML		 13644 old_intel_state = to_intel_plane_state(old_state);
13645
1ee49399 13646 if (!obj && !old_obj)
38f3ce3a
MR		 13647 return;
13648
1ee49399
ML		 13649 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13650 !INTEL_INFO(dev)->cursor_needs_physical))
844f9111 13651 intel_unpin_fb_obj(old_state->fb, old_state);
1ee49399
ML		 13652
13653 /* prepare_fb aborted? */
13654 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13655 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13656 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774
ML		 13657
13658 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13659
465c120c
MR		 13660}
13661
6156a456
CK		 13662int
13663skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13664{
13665 int max_scale;
13666 struct drm_device *dev;
13667 struct drm_i915_private *dev_priv;
13668 int crtc_clock, cdclk;
13669
13670 if (!intel_crtc || !crtc_state)
13671 return DRM_PLANE_HELPER_NO_SCALING;
13672
13673 dev = intel_crtc->base.dev;
13674 dev_priv = dev->dev_private;
13675 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13676 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456 13677
54bf1ce6 13678 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
6156a456
CK		 13679 return DRM_PLANE_HELPER_NO_SCALING;
13680
13681 /*
13682 * skl max scale is lower of:
13683 * close to 3 but not 3, -1 is for that purpose
13684 * or
13685 * cdclk/crtc_clock
13686 */
13687 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13688
13689 return max_scale;
13690}
13691
465c120c 13692static int
3c692a41 13693intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13694 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13695 struct intel_plane_state *state)
13696{
2b875c22
MR		 13697 struct drm_crtc *crtc = state->base.crtc;
13698 struct drm_framebuffer *fb = state->base.fb;
6156a456 13699 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13700 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13701 bool can_position = false;
465c120c 13702
061e4b8d
ML		 13703 /* use scaler when colorkey is not required */
13704 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13705 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13706 min_scale = 1;
13707 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13708 can_position = true;
6156a456 13709 }
d8106366 13710
061e4b8d
ML		 13711 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13712 &state->dst, &state->clip,
da20eabd
ML		 13713 min_scale, max_scale,
13714 can_position, true,
13715 &state->visible);
14af293f
GP		 13716}
13717
13718static void
13719intel_commit_primary_plane(struct drm_plane *plane,
13720 struct intel_plane_state *state)
13721{
2b875c22
MR		 13722 struct drm_crtc *crtc = state->base.crtc;
13723 struct drm_framebuffer *fb = state->base.fb;
13724 struct drm_device *dev = plane->dev;
14af293f 13725 struct drm_i915_private *dev_priv = dev->dev_private;
14af293f 13726
ea2c67bb 13727 crtc = crtc ? crtc : plane->crtc;
ccc759dc 13728
d4b08630
ML		 13729 dev_priv->display.update_primary_plane(crtc, fb,
13730 state->src.x1 >> 16,
13731 state->src.y1 >> 16);
465c120c
MR		 13732}
13733
a8ad0d8e
ML		 13734static void
13735intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13736 struct drm_crtc *crtc)
a8ad0d8e
ML		 13737{
13738 struct drm_device *dev = plane->dev;
13739 struct drm_i915_private *dev_priv = dev->dev_private;
13740
a8ad0d8e
ML		 13741 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13742}
13743
613d2b27
ML		 13744static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13745 struct drm_crtc_state *old_crtc_state)
3c692a41 13746{
32b7eeec 13747 struct drm_device *dev = crtc->dev;
3c692a41 13748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13749 struct intel_crtc_state *old_intel_state =
13750 to_intel_crtc_state(old_crtc_state);
13751 bool modeset = needs_modeset(crtc->state);
3c692a41 13752
f015c551 13753 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13754 intel_update_watermarks(crtc);
3c692a41 13755
c34c9ee4 13756 /* Perform vblank evasion around commit operation */
62852622 13757 intel_pipe_update_start(intel_crtc);
0583236e 13758
bfd16b2a
ML		 13759 if (modeset)
13760 return;
13761
13762 if (to_intel_crtc_state(crtc->state)->update_pipe)
13763 intel_update_pipe_config(intel_crtc, old_intel_state);
13764 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13765 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13766}
13767
613d2b27
ML		 13768static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13769 struct drm_crtc_state *old_crtc_state)
32b7eeec 13770{
32b7eeec 13771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13772
62852622 13773 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13774}
13775
cf4c7c12 13776/**
4a3b8769
MR		 13777 * intel_plane_destroy - destroy a plane
13778 * @plane: plane to destroy
cf4c7c12 13779 *
4a3b8769
MR		 13780 * Common destruction function for all types of planes (primary, cursor,
13781 * sprite).
cf4c7c12 13782 */
4a3b8769 13783void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13784{
13785 struct intel_plane *intel_plane = to_intel_plane(plane);
13786 drm_plane_cleanup(plane);
13787 kfree(intel_plane);
13788}
13789
65a3fea0 13790const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13791 .update_plane = drm_atomic_helper_update_plane,
13792 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13793 .destroy = intel_plane_destroy,
c196e1d6 13794 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13795 .atomic_get_property = intel_plane_atomic_get_property,
13796 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13797 .atomic_duplicate_state = intel_plane_duplicate_state,
13798 .atomic_destroy_state = intel_plane_destroy_state,
13799
465c120c
MR		 13800};
13801
13802static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13803 int pipe)
13804{
13805 struct intel_plane *primary;
8e7d688b 13806 struct intel_plane_state *state;
465c120c 13807 const uint32_t *intel_primary_formats;
45e3743a 13808 unsigned int num_formats;
465c120c
MR		 13809
13810 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13811 if (primary == NULL)
13812 return NULL;
13813
8e7d688b
MR		 13814 state = intel_create_plane_state(&primary->base);
13815 if (!state) {
ea2c67bb
MR		 13816 kfree(primary);
13817 return NULL;
13818 }
8e7d688b 13819 primary->base.state = &state->base;
ea2c67bb 13820
465c120c
MR		 13821 primary->can_scale = false;
13822 primary->max_downscale = 1;
6156a456
CK		 13823 if (INTEL_INFO(dev)->gen >= 9) {
13824 primary->can_scale = true;
af99ceda 13825 state->scaler_id = -1;
6156a456 13826 }
465c120c
MR		 13827 primary->pipe = pipe;
13828 primary->plane = pipe;
a9ff8714 13829 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13830 primary->check_plane = intel_check_primary_plane;
13831 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13832 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13833 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13834 primary->plane = !pipe;
13835
6c0fd451
DL		 13836 if (INTEL_INFO(dev)->gen >= 9) {
13837 intel_primary_formats = skl_primary_formats;
13838 num_formats = ARRAY_SIZE(skl_primary_formats);
13839 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13840 intel_primary_formats = i965_primary_formats;
13841 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13842 } else {
13843 intel_primary_formats = i8xx_primary_formats;
13844 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13845 }
13846
13847 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13848 &intel_plane_funcs,
465c120c
MR		 13849 intel_primary_formats, num_formats,
13850 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13851
3b7a5119
SJ		 13852 if (INTEL_INFO(dev)->gen >= 4)
13853 intel_create_rotation_property(dev, primary);
48404c1e 13854
ea2c67bb
MR		 13855 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13856
465c120c
MR		 13857 return &primary->base;
13858}
13859
3b7a5119
SJ		 13860void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13861{
13862 if (!dev->mode_config.rotation_property) {
13863 unsigned long flags = BIT(DRM_ROTATE_0) |
13864 BIT(DRM_ROTATE_180);
13865
13866 if (INTEL_INFO(dev)->gen >= 9)
13867 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13868
13869 dev->mode_config.rotation_property =
13870 drm_mode_create_rotation_property(dev, flags);
13871 }
13872 if (dev->mode_config.rotation_property)
13873 drm_object_attach_property(&plane->base.base,
13874 dev->mode_config.rotation_property,
13875 plane->base.state->rotation);
13876}
13877
3d7d6510 13878static int
852e787c 13879intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13880 struct intel_crtc_state *crtc_state,
852e787c 13881 struct intel_plane_state *state)
3d7d6510 13882{
061e4b8d 13883 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13884 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13885 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13886 unsigned stride;
13887 int ret;
3d7d6510 13888
061e4b8d
ML		 13889 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13890 &state->dst, &state->clip,
3d7d6510
MR		 13891 DRM_PLANE_HELPER_NO_SCALING,
13892 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13893 true, true, &state->visible);
757f9a3e
GP		 13894 if (ret)
13895 return ret;
13896
757f9a3e
GP		 13897 /* if we want to turn off the cursor ignore width and height */
13898 if (!obj)
da20eabd 13899 return 0;
757f9a3e 13900
757f9a3e 13901 /* Check for which cursor types we support */
061e4b8d 13902 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13903 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13904 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13905 return -EINVAL;
13906 }
13907
ea2c67bb
MR		 13908 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13909 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13910 DRM_DEBUG_KMS("buffer is too small\n");
13911 return -ENOMEM;
13912 }
13913
3a656b54 13914 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13915 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13916 return -EINVAL;
32b7eeec
MR		 13917 }
13918
da20eabd 13919 return 0;
852e787c 13920}
3d7d6510 13921
a8ad0d8e
ML		 13922static void
13923intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13924 struct drm_crtc *crtc)
a8ad0d8e 13925{
a8ad0d8e
ML		 13926 intel_crtc_update_cursor(crtc, false);
13927}
13928
f4a2cf29 13929static void
852e787c
GP		 13930intel_commit_cursor_plane(struct drm_plane *plane,
13931 struct intel_plane_state *state)
13932{
2b875c22 13933 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13934 struct drm_device *dev = plane->dev;
13935 struct intel_crtc *intel_crtc;
2b875c22 13936 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13937 uint32_t addr;
852e787c 13938
ea2c67bb
MR		 13939 crtc = crtc ? crtc : plane->crtc;
13940 intel_crtc = to_intel_crtc(crtc);
13941
a912f12f
GP		 13942 if (intel_crtc->cursor_bo == obj)
13943 goto update;
4ed91096 13944
f4a2cf29 13945 if (!obj)
a912f12f 13946 addr = 0;
f4a2cf29 13947 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13948 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13949 else
a912f12f 13950 addr = obj->phys_handle->busaddr;
852e787c 13951
a912f12f
GP		 13952 intel_crtc->cursor_addr = addr;
13953 intel_crtc->cursor_bo = obj;
852e787c 13954
302d19ac 13955update:
62852622 13956 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13957}
13958
3d7d6510
MR		 13959static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13960 int pipe)
13961{
13962 struct intel_plane *cursor;
8e7d688b 13963 struct intel_plane_state *state;
3d7d6510
MR		 13964
13965 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13966 if (cursor == NULL)
13967 return NULL;
13968
8e7d688b
MR		 13969 state = intel_create_plane_state(&cursor->base);
13970 if (!state) {
ea2c67bb
MR		 13971 kfree(cursor);
13972 return NULL;
13973 }
8e7d688b 13974 cursor->base.state = &state->base;
ea2c67bb 13975
3d7d6510
MR		 13976 cursor->can_scale = false;
13977 cursor->max_downscale = 1;
13978 cursor->pipe = pipe;
13979 cursor->plane = pipe;
a9ff8714 13980 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13981 cursor->check_plane = intel_check_cursor_plane;
13982 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13983 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13984
13985 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13986 &intel_plane_funcs,
3d7d6510
MR		 13987 intel_cursor_formats,
13988 ARRAY_SIZE(intel_cursor_formats),
13989 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13990
13991 if (INTEL_INFO(dev)->gen >= 4) {
13992 if (!dev->mode_config.rotation_property)
13993 dev->mode_config.rotation_property =
13994 drm_mode_create_rotation_property(dev,
13995 BIT(DRM_ROTATE_0) |
13996 BIT(DRM_ROTATE_180));
13997 if (dev->mode_config.rotation_property)
13998 drm_object_attach_property(&cursor->base.base,
13999 dev->mode_config.rotation_property,
8e7d688b 14000 state->base.rotation);
4398ad45
VS		 14001 }
14002
af99ceda
CK		 14003 if (INTEL_INFO(dev)->gen >=9)
14004 state->scaler_id = -1;
14005
ea2c67bb
MR		 14006 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14007
3d7d6510
MR		 14008 return &cursor->base;
14009}
14010
549e2bfb
CK		 14011static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14012 struct intel_crtc_state *crtc_state)
14013{
14014 int i;
14015 struct intel_scaler *intel_scaler;
14016 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14017
14018 for (i = 0; i < intel_crtc->num_scalers; i++) {
14019 intel_scaler = &scaler_state->scalers[i];
14020 intel_scaler->in_use = 0;
549e2bfb
CK		 14021 intel_scaler->mode = PS_SCALER_MODE_DYN;
14022 }
14023
14024 scaler_state->scaler_id = -1;
14025}
14026
b358d0a6 14027static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14028{
fbee40df 14029 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14030 struct intel_crtc *intel_crtc;
f5de6e07 14031 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14032 struct drm_plane *primary = NULL;
14033 struct drm_plane *cursor = NULL;
465c120c 14034 int i, ret;
79e53945 14035
955382f3 14036 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14037 if (intel_crtc == NULL)
14038 return;
14039
f5de6e07
ACO		 14040 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14041 if (!crtc_state)
14042 goto fail;
550acefd
ACO		 14043 intel_crtc->config = crtc_state;
14044 intel_crtc->base.state = &crtc_state->base;
07878248 14045 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14046
549e2bfb
CK		 14047 /* initialize shared scalers */
14048 if (INTEL_INFO(dev)->gen >= 9) {
14049 if (pipe == PIPE_C)
14050 intel_crtc->num_scalers = 1;
14051 else
14052 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14053
14054 skl_init_scalers(dev, intel_crtc, crtc_state);
14055 }
14056
465c120c 14057 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14058 if (!primary)
14059 goto fail;
14060
14061 cursor = intel_cursor_plane_create(dev, pipe);
14062 if (!cursor)
14063 goto fail;
14064
465c120c 14065 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14066 cursor, &intel_crtc_funcs);
14067 if (ret)
14068 goto fail;
79e53945
JB		 14069
14070 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14071 for (i = 0; i < 256; i++) {
14072 intel_crtc->lut_r[i] = i;
14073 intel_crtc->lut_g[i] = i;
14074 intel_crtc->lut_b[i] = i;
14075 }
14076
1f1c2e24
VS		 14077 /*
14078 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14079 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14080 */
80824003
JB		 14081 intel_crtc->pipe = pipe;
14082 intel_crtc->plane = pipe;
3a77c4c4 14083 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14084 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14085 intel_crtc->plane = !pipe;
80824003
JB		 14086 }
14087
4b0e333e
CW		 14088 intel_crtc->cursor_base = ~0;
14089 intel_crtc->cursor_cntl = ~0;
dc41c154 14090 intel_crtc->cursor_size = ~0;
8d7849db 14091
852eb00d
VS		 14092 intel_crtc->wm.cxsr_allowed = true;
14093
22fd0fab
JB		 14094 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14095 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14096 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14097 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14098
79e53945 14099 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14100
14101 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14102 return;
14103
14104fail:
14105 if (primary)
14106 drm_plane_cleanup(primary);
14107 if (cursor)
14108 drm_plane_cleanup(cursor);
f5de6e07 14109 kfree(crtc_state);
3d7d6510 14110 kfree(intel_crtc);
79e53945
JB		 14111}
14112
752aa88a
JB		 14113enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14114{
14115 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14116 struct drm_device *dev = connector->base.dev;
752aa88a 14117
51fd371b 14118 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14119
d3babd3f 14120 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14121 return INVALID_PIPE;
14122
14123 return to_intel_crtc(encoder->crtc)->pipe;
14124}
14125
08d7b3d1 14126int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14127 struct drm_file *file)
08d7b3d1 14128{
08d7b3d1 14129 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14130 struct drm_crtc *drmmode_crtc;
c05422d5 14131 struct intel_crtc *crtc;
08d7b3d1 14132
7707e653 14133 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14134
7707e653 14135 if (!drmmode_crtc) {
08d7b3d1 14136 DRM_ERROR("no such CRTC id\n");
3f2c2057 14137 return -ENOENT;
08d7b3d1
CW		 14138 }
14139
7707e653 14140 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14141 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14142
c05422d5 14143 return 0;
08d7b3d1
CW		 14144}
14145
66a9278e 14146static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14147{
66a9278e
DV		 14148 struct drm_device *dev = encoder->base.dev;
14149 struct intel_encoder *source_encoder;
79e53945 14150 int index_mask = 0;
79e53945
JB		 14151 int entry = 0;
14152
b2784e15 14153 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14154 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14155 index_mask |= (1 << entry);
14156
79e53945
JB		 14157 entry++;
14158 }
4ef69c7a 14159
79e53945
JB		 14160 return index_mask;
14161}
14162
4d302442
CW		 14163static bool has_edp_a(struct drm_device *dev)
14164{
14165 struct drm_i915_private *dev_priv = dev->dev_private;
14166
14167 if (!IS_MOBILE(dev))
14168 return false;
14169
14170 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14171 return false;
14172
e3589908 14173 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14174 return false;
14175
14176 return true;
14177}
14178
84b4e042
JB		 14179static bool intel_crt_present(struct drm_device *dev)
14180{
14181 struct drm_i915_private *dev_priv = dev->dev_private;
14182
884497ed
DL		 14183 if (INTEL_INFO(dev)->gen >= 9)
14184 return false;
14185
cf404ce4 14186 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14187 return false;
14188
14189 if (IS_CHERRYVIEW(dev))
14190 return false;
14191
14192 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14193 return false;
14194
14195 return true;
14196}
14197
79e53945
JB		 14198static void intel_setup_outputs(struct drm_device *dev)
14199{
725e30ad 14200 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14201 struct intel_encoder *encoder;
cb0953d7 14202 bool dpd_is_edp = false;
79e53945 14203
c9093354 14204 intel_lvds_init(dev);
79e53945 14205
84b4e042 14206 if (intel_crt_present(dev))
79935fca 14207 intel_crt_init(dev);
cb0953d7 14208
c776eb2e
VK		 14209 if (IS_BROXTON(dev)) {
14210 /*
14211 * FIXME: Broxton doesn't support port detection via the
14212 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14213 * detect the ports.
14214 */
14215 intel_ddi_init(dev, PORT_A);
14216 intel_ddi_init(dev, PORT_B);
14217 intel_ddi_init(dev, PORT_C);
14218 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14219 int found;
14220
de31facd
JB		 14221 /*
14222 * Haswell uses DDI functions to detect digital outputs.
14223 * On SKL pre-D0 the strap isn't connected, so we assume
14224 * it's there.
14225 */
77179400 14226 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14227 /* WaIgnoreDDIAStrap: skl */
ef11bdb3 14228 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
0e72a5b5
ED		 14229 intel_ddi_init(dev, PORT_A);
14230
14231 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14232 * register */
14233 found = I915_READ(SFUSE_STRAP);
14234
14235 if (found & SFUSE_STRAP_DDIB_DETECTED)
14236 intel_ddi_init(dev, PORT_B);
14237 if (found & SFUSE_STRAP_DDIC_DETECTED)
14238 intel_ddi_init(dev, PORT_C);
14239 if (found & SFUSE_STRAP_DDID_DETECTED)
14240 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14241 /*
14242 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14243 */
ef11bdb3 14244 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
2800e4c2
RV		 14245 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14246 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14247 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14248 intel_ddi_init(dev, PORT_E);
14249
0e72a5b5 14250 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14251 int found;
5d8a7752 14252 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14253
14254 if (has_edp_a(dev))
14255 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14256
dc0fa718 14257 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14258 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14259 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14260 if (!found)
e2debe91 14261 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14262 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14263 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14264 }
14265
dc0fa718 14266 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14267 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14268
dc0fa718 14269 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14270 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14271
5eb08b69 14272 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14273 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14274
270b3042 14275 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14276 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14277 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14278 /*
14279 * The DP_DETECTED bit is the latched state of the DDC
14280 * SDA pin at boot. However since eDP doesn't require DDC
14281 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14282 * eDP ports may have been muxed to an alternate function.
14283 * Thus we can't rely on the DP_DETECTED bit alone to detect
14284 * eDP ports. Consult the VBT as well as DP_DETECTED to
14285 * detect eDP ports.
14286 */
e66eb81d 14287 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14288 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14289 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14290 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14291 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14292 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14293
e66eb81d 14294 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14295 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14296 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14297 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14298 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14299 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14300
9418c1f1 14301 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14302 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14303 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14304 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14305 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14306 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14307 }
14308
3cfca973 14309 intel_dsi_init(dev);
09da55dc 14310 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14311 bool found = false;
7d57382e 14312
e2debe91 14313 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14314 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14315 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14316 if (!found && IS_G4X(dev)) {
b01f2c3a 14317 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14318 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14319 }
27185ae1 14320
3fec3d2f 14321 if (!found && IS_G4X(dev))
ab9d7c30 14322 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14323 }
13520b05
KH		 14324
14325 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14326
e2debe91 14327 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14328 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14329 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14330 }
27185ae1 14331
e2debe91 14332 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14333
3fec3d2f 14334 if (IS_G4X(dev)) {
b01f2c3a 14335 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14336 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14337 }
3fec3d2f 14338 if (IS_G4X(dev))
ab9d7c30 14339 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14340 }
27185ae1 14341
3fec3d2f 14342 if (IS_G4X(dev) &&
e7281eab 14343 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14344 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14345 } else if (IS_GEN2(dev))
79e53945
JB		 14346 intel_dvo_init(dev);
14347
103a196f 14348 if (SUPPORTS_TV(dev))
79e53945
JB		 14349 intel_tv_init(dev);
14350
0bc12bcb 14351 intel_psr_init(dev);
7c8f8a70 14352
b2784e15 14353 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14354 encoder->base.possible_crtcs = encoder->crtc_mask;
14355 encoder->base.possible_clones =
66a9278e 14356 intel_encoder_clones(encoder);
79e53945 14357 }
47356eb6 14358
dde86e2d 14359 intel_init_pch_refclk(dev);
270b3042
DV		 14360
14361 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14362}
14363
14364static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14365{
60a5ca01 14366 struct drm_device *dev = fb->dev;
79e53945 14367 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14368
ef2d633e 14369 drm_framebuffer_cleanup(fb);
60a5ca01 14370 mutex_lock(&dev->struct_mutex);
ef2d633e 14371 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14372 drm_gem_object_unreference(&intel_fb->obj->base);
14373 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14374 kfree(intel_fb);
14375}
14376
14377static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14378 struct drm_file *file,
79e53945
JB		 14379 unsigned int *handle)
14380{
14381 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14382 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14383
05394f39 14384 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14385}
14386
86c98588
RV		 14387static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14388 struct drm_file *file,
14389 unsigned flags, unsigned color,
14390 struct drm_clip_rect *clips,
14391 unsigned num_clips)
14392{
14393 struct drm_device *dev = fb->dev;
14394 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14395 struct drm_i915_gem_object *obj = intel_fb->obj;
14396
14397 mutex_lock(&dev->struct_mutex);
74b4ea1e 14398 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14399 mutex_unlock(&dev->struct_mutex);
14400
14401 return 0;
14402}
14403
79e53945
JB		 14404static const struct drm_framebuffer_funcs intel_fb_funcs = {
14405 .destroy = intel_user_framebuffer_destroy,
14406 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14407 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14408};
14409
b321803d
DL		 14410static
14411u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14412 uint32_t pixel_format)
14413{
14414 u32 gen = INTEL_INFO(dev)->gen;
14415
14416 if (gen >= 9) {
14417 /* "The stride in bytes must not exceed the of the size of 8K
14418 * pixels and 32K bytes."
14419 */
14420 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14421 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14422 return 32*1024;
14423 } else if (gen >= 4) {
14424 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14425 return 16*1024;
14426 else
14427 return 32*1024;
14428 } else if (gen >= 3) {
14429 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14430 return 8*1024;
14431 else
14432 return 16*1024;
14433 } else {
14434 /* XXX DSPC is limited to 4k tiled */
14435 return 8*1024;
14436 }
14437}
14438
b5ea642a
DV		 14439static int intel_framebuffer_init(struct drm_device *dev,
14440 struct intel_framebuffer *intel_fb,
14441 struct drm_mode_fb_cmd2 *mode_cmd,
14442 struct drm_i915_gem_object *obj)
79e53945 14443{
6761dd31 14444 unsigned int aligned_height;
79e53945 14445 int ret;
b321803d 14446 u32 pitch_limit, stride_alignment;
79e53945 14447
dd4916c5
DV		 14448 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14449
2a80eada
DV		 14450 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14451 /* Enforce that fb modifier and tiling mode match, but only for
14452 * X-tiled. This is needed for FBC. */
14453 if (!!(obj->tiling_mode == I915_TILING_X) !=
14454 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14455 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14456 return -EINVAL;
14457 }
14458 } else {
14459 if (obj->tiling_mode == I915_TILING_X)
14460 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14461 else if (obj->tiling_mode == I915_TILING_Y) {
14462 DRM_DEBUG("No Y tiling for legacy addfb\n");
14463 return -EINVAL;
14464 }
14465 }
14466
9a8f0a12
TU		 14467 /* Passed in modifier sanity checking. */
14468 switch (mode_cmd->modifier[0]) {
14469 case I915_FORMAT_MOD_Y_TILED:
14470 case I915_FORMAT_MOD_Yf_TILED:
14471 if (INTEL_INFO(dev)->gen < 9) {
14472 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14473 mode_cmd->modifier[0]);
14474 return -EINVAL;
14475 }
14476 case DRM_FORMAT_MOD_NONE:
14477 case I915_FORMAT_MOD_X_TILED:
14478 break;
14479 default:
c0f40428
JB		 14480 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14481 mode_cmd->modifier[0]);
57cd6508 14482 return -EINVAL;
c16ed4be 14483 }
57cd6508 14484
b321803d
DL		 14485 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14486 mode_cmd->pixel_format);
14487 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14488 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14489 mode_cmd->pitches[0], stride_alignment);
57cd6508 14490 return -EINVAL;
c16ed4be 14491 }
57cd6508 14492
b321803d
DL		 14493 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14494 mode_cmd->pixel_format);
a35cdaa0 14495 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14496 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14497 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14498 "tiled" : "linear",
a35cdaa0 14499 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14500 return -EINVAL;
c16ed4be 14501 }
5d7bd705 14502
2a80eada 14503 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14504 mode_cmd->pitches[0] != obj->stride) {
14505 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14506 mode_cmd->pitches[0], obj->stride);
5d7bd705 14507 return -EINVAL;
c16ed4be 14508 }
5d7bd705 14509
57779d06 14510 /* Reject formats not supported by any plane early. */
308e5bcb 14511 switch (mode_cmd->pixel_format) {
57779d06 14512 case DRM_FORMAT_C8:
04b3924d
VS		 14513 case DRM_FORMAT_RGB565:
14514 case DRM_FORMAT_XRGB8888:
14515 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14516 break;
14517 case DRM_FORMAT_XRGB1555:
c16ed4be 14518 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14519 DRM_DEBUG("unsupported pixel format: %s\n",
14520 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14521 return -EINVAL;
c16ed4be 14522 }
57779d06 14523 break;
57779d06 14524 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14525 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14526 DRM_DEBUG("unsupported pixel format: %s\n",
14527 drm_get_format_name(mode_cmd->pixel_format));
14528 return -EINVAL;
14529 }
14530 break;
14531 case DRM_FORMAT_XBGR8888:
04b3924d 14532 case DRM_FORMAT_XRGB2101010:
57779d06 14533 case DRM_FORMAT_XBGR2101010:
c16ed4be 14534 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14535 DRM_DEBUG("unsupported pixel format: %s\n",
14536 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14537 return -EINVAL;
c16ed4be 14538 }
b5626747 14539 break;
7531208b
DL		 14540 case DRM_FORMAT_ABGR2101010:
14541 if (!IS_VALLEYVIEW(dev)) {
14542 DRM_DEBUG("unsupported pixel format: %s\n",
14543 drm_get_format_name(mode_cmd->pixel_format));
14544 return -EINVAL;
14545 }
14546 break;
04b3924d
VS		 14547 case DRM_FORMAT_YUYV:
14548 case DRM_FORMAT_UYVY:
14549 case DRM_FORMAT_YVYU:
14550 case DRM_FORMAT_VYUY:
c16ed4be 14551 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14552 DRM_DEBUG("unsupported pixel format: %s\n",
14553 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14554 return -EINVAL;
c16ed4be 14555 }
57cd6508
CW		 14556 break;
14557 default:
4ee62c76
VS		 14558 DRM_DEBUG("unsupported pixel format: %s\n",
14559 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14560 return -EINVAL;
14561 }
14562
90f9a336
VS		 14563 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14564 if (mode_cmd->offsets[0] != 0)
14565 return -EINVAL;
14566
ec2c981e 14567 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14568 mode_cmd->pixel_format,
14569 mode_cmd->modifier[0]);
53155c0a
DV		 14570 /* FIXME drm helper for size checks (especially planar formats)? */
14571 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14572 return -EINVAL;
14573
c7d73f6a
DV		 14574 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14575 intel_fb->obj = obj;
80075d49 14576 intel_fb->obj->framebuffer_references++;
c7d73f6a 14577
79e53945
JB		 14578 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14579 if (ret) {
14580 DRM_ERROR("framebuffer init failed %d\n", ret);
14581 return ret;
14582 }
14583
79e53945
JB		 14584 return 0;
14585}
14586
79e53945
JB		 14587static struct drm_framebuffer *
14588intel_user_framebuffer_create(struct drm_device *dev,
14589 struct drm_file *filp,
308e5bcb 14590 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14591{
dcb1394e 14592 struct drm_framebuffer *fb;
05394f39 14593 struct drm_i915_gem_object *obj;
79e53945 14594
308e5bcb
JB		 14595 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14596 mode_cmd->handles[0]));
c8725226 14597 if (&obj->base == NULL)
cce13ff7 14598 return ERR_PTR(-ENOENT);
79e53945 14599
dcb1394e
LW		 14600 fb = intel_framebuffer_create(dev, mode_cmd, obj);
14601 if (IS_ERR(fb))
14602 drm_gem_object_unreference_unlocked(&obj->base);
14603
14604 return fb;
79e53945
JB		 14605}
14606
0695726e 14607#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14608static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14609{
14610}
14611#endif
14612
79e53945 14613static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14614 .fb_create = intel_user_framebuffer_create,
0632fef6 14615 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14616 .atomic_check = intel_atomic_check,
14617 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14618 .atomic_state_alloc = intel_atomic_state_alloc,
14619 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14620};
14621
e70236a8
JB		 14622/* Set up chip specific display functions */
14623static void intel_init_display(struct drm_device *dev)
14624{
14625 struct drm_i915_private *dev_priv = dev->dev_private;
14626
ee9300bb
DV		 14627 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14628 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14629 else if (IS_CHERRYVIEW(dev))
14630 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14631 else if (IS_VALLEYVIEW(dev))
14632 dev_priv->display.find_dpll = vlv_find_best_dpll;
14633 else if (IS_PINEVIEW(dev))
14634 dev_priv->display.find_dpll = pnv_find_best_dpll;
14635 else
14636 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14637
bc8d7dff
DL		 14638 if (INTEL_INFO(dev)->gen >= 9) {
14639 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14640 dev_priv->display.get_initial_plane_config =
14641 skylake_get_initial_plane_config;
bc8d7dff
DL		 14642 dev_priv->display.crtc_compute_clock =
14643 haswell_crtc_compute_clock;
14644 dev_priv->display.crtc_enable = haswell_crtc_enable;
14645 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14646 dev_priv->display.update_primary_plane =
14647 skylake_update_primary_plane;
14648 } else if (HAS_DDI(dev)) {
0e8ffe1b 14649 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14650 dev_priv->display.get_initial_plane_config =
14651 ironlake_get_initial_plane_config;
797d0259
ACO		 14652 dev_priv->display.crtc_compute_clock =
14653 haswell_crtc_compute_clock;
4f771f10
PZ		 14654 dev_priv->display.crtc_enable = haswell_crtc_enable;
14655 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14656 dev_priv->display.update_primary_plane =
14657 ironlake_update_primary_plane;
09b4ddf9 14658 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14659 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14660 dev_priv->display.get_initial_plane_config =
14661 ironlake_get_initial_plane_config;
3fb37703
ACO		 14662 dev_priv->display.crtc_compute_clock =
14663 ironlake_crtc_compute_clock;
76e5a89c
DV		 14664 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14665 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14666 dev_priv->display.update_primary_plane =
14667 ironlake_update_primary_plane;
89b667f8
JB		 14668 } else if (IS_VALLEYVIEW(dev)) {
14669 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14670 dev_priv->display.get_initial_plane_config =
14671 i9xx_get_initial_plane_config;
d6dfee7a 14672 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14673 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14674 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14675 dev_priv->display.update_primary_plane =
14676 i9xx_update_primary_plane;
f564048e 14677 } else {
0e8ffe1b 14678 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14679 dev_priv->display.get_initial_plane_config =
14680 i9xx_get_initial_plane_config;
d6dfee7a 14681 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14682 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14683 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14684 dev_priv->display.update_primary_plane =
14685 i9xx_update_primary_plane;
f564048e 14686 }
e70236a8 14687
e70236a8 14688 /* Returns the core display clock speed */
ef11bdb3 14689 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1652d19e
VS		 14690 dev_priv->display.get_display_clock_speed =
14691 skylake_get_display_clock_speed;
acd3f3d3
BP		 14692 else if (IS_BROXTON(dev))
14693 dev_priv->display.get_display_clock_speed =
14694 broxton_get_display_clock_speed;
1652d19e
VS		 14695 else if (IS_BROADWELL(dev))
14696 dev_priv->display.get_display_clock_speed =
14697 broadwell_get_display_clock_speed;
14698 else if (IS_HASWELL(dev))
14699 dev_priv->display.get_display_clock_speed =
14700 haswell_get_display_clock_speed;
14701 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14702 dev_priv->display.get_display_clock_speed =
14703 valleyview_get_display_clock_speed;
b37a6434
VS		 14704 else if (IS_GEN5(dev))
14705 dev_priv->display.get_display_clock_speed =
14706 ilk_get_display_clock_speed;
a7c66cd8 14707 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14708 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14709 dev_priv->display.get_display_clock_speed =
14710 i945_get_display_clock_speed;
34edce2f
VS		 14711 else if (IS_GM45(dev))
14712 dev_priv->display.get_display_clock_speed =
14713 gm45_get_display_clock_speed;
14714 else if (IS_CRESTLINE(dev))
14715 dev_priv->display.get_display_clock_speed =
14716 i965gm_get_display_clock_speed;
14717 else if (IS_PINEVIEW(dev))
14718 dev_priv->display.get_display_clock_speed =
14719 pnv_get_display_clock_speed;
14720 else if (IS_G33(dev) || IS_G4X(dev))
14721 dev_priv->display.get_display_clock_speed =
14722 g33_get_display_clock_speed;
e70236a8
JB		 14723 else if (IS_I915G(dev))
14724 dev_priv->display.get_display_clock_speed =
14725 i915_get_display_clock_speed;
257a7ffc 14726 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14727 dev_priv->display.get_display_clock_speed =
14728 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14729 else if (IS_PINEVIEW(dev))
14730 dev_priv->display.get_display_clock_speed =
14731 pnv_get_display_clock_speed;
e70236a8
JB		 14732 else if (IS_I915GM(dev))
14733 dev_priv->display.get_display_clock_speed =
14734 i915gm_get_display_clock_speed;
14735 else if (IS_I865G(dev))
14736 dev_priv->display.get_display_clock_speed =
14737 i865_get_display_clock_speed;
f0f8a9ce 14738 else if (IS_I85X(dev))
e70236a8 14739 dev_priv->display.get_display_clock_speed =
1b1d2716 14740 i85x_get_display_clock_speed;
623e01e5
VS		 14741 else { /* 830 */
14742 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14743 dev_priv->display.get_display_clock_speed =
14744 i830_get_display_clock_speed;
623e01e5 14745 }
e70236a8 14746
7c10a2b5 14747 if (IS_GEN5(dev)) {
3bb11b53 14748 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14749 } else if (IS_GEN6(dev)) {
14750 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14751 } else if (IS_IVYBRIDGE(dev)) {
14752 /* FIXME: detect B0+ stepping and use auto training */
14753 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14754 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14755 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14756 if (IS_BROADWELL(dev)) {
14757 dev_priv->display.modeset_commit_cdclk =
14758 broadwell_modeset_commit_cdclk;
14759 dev_priv->display.modeset_calc_cdclk =
14760 broadwell_modeset_calc_cdclk;
14761 }
30a970c6 14762 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14763 dev_priv->display.modeset_commit_cdclk =
14764 valleyview_modeset_commit_cdclk;
14765 dev_priv->display.modeset_calc_cdclk =
14766 valleyview_modeset_calc_cdclk;
f8437dd1 14767 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14768 dev_priv->display.modeset_commit_cdclk =
14769 broxton_modeset_commit_cdclk;
14770 dev_priv->display.modeset_calc_cdclk =
14771 broxton_modeset_calc_cdclk;
e70236a8 14772 }
8c9f3aaf 14773
8c9f3aaf
JB		 14774 switch (INTEL_INFO(dev)->gen) {
14775 case 2:
14776 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14777 break;
14778
14779 case 3:
14780 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14781 break;
14782
14783 case 4:
14784 case 5:
14785 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14786 break;
14787
14788 case 6:
14789 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14790 break;
7c9017e5 14791 case 7:
4e0bbc31 14792 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14793 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14794 break;
830c81db 14795 case 9:
ba343e02
TU		 14796 /* Drop through - unsupported since execlist only. */
14797 default:
14798 /* Default just returns -ENODEV to indicate unsupported */
14799 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14800 }
7bd688cd 14801
e39b999a 14802 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14803}
14804
b690e96c
JB		 14805/*
14806 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14807 * resume, or other times. This quirk makes sure that's the case for
14808 * affected systems.
14809 */
0206e353 14810static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14811{
14812 struct drm_i915_private *dev_priv = dev->dev_private;
14813
14814 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14815 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14816}
14817
b6b5d049
VS		 14818static void quirk_pipeb_force(struct drm_device *dev)
14819{
14820 struct drm_i915_private *dev_priv = dev->dev_private;
14821
14822 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14823 DRM_INFO("applying pipe b force quirk\n");
14824}
14825
435793df
KP		 14826/*
14827 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14828 */
14829static void quirk_ssc_force_disable(struct drm_device *dev)
14830{
14831 struct drm_i915_private *dev_priv = dev->dev_private;
14832 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14833 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14834}
14835
4dca20ef 14836/*
5a15ab5b
CE		 14837 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14838 * brightness value
4dca20ef
CE		 14839 */
14840static void quirk_invert_brightness(struct drm_device *dev)
14841{
14842 struct drm_i915_private *dev_priv = dev->dev_private;
14843 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14844 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14845}
14846
9c72cc6f
SD		 14847/* Some VBT's incorrectly indicate no backlight is present */
14848static void quirk_backlight_present(struct drm_device *dev)
14849{
14850 struct drm_i915_private *dev_priv = dev->dev_private;
14851 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14852 DRM_INFO("applying backlight present quirk\n");
14853}
14854
b690e96c
JB		 14855struct intel_quirk {
14856 int device;
14857 int subsystem_vendor;
14858 int subsystem_device;
14859 void (*hook)(struct drm_device *dev);
14860};
14861
5f85f176
EE		 14862/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14863struct intel_dmi_quirk {
14864 void (*hook)(struct drm_device *dev);
14865 const struct dmi_system_id (*dmi_id_list)[];
14866};
14867
14868static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14869{
14870 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14871 return 1;
14872}
14873
14874static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14875 {
14876 .dmi_id_list = &(const struct dmi_system_id[]) {
14877 {
14878 .callback = intel_dmi_reverse_brightness,
14879 .ident = "NCR Corporation",
14880 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14881 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14882 },
14883 },
14884 { } /* terminating entry */
14885 },
14886 .hook = quirk_invert_brightness,
14887 },
14888};
14889
c43b5634 14890static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14891 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14892 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14893
b690e96c
JB		 14894 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14895 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14896
5f080c0f
VS		 14897 /* 830 needs to leave pipe A & dpll A up */
14898 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14899
b6b5d049
VS		 14900 /* 830 needs to leave pipe B & dpll B up */
14901 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14902
435793df
KP		 14903 /* Lenovo U160 cannot use SSC on LVDS */
14904 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14905
14906 /* Sony Vaio Y cannot use SSC on LVDS */
14907 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14908
be505f64
AH		 14909 /* Acer Aspire 5734Z must invert backlight brightness */
14910 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14911
14912 /* Acer/eMachines G725 */
14913 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14914
14915 /* Acer/eMachines e725 */
14916 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14917
14918 /* Acer/Packard Bell NCL20 */
14919 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14920
14921 /* Acer Aspire 4736Z */
14922 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14923
14924 /* Acer Aspire 5336 */
14925 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14926
14927 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14928 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14929
dfb3d47b
SD		 14930 /* Acer C720 Chromebook (Core i3 4005U) */
14931 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14932
b2a9601c 14933 /* Apple Macbook 2,1 (Core 2 T7400) */
14934 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14935
d4967d8c
SD		 14936 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14937 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14938
14939 /* HP Chromebook 14 (Celeron 2955U) */
14940 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14941
14942 /* Dell Chromebook 11 */
14943 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14944};
14945
14946static void intel_init_quirks(struct drm_device *dev)
14947{
14948 struct pci_dev *d = dev->pdev;
14949 int i;
14950
14951 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14952 struct intel_quirk *q = &intel_quirks[i];
14953
14954 if (d->device == q->device &&
14955 (d->subsystem_vendor == q->subsystem_vendor ||
14956 q->subsystem_vendor == PCI_ANY_ID) &&
14957 (d->subsystem_device == q->subsystem_device ||
14958 q->subsystem_device == PCI_ANY_ID))
14959 q->hook(dev);
14960 }
5f85f176
EE		 14961 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14962 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14963 intel_dmi_quirks[i].hook(dev);
14964 }
b690e96c
JB		 14965}
14966
9cce37f4
JB		 14967/* Disable the VGA plane that we never use */
14968static void i915_disable_vga(struct drm_device *dev)
14969{
14970 struct drm_i915_private *dev_priv = dev->dev_private;
14971 u8 sr1;
766aa1c4 14972 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14973
2b37c616 14974 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14975 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14976 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14977 sr1 = inb(VGA_SR_DATA);
14978 outb(sr1 | 1<<5, VGA_SR_DATA);
14979 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14980 udelay(300);
14981
01f5a626 14982 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14983 POSTING_READ(vga_reg);
14984}
14985
f817586c
DV		 14986void intel_modeset_init_hw(struct drm_device *dev)
14987{
b6283055 14988 intel_update_cdclk(dev);
a8f78b58 14989 intel_prepare_ddi(dev);
f817586c 14990 intel_init_clock_gating(dev);
8090c6b9 14991 intel_enable_gt_powersave(dev);
f817586c
DV		 14992}
14993
79e53945
JB		 14994void intel_modeset_init(struct drm_device *dev)
14995{
652c393a 14996 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14997 int sprite, ret;
8cc87b75 14998 enum pipe pipe;
46f297fb 14999 struct intel_crtc *crtc;
79e53945
JB		 15000
15001 drm_mode_config_init(dev);
15002
15003 dev->mode_config.min_width = 0;
15004 dev->mode_config.min_height = 0;
15005
019d96cb
DA		 15006 dev->mode_config.preferred_depth = 24;
15007 dev->mode_config.prefer_shadow = 1;
15008
25bab385
TU		 15009 dev->mode_config.allow_fb_modifiers = true;
15010
e6ecefaa 15011 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15012
b690e96c
JB		 15013 intel_init_quirks(dev);
15014
1fa61106
ED		 15015 intel_init_pm(dev);
15016
e3c74757
BW		 15017 if (INTEL_INFO(dev)->num_pipes == 0)
15018 return;
15019
69f92f67
LW		 15020 /*
15021 * There may be no VBT; and if the BIOS enabled SSC we can
15022 * just keep using it to avoid unnecessary flicker. Whereas if the
15023 * BIOS isn't using it, don't assume it will work even if the VBT
15024 * indicates as much.
15025 */
15026 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15027 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15028 DREF_SSC1_ENABLE);
15029
15030 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15031 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15032 bios_lvds_use_ssc ? "en" : "dis",
15033 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15034 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15035 }
15036 }
15037
e70236a8 15038 intel_init_display(dev);
7c10a2b5 15039 intel_init_audio(dev);
e70236a8 15040
a6c45cf0
CW		 15041 if (IS_GEN2(dev)) {
15042 dev->mode_config.max_width = 2048;
15043 dev->mode_config.max_height = 2048;
15044 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15045 dev->mode_config.max_width = 4096;
15046 dev->mode_config.max_height = 4096;
79e53945 15047 } else {
a6c45cf0
CW		 15048 dev->mode_config.max_width = 8192;
15049 dev->mode_config.max_height = 8192;
79e53945 15050 }
068be561 15051
dc41c154
VS		 15052 if (IS_845G(dev) || IS_I865G(dev)) {
15053 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15054 dev->mode_config.cursor_height = 1023;
15055 } else if (IS_GEN2(dev)) {
068be561
DL		 15056 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15057 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15058 } else {
15059 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15060 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15061 }
15062
5d4545ae 15063 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15064
28c97730 15065 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15066 INTEL_INFO(dev)->num_pipes,
15067 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15068
055e393f 15069 for_each_pipe(dev_priv, pipe) {
8cc87b75 15070 intel_crtc_init(dev, pipe);
3bdcfc0c 15071 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15072 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15073 if (ret)
06da8da2 15074 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15075 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15076 }
79e53945
JB		 15077 }
15078
bfa7df01
VS		 15079 intel_update_czclk(dev_priv);
15080 intel_update_cdclk(dev);
15081
e72f9fbf 15082 intel_shared_dpll_init(dev);
ee7b9f93 15083
9cce37f4
JB		 15084 /* Just disable it once at startup */
15085 i915_disable_vga(dev);
79e53945 15086 intel_setup_outputs(dev);
11be49eb 15087
6e9f798d 15088 drm_modeset_lock_all(dev);
043e9bda 15089 intel_modeset_setup_hw_state(dev);
6e9f798d 15090 drm_modeset_unlock_all(dev);
46f297fb 15091
d3fcc808 15092 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 15093 struct intel_initial_plane_config plane_config = {};
15094
46f297fb
JB		 15095 if (!crtc->active)
15096 continue;
15097
46f297fb 15098 /*
46f297fb
JB		 15099 * Note that reserving the BIOS fb up front prevents us
15100 * from stuffing other stolen allocations like the ring
15101 * on top. This prevents some ugliness at boot time, and
15102 * can even allow for smooth boot transitions if the BIOS
15103 * fb is large enough for the active pipe configuration.
15104 */
eeebeac5
ML		 15105 dev_priv->display.get_initial_plane_config(crtc,
15106 &plane_config);
15107
15108 /*
15109 * If the fb is shared between multiple heads, we'll
15110 * just get the first one.
15111 */
15112 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15113 }
2c7111db
CW		 15114}
15115
7fad798e
DV		 15116static void intel_enable_pipe_a(struct drm_device *dev)
15117{
15118 struct intel_connector *connector;
15119 struct drm_connector *crt = NULL;
15120 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15121 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15122
15123 /* We can't just switch on the pipe A, we need to set things up with a
15124 * proper mode and output configuration. As a gross hack, enable pipe A
15125 * by enabling the load detect pipe once. */
3a3371ff 15126 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15127 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15128 crt = &connector->base;
15129 break;
15130 }
15131 }
15132
15133 if (!crt)
15134 return;
15135
208bf9fd 15136 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15137 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15138}
15139
fa555837
DV		 15140static bool
15141intel_check_plane_mapping(struct intel_crtc *crtc)
15142{
7eb552ae
BW		 15143 struct drm_device *dev = crtc->base.dev;
15144 struct drm_i915_private *dev_priv = dev->dev_private;
649636ef 15145 u32 val;
fa555837 15146
7eb552ae 15147 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15148 return true;
15149
649636ef 15150 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV		 15151
15152 if ((val & DISPLAY_PLANE_ENABLE) &&
15153 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15154 return false;
15155
15156 return true;
15157}
15158
02e93c35
VS		 15159static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15160{
15161 struct drm_device *dev = crtc->base.dev;
15162 struct intel_encoder *encoder;
15163
15164 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15165 return true;
15166
15167 return false;
15168}
15169
24929352
DV		 15170static void intel_sanitize_crtc(struct intel_crtc *crtc)
15171{
15172 struct drm_device *dev = crtc->base.dev;
15173 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15174 u32 reg;
24929352 15175
24929352 15176 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15177 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15178 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15179
d3eaf884 15180 /* restore vblank interrupts to correct state */
9625604c 15181 drm_crtc_vblank_reset(&crtc->base);
d297e103 15182 if (crtc->active) {
f9cd7b88
VS		 15183 struct intel_plane *plane;
15184
9625604c 15185 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 15186
15187 /* Disable everything but the primary plane */
15188 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15189 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15190 continue;
15191
15192 plane->disable_plane(&plane->base, &crtc->base);
15193 }
9625604c 15194 }
d3eaf884 15195
24929352 15196 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15197 * disable the crtc (and hence change the state) if it is wrong. Note
15198 * that gen4+ has a fixed plane -> pipe mapping. */
15199 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15200 bool plane;
15201
24929352
DV		 15202 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15203 crtc->base.base.id);
15204
15205 /* Pipe has the wrong plane attached and the plane is active.
15206 * Temporarily change the plane mapping and disable everything
15207 * ... */
15208 plane = crtc->plane;
b70709a6 15209 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15210 crtc->plane = !plane;
b17d48e2 15211 intel_crtc_disable_noatomic(&crtc->base);
24929352 15212 crtc->plane = plane;
24929352 15213 }
24929352 15214
7fad798e
DV		 15215 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15216 crtc->pipe == PIPE_A && !crtc->active) {
15217 /* BIOS forgot to enable pipe A, this mostly happens after
15218 * resume. Force-enable the pipe to fix this, the update_dpms
15219 * call below we restore the pipe to the right state, but leave
15220 * the required bits on. */
15221 intel_enable_pipe_a(dev);
15222 }
15223
24929352
DV		 15224 /* Adjust the state of the output pipe according to whether we
15225 * have active connectors/encoders. */
02e93c35 15226 if (!intel_crtc_has_encoders(crtc))
b17d48e2 15227 intel_crtc_disable_noatomic(&crtc->base);
24929352 15228
53d9f4e9 15229 if (crtc->active != crtc->base.state->active) {
02e93c35 15230 struct intel_encoder *encoder;
24929352
DV		 15231
15232 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15233 * functions or because of calls to intel_crtc_disable_noatomic,
15234 * or because the pipe is force-enabled due to the
24929352
DV		 15235 * pipe A quirk. */
15236 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15237 crtc->base.base.id,
83d65738 15238 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15239 crtc->active ? "enabled" : "disabled");
15240
4be40c98 15241 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15242 crtc->base.state->active = crtc->active;
24929352
DV		 15243 crtc->base.enabled = crtc->active;
15244
15245 /* Because we only establish the connector -> encoder ->
15246 * crtc links if something is active, this means the
15247 * crtc is now deactivated. Break the links. connector
15248 * -> encoder links are only establish when things are
15249 * actually up, hence no need to break them. */
15250 WARN_ON(crtc->active);
15251
2d406bb0 15252 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 15253 encoder->base.crtc = NULL;
24929352 15254 }
c5ab3bc0 15255
a3ed6aad 15256 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15257 /*
15258 * We start out with underrun reporting disabled to avoid races.
15259 * For correct bookkeeping mark this on active crtcs.
15260 *
c5ab3bc0
DV		 15261 * Also on gmch platforms we dont have any hardware bits to
15262 * disable the underrun reporting. Which means we need to start
15263 * out with underrun reporting disabled also on inactive pipes,
15264 * since otherwise we'll complain about the garbage we read when
15265 * e.g. coming up after runtime pm.
15266 *
4cc31489
DV		 15267 * No protection against concurrent access is required - at
15268 * worst a fifo underrun happens which also sets this to false.
15269 */
15270 crtc->cpu_fifo_underrun_disabled = true;
15271 crtc->pch_fifo_underrun_disabled = true;
15272 }
24929352
DV		 15273}
15274
15275static void intel_sanitize_encoder(struct intel_encoder *encoder)
15276{
15277 struct intel_connector *connector;
15278 struct drm_device *dev = encoder->base.dev;
873ffe69 15279 bool active = false;
24929352
DV		 15280
15281 /* We need to check both for a crtc link (meaning that the
15282 * encoder is active and trying to read from a pipe) and the
15283 * pipe itself being active. */
15284 bool has_active_crtc = encoder->base.crtc &&
15285 to_intel_crtc(encoder->base.crtc)->active;
15286
873ffe69
ML		 15287 for_each_intel_connector(dev, connector) {
15288 if (connector->base.encoder != &encoder->base)
15289 continue;
15290
15291 active = true;
15292 break;
15293 }
15294
15295 if (active && !has_active_crtc) {
24929352
DV		 15296 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15297 encoder->base.base.id,
8e329a03 15298 encoder->base.name);
24929352
DV		 15299
15300 /* Connector is active, but has no active pipe. This is
15301 * fallout from our resume register restoring. Disable
15302 * the encoder manually again. */
15303 if (encoder->base.crtc) {
15304 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15305 encoder->base.base.id,
8e329a03 15306 encoder->base.name);
24929352 15307 encoder->disable(encoder);
a62d1497
VS		 15308 if (encoder->post_disable)
15309 encoder->post_disable(encoder);
24929352 15310 }
7f1950fb 15311 encoder->base.crtc = NULL;
24929352
DV		 15312
15313 /* Inconsistent output/port/pipe state happens presumably due to
15314 * a bug in one of the get_hw_state functions. Or someplace else
15315 * in our code, like the register restore mess on resume. Clamp
15316 * things to off as a safer default. */
3a3371ff 15317 for_each_intel_connector(dev, connector) {
24929352
DV		 15318 if (connector->encoder != encoder)
15319 continue;
7f1950fb
EE		 15320 connector->base.dpms = DRM_MODE_DPMS_OFF;
15321 connector->base.encoder = NULL;
24929352
DV		 15322 }
15323 }
15324 /* Enabled encoders without active connectors will be fixed in
15325 * the crtc fixup. */
15326}
15327
04098753 15328void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15329{
15330 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15331 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15332
04098753
ID		 15333 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15334 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15335 i915_disable_vga(dev);
15336 }
15337}
15338
15339void i915_redisable_vga(struct drm_device *dev)
15340{
15341 struct drm_i915_private *dev_priv = dev->dev_private;
15342
8dc8a27c
PZ		 15343 /* This function can be called both from intel_modeset_setup_hw_state or
15344 * at a very early point in our resume sequence, where the power well
15345 * structures are not yet restored. Since this function is at a very
15346 * paranoid "someone might have enabled VGA while we were not looking"
15347 * level, just check if the power well is enabled instead of trying to
15348 * follow the "don't touch the power well if we don't need it" policy
15349 * the rest of the driver uses. */
f458ebbc 15350 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15351 return;
15352
04098753 15353 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15354}
15355
f9cd7b88 15356static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15357{
f9cd7b88 15358 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15359
f9cd7b88 15360 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15361}
15362
f9cd7b88
VS		 15363/* FIXME read out full plane state for all planes */
15364static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15365{
b26d3ea3 15366 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15367 struct intel_plane_state *plane_state =
b26d3ea3 15368 to_intel_plane_state(primary->state);
d032ffa0 15369
19b8d387 15370 plane_state->visible = crtc->active &&
b26d3ea3
ML		 15371 primary_get_hw_state(to_intel_plane(primary));
15372
15373 if (plane_state->visible)
15374 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15375}
15376
30e984df 15377static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15378{
15379 struct drm_i915_private *dev_priv = dev->dev_private;
15380 enum pipe pipe;
24929352
DV		 15381 struct intel_crtc *crtc;
15382 struct intel_encoder *encoder;
15383 struct intel_connector *connector;
5358901f 15384 int i;
24929352 15385
d3fcc808 15386 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15387 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15388 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15389 crtc->config->base.crtc = &crtc->base;
3b117c8f 15390
0e8ffe1b 15391 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15392 crtc->config);
24929352 15393
49d6fa21 15394 crtc->base.state->active = crtc->active;
24929352 15395 crtc->base.enabled = crtc->active;
b70709a6 15396
f9cd7b88 15397 readout_plane_state(crtc);
24929352
DV		 15398
15399 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15400 crtc->base.base.id,
15401 crtc->active ? "enabled" : "disabled");
15402 }
15403
5358901f
DV		 15404 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15405 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15406
3e369b76
ACO		 15407 pll->on = pll->get_hw_state(dev_priv, pll,
15408 &pll->config.hw_state);
5358901f 15409 pll->active = 0;
3e369b76 15410 pll->config.crtc_mask = 0;
d3fcc808 15411 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15412 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15413 pll->active++;
3e369b76 15414 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15415 }
5358901f 15416 }
5358901f 15417
1e6f2ddc 15418 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15419 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15420
3e369b76 15421 if (pll->config.crtc_mask)
bd2bb1b9 15422 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15423 }
15424
b2784e15 15425 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15426 pipe = 0;
15427
15428 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15429 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15430 encoder->base.crtc = &crtc->base;
6e3c9717 15431 encoder->get_config(encoder, crtc->config);
24929352
DV		 15432 } else {
15433 encoder->base.crtc = NULL;
15434 }
15435
6f2bcceb 15436 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15437 encoder->base.base.id,
8e329a03 15438 encoder->base.name,
24929352 15439 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15440 pipe_name(pipe));
24929352
DV		 15441 }
15442
3a3371ff 15443 for_each_intel_connector(dev, connector) {
24929352
DV		 15444 if (connector->get_hw_state(connector)) {
15445 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15446 connector->base.encoder = &connector->encoder->base;
15447 } else {
15448 connector->base.dpms = DRM_MODE_DPMS_OFF;
15449 connector->base.encoder = NULL;
15450 }
15451 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15452 connector->base.base.id,
c23cc417 15453 connector->base.name,
24929352
DV		 15454 connector->base.encoder ? "enabled" : "disabled");
15455 }
7f4c6284
VS		 15456
15457 for_each_intel_crtc(dev, crtc) {
15458 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15459
15460 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15461 if (crtc->base.state->active) {
15462 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15463 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15464 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15465
15466 /*
15467 * The initial mode needs to be set in order to keep
15468 * the atomic core happy. It wants a valid mode if the
15469 * crtc's enabled, so we do the above call.
15470 *
15471 * At this point some state updated by the connectors
15472 * in their ->detect() callback has not run yet, so
15473 * no recalculation can be done yet.
15474 *
15475 * Even if we could do a recalculation and modeset
15476 * right now it would cause a double modeset if
15477 * fbdev or userspace chooses a different initial mode.
15478 *
15479 * If that happens, someone indicated they wanted a
15480 * mode change, which means it's safe to do a full
15481 * recalculation.
15482 */
15483 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15484
15485 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15486 update_scanline_offset(crtc);
7f4c6284
VS		 15487 }
15488 }
30e984df
DV		 15489}
15490
043e9bda
ML		 15491/* Scan out the current hw modeset state,
15492 * and sanitizes it to the current state
15493 */
15494static void
15495intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15496{
15497 struct drm_i915_private *dev_priv = dev->dev_private;
15498 enum pipe pipe;
30e984df
DV		 15499 struct intel_crtc *crtc;
15500 struct intel_encoder *encoder;
35c95375 15501 int i;
30e984df
DV		 15502
15503 intel_modeset_readout_hw_state(dev);
24929352
DV		 15504
15505 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15506 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15507 intel_sanitize_encoder(encoder);
15508 }
15509
055e393f 15510 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15511 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15512 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15513 intel_dump_pipe_config(crtc, crtc->config,
15514 "[setup_hw_state]");
24929352 15515 }
9a935856 15516
d29b2f9d
ACO		 15517 intel_modeset_update_connector_atomic_state(dev);
15518
35c95375
DV		 15519 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15520 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15521
15522 if (!pll->on || pll->active)
15523 continue;
15524
15525 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15526
15527 pll->disable(dev_priv, pll);
15528 pll->on = false;
15529 }
15530
26e1fe4f 15531 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15532 vlv_wm_get_hw_state(dev);
15533 else if (IS_GEN9(dev))
3078999f
PB		 15534 skl_wm_get_hw_state(dev);
15535 else if (HAS_PCH_SPLIT(dev))
243e6a44 15536 ilk_wm_get_hw_state(dev);
292b990e
ML		 15537
15538 for_each_intel_crtc(dev, crtc) {
15539 unsigned long put_domains;
15540
15541 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15542 if (WARN_ON(put_domains))
15543 modeset_put_power_domains(dev_priv, put_domains);
15544 }
15545 intel_display_set_init_power(dev_priv, false);
043e9bda 15546}
7d0bc1ea 15547
043e9bda
ML		 15548void intel_display_resume(struct drm_device *dev)
15549{
15550 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15551 struct intel_connector *conn;
15552 struct intel_plane *plane;
15553 struct drm_crtc *crtc;
15554 int ret;
f30da187 15555
043e9bda
ML		 15556 if (!state)
15557 return;
15558
15559 state->acquire_ctx = dev->mode_config.acquire_ctx;
15560
15561 /* preserve complete old state, including dpll */
15562 intel_atomic_get_shared_dpll_state(state);
15563
15564 for_each_crtc(dev, crtc) {
15565 struct drm_crtc_state *crtc_state =
15566 drm_atomic_get_crtc_state(state, crtc);
15567
15568 ret = PTR_ERR_OR_ZERO(crtc_state);
15569 if (ret)
15570 goto err;
15571
15572 /* force a restore */
15573 crtc_state->mode_changed = true;
45e2b5f6 15574 }
8af6cf88 15575
043e9bda
ML		 15576 for_each_intel_plane(dev, plane) {
15577 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15578 if (ret)
15579 goto err;
15580 }
15581
15582 for_each_intel_connector(dev, conn) {
15583 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15584 if (ret)
15585 goto err;
15586 }
15587
15588 intel_modeset_setup_hw_state(dev);
15589
15590 i915_redisable_vga(dev);
74c090b1 15591 ret = drm_atomic_commit(state);
043e9bda
ML		 15592 if (!ret)
15593 return;
15594
15595err:
15596 DRM_ERROR("Restoring old state failed with %i\n", ret);
15597 drm_atomic_state_free(state);
2c7111db
CW		 15598}
15599
15600void intel_modeset_gem_init(struct drm_device *dev)
15601{
484b41dd 15602 struct drm_crtc *c;
2ff8fde1 15603 struct drm_i915_gem_object *obj;
e0d6149b 15604 int ret;
484b41dd 15605
ae48434c
ID		 15606 mutex_lock(&dev->struct_mutex);
15607 intel_init_gt_powersave(dev);
15608 mutex_unlock(&dev->struct_mutex);
15609
1833b134 15610 intel_modeset_init_hw(dev);
02e792fb
DV		 15611
15612 intel_setup_overlay(dev);
484b41dd
JB		 15613
15614 /*
15615 * Make sure any fbs we allocated at startup are properly
15616 * pinned & fenced. When we do the allocation it's too early
15617 * for this.
15618 */
70e1e0ec 15619 for_each_crtc(dev, c) {
2ff8fde1
MR		 15620 obj = intel_fb_obj(c->primary->fb);
15621 if (obj == NULL)
484b41dd
JB		 15622 continue;
15623
e0d6149b
TU		 15624 mutex_lock(&dev->struct_mutex);
15625 ret = intel_pin_and_fence_fb_obj(c->primary,
15626 c->primary->fb,
7580d774 15627 c->primary->state);
e0d6149b
TU		 15628 mutex_unlock(&dev->struct_mutex);
15629 if (ret) {
484b41dd
JB		 15630 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15631 to_intel_crtc(c)->pipe);
66e514c1
DA		 15632 drm_framebuffer_unreference(c->primary->fb);
15633 c->primary->fb = NULL;
36750f28 15634 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15635 update_state_fb(c->primary);
36750f28 15636 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15637 }
15638 }
0962c3c9
VS		 15639
15640 intel_backlight_register(dev);
79e53945
JB		 15641}
15642
4932e2c3
ID		 15643void intel_connector_unregister(struct intel_connector *intel_connector)
15644{
15645 struct drm_connector *connector = &intel_connector->base;
15646
15647 intel_panel_destroy_backlight(connector);
34ea3d38 15648 drm_connector_unregister(connector);
4932e2c3
ID		 15649}
15650
79e53945
JB		 15651void intel_modeset_cleanup(struct drm_device *dev)
15652{
652c393a 15653 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15654 struct drm_connector *connector;
652c393a 15655
2eb5252e
ID		 15656 intel_disable_gt_powersave(dev);
15657
0962c3c9
VS		 15658 intel_backlight_unregister(dev);
15659
fd0c0642
DV		 15660 /*
15661 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15662 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15663 * experience fancy races otherwise.
15664 */
2aeb7d3a 15665 intel_irq_uninstall(dev_priv);
eb21b92b 15666
fd0c0642
DV		 15667 /*
15668 * Due to the hpd irq storm handling the hotplug work can re-arm the
15669 * poll handlers. Hence disable polling after hpd handling is shut down.
15670 */
f87ea761 15671 drm_kms_helper_poll_fini(dev);
fd0c0642 15672
723bfd70
JB		 15673 intel_unregister_dsm_handler();
15674
7733b49b 15675 intel_fbc_disable(dev_priv);
69341a5e 15676
1630fe75
CW		 15677 /* flush any delayed tasks or pending work */
15678 flush_scheduled_work();
15679
db31af1d
JN		 15680 /* destroy the backlight and sysfs files before encoders/connectors */
15681 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15682 struct intel_connector *intel_connector;
15683
15684 intel_connector = to_intel_connector(connector);
15685 intel_connector->unregister(intel_connector);
db31af1d 15686 }
d9255d57 15687
79e53945 15688 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15689
15690 intel_cleanup_overlay(dev);
ae48434c
ID		 15691
15692 mutex_lock(&dev->struct_mutex);
15693 intel_cleanup_gt_powersave(dev);
15694 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15695}
15696
f1c79df3
ZW		 15697/*
15698 * Return which encoder is currently attached for connector.
15699 */
df0e9248 15700struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15701{
df0e9248
CW		 15702 return &intel_attached_encoder(connector)->base;
15703}
f1c79df3 15704
df0e9248
CW		 15705void intel_connector_attach_encoder(struct intel_connector *connector,
15706 struct intel_encoder *encoder)
15707{
15708 connector->encoder = encoder;
15709 drm_mode_connector_attach_encoder(&connector->base,
15710 &encoder->base);
79e53945 15711}
28d52043
DA		 15712
15713/*
15714 * set vga decode state - true == enable VGA decode
15715 */
15716int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15717{
15718 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15719 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15720 u16 gmch_ctrl;
15721
75fa041d
CW		 15722 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15723 DRM_ERROR("failed to read control word\n");
15724 return -EIO;
15725 }
15726
c0cc8a55
CW		 15727 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15728 return 0;
15729
28d52043
DA		 15730 if (state)
15731 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15732 else
15733 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15734
15735 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15736 DRM_ERROR("failed to write control word\n");
15737 return -EIO;
15738 }
15739
28d52043
DA		 15740 return 0;
15741}
c4a1d9e4 15742
c4a1d9e4 15743struct intel_display_error_state {
ff57f1b0
PZ		 15744
15745 u32 power_well_driver;
15746
63b66e5b
CW		 15747 int num_transcoders;
15748
c4a1d9e4
CW		 15749 struct intel_cursor_error_state {
15750 u32 control;
15751 u32 position;
15752 u32 base;
15753 u32 size;
52331309 15754 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15755
15756 struct intel_pipe_error_state {
ddf9c536 15757 bool power_domain_on;
c4a1d9e4 15758 u32 source;
f301b1e1 15759 u32 stat;
52331309 15760 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15761
15762 struct intel_plane_error_state {
15763 u32 control;
15764 u32 stride;
15765 u32 size;
15766 u32 pos;
15767 u32 addr;
15768 u32 surface;
15769 u32 tile_offset;
52331309 15770 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15771
15772 struct intel_transcoder_error_state {
ddf9c536 15773 bool power_domain_on;
63b66e5b
CW		 15774 enum transcoder cpu_transcoder;
15775
15776 u32 conf;
15777
15778 u32 htotal;
15779 u32 hblank;
15780 u32 hsync;
15781 u32 vtotal;
15782 u32 vblank;
15783 u32 vsync;
15784 } transcoder[4];
c4a1d9e4
CW		 15785};
15786
15787struct intel_display_error_state *
15788intel_display_capture_error_state(struct drm_device *dev)
15789{
fbee40df 15790 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15791 struct intel_display_error_state *error;
63b66e5b
CW		 15792 int transcoders[] = {
15793 TRANSCODER_A,
15794 TRANSCODER_B,
15795 TRANSCODER_C,
15796 TRANSCODER_EDP,
15797 };
c4a1d9e4
CW		 15798 int i;
15799
63b66e5b
CW		 15800 if (INTEL_INFO(dev)->num_pipes == 0)
15801 return NULL;
15802
9d1cb914 15803 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15804 if (error == NULL)
15805 return NULL;
15806
190be112 15807 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15808 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15809
055e393f 15810 for_each_pipe(dev_priv, i) {
ddf9c536 15811 error->pipe[i].power_domain_on =
f458ebbc
DV		 15812 __intel_display_power_is_enabled(dev_priv,
15813 POWER_DOMAIN_PIPE(i));
ddf9c536 15814 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15815 continue;
15816
5efb3e28
VS		 15817 error->cursor[i].control = I915_READ(CURCNTR(i));
15818 error->cursor[i].position = I915_READ(CURPOS(i));
15819 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15820
15821 error->plane[i].control = I915_READ(DSPCNTR(i));
15822 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15823 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15824 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15825 error->plane[i].pos = I915_READ(DSPPOS(i));
15826 }
ca291363
PZ		 15827 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15828 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15829 if (INTEL_INFO(dev)->gen >= 4) {
15830 error->plane[i].surface = I915_READ(DSPSURF(i));
15831 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15832 }
15833
c4a1d9e4 15834 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15835
3abfce77 15836 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15837 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15838 }
15839
15840 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15841 if (HAS_DDI(dev_priv->dev))
15842 error->num_transcoders++; /* Account for eDP. */
15843
15844 for (i = 0; i < error->num_transcoders; i++) {
15845 enum transcoder cpu_transcoder = transcoders[i];
15846
ddf9c536 15847 error->transcoder[i].power_domain_on =
f458ebbc 15848 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15849 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15850 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15851 continue;
15852
63b66e5b
CW		 15853 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15854
15855 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15856 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15857 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15858 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15859 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15860 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15861 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15862 }
15863
15864 return error;
15865}
15866
edc3d884
MK		 15867#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15868
c4a1d9e4 15869void
edc3d884 15870intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15871 struct drm_device *dev,
15872 struct intel_display_error_state *error)
15873{
055e393f 15874 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15875 int i;
15876
63b66e5b
CW		 15877 if (!error)
15878 return;
15879
edc3d884 15880 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15881 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15882 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15883 error->power_well_driver);
055e393f 15884 for_each_pipe(dev_priv, i) {
edc3d884 15885 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15886 err_printf(m, " Power: %s\n",
15887 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15888 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15889 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15890
15891 err_printf(m, "Plane [%d]:\n", i);
15892 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15893 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15894 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15895 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15896 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15897 }
4b71a570 15898 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15899 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15900 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15901 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15902 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15903 }
15904
edc3d884
MK		 15905 err_printf(m, "Cursor [%d]:\n", i);
15906 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15907 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15908 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15909 }
63b66e5b
CW		 15910
15911 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15912 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15913 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15914 err_printf(m, " Power: %s\n",
15915 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15916 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15917 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15918 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15919 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15920 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15921 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15922 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15923 }
c4a1d9e4 15924}
e2fcdaa9
VS		 15925
15926void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15927{
15928 struct intel_crtc *crtc;
15929
15930 for_each_intel_crtc(dev, crtc) {
15931 struct intel_unpin_work *work;
e2fcdaa9 15932
5e2d7afc 15933 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15934
15935 work = crtc->unpin_work;
15936
15937 if (work && work->event &&
15938 work->event->base.file_priv == file) {
15939 kfree(work->event);
15940 work->event = NULL;
15941 }
15942
5e2d7afc 15943 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15944 }
15945}
Linux kernel - Deliverables
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