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drm/i915: do not use fdi_normal_train on Haswell
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
a928d536
PZ		 787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
9d0498a2
JB		 798/**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 807{
9d0498a2 808 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 809 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 810
a928d536
PZ		 811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
300387c0
CW		 816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
9d0498a2 832 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
9d0498a2
JB		 836 DRM_DEBUG_KMS("vblank wait timed out\n");
837}
838
ab7ad7f6
KP		 839/*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
ab7ad7f6
KP		 848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
58e10eb9 854 *
9d0498a2 855 */
58e10eb9 856void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 857{
858 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 859
860 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 861 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 862
863 /* Wait for the Pipe State to go off */
58e10eb9
CW		 864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
ab7ad7f6
KP		 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
837ba00f 868 u32 last_line, line_mask;
58e10eb9 869 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
837ba00f
PZ		 872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
ab7ad7f6
KP		 877 /* Wait for the display line to settle */
878 do {
837ba00f 879 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 880 mdelay(5);
837ba00f 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
79e53945
JB		 886}
887
b24e7179
JB		 888static const char *state_string(bool enabled)
889{
890 return enabled ? "on" : "off";
891}
892
893/* Only for pre-ILK configs */
894static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896{
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907}
908#define assert_pll_enabled(d, p) assert_pll(d, p, true)
909#define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
040484af
JB		 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv,
ee7b9f93 913 struct intel_crtc *intel_crtc, bool state)
040484af
JB		 914{
915 int reg;
916 u32 val;
917 bool cur_state;
918
ee7b9f93
JB		 919 if (!intel_crtc->pch_pll) {
920 WARN(1, "asserting PCH PLL enabled with no PLL\n");
921 return;
922 }
923
d3ccbe86
JB		 924 if (HAS_PCH_CPT(dev_priv->dev)) {
925 u32 pch_dpll;
926
927 pch_dpll = I915_READ(PCH_DPLL_SEL);
928
929 /* Make sure the selected PLL is enabled to the transcoder */
ee7b9f93
JB		 930 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
931 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
d3ccbe86
JB		 932 }
933
ee7b9f93 934 reg = intel_crtc->pch_pll->pll_reg;
040484af
JB		 935 val = I915_READ(reg);
936 cur_state = !!(val & DPLL_VCO_ENABLE);
937 WARN(cur_state != state,
938 "PCH PLL state assertion failure (expected %s, current %s)\n",
939 state_string(state), state_string(cur_state));
940}
941#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
942#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
943
944static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946{
947 int reg;
948 u32 val;
949 bool cur_state;
950
951 reg = FDI_TX_CTL(pipe);
952 val = I915_READ(reg);
953 cur_state = !!(val & FDI_TX_ENABLE);
954 WARN(cur_state != state,
955 "FDI TX state assertion failure (expected %s, current %s)\n",
956 state_string(state), state_string(cur_state));
957}
958#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
959#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
960
961static void assert_fdi_rx(struct drm_i915_private *dev_priv,
962 enum pipe pipe, bool state)
963{
964 int reg;
965 u32 val;
966 bool cur_state;
967
968 reg = FDI_RX_CTL(pipe);
969 val = I915_READ(reg);
970 cur_state = !!(val & FDI_RX_ENABLE);
971 WARN(cur_state != state,
972 "FDI RX state assertion failure (expected %s, current %s)\n",
973 state_string(state), state_string(cur_state));
974}
975#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
976#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
977
978static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
979 enum pipe pipe)
980{
981 int reg;
982 u32 val;
983
984 /* ILK FDI PLL is always enabled */
985 if (dev_priv->info->gen == 5)
986 return;
987
988 reg = FDI_TX_CTL(pipe);
989 val = I915_READ(reg);
990 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
991}
992
993static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
994 enum pipe pipe)
995{
996 int reg;
997 u32 val;
998
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002}
1003
ea0760cf
JB		 1004static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006{
1007 int pp_reg, lvds_reg;
1008 u32 val;
1009 enum pipe panel_pipe = PIPE_A;
0de3b485 1010 bool locked = true;
ea0760cf
JB		 1011
1012 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013 pp_reg = PCH_PP_CONTROL;
1014 lvds_reg = PCH_LVDS;
1015 } else {
1016 pp_reg = PP_CONTROL;
1017 lvds_reg = LVDS;
1018 }
1019
1020 val = I915_READ(pp_reg);
1021 if (!(val & PANEL_POWER_ON) ||
1022 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023 locked = false;
1024
1025 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026 panel_pipe = PIPE_B;
1027
1028 WARN(panel_pipe == pipe && locked,
1029 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1030 pipe_name(pipe));
ea0760cf
JB		 1031}
1032
b840d907
JB		 1033void assert_pipe(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
b24e7179
JB		 1035{
1036 int reg;
1037 u32 val;
63d7bbe9 1038 bool cur_state;
b24e7179 1039
8e636784
DV		 1040 /* if we need the pipe A quirk it must be always on */
1041 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042 state = true;
1043
b24e7179
JB		 1044 reg = PIPECONF(pipe);
1045 val = I915_READ(reg);
63d7bbe9
JB		 1046 cur_state = !!(val & PIPECONF_ENABLE);
1047 WARN(cur_state != state,
1048 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1049 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1050}
1051
931872fc
CW		 1052static void assert_plane(struct drm_i915_private *dev_priv,
1053 enum plane plane, bool state)
b24e7179
JB		 1054{
1055 int reg;
1056 u32 val;
931872fc 1057 bool cur_state;
b24e7179
JB		 1058
1059 reg = DSPCNTR(plane);
1060 val = I915_READ(reg);
931872fc
CW		 1061 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062 WARN(cur_state != state,
1063 "plane %c assertion failure (expected %s, current %s)\n",
1064 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1065}
1066
931872fc
CW		 1067#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
b24e7179
JB		 1070static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe)
1072{
1073 int reg, i;
1074 u32 val;
1075 int cur_pipe;
1076
19ec1358 1077 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1078 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079 reg = DSPCNTR(pipe);
1080 val = I915_READ(reg);
1081 WARN((val & DISPLAY_PLANE_ENABLE),
1082 "plane %c assertion failure, should be disabled but not\n",
1083 plane_name(pipe));
19ec1358 1084 return;
28c05794 1085 }
19ec1358 1086
b24e7179
JB		 1087 /* Need to check both planes against the pipe */
1088 for (i = 0; i < 2; i++) {
1089 reg = DSPCNTR(i);
1090 val = I915_READ(reg);
1091 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092 DISPPLANE_SEL_PIPE_SHIFT;
1093 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1094 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1096 }
1097}
1098
92f2584a
JB		 1099static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100{
1101 u32 val;
1102 bool enabled;
1103
1104 val = I915_READ(PCH_DREF_CONTROL);
1105 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106 DREF_SUPERSPREAD_SOURCE_MASK));
1107 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108}
1109
1110static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111 enum pipe pipe)
1112{
1113 int reg;
1114 u32 val;
1115 bool enabled;
1116
1117 reg = TRANSCONF(pipe);
1118 val = I915_READ(reg);
1119 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1120 WARN(enabled,
1121 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122 pipe_name(pipe));
92f2584a
JB		 1123}
1124
4e634389
KP		 1125static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1127{
1128 if ((val & DP_PORT_EN) == 0)
1129 return false;
1130
1131 if (HAS_PCH_CPT(dev_priv->dev)) {
1132 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135 return false;
1136 } else {
1137 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138 return false;
1139 }
1140 return true;
1141}
1142
1519b995
KP		 1143static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, u32 val)
1145{
1146 if ((val & PORT_ENABLE) == 0)
1147 return false;
1148
1149 if (HAS_PCH_CPT(dev_priv->dev)) {
1150 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151 return false;
1152 } else {
1153 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154 return false;
1155 }
1156 return true;
1157}
1158
1159static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, u32 val)
1161{
1162 if ((val & LVDS_PORT_EN) == 0)
1163 return false;
1164
1165 if (HAS_PCH_CPT(dev_priv->dev)) {
1166 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167 return false;
1168 } else {
1169 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170 return false;
1171 }
1172 return true;
1173}
1174
1175static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176 enum pipe pipe, u32 val)
1177{
1178 if ((val & ADPA_DAC_ENABLE) == 0)
1179 return false;
1180 if (HAS_PCH_CPT(dev_priv->dev)) {
1181 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182 return false;
1183 } else {
1184 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185 return false;
1186 }
1187 return true;
1188}
1189
291906f1 1190static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1191 enum pipe pipe, int reg, u32 port_sel)
291906f1 1192{
47a05eca 1193 u32 val = I915_READ(reg);
4e634389 1194 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1195 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1196 reg, pipe_name(pipe));
291906f1
JB		 1197}
1198
1199static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, int reg)
1201{
47a05eca 1202 u32 val = I915_READ(reg);
1519b995 1203 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1204 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1205 reg, pipe_name(pipe));
291906f1
JB		 1206}
1207
1208static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210{
1211 int reg;
1212 u32 val;
291906f1 1213
f0575e92
KP		 1214 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1217
1218 reg = PCH_ADPA;
1219 val = I915_READ(reg);
1519b995 1220 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1221 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1222 pipe_name(pipe));
291906f1
JB		 1223
1224 reg = PCH_LVDS;
1225 val = I915_READ(reg);
1519b995 1226 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1227 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1228 pipe_name(pipe));
291906f1
JB		 1229
1230 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233}
1234
63d7bbe9
JB		 1235/**
1236 * intel_enable_pll - enable a PLL
1237 * @dev_priv: i915 private structure
1238 * @pipe: pipe PLL to enable
1239 *
1240 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1241 * make sure the PLL reg is writable first though, since the panel write
1242 * protect mechanism may be enabled.
1243 *
1244 * Note! This is for pre-ILK only.
1245 */
1246static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247{
1248 int reg;
1249 u32 val;
1250
1251 /* No really, not for ILK+ */
1252 BUG_ON(dev_priv->info->gen >= 5);
1253
1254 /* PLL is protected by panel, make sure we can write it */
1255 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256 assert_panel_unlocked(dev_priv, pipe);
1257
1258 reg = DPLL(pipe);
1259 val = I915_READ(reg);
1260 val |= DPLL_VCO_ENABLE;
1261
1262 /* We do this three times for luck */
1263 I915_WRITE(reg, val);
1264 POSTING_READ(reg);
1265 udelay(150); /* wait for warmup */
1266 I915_WRITE(reg, val);
1267 POSTING_READ(reg);
1268 udelay(150); /* wait for warmup */
1269 I915_WRITE(reg, val);
1270 POSTING_READ(reg);
1271 udelay(150); /* wait for warmup */
1272}
1273
1274/**
1275 * intel_disable_pll - disable a PLL
1276 * @dev_priv: i915 private structure
1277 * @pipe: pipe PLL to disable
1278 *
1279 * Disable the PLL for @pipe, making sure the pipe is off first.
1280 *
1281 * Note! This is for pre-ILK only.
1282 */
1283static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
1287
1288 /* Don't disable pipe A or pipe A PLLs if needed */
1289 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290 return;
1291
1292 /* Make sure the pipe isn't still relying on us */
1293 assert_pipe_disabled(dev_priv, pipe);
1294
1295 reg = DPLL(pipe);
1296 val = I915_READ(reg);
1297 val &= ~DPLL_VCO_ENABLE;
1298 I915_WRITE(reg, val);
1299 POSTING_READ(reg);
1300}
1301
a416edef
ED		 1302/* SBI access */
1303static void
1304intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1305{
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1309 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1310 100)) {
1311 DRM_ERROR("timeout waiting for SBI to become ready\n");
1312 goto out_unlock;
1313 }
1314
1315 I915_WRITE(SBI_ADDR,
1316 (reg << 16));
1317 I915_WRITE(SBI_DATA,
1318 value);
1319 I915_WRITE(SBI_CTL_STAT,
1320 SBI_BUSY |
1321 SBI_CTL_OP_CRWR);
1322
1323 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1324 100)) {
1325 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1326 goto out_unlock;
1327 }
1328
1329out_unlock:
1330 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1331}
1332
1333static u32
1334intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1335{
1336 unsigned long flags;
1337 u32 value;
1338
1339 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1340 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1341 100)) {
1342 DRM_ERROR("timeout waiting for SBI to become ready\n");
1343 goto out_unlock;
1344 }
1345
1346 I915_WRITE(SBI_ADDR,
1347 (reg << 16));
1348 I915_WRITE(SBI_CTL_STAT,
1349 SBI_BUSY |
1350 SBI_CTL_OP_CRRD);
1351
1352 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1353 100)) {
1354 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1355 goto out_unlock;
1356 }
1357
1358 value = I915_READ(SBI_DATA);
1359
1360out_unlock:
1361 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1362 return value;
1363}
1364
92f2584a
JB		 1365/**
1366 * intel_enable_pch_pll - enable PCH PLL
1367 * @dev_priv: i915 private structure
1368 * @pipe: pipe PLL to enable
1369 *
1370 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1371 * drives the transcoder clock.
1372 */
ee7b9f93 1373static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1374{
ee7b9f93
JB		 1375 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1376 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a
JB		 1377 int reg;
1378 u32 val;
1379
1380 /* PCH only available on ILK+ */
1381 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1382 BUG_ON(pll == NULL);
1383 BUG_ON(pll->refcount == 0);
1384
1385 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1386 pll->pll_reg, pll->active, pll->on,
1387 intel_crtc->base.base.id);
92f2584a
JB		 1388
1389 /* PCH refclock must be enabled first */
1390 assert_pch_refclk_enabled(dev_priv);
1391
ee7b9f93
JB		 1392 if (pll->active++ && pll->on) {
1393 assert_pch_pll_enabled(dev_priv, intel_crtc);
1394 return;
1395 }
1396
1397 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1398
1399 reg = pll->pll_reg;
92f2584a
JB		 1400 val = I915_READ(reg);
1401 val |= DPLL_VCO_ENABLE;
1402 I915_WRITE(reg, val);
1403 POSTING_READ(reg);
1404 udelay(200);
ee7b9f93
JB		 1405
1406 pll->on = true;
92f2584a
JB		 1407}
1408
ee7b9f93 1409static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1410{
ee7b9f93
JB		 1411 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1412 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1413 int reg;
ee7b9f93 1414 u32 val;
4c609cb8 1415
92f2584a
JB		 1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1418 if (pll == NULL)
1419 return;
92f2584a 1420
ee7b9f93 1421 BUG_ON(pll->refcount == 0);
7a419866 1422
ee7b9f93
JB		 1423 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1424 pll->pll_reg, pll->active, pll->on,
1425 intel_crtc->base.base.id);
7a419866 1426
ee7b9f93
JB		 1427 BUG_ON(pll->active == 0);
1428 if (--pll->active) {
1429 assert_pch_pll_enabled(dev_priv, intel_crtc);
7a419866 1430 return;
ee7b9f93
JB		 1431 }
1432
1433 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1434
1435 /* Make sure transcoder isn't still depending on us */
1436 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1437
ee7b9f93 1438 reg = pll->pll_reg;
92f2584a
JB		 1439 val = I915_READ(reg);
1440 val &= ~DPLL_VCO_ENABLE;
1441 I915_WRITE(reg, val);
1442 POSTING_READ(reg);
1443 udelay(200);
ee7b9f93
JB		 1444
1445 pll->on = false;
92f2584a
JB		 1446}
1447
040484af
JB		 1448static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450{
1451 int reg;
5f7f726d 1452 u32 val, pipeconf_val;
7c26e5c6 1453 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1454
1455 /* PCH only available on ILK+ */
1456 BUG_ON(dev_priv->info->gen < 5);
1457
1458 /* Make sure PCH DPLL is enabled */
ee7b9f93 1459 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
040484af
JB		 1460
1461 /* FDI must be feeding us bits for PCH ports */
1462 assert_fdi_tx_enabled(dev_priv, pipe);
1463 assert_fdi_rx_enabled(dev_priv, pipe);
1464
1465 reg = TRANSCONF(pipe);
1466 val = I915_READ(reg);
5f7f726d 1467 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1468
1469 if (HAS_PCH_IBX(dev_priv->dev)) {
1470 /*
1471 * make the BPC in transcoder be consistent with
1472 * that in pipeconf reg.
1473 */
1474 val &= ~PIPE_BPC_MASK;
5f7f726d 1475 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1476 }
5f7f726d
PZ		 1477
1478 val &= ~TRANS_INTERLACE_MASK;
1479 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1480 if (HAS_PCH_IBX(dev_priv->dev) &&
1481 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1482 val |= TRANS_LEGACY_INTERLACED_ILK;
1483 else
1484 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1485 else
1486 val |= TRANS_PROGRESSIVE;
1487
040484af
JB		 1488 I915_WRITE(reg, val | TRANS_ENABLE);
1489 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1490 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1491}
1492
1493static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1494 enum pipe pipe)
1495{
1496 int reg;
1497 u32 val;
1498
1499 /* FDI relies on the transcoder */
1500 assert_fdi_tx_disabled(dev_priv, pipe);
1501 assert_fdi_rx_disabled(dev_priv, pipe);
1502
291906f1
JB		 1503 /* Ports must be off as well */
1504 assert_pch_ports_disabled(dev_priv, pipe);
1505
040484af
JB		 1506 reg = TRANSCONF(pipe);
1507 val = I915_READ(reg);
1508 val &= ~TRANS_ENABLE;
1509 I915_WRITE(reg, val);
1510 /* wait for PCH transcoder off, transcoder state */
1511 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1512 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1513}
1514
b24e7179 1515/**
309cfea8 1516 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1517 * @dev_priv: i915 private structure
1518 * @pipe: pipe to enable
040484af 1519 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1520 *
1521 * Enable @pipe, making sure that various hardware specific requirements
1522 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1523 *
1524 * @pipe should be %PIPE_A or %PIPE_B.
1525 *
1526 * Will wait until the pipe is actually running (i.e. first vblank) before
1527 * returning.
1528 */
040484af
JB		 1529static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1530 bool pch_port)
b24e7179
JB		 1531{
1532 int reg;
1533 u32 val;
1534
1535 /*
1536 * A pipe without a PLL won't actually be able to drive bits from
1537 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1538 * need the check.
1539 */
1540 if (!HAS_PCH_SPLIT(dev_priv->dev))
1541 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1542 else {
1543 if (pch_port) {
1544 /* if driving the PCH, we need FDI enabled */
1545 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1546 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1547 }
1548 /* FIXME: assert CPU port conditions for SNB+ */
1549 }
b24e7179
JB		 1550
1551 reg = PIPECONF(pipe);
1552 val = I915_READ(reg);
00d70b15
CW		 1553 if (val & PIPECONF_ENABLE)
1554 return;
1555
1556 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1557 intel_wait_for_vblank(dev_priv->dev, pipe);
1558}
1559
1560/**
309cfea8 1561 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1562 * @dev_priv: i915 private structure
1563 * @pipe: pipe to disable
1564 *
1565 * Disable @pipe, making sure that various hardware specific requirements
1566 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1567 *
1568 * @pipe should be %PIPE_A or %PIPE_B.
1569 *
1570 * Will wait until the pipe has shut down before returning.
1571 */
1572static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1573 enum pipe pipe)
1574{
1575 int reg;
1576 u32 val;
1577
1578 /*
1579 * Make sure planes won't keep trying to pump pixels to us,
1580 * or we might hang the display.
1581 */
1582 assert_planes_disabled(dev_priv, pipe);
1583
1584 /* Don't disable pipe A or pipe A PLLs if needed */
1585 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1586 return;
1587
1588 reg = PIPECONF(pipe);
1589 val = I915_READ(reg);
00d70b15
CW		 1590 if ((val & PIPECONF_ENABLE) == 0)
1591 return;
1592
1593 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1594 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1595}
1596
d74362c9
KP		 1597/*
1598 * Plane regs are double buffered, going from enabled->disabled needs a
1599 * trigger in order to latch. The display address reg provides this.
1600 */
6f1d69b0 1601void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1602 enum plane plane)
1603{
1604 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1605 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1606}
1607
b24e7179
JB		 1608/**
1609 * intel_enable_plane - enable a display plane on a given pipe
1610 * @dev_priv: i915 private structure
1611 * @plane: plane to enable
1612 * @pipe: pipe being fed
1613 *
1614 * Enable @plane on @pipe, making sure that @pipe is running first.
1615 */
1616static void intel_enable_plane(struct drm_i915_private *dev_priv,
1617 enum plane plane, enum pipe pipe)
1618{
1619 int reg;
1620 u32 val;
1621
1622 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1623 assert_pipe_enabled(dev_priv, pipe);
1624
1625 reg = DSPCNTR(plane);
1626 val = I915_READ(reg);
00d70b15
CW		 1627 if (val & DISPLAY_PLANE_ENABLE)
1628 return;
1629
1630 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1631 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1632 intel_wait_for_vblank(dev_priv->dev, pipe);
1633}
1634
b24e7179
JB		 1635/**
1636 * intel_disable_plane - disable a display plane
1637 * @dev_priv: i915 private structure
1638 * @plane: plane to disable
1639 * @pipe: pipe consuming the data
1640 *
1641 * Disable @plane; should be an independent operation.
1642 */
1643static void intel_disable_plane(struct drm_i915_private *dev_priv,
1644 enum plane plane, enum pipe pipe)
1645{
1646 int reg;
1647 u32 val;
1648
1649 reg = DSPCNTR(plane);
1650 val = I915_READ(reg);
00d70b15
CW		 1651 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1652 return;
1653
1654 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1655 intel_flush_display_plane(dev_priv, plane);
1656 intel_wait_for_vblank(dev_priv->dev, pipe);
1657}
1658
47a05eca 1659static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1660 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1661{
1662 u32 val = I915_READ(reg);
4e634389 1663 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1664 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1665 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1666 }
47a05eca
JB		 1667}
1668
1669static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1670 enum pipe pipe, int reg)
1671{
1672 u32 val = I915_READ(reg);
1519b995 1673 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1674 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1675 reg, pipe);
47a05eca 1676 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1677 }
47a05eca
JB		 1678}
1679
1680/* Disable any ports connected to this transcoder */
1681static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
1683{
1684 u32 reg, val;
1685
1686 val = I915_READ(PCH_PP_CONTROL);
1687 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1688
f0575e92
KP		 1689 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1690 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1691 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1692
1693 reg = PCH_ADPA;
1694 val = I915_READ(reg);
1519b995 1695 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1696 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1697
1698 reg = PCH_LVDS;
1699 val = I915_READ(reg);
1519b995
KP		 1700 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1701 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1702 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1703 POSTING_READ(reg);
1704 udelay(100);
1705 }
1706
1707 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1708 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1709 disable_pch_hdmi(dev_priv, pipe, HDMID);
1710}
1711
127bd2ac 1712int
48b956c5 1713intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1714 struct drm_i915_gem_object *obj,
919926ae 1715 struct intel_ring_buffer *pipelined)
6b95a207 1716{
ce453d81 1717 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1718 u32 alignment;
1719 int ret;
1720
05394f39 1721 switch (obj->tiling_mode) {
6b95a207 1722 case I915_TILING_NONE:
534843da
CW		 1723 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1724 alignment = 128 * 1024;
a6c45cf0 1725 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1726 alignment = 4 * 1024;
1727 else
1728 alignment = 64 * 1024;
6b95a207
KH		 1729 break;
1730 case I915_TILING_X:
1731 /* pin() will align the object as required by fence */
1732 alignment = 0;
1733 break;
1734 case I915_TILING_Y:
1735 /* FIXME: Is this true? */
1736 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1737 return -EINVAL;
1738 default:
1739 BUG();
1740 }
1741
ce453d81 1742 dev_priv->mm.interruptible = false;
2da3b9b9 1743 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1744 if (ret)
ce453d81 1745 goto err_interruptible;
6b95a207
KH		 1746
1747 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1748 * fence, whereas 965+ only requires a fence if using
1749 * framebuffer compression. For simplicity, we always install
1750 * a fence as the cost is not that onerous.
1751 */
06d98131 1752 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1753 if (ret)
1754 goto err_unpin;
1690e1eb 1755
9a5a53b3 1756 i915_gem_object_pin_fence(obj);
6b95a207 1757
ce453d81 1758 dev_priv->mm.interruptible = true;
6b95a207 1759 return 0;
48b956c5
CW		 1760
1761err_unpin:
1762 i915_gem_object_unpin(obj);
ce453d81
CW		 1763err_interruptible:
1764 dev_priv->mm.interruptible = true;
48b956c5 1765 return ret;
6b95a207
KH		 1766}
1767
1690e1eb
CW		 1768void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1769{
1770 i915_gem_object_unpin_fence(obj);
1771 i915_gem_object_unpin(obj);
1772}
1773
17638cd6
JB		 1774static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1775 int x, int y)
81255565
JB		 1776{
1777 struct drm_device *dev = crtc->dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780 struct intel_framebuffer *intel_fb;
05394f39 1781 struct drm_i915_gem_object *obj;
81255565
JB		 1782 int plane = intel_crtc->plane;
1783 unsigned long Start, Offset;
81255565 1784 u32 dspcntr;
5eddb70b 1785 u32 reg;
81255565
JB		 1786
1787 switch (plane) {
1788 case 0:
1789 case 1:
1790 break;
1791 default:
1792 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1793 return -EINVAL;
1794 }
1795
1796 intel_fb = to_intel_framebuffer(fb);
1797 obj = intel_fb->obj;
81255565 1798
5eddb70b
CW		 1799 reg = DSPCNTR(plane);
1800 dspcntr = I915_READ(reg);
81255565
JB		 1801 /* Mask out pixel format bits in case we change it */
1802 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1803 switch (fb->bits_per_pixel) {
1804 case 8:
1805 dspcntr |= DISPPLANE_8BPP;
1806 break;
1807 case 16:
1808 if (fb->depth == 15)
1809 dspcntr |= DISPPLANE_15_16BPP;
1810 else
1811 dspcntr |= DISPPLANE_16BPP;
1812 break;
1813 case 24:
1814 case 32:
1815 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1816 break;
1817 default:
17638cd6 1818 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1819 return -EINVAL;
1820 }
a6c45cf0 1821 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1822 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1823 dspcntr |= DISPPLANE_TILED;
1824 else
1825 dspcntr &= ~DISPPLANE_TILED;
1826 }
1827
5eddb70b 1828 I915_WRITE(reg, dspcntr);
81255565 1829
05394f39 1830 Start = obj->gtt_offset;
01f2c773 1831 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1832
4e6cfefc 1833 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1834 Start, Offset, x, y, fb->pitches[0]);
1835 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1836 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1837 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1838 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1839 I915_WRITE(DSPADDR(plane), Offset);
1840 } else
1841 I915_WRITE(DSPADDR(plane), Start + Offset);
1842 POSTING_READ(reg);
81255565 1843
17638cd6
JB		 1844 return 0;
1845}
1846
1847static int ironlake_update_plane(struct drm_crtc *crtc,
1848 struct drm_framebuffer *fb, int x, int y)
1849{
1850 struct drm_device *dev = crtc->dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
1852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853 struct intel_framebuffer *intel_fb;
1854 struct drm_i915_gem_object *obj;
1855 int plane = intel_crtc->plane;
1856 unsigned long Start, Offset;
1857 u32 dspcntr;
1858 u32 reg;
1859
1860 switch (plane) {
1861 case 0:
1862 case 1:
27f8227b 1863 case 2:
17638cd6
JB		 1864 break;
1865 default:
1866 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1867 return -EINVAL;
1868 }
1869
1870 intel_fb = to_intel_framebuffer(fb);
1871 obj = intel_fb->obj;
1872
1873 reg = DSPCNTR(plane);
1874 dspcntr = I915_READ(reg);
1875 /* Mask out pixel format bits in case we change it */
1876 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1877 switch (fb->bits_per_pixel) {
1878 case 8:
1879 dspcntr |= DISPPLANE_8BPP;
1880 break;
1881 case 16:
1882 if (fb->depth != 16)
1883 return -EINVAL;
1884
1885 dspcntr |= DISPPLANE_16BPP;
1886 break;
1887 case 24:
1888 case 32:
1889 if (fb->depth == 24)
1890 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1891 else if (fb->depth == 30)
1892 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1893 else
1894 return -EINVAL;
1895 break;
1896 default:
1897 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1898 return -EINVAL;
1899 }
1900
1901 if (obj->tiling_mode != I915_TILING_NONE)
1902 dspcntr |= DISPPLANE_TILED;
1903 else
1904 dspcntr &= ~DISPPLANE_TILED;
1905
1906 /* must disable */
1907 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1908
1909 I915_WRITE(reg, dspcntr);
1910
1911 Start = obj->gtt_offset;
01f2c773 1912 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1913
1914 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1915 Start, Offset, x, y, fb->pitches[0]);
1916 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1917 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1918 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1919 I915_WRITE(DSPADDR(plane), Offset);
1920 POSTING_READ(reg);
1921
1922 return 0;
1923}
1924
1925/* Assume fb object is pinned & idle & fenced and just update base pointers */
1926static int
1927intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1928 int x, int y, enum mode_set_atomic state)
1929{
1930 struct drm_device *dev = crtc->dev;
1931 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1932
6b8e6ed0
CW		 1933 if (dev_priv->display.disable_fbc)
1934 dev_priv->display.disable_fbc(dev);
3dec0095 1935 intel_increase_pllclock(crtc);
81255565 1936
6b8e6ed0 1937 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1938}
1939
14667a4b
CW		 1940static int
1941intel_finish_fb(struct drm_framebuffer *old_fb)
1942{
1943 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1944 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1945 bool was_interruptible = dev_priv->mm.interruptible;
1946 int ret;
1947
1948 wait_event(dev_priv->pending_flip_queue,
1949 atomic_read(&dev_priv->mm.wedged) ||
1950 atomic_read(&obj->pending_flip) == 0);
1951
1952 /* Big Hammer, we also need to ensure that any pending
1953 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1954 * current scanout is retired before unpinning the old
1955 * framebuffer.
1956 *
1957 * This should only fail upon a hung GPU, in which case we
1958 * can safely continue.
1959 */
1960 dev_priv->mm.interruptible = false;
1961 ret = i915_gem_object_finish_gpu(obj);
1962 dev_priv->mm.interruptible = was_interruptible;
1963
1964 return ret;
1965}
1966
5c3b82e2 1967static int
3c4fdcfb
KH		 1968intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1969 struct drm_framebuffer *old_fb)
79e53945
JB		 1970{
1971 struct drm_device *dev = crtc->dev;
6b8e6ed0 1972 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1973 struct drm_i915_master_private *master_priv;
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1975 int ret;
79e53945
JB		 1976
1977 /* no fb bound */
1978 if (!crtc->fb) {
a5071c2f 1979 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 1980 return 0;
1981 }
1982
5826eca5
ED		 1983 if(intel_crtc->plane > dev_priv->num_pipe) {
1984 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
1985 intel_crtc->plane,
1986 dev_priv->num_pipe);
5c3b82e2 1987 return -EINVAL;
79e53945
JB		 1988 }
1989
5c3b82e2 1990 mutex_lock(&dev->struct_mutex);
265db958
CW		 1991 ret = intel_pin_and_fence_fb_obj(dev,
1992 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1993 NULL);
5c3b82e2
CW		 1994 if (ret != 0) {
1995 mutex_unlock(&dev->struct_mutex);
a5071c2f 1996 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 1997 return ret;
1998 }
79e53945 1999
14667a4b
CW		 2000 if (old_fb)
2001 intel_finish_fb(old_fb);
265db958 2002
6b8e6ed0 2003 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2004 if (ret) {
1690e1eb 2005 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2006 mutex_unlock(&dev->struct_mutex);
a5071c2f 2007 DRM_ERROR("failed to update base address\n");
4e6cfefc 2008 return ret;
79e53945 2009 }
3c4fdcfb 2010
b7f1de28
CW		 2011 if (old_fb) {
2012 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2013 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2014 }
652c393a 2015
6b8e6ed0 2016 intel_update_fbc(dev);
5c3b82e2 2017 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2018
2019 if (!dev->primary->master)
5c3b82e2 2020 return 0;
79e53945
JB		 2021
2022 master_priv = dev->primary->master->driver_priv;
2023 if (!master_priv->sarea_priv)
5c3b82e2 2024 return 0;
79e53945 2025
265db958 2026 if (intel_crtc->pipe) {
79e53945
JB		 2027 master_priv->sarea_priv->pipeB_x = x;
2028 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2029 } else {
2030 master_priv->sarea_priv->pipeA_x = x;
2031 master_priv->sarea_priv->pipeA_y = y;
79e53945 2032 }
5c3b82e2
CW		 2033
2034 return 0;
79e53945
JB		 2035}
2036
5eddb70b 2037static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2038{
2039 struct drm_device *dev = crtc->dev;
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 u32 dpa_ctl;
2042
28c97730 2043 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2044 dpa_ctl = I915_READ(DP_A);
2045 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2046
2047 if (clock < 200000) {
2048 u32 temp;
2049 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2050 /* workaround for 160Mhz:
2051 1) program 0x4600c bits 15:0 = 0x8124
2052 2) program 0x46010 bit 0 = 1
2053 3) program 0x46034 bit 24 = 1
2054 4) program 0x64000 bit 14 = 1
2055 */
2056 temp = I915_READ(0x4600c);
2057 temp &= 0xffff0000;
2058 I915_WRITE(0x4600c, temp | 0x8124);
2059
2060 temp = I915_READ(0x46010);
2061 I915_WRITE(0x46010, temp | 1);
2062
2063 temp = I915_READ(0x46034);
2064 I915_WRITE(0x46034, temp | (1 << 24));
2065 } else {
2066 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2067 }
2068 I915_WRITE(DP_A, dpa_ctl);
2069
5eddb70b 2070 POSTING_READ(DP_A);
32f9d658
ZW		 2071 udelay(500);
2072}
2073
5e84e1a4
ZW		 2074static void intel_fdi_normal_train(struct drm_crtc *crtc)
2075{
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 int pipe = intel_crtc->pipe;
2080 u32 reg, temp;
2081
2082 /* enable normal train */
2083 reg = FDI_TX_CTL(pipe);
2084 temp = I915_READ(reg);
61e499bf 2085 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2086 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2087 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2088 } else {
2089 temp &= ~FDI_LINK_TRAIN_NONE;
2090 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2091 }
5e84e1a4
ZW		 2092 I915_WRITE(reg, temp);
2093
2094 reg = FDI_RX_CTL(pipe);
2095 temp = I915_READ(reg);
2096 if (HAS_PCH_CPT(dev)) {
2097 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2098 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2099 } else {
2100 temp &= ~FDI_LINK_TRAIN_NONE;
2101 temp |= FDI_LINK_TRAIN_NONE;
2102 }
2103 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2104
2105 /* wait one idle pattern time */
2106 POSTING_READ(reg);
2107 udelay(1000);
357555c0
JB		 2108
2109 /* IVB wants error correction enabled */
2110 if (IS_IVYBRIDGE(dev))
2111 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2112 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2113}
2114
291427f5
JB		 2115static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2116{
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 u32 flags = I915_READ(SOUTH_CHICKEN1);
2119
2120 flags |= FDI_PHASE_SYNC_OVR(pipe);
2121 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2122 flags |= FDI_PHASE_SYNC_EN(pipe);
2123 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2124 POSTING_READ(SOUTH_CHICKEN1);
2125}
2126
8db9d77b
ZW		 2127/* The FDI link training functions for ILK/Ibexpeak. */
2128static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2129{
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 int pipe = intel_crtc->pipe;
0fc932b8 2134 int plane = intel_crtc->plane;
5eddb70b 2135 u32 reg, temp, tries;
8db9d77b 2136
0fc932b8
JB		 2137 /* FDI needs bits from pipe & plane first */
2138 assert_pipe_enabled(dev_priv, pipe);
2139 assert_plane_enabled(dev_priv, plane);
2140
e1a44743
AJ		 2141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2142 for train result */
5eddb70b
CW		 2143 reg = FDI_RX_IMR(pipe);
2144 temp = I915_READ(reg);
e1a44743
AJ		 2145 temp &= ~FDI_RX_SYMBOL_LOCK;
2146 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2147 I915_WRITE(reg, temp);
2148 I915_READ(reg);
e1a44743
AJ		 2149 udelay(150);
2150
8db9d77b 2151 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2152 reg = FDI_TX_CTL(pipe);
2153 temp = I915_READ(reg);
77ffb597
AJ		 2154 temp &= ~(7 << 19);
2155 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2156 temp &= ~FDI_LINK_TRAIN_NONE;
2157 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2158 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2159
5eddb70b
CW		 2160 reg = FDI_RX_CTL(pipe);
2161 temp = I915_READ(reg);
8db9d77b
ZW		 2162 temp &= ~FDI_LINK_TRAIN_NONE;
2163 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2164 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2165
2166 POSTING_READ(reg);
8db9d77b
ZW		 2167 udelay(150);
2168
5b2adf89 2169 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2170 if (HAS_PCH_IBX(dev)) {
2171 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2172 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2173 FDI_RX_PHASE_SYNC_POINTER_EN);
2174 }
5b2adf89 2175
5eddb70b 2176 reg = FDI_RX_IIR(pipe);
e1a44743 2177 for (tries = 0; tries < 5; tries++) {
5eddb70b 2178 temp = I915_READ(reg);
8db9d77b
ZW		 2179 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2180
2181 if ((temp & FDI_RX_BIT_LOCK)) {
2182 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2183 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2184 break;
2185 }
8db9d77b 2186 }
e1a44743 2187 if (tries == 5)
5eddb70b 2188 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2189
2190 /* Train 2 */
5eddb70b
CW		 2191 reg = FDI_TX_CTL(pipe);
2192 temp = I915_READ(reg);
8db9d77b
ZW		 2193 temp &= ~FDI_LINK_TRAIN_NONE;
2194 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2195 I915_WRITE(reg, temp);
8db9d77b 2196
5eddb70b
CW		 2197 reg = FDI_RX_CTL(pipe);
2198 temp = I915_READ(reg);
8db9d77b
ZW		 2199 temp &= ~FDI_LINK_TRAIN_NONE;
2200 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2201 I915_WRITE(reg, temp);
8db9d77b 2202
5eddb70b
CW		 2203 POSTING_READ(reg);
2204 udelay(150);
8db9d77b 2205
5eddb70b 2206 reg = FDI_RX_IIR(pipe);
e1a44743 2207 for (tries = 0; tries < 5; tries++) {
5eddb70b 2208 temp = I915_READ(reg);
8db9d77b
ZW		 2209 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2210
2211 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2212 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2213 DRM_DEBUG_KMS("FDI train 2 done.\n");
2214 break;
2215 }
8db9d77b 2216 }
e1a44743 2217 if (tries == 5)
5eddb70b 2218 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2219
2220 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2221
8db9d77b
ZW		 2222}
2223
0206e353 2224static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2225 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2226 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2227 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2228 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2229};
2230
2231/* The FDI link training functions for SNB/Cougarpoint. */
2232static void gen6_fdi_link_train(struct drm_crtc *crtc)
2233{
2234 struct drm_device *dev = crtc->dev;
2235 struct drm_i915_private *dev_priv = dev->dev_private;
2236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2237 int pipe = intel_crtc->pipe;
fa37d39e 2238 u32 reg, temp, i, retry;
8db9d77b 2239
e1a44743
AJ		 2240 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2241 for train result */
5eddb70b
CW		 2242 reg = FDI_RX_IMR(pipe);
2243 temp = I915_READ(reg);
e1a44743
AJ		 2244 temp &= ~FDI_RX_SYMBOL_LOCK;
2245 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2246 I915_WRITE(reg, temp);
2247
2248 POSTING_READ(reg);
e1a44743
AJ		 2249 udelay(150);
2250
8db9d77b 2251 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2252 reg = FDI_TX_CTL(pipe);
2253 temp = I915_READ(reg);
77ffb597
AJ		 2254 temp &= ~(7 << 19);
2255 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2256 temp &= ~FDI_LINK_TRAIN_NONE;
2257 temp |= FDI_LINK_TRAIN_PATTERN_1;
2258 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2259 /* SNB-B */
2260 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2261 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2262
5eddb70b
CW		 2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
8db9d77b
ZW		 2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2268 } else {
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_PATTERN_1;
2271 }
5eddb70b
CW		 2272 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2273
2274 POSTING_READ(reg);
8db9d77b
ZW		 2275 udelay(150);
2276
291427f5
JB		 2277 if (HAS_PCH_CPT(dev))
2278 cpt_phase_pointer_enable(dev, pipe);
2279
0206e353 2280 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2281 reg = FDI_TX_CTL(pipe);
2282 temp = I915_READ(reg);
8db9d77b
ZW		 2283 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2284 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2285 I915_WRITE(reg, temp);
2286
2287 POSTING_READ(reg);
8db9d77b
ZW		 2288 udelay(500);
2289
fa37d39e
SP		 2290 for (retry = 0; retry < 5; retry++) {
2291 reg = FDI_RX_IIR(pipe);
2292 temp = I915_READ(reg);
2293 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2294 if (temp & FDI_RX_BIT_LOCK) {
2295 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2296 DRM_DEBUG_KMS("FDI train 1 done.\n");
2297 break;
2298 }
2299 udelay(50);
8db9d77b 2300 }
fa37d39e
SP		 2301 if (retry < 5)
2302 break;
8db9d77b
ZW		 2303 }
2304 if (i == 4)
5eddb70b 2305 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2306
2307 /* Train 2 */
5eddb70b
CW		 2308 reg = FDI_TX_CTL(pipe);
2309 temp = I915_READ(reg);
8db9d77b
ZW		 2310 temp &= ~FDI_LINK_TRAIN_NONE;
2311 temp |= FDI_LINK_TRAIN_PATTERN_2;
2312 if (IS_GEN6(dev)) {
2313 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2314 /* SNB-B */
2315 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2316 }
5eddb70b 2317 I915_WRITE(reg, temp);
8db9d77b 2318
5eddb70b
CW		 2319 reg = FDI_RX_CTL(pipe);
2320 temp = I915_READ(reg);
8db9d77b
ZW		 2321 if (HAS_PCH_CPT(dev)) {
2322 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2323 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2324 } else {
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_PATTERN_2;
2327 }
5eddb70b
CW		 2328 I915_WRITE(reg, temp);
2329
2330 POSTING_READ(reg);
8db9d77b
ZW		 2331 udelay(150);
2332
0206e353 2333 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
8db9d77b
ZW		 2336 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2338 I915_WRITE(reg, temp);
2339
2340 POSTING_READ(reg);
8db9d77b
ZW		 2341 udelay(500);
2342
fa37d39e
SP		 2343 for (retry = 0; retry < 5; retry++) {
2344 reg = FDI_RX_IIR(pipe);
2345 temp = I915_READ(reg);
2346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2347 if (temp & FDI_RX_SYMBOL_LOCK) {
2348 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2349 DRM_DEBUG_KMS("FDI train 2 done.\n");
2350 break;
2351 }
2352 udelay(50);
8db9d77b 2353 }
fa37d39e
SP		 2354 if (retry < 5)
2355 break;
8db9d77b
ZW		 2356 }
2357 if (i == 4)
5eddb70b 2358 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2359
2360 DRM_DEBUG_KMS("FDI train done.\n");
2361}
2362
357555c0
JB		 2363/* Manual link training for Ivy Bridge A0 parts */
2364static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2365{
2366 struct drm_device *dev = crtc->dev;
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2369 int pipe = intel_crtc->pipe;
2370 u32 reg, temp, i;
2371
2372 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2373 for train result */
2374 reg = FDI_RX_IMR(pipe);
2375 temp = I915_READ(reg);
2376 temp &= ~FDI_RX_SYMBOL_LOCK;
2377 temp &= ~FDI_RX_BIT_LOCK;
2378 I915_WRITE(reg, temp);
2379
2380 POSTING_READ(reg);
2381 udelay(150);
2382
2383 /* enable CPU FDI TX and PCH FDI RX */
2384 reg = FDI_TX_CTL(pipe);
2385 temp = I915_READ(reg);
2386 temp &= ~(7 << 19);
2387 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2388 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2389 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2390 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2391 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2392 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_AUTO;
2398 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2399 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2400 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2401 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2402
2403 POSTING_READ(reg);
2404 udelay(150);
2405
291427f5
JB		 2406 if (HAS_PCH_CPT(dev))
2407 cpt_phase_pointer_enable(dev, pipe);
2408
0206e353 2409 for (i = 0; i < 4; i++) {
357555c0
JB		 2410 reg = FDI_TX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2413 temp |= snb_b_fdi_train_param[i];
2414 I915_WRITE(reg, temp);
2415
2416 POSTING_READ(reg);
2417 udelay(500);
2418
2419 reg = FDI_RX_IIR(pipe);
2420 temp = I915_READ(reg);
2421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2422
2423 if (temp & FDI_RX_BIT_LOCK ||
2424 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
2427 break;
2428 }
2429 }
2430 if (i == 4)
2431 DRM_ERROR("FDI train 1 fail!\n");
2432
2433 /* Train 2 */
2434 reg = FDI_TX_CTL(pipe);
2435 temp = I915_READ(reg);
2436 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2437 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2438 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2439 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2440 I915_WRITE(reg, temp);
2441
2442 reg = FDI_RX_CTL(pipe);
2443 temp = I915_READ(reg);
2444 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2446 I915_WRITE(reg, temp);
2447
2448 POSTING_READ(reg);
2449 udelay(150);
2450
0206e353 2451 for (i = 0; i < 4; i++) {
357555c0
JB		 2452 reg = FDI_TX_CTL(pipe);
2453 temp = I915_READ(reg);
2454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2455 temp |= snb_b_fdi_train_param[i];
2456 I915_WRITE(reg, temp);
2457
2458 POSTING_READ(reg);
2459 udelay(500);
2460
2461 reg = FDI_RX_IIR(pipe);
2462 temp = I915_READ(reg);
2463 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464
2465 if (temp & FDI_RX_SYMBOL_LOCK) {
2466 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2467 DRM_DEBUG_KMS("FDI train 2 done.\n");
2468 break;
2469 }
2470 }
2471 if (i == 4)
2472 DRM_ERROR("FDI train 2 fail!\n");
2473
2474 DRM_DEBUG_KMS("FDI train done.\n");
2475}
2476
2477static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2478{
2479 struct drm_device *dev = crtc->dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482 int pipe = intel_crtc->pipe;
5eddb70b 2483 u32 reg, temp;
79e53945 2484
c64e311e 2485 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2486 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2487 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2488
c98e9dcf 2489 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2490 reg = FDI_RX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2493 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2494 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2495 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2496
2497 POSTING_READ(reg);
c98e9dcf
JB		 2498 udelay(200);
2499
2500 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2501 temp = I915_READ(reg);
2502 I915_WRITE(reg, temp | FDI_PCDCLK);
2503
2504 POSTING_READ(reg);
c98e9dcf
JB		 2505 udelay(200);
2506
2507 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
c98e9dcf 2510 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2511 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2512
2513 POSTING_READ(reg);
c98e9dcf 2514 udelay(100);
6be4a607 2515 }
0e23b99d
JB		 2516}
2517
291427f5
JB		 2518static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2519{
2520 struct drm_i915_private *dev_priv = dev->dev_private;
2521 u32 flags = I915_READ(SOUTH_CHICKEN1);
2522
2523 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2524 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2525 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2526 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2527 POSTING_READ(SOUTH_CHICKEN1);
2528}
0fc932b8
JB		 2529static void ironlake_fdi_disable(struct drm_crtc *crtc)
2530{
2531 struct drm_device *dev = crtc->dev;
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534 int pipe = intel_crtc->pipe;
2535 u32 reg, temp;
2536
2537 /* disable CPU FDI tx and PCH FDI rx */
2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2541 POSTING_READ(reg);
2542
2543 reg = FDI_RX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~(0x7 << 16);
2546 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2547 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2548
2549 POSTING_READ(reg);
2550 udelay(100);
2551
2552 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2553 if (HAS_PCH_IBX(dev)) {
2554 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2555 I915_WRITE(FDI_RX_CHICKEN(pipe),
2556 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2557 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2558 } else if (HAS_PCH_CPT(dev)) {
2559 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2560 }
0fc932b8
JB		 2561
2562 /* still set train pattern 1 */
2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_1;
2567 I915_WRITE(reg, temp);
2568
2569 reg = FDI_RX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 if (HAS_PCH_CPT(dev)) {
2572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2574 } else {
2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1;
2577 }
2578 /* BPC in FDI rx is consistent with that in PIPECONF */
2579 temp &= ~(0x07 << 16);
2580 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2581 I915_WRITE(reg, temp);
2582
2583 POSTING_READ(reg);
2584 udelay(100);
2585}
2586
e6c3a2a6
CW		 2587static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2588{
0f91128d 2589 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2590
2591 if (crtc->fb == NULL)
2592 return;
2593
0f91128d
CW		 2594 mutex_lock(&dev->struct_mutex);
2595 intel_finish_fb(crtc->fb);
2596 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2597}
2598
040484af
JB		 2599static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_mode_config *mode_config = &dev->mode_config;
2603 struct intel_encoder *encoder;
2604
2605 /*
2606 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2607 * must be driven by its own crtc; no sharing is possible.
2608 */
2609 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2610 if (encoder->base.crtc != crtc)
2611 continue;
2612
2613 switch (encoder->type) {
2614 case INTEL_OUTPUT_EDP:
2615 if (!intel_encoder_is_pch_edp(&encoder->base))
2616 return false;
2617 continue;
2618 }
2619 }
2620
2621 return true;
2622}
2623
f67a559d
JB		 2624/*
2625 * Enable PCH resources required for PCH ports:
2626 * - PCH PLLs
2627 * - FDI training & RX/TX
2628 * - update transcoder timings
2629 * - DP transcoding bits
2630 * - transcoder
2631 */
2632static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
ee7b9f93 2638 u32 reg, temp;
2c07245f 2639
c98e9dcf 2640 /* For PCH output, training FDI link */
674cf967 2641 dev_priv->display.fdi_link_train(crtc);
2c07245f 2642
ee7b9f93 2643 intel_enable_pch_pll(intel_crtc);
8db9d77b 2644
c98e9dcf 2645 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2646 u32 sel;
4b645f14 2647
c98e9dcf 2648 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2649 switch (pipe) {
2650 default:
2651 case 0:
2652 temp |= TRANSA_DPLL_ENABLE;
2653 sel = TRANSA_DPLLB_SEL;
2654 break;
2655 case 1:
2656 temp |= TRANSB_DPLL_ENABLE;
2657 sel = TRANSB_DPLLB_SEL;
2658 break;
2659 case 2:
2660 temp |= TRANSC_DPLL_ENABLE;
2661 sel = TRANSC_DPLLB_SEL;
2662 break;
d64311ab 2663 }
ee7b9f93
JB		 2664 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2665 temp |= sel;
2666 else
2667 temp &= ~sel;
c98e9dcf 2668 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2669 }
5eddb70b 2670
d9b6cb56
JB		 2671 /* set transcoder timing, panel must allow it */
2672 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2673 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2674 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2675 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2676
5eddb70b
CW		 2677 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2678 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2679 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2680 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2681
f57e1e3a
ED		 2682 if (!IS_HASWELL(dev))
2683 intel_fdi_normal_train(crtc);
5e84e1a4 2684
c98e9dcf
JB		 2685 /* For PCH DP, enable TRANS_DP_CTL */
2686 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2687 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2688 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2689 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2690 reg = TRANS_DP_CTL(pipe);
2691 temp = I915_READ(reg);
2692 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2693 TRANS_DP_SYNC_MASK |
2694 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2695 temp |= (TRANS_DP_OUTPUT_ENABLE |
2696 TRANS_DP_ENH_FRAMING);
9325c9f0 2697 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2698
2699 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2700 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2701 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2702 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2703
2704 switch (intel_trans_dp_port_sel(crtc)) {
2705 case PCH_DP_B:
5eddb70b 2706 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2707 break;
2708 case PCH_DP_C:
5eddb70b 2709 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2710 break;
2711 case PCH_DP_D:
5eddb70b 2712 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2713 break;
2714 default:
2715 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2716 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2717 break;
32f9d658 2718 }
2c07245f 2719
5eddb70b 2720 I915_WRITE(reg, temp);
6be4a607 2721 }
b52eb4dc 2722
040484af 2723 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2724}
2725
ee7b9f93
JB		 2726static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2727{
2728 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2729
2730 if (pll == NULL)
2731 return;
2732
2733 if (pll->refcount == 0) {
2734 WARN(1, "bad PCH PLL refcount\n");
2735 return;
2736 }
2737
2738 --pll->refcount;
2739 intel_crtc->pch_pll = NULL;
2740}
2741
2742static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2743{
2744 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2745 struct intel_pch_pll *pll;
2746 int i;
2747
2748 pll = intel_crtc->pch_pll;
2749 if (pll) {
2750 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2751 intel_crtc->base.base.id, pll->pll_reg);
2752 goto prepare;
2753 }
2754
2755 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2756 pll = &dev_priv->pch_plls[i];
2757
2758 /* Only want to check enabled timings first */
2759 if (pll->refcount == 0)
2760 continue;
2761
2762 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2763 fp == I915_READ(pll->fp0_reg)) {
2764 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2765 intel_crtc->base.base.id,
2766 pll->pll_reg, pll->refcount, pll->active);
2767
2768 goto found;
2769 }
2770 }
2771
2772 /* Ok no matching timings, maybe there's a free one? */
2773 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2774 pll = &dev_priv->pch_plls[i];
2775 if (pll->refcount == 0) {
2776 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2777 intel_crtc->base.base.id, pll->pll_reg);
2778 goto found;
2779 }
2780 }
2781
2782 return NULL;
2783
2784found:
2785 intel_crtc->pch_pll = pll;
2786 pll->refcount++;
2787 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2788prepare: /* separate function? */
2789 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2790
e04c7350
CW		 2791 /* Wait for the clocks to stabilize before rewriting the regs */
2792 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2793 POSTING_READ(pll->pll_reg);
2794 udelay(150);
e04c7350
CW		 2795
2796 I915_WRITE(pll->fp0_reg, fp);
2797 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2798 pll->on = false;
2799 return pll;
2800}
2801
d4270e57
JB		 2802void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2803{
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2806 u32 temp;
2807
2808 temp = I915_READ(dslreg);
2809 udelay(500);
2810 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2811 /* Without this, mode sets may fail silently on FDI */
2812 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2813 udelay(250);
2814 I915_WRITE(tc2reg, 0);
2815 if (wait_for(I915_READ(dslreg) != temp, 5))
2816 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2817 }
2818}
2819
f67a559d
JB		 2820static void ironlake_crtc_enable(struct drm_crtc *crtc)
2821{
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 int plane = intel_crtc->plane;
2827 u32 temp;
2828 bool is_pch_port;
2829
2830 if (intel_crtc->active)
2831 return;
2832
2833 intel_crtc->active = true;
2834 intel_update_watermarks(dev);
2835
2836 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2837 temp = I915_READ(PCH_LVDS);
2838 if ((temp & LVDS_PORT_EN) == 0)
2839 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2840 }
2841
2842 is_pch_port = intel_crtc_driving_pch(crtc);
2843
2844 if (is_pch_port)
357555c0 2845 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2846 else
2847 ironlake_fdi_disable(crtc);
2848
2849 /* Enable panel fitting for LVDS */
2850 if (dev_priv->pch_pf_size &&
2851 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2852 /* Force use of hard-coded filter coefficients
2853 * as some pre-programmed values are broken,
2854 * e.g. x201.
2855 */
9db4a9c7
JB		 2856 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2857 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2858 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2859 }
2860
9c54c0dd
JB		 2861 /*
2862 * On ILK+ LUT must be loaded before the pipe is running but with
2863 * clocks enabled
2864 */
2865 intel_crtc_load_lut(crtc);
2866
f67a559d
JB		 2867 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2868 intel_enable_plane(dev_priv, plane, pipe);
2869
2870 if (is_pch_port)
2871 ironlake_pch_enable(crtc);
c98e9dcf 2872
d1ebd816 2873 mutex_lock(&dev->struct_mutex);
bed4a673 2874 intel_update_fbc(dev);
d1ebd816
BW		 2875 mutex_unlock(&dev->struct_mutex);
2876
6b383a7f 2877 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2878}
2879
2880static void ironlake_crtc_disable(struct drm_crtc *crtc)
2881{
2882 struct drm_device *dev = crtc->dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 int pipe = intel_crtc->pipe;
2886 int plane = intel_crtc->plane;
5eddb70b 2887 u32 reg, temp;
b52eb4dc 2888
f7abfe8b
CW		 2889 if (!intel_crtc->active)
2890 return;
2891
e6c3a2a6 2892 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2893 drm_vblank_off(dev, pipe);
6b383a7f 2894 intel_crtc_update_cursor(crtc, false);
5eddb70b 2895
b24e7179 2896 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2897
973d04f9
CW		 2898 if (dev_priv->cfb_plane == plane)
2899 intel_disable_fbc(dev);
2c07245f 2900
b24e7179 2901 intel_disable_pipe(dev_priv, pipe);
32f9d658 2902
6be4a607 2903 /* Disable PF */
9db4a9c7
JB		 2904 I915_WRITE(PF_CTL(pipe), 0);
2905 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2906
0fc932b8 2907 ironlake_fdi_disable(crtc);
2c07245f 2908
47a05eca
JB		 2909 /* This is a horrible layering violation; we should be doing this in
2910 * the connector/encoder ->prepare instead, but we don't always have
2911 * enough information there about the config to know whether it will
2912 * actually be necessary or just cause undesired flicker.
2913 */
2914 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2915
040484af 2916 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2917
6be4a607
JB		 2918 if (HAS_PCH_CPT(dev)) {
2919 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2920 reg = TRANS_DP_CTL(pipe);
2921 temp = I915_READ(reg);
2922 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2923 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2924 I915_WRITE(reg, temp);
6be4a607
JB		 2925
2926 /* disable DPLL_SEL */
2927 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2928 switch (pipe) {
2929 case 0:
d64311ab 2930 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 2931 break;
2932 case 1:
6be4a607 2933 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2934 break;
2935 case 2:
4b645f14 2936 /* C shares PLL A or B */
d64311ab 2937 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 2938 break;
2939 default:
2940 BUG(); /* wtf */
2941 }
6be4a607 2942 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2943 }
e3421a18 2944
6be4a607 2945 /* disable PCH DPLL */
ee7b9f93 2946 intel_disable_pch_pll(intel_crtc);
8db9d77b 2947
6be4a607 2948 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2949 reg = FDI_RX_CTL(pipe);
2950 temp = I915_READ(reg);
2951 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2952
6be4a607 2953 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2954 reg = FDI_TX_CTL(pipe);
2955 temp = I915_READ(reg);
2956 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2957
2958 POSTING_READ(reg);
6be4a607 2959 udelay(100);
8db9d77b 2960
5eddb70b
CW		 2961 reg = FDI_RX_CTL(pipe);
2962 temp = I915_READ(reg);
2963 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2964
6be4a607 2965 /* Wait for the clocks to turn off. */
5eddb70b 2966 POSTING_READ(reg);
6be4a607 2967 udelay(100);
6b383a7f 2968
f7abfe8b 2969 intel_crtc->active = false;
6b383a7f 2970 intel_update_watermarks(dev);
d1ebd816
BW		 2971
2972 mutex_lock(&dev->struct_mutex);
6b383a7f 2973 intel_update_fbc(dev);
d1ebd816 2974 mutex_unlock(&dev->struct_mutex);
6be4a607 2975}
1b3c7a47 2976
6be4a607
JB		 2977static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2978{
2979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2980 int pipe = intel_crtc->pipe;
2981 int plane = intel_crtc->plane;
8db9d77b 2982
6be4a607
JB		 2983 /* XXX: When our outputs are all unaware of DPMS modes other than off
2984 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2985 */
2986 switch (mode) {
2987 case DRM_MODE_DPMS_ON:
2988 case DRM_MODE_DPMS_STANDBY:
2989 case DRM_MODE_DPMS_SUSPEND:
2990 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2991 ironlake_crtc_enable(crtc);
2992 break;
1b3c7a47 2993
6be4a607
JB		 2994 case DRM_MODE_DPMS_OFF:
2995 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2996 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2997 break;
2998 }
2999}
3000
ee7b9f93
JB		 3001static void ironlake_crtc_off(struct drm_crtc *crtc)
3002{
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004 intel_put_pch_pll(intel_crtc);
3005}
3006
02e792fb
DV		 3007static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3008{
02e792fb 3009 if (!enable && intel_crtc->overlay) {
23f09ce3 3010 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3011 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3012
23f09ce3 3013 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3014 dev_priv->mm.interruptible = false;
3015 (void) intel_overlay_switch_off(intel_crtc->overlay);
3016 dev_priv->mm.interruptible = true;
23f09ce3 3017 mutex_unlock(&dev->struct_mutex);
02e792fb 3018 }
02e792fb 3019
5dcdbcb0
CW		 3020 /* Let userspace switch the overlay on again. In most cases userspace
3021 * has to recompute where to put it anyway.
3022 */
02e792fb
DV		 3023}
3024
0b8765c6 3025static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3026{
3027 struct drm_device *dev = crtc->dev;
79e53945
JB		 3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3030 int pipe = intel_crtc->pipe;
80824003 3031 int plane = intel_crtc->plane;
79e53945 3032
f7abfe8b
CW		 3033 if (intel_crtc->active)
3034 return;
3035
3036 intel_crtc->active = true;
6b383a7f
CW		 3037 intel_update_watermarks(dev);
3038
63d7bbe9 3039 intel_enable_pll(dev_priv, pipe);
040484af 3040 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3041 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3042
0b8765c6 3043 intel_crtc_load_lut(crtc);
bed4a673 3044 intel_update_fbc(dev);
79e53945 3045
0b8765c6
JB		 3046 /* Give the overlay scaler a chance to enable if it's on this pipe */
3047 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3048 intel_crtc_update_cursor(crtc, true);
0b8765c6 3049}
79e53945 3050
0b8765c6
JB		 3051static void i9xx_crtc_disable(struct drm_crtc *crtc)
3052{
3053 struct drm_device *dev = crtc->dev;
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3056 int pipe = intel_crtc->pipe;
3057 int plane = intel_crtc->plane;
b690e96c 3058
f7abfe8b
CW		 3059 if (!intel_crtc->active)
3060 return;
3061
0b8765c6 3062 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3063 intel_crtc_wait_for_pending_flips(crtc);
3064 drm_vblank_off(dev, pipe);
0b8765c6 3065 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3066 intel_crtc_update_cursor(crtc, false);
0b8765c6 3067
973d04f9
CW		 3068 if (dev_priv->cfb_plane == plane)
3069 intel_disable_fbc(dev);
79e53945 3070
b24e7179 3071 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3072 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3073 intel_disable_pll(dev_priv, pipe);
0b8765c6 3074
f7abfe8b 3075 intel_crtc->active = false;
6b383a7f
CW		 3076 intel_update_fbc(dev);
3077 intel_update_watermarks(dev);
0b8765c6
JB		 3078}
3079
3080static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3081{
3082 /* XXX: When our outputs are all unaware of DPMS modes other than off
3083 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3084 */
3085 switch (mode) {
3086 case DRM_MODE_DPMS_ON:
3087 case DRM_MODE_DPMS_STANDBY:
3088 case DRM_MODE_DPMS_SUSPEND:
3089 i9xx_crtc_enable(crtc);
3090 break;
3091 case DRM_MODE_DPMS_OFF:
3092 i9xx_crtc_disable(crtc);
79e53945
JB		 3093 break;
3094 }
2c07245f
ZW		 3095}
3096
ee7b9f93
JB		 3097static void i9xx_crtc_off(struct drm_crtc *crtc)
3098{
3099}
3100
2c07245f
ZW		 3101/**
3102 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3103 */
3104static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3105{
3106 struct drm_device *dev = crtc->dev;
e70236a8 3107 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3108 struct drm_i915_master_private *master_priv;
3109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110 int pipe = intel_crtc->pipe;
3111 bool enabled;
3112
032d2a0d
CW		 3113 if (intel_crtc->dpms_mode == mode)
3114 return;
3115
65655d4a 3116 intel_crtc->dpms_mode = mode;
debcaddc 3117
e70236a8 3118 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3119
3120 if (!dev->primary->master)
3121 return;
3122
3123 master_priv = dev->primary->master->driver_priv;
3124 if (!master_priv->sarea_priv)
3125 return;
3126
3127 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3128
3129 switch (pipe) {
3130 case 0:
3131 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3132 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3133 break;
3134 case 1:
3135 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3136 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3137 break;
3138 default:
9db4a9c7 3139 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3140 break;
3141 }
79e53945
JB		 3142}
3143
cdd59983
CW		 3144static void intel_crtc_disable(struct drm_crtc *crtc)
3145{
3146 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3147 struct drm_device *dev = crtc->dev;
ee7b9f93 3148 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3149
3150 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3151 dev_priv->display.off(crtc);
3152
931872fc
CW		 3153 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3154 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3155
3156 if (crtc->fb) {
3157 mutex_lock(&dev->struct_mutex);
1690e1eb 3158 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3159 mutex_unlock(&dev->struct_mutex);
3160 }
3161}
3162
7e7d76c3
JB		 3163/* Prepare for a mode set.
3164 *
3165 * Note we could be a lot smarter here. We need to figure out which outputs
3166 * will be enabled, which disabled (in short, how the config will changes)
3167 * and perform the minimum necessary steps to accomplish that, e.g. updating
3168 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3169 * panel fitting is in the proper state, etc.
3170 */
3171static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3172{
7e7d76c3 3173 i9xx_crtc_disable(crtc);
79e53945
JB		 3174}
3175
7e7d76c3 3176static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3177{
7e7d76c3 3178 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3179}
3180
3181static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3182{
7e7d76c3 3183 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3184}
3185
3186static void ironlake_crtc_commit(struct drm_crtc *crtc)
3187{
7e7d76c3 3188 ironlake_crtc_enable(crtc);
79e53945
JB		 3189}
3190
0206e353 3191void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3192{
3193 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3194 /* lvds has its own version of prepare see intel_lvds_prepare */
3195 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3196}
3197
0206e353 3198void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3199{
3200 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3201 struct drm_device *dev = encoder->dev;
d47d7cb8 3202 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3203
79e53945
JB		 3204 /* lvds has its own version of commit see intel_lvds_commit */
3205 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3206
3207 if (HAS_PCH_CPT(dev))
3208 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3209}
3210
ea5b213a
CW		 3211void intel_encoder_destroy(struct drm_encoder *encoder)
3212{
4ef69c7a 3213 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3214
ea5b213a
CW		 3215 drm_encoder_cleanup(encoder);
3216 kfree(intel_encoder);
3217}
3218
79e53945
JB		 3219static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3220 struct drm_display_mode *mode,
3221 struct drm_display_mode *adjusted_mode)
3222{
2c07245f 3223 struct drm_device *dev = crtc->dev;
89749350 3224
bad720ff 3225 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3226 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3227 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3228 return false;
2c07245f 3229 }
89749350 3230
f9bef081
DV		 3231 /* All interlaced capable intel hw wants timings in frames. Note though
3232 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3233 * timings, so we need to be careful not to clobber these.*/
3234 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3235 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3236
79e53945
JB		 3237 return true;
3238}
3239
25eb05fc
JB		 3240static int valleyview_get_display_clock_speed(struct drm_device *dev)
3241{
3242 return 400000; /* FIXME */
3243}
3244
e70236a8
JB		 3245static int i945_get_display_clock_speed(struct drm_device *dev)
3246{
3247 return 400000;
3248}
79e53945 3249
e70236a8 3250static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3251{
e70236a8
JB		 3252 return 333000;
3253}
79e53945 3254
e70236a8
JB		 3255static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3256{
3257 return 200000;
3258}
79e53945 3259
e70236a8
JB		 3260static int i915gm_get_display_clock_speed(struct drm_device *dev)
3261{
3262 u16 gcfgc = 0;
79e53945 3263
e70236a8
JB		 3264 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3265
3266 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3267 return 133000;
3268 else {
3269 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3270 case GC_DISPLAY_CLOCK_333_MHZ:
3271 return 333000;
3272 default:
3273 case GC_DISPLAY_CLOCK_190_200_MHZ:
3274 return 190000;
79e53945 3275 }
e70236a8
JB		 3276 }
3277}
3278
3279static int i865_get_display_clock_speed(struct drm_device *dev)
3280{
3281 return 266000;
3282}
3283
3284static int i855_get_display_clock_speed(struct drm_device *dev)
3285{
3286 u16 hpllcc = 0;
3287 /* Assume that the hardware is in the high speed state. This
3288 * should be the default.
3289 */
3290 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3291 case GC_CLOCK_133_200:
3292 case GC_CLOCK_100_200:
3293 return 200000;
3294 case GC_CLOCK_166_250:
3295 return 250000;
3296 case GC_CLOCK_100_133:
79e53945 3297 return 133000;
e70236a8 3298 }
79e53945 3299
e70236a8
JB		 3300 /* Shouldn't happen */
3301 return 0;
3302}
79e53945 3303
e70236a8
JB		 3304static int i830_get_display_clock_speed(struct drm_device *dev)
3305{
3306 return 133000;
79e53945
JB		 3307}
3308
2c07245f
ZW		 3309struct fdi_m_n {
3310 u32 tu;
3311 u32 gmch_m;
3312 u32 gmch_n;
3313 u32 link_m;
3314 u32 link_n;
3315};
3316
3317static void
3318fdi_reduce_ratio(u32 *num, u32 *den)
3319{
3320 while (*num > 0xffffff || *den > 0xffffff) {
3321 *num >>= 1;
3322 *den >>= 1;
3323 }
3324}
3325
2c07245f 3326static void
f2b115e6
AJ		 3327ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3328 int link_clock, struct fdi_m_n *m_n)
2c07245f 3329{
2c07245f
ZW		 3330 m_n->tu = 64; /* default size */
3331
22ed1113
CW		 3332 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3333 m_n->gmch_m = bits_per_pixel * pixel_clock;
3334 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3335 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3336
22ed1113
CW		 3337 m_n->link_m = pixel_clock;
3338 m_n->link_n = link_clock;
2c07245f
ZW		 3339 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3340}
3341
a7615030
CW		 3342static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3343{
72bbe58c
KP		 3344 if (i915_panel_use_ssc >= 0)
3345 return i915_panel_use_ssc != 0;
3346 return dev_priv->lvds_use_ssc
435793df 3347 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3348}
3349
5a354204
JB		 3350/**
3351 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3352 * @crtc: CRTC structure
3b5c78a3 3353 * @mode: requested mode
5a354204
JB		 3354 *
3355 * A pipe may be connected to one or more outputs. Based on the depth of the
3356 * attached framebuffer, choose a good color depth to use on the pipe.
3357 *
3358 * If possible, match the pipe depth to the fb depth. In some cases, this
3359 * isn't ideal, because the connected output supports a lesser or restricted
3360 * set of depths. Resolve that here:
3361 * LVDS typically supports only 6bpc, so clamp down in that case
3362 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3363 * Displays may support a restricted set as well, check EDID and clamp as
3364 * appropriate.
3b5c78a3 3365 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3366 *
3367 * RETURNS:
3368 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3369 * true if they don't match).
3370 */
3371static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3372 unsigned int *pipe_bpp,
3373 struct drm_display_mode *mode)
5a354204
JB		 3374{
3375 struct drm_device *dev = crtc->dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 struct drm_encoder *encoder;
3378 struct drm_connector *connector;
3379 unsigned int display_bpc = UINT_MAX, bpc;
3380
3381 /* Walk the encoders & connectors on this crtc, get min bpc */
3382 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3383 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3384
3385 if (encoder->crtc != crtc)
3386 continue;
3387
3388 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3389 unsigned int lvds_bpc;
3390
3391 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3392 LVDS_A3_POWER_UP)
3393 lvds_bpc = 8;
3394 else
3395 lvds_bpc = 6;
3396
3397 if (lvds_bpc < display_bpc) {
82820490 3398 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3399 display_bpc = lvds_bpc;
3400 }
3401 continue;
3402 }
3403
3404 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3405 /* Use VBT settings if we have an eDP panel */
3406 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3407
3408 if (edp_bpc < display_bpc) {
82820490 3409 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3410 display_bpc = edp_bpc;
3411 }
3412 continue;
3413 }
3414
3415 /* Not one of the known troublemakers, check the EDID */
3416 list_for_each_entry(connector, &dev->mode_config.connector_list,
3417 head) {
3418 if (connector->encoder != encoder)
3419 continue;
3420
62ac41a6
JB		 3421 /* Don't use an invalid EDID bpc value */
3422 if (connector->display_info.bpc &&
3423 connector->display_info.bpc < display_bpc) {
82820490 3424 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3425 display_bpc = connector->display_info.bpc;
3426 }
3427 }
3428
3429 /*
3430 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3431 * through, clamp it down. (Note: >12bpc will be caught below.)
3432 */
3433 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3434 if (display_bpc > 8 && display_bpc < 12) {
82820490 3435 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3436 display_bpc = 12;
3437 } else {
82820490 3438 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3439 display_bpc = 8;
3440 }
3441 }
3442 }
3443
3b5c78a3
AJ		 3444 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3445 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3446 display_bpc = 6;
3447 }
3448
5a354204
JB		 3449 /*
3450 * We could just drive the pipe at the highest bpc all the time and
3451 * enable dithering as needed, but that costs bandwidth. So choose
3452 * the minimum value that expresses the full color range of the fb but
3453 * also stays within the max display bpc discovered above.
3454 */
3455
3456 switch (crtc->fb->depth) {
3457 case 8:
3458 bpc = 8; /* since we go through a colormap */
3459 break;
3460 case 15:
3461 case 16:
3462 bpc = 6; /* min is 18bpp */
3463 break;
3464 case 24:
578393cd 3465 bpc = 8;
5a354204
JB		 3466 break;
3467 case 30:
578393cd 3468 bpc = 10;
5a354204
JB		 3469 break;
3470 case 48:
578393cd 3471 bpc = 12;
5a354204
JB		 3472 break;
3473 default:
3474 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3475 bpc = min((unsigned int)8, display_bpc);
3476 break;
3477 }
3478
578393cd
KP		 3479 display_bpc = min(display_bpc, bpc);
3480
82820490
AJ		 3481 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3482 bpc, display_bpc);
5a354204 3483
578393cd 3484 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3485
3486 return display_bpc != bpc;
3487}
3488
c65d77d8
JB		 3489static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3490{
3491 struct drm_device *dev = crtc->dev;
3492 struct drm_i915_private *dev_priv = dev->dev_private;
3493 int refclk;
3494
3495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3496 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3497 refclk = dev_priv->lvds_ssc_freq * 1000;
3498 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3499 refclk / 1000);
3500 } else if (!IS_GEN2(dev)) {
3501 refclk = 96000;
3502 } else {
3503 refclk = 48000;
3504 }
3505
3506 return refclk;
3507}
3508
3509static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3510 intel_clock_t *clock)
3511{
3512 /* SDVO TV has fixed PLL values depend on its clock range,
3513 this mirrors vbios setting. */
3514 if (adjusted_mode->clock >= 100000
3515 && adjusted_mode->clock < 140500) {
3516 clock->p1 = 2;
3517 clock->p2 = 10;
3518 clock->n = 3;
3519 clock->m1 = 16;
3520 clock->m2 = 8;
3521 } else if (adjusted_mode->clock >= 140500
3522 && adjusted_mode->clock <= 200000) {
3523 clock->p1 = 1;
3524 clock->p2 = 10;
3525 clock->n = 6;
3526 clock->m1 = 12;
3527 clock->m2 = 8;
3528 }
3529}
3530
a7516a05
JB		 3531static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3532 intel_clock_t *clock,
3533 intel_clock_t *reduced_clock)
3534{
3535 struct drm_device *dev = crtc->dev;
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3538 int pipe = intel_crtc->pipe;
3539 u32 fp, fp2 = 0;
3540
3541 if (IS_PINEVIEW(dev)) {
3542 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3543 if (reduced_clock)
3544 fp2 = (1 << reduced_clock->n) << 16 |
3545 reduced_clock->m1 << 8 | reduced_clock->m2;
3546 } else {
3547 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3548 if (reduced_clock)
3549 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3550 reduced_clock->m2;
3551 }
3552
3553 I915_WRITE(FP0(pipe), fp);
3554
3555 intel_crtc->lowfreq_avail = false;
3556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3557 reduced_clock && i915_powersave) {
3558 I915_WRITE(FP1(pipe), fp2);
3559 intel_crtc->lowfreq_avail = true;
3560 } else {
3561 I915_WRITE(FP1(pipe), fp);
3562 }
3563}
3564
93e537a1
DV		 3565static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3566 struct drm_display_mode *adjusted_mode)
3567{
3568 struct drm_device *dev = crtc->dev;
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 int pipe = intel_crtc->pipe;
284d5df5 3572 u32 temp;
93e537a1
DV		 3573
3574 temp = I915_READ(LVDS);
3575 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3576 if (pipe == 1) {
3577 temp |= LVDS_PIPEB_SELECT;
3578 } else {
3579 temp &= ~LVDS_PIPEB_SELECT;
3580 }
3581 /* set the corresponsding LVDS_BORDER bit */
3582 temp |= dev_priv->lvds_border_bits;
3583 /* Set the B0-B3 data pairs corresponding to whether we're going to
3584 * set the DPLLs for dual-channel mode or not.
3585 */
3586 if (clock->p2 == 7)
3587 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3588 else
3589 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3590
3591 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3592 * appropriately here, but we need to look more thoroughly into how
3593 * panels behave in the two modes.
3594 */
3595 /* set the dithering flag on LVDS as needed */
3596 if (INTEL_INFO(dev)->gen >= 4) {
3597 if (dev_priv->lvds_dither)
3598 temp |= LVDS_ENABLE_DITHER;
3599 else
3600 temp &= ~LVDS_ENABLE_DITHER;
3601 }
284d5df5 3602 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3603 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3604 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3605 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3606 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3607 I915_WRITE(LVDS, temp);
3608}
3609
eb1cbe48
DV		 3610static void i9xx_update_pll(struct drm_crtc *crtc,
3611 struct drm_display_mode *mode,
3612 struct drm_display_mode *adjusted_mode,
3613 intel_clock_t *clock, intel_clock_t *reduced_clock,
3614 int num_connectors)
3615{
3616 struct drm_device *dev = crtc->dev;
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619 int pipe = intel_crtc->pipe;
3620 u32 dpll;
3621 bool is_sdvo;
3622
3623 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3624 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3625
3626 dpll = DPLL_VGA_MODE_DIS;
3627
3628 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3629 dpll |= DPLLB_MODE_LVDS;
3630 else
3631 dpll |= DPLLB_MODE_DAC_SERIAL;
3632 if (is_sdvo) {
3633 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3634 if (pixel_multiplier > 1) {
3635 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3636 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3637 }
3638 dpll |= DPLL_DVO_HIGH_SPEED;
3639 }
3640 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3641 dpll |= DPLL_DVO_HIGH_SPEED;
3642
3643 /* compute bitmask from p1 value */
3644 if (IS_PINEVIEW(dev))
3645 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3646 else {
3647 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3648 if (IS_G4X(dev) && reduced_clock)
3649 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3650 }
3651 switch (clock->p2) {
3652 case 5:
3653 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3654 break;
3655 case 7:
3656 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3657 break;
3658 case 10:
3659 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3660 break;
3661 case 14:
3662 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3663 break;
3664 }
3665 if (INTEL_INFO(dev)->gen >= 4)
3666 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3667
3668 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3669 dpll |= PLL_REF_INPUT_TVCLKINBC;
3670 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3671 /* XXX: just matching BIOS for now */
3672 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3673 dpll |= 3;
3674 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3675 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3676 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3677 else
3678 dpll |= PLL_REF_INPUT_DREFCLK;
3679
3680 dpll |= DPLL_VCO_ENABLE;
3681 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3682 POSTING_READ(DPLL(pipe));
3683 udelay(150);
3684
3685 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3686 * This is an exception to the general rule that mode_set doesn't turn
3687 * things on.
3688 */
3689 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3690 intel_update_lvds(crtc, clock, adjusted_mode);
3691
3692 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3693 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3694
3695 I915_WRITE(DPLL(pipe), dpll);
3696
3697 /* Wait for the clocks to stabilize. */
3698 POSTING_READ(DPLL(pipe));
3699 udelay(150);
3700
3701 if (INTEL_INFO(dev)->gen >= 4) {
3702 u32 temp = 0;
3703 if (is_sdvo) {
3704 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3705 if (temp > 1)
3706 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3707 else
3708 temp = 0;
3709 }
3710 I915_WRITE(DPLL_MD(pipe), temp);
3711 } else {
3712 /* The pixel multiplier can only be updated once the
3713 * DPLL is enabled and the clocks are stable.
3714 *
3715 * So write it again.
3716 */
3717 I915_WRITE(DPLL(pipe), dpll);
3718 }
3719}
3720
3721static void i8xx_update_pll(struct drm_crtc *crtc,
3722 struct drm_display_mode *adjusted_mode,
3723 intel_clock_t *clock,
3724 int num_connectors)
3725{
3726 struct drm_device *dev = crtc->dev;
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3729 int pipe = intel_crtc->pipe;
3730 u32 dpll;
3731
3732 dpll = DPLL_VGA_MODE_DIS;
3733
3734 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3735 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3736 } else {
3737 if (clock->p1 == 2)
3738 dpll |= PLL_P1_DIVIDE_BY_TWO;
3739 else
3740 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3741 if (clock->p2 == 4)
3742 dpll |= PLL_P2_DIVIDE_BY_4;
3743 }
3744
3745 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3746 /* XXX: just matching BIOS for now */
3747 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3748 dpll |= 3;
3749 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3750 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3751 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3752 else
3753 dpll |= PLL_REF_INPUT_DREFCLK;
3754
3755 dpll |= DPLL_VCO_ENABLE;
3756 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3757 POSTING_READ(DPLL(pipe));
3758 udelay(150);
3759
3760 I915_WRITE(DPLL(pipe), dpll);
3761
3762 /* Wait for the clocks to stabilize. */
3763 POSTING_READ(DPLL(pipe));
3764 udelay(150);
3765
3766 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3767 * This is an exception to the general rule that mode_set doesn't turn
3768 * things on.
3769 */
3770 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3771 intel_update_lvds(crtc, clock, adjusted_mode);
3772
3773 /* The pixel multiplier can only be updated once the
3774 * DPLL is enabled and the clocks are stable.
3775 *
3776 * So write it again.
3777 */
3778 I915_WRITE(DPLL(pipe), dpll);
3779}
3780
f564048e
EA		 3781static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3782 struct drm_display_mode *mode,
3783 struct drm_display_mode *adjusted_mode,
3784 int x, int y,
3785 struct drm_framebuffer *old_fb)
79e53945
JB		 3786{
3787 struct drm_device *dev = crtc->dev;
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790 int pipe = intel_crtc->pipe;
80824003 3791 int plane = intel_crtc->plane;
c751ce4f 3792 int refclk, num_connectors = 0;
652c393a 3793 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3794 u32 dspcntr, pipeconf, vsyncshift;
3795 bool ok, has_reduced_clock = false, is_sdvo = false;
3796 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3797 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3798 struct intel_encoder *encoder;
d4906093 3799 const intel_limit_t *limit;
5c3b82e2 3800 int ret;
79e53945 3801
5eddb70b
CW		 3802 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3803 if (encoder->base.crtc != crtc)
79e53945
JB		 3804 continue;
3805
5eddb70b 3806 switch (encoder->type) {
79e53945
JB		 3807 case INTEL_OUTPUT_LVDS:
3808 is_lvds = true;
3809 break;
3810 case INTEL_OUTPUT_SDVO:
7d57382e 3811 case INTEL_OUTPUT_HDMI:
79e53945 3812 is_sdvo = true;
5eddb70b 3813 if (encoder->needs_tv_clock)
e2f0ba97 3814 is_tv = true;
79e53945 3815 break;
79e53945
JB		 3816 case INTEL_OUTPUT_TVOUT:
3817 is_tv = true;
3818 break;
a4fc5ed6
KP		 3819 case INTEL_OUTPUT_DISPLAYPORT:
3820 is_dp = true;
3821 break;
79e53945 3822 }
43565a06 3823
c751ce4f 3824 num_connectors++;
79e53945
JB		 3825 }
3826
c65d77d8 3827 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3828
d4906093
ML		 3829 /*
3830 * Returns a set of divisors for the desired target clock with the given
3831 * refclk, or FALSE. The returned values represent the clock equation:
3832 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3833 */
1b894b59 3834 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3835 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3836 &clock);
79e53945
JB		 3837 if (!ok) {
3838 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3839 return -EINVAL;
79e53945
JB		 3840 }
3841
cda4b7d3 3842 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3843 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3844
ddc9003c 3845 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 3846 /*
3847 * Ensure we match the reduced clock's P to the target clock.
3848 * If the clocks don't match, we can't switch the display clock
3849 * by using the FP0/FP1. In such case we will disable the LVDS
3850 * downclock feature.
3851 */
ddc9003c 3852 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 3853 dev_priv->lvds_downclock,
3854 refclk,
cec2f356 3855 &clock,
5eddb70b 3856 &reduced_clock);
7026d4ac
ZW		 3857 }
3858
c65d77d8
JB		 3859 if (is_sdvo && is_tv)
3860 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 3861
a7516a05
JB		 3862 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3863 &reduced_clock : NULL);
79e53945 3864
eb1cbe48
DV		 3865 if (IS_GEN2(dev))
3866 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 3867 else
eb1cbe48
DV		 3868 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3869 has_reduced_clock ? &reduced_clock : NULL,
3870 num_connectors);
79e53945
JB		 3871
3872 /* setup pipeconf */
5eddb70b 3873 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 3874
3875 /* Set up the display plane register */
3876 dspcntr = DISPPLANE_GAMMA_ENABLE;
3877
929c77fb
EA		 3878 if (pipe == 0)
3879 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3880 else
3881 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 3882
a6c45cf0 3883 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 3884 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3885 * core speed.
3886 *
3887 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3888 * pipe == 0 check?
3889 */
e70236a8
JB		 3890 if (mode->clock >
3891 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 3892 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 3893 else
5eddb70b 3894 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 3895 }
3896
3b5c78a3
AJ		 3897 /* default to 8bpc */
3898 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3899 if (is_dp) {
3900 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3901 pipeconf |= PIPECONF_BPP_6 |
3902 PIPECONF_DITHER_EN |
3903 PIPECONF_DITHER_TYPE_SP;
3904 }
3905 }
3906
28c97730 3907 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 3908 drm_mode_debug_printmodeline(mode);
3909
a7516a05
JB		 3910 if (HAS_PIPE_CXSR(dev)) {
3911 if (intel_crtc->lowfreq_avail) {
28c97730 3912 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 3913 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 3914 } else {
28c97730 3915 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 3916 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3917 }
3918 }
3919
617cf884 3920 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 3921 if (!IS_GEN2(dev) &&
3922 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 3923 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3924 /* the chip adds 2 halflines automatically */
734b4157 3925 adjusted_mode->crtc_vtotal -= 1;
734b4157 3926 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 3927 vsyncshift = adjusted_mode->crtc_hsync_start
3928 - adjusted_mode->crtc_htotal/2;
3929 } else {
617cf884 3930 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 3931 vsyncshift = 0;
3932 }
3933
3934 if (!IS_GEN3(dev))
3935 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 3936
5eddb70b
CW		 3937 I915_WRITE(HTOTAL(pipe),
3938 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 3939 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 3940 I915_WRITE(HBLANK(pipe),
3941 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 3942 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 3943 I915_WRITE(HSYNC(pipe),
3944 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 3945 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 3946
3947 I915_WRITE(VTOTAL(pipe),
3948 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 3949 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 3950 I915_WRITE(VBLANK(pipe),
3951 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 3952 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 3953 I915_WRITE(VSYNC(pipe),
3954 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 3955 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 3956
3957 /* pipesrc and dspsize control the size that is scaled from,
3958 * which should always be the user's requested size.
79e53945 3959 */
929c77fb
EA		 3960 I915_WRITE(DSPSIZE(plane),
3961 ((mode->vdisplay - 1) << 16) |
3962 (mode->hdisplay - 1));
3963 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 3964 I915_WRITE(PIPESRC(pipe),
3965 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 3966
f564048e
EA		 3967 I915_WRITE(PIPECONF(pipe), pipeconf);
3968 POSTING_READ(PIPECONF(pipe));
929c77fb 3969 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 3970
3971 intel_wait_for_vblank(dev, pipe);
3972
f564048e
EA		 3973 I915_WRITE(DSPCNTR(plane), dspcntr);
3974 POSTING_READ(DSPCNTR(plane));
3975
3976 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3977
3978 intel_update_watermarks(dev);
3979
f564048e
EA		 3980 return ret;
3981}
3982
9fb526db
KP		 3983/*
3984 * Initialize reference clocks when the driver loads
3985 */
3986void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 3987{
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 3990 struct intel_encoder *encoder;
13d83a67
JB		 3991 u32 temp;
3992 bool has_lvds = false;
199e5d79
KP		 3993 bool has_cpu_edp = false;
3994 bool has_pch_edp = false;
3995 bool has_panel = false;
99eb6a01
KP		 3996 bool has_ck505 = false;
3997 bool can_ssc = false;
13d83a67
JB		 3998
3999 /* We need to take the global config into account */
199e5d79
KP		 4000 list_for_each_entry(encoder, &mode_config->encoder_list,
4001 base.head) {
4002 switch (encoder->type) {
4003 case INTEL_OUTPUT_LVDS:
4004 has_panel = true;
4005 has_lvds = true;
4006 break;
4007 case INTEL_OUTPUT_EDP:
4008 has_panel = true;
4009 if (intel_encoder_is_pch_edp(&encoder->base))
4010 has_pch_edp = true;
4011 else
4012 has_cpu_edp = true;
4013 break;
13d83a67
JB		 4014 }
4015 }
4016
99eb6a01
KP		 4017 if (HAS_PCH_IBX(dev)) {
4018 has_ck505 = dev_priv->display_clock_mode;
4019 can_ssc = has_ck505;
4020 } else {
4021 has_ck505 = false;
4022 can_ssc = true;
4023 }
4024
4025 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4026 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4027 has_ck505);
13d83a67
JB		 4028
4029 /* Ironlake: try to setup display ref clock before DPLL
4030 * enabling. This is only under driver's control after
4031 * PCH B stepping, previous chipset stepping should be
4032 * ignoring this setting.
4033 */
4034 temp = I915_READ(PCH_DREF_CONTROL);
4035 /* Always enable nonspread source */
4036 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4037
99eb6a01
KP		 4038 if (has_ck505)
4039 temp |= DREF_NONSPREAD_CK505_ENABLE;
4040 else
4041 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4042
199e5d79
KP		 4043 if (has_panel) {
4044 temp &= ~DREF_SSC_SOURCE_MASK;
4045 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4046
199e5d79 4047 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4048 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4049 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4050 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4051 } else
4052 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4053
4054 /* Get SSC going before enabling the outputs */
4055 I915_WRITE(PCH_DREF_CONTROL, temp);
4056 POSTING_READ(PCH_DREF_CONTROL);
4057 udelay(200);
4058
13d83a67
JB		 4059 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4060
4061 /* Enable CPU source on CPU attached eDP */
199e5d79 4062 if (has_cpu_edp) {
99eb6a01 4063 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4064 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4065 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4066 }
13d83a67
JB		 4067 else
4068 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4069 } else
4070 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4071
4072 I915_WRITE(PCH_DREF_CONTROL, temp);
4073 POSTING_READ(PCH_DREF_CONTROL);
4074 udelay(200);
4075 } else {
4076 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4077
4078 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4079
4080 /* Turn off CPU output */
4081 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4082
4083 I915_WRITE(PCH_DREF_CONTROL, temp);
4084 POSTING_READ(PCH_DREF_CONTROL);
4085 udelay(200);
4086
4087 /* Turn off the SSC source */
4088 temp &= ~DREF_SSC_SOURCE_MASK;
4089 temp |= DREF_SSC_SOURCE_DISABLE;
4090
4091 /* Turn off SSC1 */
4092 temp &= ~ DREF_SSC1_ENABLE;
4093
13d83a67
JB		 4094 I915_WRITE(PCH_DREF_CONTROL, temp);
4095 POSTING_READ(PCH_DREF_CONTROL);
4096 udelay(200);
4097 }
4098}
4099
d9d444cb
JB		 4100static int ironlake_get_refclk(struct drm_crtc *crtc)
4101{
4102 struct drm_device *dev = crtc->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_encoder *encoder;
4105 struct drm_mode_config *mode_config = &dev->mode_config;
4106 struct intel_encoder *edp_encoder = NULL;
4107 int num_connectors = 0;
4108 bool is_lvds = false;
4109
4110 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4111 if (encoder->base.crtc != crtc)
4112 continue;
4113
4114 switch (encoder->type) {
4115 case INTEL_OUTPUT_LVDS:
4116 is_lvds = true;
4117 break;
4118 case INTEL_OUTPUT_EDP:
4119 edp_encoder = encoder;
4120 break;
4121 }
4122 num_connectors++;
4123 }
4124
4125 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4126 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4127 dev_priv->lvds_ssc_freq);
4128 return dev_priv->lvds_ssc_freq * 1000;
4129 }
4130
4131 return 120000;
4132}
4133
f564048e
EA		 4134static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4135 struct drm_display_mode *mode,
4136 struct drm_display_mode *adjusted_mode,
4137 int x, int y,
4138 struct drm_framebuffer *old_fb)
79e53945
JB		 4139{
4140 struct drm_device *dev = crtc->dev;
4141 struct drm_i915_private *dev_priv = dev->dev_private;
4142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4143 int pipe = intel_crtc->pipe;
80824003 4144 int plane = intel_crtc->plane;
c751ce4f 4145 int refclk, num_connectors = 0;
652c393a 4146 intel_clock_t clock, reduced_clock;
5eddb70b 4147 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4148 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4149 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4150 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4151 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4152 const intel_limit_t *limit;
5c3b82e2 4153 int ret;
2c07245f 4154 struct fdi_m_n m_n = {0};
fae14981 4155 u32 temp;
5a354204
JB		 4156 int target_clock, pixel_multiplier, lane, link_bw, factor;
4157 unsigned int pipe_bpp;
4158 bool dither;
e3aef172 4159 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4160
5eddb70b
CW		 4161 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4162 if (encoder->base.crtc != crtc)
79e53945
JB		 4163 continue;
4164
5eddb70b 4165 switch (encoder->type) {
79e53945
JB		 4166 case INTEL_OUTPUT_LVDS:
4167 is_lvds = true;
4168 break;
4169 case INTEL_OUTPUT_SDVO:
7d57382e 4170 case INTEL_OUTPUT_HDMI:
79e53945 4171 is_sdvo = true;
5eddb70b 4172 if (encoder->needs_tv_clock)
e2f0ba97 4173 is_tv = true;
79e53945 4174 break;
79e53945
JB		 4175 case INTEL_OUTPUT_TVOUT:
4176 is_tv = true;
4177 break;
4178 case INTEL_OUTPUT_ANALOG:
4179 is_crt = true;
4180 break;
a4fc5ed6
KP		 4181 case INTEL_OUTPUT_DISPLAYPORT:
4182 is_dp = true;
4183 break;
32f9d658 4184 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4185 is_dp = true;
4186 if (intel_encoder_is_pch_edp(&encoder->base))
4187 is_pch_edp = true;
4188 else
4189 is_cpu_edp = true;
4190 edp_encoder = encoder;
32f9d658 4191 break;
79e53945 4192 }
43565a06 4193
c751ce4f 4194 num_connectors++;
79e53945
JB		 4195 }
4196
d9d444cb 4197 refclk = ironlake_get_refclk(crtc);
79e53945 4198
d4906093
ML		 4199 /*
4200 * Returns a set of divisors for the desired target clock with the given
4201 * refclk, or FALSE. The returned values represent the clock equation:
4202 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4203 */
1b894b59 4204 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4205 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4206 &clock);
79e53945
JB		 4207 if (!ok) {
4208 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4209 return -EINVAL;
79e53945
JB		 4210 }
4211
cda4b7d3 4212 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4213 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4214
ddc9003c 4215 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4216 /*
4217 * Ensure we match the reduced clock's P to the target clock.
4218 * If the clocks don't match, we can't switch the display clock
4219 * by using the FP0/FP1. In such case we will disable the LVDS
4220 * downclock feature.
4221 */
ddc9003c 4222 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4223 dev_priv->lvds_downclock,
4224 refclk,
cec2f356 4225 &clock,
5eddb70b 4226 &reduced_clock);
652c393a 4227 }
7026d4ac
ZW		 4228 /* SDVO TV has fixed PLL values depend on its clock range,
4229 this mirrors vbios setting. */
4230 if (is_sdvo && is_tv) {
4231 if (adjusted_mode->clock >= 100000
5eddb70b 4232 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4233 clock.p1 = 2;
4234 clock.p2 = 10;
4235 clock.n = 3;
4236 clock.m1 = 16;
4237 clock.m2 = 8;
4238 } else if (adjusted_mode->clock >= 140500
5eddb70b 4239 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4240 clock.p1 = 1;
4241 clock.p2 = 10;
4242 clock.n = 6;
4243 clock.m1 = 12;
4244 clock.m2 = 8;
4245 }
4246 }
4247
2c07245f 4248 /* FDI link */
8febb297
EA		 4249 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4250 lane = 0;
4251 /* CPU eDP doesn't require FDI link, so just set DP M/N
4252 according to current link config */
e3aef172 4253 if (is_cpu_edp) {
8febb297 4254 target_clock = mode->clock;
e3aef172 4255 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4256 } else {
4257 /* [e]DP over FDI requires target mode clock
4258 instead of link clock */
e3aef172 4259 if (is_dp)
5eb08b69 4260 target_clock = mode->clock;
8febb297
EA		 4261 else
4262 target_clock = adjusted_mode->clock;
4263
4264 /* FDI is a binary signal running at ~2.7GHz, encoding
4265 * each output octet as 10 bits. The actual frequency
4266 * is stored as a divider into a 100MHz clock, and the
4267 * mode pixel clock is stored in units of 1KHz.
4268 * Hence the bw of each lane in terms of the mode signal
4269 * is:
4270 */
4271 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4272 }
58a27471 4273
8febb297
EA		 4274 /* determine panel color depth */
4275 temp = I915_READ(PIPECONF(pipe));
4276 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4277 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4278 switch (pipe_bpp) {
4279 case 18:
4280 temp |= PIPE_6BPC;
8febb297 4281 break;
5a354204
JB		 4282 case 24:
4283 temp |= PIPE_8BPC;
8febb297 4284 break;
5a354204
JB		 4285 case 30:
4286 temp |= PIPE_10BPC;
8febb297 4287 break;
5a354204
JB		 4288 case 36:
4289 temp |= PIPE_12BPC;
8febb297
EA		 4290 break;
4291 default:
62ac41a6
JB		 4292 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4293 pipe_bpp);
5a354204
JB		 4294 temp |= PIPE_8BPC;
4295 pipe_bpp = 24;
4296 break;
8febb297 4297 }
77ffb597 4298
5a354204
JB		 4299 intel_crtc->bpp = pipe_bpp;
4300 I915_WRITE(PIPECONF(pipe), temp);
4301
8febb297
EA		 4302 if (!lane) {
4303 /*
4304 * Account for spread spectrum to avoid
4305 * oversubscribing the link. Max center spread
4306 * is 2.5%; use 5% for safety's sake.
4307 */
5a354204 4308 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4309 lane = bps / (link_bw * 8) + 1;
5eb08b69 4310 }
2c07245f 4311
8febb297
EA		 4312 intel_crtc->fdi_lanes = lane;
4313
4314 if (pixel_multiplier > 1)
4315 link_bw *= pixel_multiplier;
5a354204
JB		 4316 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4317 &m_n);
8febb297 4318
a07d6787
EA		 4319 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4320 if (has_reduced_clock)
4321 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4322 reduced_clock.m2;
79e53945 4323
c1858123 4324 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4325 factor = 21;
4326 if (is_lvds) {
4327 if ((intel_panel_use_ssc(dev_priv) &&
4328 dev_priv->lvds_ssc_freq == 100) ||
4329 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4330 factor = 25;
4331 } else if (is_sdvo && is_tv)
4332 factor = 20;
c1858123 4333
cb0e0931 4334 if (clock.m < factor * clock.n)
8febb297 4335 fp |= FP_CB_TUNE;
2c07245f 4336
5eddb70b 4337 dpll = 0;
2c07245f 4338
a07d6787
EA		 4339 if (is_lvds)
4340 dpll |= DPLLB_MODE_LVDS;
4341 else
4342 dpll |= DPLLB_MODE_DAC_SERIAL;
4343 if (is_sdvo) {
4344 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4345 if (pixel_multiplier > 1) {
4346 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4347 }
a07d6787
EA		 4348 dpll |= DPLL_DVO_HIGH_SPEED;
4349 }
e3aef172 4350 if (is_dp && !is_cpu_edp)
a07d6787 4351 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4352
a07d6787
EA		 4353 /* compute bitmask from p1 value */
4354 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4355 /* also FPA1 */
4356 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4357
4358 switch (clock.p2) {
4359 case 5:
4360 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4361 break;
4362 case 7:
4363 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4364 break;
4365 case 10:
4366 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4367 break;
4368 case 14:
4369 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4370 break;
79e53945
JB		 4371 }
4372
43565a06
KH		 4373 if (is_sdvo && is_tv)
4374 dpll |= PLL_REF_INPUT_TVCLKINBC;
4375 else if (is_tv)
79e53945 4376 /* XXX: just matching BIOS for now */
43565a06 4377 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4378 dpll |= 3;
a7615030 4379 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4380 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4381 else
4382 dpll |= PLL_REF_INPUT_DREFCLK;
4383
4384 /* setup pipeconf */
5eddb70b 4385 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4386
4387 /* Set up the display plane register */
4388 dspcntr = DISPPLANE_GAMMA_ENABLE;
4389
f7cb34d4 4390 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4391 drm_mode_debug_printmodeline(mode);
4392
ee7b9f93
JB		 4393 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4394 if (!is_cpu_edp) {
4395 struct intel_pch_pll *pll;
4b645f14 4396
ee7b9f93
JB		 4397 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4398 if (pll == NULL) {
4399 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4400 pipe);
4b645f14
JB		 4401 return -EINVAL;
4402 }
ee7b9f93
JB		 4403 } else
4404 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4405
4406 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4407 * This is an exception to the general rule that mode_set doesn't turn
4408 * things on.
4409 */
4410 if (is_lvds) {
fae14981 4411 temp = I915_READ(PCH_LVDS);
5eddb70b 4412 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4413 if (HAS_PCH_CPT(dev)) {
4414 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4415 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4416 } else {
4417 if (pipe == 1)
4418 temp |= LVDS_PIPEB_SELECT;
4419 else
4420 temp &= ~LVDS_PIPEB_SELECT;
4421 }
4b645f14 4422
a3e17eb8 4423 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4424 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4425 /* Set the B0-B3 data pairs corresponding to whether we're going to
4426 * set the DPLLs for dual-channel mode or not.
4427 */
4428 if (clock.p2 == 7)
5eddb70b 4429 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4430 else
5eddb70b 4431 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4432
4433 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4434 * appropriately here, but we need to look more thoroughly into how
4435 * panels behave in the two modes.
4436 */
284d5df5 4437 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4438 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4439 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4440 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4441 temp |= LVDS_VSYNC_POLARITY;
fae14981 4442 I915_WRITE(PCH_LVDS, temp);
79e53945 4443 }
434ed097 4444
8febb297
EA		 4445 pipeconf &= ~PIPECONF_DITHER_EN;
4446 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4447 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4448 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4449 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4450 }
e3aef172 4451 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4452 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4453 } else {
8db9d77b 4454 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4455 I915_WRITE(TRANSDATA_M1(pipe), 0);
4456 I915_WRITE(TRANSDATA_N1(pipe), 0);
4457 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4458 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4459 }
79e53945 4460
ee7b9f93
JB		 4461 if (intel_crtc->pch_pll) {
4462 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4463
32f9d658 4464 /* Wait for the clocks to stabilize. */
ee7b9f93 4465 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4466 udelay(150);
4467
8febb297
EA		 4468 /* The pixel multiplier can only be updated once the
4469 * DPLL is enabled and the clocks are stable.
4470 *
4471 * So write it again.
4472 */
ee7b9f93 4473 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4474 }
79e53945 4475
5eddb70b 4476 intel_crtc->lowfreq_avail = false;
ee7b9f93 4477 if (intel_crtc->pch_pll) {
4b645f14 4478 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4479 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14
JB		 4480 intel_crtc->lowfreq_avail = true;
4481 if (HAS_PIPE_CXSR(dev)) {
4482 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4483 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4484 }
4485 } else {
ee7b9f93 4486 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4b645f14
JB		 4487 if (HAS_PIPE_CXSR(dev)) {
4488 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4489 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4490 }
652c393a
JB		 4491 }
4492 }
4493
617cf884 4494 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4495 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4496 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4497 /* the chip adds 2 halflines automatically */
734b4157 4498 adjusted_mode->crtc_vtotal -= 1;
734b4157 4499 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4500 I915_WRITE(VSYNCSHIFT(pipe),
4501 adjusted_mode->crtc_hsync_start
4502 - adjusted_mode->crtc_htotal/2);
4503 } else {
617cf884 4504 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4505 I915_WRITE(VSYNCSHIFT(pipe), 0);
4506 }
734b4157 4507
5eddb70b
CW		 4508 I915_WRITE(HTOTAL(pipe),
4509 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4510 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4511 I915_WRITE(HBLANK(pipe),
4512 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4513 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4514 I915_WRITE(HSYNC(pipe),
4515 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4516 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4517
4518 I915_WRITE(VTOTAL(pipe),
4519 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4520 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4521 I915_WRITE(VBLANK(pipe),
4522 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4523 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4524 I915_WRITE(VSYNC(pipe),
4525 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4526 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4527
8febb297
EA		 4528 /* pipesrc controls the size that is scaled from, which should
4529 * always be the user's requested size.
79e53945 4530 */
5eddb70b
CW		 4531 I915_WRITE(PIPESRC(pipe),
4532 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4533
8febb297
EA		 4534 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4535 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4536 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4537 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4538
e3aef172 4539 if (is_cpu_edp)
8febb297 4540 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4541
5eddb70b
CW		 4542 I915_WRITE(PIPECONF(pipe), pipeconf);
4543 POSTING_READ(PIPECONF(pipe));
79e53945 4544
9d0498a2 4545 intel_wait_for_vblank(dev, pipe);
79e53945 4546
5eddb70b 4547 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4548 POSTING_READ(DSPCNTR(plane));
79e53945 4549
5c3b82e2 4550 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4551
4552 intel_update_watermarks(dev);
4553
1f803ee5 4554 return ret;
79e53945
JB		 4555}
4556
f564048e
EA		 4557static int intel_crtc_mode_set(struct drm_crtc *crtc,
4558 struct drm_display_mode *mode,
4559 struct drm_display_mode *adjusted_mode,
4560 int x, int y,
4561 struct drm_framebuffer *old_fb)
4562{
4563 struct drm_device *dev = crtc->dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566 int pipe = intel_crtc->pipe;
f564048e
EA		 4567 int ret;
4568
0b701d27 4569 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4570
f564048e
EA		 4571 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4572 x, y, old_fb);
79e53945 4573 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4574
d8e70a25
JB		 4575 if (ret)
4576 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4577 else
4578 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4579
1f803ee5 4580 return ret;
79e53945
JB		 4581}
4582
3a9627f4
WF		 4583static bool intel_eld_uptodate(struct drm_connector *connector,
4584 int reg_eldv, uint32_t bits_eldv,
4585 int reg_elda, uint32_t bits_elda,
4586 int reg_edid)
4587{
4588 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4589 uint8_t *eld = connector->eld;
4590 uint32_t i;
4591
4592 i = I915_READ(reg_eldv);
4593 i &= bits_eldv;
4594
4595 if (!eld[0])
4596 return !i;
4597
4598 if (!i)
4599 return false;
4600
4601 i = I915_READ(reg_elda);
4602 i &= ~bits_elda;
4603 I915_WRITE(reg_elda, i);
4604
4605 for (i = 0; i < eld[2]; i++)
4606 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4607 return false;
4608
4609 return true;
4610}
4611
e0dac65e
WF		 4612static void g4x_write_eld(struct drm_connector *connector,
4613 struct drm_crtc *crtc)
4614{
4615 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4616 uint8_t *eld = connector->eld;
4617 uint32_t eldv;
4618 uint32_t len;
4619 uint32_t i;
4620
4621 i = I915_READ(G4X_AUD_VID_DID);
4622
4623 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4624 eldv = G4X_ELDV_DEVCL_DEVBLC;
4625 else
4626 eldv = G4X_ELDV_DEVCTG;
4627
3a9627f4
WF		 4628 if (intel_eld_uptodate(connector,
4629 G4X_AUD_CNTL_ST, eldv,
4630 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4631 G4X_HDMIW_HDMIEDID))
4632 return;
4633
e0dac65e
WF		 4634 i = I915_READ(G4X_AUD_CNTL_ST);
4635 i &= ~(eldv | G4X_ELD_ADDR);
4636 len = (i >> 9) & 0x1f; /* ELD buffer size */
4637 I915_WRITE(G4X_AUD_CNTL_ST, i);
4638
4639 if (!eld[0])
4640 return;
4641
4642 len = min_t(uint8_t, eld[2], len);
4643 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4644 for (i = 0; i < len; i++)
4645 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4646
4647 i = I915_READ(G4X_AUD_CNTL_ST);
4648 i |= eldv;
4649 I915_WRITE(G4X_AUD_CNTL_ST, i);
4650}
4651
4652static void ironlake_write_eld(struct drm_connector *connector,
4653 struct drm_crtc *crtc)
4654{
4655 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4656 uint8_t *eld = connector->eld;
4657 uint32_t eldv;
4658 uint32_t i;
4659 int len;
4660 int hdmiw_hdmiedid;
b6daa025 4661 int aud_config;
e0dac65e
WF		 4662 int aud_cntl_st;
4663 int aud_cntrl_st2;
4664
b3f33cbf 4665 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4666 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4667 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4668 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4669 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4670 } else {
1202b4c6 4671 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4672 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4673 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4674 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4675 }
4676
4677 i = to_intel_crtc(crtc)->pipe;
4678 hdmiw_hdmiedid += i * 0x100;
4679 aud_cntl_st += i * 0x100;
b6daa025 4680 aud_config += i * 0x100;
e0dac65e
WF		 4681
4682 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4683
4684 i = I915_READ(aud_cntl_st);
4685 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4686 if (!i) {
4687 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4688 /* operate blindly on all ports */
1202b4c6
WF		 4689 eldv = IBX_ELD_VALIDB;
4690 eldv |= IBX_ELD_VALIDB << 4;
4691 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4692 } else {
4693 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4694 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4695 }
4696
3a9627f4
WF		 4697 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4698 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4699 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4700 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4701 } else
4702 I915_WRITE(aud_config, 0);
e0dac65e 4703
3a9627f4
WF		 4704 if (intel_eld_uptodate(connector,
4705 aud_cntrl_st2, eldv,
4706 aud_cntl_st, IBX_ELD_ADDRESS,
4707 hdmiw_hdmiedid))
4708 return;
4709
e0dac65e
WF		 4710 i = I915_READ(aud_cntrl_st2);
4711 i &= ~eldv;
4712 I915_WRITE(aud_cntrl_st2, i);
4713
4714 if (!eld[0])
4715 return;
4716
e0dac65e 4717 i = I915_READ(aud_cntl_st);
1202b4c6 4718 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4719 I915_WRITE(aud_cntl_st, i);
4720
4721 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4722 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4723 for (i = 0; i < len; i++)
4724 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4725
4726 i = I915_READ(aud_cntrl_st2);
4727 i |= eldv;
4728 I915_WRITE(aud_cntrl_st2, i);
4729}
4730
4731void intel_write_eld(struct drm_encoder *encoder,
4732 struct drm_display_mode *mode)
4733{
4734 struct drm_crtc *crtc = encoder->crtc;
4735 struct drm_connector *connector;
4736 struct drm_device *dev = encoder->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738
4739 connector = drm_select_eld(encoder, mode);
4740 if (!connector)
4741 return;
4742
4743 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4744 connector->base.id,
4745 drm_get_connector_name(connector),
4746 connector->encoder->base.id,
4747 drm_get_encoder_name(connector->encoder));
4748
4749 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4750
4751 if (dev_priv->display.write_eld)
4752 dev_priv->display.write_eld(connector, crtc);
4753}
4754
79e53945
JB		 4755/** Loads the palette/gamma unit for the CRTC with the prepared values */
4756void intel_crtc_load_lut(struct drm_crtc *crtc)
4757{
4758 struct drm_device *dev = crtc->dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4761 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4762 int i;
4763
4764 /* The clocks have to be on to load the palette. */
aed3f09d 4765 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4766 return;
4767
f2b115e6 4768 /* use legacy palette for Ironlake */
bad720ff 4769 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4770 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4771
79e53945
JB		 4772 for (i = 0; i < 256; i++) {
4773 I915_WRITE(palreg + 4 * i,
4774 (intel_crtc->lut_r[i] << 16) |
4775 (intel_crtc->lut_g[i] << 8) |
4776 intel_crtc->lut_b[i]);
4777 }
4778}
4779
560b85bb
CW		 4780static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4781{
4782 struct drm_device *dev = crtc->dev;
4783 struct drm_i915_private *dev_priv = dev->dev_private;
4784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4785 bool visible = base != 0;
4786 u32 cntl;
4787
4788 if (intel_crtc->cursor_visible == visible)
4789 return;
4790
9db4a9c7 4791 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4792 if (visible) {
4793 /* On these chipsets we can only modify the base whilst
4794 * the cursor is disabled.
4795 */
9db4a9c7 4796 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4797
4798 cntl &= ~(CURSOR_FORMAT_MASK);
4799 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4800 cntl |= CURSOR_ENABLE |
4801 CURSOR_GAMMA_ENABLE |
4802 CURSOR_FORMAT_ARGB;
4803 } else
4804 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4805 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4806
4807 intel_crtc->cursor_visible = visible;
4808}
4809
4810static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4811{
4812 struct drm_device *dev = crtc->dev;
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4815 int pipe = intel_crtc->pipe;
4816 bool visible = base != 0;
4817
4818 if (intel_crtc->cursor_visible != visible) {
548f245b 4819 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4820 if (base) {
4821 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4822 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4823 cntl |= pipe << 28; /* Connect to correct pipe */
4824 } else {
4825 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4826 cntl |= CURSOR_MODE_DISABLE;
4827 }
9db4a9c7 4828 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4829
4830 intel_crtc->cursor_visible = visible;
4831 }
4832 /* and commit changes on next vblank */
9db4a9c7 4833 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4834}
4835
65a21cd6
JB		 4836static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4837{
4838 struct drm_device *dev = crtc->dev;
4839 struct drm_i915_private *dev_priv = dev->dev_private;
4840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4841 int pipe = intel_crtc->pipe;
4842 bool visible = base != 0;
4843
4844 if (intel_crtc->cursor_visible != visible) {
4845 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4846 if (base) {
4847 cntl &= ~CURSOR_MODE;
4848 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4849 } else {
4850 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4851 cntl |= CURSOR_MODE_DISABLE;
4852 }
4853 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4854
4855 intel_crtc->cursor_visible = visible;
4856 }
4857 /* and commit changes on next vblank */
4858 I915_WRITE(CURBASE_IVB(pipe), base);
4859}
4860
cda4b7d3 4861/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 4862static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4863 bool on)
cda4b7d3
CW		 4864{
4865 struct drm_device *dev = crtc->dev;
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4868 int pipe = intel_crtc->pipe;
4869 int x = intel_crtc->cursor_x;
4870 int y = intel_crtc->cursor_y;
560b85bb 4871 u32 base, pos;
cda4b7d3
CW		 4872 bool visible;
4873
4874 pos = 0;
4875
6b383a7f 4876 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 4877 base = intel_crtc->cursor_addr;
4878 if (x > (int) crtc->fb->width)
4879 base = 0;
4880
4881 if (y > (int) crtc->fb->height)
4882 base = 0;
4883 } else
4884 base = 0;
4885
4886 if (x < 0) {
4887 if (x + intel_crtc->cursor_width < 0)
4888 base = 0;
4889
4890 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4891 x = -x;
4892 }
4893 pos |= x << CURSOR_X_SHIFT;
4894
4895 if (y < 0) {
4896 if (y + intel_crtc->cursor_height < 0)
4897 base = 0;
4898
4899 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4900 y = -y;
4901 }
4902 pos |= y << CURSOR_Y_SHIFT;
4903
4904 visible = base != 0;
560b85bb 4905 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 4906 return;
4907
0cd83aa9 4908 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 4909 I915_WRITE(CURPOS_IVB(pipe), pos);
4910 ivb_update_cursor(crtc, base);
4911 } else {
4912 I915_WRITE(CURPOS(pipe), pos);
4913 if (IS_845G(dev) || IS_I865G(dev))
4914 i845_update_cursor(crtc, base);
4915 else
4916 i9xx_update_cursor(crtc, base);
4917 }
cda4b7d3
CW		 4918}
4919
79e53945 4920static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 4921 struct drm_file *file,
79e53945
JB		 4922 uint32_t handle,
4923 uint32_t width, uint32_t height)
4924{
4925 struct drm_device *dev = crtc->dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 4928 struct drm_i915_gem_object *obj;
cda4b7d3 4929 uint32_t addr;
3f8bc370 4930 int ret;
79e53945 4931
28c97730 4932 DRM_DEBUG_KMS("\n");
79e53945
JB		 4933
4934 /* if we want to turn off the cursor ignore width and height */
4935 if (!handle) {
28c97730 4936 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 4937 addr = 0;
05394f39 4938 obj = NULL;
5004417d 4939 mutex_lock(&dev->struct_mutex);
3f8bc370 4940 goto finish;
79e53945
JB		 4941 }
4942
4943 /* Currently we only support 64x64 cursors */
4944 if (width != 64 || height != 64) {
4945 DRM_ERROR("we currently only support 64x64 cursors\n");
4946 return -EINVAL;
4947 }
4948
05394f39 4949 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 4950 if (&obj->base == NULL)
79e53945
JB		 4951 return -ENOENT;
4952
05394f39 4953 if (obj->base.size < width * height * 4) {
79e53945 4954 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 4955 ret = -ENOMEM;
4956 goto fail;
79e53945
JB		 4957 }
4958
71acb5eb 4959 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 4960 mutex_lock(&dev->struct_mutex);
b295d1b6 4961 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 4962 if (obj->tiling_mode) {
4963 DRM_ERROR("cursor cannot be tiled\n");
4964 ret = -EINVAL;
4965 goto fail_locked;
4966 }
4967
2da3b9b9 4968 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 4969 if (ret) {
4970 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 4971 goto fail_locked;
e7b526bb
CW		 4972 }
4973
d9e86c0e
CW		 4974 ret = i915_gem_object_put_fence(obj);
4975 if (ret) {
2da3b9b9 4976 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 4977 goto fail_unpin;
4978 }
4979
05394f39 4980 addr = obj->gtt_offset;
71acb5eb 4981 } else {
6eeefaf3 4982 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 4983 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 4984 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4985 align);
71acb5eb
DA		 4986 if (ret) {
4987 DRM_ERROR("failed to attach phys object\n");
7f9872e0 4988 goto fail_locked;
71acb5eb 4989 }
05394f39 4990 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 4991 }
4992
a6c45cf0 4993 if (IS_GEN2(dev))
14b60391
JB		 4994 I915_WRITE(CURSIZE, (height << 12) | width);
4995
3f8bc370 4996 finish:
3f8bc370 4997 if (intel_crtc->cursor_bo) {
b295d1b6 4998 if (dev_priv->info->cursor_needs_physical) {
05394f39 4999 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5000 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5001 } else
5002 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5003 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5004 }
80824003 5005
7f9872e0 5006 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5007
5008 intel_crtc->cursor_addr = addr;
05394f39 5009 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5010 intel_crtc->cursor_width = width;
5011 intel_crtc->cursor_height = height;
5012
6b383a7f 5013 intel_crtc_update_cursor(crtc, true);
3f8bc370 5014
79e53945 5015 return 0;
e7b526bb 5016fail_unpin:
05394f39 5017 i915_gem_object_unpin(obj);
7f9872e0 5018fail_locked:
34b8686e 5019 mutex_unlock(&dev->struct_mutex);
bc9025bd 5020fail:
05394f39 5021 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5022 return ret;
79e53945
JB		 5023}
5024
5025static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5026{
79e53945 5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5028
cda4b7d3
CW		 5029 intel_crtc->cursor_x = x;
5030 intel_crtc->cursor_y = y;
652c393a 5031
6b383a7f 5032 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5033
5034 return 0;
5035}
5036
5037/** Sets the color ramps on behalf of RandR */
5038void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5039 u16 blue, int regno)
5040{
5041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5042
5043 intel_crtc->lut_r[regno] = red >> 8;
5044 intel_crtc->lut_g[regno] = green >> 8;
5045 intel_crtc->lut_b[regno] = blue >> 8;
5046}
5047
b8c00ac5
DA		 5048void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5049 u16 *blue, int regno)
5050{
5051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5052
5053 *red = intel_crtc->lut_r[regno] << 8;
5054 *green = intel_crtc->lut_g[regno] << 8;
5055 *blue = intel_crtc->lut_b[regno] << 8;
5056}
5057
79e53945 5058static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5059 u16 *blue, uint32_t start, uint32_t size)
79e53945 5060{
7203425a 5061 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5063
7203425a 5064 for (i = start; i < end; i++) {
79e53945
JB		 5065 intel_crtc->lut_r[i] = red[i] >> 8;
5066 intel_crtc->lut_g[i] = green[i] >> 8;
5067 intel_crtc->lut_b[i] = blue[i] >> 8;
5068 }
5069
5070 intel_crtc_load_lut(crtc);
5071}
5072
5073/**
5074 * Get a pipe with a simple mode set on it for doing load-based monitor
5075 * detection.
5076 *
5077 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5078 * its requirements. The pipe will be connected to no other encoders.
79e53945 5079 *
c751ce4f 5080 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5081 * configured for it. In the future, it could choose to temporarily disable
5082 * some outputs to free up a pipe for its use.
5083 *
5084 * \return crtc, or NULL if no pipes are available.
5085 */
5086
5087/* VESA 640x480x72Hz mode to set on the pipe */
5088static struct drm_display_mode load_detect_mode = {
5089 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5090 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5091};
5092
d2dff872
CW		 5093static struct drm_framebuffer *
5094intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5095 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5096 struct drm_i915_gem_object *obj)
5097{
5098 struct intel_framebuffer *intel_fb;
5099 int ret;
5100
5101 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5102 if (!intel_fb) {
5103 drm_gem_object_unreference_unlocked(&obj->base);
5104 return ERR_PTR(-ENOMEM);
5105 }
5106
5107 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5108 if (ret) {
5109 drm_gem_object_unreference_unlocked(&obj->base);
5110 kfree(intel_fb);
5111 return ERR_PTR(ret);
5112 }
5113
5114 return &intel_fb->base;
5115}
5116
5117static u32
5118intel_framebuffer_pitch_for_width(int width, int bpp)
5119{
5120 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5121 return ALIGN(pitch, 64);
5122}
5123
5124static u32
5125intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5126{
5127 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5128 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5129}
5130
5131static struct drm_framebuffer *
5132intel_framebuffer_create_for_mode(struct drm_device *dev,
5133 struct drm_display_mode *mode,
5134 int depth, int bpp)
5135{
5136 struct drm_i915_gem_object *obj;
308e5bcb 5137 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5138
5139 obj = i915_gem_alloc_object(dev,
5140 intel_framebuffer_size_for_mode(mode, bpp));
5141 if (obj == NULL)
5142 return ERR_PTR(-ENOMEM);
5143
5144 mode_cmd.width = mode->hdisplay;
5145 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5146 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5147 bpp);
5ca0c34a 5148 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5149
5150 return intel_framebuffer_create(dev, &mode_cmd, obj);
5151}
5152
5153static struct drm_framebuffer *
5154mode_fits_in_fbdev(struct drm_device *dev,
5155 struct drm_display_mode *mode)
5156{
5157 struct drm_i915_private *dev_priv = dev->dev_private;
5158 struct drm_i915_gem_object *obj;
5159 struct drm_framebuffer *fb;
5160
5161 if (dev_priv->fbdev == NULL)
5162 return NULL;
5163
5164 obj = dev_priv->fbdev->ifb.obj;
5165 if (obj == NULL)
5166 return NULL;
5167
5168 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5169 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5170 fb->bits_per_pixel))
d2dff872
CW		 5171 return NULL;
5172
01f2c773 5173 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5174 return NULL;
5175
5176 return fb;
5177}
5178
7173188d
CW		 5179bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5180 struct drm_connector *connector,
5181 struct drm_display_mode *mode,
8261b191 5182 struct intel_load_detect_pipe *old)
79e53945
JB		 5183{
5184 struct intel_crtc *intel_crtc;
5185 struct drm_crtc *possible_crtc;
4ef69c7a 5186 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5187 struct drm_crtc *crtc = NULL;
5188 struct drm_device *dev = encoder->dev;
d2dff872 5189 struct drm_framebuffer *old_fb;
79e53945
JB		 5190 int i = -1;
5191
d2dff872
CW		 5192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5193 connector->base.id, drm_get_connector_name(connector),
5194 encoder->base.id, drm_get_encoder_name(encoder));
5195
79e53945
JB		 5196 /*
5197 * Algorithm gets a little messy:
7a5e4805 5198 *
79e53945
JB		 5199 * - if the connector already has an assigned crtc, use it (but make
5200 * sure it's on first)
7a5e4805 5201 *
79e53945
JB		 5202 * - try to find the first unused crtc that can drive this connector,
5203 * and use that if we find one
79e53945
JB		 5204 */
5205
5206 /* See if we already have a CRTC for this connector */
5207 if (encoder->crtc) {
5208 crtc = encoder->crtc;
8261b191 5209
79e53945 5210 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5211 old->dpms_mode = intel_crtc->dpms_mode;
5212 old->load_detect_temp = false;
5213
5214 /* Make sure the crtc and connector are running */
79e53945 5215 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5216 struct drm_encoder_helper_funcs *encoder_funcs;
5217 struct drm_crtc_helper_funcs *crtc_funcs;
5218
79e53945
JB		 5219 crtc_funcs = crtc->helper_private;
5220 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5221
5222 encoder_funcs = encoder->helper_private;
79e53945
JB		 5223 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5224 }
8261b191 5225
7173188d 5226 return true;
79e53945
JB		 5227 }
5228
5229 /* Find an unused one (if possible) */
5230 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5231 i++;
5232 if (!(encoder->possible_crtcs & (1 << i)))
5233 continue;
5234 if (!possible_crtc->enabled) {
5235 crtc = possible_crtc;
5236 break;
5237 }
79e53945
JB		 5238 }
5239
5240 /*
5241 * If we didn't find an unused CRTC, don't use any.
5242 */
5243 if (!crtc) {
7173188d
CW		 5244 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5245 return false;
79e53945
JB		 5246 }
5247
5248 encoder->crtc = crtc;
c1c43977 5249 connector->encoder = encoder;
79e53945
JB		 5250
5251 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5252 old->dpms_mode = intel_crtc->dpms_mode;
5253 old->load_detect_temp = true;
d2dff872 5254 old->release_fb = NULL;
79e53945 5255
6492711d
CW		 5256 if (!mode)
5257 mode = &load_detect_mode;
79e53945 5258
d2dff872
CW		 5259 old_fb = crtc->fb;
5260
5261 /* We need a framebuffer large enough to accommodate all accesses
5262 * that the plane may generate whilst we perform load detection.
5263 * We can not rely on the fbcon either being present (we get called
5264 * during its initialisation to detect all boot displays, or it may
5265 * not even exist) or that it is large enough to satisfy the
5266 * requested mode.
5267 */
5268 crtc->fb = mode_fits_in_fbdev(dev, mode);
5269 if (crtc->fb == NULL) {
5270 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5271 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5272 old->release_fb = crtc->fb;
5273 } else
5274 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5275 if (IS_ERR(crtc->fb)) {
5276 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5277 crtc->fb = old_fb;
5278 return false;
79e53945 5279 }
79e53945 5280
d2dff872 5281 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5282 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5283 if (old->release_fb)
5284 old->release_fb->funcs->destroy(old->release_fb);
5285 crtc->fb = old_fb;
6492711d 5286 return false;
79e53945 5287 }
7173188d 5288
79e53945 5289 /* let the connector get through one full cycle before testing */
9d0498a2 5290 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5291
7173188d 5292 return true;
79e53945
JB		 5293}
5294
c1c43977 5295void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5296 struct drm_connector *connector,
5297 struct intel_load_detect_pipe *old)
79e53945 5298{
4ef69c7a 5299 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5300 struct drm_device *dev = encoder->dev;
5301 struct drm_crtc *crtc = encoder->crtc;
5302 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5303 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5304
d2dff872
CW		 5305 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5306 connector->base.id, drm_get_connector_name(connector),
5307 encoder->base.id, drm_get_encoder_name(encoder));
5308
8261b191 5309 if (old->load_detect_temp) {
c1c43977 5310 connector->encoder = NULL;
79e53945 5311 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5312
5313 if (old->release_fb)
5314 old->release_fb->funcs->destroy(old->release_fb);
5315
0622a53c 5316 return;
79e53945
JB		 5317 }
5318
c751ce4f 5319 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5320 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5321 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5322 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5323 }
5324}
5325
5326/* Returns the clock of the currently programmed mode of the given pipe. */
5327static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5328{
5329 struct drm_i915_private *dev_priv = dev->dev_private;
5330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331 int pipe = intel_crtc->pipe;
548f245b 5332 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5333 u32 fp;
5334 intel_clock_t clock;
5335
5336 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5337 fp = I915_READ(FP0(pipe));
79e53945 5338 else
39adb7a5 5339 fp = I915_READ(FP1(pipe));
79e53945
JB		 5340
5341 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5342 if (IS_PINEVIEW(dev)) {
5343 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5344 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5345 } else {
5346 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5347 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5348 }
5349
a6c45cf0 5350 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5351 if (IS_PINEVIEW(dev))
5352 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5353 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5354 else
5355 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5356 DPLL_FPA01_P1_POST_DIV_SHIFT);
5357
5358 switch (dpll & DPLL_MODE_MASK) {
5359 case DPLLB_MODE_DAC_SERIAL:
5360 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5361 5 : 10;
5362 break;
5363 case DPLLB_MODE_LVDS:
5364 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5365 7 : 14;
5366 break;
5367 default:
28c97730 5368 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5369 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5370 return 0;
5371 }
5372
5373 /* XXX: Handle the 100Mhz refclk */
2177832f 5374 intel_clock(dev, 96000, &clock);
79e53945
JB		 5375 } else {
5376 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5377
5378 if (is_lvds) {
5379 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5380 DPLL_FPA01_P1_POST_DIV_SHIFT);
5381 clock.p2 = 14;
5382
5383 if ((dpll & PLL_REF_INPUT_MASK) ==
5384 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5385 /* XXX: might not be 66MHz */
2177832f 5386 intel_clock(dev, 66000, &clock);
79e53945 5387 } else
2177832f 5388 intel_clock(dev, 48000, &clock);
79e53945
JB		 5389 } else {
5390 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5391 clock.p1 = 2;
5392 else {
5393 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5394 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5395 }
5396 if (dpll & PLL_P2_DIVIDE_BY_4)
5397 clock.p2 = 4;
5398 else
5399 clock.p2 = 2;
5400
2177832f 5401 intel_clock(dev, 48000, &clock);
79e53945
JB		 5402 }
5403 }
5404
5405 /* XXX: It would be nice to validate the clocks, but we can't reuse
5406 * i830PllIsValid() because it relies on the xf86_config connector
5407 * configuration being accurate, which it isn't necessarily.
5408 */
5409
5410 return clock.dot;
5411}
5412
5413/** Returns the currently programmed mode of the given pipe. */
5414struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5415 struct drm_crtc *crtc)
5416{
548f245b 5417 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419 int pipe = intel_crtc->pipe;
5420 struct drm_display_mode *mode;
548f245b
JB		 5421 int htot = I915_READ(HTOTAL(pipe));
5422 int hsync = I915_READ(HSYNC(pipe));
5423 int vtot = I915_READ(VTOTAL(pipe));
5424 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5425
5426 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5427 if (!mode)
5428 return NULL;
5429
5430 mode->clock = intel_crtc_clock_get(dev, crtc);
5431 mode->hdisplay = (htot & 0xffff) + 1;
5432 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5433 mode->hsync_start = (hsync & 0xffff) + 1;
5434 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5435 mode->vdisplay = (vtot & 0xffff) + 1;
5436 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5437 mode->vsync_start = (vsync & 0xffff) + 1;
5438 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5439
5440 drm_mode_set_name(mode);
79e53945
JB		 5441
5442 return mode;
5443}
5444
652c393a
JB		 5445#define GPU_IDLE_TIMEOUT 500 /* ms */
5446
5447/* When this timer fires, we've been idle for awhile */
5448static void intel_gpu_idle_timer(unsigned long arg)
5449{
5450 struct drm_device *dev = (struct drm_device *)arg;
5451 drm_i915_private_t *dev_priv = dev->dev_private;
5452
ff7ea4c0
CW		 5453 if (!list_empty(&dev_priv->mm.active_list)) {
5454 /* Still processing requests, so just re-arm the timer. */
5455 mod_timer(&dev_priv->idle_timer, jiffies +
5456 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5457 return;
5458 }
652c393a 5459
ff7ea4c0 5460 dev_priv->busy = false;
01dfba93 5461 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5462}
5463
652c393a
JB		 5464#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5465
5466static void intel_crtc_idle_timer(unsigned long arg)
5467{
5468 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5469 struct drm_crtc *crtc = &intel_crtc->base;
5470 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5471 struct intel_framebuffer *intel_fb;
652c393a 5472
ff7ea4c0
CW		 5473 intel_fb = to_intel_framebuffer(crtc->fb);
5474 if (intel_fb && intel_fb->obj->active) {
5475 /* The framebuffer is still being accessed by the GPU. */
5476 mod_timer(&intel_crtc->idle_timer, jiffies +
5477 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5478 return;
5479 }
652c393a 5480
ff7ea4c0 5481 intel_crtc->busy = false;
01dfba93 5482 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5483}
5484
3dec0095 5485static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5486{
5487 struct drm_device *dev = crtc->dev;
5488 drm_i915_private_t *dev_priv = dev->dev_private;
5489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5490 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5491 int dpll_reg = DPLL(pipe);
5492 int dpll;
652c393a 5493
bad720ff 5494 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5495 return;
5496
5497 if (!dev_priv->lvds_downclock_avail)
5498 return;
5499
dbdc6479 5500 dpll = I915_READ(dpll_reg);
652c393a 5501 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5502 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5503
8ac5a6d5 5504 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5505
5506 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5507 I915_WRITE(dpll_reg, dpll);
9d0498a2 5508 intel_wait_for_vblank(dev, pipe);
dbdc6479 5509
652c393a
JB		 5510 dpll = I915_READ(dpll_reg);
5511 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5512 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5513 }
5514
5515 /* Schedule downclock */
3dec0095
DV		 5516 mod_timer(&intel_crtc->idle_timer, jiffies +
5517 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5518}
5519
5520static void intel_decrease_pllclock(struct drm_crtc *crtc)
5521{
5522 struct drm_device *dev = crtc->dev;
5523 drm_i915_private_t *dev_priv = dev->dev_private;
5524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5525
bad720ff 5526 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5527 return;
5528
5529 if (!dev_priv->lvds_downclock_avail)
5530 return;
5531
5532 /*
5533 * Since this is called by a timer, we should never get here in
5534 * the manual case.
5535 */
5536 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5537 int pipe = intel_crtc->pipe;
5538 int dpll_reg = DPLL(pipe);
5539 int dpll;
f6e5b160 5540
44d98a61 5541 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5542
8ac5a6d5 5543 assert_panel_unlocked(dev_priv, pipe);
652c393a 5544
dc257cf1 5545 dpll = I915_READ(dpll_reg);
652c393a
JB		 5546 dpll |= DISPLAY_RATE_SELECT_FPA1;
5547 I915_WRITE(dpll_reg, dpll);
9d0498a2 5548 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5549 dpll = I915_READ(dpll_reg);
5550 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5551 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5552 }
5553
5554}
5555
5556/**
5557 * intel_idle_update - adjust clocks for idleness
5558 * @work: work struct
5559 *
5560 * Either the GPU or display (or both) went idle. Check the busy status
5561 * here and adjust the CRTC and GPU clocks as necessary.
5562 */
5563static void intel_idle_update(struct work_struct *work)
5564{
5565 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5566 idle_work);
5567 struct drm_device *dev = dev_priv->dev;
5568 struct drm_crtc *crtc;
5569 struct intel_crtc *intel_crtc;
5570
5571 if (!i915_powersave)
5572 return;
5573
5574 mutex_lock(&dev->struct_mutex);
5575
7648fa99
JB		 5576 i915_update_gfx_val(dev_priv);
5577
652c393a
JB		 5578 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5579 /* Skip inactive CRTCs */
5580 if (!crtc->fb)
5581 continue;
5582
5583 intel_crtc = to_intel_crtc(crtc);
5584 if (!intel_crtc->busy)
5585 intel_decrease_pllclock(crtc);
5586 }
5587
45ac22c8 5588
652c393a
JB		 5589 mutex_unlock(&dev->struct_mutex);
5590}
5591
5592/**
5593 * intel_mark_busy - mark the GPU and possibly the display busy
5594 * @dev: drm device
5595 * @obj: object we're operating on
5596 *
5597 * Callers can use this function to indicate that the GPU is busy processing
5598 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5599 * buffer), we'll also mark the display as busy, so we know to increase its
5600 * clock frequency.
5601 */
05394f39 5602void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5603{
5604 drm_i915_private_t *dev_priv = dev->dev_private;
5605 struct drm_crtc *crtc = NULL;
5606 struct intel_framebuffer *intel_fb;
5607 struct intel_crtc *intel_crtc;
5608
5e17ee74
ZW		 5609 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5610 return;
5611
9104183d
CW		 5612 if (!dev_priv->busy) {
5613 intel_sanitize_pm(dev);
28cf798f 5614 dev_priv->busy = true;
9104183d 5615 } else
28cf798f
CW		 5616 mod_timer(&dev_priv->idle_timer, jiffies +
5617 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 5618
acb87dfb
CW		 5619 if (obj == NULL)
5620 return;
5621
652c393a
JB		 5622 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5623 if (!crtc->fb)
5624 continue;
5625
5626 intel_crtc = to_intel_crtc(crtc);
5627 intel_fb = to_intel_framebuffer(crtc->fb);
5628 if (intel_fb->obj == obj) {
5629 if (!intel_crtc->busy) {
5630 /* Non-busy -> busy, upclock */
3dec0095 5631 intel_increase_pllclock(crtc);
652c393a
JB		 5632 intel_crtc->busy = true;
5633 } else {
5634 /* Busy -> busy, put off timer */
5635 mod_timer(&intel_crtc->idle_timer, jiffies +
5636 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5637 }
5638 }
5639 }
5640}
5641
79e53945
JB		 5642static void intel_crtc_destroy(struct drm_crtc *crtc)
5643{
5644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5645 struct drm_device *dev = crtc->dev;
5646 struct intel_unpin_work *work;
5647 unsigned long flags;
5648
5649 spin_lock_irqsave(&dev->event_lock, flags);
5650 work = intel_crtc->unpin_work;
5651 intel_crtc->unpin_work = NULL;
5652 spin_unlock_irqrestore(&dev->event_lock, flags);
5653
5654 if (work) {
5655 cancel_work_sync(&work->work);
5656 kfree(work);
5657 }
79e53945
JB		 5658
5659 drm_crtc_cleanup(crtc);
67e77c5a 5660
79e53945
JB		 5661 kfree(intel_crtc);
5662}
5663
6b95a207
KH		 5664static void intel_unpin_work_fn(struct work_struct *__work)
5665{
5666 struct intel_unpin_work *work =
5667 container_of(__work, struct intel_unpin_work, work);
5668
5669 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5670 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5671 drm_gem_object_unreference(&work->pending_flip_obj->base);
5672 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5673
7782de3b 5674 intel_update_fbc(work->dev);
6b95a207
KH		 5675 mutex_unlock(&work->dev->struct_mutex);
5676 kfree(work);
5677}
5678
1afe3e9d 5679static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5680 struct drm_crtc *crtc)
6b95a207
KH		 5681{
5682 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5684 struct intel_unpin_work *work;
05394f39 5685 struct drm_i915_gem_object *obj;
6b95a207 5686 struct drm_pending_vblank_event *e;
49b14a5c 5687 struct timeval tnow, tvbl;
6b95a207
KH		 5688 unsigned long flags;
5689
5690 /* Ignore early vblank irqs */
5691 if (intel_crtc == NULL)
5692 return;
5693
49b14a5c
MK		 5694 do_gettimeofday(&tnow);
5695
6b95a207
KH		 5696 spin_lock_irqsave(&dev->event_lock, flags);
5697 work = intel_crtc->unpin_work;
5698 if (work == NULL || !work->pending) {
5699 spin_unlock_irqrestore(&dev->event_lock, flags);
5700 return;
5701 }
5702
5703 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5704
5705 if (work->event) {
5706 e = work->event;
49b14a5c 5707 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5708
5709 /* Called before vblank count and timestamps have
5710 * been updated for the vblank interval of flip
5711 * completion? Need to increment vblank count and
5712 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5713 * to account for this. We assume this happened if we
5714 * get called over 0.9 frame durations after the last
5715 * timestamped vblank.
5716 *
5717 * This calculation can not be used with vrefresh rates
5718 * below 5Hz (10Hz to be on the safe side) without
5719 * promoting to 64 integers.
0af7e4df 5720 */
49b14a5c
MK		 5721 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5722 9 * crtc->framedur_ns) {
0af7e4df 5723 e->event.sequence++;
49b14a5c
MK		 5724 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5725 crtc->framedur_ns);
0af7e4df
MK		 5726 }
5727
49b14a5c
MK		 5728 e->event.tv_sec = tvbl.tv_sec;
5729 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5730
6b95a207
KH		 5731 list_add_tail(&e->base.link,
5732 &e->base.file_priv->event_list);
5733 wake_up_interruptible(&e->base.file_priv->event_wait);
5734 }
5735
0af7e4df
MK		 5736 drm_vblank_put(dev, intel_crtc->pipe);
5737
6b95a207
KH		 5738 spin_unlock_irqrestore(&dev->event_lock, flags);
5739
05394f39 5740 obj = work->old_fb_obj;
d9e86c0e 5741
e59f2bac 5742 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5743 &obj->pending_flip.counter);
5744 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5745 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5746
6b95a207 5747 schedule_work(&work->work);
e5510fac
JB		 5748
5749 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5750}
5751
1afe3e9d
JB		 5752void intel_finish_page_flip(struct drm_device *dev, int pipe)
5753{
5754 drm_i915_private_t *dev_priv = dev->dev_private;
5755 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5756
49b14a5c 5757 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5758}
5759
5760void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5761{
5762 drm_i915_private_t *dev_priv = dev->dev_private;
5763 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5764
49b14a5c 5765 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5766}
5767
6b95a207
KH		 5768void intel_prepare_page_flip(struct drm_device *dev, int plane)
5769{
5770 drm_i915_private_t *dev_priv = dev->dev_private;
5771 struct intel_crtc *intel_crtc =
5772 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5773 unsigned long flags;
5774
5775 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5776 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5777 if ((++intel_crtc->unpin_work->pending) > 1)
5778 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5779 } else {
5780 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5781 }
6b95a207
KH		 5782 spin_unlock_irqrestore(&dev->event_lock, flags);
5783}
5784
8c9f3aaf
JB		 5785static int intel_gen2_queue_flip(struct drm_device *dev,
5786 struct drm_crtc *crtc,
5787 struct drm_framebuffer *fb,
5788 struct drm_i915_gem_object *obj)
5789{
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5792 unsigned long offset;
5793 u32 flip_mask;
6d90c952 5794 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5795 int ret;
5796
6d90c952 5797 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5798 if (ret)
83d4092b 5799 goto err;
8c9f3aaf
JB		 5800
5801 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5802 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5803
6d90c952 5804 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5805 if (ret)
83d4092b 5806 goto err_unpin;
8c9f3aaf
JB		 5807
5808 /* Can't queue multiple flips, so wait for the previous
5809 * one to finish before executing the next.
5810 */
5811 if (intel_crtc->plane)
5812 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5813 else
5814 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5815 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5816 intel_ring_emit(ring, MI_NOOP);
5817 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5818 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5819 intel_ring_emit(ring, fb->pitches[0]);
5820 intel_ring_emit(ring, obj->gtt_offset + offset);
5821 intel_ring_emit(ring, 0); /* aux display base address, unused */
5822 intel_ring_advance(ring);
83d4092b
CW		 5823 return 0;
5824
5825err_unpin:
5826 intel_unpin_fb_obj(obj);
5827err:
8c9f3aaf
JB		 5828 return ret;
5829}
5830
5831static int intel_gen3_queue_flip(struct drm_device *dev,
5832 struct drm_crtc *crtc,
5833 struct drm_framebuffer *fb,
5834 struct drm_i915_gem_object *obj)
5835{
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5838 unsigned long offset;
5839 u32 flip_mask;
6d90c952 5840 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5841 int ret;
5842
6d90c952 5843 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5844 if (ret)
83d4092b 5845 goto err;
8c9f3aaf
JB		 5846
5847 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5848 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5849
6d90c952 5850 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5851 if (ret)
83d4092b 5852 goto err_unpin;
8c9f3aaf
JB		 5853
5854 if (intel_crtc->plane)
5855 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5856 else
5857 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5858 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5859 intel_ring_emit(ring, MI_NOOP);
5860 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5861 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5862 intel_ring_emit(ring, fb->pitches[0]);
5863 intel_ring_emit(ring, obj->gtt_offset + offset);
5864 intel_ring_emit(ring, MI_NOOP);
5865
5866 intel_ring_advance(ring);
83d4092b
CW		 5867 return 0;
5868
5869err_unpin:
5870 intel_unpin_fb_obj(obj);
5871err:
8c9f3aaf
JB		 5872 return ret;
5873}
5874
5875static int intel_gen4_queue_flip(struct drm_device *dev,
5876 struct drm_crtc *crtc,
5877 struct drm_framebuffer *fb,
5878 struct drm_i915_gem_object *obj)
5879{
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5882 uint32_t pf, pipesrc;
6d90c952 5883 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5884 int ret;
5885
6d90c952 5886 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5887 if (ret)
83d4092b 5888 goto err;
8c9f3aaf 5889
6d90c952 5890 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5891 if (ret)
83d4092b 5892 goto err_unpin;
8c9f3aaf
JB		 5893
5894 /* i965+ uses the linear or tiled offsets from the
5895 * Display Registers (which do not change across a page-flip)
5896 * so we need only reprogram the base address.
5897 */
6d90c952
DV		 5898 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5899 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5900 intel_ring_emit(ring, fb->pitches[0]);
5901 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 5902
5903 /* XXX Enabling the panel-fitter across page-flip is so far
5904 * untested on non-native modes, so ignore it for now.
5905 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5906 */
5907 pf = 0;
5908 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5909 intel_ring_emit(ring, pf | pipesrc);
5910 intel_ring_advance(ring);
83d4092b
CW		 5911 return 0;
5912
5913err_unpin:
5914 intel_unpin_fb_obj(obj);
5915err:
8c9f3aaf
JB		 5916 return ret;
5917}
5918
5919static int intel_gen6_queue_flip(struct drm_device *dev,
5920 struct drm_crtc *crtc,
5921 struct drm_framebuffer *fb,
5922 struct drm_i915_gem_object *obj)
5923{
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 5926 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5927 uint32_t pf, pipesrc;
5928 int ret;
5929
6d90c952 5930 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5931 if (ret)
83d4092b 5932 goto err;
8c9f3aaf 5933
6d90c952 5934 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5935 if (ret)
83d4092b 5936 goto err_unpin;
8c9f3aaf 5937
6d90c952
DV		 5938 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5939 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5940 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5941 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 5942
dc257cf1
DV		 5943 /* Contrary to the suggestions in the documentation,
5944 * "Enable Panel Fitter" does not seem to be required when page
5945 * flipping with a non-native mode, and worse causes a normal
5946 * modeset to fail.
5947 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5948 */
5949 pf = 0;
8c9f3aaf 5950 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5951 intel_ring_emit(ring, pf | pipesrc);
5952 intel_ring_advance(ring);
83d4092b
CW		 5953 return 0;
5954
5955err_unpin:
5956 intel_unpin_fb_obj(obj);
5957err:
8c9f3aaf
JB		 5958 return ret;
5959}
5960
7c9017e5
JB		 5961/*
5962 * On gen7 we currently use the blit ring because (in early silicon at least)
5963 * the render ring doesn't give us interrpts for page flip completion, which
5964 * means clients will hang after the first flip is queued. Fortunately the
5965 * blit ring generates interrupts properly, so use it instead.
5966 */
5967static int intel_gen7_queue_flip(struct drm_device *dev,
5968 struct drm_crtc *crtc,
5969 struct drm_framebuffer *fb,
5970 struct drm_i915_gem_object *obj)
5971{
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5974 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5975 int ret;
5976
5977 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5978 if (ret)
83d4092b 5979 goto err;
7c9017e5
JB		 5980
5981 ret = intel_ring_begin(ring, 4);
5982 if (ret)
83d4092b 5983 goto err_unpin;
7c9017e5
JB		 5984
5985 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 5986 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 5987 intel_ring_emit(ring, (obj->gtt_offset));
5988 intel_ring_emit(ring, (MI_NOOP));
5989 intel_ring_advance(ring);
83d4092b
CW		 5990 return 0;
5991
5992err_unpin:
5993 intel_unpin_fb_obj(obj);
5994err:
7c9017e5
JB		 5995 return ret;
5996}
5997
8c9f3aaf
JB		 5998static int intel_default_queue_flip(struct drm_device *dev,
5999 struct drm_crtc *crtc,
6000 struct drm_framebuffer *fb,
6001 struct drm_i915_gem_object *obj)
6002{
6003 return -ENODEV;
6004}
6005
6b95a207
KH		 6006static int intel_crtc_page_flip(struct drm_crtc *crtc,
6007 struct drm_framebuffer *fb,
6008 struct drm_pending_vblank_event *event)
6009{
6010 struct drm_device *dev = crtc->dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 struct intel_framebuffer *intel_fb;
05394f39 6013 struct drm_i915_gem_object *obj;
6b95a207
KH		 6014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6015 struct intel_unpin_work *work;
8c9f3aaf 6016 unsigned long flags;
52e68630 6017 int ret;
6b95a207
KH		 6018
6019 work = kzalloc(sizeof *work, GFP_KERNEL);
6020 if (work == NULL)
6021 return -ENOMEM;
6022
6b95a207
KH		 6023 work->event = event;
6024 work->dev = crtc->dev;
6025 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6026 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6027 INIT_WORK(&work->work, intel_unpin_work_fn);
6028
7317c75e
JB		 6029 ret = drm_vblank_get(dev, intel_crtc->pipe);
6030 if (ret)
6031 goto free_work;
6032
6b95a207
KH		 6033 /* We borrow the event spin lock for protecting unpin_work */
6034 spin_lock_irqsave(&dev->event_lock, flags);
6035 if (intel_crtc->unpin_work) {
6036 spin_unlock_irqrestore(&dev->event_lock, flags);
6037 kfree(work);
7317c75e 6038 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6039
6040 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6041 return -EBUSY;
6042 }
6043 intel_crtc->unpin_work = work;
6044 spin_unlock_irqrestore(&dev->event_lock, flags);
6045
6046 intel_fb = to_intel_framebuffer(fb);
6047 obj = intel_fb->obj;
6048
468f0b44 6049 mutex_lock(&dev->struct_mutex);
6b95a207 6050
75dfca80 6051 /* Reference the objects for the scheduled work. */
05394f39
CW		 6052 drm_gem_object_reference(&work->old_fb_obj->base);
6053 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6054
6055 crtc->fb = fb;
96b099fd 6056
e1f99ce6 6057 work->pending_flip_obj = obj;
e1f99ce6 6058
4e5359cd
SF		 6059 work->enable_stall_check = true;
6060
e1f99ce6
CW		 6061 /* Block clients from rendering to the new back buffer until
6062 * the flip occurs and the object is no longer visible.
6063 */
05394f39 6064 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6065
8c9f3aaf
JB		 6066 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6067 if (ret)
6068 goto cleanup_pending;
6b95a207 6069
7782de3b 6070 intel_disable_fbc(dev);
acb87dfb 6071 intel_mark_busy(dev, obj);
6b95a207
KH		 6072 mutex_unlock(&dev->struct_mutex);
6073
e5510fac
JB		 6074 trace_i915_flip_request(intel_crtc->plane, obj);
6075
6b95a207 6076 return 0;
96b099fd 6077
8c9f3aaf
JB		 6078cleanup_pending:
6079 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6080 drm_gem_object_unreference(&work->old_fb_obj->base);
6081 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6082 mutex_unlock(&dev->struct_mutex);
6083
6084 spin_lock_irqsave(&dev->event_lock, flags);
6085 intel_crtc->unpin_work = NULL;
6086 spin_unlock_irqrestore(&dev->event_lock, flags);
6087
7317c75e
JB		 6088 drm_vblank_put(dev, intel_crtc->pipe);
6089free_work:
96b099fd
CW		 6090 kfree(work);
6091
6092 return ret;
6b95a207
KH		 6093}
6094
47f1c6c9
CW		 6095static void intel_sanitize_modesetting(struct drm_device *dev,
6096 int pipe, int plane)
6097{
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099 u32 reg, val;
6100
f47166d2
CW		 6101 /* Clear any frame start delays used for debugging left by the BIOS */
6102 for_each_pipe(pipe) {
6103 reg = PIPECONF(pipe);
6104 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6105 }
6106
47f1c6c9
CW		 6107 if (HAS_PCH_SPLIT(dev))
6108 return;
6109
6110 /* Who knows what state these registers were left in by the BIOS or
6111 * grub?
6112 *
6113 * If we leave the registers in a conflicting state (e.g. with the
6114 * display plane reading from the other pipe than the one we intend
6115 * to use) then when we attempt to teardown the active mode, we will
6116 * not disable the pipes and planes in the correct order -- leaving
6117 * a plane reading from a disabled pipe and possibly leading to
6118 * undefined behaviour.
6119 */
6120
6121 reg = DSPCNTR(plane);
6122 val = I915_READ(reg);
6123
6124 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6125 return;
6126 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6127 return;
6128
6129 /* This display plane is active and attached to the other CPU pipe. */
6130 pipe = !pipe;
6131
6132 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6133 intel_disable_plane(dev_priv, plane, pipe);
6134 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6135}
79e53945 6136
f6e5b160
CW		 6137static void intel_crtc_reset(struct drm_crtc *crtc)
6138{
6139 struct drm_device *dev = crtc->dev;
6140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6141
6142 /* Reset flags back to the 'unknown' status so that they
6143 * will be correctly set on the initial modeset.
6144 */
6145 intel_crtc->dpms_mode = -1;
6146
6147 /* We need to fix up any BIOS configuration that conflicts with
6148 * our expectations.
6149 */
6150 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6151}
6152
6153static struct drm_crtc_helper_funcs intel_helper_funcs = {
6154 .dpms = intel_crtc_dpms,
6155 .mode_fixup = intel_crtc_mode_fixup,
6156 .mode_set = intel_crtc_mode_set,
6157 .mode_set_base = intel_pipe_set_base,
6158 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6159 .load_lut = intel_crtc_load_lut,
6160 .disable = intel_crtc_disable,
6161};
6162
6163static const struct drm_crtc_funcs intel_crtc_funcs = {
6164 .reset = intel_crtc_reset,
6165 .cursor_set = intel_crtc_cursor_set,
6166 .cursor_move = intel_crtc_cursor_move,
6167 .gamma_set = intel_crtc_gamma_set,
6168 .set_config = drm_crtc_helper_set_config,
6169 .destroy = intel_crtc_destroy,
6170 .page_flip = intel_crtc_page_flip,
6171};
6172
ee7b9f93
JB		 6173static void intel_pch_pll_init(struct drm_device *dev)
6174{
6175 drm_i915_private_t *dev_priv = dev->dev_private;
6176 int i;
6177
6178 if (dev_priv->num_pch_pll == 0) {
6179 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6180 return;
6181 }
6182
6183 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6184 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6185 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6186 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6187 }
6188}
6189
b358d0a6 6190static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6191{
22fd0fab 6192 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6193 struct intel_crtc *intel_crtc;
6194 int i;
6195
6196 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6197 if (intel_crtc == NULL)
6198 return;
6199
6200 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6201
6202 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6203 for (i = 0; i < 256; i++) {
6204 intel_crtc->lut_r[i] = i;
6205 intel_crtc->lut_g[i] = i;
6206 intel_crtc->lut_b[i] = i;
6207 }
6208
80824003
JB		 6209 /* Swap pipes & planes for FBC on pre-965 */
6210 intel_crtc->pipe = pipe;
6211 intel_crtc->plane = pipe;
e2e767ab 6212 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6213 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6214 intel_crtc->plane = !pipe;
80824003
JB		 6215 }
6216
22fd0fab
JB		 6217 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6218 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6219 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6220 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6221
5d1d0cc8 6222 intel_crtc_reset(&intel_crtc->base);
04dbff52 6223 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6224 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6225
6226 if (HAS_PCH_SPLIT(dev)) {
6227 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6228 intel_helper_funcs.commit = ironlake_crtc_commit;
6229 } else {
6230 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6231 intel_helper_funcs.commit = i9xx_crtc_commit;
6232 }
6233
79e53945
JB		 6234 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6235
652c393a
JB		 6236 intel_crtc->busy = false;
6237
6238 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6239 (unsigned long)intel_crtc);
79e53945
JB		 6240}
6241
08d7b3d1 6242int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6243 struct drm_file *file)
08d7b3d1 6244{
08d7b3d1 6245 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6246 struct drm_mode_object *drmmode_obj;
6247 struct intel_crtc *crtc;
08d7b3d1 6248
1cff8f6b
DV		 6249 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6250 return -ENODEV;
08d7b3d1 6251
c05422d5
DV		 6252 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6253 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6254
c05422d5 6255 if (!drmmode_obj) {
08d7b3d1
CW		 6256 DRM_ERROR("no such CRTC id\n");
6257 return -EINVAL;
6258 }
6259
c05422d5
DV		 6260 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6261 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6262
c05422d5 6263 return 0;
08d7b3d1
CW		 6264}
6265
c5e4df33 6266static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6267{
4ef69c7a 6268 struct intel_encoder *encoder;
79e53945 6269 int index_mask = 0;
79e53945
JB		 6270 int entry = 0;
6271
4ef69c7a
CW		 6272 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6273 if (type_mask & encoder->clone_mask)
79e53945
JB		 6274 index_mask |= (1 << entry);
6275 entry++;
6276 }
4ef69c7a 6277
79e53945
JB		 6278 return index_mask;
6279}
6280
4d302442
CW		 6281static bool has_edp_a(struct drm_device *dev)
6282{
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284
6285 if (!IS_MOBILE(dev))
6286 return false;
6287
6288 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6289 return false;
6290
6291 if (IS_GEN5(dev) &&
6292 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6293 return false;
6294
6295 return true;
6296}
6297
79e53945
JB		 6298static void intel_setup_outputs(struct drm_device *dev)
6299{
725e30ad 6300 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6301 struct intel_encoder *encoder;
cb0953d7 6302 bool dpd_is_edp = false;
f3cfcba6 6303 bool has_lvds;
79e53945 6304
f3cfcba6 6305 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6306 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6307 /* disable the panel fitter on everything but LVDS */
6308 I915_WRITE(PFIT_CONTROL, 0);
6309 }
79e53945 6310
bad720ff 6311 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6312 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6313
4d302442 6314 if (has_edp_a(dev))
32f9d658
ZW		 6315 intel_dp_init(dev, DP_A);
6316
cb0953d7
AJ		 6317 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6318 intel_dp_init(dev, PCH_DP_D);
6319 }
6320
6321 intel_crt_init(dev);
6322
6323 if (HAS_PCH_SPLIT(dev)) {
6324 int found;
6325
30ad48b7 6326 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6327 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6328 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6329 if (!found)
6330 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6331 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6332 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6333 }
6334
6335 if (I915_READ(HDMIC) & PORT_DETECTED)
6336 intel_hdmi_init(dev, HDMIC);
6337
6338 if (I915_READ(HDMID) & PORT_DETECTED)
6339 intel_hdmi_init(dev, HDMID);
6340
5eb08b69
ZW		 6341 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6342 intel_dp_init(dev, PCH_DP_C);
6343
cb0953d7 6344 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6345 intel_dp_init(dev, PCH_DP_D);
6346
103a196f 6347 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6348 bool found = false;
7d57382e 6349
725e30ad 6350 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6351 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6352 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6353 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6354 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6355 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6356 }
27185ae1 6357
b01f2c3a
JB		 6358 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6359 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6360 intel_dp_init(dev, DP_B);
b01f2c3a 6361 }
725e30ad 6362 }
13520b05
KH		 6363
6364 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6365
b01f2c3a
JB		 6366 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6367 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6368 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6369 }
27185ae1
ML		 6370
6371 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6372
b01f2c3a
JB		 6373 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6374 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6375 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6376 }
6377 if (SUPPORTS_INTEGRATED_DP(dev)) {
6378 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6379 intel_dp_init(dev, DP_C);
b01f2c3a 6380 }
725e30ad 6381 }
27185ae1 6382
b01f2c3a
JB		 6383 if (SUPPORTS_INTEGRATED_DP(dev) &&
6384 (I915_READ(DP_D) & DP_DETECTED)) {
6385 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6386 intel_dp_init(dev, DP_D);
b01f2c3a 6387 }
bad720ff 6388 } else if (IS_GEN2(dev))
79e53945
JB		 6389 intel_dvo_init(dev);
6390
103a196f 6391 if (SUPPORTS_TV(dev))
79e53945
JB		 6392 intel_tv_init(dev);
6393
4ef69c7a
CW		 6394 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6395 encoder->base.possible_crtcs = encoder->crtc_mask;
6396 encoder->base.possible_clones =
6397 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6398 }
47356eb6 6399
2c7111db
CW		 6400 /* disable all the possible outputs/crtcs before entering KMS mode */
6401 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6402
6403 if (HAS_PCH_SPLIT(dev))
6404 ironlake_init_pch_refclk(dev);
79e53945
JB		 6405}
6406
6407static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6408{
6409 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6410
6411 drm_framebuffer_cleanup(fb);
05394f39 6412 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6413
6414 kfree(intel_fb);
6415}
6416
6417static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6418 struct drm_file *file,
79e53945
JB		 6419 unsigned int *handle)
6420{
6421 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6422 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6423
05394f39 6424 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6425}
6426
6427static const struct drm_framebuffer_funcs intel_fb_funcs = {
6428 .destroy = intel_user_framebuffer_destroy,
6429 .create_handle = intel_user_framebuffer_create_handle,
6430};
6431
38651674
DA		 6432int intel_framebuffer_init(struct drm_device *dev,
6433 struct intel_framebuffer *intel_fb,
308e5bcb 6434 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6435 struct drm_i915_gem_object *obj)
79e53945 6436{
79e53945
JB		 6437 int ret;
6438
05394f39 6439 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6440 return -EINVAL;
6441
308e5bcb 6442 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6443 return -EINVAL;
6444
308e5bcb 6445 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6446 case DRM_FORMAT_RGB332:
6447 case DRM_FORMAT_RGB565:
6448 case DRM_FORMAT_XRGB8888:
b250da79 6449 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6450 case DRM_FORMAT_ARGB8888:
6451 case DRM_FORMAT_XRGB2101010:
6452 case DRM_FORMAT_ARGB2101010:
308e5bcb 6453 /* RGB formats are common across chipsets */
b5626747 6454 break;
04b3924d
VS		 6455 case DRM_FORMAT_YUYV:
6456 case DRM_FORMAT_UYVY:
6457 case DRM_FORMAT_YVYU:
6458 case DRM_FORMAT_VYUY:
57cd6508
CW		 6459 break;
6460 default:
aca25848
ED		 6461 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6462 mode_cmd->pixel_format);
57cd6508
CW		 6463 return -EINVAL;
6464 }
6465
79e53945
JB		 6466 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6467 if (ret) {
6468 DRM_ERROR("framebuffer init failed %d\n", ret);
6469 return ret;
6470 }
6471
6472 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6473 intel_fb->obj = obj;
79e53945
JB		 6474 return 0;
6475}
6476
79e53945
JB		 6477static struct drm_framebuffer *
6478intel_user_framebuffer_create(struct drm_device *dev,
6479 struct drm_file *filp,
308e5bcb 6480 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6481{
05394f39 6482 struct drm_i915_gem_object *obj;
79e53945 6483
308e5bcb
JB		 6484 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6485 mode_cmd->handles[0]));
c8725226 6486 if (&obj->base == NULL)
cce13ff7 6487 return ERR_PTR(-ENOENT);
79e53945 6488
d2dff872 6489 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6490}
6491
79e53945 6492static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6493 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6494 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6495};
6496
e70236a8
JB		 6497/* Set up chip specific display functions */
6498static void intel_init_display(struct drm_device *dev)
6499{
6500 struct drm_i915_private *dev_priv = dev->dev_private;
6501
6502 /* We always want a DPMS function */
f564048e 6503 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6504 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6505 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6506 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6507 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6508 } else {
e70236a8 6509 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6510 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6511 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6512 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6513 }
e70236a8 6514
e70236a8 6515 /* Returns the core display clock speed */
25eb05fc
JB		 6516 if (IS_VALLEYVIEW(dev))
6517 dev_priv->display.get_display_clock_speed =
6518 valleyview_get_display_clock_speed;
6519 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6520 dev_priv->display.get_display_clock_speed =
6521 i945_get_display_clock_speed;
6522 else if (IS_I915G(dev))
6523 dev_priv->display.get_display_clock_speed =
6524 i915_get_display_clock_speed;
f2b115e6 6525 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6526 dev_priv->display.get_display_clock_speed =
6527 i9xx_misc_get_display_clock_speed;
6528 else if (IS_I915GM(dev))
6529 dev_priv->display.get_display_clock_speed =
6530 i915gm_get_display_clock_speed;
6531 else if (IS_I865G(dev))
6532 dev_priv->display.get_display_clock_speed =
6533 i865_get_display_clock_speed;
f0f8a9ce 6534 else if (IS_I85X(dev))
e70236a8
JB		 6535 dev_priv->display.get_display_clock_speed =
6536 i855_get_display_clock_speed;
6537 else /* 852, 830 */
6538 dev_priv->display.get_display_clock_speed =
6539 i830_get_display_clock_speed;
6540
7f8a8569 6541 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6542 if (IS_GEN5(dev)) {
674cf967 6543 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6544 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6545 } else if (IS_GEN6(dev)) {
674cf967 6546 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6547 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6548 } else if (IS_IVYBRIDGE(dev)) {
6549 /* FIXME: detect B0+ stepping and use auto training */
6550 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6551 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6552 } else
6553 dev_priv->display.update_wm = NULL;
ceb04246 6554 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6555 dev_priv->display.force_wake_get = vlv_force_wake_get;
6556 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6557 } else if (IS_G4X(dev)) {
e0dac65e 6558 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6559 }
8c9f3aaf
JB		 6560
6561 /* Default just returns -ENODEV to indicate unsupported */
6562 dev_priv->display.queue_flip = intel_default_queue_flip;
6563
6564 switch (INTEL_INFO(dev)->gen) {
6565 case 2:
6566 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6567 break;
6568
6569 case 3:
6570 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6571 break;
6572
6573 case 4:
6574 case 5:
6575 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6576 break;
6577
6578 case 6:
6579 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6580 break;
7c9017e5
JB		 6581 case 7:
6582 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6583 break;
8c9f3aaf 6584 }
e70236a8
JB		 6585}
6586
b690e96c
JB		 6587/*
6588 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6589 * resume, or other times. This quirk makes sure that's the case for
6590 * affected systems.
6591 */
0206e353 6592static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6593{
6594 struct drm_i915_private *dev_priv = dev->dev_private;
6595
6596 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6597 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6598}
6599
435793df
KP		 6600/*
6601 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6602 */
6603static void quirk_ssc_force_disable(struct drm_device *dev)
6604{
6605 struct drm_i915_private *dev_priv = dev->dev_private;
6606 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6607 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6608}
6609
4dca20ef 6610/*
5a15ab5b
CE		 6611 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6612 * brightness value
4dca20ef
CE		 6613 */
6614static void quirk_invert_brightness(struct drm_device *dev)
6615{
6616 struct drm_i915_private *dev_priv = dev->dev_private;
6617 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6618 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6619}
6620
b690e96c
JB		 6621struct intel_quirk {
6622 int device;
6623 int subsystem_vendor;
6624 int subsystem_device;
6625 void (*hook)(struct drm_device *dev);
6626};
6627
c43b5634 6628static struct intel_quirk intel_quirks[] = {
b690e96c 6629 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6630 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6631
6632 /* Thinkpad R31 needs pipe A force quirk */
6633 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6634 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6635 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6636
6637 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6638 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6639 /* ThinkPad X40 needs pipe A force quirk */
6640
6641 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6642 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6643
6644 /* 855 & before need to leave pipe A & dpll A up */
6645 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6646 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6647
6648 /* Lenovo U160 cannot use SSC on LVDS */
6649 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6650
6651 /* Sony Vaio Y cannot use SSC on LVDS */
6652 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6653
6654 /* Acer Aspire 5734Z must invert backlight brightness */
6655 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6656};
6657
6658static void intel_init_quirks(struct drm_device *dev)
6659{
6660 struct pci_dev *d = dev->pdev;
6661 int i;
6662
6663 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6664 struct intel_quirk *q = &intel_quirks[i];
6665
6666 if (d->device == q->device &&
6667 (d->subsystem_vendor == q->subsystem_vendor ||
6668 q->subsystem_vendor == PCI_ANY_ID) &&
6669 (d->subsystem_device == q->subsystem_device ||
6670 q->subsystem_device == PCI_ANY_ID))
6671 q->hook(dev);
6672 }
6673}
6674
9cce37f4
JB		 6675/* Disable the VGA plane that we never use */
6676static void i915_disable_vga(struct drm_device *dev)
6677{
6678 struct drm_i915_private *dev_priv = dev->dev_private;
6679 u8 sr1;
6680 u32 vga_reg;
6681
6682 if (HAS_PCH_SPLIT(dev))
6683 vga_reg = CPU_VGACNTRL;
6684 else
6685 vga_reg = VGACNTRL;
6686
6687 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6688 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6689 sr1 = inb(VGA_SR_DATA);
6690 outb(sr1 | 1<<5, VGA_SR_DATA);
6691 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6692 udelay(300);
6693
6694 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6695 POSTING_READ(vga_reg);
6696}
6697
f82cfb6b
JB		 6698static void ivb_pch_pwm_override(struct drm_device *dev)
6699{
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701
6702 /*
6703 * IVB has CPU eDP backlight regs too, set things up to let the
6704 * PCH regs control the backlight
6705 */
6706 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6707 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6708 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6709}
6710
f817586c
DV		 6711void intel_modeset_init_hw(struct drm_device *dev)
6712{
6713 struct drm_i915_private *dev_priv = dev->dev_private;
6714
6715 intel_init_clock_gating(dev);
6716
6717 if (IS_IRONLAKE_M(dev)) {
6718 ironlake_enable_drps(dev);
1833b134 6719 ironlake_enable_rc6(dev);
f817586c
DV		 6720 intel_init_emon(dev);
6721 }
6722
b6834bd6 6723 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6724 gen6_enable_rps(dev_priv);
6725 gen6_update_ring_freq(dev_priv);
6726 }
f82cfb6b
JB		 6727
6728 if (IS_IVYBRIDGE(dev))
6729 ivb_pch_pwm_override(dev);
f817586c
DV		 6730}
6731
79e53945
JB		 6732void intel_modeset_init(struct drm_device *dev)
6733{
652c393a 6734 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6735 int i, ret;
79e53945
JB		 6736
6737 drm_mode_config_init(dev);
6738
6739 dev->mode_config.min_width = 0;
6740 dev->mode_config.min_height = 0;
6741
019d96cb
DA		 6742 dev->mode_config.preferred_depth = 24;
6743 dev->mode_config.prefer_shadow = 1;
6744
79e53945
JB		 6745 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6746
b690e96c
JB		 6747 intel_init_quirks(dev);
6748
1fa61106
ED		 6749 intel_init_pm(dev);
6750
e70236a8
JB		 6751 intel_init_display(dev);
6752
a6c45cf0
CW		 6753 if (IS_GEN2(dev)) {
6754 dev->mode_config.max_width = 2048;
6755 dev->mode_config.max_height = 2048;
6756 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6757 dev->mode_config.max_width = 4096;
6758 dev->mode_config.max_height = 4096;
79e53945 6759 } else {
a6c45cf0
CW		 6760 dev->mode_config.max_width = 8192;
6761 dev->mode_config.max_height = 8192;
79e53945 6762 }
35c3047a 6763 dev->mode_config.fb_base = dev->agp->base;
79e53945 6764
28c97730 6765 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6766 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6767
a3524f1b 6768 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6769 intel_crtc_init(dev, i);
00c2064b
JB		 6770 ret = intel_plane_init(dev, i);
6771 if (ret)
6772 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6773 }
6774
ee7b9f93
JB		 6775 intel_pch_pll_init(dev);
6776
9cce37f4
JB		 6777 /* Just disable it once at startup */
6778 i915_disable_vga(dev);
79e53945 6779 intel_setup_outputs(dev);
652c393a 6780
652c393a
JB		 6781 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6782 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6783 (unsigned long)dev);
2c7111db
CW		 6784}
6785
6786void intel_modeset_gem_init(struct drm_device *dev)
6787{
1833b134 6788 intel_modeset_init_hw(dev);
02e792fb
DV		 6789
6790 intel_setup_overlay(dev);
79e53945
JB		 6791}
6792
6793void intel_modeset_cleanup(struct drm_device *dev)
6794{
652c393a
JB		 6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 struct drm_crtc *crtc;
6797 struct intel_crtc *intel_crtc;
6798
f87ea761 6799 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6800 mutex_lock(&dev->struct_mutex);
6801
723bfd70
JB		 6802 intel_unregister_dsm_handler();
6803
6804
652c393a
JB		 6805 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6806 /* Skip inactive CRTCs */
6807 if (!crtc->fb)
6808 continue;
6809
6810 intel_crtc = to_intel_crtc(crtc);
3dec0095 6811 intel_increase_pllclock(crtc);
652c393a
JB		 6812 }
6813
973d04f9 6814 intel_disable_fbc(dev);
e70236a8 6815
f97108d1
JB		 6816 if (IS_IRONLAKE_M(dev))
6817 ironlake_disable_drps(dev);
b6834bd6 6818 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 6819 gen6_disable_rps(dev);
f97108d1 6820
d5bb081b
JB		 6821 if (IS_IRONLAKE_M(dev))
6822 ironlake_disable_rc6(dev);
0cdab21f 6823
57f350b6
JB		 6824 if (IS_VALLEYVIEW(dev))
6825 vlv_init_dpio(dev);
6826
69341a5e
KH		 6827 mutex_unlock(&dev->struct_mutex);
6828
6c0d9350
DV		 6829 /* Disable the irq before mode object teardown, for the irq might
6830 * enqueue unpin/hotplug work. */
6831 drm_irq_uninstall(dev);
6832 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 6833 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 6834
1630fe75
CW		 6835 /* flush any delayed tasks or pending work */
6836 flush_scheduled_work();
6837
3dec0095
DV		 6838 /* Shut off idle work before the crtcs get freed. */
6839 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6840 intel_crtc = to_intel_crtc(crtc);
6841 del_timer_sync(&intel_crtc->idle_timer);
6842 }
6843 del_timer_sync(&dev_priv->idle_timer);
6844 cancel_work_sync(&dev_priv->idle_work);
6845
79e53945
JB		 6846 drm_mode_config_cleanup(dev);
6847}
6848
f1c79df3
ZW		 6849/*
6850 * Return which encoder is currently attached for connector.
6851 */
df0e9248 6852struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 6853{
df0e9248
CW		 6854 return &intel_attached_encoder(connector)->base;
6855}
f1c79df3 6856
df0e9248
CW		 6857void intel_connector_attach_encoder(struct intel_connector *connector,
6858 struct intel_encoder *encoder)
6859{
6860 connector->encoder = encoder;
6861 drm_mode_connector_attach_encoder(&connector->base,
6862 &encoder->base);
79e53945 6863}
28d52043
DA		 6864
6865/*
6866 * set vga decode state - true == enable VGA decode
6867 */
6868int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6869{
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871 u16 gmch_ctrl;
6872
6873 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6874 if (state)
6875 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6876 else
6877 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6878 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6879 return 0;
6880}
c4a1d9e4
CW		 6881
6882#ifdef CONFIG_DEBUG_FS
6883#include <linux/seq_file.h>
6884
6885struct intel_display_error_state {
6886 struct intel_cursor_error_state {
6887 u32 control;
6888 u32 position;
6889 u32 base;
6890 u32 size;
6891 } cursor[2];
6892
6893 struct intel_pipe_error_state {
6894 u32 conf;
6895 u32 source;
6896
6897 u32 htotal;
6898 u32 hblank;
6899 u32 hsync;
6900 u32 vtotal;
6901 u32 vblank;
6902 u32 vsync;
6903 } pipe[2];
6904
6905 struct intel_plane_error_state {
6906 u32 control;
6907 u32 stride;
6908 u32 size;
6909 u32 pos;
6910 u32 addr;
6911 u32 surface;
6912 u32 tile_offset;
6913 } plane[2];
6914};
6915
6916struct intel_display_error_state *
6917intel_display_capture_error_state(struct drm_device *dev)
6918{
0206e353 6919 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 6920 struct intel_display_error_state *error;
6921 int i;
6922
6923 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6924 if (error == NULL)
6925 return NULL;
6926
6927 for (i = 0; i < 2; i++) {
6928 error->cursor[i].control = I915_READ(CURCNTR(i));
6929 error->cursor[i].position = I915_READ(CURPOS(i));
6930 error->cursor[i].base = I915_READ(CURBASE(i));
6931
6932 error->plane[i].control = I915_READ(DSPCNTR(i));
6933 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6934 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 6935 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 6936 error->plane[i].addr = I915_READ(DSPADDR(i));
6937 if (INTEL_INFO(dev)->gen >= 4) {
6938 error->plane[i].surface = I915_READ(DSPSURF(i));
6939 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6940 }
6941
6942 error->pipe[i].conf = I915_READ(PIPECONF(i));
6943 error->pipe[i].source = I915_READ(PIPESRC(i));
6944 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6945 error->pipe[i].hblank = I915_READ(HBLANK(i));
6946 error->pipe[i].hsync = I915_READ(HSYNC(i));
6947 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6948 error->pipe[i].vblank = I915_READ(VBLANK(i));
6949 error->pipe[i].vsync = I915_READ(VSYNC(i));
6950 }
6951
6952 return error;
6953}
6954
6955void
6956intel_display_print_error_state(struct seq_file *m,
6957 struct drm_device *dev,
6958 struct intel_display_error_state *error)
6959{
6960 int i;
6961
6962 for (i = 0; i < 2; i++) {
6963 seq_printf(m, "Pipe [%d]:\n", i);
6964 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6965 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6966 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6967 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6968 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6969 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6970 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6971 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6972
6973 seq_printf(m, "Plane [%d]:\n", i);
6974 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6975 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6976 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6977 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6978 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6979 if (INTEL_INFO(dev)->gen >= 4) {
6980 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6981 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6982 }
6983
6984 seq_printf(m, "Cursor [%d]:\n", i);
6985 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6986 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6987 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6988 }
6989}
6990#endif
Linux kernel - Deliverables
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