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drm/i915: rip out encoder->disable/enable checks
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
ab7ad7f6
KP		 1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
e9a851ed 1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
e9a851ed 1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
e9a851ed 1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
7434a255
TR		 1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1434 */
a37b9b34 1435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
a0c4da24 1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
a416edef
ED		 1491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
39fb50f6 1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
39fb50f6 1526 u32 value = 0;
a416edef
ED		 1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
39fb50f6 1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
92f2584a
JB		 1554/**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
ee7b9f93 1562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1563{
ee7b9f93 1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1565 struct intel_pch_pll *pll;
92f2584a
JB		 1566 int reg;
1567 u32 val;
1568
48da64a8 1569 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1570 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
ee7b9f93
JB		 1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
92f2584a
JB		 1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
ee7b9f93 1585 if (pll->active++ && pll->on) {
92b27b08 1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
92f2584a
JB		 1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
ee7b9f93
JB		 1598
1599 pll->on = true;
92f2584a
JB		 1600}
1601
ee7b9f93 1602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1603{
ee7b9f93
JB		 1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1606 int reg;
ee7b9f93 1607 u32 val;
4c609cb8 1608
92f2584a
JB		 1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1611 if (pll == NULL)
1612 return;
92f2584a 1613
48da64a8
CW		 1614 if (WARN_ON(pll->refcount == 0))
1615 return;
7a419866 1616
ee7b9f93
JB		 1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
7a419866 1620
48da64a8 1621 if (WARN_ON(pll->active == 0)) {
92b27b08 1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1623 return;
1624 }
1625
ee7b9f93 1626 if (--pll->active) {
92b27b08 1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1628 return;
ee7b9f93
JB		 1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1635
ee7b9f93 1636 reg = pll->pll_reg;
92f2584a
JB		 1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
ee7b9f93
JB		 1642
1643 pll->on = false;
92f2584a
JB		 1644}
1645
040484af
JB		 1646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
5f7f726d 1650 u32 val, pipeconf_val;
7c26e5c6 1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
040484af
JB		 1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
59c859d6
ED		 1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
040484af
JB		 1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
5f7f726d 1671 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
5f7f726d 1679 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1680 }
5f7f726d
PZ		 1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
040484af
JB		 1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
291906f1
JB		 1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
040484af
JB		 1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1717}
1718
b24e7179 1719/**
309cfea8 1720 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
040484af 1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
040484af
JB		 1733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
b24e7179
JB		 1735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
b24e7179
JB		 1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
00d70b15
CW		 1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
309cfea8 1765 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
00d70b15
CW		 1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
d74362c9
KP		 1801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
6f1d69b0 1805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
b24e7179
JB		 1812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
00d70b15
CW		 1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1835 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
b24e7179
JB		 1839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
47a05eca 1863static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1864 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1865{
1866 u32 val = I915_READ(reg);
4e634389 1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1869 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1870 }
47a05eca
JB		 1871}
1872
1873static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875{
1876 u32 val = I915_READ(reg);
e9a851ed 1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
f0575e92
KP		 1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
47a05eca 1880 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1881 }
47a05eca
JB		 1882}
1883
1884/* Disable any ports connected to this transcoder */
1885static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887{
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
f0575e92
KP		 1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
e9a851ed 1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
47a05eca
JB		 1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
e9a851ed 1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1519b995 1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914}
1915
127bd2ac 1916int
48b956c5 1917intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1918 struct drm_i915_gem_object *obj,
919926ae 1919 struct intel_ring_buffer *pipelined)
6b95a207 1920{
ce453d81 1921 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1922 u32 alignment;
1923 int ret;
1924
05394f39 1925 switch (obj->tiling_mode) {
6b95a207 1926 case I915_TILING_NONE:
534843da
CW		 1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
a6c45cf0 1929 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
6b95a207
KH		 1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
ce453d81 1946 dev_priv->mm.interruptible = false;
2da3b9b9 1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1948 if (ret)
ce453d81 1949 goto err_interruptible;
6b95a207
KH		 1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
06d98131 1956 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1957 if (ret)
1958 goto err_unpin;
1690e1eb 1959
9a5a53b3 1960 i915_gem_object_pin_fence(obj);
6b95a207 1961
ce453d81 1962 dev_priv->mm.interruptible = true;
6b95a207 1963 return 0;
48b956c5
CW		 1964
1965err_unpin:
1966 i915_gem_object_unpin(obj);
ce453d81
CW		 1967err_interruptible:
1968 dev_priv->mm.interruptible = true;
48b956c5 1969 return ret;
6b95a207
KH		 1970}
1971
1690e1eb
CW		 1972void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973{
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976}
1977
c2c75131
DV		 1978/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983{
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992}
1993
17638cd6
JB		 1994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
81255565
JB		 1996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
05394f39 2001 struct drm_i915_gem_object *obj;
81255565 2002 int plane = intel_crtc->plane;
e506a0c6 2003 unsigned long linear_offset;
81255565 2004 u32 dspcntr;
5eddb70b 2005 u32 reg;
81255565
JB		 2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
81255565 2018
5eddb70b
CW		 2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
81255565
JB		 2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
17638cd6 2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2039 return -EINVAL;
2040 }
a6c45cf0 2041 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2042 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
5eddb70b 2048 I915_WRITE(reg, dspcntr);
81255565 2049
e506a0c6 2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2051
c2c75131
DV		 2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
e506a0c6 2059 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2060 }
e506a0c6
DV		 2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2065 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2070 } else
e506a0c6 2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2072 POSTING_READ(reg);
81255565 2073
17638cd6
JB		 2074 return 0;
2075}
2076
2077static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
e506a0c6 2086 unsigned long linear_offset;
17638cd6
JB		 2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
27f8227b 2093 case 2:
17638cd6
JB		 2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
e506a0c6 2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2147
e506a0c6
DV		 2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2155 POSTING_READ(reg);
2156
2157 return 0;
2158}
2159
2160/* Assume fb object is pinned & idle & fenced and just update base pointers */
2161static int
2162intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164{
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2167
6b8e6ed0
CW		 2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
3dec0095 2170 intel_increase_pllclock(crtc);
81255565 2171
6b8e6ed0 2172 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2173}
2174
14667a4b
CW		 2175static int
2176intel_finish_fb(struct drm_framebuffer *old_fb)
2177{
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200}
2201
5c3b82e2 2202static int
3c4fdcfb
KH		 2203intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
79e53945
JB		 2205{
2206 struct drm_device *dev = crtc->dev;
6b8e6ed0 2207 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2210 int ret;
79e53945
JB		 2211
2212 /* no fb bound */
2213 if (!crtc->fb) {
a5071c2f 2214 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2215 return 0;
2216 }
2217
5826eca5
ED		 2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
5c3b82e2 2222 return -EINVAL;
79e53945
JB		 2223 }
2224
5c3b82e2 2225 mutex_lock(&dev->struct_mutex);
265db958
CW		 2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2228 NULL);
5c3b82e2
CW		 2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
a5071c2f 2231 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2232 return ret;
2233 }
79e53945 2234
14667a4b
CW		 2235 if (old_fb)
2236 intel_finish_fb(old_fb);
265db958 2237
6b8e6ed0 2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2239 if (ret) {
1690e1eb 2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2241 mutex_unlock(&dev->struct_mutex);
a5071c2f 2242 DRM_ERROR("failed to update base address\n");
4e6cfefc 2243 return ret;
79e53945 2244 }
3c4fdcfb 2245
b7f1de28
CW		 2246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2249 }
652c393a 2250
6b8e6ed0 2251 intel_update_fbc(dev);
5c3b82e2 2252 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2253
2254 if (!dev->primary->master)
5c3b82e2 2255 return 0;
79e53945
JB		 2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
5c3b82e2 2259 return 0;
79e53945 2260
265db958 2261 if (intel_crtc->pipe) {
79e53945
JB		 2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
79e53945 2267 }
5c3b82e2
CW		 2268
2269 return 0;
79e53945
JB		 2270}
2271
5eddb70b 2272static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2273{
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
28c97730 2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
5eddb70b 2305 POSTING_READ(DP_A);
32f9d658
ZW		 2306 udelay(500);
2307}
2308
5e84e1a4
ZW		 2309static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310{
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
61e499bf 2320 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2326 }
5e84e1a4
ZW		 2327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
357555c0
JB		 2343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2348}
2349
291427f5
JB		 2350static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360}
2361
8db9d77b
ZW		 2362/* The FDI link training functions for ILK/Ibexpeak. */
2363static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364{
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
0fc932b8 2369 int plane = intel_crtc->plane;
5eddb70b 2370 u32 reg, temp, tries;
8db9d77b 2371
0fc932b8
JB		 2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
e1a44743
AJ		 2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
5eddb70b
CW		 2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
e1a44743
AJ		 2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
e1a44743
AJ		 2384 udelay(150);
2385
8db9d77b 2386 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
77ffb597
AJ		 2389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2394
5eddb70b
CW		 2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
8db9d77b
ZW		 2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
8db9d77b
ZW		 2402 udelay(150);
2403
5b2adf89 2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
5b2adf89 2410
5eddb70b 2411 reg = FDI_RX_IIR(pipe);
e1a44743 2412 for (tries = 0; tries < 5; tries++) {
5eddb70b 2413 temp = I915_READ(reg);
8db9d77b
ZW		 2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2419 break;
2420 }
8db9d77b 2421 }
e1a44743 2422 if (tries == 5)
5eddb70b 2423 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2424
2425 /* Train 2 */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2430 I915_WRITE(reg, temp);
8db9d77b 2431
5eddb70b
CW		 2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
8db9d77b
ZW		 2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2436 I915_WRITE(reg, temp);
8db9d77b 2437
5eddb70b
CW		 2438 POSTING_READ(reg);
2439 udelay(150);
8db9d77b 2440
5eddb70b 2441 reg = FDI_RX_IIR(pipe);
e1a44743 2442 for (tries = 0; tries < 5; tries++) {
5eddb70b 2443 temp = I915_READ(reg);
8db9d77b
ZW		 2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
8db9d77b 2451 }
e1a44743 2452 if (tries == 5)
5eddb70b 2453 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2454
2455 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2456
8db9d77b
ZW		 2457}
2458
0206e353 2459static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464};
2465
2466/* The FDI link training functions for SNB/Cougarpoint. */
2467static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468{
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
fa37d39e 2473 u32 reg, temp, i, retry;
8db9d77b 2474
e1a44743
AJ		 2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
5eddb70b
CW		 2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
e1a44743
AJ		 2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
e1a44743
AJ		 2484 udelay(150);
2485
8db9d77b 2486 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
77ffb597
AJ		 2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2497
5eddb70b
CW		 2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
5eddb70b
CW		 2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
8db9d77b
ZW		 2510 udelay(150);
2511
291427f5
JB		 2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
0206e353 2515 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
8db9d77b
ZW		 2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
8db9d77b
ZW		 2523 udelay(500);
2524
fa37d39e
SP		 2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
8db9d77b 2535 }
fa37d39e
SP		 2536 if (retry < 5)
2537 break;
8db9d77b
ZW		 2538 }
2539 if (i == 4)
5eddb70b 2540 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2541
2542 /* Train 2 */
5eddb70b
CW		 2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
8db9d77b
ZW		 2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
5eddb70b 2552 I915_WRITE(reg, temp);
8db9d77b 2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596}
2597
357555c0
JB		 2598/* Manual link training for Ivy Bridge A0 parts */
2599static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2627 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2635 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
291427f5
JB		 2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
0206e353 2644 for (i = 0; i < 4; i++) {
357555c0
JB		 2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710}
2711
88cefb6c 2712static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2713{
88cefb6c 2714 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2715 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2716 int pipe = intel_crtc->pipe;
5eddb70b 2717 u32 reg, temp;
79e53945 2718
c64e311e 2719 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2722
c98e9dcf 2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
c98e9dcf
JB		 2732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
c98e9dcf
JB		 2739 udelay(200);
2740
bf507ef7
ED		 2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2749
bf507ef7
ED		 2750 POSTING_READ(reg);
2751 udelay(100);
2752 }
6be4a607 2753 }
0e23b99d
JB		 2754}
2755
88cefb6c
DV		 2756static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757{
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(100);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780 /* Wait for the clocks to turn off. */
2781 POSTING_READ(reg);
2782 udelay(100);
2783}
2784
291427f5
JB		 2785static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786{
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2795}
0fc932b8
JB		 2796static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797{
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2802 u32 reg, temp;
2803
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808 POSTING_READ(reg);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816 POSTING_READ(reg);
2817 udelay(100);
2818
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2827 }
0fc932b8
JB		 2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852}
2853
e6c3a2a6
CW		 2854static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855{
0f91128d 2856 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2857
2858 if (crtc->fb == NULL)
2859 return;
2860
0f91128d
CW		 2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2864}
2865
040484af
JB		 2866static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867{
2868 struct drm_device *dev = crtc->dev;
228d3e36 2869 struct intel_encoder *intel_encoder;
040484af
JB		 2870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
228d3e36 2875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2876
6ee8bab0
ED		 2877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2882
228d3e36 2883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885 return true;
2886 } else {
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2888 intel_encoder->type);
6ee8bab0
ED		 2889 return false;
2890 }
2891 }
2892
228d3e36 2893 switch (intel_encoder->type) {
040484af 2894 case INTEL_OUTPUT_EDP:
228d3e36 2895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902}
2903
e615efe4
ED		 2904/* Program iCLKIP clock to the desired frequency */
2905static void lpt_program_iclkip(struct drm_crtc *crtc)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2921
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2924 auxdiv = 1;
2925 divsel = 0x41;
2926 phaseinc = 0x20;
2927 } else {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2932 * precision.
2933 */
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2941
2942 auxdiv = 0;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2945 }
2946
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954 crtc->mode.clock,
2955 auxdiv,
2956 divsel,
2957 phasedir,
2958 phaseinc);
2959
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2971 temp);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2978 SBI_SSCAUXDIV6,
2979 temp);
2980
2981
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2986 SBI_SSCCTL6,
2987 temp);
2988
2989 /* Wait for initialization time */
2990 udelay(24);
2991
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993}
2994
f67a559d
JB		 2995/*
2996 * Enable PCH resources required for PCH ports:
2997 * - PCH PLLs
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3001 * - transcoder
3002 */
3003static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3004{
3005 struct drm_device *dev = crtc->dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
ee7b9f93 3009 u32 reg, temp;
2c07245f 3010
e7e164db
CW		 3011 assert_transcoder_disabled(dev_priv, pipe);
3012
c98e9dcf 3013 /* For PCH output, training FDI link */
674cf967 3014 dev_priv->display.fdi_link_train(crtc);
2c07245f 3015
6f13b7b5
CW		 3016 intel_enable_pch_pll(intel_crtc);
3017
e615efe4
ED		 3018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3022 u32 sel;
4b645f14 3023
c98e9dcf 3024 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3025 switch (pipe) {
3026 default:
3027 case 0:
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3030 break;
3031 case 1:
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3034 break;
3035 case 2:
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3038 break;
d64311ab 3039 }
ee7b9f93
JB		 3040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041 temp |= sel;
3042 else
3043 temp &= ~sel;
c98e9dcf 3044 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3045 }
5eddb70b 3046
d9b6cb56
JB		 3047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3052
5eddb70b
CW		 3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3057
f57e1e3a
ED		 3058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
5e84e1a4 3060
c98e9dcf
JB		 3061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3069 TRANS_DP_SYNC_MASK |
3070 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
9325c9f0 3073 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3074
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3079
3080 switch (intel_trans_dp_port_sel(crtc)) {
3081 case PCH_DP_B:
5eddb70b 3082 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3083 break;
3084 case PCH_DP_C:
5eddb70b 3085 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3086 break;
3087 case PCH_DP_D:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3089 break;
3090 default:
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3092 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3093 break;
32f9d658 3094 }
2c07245f 3095
5eddb70b 3096 I915_WRITE(reg, temp);
6be4a607 3097 }
b52eb4dc 3098
040484af 3099 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3100}
3101
ee7b9f93
JB		 3102static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103{
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116}
3117
3118static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119{
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
98b6bd99
DV		 3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
ee7b9f93
JB		 3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3177
e04c7350
CW		 3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
e04c7350
CW		 3182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3185 pll->on = false;
3186 return pll;
3187}
3188
d4270e57
JB		 3189void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200 udelay(250);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204 }
3205}
3206
f67a559d
JB		 3207static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3212 struct intel_encoder *encoder;
f67a559d
JB		 3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
3216 bool is_pch_port;
3217
ef9c3aee
DV		 3218 /* XXX: For compatability with the crtc helper code, call the encoder's
3219 * enable function unconditionally for now. */
f67a559d 3220 if (intel_crtc->active)
ef9c3aee 3221 goto encoders;
f67a559d
JB		 3222
3223 intel_crtc->active = true;
3224 intel_update_watermarks(dev);
3225
3226 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3227 temp = I915_READ(PCH_LVDS);
3228 if ((temp & LVDS_PORT_EN) == 0)
3229 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3230 }
3231
3232 is_pch_port = intel_crtc_driving_pch(crtc);
3233
3234 if (is_pch_port)
88cefb6c 3235 ironlake_fdi_pll_enable(intel_crtc);
f67a559d
JB		 3236 else
3237 ironlake_fdi_disable(crtc);
3238
3239 /* Enable panel fitting for LVDS */
3240 if (dev_priv->pch_pf_size &&
3241 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3242 /* Force use of hard-coded filter coefficients
3243 * as some pre-programmed values are broken,
3244 * e.g. x201.
3245 */
9db4a9c7
JB		 3246 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3247 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3248 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3249 }
3250
9c54c0dd
JB		 3251 /*
3252 * On ILK+ LUT must be loaded before the pipe is running but with
3253 * clocks enabled
3254 */
3255 intel_crtc_load_lut(crtc);
3256
f67a559d
JB		 3257 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3258 intel_enable_plane(dev_priv, plane, pipe);
3259
3260 if (is_pch_port)
3261 ironlake_pch_enable(crtc);
c98e9dcf 3262
d1ebd816 3263 mutex_lock(&dev->struct_mutex);
bed4a673 3264 intel_update_fbc(dev);
d1ebd816
BW		 3265 mutex_unlock(&dev->struct_mutex);
3266
6b383a7f 3267 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3268
3269encoders:
fa5c73b1
DV		 3270 for_each_encoder_on_crtc(dev, crtc, encoder)
3271 encoder->enable(encoder);
6be4a607
JB		 3272}
3273
3274static void ironlake_crtc_disable(struct drm_crtc *crtc)
3275{
3276 struct drm_device *dev = crtc->dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3279 struct intel_encoder *encoder;
6be4a607
JB		 3280 int pipe = intel_crtc->pipe;
3281 int plane = intel_crtc->plane;
5eddb70b 3282 u32 reg, temp;
b52eb4dc 3283
ef9c3aee
DV		 3284 /* XXX: For compatability with the crtc helper code, call the encoder's
3285 * disable function unconditionally for now. */
fa5c73b1
DV		 3286 for_each_encoder_on_crtc(dev, crtc, encoder)
3287 encoder->disable(encoder);
ef9c3aee 3288
f7abfe8b
CW		 3289 if (!intel_crtc->active)
3290 return;
3291
e6c3a2a6 3292 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3293 drm_vblank_off(dev, pipe);
6b383a7f 3294 intel_crtc_update_cursor(crtc, false);
5eddb70b 3295
b24e7179 3296 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3297
973d04f9
CW		 3298 if (dev_priv->cfb_plane == plane)
3299 intel_disable_fbc(dev);
2c07245f 3300
b24e7179 3301 intel_disable_pipe(dev_priv, pipe);
32f9d658 3302
6be4a607 3303 /* Disable PF */
9db4a9c7
JB		 3304 I915_WRITE(PF_CTL(pipe), 0);
3305 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3306
0fc932b8 3307 ironlake_fdi_disable(crtc);
2c07245f 3308
47a05eca
JB		 3309 /* This is a horrible layering violation; we should be doing this in
3310 * the connector/encoder ->prepare instead, but we don't always have
3311 * enough information there about the config to know whether it will
3312 * actually be necessary or just cause undesired flicker.
3313 */
3314 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3315
040484af 3316 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3317
6be4a607
JB		 3318 if (HAS_PCH_CPT(dev)) {
3319 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3320 reg = TRANS_DP_CTL(pipe);
3321 temp = I915_READ(reg);
3322 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3323 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3324 I915_WRITE(reg, temp);
6be4a607
JB		 3325
3326 /* disable DPLL_SEL */
3327 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3328 switch (pipe) {
3329 case 0:
d64311ab 3330 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3331 break;
3332 case 1:
6be4a607 3333 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3334 break;
3335 case 2:
4b645f14 3336 /* C shares PLL A or B */
d64311ab 3337 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3338 break;
3339 default:
3340 BUG(); /* wtf */
3341 }
6be4a607 3342 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3343 }
e3421a18 3344
6be4a607 3345 /* disable PCH DPLL */
ee7b9f93 3346 intel_disable_pch_pll(intel_crtc);
8db9d77b 3347
88cefb6c 3348 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3349
f7abfe8b 3350 intel_crtc->active = false;
6b383a7f 3351 intel_update_watermarks(dev);
d1ebd816
BW		 3352
3353 mutex_lock(&dev->struct_mutex);
6b383a7f 3354 intel_update_fbc(dev);
d1ebd816 3355 mutex_unlock(&dev->struct_mutex);
6be4a607 3356}
1b3c7a47 3357
ee7b9f93
JB		 3358static void ironlake_crtc_off(struct drm_crtc *crtc)
3359{
3360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3361 intel_put_pch_pll(intel_crtc);
3362}
3363
02e792fb
DV		 3364static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3365{
02e792fb 3366 if (!enable && intel_crtc->overlay) {
23f09ce3 3367 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3368 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3369
23f09ce3 3370 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3371 dev_priv->mm.interruptible = false;
3372 (void) intel_overlay_switch_off(intel_crtc->overlay);
3373 dev_priv->mm.interruptible = true;
23f09ce3 3374 mutex_unlock(&dev->struct_mutex);
02e792fb 3375 }
02e792fb 3376
5dcdbcb0
CW		 3377 /* Let userspace switch the overlay on again. In most cases userspace
3378 * has to recompute where to put it anyway.
3379 */
02e792fb
DV		 3380}
3381
0b8765c6 3382static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3383{
3384 struct drm_device *dev = crtc->dev;
79e53945
JB		 3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3387 struct intel_encoder *encoder;
79e53945 3388 int pipe = intel_crtc->pipe;
80824003 3389 int plane = intel_crtc->plane;
79e53945 3390
ef9c3aee
DV		 3391 /* XXX: For compatability with the crtc helper code, call the encoder's
3392 * enable function unconditionally for now. */
f7abfe8b 3393 if (intel_crtc->active)
ef9c3aee 3394 goto encoders;
f7abfe8b
CW		 3395
3396 intel_crtc->active = true;
6b383a7f
CW		 3397 intel_update_watermarks(dev);
3398
63d7bbe9 3399 intel_enable_pll(dev_priv, pipe);
040484af 3400 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3401 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3402
0b8765c6 3403 intel_crtc_load_lut(crtc);
bed4a673 3404 intel_update_fbc(dev);
79e53945 3405
0b8765c6
JB		 3406 /* Give the overlay scaler a chance to enable if it's on this pipe */
3407 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3408 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3409
3410encoders:
fa5c73b1
DV		 3411 for_each_encoder_on_crtc(dev, crtc, encoder)
3412 encoder->enable(encoder);
0b8765c6 3413}
79e53945 3414
0b8765c6
JB		 3415static void i9xx_crtc_disable(struct drm_crtc *crtc)
3416{
3417 struct drm_device *dev = crtc->dev;
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3420 struct intel_encoder *encoder;
0b8765c6
JB		 3421 int pipe = intel_crtc->pipe;
3422 int plane = intel_crtc->plane;
b690e96c 3423
ef9c3aee
DV		 3424 /* XXX: For compatability with the crtc helper code, call the encoder's
3425 * disable function unconditionally for now. */
fa5c73b1
DV		 3426 for_each_encoder_on_crtc(dev, crtc, encoder)
3427 encoder->disable(encoder);
ef9c3aee 3428
f7abfe8b
CW		 3429 if (!intel_crtc->active)
3430 return;
3431
0b8765c6 3432 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3433 intel_crtc_wait_for_pending_flips(crtc);
3434 drm_vblank_off(dev, pipe);
0b8765c6 3435 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3436 intel_crtc_update_cursor(crtc, false);
0b8765c6 3437
973d04f9
CW		 3438 if (dev_priv->cfb_plane == plane)
3439 intel_disable_fbc(dev);
79e53945 3440
b24e7179 3441 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3442 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3443 intel_disable_pll(dev_priv, pipe);
0b8765c6 3444
f7abfe8b 3445 intel_crtc->active = false;
6b383a7f
CW		 3446 intel_update_fbc(dev);
3447 intel_update_watermarks(dev);
0b8765c6
JB		 3448}
3449
ee7b9f93
JB		 3450static void i9xx_crtc_off(struct drm_crtc *crtc)
3451{
3452}
3453
2c07245f
ZW		 3454/**
3455 * Sets the power management mode of the pipe and plane.
2c07245f 3456 */
b2cabb0e 3457void intel_crtc_update_dpms(struct drm_crtc *crtc)
2c07245f
ZW		 3458{
3459 struct drm_device *dev = crtc->dev;
e70236a8 3460 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3461 struct drm_i915_master_private *master_priv;
3462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b2cabb0e 3463 struct intel_encoder *intel_encoder;
2c07245f 3464 int pipe = intel_crtc->pipe;
b2cabb0e
DV		 3465 bool enabled, enable = false;
3466 int mode;
3467
3468 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3469 enable |= intel_encoder->connectors_active;
3470
3471 mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
2c07245f 3472
032d2a0d
CW		 3473 if (intel_crtc->dpms_mode == mode)
3474 return;
3475
65655d4a 3476 intel_crtc->dpms_mode = mode;
debcaddc 3477
b2cabb0e 3478 if (enable)
76e5a89c 3479 dev_priv->display.crtc_enable(crtc);
b2cabb0e 3480 else
76e5a89c 3481 dev_priv->display.crtc_disable(crtc);
79e53945
JB		 3482
3483 if (!dev->primary->master)
3484 return;
3485
3486 master_priv = dev->primary->master->driver_priv;
3487 if (!master_priv->sarea_priv)
3488 return;
3489
b2cabb0e 3490 enabled = crtc->enabled && enable;
79e53945
JB		 3491
3492 switch (pipe) {
3493 case 0:
3494 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3495 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3496 break;
3497 case 1:
3498 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3499 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3500 break;
3501 default:
9db4a9c7 3502 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3503 break;
3504 }
79e53945
JB		 3505}
3506
cdd59983
CW		 3507static void intel_crtc_disable(struct drm_crtc *crtc)
3508{
cdd59983 3509 struct drm_device *dev = crtc->dev;
ee7b9f93 3510 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3511
b2cabb0e
DV		 3512 /* crtc->disable is only called when we have no encoders, hence this
3513 * will disable the pipe. */
3514 intel_crtc_update_dpms(crtc);
ee7b9f93
JB		 3515 dev_priv->display.off(crtc);
3516
931872fc
CW		 3517 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3518 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3519
3520 if (crtc->fb) {
3521 mutex_lock(&dev->struct_mutex);
1690e1eb 3522 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3523 mutex_unlock(&dev->struct_mutex);
3524 }
3525}
3526
0206e353 3527void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3528{
3529 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3530 /* lvds has its own version of prepare see intel_lvds_prepare */
3531 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3532}
3533
0206e353 3534void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3535{
3536 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3537 struct drm_device *dev = encoder->dev;
d47d7cb8 3538 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3539
79e53945
JB		 3540 /* lvds has its own version of commit see intel_lvds_commit */
3541 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3542
3543 if (HAS_PCH_CPT(dev))
3544 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3545}
3546
5ab432ef
DV		 3547void intel_encoder_noop(struct drm_encoder *encoder)
3548{
3549}
3550
3551void intel_encoder_disable(struct drm_encoder *encoder)
3552{
3553 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3554
3555 intel_encoder->disable(intel_encoder);
3556}
3557
ea5b213a
CW		 3558void intel_encoder_destroy(struct drm_encoder *encoder)
3559{
4ef69c7a 3560 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3561
ea5b213a
CW		 3562 drm_encoder_cleanup(encoder);
3563 kfree(intel_encoder);
3564}
3565
5ab432ef
DV		 3566/* Simple dpms helper for encodres with just one connector, no cloning and only
3567 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3568 * state of the entire output pipe. */
3569void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3570{
3571 if (mode == DRM_MODE_DPMS_ON) {
3572 encoder->connectors_active = true;
3573
b2cabb0e 3574 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3575 } else {
3576 encoder->connectors_active = false;
3577
b2cabb0e 3578 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3579 }
3580}
3581
3582/* Even simpler default implementation, if there's really no special case to
3583 * consider. */
3584void intel_connector_dpms(struct drm_connector *connector, int mode)
3585{
3586 struct intel_encoder *encoder = intel_attached_encoder(connector);
3587
3588 /* All the simple cases only support two dpms states. */
3589 if (mode != DRM_MODE_DPMS_ON)
3590 mode = DRM_MODE_DPMS_OFF;
3591
3592 if (mode == connector->dpms)
3593 return;
3594
3595 connector->dpms = mode;
3596
3597 /* Only need to change hw state when actually enabled */
3598 if (encoder->base.crtc)
3599 intel_encoder_dpms(encoder, mode);
3600 else
3601 encoder->connectors_active = false;
3602}
3603
79e53945 3604static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3605 const struct drm_display_mode *mode,
79e53945
JB		 3606 struct drm_display_mode *adjusted_mode)
3607{
2c07245f 3608 struct drm_device *dev = crtc->dev;
89749350 3609
bad720ff 3610 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3611 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3612 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3613 return false;
2c07245f 3614 }
89749350 3615
f9bef081
DV		 3616 /* All interlaced capable intel hw wants timings in frames. Note though
3617 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3618 * timings, so we need to be careful not to clobber these.*/
3619 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3620 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3621
79e53945
JB		 3622 return true;
3623}
3624
25eb05fc
JB		 3625static int valleyview_get_display_clock_speed(struct drm_device *dev)
3626{
3627 return 400000; /* FIXME */
3628}
3629
e70236a8
JB		 3630static int i945_get_display_clock_speed(struct drm_device *dev)
3631{
3632 return 400000;
3633}
79e53945 3634
e70236a8 3635static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3636{
e70236a8
JB		 3637 return 333000;
3638}
79e53945 3639
e70236a8
JB		 3640static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3641{
3642 return 200000;
3643}
79e53945 3644
e70236a8
JB		 3645static int i915gm_get_display_clock_speed(struct drm_device *dev)
3646{
3647 u16 gcfgc = 0;
79e53945 3648
e70236a8
JB		 3649 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3650
3651 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3652 return 133000;
3653 else {
3654 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3655 case GC_DISPLAY_CLOCK_333_MHZ:
3656 return 333000;
3657 default:
3658 case GC_DISPLAY_CLOCK_190_200_MHZ:
3659 return 190000;
79e53945 3660 }
e70236a8
JB		 3661 }
3662}
3663
3664static int i865_get_display_clock_speed(struct drm_device *dev)
3665{
3666 return 266000;
3667}
3668
3669static int i855_get_display_clock_speed(struct drm_device *dev)
3670{
3671 u16 hpllcc = 0;
3672 /* Assume that the hardware is in the high speed state. This
3673 * should be the default.
3674 */
3675 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3676 case GC_CLOCK_133_200:
3677 case GC_CLOCK_100_200:
3678 return 200000;
3679 case GC_CLOCK_166_250:
3680 return 250000;
3681 case GC_CLOCK_100_133:
79e53945 3682 return 133000;
e70236a8 3683 }
79e53945 3684
e70236a8
JB		 3685 /* Shouldn't happen */
3686 return 0;
3687}
79e53945 3688
e70236a8
JB		 3689static int i830_get_display_clock_speed(struct drm_device *dev)
3690{
3691 return 133000;
79e53945
JB		 3692}
3693
2c07245f
ZW		 3694struct fdi_m_n {
3695 u32 tu;
3696 u32 gmch_m;
3697 u32 gmch_n;
3698 u32 link_m;
3699 u32 link_n;
3700};
3701
3702static void
3703fdi_reduce_ratio(u32 *num, u32 *den)
3704{
3705 while (*num > 0xffffff || *den > 0xffffff) {
3706 *num >>= 1;
3707 *den >>= 1;
3708 }
3709}
3710
2c07245f 3711static void
f2b115e6
AJ		 3712ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3713 int link_clock, struct fdi_m_n *m_n)
2c07245f 3714{
2c07245f
ZW		 3715 m_n->tu = 64; /* default size */
3716
22ed1113
CW		 3717 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3718 m_n->gmch_m = bits_per_pixel * pixel_clock;
3719 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3720 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3721
22ed1113
CW		 3722 m_n->link_m = pixel_clock;
3723 m_n->link_n = link_clock;
2c07245f
ZW		 3724 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3725}
3726
a7615030
CW		 3727static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3728{
72bbe58c
KP		 3729 if (i915_panel_use_ssc >= 0)
3730 return i915_panel_use_ssc != 0;
3731 return dev_priv->lvds_use_ssc
435793df 3732 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3733}
3734
5a354204
JB		 3735/**
3736 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3737 * @crtc: CRTC structure
3b5c78a3 3738 * @mode: requested mode
5a354204
JB		 3739 *
3740 * A pipe may be connected to one or more outputs. Based on the depth of the
3741 * attached framebuffer, choose a good color depth to use on the pipe.
3742 *
3743 * If possible, match the pipe depth to the fb depth. In some cases, this
3744 * isn't ideal, because the connected output supports a lesser or restricted
3745 * set of depths. Resolve that here:
3746 * LVDS typically supports only 6bpc, so clamp down in that case
3747 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3748 * Displays may support a restricted set as well, check EDID and clamp as
3749 * appropriate.
3b5c78a3 3750 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3751 *
3752 * RETURNS:
3753 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3754 * true if they don't match).
3755 */
3756static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3757 unsigned int *pipe_bpp,
3758 struct drm_display_mode *mode)
5a354204
JB		 3759{
3760 struct drm_device *dev = crtc->dev;
3761 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3762 struct drm_connector *connector;
6c2b7c12 3763 struct intel_encoder *intel_encoder;
5a354204
JB		 3764 unsigned int display_bpc = UINT_MAX, bpc;
3765
3766 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3767 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3768
3769 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3770 unsigned int lvds_bpc;
3771
3772 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3773 LVDS_A3_POWER_UP)
3774 lvds_bpc = 8;
3775 else
3776 lvds_bpc = 6;
3777
3778 if (lvds_bpc < display_bpc) {
82820490 3779 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3780 display_bpc = lvds_bpc;
3781 }
3782 continue;
3783 }
3784
5a354204
JB		 3785 /* Not one of the known troublemakers, check the EDID */
3786 list_for_each_entry(connector, &dev->mode_config.connector_list,
3787 head) {
6c2b7c12 3788 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3789 continue;
3790
62ac41a6
JB		 3791 /* Don't use an invalid EDID bpc value */
3792 if (connector->display_info.bpc &&
3793 connector->display_info.bpc < display_bpc) {
82820490 3794 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3795 display_bpc = connector->display_info.bpc;
3796 }
3797 }
3798
3799 /*
3800 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3801 * through, clamp it down. (Note: >12bpc will be caught below.)
3802 */
3803 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3804 if (display_bpc > 8 && display_bpc < 12) {
82820490 3805 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3806 display_bpc = 12;
3807 } else {
82820490 3808 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3809 display_bpc = 8;
3810 }
3811 }
3812 }
3813
3b5c78a3
AJ		 3814 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3815 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3816 display_bpc = 6;
3817 }
3818
5a354204
JB		 3819 /*
3820 * We could just drive the pipe at the highest bpc all the time and
3821 * enable dithering as needed, but that costs bandwidth. So choose
3822 * the minimum value that expresses the full color range of the fb but
3823 * also stays within the max display bpc discovered above.
3824 */
3825
3826 switch (crtc->fb->depth) {
3827 case 8:
3828 bpc = 8; /* since we go through a colormap */
3829 break;
3830 case 15:
3831 case 16:
3832 bpc = 6; /* min is 18bpp */
3833 break;
3834 case 24:
578393cd 3835 bpc = 8;
5a354204
JB		 3836 break;
3837 case 30:
578393cd 3838 bpc = 10;
5a354204
JB		 3839 break;
3840 case 48:
578393cd 3841 bpc = 12;
5a354204
JB		 3842 break;
3843 default:
3844 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3845 bpc = min((unsigned int)8, display_bpc);
3846 break;
3847 }
3848
578393cd
KP		 3849 display_bpc = min(display_bpc, bpc);
3850
82820490
AJ		 3851 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3852 bpc, display_bpc);
5a354204 3853
578393cd 3854 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3855
3856 return display_bpc != bpc;
3857}
3858
a0c4da24
JB		 3859static int vlv_get_refclk(struct drm_crtc *crtc)
3860{
3861 struct drm_device *dev = crtc->dev;
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 int refclk = 27000; /* for DP & HDMI */
3864
3865 return 100000; /* only one validated so far */
3866
3867 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3868 refclk = 96000;
3869 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3870 if (intel_panel_use_ssc(dev_priv))
3871 refclk = 100000;
3872 else
3873 refclk = 96000;
3874 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3875 refclk = 100000;
3876 }
3877
3878 return refclk;
3879}
3880
c65d77d8
JB		 3881static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3882{
3883 struct drm_device *dev = crtc->dev;
3884 struct drm_i915_private *dev_priv = dev->dev_private;
3885 int refclk;
3886
a0c4da24
JB		 3887 if (IS_VALLEYVIEW(dev)) {
3888 refclk = vlv_get_refclk(crtc);
3889 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3890 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3891 refclk = dev_priv->lvds_ssc_freq * 1000;
3892 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3893 refclk / 1000);
3894 } else if (!IS_GEN2(dev)) {
3895 refclk = 96000;
3896 } else {
3897 refclk = 48000;
3898 }
3899
3900 return refclk;
3901}
3902
3903static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3904 intel_clock_t *clock)
3905{
3906 /* SDVO TV has fixed PLL values depend on its clock range,
3907 this mirrors vbios setting. */
3908 if (adjusted_mode->clock >= 100000
3909 && adjusted_mode->clock < 140500) {
3910 clock->p1 = 2;
3911 clock->p2 = 10;
3912 clock->n = 3;
3913 clock->m1 = 16;
3914 clock->m2 = 8;
3915 } else if (adjusted_mode->clock >= 140500
3916 && adjusted_mode->clock <= 200000) {
3917 clock->p1 = 1;
3918 clock->p2 = 10;
3919 clock->n = 6;
3920 clock->m1 = 12;
3921 clock->m2 = 8;
3922 }
3923}
3924
a7516a05
JB		 3925static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3926 intel_clock_t *clock,
3927 intel_clock_t *reduced_clock)
3928{
3929 struct drm_device *dev = crtc->dev;
3930 struct drm_i915_private *dev_priv = dev->dev_private;
3931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3932 int pipe = intel_crtc->pipe;
3933 u32 fp, fp2 = 0;
3934
3935 if (IS_PINEVIEW(dev)) {
3936 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3937 if (reduced_clock)
3938 fp2 = (1 << reduced_clock->n) << 16 |
3939 reduced_clock->m1 << 8 | reduced_clock->m2;
3940 } else {
3941 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3942 if (reduced_clock)
3943 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3944 reduced_clock->m2;
3945 }
3946
3947 I915_WRITE(FP0(pipe), fp);
3948
3949 intel_crtc->lowfreq_avail = false;
3950 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3951 reduced_clock && i915_powersave) {
3952 I915_WRITE(FP1(pipe), fp2);
3953 intel_crtc->lowfreq_avail = true;
3954 } else {
3955 I915_WRITE(FP1(pipe), fp);
3956 }
3957}
3958
93e537a1
DV		 3959static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3960 struct drm_display_mode *adjusted_mode)
3961{
3962 struct drm_device *dev = crtc->dev;
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3965 int pipe = intel_crtc->pipe;
284d5df5 3966 u32 temp;
93e537a1
DV		 3967
3968 temp = I915_READ(LVDS);
3969 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3970 if (pipe == 1) {
3971 temp |= LVDS_PIPEB_SELECT;
3972 } else {
3973 temp &= ~LVDS_PIPEB_SELECT;
3974 }
3975 /* set the corresponsding LVDS_BORDER bit */
3976 temp |= dev_priv->lvds_border_bits;
3977 /* Set the B0-B3 data pairs corresponding to whether we're going to
3978 * set the DPLLs for dual-channel mode or not.
3979 */
3980 if (clock->p2 == 7)
3981 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3982 else
3983 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3984
3985 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3986 * appropriately here, but we need to look more thoroughly into how
3987 * panels behave in the two modes.
3988 */
3989 /* set the dithering flag on LVDS as needed */
3990 if (INTEL_INFO(dev)->gen >= 4) {
3991 if (dev_priv->lvds_dither)
3992 temp |= LVDS_ENABLE_DITHER;
3993 else
3994 temp &= ~LVDS_ENABLE_DITHER;
3995 }
284d5df5 3996 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3997 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3998 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3999 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4000 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4001 I915_WRITE(LVDS, temp);
4002}
4003
a0c4da24
JB		 4004static void vlv_update_pll(struct drm_crtc *crtc,
4005 struct drm_display_mode *mode,
4006 struct drm_display_mode *adjusted_mode,
4007 intel_clock_t *clock, intel_clock_t *reduced_clock,
4008 int refclk, int num_connectors)
4009{
4010 struct drm_device *dev = crtc->dev;
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4013 int pipe = intel_crtc->pipe;
4014 u32 dpll, mdiv, pdiv;
4015 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4016 bool is_hdmi;
4017
4018 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4019
4020 bestn = clock->n;
4021 bestm1 = clock->m1;
4022 bestm2 = clock->m2;
4023 bestp1 = clock->p1;
4024 bestp2 = clock->p2;
4025
4026 /* Enable DPIO clock input */
4027 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4028 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4029 I915_WRITE(DPLL(pipe), dpll);
4030 POSTING_READ(DPLL(pipe));
4031
4032 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4033 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4034 mdiv |= ((bestn << DPIO_N_SHIFT));
4035 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4036 mdiv |= (1 << DPIO_K_SHIFT);
4037 mdiv |= DPIO_ENABLE_CALIBRATION;
4038 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4039
4040 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4041
4042 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4043 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4044 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4045 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4046
4047 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4048
4049 dpll |= DPLL_VCO_ENABLE;
4050 I915_WRITE(DPLL(pipe), dpll);
4051 POSTING_READ(DPLL(pipe));
4052 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4053 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4054
4055 if (is_hdmi) {
4056 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4057
4058 if (temp > 1)
4059 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4060 else
4061 temp = 0;
4062
4063 I915_WRITE(DPLL_MD(pipe), temp);
4064 POSTING_READ(DPLL_MD(pipe));
4065 }
4066
4067 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4068}
4069
eb1cbe48
DV		 4070static void i9xx_update_pll(struct drm_crtc *crtc,
4071 struct drm_display_mode *mode,
4072 struct drm_display_mode *adjusted_mode,
4073 intel_clock_t *clock, intel_clock_t *reduced_clock,
4074 int num_connectors)
4075{
4076 struct drm_device *dev = crtc->dev;
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4079 int pipe = intel_crtc->pipe;
4080 u32 dpll;
4081 bool is_sdvo;
4082
4083 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4084 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4085
4086 dpll = DPLL_VGA_MODE_DIS;
4087
4088 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4089 dpll |= DPLLB_MODE_LVDS;
4090 else
4091 dpll |= DPLLB_MODE_DAC_SERIAL;
4092 if (is_sdvo) {
4093 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4094 if (pixel_multiplier > 1) {
4095 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4096 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4097 }
4098 dpll |= DPLL_DVO_HIGH_SPEED;
4099 }
4100 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4101 dpll |= DPLL_DVO_HIGH_SPEED;
4102
4103 /* compute bitmask from p1 value */
4104 if (IS_PINEVIEW(dev))
4105 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4106 else {
4107 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4108 if (IS_G4X(dev) && reduced_clock)
4109 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4110 }
4111 switch (clock->p2) {
4112 case 5:
4113 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4114 break;
4115 case 7:
4116 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4117 break;
4118 case 10:
4119 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4120 break;
4121 case 14:
4122 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4123 break;
4124 }
4125 if (INTEL_INFO(dev)->gen >= 4)
4126 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4127
4128 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4129 dpll |= PLL_REF_INPUT_TVCLKINBC;
4130 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4131 /* XXX: just matching BIOS for now */
4132 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4133 dpll |= 3;
4134 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4135 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4136 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4137 else
4138 dpll |= PLL_REF_INPUT_DREFCLK;
4139
4140 dpll |= DPLL_VCO_ENABLE;
4141 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4142 POSTING_READ(DPLL(pipe));
4143 udelay(150);
4144
4145 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4146 * This is an exception to the general rule that mode_set doesn't turn
4147 * things on.
4148 */
4149 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4150 intel_update_lvds(crtc, clock, adjusted_mode);
4151
4152 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4153 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4154
4155 I915_WRITE(DPLL(pipe), dpll);
4156
4157 /* Wait for the clocks to stabilize. */
4158 POSTING_READ(DPLL(pipe));
4159 udelay(150);
4160
4161 if (INTEL_INFO(dev)->gen >= 4) {
4162 u32 temp = 0;
4163 if (is_sdvo) {
4164 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4165 if (temp > 1)
4166 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4167 else
4168 temp = 0;
4169 }
4170 I915_WRITE(DPLL_MD(pipe), temp);
4171 } else {
4172 /* The pixel multiplier can only be updated once the
4173 * DPLL is enabled and the clocks are stable.
4174 *
4175 * So write it again.
4176 */
4177 I915_WRITE(DPLL(pipe), dpll);
4178 }
4179}
4180
4181static void i8xx_update_pll(struct drm_crtc *crtc,
4182 struct drm_display_mode *adjusted_mode,
4183 intel_clock_t *clock,
4184 int num_connectors)
4185{
4186 struct drm_device *dev = crtc->dev;
4187 struct drm_i915_private *dev_priv = dev->dev_private;
4188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4189 int pipe = intel_crtc->pipe;
4190 u32 dpll;
4191
4192 dpll = DPLL_VGA_MODE_DIS;
4193
4194 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4195 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4196 } else {
4197 if (clock->p1 == 2)
4198 dpll |= PLL_P1_DIVIDE_BY_TWO;
4199 else
4200 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4201 if (clock->p2 == 4)
4202 dpll |= PLL_P2_DIVIDE_BY_4;
4203 }
4204
4205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4206 /* XXX: just matching BIOS for now */
4207 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4208 dpll |= 3;
4209 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4210 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4211 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4212 else
4213 dpll |= PLL_REF_INPUT_DREFCLK;
4214
4215 dpll |= DPLL_VCO_ENABLE;
4216 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4217 POSTING_READ(DPLL(pipe));
4218 udelay(150);
4219
4220 I915_WRITE(DPLL(pipe), dpll);
4221
4222 /* Wait for the clocks to stabilize. */
4223 POSTING_READ(DPLL(pipe));
4224 udelay(150);
4225
4226 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4227 * This is an exception to the general rule that mode_set doesn't turn
4228 * things on.
4229 */
4230 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4231 intel_update_lvds(crtc, clock, adjusted_mode);
4232
4233 /* The pixel multiplier can only be updated once the
4234 * DPLL is enabled and the clocks are stable.
4235 *
4236 * So write it again.
4237 */
4238 I915_WRITE(DPLL(pipe), dpll);
4239}
4240
f564048e
EA		 4241static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4242 struct drm_display_mode *mode,
4243 struct drm_display_mode *adjusted_mode,
4244 int x, int y,
4245 struct drm_framebuffer *old_fb)
79e53945
JB		 4246{
4247 struct drm_device *dev = crtc->dev;
4248 struct drm_i915_private *dev_priv = dev->dev_private;
4249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4250 int pipe = intel_crtc->pipe;
80824003 4251 int plane = intel_crtc->plane;
c751ce4f 4252 int refclk, num_connectors = 0;
652c393a 4253 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4254 u32 dspcntr, pipeconf, vsyncshift;
4255 bool ok, has_reduced_clock = false, is_sdvo = false;
4256 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4257 struct intel_encoder *encoder;
d4906093 4258 const intel_limit_t *limit;
5c3b82e2 4259 int ret;
79e53945 4260
6c2b7c12 4261 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4262 switch (encoder->type) {
79e53945
JB		 4263 case INTEL_OUTPUT_LVDS:
4264 is_lvds = true;
4265 break;
4266 case INTEL_OUTPUT_SDVO:
7d57382e 4267 case INTEL_OUTPUT_HDMI:
79e53945 4268 is_sdvo = true;
5eddb70b 4269 if (encoder->needs_tv_clock)
e2f0ba97 4270 is_tv = true;
79e53945 4271 break;
79e53945
JB		 4272 case INTEL_OUTPUT_TVOUT:
4273 is_tv = true;
4274 break;
a4fc5ed6
KP		 4275 case INTEL_OUTPUT_DISPLAYPORT:
4276 is_dp = true;
4277 break;
79e53945 4278 }
43565a06 4279
c751ce4f 4280 num_connectors++;
79e53945
JB		 4281 }
4282
c65d77d8 4283 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4284
d4906093
ML		 4285 /*
4286 * Returns a set of divisors for the desired target clock with the given
4287 * refclk, or FALSE. The returned values represent the clock equation:
4288 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4289 */
1b894b59 4290 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4291 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4292 &clock);
79e53945
JB		 4293 if (!ok) {
4294 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4295 return -EINVAL;
79e53945
JB		 4296 }
4297
cda4b7d3 4298 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4299 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4300
ddc9003c 4301 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4302 /*
4303 * Ensure we match the reduced clock's P to the target clock.
4304 * If the clocks don't match, we can't switch the display clock
4305 * by using the FP0/FP1. In such case we will disable the LVDS
4306 * downclock feature.
4307 */
ddc9003c 4308 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4309 dev_priv->lvds_downclock,
4310 refclk,
cec2f356 4311 &clock,
5eddb70b 4312 &reduced_clock);
7026d4ac
ZW		 4313 }
4314
c65d77d8
JB		 4315 if (is_sdvo && is_tv)
4316 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4317
a7516a05
JB		 4318 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4319 &reduced_clock : NULL);
79e53945 4320
eb1cbe48
DV		 4321 if (IS_GEN2(dev))
4322 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4323 else if (IS_VALLEYVIEW(dev))
4324 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4325 refclk, num_connectors);
79e53945 4326 else
eb1cbe48
DV		 4327 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4328 has_reduced_clock ? &reduced_clock : NULL,
4329 num_connectors);
79e53945
JB		 4330
4331 /* setup pipeconf */
5eddb70b 4332 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4333
4334 /* Set up the display plane register */
4335 dspcntr = DISPPLANE_GAMMA_ENABLE;
4336
929c77fb
EA		 4337 if (pipe == 0)
4338 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4339 else
4340 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4341
a6c45cf0 4342 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4343 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4344 * core speed.
4345 *
4346 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4347 * pipe == 0 check?
4348 */
e70236a8
JB		 4349 if (mode->clock >
4350 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4351 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4352 else
5eddb70b 4353 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4354 }
4355
3b5c78a3
AJ		 4356 /* default to 8bpc */
4357 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4358 if (is_dp) {
4359 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4360 pipeconf |= PIPECONF_BPP_6 |
4361 PIPECONF_DITHER_EN |
4362 PIPECONF_DITHER_TYPE_SP;
4363 }
4364 }
4365
28c97730 4366 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4367 drm_mode_debug_printmodeline(mode);
4368
a7516a05
JB		 4369 if (HAS_PIPE_CXSR(dev)) {
4370 if (intel_crtc->lowfreq_avail) {
28c97730 4371 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4372 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4373 } else {
28c97730 4374 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4375 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4376 }
4377 }
4378
617cf884 4379 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4380 if (!IS_GEN2(dev) &&
4381 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4382 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4383 /* the chip adds 2 halflines automatically */
734b4157 4384 adjusted_mode->crtc_vtotal -= 1;
734b4157 4385 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4386 vsyncshift = adjusted_mode->crtc_hsync_start
4387 - adjusted_mode->crtc_htotal/2;
4388 } else {
617cf884 4389 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4390 vsyncshift = 0;
4391 }
4392
4393 if (!IS_GEN3(dev))
4394 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4395
5eddb70b
CW		 4396 I915_WRITE(HTOTAL(pipe),
4397 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4398 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4399 I915_WRITE(HBLANK(pipe),
4400 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4401 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4402 I915_WRITE(HSYNC(pipe),
4403 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4404 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4405
4406 I915_WRITE(VTOTAL(pipe),
4407 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4408 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4409 I915_WRITE(VBLANK(pipe),
4410 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4411 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4412 I915_WRITE(VSYNC(pipe),
4413 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4414 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4415
4416 /* pipesrc and dspsize control the size that is scaled from,
4417 * which should always be the user's requested size.
79e53945 4418 */
929c77fb
EA		 4419 I915_WRITE(DSPSIZE(plane),
4420 ((mode->vdisplay - 1) << 16) |
4421 (mode->hdisplay - 1));
4422 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4423 I915_WRITE(PIPESRC(pipe),
4424 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4425
f564048e
EA		 4426 I915_WRITE(PIPECONF(pipe), pipeconf);
4427 POSTING_READ(PIPECONF(pipe));
929c77fb 4428 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4429
4430 intel_wait_for_vblank(dev, pipe);
4431
f564048e
EA		 4432 I915_WRITE(DSPCNTR(plane), dspcntr);
4433 POSTING_READ(DSPCNTR(plane));
4434
4435 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4436
4437 intel_update_watermarks(dev);
4438
f564048e
EA		 4439 return ret;
4440}
4441
9fb526db
KP		 4442/*
4443 * Initialize reference clocks when the driver loads
4444 */
4445void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4446{
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4449 struct intel_encoder *encoder;
13d83a67
JB		 4450 u32 temp;
4451 bool has_lvds = false;
199e5d79
KP		 4452 bool has_cpu_edp = false;
4453 bool has_pch_edp = false;
4454 bool has_panel = false;
99eb6a01
KP		 4455 bool has_ck505 = false;
4456 bool can_ssc = false;
13d83a67
JB		 4457
4458 /* We need to take the global config into account */
199e5d79
KP		 4459 list_for_each_entry(encoder, &mode_config->encoder_list,
4460 base.head) {
4461 switch (encoder->type) {
4462 case INTEL_OUTPUT_LVDS:
4463 has_panel = true;
4464 has_lvds = true;
4465 break;
4466 case INTEL_OUTPUT_EDP:
4467 has_panel = true;
4468 if (intel_encoder_is_pch_edp(&encoder->base))
4469 has_pch_edp = true;
4470 else
4471 has_cpu_edp = true;
4472 break;
13d83a67
JB		 4473 }
4474 }
4475
99eb6a01
KP		 4476 if (HAS_PCH_IBX(dev)) {
4477 has_ck505 = dev_priv->display_clock_mode;
4478 can_ssc = has_ck505;
4479 } else {
4480 has_ck505 = false;
4481 can_ssc = true;
4482 }
4483
4484 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4485 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4486 has_ck505);
13d83a67
JB		 4487
4488 /* Ironlake: try to setup display ref clock before DPLL
4489 * enabling. This is only under driver's control after
4490 * PCH B stepping, previous chipset stepping should be
4491 * ignoring this setting.
4492 */
4493 temp = I915_READ(PCH_DREF_CONTROL);
4494 /* Always enable nonspread source */
4495 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4496
99eb6a01
KP		 4497 if (has_ck505)
4498 temp |= DREF_NONSPREAD_CK505_ENABLE;
4499 else
4500 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4501
199e5d79
KP		 4502 if (has_panel) {
4503 temp &= ~DREF_SSC_SOURCE_MASK;
4504 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4505
199e5d79 4506 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4507 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4508 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4509 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4510 } else
4511 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4512
4513 /* Get SSC going before enabling the outputs */
4514 I915_WRITE(PCH_DREF_CONTROL, temp);
4515 POSTING_READ(PCH_DREF_CONTROL);
4516 udelay(200);
4517
13d83a67
JB		 4518 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4519
4520 /* Enable CPU source on CPU attached eDP */
199e5d79 4521 if (has_cpu_edp) {
99eb6a01 4522 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4523 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4524 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4525 }
13d83a67
JB		 4526 else
4527 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4528 } else
4529 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4530
4531 I915_WRITE(PCH_DREF_CONTROL, temp);
4532 POSTING_READ(PCH_DREF_CONTROL);
4533 udelay(200);
4534 } else {
4535 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4536
4537 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4538
4539 /* Turn off CPU output */
4540 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4541
4542 I915_WRITE(PCH_DREF_CONTROL, temp);
4543 POSTING_READ(PCH_DREF_CONTROL);
4544 udelay(200);
4545
4546 /* Turn off the SSC source */
4547 temp &= ~DREF_SSC_SOURCE_MASK;
4548 temp |= DREF_SSC_SOURCE_DISABLE;
4549
4550 /* Turn off SSC1 */
4551 temp &= ~ DREF_SSC1_ENABLE;
4552
13d83a67
JB		 4553 I915_WRITE(PCH_DREF_CONTROL, temp);
4554 POSTING_READ(PCH_DREF_CONTROL);
4555 udelay(200);
4556 }
4557}
4558
d9d444cb
JB		 4559static int ironlake_get_refclk(struct drm_crtc *crtc)
4560{
4561 struct drm_device *dev = crtc->dev;
4562 struct drm_i915_private *dev_priv = dev->dev_private;
4563 struct intel_encoder *encoder;
d9d444cb
JB		 4564 struct intel_encoder *edp_encoder = NULL;
4565 int num_connectors = 0;
4566 bool is_lvds = false;
4567
6c2b7c12 4568 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4569 switch (encoder->type) {
4570 case INTEL_OUTPUT_LVDS:
4571 is_lvds = true;
4572 break;
4573 case INTEL_OUTPUT_EDP:
4574 edp_encoder = encoder;
4575 break;
4576 }
4577 num_connectors++;
4578 }
4579
4580 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4581 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4582 dev_priv->lvds_ssc_freq);
4583 return dev_priv->lvds_ssc_freq * 1000;
4584 }
4585
4586 return 120000;
4587}
4588
f564048e
EA		 4589static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4590 struct drm_display_mode *mode,
4591 struct drm_display_mode *adjusted_mode,
4592 int x, int y,
4593 struct drm_framebuffer *old_fb)
79e53945
JB		 4594{
4595 struct drm_device *dev = crtc->dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598 int pipe = intel_crtc->pipe;
80824003 4599 int plane = intel_crtc->plane;
c751ce4f 4600 int refclk, num_connectors = 0;
652c393a 4601 intel_clock_t clock, reduced_clock;
5eddb70b 4602 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4603 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4604 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4605 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4606 const intel_limit_t *limit;
5c3b82e2 4607 int ret;
2c07245f 4608 struct fdi_m_n m_n = {0};
fae14981 4609 u32 temp;
5a354204
JB		 4610 int target_clock, pixel_multiplier, lane, link_bw, factor;
4611 unsigned int pipe_bpp;
4612 bool dither;
e3aef172 4613 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4614
6c2b7c12 4615 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4616 switch (encoder->type) {
79e53945
JB		 4617 case INTEL_OUTPUT_LVDS:
4618 is_lvds = true;
4619 break;
4620 case INTEL_OUTPUT_SDVO:
7d57382e 4621 case INTEL_OUTPUT_HDMI:
79e53945 4622 is_sdvo = true;
5eddb70b 4623 if (encoder->needs_tv_clock)
e2f0ba97 4624 is_tv = true;
79e53945 4625 break;
79e53945
JB		 4626 case INTEL_OUTPUT_TVOUT:
4627 is_tv = true;
4628 break;
4629 case INTEL_OUTPUT_ANALOG:
4630 is_crt = true;
4631 break;
a4fc5ed6
KP		 4632 case INTEL_OUTPUT_DISPLAYPORT:
4633 is_dp = true;
4634 break;
32f9d658 4635 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4636 is_dp = true;
4637 if (intel_encoder_is_pch_edp(&encoder->base))
4638 is_pch_edp = true;
4639 else
4640 is_cpu_edp = true;
4641 edp_encoder = encoder;
32f9d658 4642 break;
79e53945 4643 }
43565a06 4644
c751ce4f 4645 num_connectors++;
79e53945
JB		 4646 }
4647
d9d444cb 4648 refclk = ironlake_get_refclk(crtc);
79e53945 4649
d4906093
ML		 4650 /*
4651 * Returns a set of divisors for the desired target clock with the given
4652 * refclk, or FALSE. The returned values represent the clock equation:
4653 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4654 */
1b894b59 4655 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4656 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4657 &clock);
79e53945
JB		 4658 if (!ok) {
4659 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4660 return -EINVAL;
79e53945
JB		 4661 }
4662
cda4b7d3 4663 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4664 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4665
ddc9003c 4666 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4667 /*
4668 * Ensure we match the reduced clock's P to the target clock.
4669 * If the clocks don't match, we can't switch the display clock
4670 * by using the FP0/FP1. In such case we will disable the LVDS
4671 * downclock feature.
4672 */
ddc9003c 4673 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4674 dev_priv->lvds_downclock,
4675 refclk,
cec2f356 4676 &clock,
5eddb70b 4677 &reduced_clock);
652c393a 4678 }
61e9653f
DV		 4679
4680 if (is_sdvo && is_tv)
4681 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4682
7026d4ac 4683
2c07245f 4684 /* FDI link */
8febb297
EA		 4685 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4686 lane = 0;
4687 /* CPU eDP doesn't require FDI link, so just set DP M/N
4688 according to current link config */
e3aef172 4689 if (is_cpu_edp) {
e3aef172 4690 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4691 } else {
8febb297
EA		 4692 /* FDI is a binary signal running at ~2.7GHz, encoding
4693 * each output octet as 10 bits. The actual frequency
4694 * is stored as a divider into a 100MHz clock, and the
4695 * mode pixel clock is stored in units of 1KHz.
4696 * Hence the bw of each lane in terms of the mode signal
4697 * is:
4698 */
4699 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4700 }
58a27471 4701
94bf2ced
DV		 4702 /* [e]DP over FDI requires target mode clock instead of link clock. */
4703 if (edp_encoder)
4704 target_clock = intel_edp_target_clock(edp_encoder, mode);
4705 else if (is_dp)
4706 target_clock = mode->clock;
4707 else
4708 target_clock = adjusted_mode->clock;
4709
8febb297
EA		 4710 /* determine panel color depth */
4711 temp = I915_READ(PIPECONF(pipe));
4712 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4713 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4714 switch (pipe_bpp) {
4715 case 18:
4716 temp |= PIPE_6BPC;
8febb297 4717 break;
5a354204
JB		 4718 case 24:
4719 temp |= PIPE_8BPC;
8febb297 4720 break;
5a354204
JB		 4721 case 30:
4722 temp |= PIPE_10BPC;
8febb297 4723 break;
5a354204
JB		 4724 case 36:
4725 temp |= PIPE_12BPC;
8febb297
EA		 4726 break;
4727 default:
62ac41a6
JB		 4728 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4729 pipe_bpp);
5a354204
JB		 4730 temp |= PIPE_8BPC;
4731 pipe_bpp = 24;
4732 break;
8febb297 4733 }
77ffb597 4734
5a354204
JB		 4735 intel_crtc->bpp = pipe_bpp;
4736 I915_WRITE(PIPECONF(pipe), temp);
4737
8febb297
EA		 4738 if (!lane) {
4739 /*
4740 * Account for spread spectrum to avoid
4741 * oversubscribing the link. Max center spread
4742 * is 2.5%; use 5% for safety's sake.
4743 */
5a354204 4744 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4745 lane = bps / (link_bw * 8) + 1;
5eb08b69 4746 }
2c07245f 4747
8febb297
EA		 4748 intel_crtc->fdi_lanes = lane;
4749
4750 if (pixel_multiplier > 1)
4751 link_bw *= pixel_multiplier;
5a354204
JB		 4752 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4753 &m_n);
8febb297 4754
a07d6787
EA		 4755 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4756 if (has_reduced_clock)
4757 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4758 reduced_clock.m2;
79e53945 4759
c1858123 4760 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4761 factor = 21;
4762 if (is_lvds) {
4763 if ((intel_panel_use_ssc(dev_priv) &&
4764 dev_priv->lvds_ssc_freq == 100) ||
4765 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4766 factor = 25;
4767 } else if (is_sdvo && is_tv)
4768 factor = 20;
c1858123 4769
cb0e0931 4770 if (clock.m < factor * clock.n)
8febb297 4771 fp |= FP_CB_TUNE;
2c07245f 4772
5eddb70b 4773 dpll = 0;
2c07245f 4774
a07d6787
EA		 4775 if (is_lvds)
4776 dpll |= DPLLB_MODE_LVDS;
4777 else
4778 dpll |= DPLLB_MODE_DAC_SERIAL;
4779 if (is_sdvo) {
4780 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4781 if (pixel_multiplier > 1) {
4782 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4783 }
a07d6787
EA		 4784 dpll |= DPLL_DVO_HIGH_SPEED;
4785 }
e3aef172 4786 if (is_dp && !is_cpu_edp)
a07d6787 4787 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4788
a07d6787
EA		 4789 /* compute bitmask from p1 value */
4790 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4791 /* also FPA1 */
4792 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4793
4794 switch (clock.p2) {
4795 case 5:
4796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4797 break;
4798 case 7:
4799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4800 break;
4801 case 10:
4802 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4803 break;
4804 case 14:
4805 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4806 break;
79e53945
JB		 4807 }
4808
43565a06
KH		 4809 if (is_sdvo && is_tv)
4810 dpll |= PLL_REF_INPUT_TVCLKINBC;
4811 else if (is_tv)
79e53945 4812 /* XXX: just matching BIOS for now */
43565a06 4813 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4814 dpll |= 3;
a7615030 4815 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4816 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4817 else
4818 dpll |= PLL_REF_INPUT_DREFCLK;
4819
4820 /* setup pipeconf */
5eddb70b 4821 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4822
4823 /* Set up the display plane register */
4824 dspcntr = DISPPLANE_GAMMA_ENABLE;
4825
f7cb34d4 4826 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4827 drm_mode_debug_printmodeline(mode);
4828
9d82aa17
ED		 4829 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4830 * pre-Haswell/LPT generation */
4831 if (HAS_PCH_LPT(dev)) {
4832 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4833 pipe);
4834 } else if (!is_cpu_edp) {
ee7b9f93 4835 struct intel_pch_pll *pll;
4b645f14 4836
ee7b9f93
JB		 4837 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4838 if (pll == NULL) {
4839 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4840 pipe);
4b645f14
JB		 4841 return -EINVAL;
4842 }
ee7b9f93
JB		 4843 } else
4844 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4845
4846 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4847 * This is an exception to the general rule that mode_set doesn't turn
4848 * things on.
4849 */
4850 if (is_lvds) {
fae14981 4851 temp = I915_READ(PCH_LVDS);
5eddb70b 4852 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4853 if (HAS_PCH_CPT(dev)) {
4854 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4855 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4856 } else {
4857 if (pipe == 1)
4858 temp |= LVDS_PIPEB_SELECT;
4859 else
4860 temp &= ~LVDS_PIPEB_SELECT;
4861 }
4b645f14 4862
a3e17eb8 4863 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4864 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4865 /* Set the B0-B3 data pairs corresponding to whether we're going to
4866 * set the DPLLs for dual-channel mode or not.
4867 */
4868 if (clock.p2 == 7)
5eddb70b 4869 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4870 else
5eddb70b 4871 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4872
4873 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4874 * appropriately here, but we need to look more thoroughly into how
4875 * panels behave in the two modes.
4876 */
284d5df5 4877 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4878 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4879 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4880 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4881 temp |= LVDS_VSYNC_POLARITY;
fae14981 4882 I915_WRITE(PCH_LVDS, temp);
79e53945 4883 }
434ed097 4884
8febb297
EA		 4885 pipeconf &= ~PIPECONF_DITHER_EN;
4886 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4887 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4888 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4889 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4890 }
e3aef172 4891 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4892 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4893 } else {
8db9d77b 4894 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4895 I915_WRITE(TRANSDATA_M1(pipe), 0);
4896 I915_WRITE(TRANSDATA_N1(pipe), 0);
4897 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4898 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4899 }
79e53945 4900
ee7b9f93
JB		 4901 if (intel_crtc->pch_pll) {
4902 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4903
32f9d658 4904 /* Wait for the clocks to stabilize. */
ee7b9f93 4905 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4906 udelay(150);
4907
8febb297
EA		 4908 /* The pixel multiplier can only be updated once the
4909 * DPLL is enabled and the clocks are stable.
4910 *
4911 * So write it again.
4912 */
ee7b9f93 4913 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4914 }
79e53945 4915
5eddb70b 4916 intel_crtc->lowfreq_avail = false;
ee7b9f93 4917 if (intel_crtc->pch_pll) {
4b645f14 4918 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4919 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4920 intel_crtc->lowfreq_avail = true;
4b645f14 4921 } else {
ee7b9f93 4922 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4923 }
4924 }
4925
617cf884 4926 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4927 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4928 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4929 /* the chip adds 2 halflines automatically */
734b4157 4930 adjusted_mode->crtc_vtotal -= 1;
734b4157 4931 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4932 I915_WRITE(VSYNCSHIFT(pipe),
4933 adjusted_mode->crtc_hsync_start
4934 - adjusted_mode->crtc_htotal/2);
4935 } else {
617cf884 4936 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4937 I915_WRITE(VSYNCSHIFT(pipe), 0);
4938 }
734b4157 4939
5eddb70b
CW		 4940 I915_WRITE(HTOTAL(pipe),
4941 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4942 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4943 I915_WRITE(HBLANK(pipe),
4944 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4945 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4946 I915_WRITE(HSYNC(pipe),
4947 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4948 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4949
4950 I915_WRITE(VTOTAL(pipe),
4951 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4952 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4953 I915_WRITE(VBLANK(pipe),
4954 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4955 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4956 I915_WRITE(VSYNC(pipe),
4957 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4958 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4959
8febb297
EA		 4960 /* pipesrc controls the size that is scaled from, which should
4961 * always be the user's requested size.
79e53945 4962 */
5eddb70b
CW		 4963 I915_WRITE(PIPESRC(pipe),
4964 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4965
8febb297
EA		 4966 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4967 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4968 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4969 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4970
e3aef172 4971 if (is_cpu_edp)
8febb297 4972 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4973
5eddb70b
CW		 4974 I915_WRITE(PIPECONF(pipe), pipeconf);
4975 POSTING_READ(PIPECONF(pipe));
79e53945 4976
9d0498a2 4977 intel_wait_for_vblank(dev, pipe);
79e53945 4978
5eddb70b 4979 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4980 POSTING_READ(DSPCNTR(plane));
79e53945 4981
5c3b82e2 4982 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4983
4984 intel_update_watermarks(dev);
4985
1f8eeabf
ED		 4986 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4987
1f803ee5 4988 return ret;
79e53945
JB		 4989}
4990
f564048e
EA		 4991static int intel_crtc_mode_set(struct drm_crtc *crtc,
4992 struct drm_display_mode *mode,
4993 struct drm_display_mode *adjusted_mode,
4994 int x, int y,
4995 struct drm_framebuffer *old_fb)
4996{
4997 struct drm_device *dev = crtc->dev;
4998 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5000 int pipe = intel_crtc->pipe;
f564048e
EA		 5001 int ret;
5002
0b701d27 5003 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5004
f564048e
EA		 5005 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5006 x, y, old_fb);
79e53945 5007 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5008
d8e70a25
JB		 5009 if (ret)
5010 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5011 else
5012 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 5013
1f803ee5 5014 return ret;
79e53945
JB		 5015}
5016
3a9627f4
WF		 5017static bool intel_eld_uptodate(struct drm_connector *connector,
5018 int reg_eldv, uint32_t bits_eldv,
5019 int reg_elda, uint32_t bits_elda,
5020 int reg_edid)
5021{
5022 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5023 uint8_t *eld = connector->eld;
5024 uint32_t i;
5025
5026 i = I915_READ(reg_eldv);
5027 i &= bits_eldv;
5028
5029 if (!eld[0])
5030 return !i;
5031
5032 if (!i)
5033 return false;
5034
5035 i = I915_READ(reg_elda);
5036 i &= ~bits_elda;
5037 I915_WRITE(reg_elda, i);
5038
5039 for (i = 0; i < eld[2]; i++)
5040 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5041 return false;
5042
5043 return true;
5044}
5045
e0dac65e
WF		 5046static void g4x_write_eld(struct drm_connector *connector,
5047 struct drm_crtc *crtc)
5048{
5049 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5050 uint8_t *eld = connector->eld;
5051 uint32_t eldv;
5052 uint32_t len;
5053 uint32_t i;
5054
5055 i = I915_READ(G4X_AUD_VID_DID);
5056
5057 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5058 eldv = G4X_ELDV_DEVCL_DEVBLC;
5059 else
5060 eldv = G4X_ELDV_DEVCTG;
5061
3a9627f4
WF		 5062 if (intel_eld_uptodate(connector,
5063 G4X_AUD_CNTL_ST, eldv,
5064 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5065 G4X_HDMIW_HDMIEDID))
5066 return;
5067
e0dac65e
WF		 5068 i = I915_READ(G4X_AUD_CNTL_ST);
5069 i &= ~(eldv | G4X_ELD_ADDR);
5070 len = (i >> 9) & 0x1f; /* ELD buffer size */
5071 I915_WRITE(G4X_AUD_CNTL_ST, i);
5072
5073 if (!eld[0])
5074 return;
5075
5076 len = min_t(uint8_t, eld[2], len);
5077 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5078 for (i = 0; i < len; i++)
5079 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5080
5081 i = I915_READ(G4X_AUD_CNTL_ST);
5082 i |= eldv;
5083 I915_WRITE(G4X_AUD_CNTL_ST, i);
5084}
5085
83358c85
WX		 5086static void haswell_write_eld(struct drm_connector *connector,
5087 struct drm_crtc *crtc)
5088{
5089 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5090 uint8_t *eld = connector->eld;
5091 struct drm_device *dev = crtc->dev;
5092 uint32_t eldv;
5093 uint32_t i;
5094 int len;
5095 int pipe = to_intel_crtc(crtc)->pipe;
5096 int tmp;
5097
5098 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5099 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5100 int aud_config = HSW_AUD_CFG(pipe);
5101 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5102
5103
5104 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5105
5106 /* Audio output enable */
5107 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5108 tmp = I915_READ(aud_cntrl_st2);
5109 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5110 I915_WRITE(aud_cntrl_st2, tmp);
5111
5112 /* Wait for 1 vertical blank */
5113 intel_wait_for_vblank(dev, pipe);
5114
5115 /* Set ELD valid state */
5116 tmp = I915_READ(aud_cntrl_st2);
5117 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5118 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5119 I915_WRITE(aud_cntrl_st2, tmp);
5120 tmp = I915_READ(aud_cntrl_st2);
5121 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5122
5123 /* Enable HDMI mode */
5124 tmp = I915_READ(aud_config);
5125 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5126 /* clear N_programing_enable and N_value_index */
5127 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5128 I915_WRITE(aud_config, tmp);
5129
5130 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5131
5132 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5133
5134 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5135 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5136 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5137 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5138 } else
5139 I915_WRITE(aud_config, 0);
5140
5141 if (intel_eld_uptodate(connector,
5142 aud_cntrl_st2, eldv,
5143 aud_cntl_st, IBX_ELD_ADDRESS,
5144 hdmiw_hdmiedid))
5145 return;
5146
5147 i = I915_READ(aud_cntrl_st2);
5148 i &= ~eldv;
5149 I915_WRITE(aud_cntrl_st2, i);
5150
5151 if (!eld[0])
5152 return;
5153
5154 i = I915_READ(aud_cntl_st);
5155 i &= ~IBX_ELD_ADDRESS;
5156 I915_WRITE(aud_cntl_st, i);
5157 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5158 DRM_DEBUG_DRIVER("port num:%d\n", i);
5159
5160 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5161 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5162 for (i = 0; i < len; i++)
5163 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5164
5165 i = I915_READ(aud_cntrl_st2);
5166 i |= eldv;
5167 I915_WRITE(aud_cntrl_st2, i);
5168
5169}
5170
e0dac65e
WF		 5171static void ironlake_write_eld(struct drm_connector *connector,
5172 struct drm_crtc *crtc)
5173{
5174 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5175 uint8_t *eld = connector->eld;
5176 uint32_t eldv;
5177 uint32_t i;
5178 int len;
5179 int hdmiw_hdmiedid;
b6daa025 5180 int aud_config;
e0dac65e
WF		 5181 int aud_cntl_st;
5182 int aud_cntrl_st2;
9b138a83 5183 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5184
b3f33cbf 5185 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5186 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5187 aud_config = IBX_AUD_CFG(pipe);
5188 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5189 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5190 } else {
9b138a83
WX		 5191 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5192 aud_config = CPT_AUD_CFG(pipe);
5193 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5194 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5195 }
5196
9b138a83 5197 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5198
5199 i = I915_READ(aud_cntl_st);
9b138a83 5200 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5201 if (!i) {
5202 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5203 /* operate blindly on all ports */
1202b4c6
WF		 5204 eldv = IBX_ELD_VALIDB;
5205 eldv |= IBX_ELD_VALIDB << 4;
5206 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5207 } else {
5208 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5209 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5210 }
5211
3a9627f4
WF		 5212 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5213 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5214 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5215 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5216 } else
5217 I915_WRITE(aud_config, 0);
e0dac65e 5218
3a9627f4
WF		 5219 if (intel_eld_uptodate(connector,
5220 aud_cntrl_st2, eldv,
5221 aud_cntl_st, IBX_ELD_ADDRESS,
5222 hdmiw_hdmiedid))
5223 return;
5224
e0dac65e
WF		 5225 i = I915_READ(aud_cntrl_st2);
5226 i &= ~eldv;
5227 I915_WRITE(aud_cntrl_st2, i);
5228
5229 if (!eld[0])
5230 return;
5231
e0dac65e 5232 i = I915_READ(aud_cntl_st);
1202b4c6 5233 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5234 I915_WRITE(aud_cntl_st, i);
5235
5236 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5237 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5238 for (i = 0; i < len; i++)
5239 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5240
5241 i = I915_READ(aud_cntrl_st2);
5242 i |= eldv;
5243 I915_WRITE(aud_cntrl_st2, i);
5244}
5245
5246void intel_write_eld(struct drm_encoder *encoder,
5247 struct drm_display_mode *mode)
5248{
5249 struct drm_crtc *crtc = encoder->crtc;
5250 struct drm_connector *connector;
5251 struct drm_device *dev = encoder->dev;
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253
5254 connector = drm_select_eld(encoder, mode);
5255 if (!connector)
5256 return;
5257
5258 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5259 connector->base.id,
5260 drm_get_connector_name(connector),
5261 connector->encoder->base.id,
5262 drm_get_encoder_name(connector->encoder));
5263
5264 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5265
5266 if (dev_priv->display.write_eld)
5267 dev_priv->display.write_eld(connector, crtc);
5268}
5269
79e53945
JB		 5270/** Loads the palette/gamma unit for the CRTC with the prepared values */
5271void intel_crtc_load_lut(struct drm_crtc *crtc)
5272{
5273 struct drm_device *dev = crtc->dev;
5274 struct drm_i915_private *dev_priv = dev->dev_private;
5275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5276 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5277 int i;
5278
5279 /* The clocks have to be on to load the palette. */
aed3f09d 5280 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5281 return;
5282
f2b115e6 5283 /* use legacy palette for Ironlake */
bad720ff 5284 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5285 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5286
79e53945
JB		 5287 for (i = 0; i < 256; i++) {
5288 I915_WRITE(palreg + 4 * i,
5289 (intel_crtc->lut_r[i] << 16) |
5290 (intel_crtc->lut_g[i] << 8) |
5291 intel_crtc->lut_b[i]);
5292 }
5293}
5294
560b85bb
CW		 5295static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5296{
5297 struct drm_device *dev = crtc->dev;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5300 bool visible = base != 0;
5301 u32 cntl;
5302
5303 if (intel_crtc->cursor_visible == visible)
5304 return;
5305
9db4a9c7 5306 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5307 if (visible) {
5308 /* On these chipsets we can only modify the base whilst
5309 * the cursor is disabled.
5310 */
9db4a9c7 5311 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5312
5313 cntl &= ~(CURSOR_FORMAT_MASK);
5314 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5315 cntl |= CURSOR_ENABLE |
5316 CURSOR_GAMMA_ENABLE |
5317 CURSOR_FORMAT_ARGB;
5318 } else
5319 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5320 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5321
5322 intel_crtc->cursor_visible = visible;
5323}
5324
5325static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5326{
5327 struct drm_device *dev = crtc->dev;
5328 struct drm_i915_private *dev_priv = dev->dev_private;
5329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5330 int pipe = intel_crtc->pipe;
5331 bool visible = base != 0;
5332
5333 if (intel_crtc->cursor_visible != visible) {
548f245b 5334 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5335 if (base) {
5336 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5337 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5338 cntl |= pipe << 28; /* Connect to correct pipe */
5339 } else {
5340 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5341 cntl |= CURSOR_MODE_DISABLE;
5342 }
9db4a9c7 5343 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5344
5345 intel_crtc->cursor_visible = visible;
5346 }
5347 /* and commit changes on next vblank */
9db4a9c7 5348 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5349}
5350
65a21cd6
JB		 5351static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5352{
5353 struct drm_device *dev = crtc->dev;
5354 struct drm_i915_private *dev_priv = dev->dev_private;
5355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5356 int pipe = intel_crtc->pipe;
5357 bool visible = base != 0;
5358
5359 if (intel_crtc->cursor_visible != visible) {
5360 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5361 if (base) {
5362 cntl &= ~CURSOR_MODE;
5363 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5364 } else {
5365 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5366 cntl |= CURSOR_MODE_DISABLE;
5367 }
5368 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5369
5370 intel_crtc->cursor_visible = visible;
5371 }
5372 /* and commit changes on next vblank */
5373 I915_WRITE(CURBASE_IVB(pipe), base);
5374}
5375
cda4b7d3 5376/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5377static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5378 bool on)
cda4b7d3
CW		 5379{
5380 struct drm_device *dev = crtc->dev;
5381 struct drm_i915_private *dev_priv = dev->dev_private;
5382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383 int pipe = intel_crtc->pipe;
5384 int x = intel_crtc->cursor_x;
5385 int y = intel_crtc->cursor_y;
560b85bb 5386 u32 base, pos;
cda4b7d3
CW		 5387 bool visible;
5388
5389 pos = 0;
5390
6b383a7f 5391 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5392 base = intel_crtc->cursor_addr;
5393 if (x > (int) crtc->fb->width)
5394 base = 0;
5395
5396 if (y > (int) crtc->fb->height)
5397 base = 0;
5398 } else
5399 base = 0;
5400
5401 if (x < 0) {
5402 if (x + intel_crtc->cursor_width < 0)
5403 base = 0;
5404
5405 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5406 x = -x;
5407 }
5408 pos |= x << CURSOR_X_SHIFT;
5409
5410 if (y < 0) {
5411 if (y + intel_crtc->cursor_height < 0)
5412 base = 0;
5413
5414 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5415 y = -y;
5416 }
5417 pos |= y << CURSOR_Y_SHIFT;
5418
5419 visible = base != 0;
560b85bb 5420 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5421 return;
5422
0cd83aa9 5423 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5424 I915_WRITE(CURPOS_IVB(pipe), pos);
5425 ivb_update_cursor(crtc, base);
5426 } else {
5427 I915_WRITE(CURPOS(pipe), pos);
5428 if (IS_845G(dev) || IS_I865G(dev))
5429 i845_update_cursor(crtc, base);
5430 else
5431 i9xx_update_cursor(crtc, base);
5432 }
cda4b7d3
CW		 5433}
5434
79e53945 5435static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5436 struct drm_file *file,
79e53945
JB		 5437 uint32_t handle,
5438 uint32_t width, uint32_t height)
5439{
5440 struct drm_device *dev = crtc->dev;
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5443 struct drm_i915_gem_object *obj;
cda4b7d3 5444 uint32_t addr;
3f8bc370 5445 int ret;
79e53945 5446
28c97730 5447 DRM_DEBUG_KMS("\n");
79e53945
JB		 5448
5449 /* if we want to turn off the cursor ignore width and height */
5450 if (!handle) {
28c97730 5451 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5452 addr = 0;
05394f39 5453 obj = NULL;
5004417d 5454 mutex_lock(&dev->struct_mutex);
3f8bc370 5455 goto finish;
79e53945
JB		 5456 }
5457
5458 /* Currently we only support 64x64 cursors */
5459 if (width != 64 || height != 64) {
5460 DRM_ERROR("we currently only support 64x64 cursors\n");
5461 return -EINVAL;
5462 }
5463
05394f39 5464 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5465 if (&obj->base == NULL)
79e53945
JB		 5466 return -ENOENT;
5467
05394f39 5468 if (obj->base.size < width * height * 4) {
79e53945 5469 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5470 ret = -ENOMEM;
5471 goto fail;
79e53945
JB		 5472 }
5473
71acb5eb 5474 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5475 mutex_lock(&dev->struct_mutex);
b295d1b6 5476 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5477 if (obj->tiling_mode) {
5478 DRM_ERROR("cursor cannot be tiled\n");
5479 ret = -EINVAL;
5480 goto fail_locked;
5481 }
5482
2da3b9b9 5483 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5484 if (ret) {
5485 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5486 goto fail_locked;
e7b526bb
CW		 5487 }
5488
d9e86c0e
CW		 5489 ret = i915_gem_object_put_fence(obj);
5490 if (ret) {
2da3b9b9 5491 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5492 goto fail_unpin;
5493 }
5494
05394f39 5495 addr = obj->gtt_offset;
71acb5eb 5496 } else {
6eeefaf3 5497 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5498 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5499 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5500 align);
71acb5eb
DA		 5501 if (ret) {
5502 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5503 goto fail_locked;
71acb5eb 5504 }
05394f39 5505 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5506 }
5507
a6c45cf0 5508 if (IS_GEN2(dev))
14b60391
JB		 5509 I915_WRITE(CURSIZE, (height << 12) | width);
5510
3f8bc370 5511 finish:
3f8bc370 5512 if (intel_crtc->cursor_bo) {
b295d1b6 5513 if (dev_priv->info->cursor_needs_physical) {
05394f39 5514 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5515 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5516 } else
5517 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5518 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5519 }
80824003 5520
7f9872e0 5521 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5522
5523 intel_crtc->cursor_addr = addr;
05394f39 5524 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5525 intel_crtc->cursor_width = width;
5526 intel_crtc->cursor_height = height;
5527
6b383a7f 5528 intel_crtc_update_cursor(crtc, true);
3f8bc370 5529
79e53945 5530 return 0;
e7b526bb 5531fail_unpin:
05394f39 5532 i915_gem_object_unpin(obj);
7f9872e0 5533fail_locked:
34b8686e 5534 mutex_unlock(&dev->struct_mutex);
bc9025bd 5535fail:
05394f39 5536 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5537 return ret;
79e53945
JB		 5538}
5539
5540static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5541{
79e53945 5542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5543
cda4b7d3
CW		 5544 intel_crtc->cursor_x = x;
5545 intel_crtc->cursor_y = y;
652c393a 5546
6b383a7f 5547 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5548
5549 return 0;
5550}
5551
5552/** Sets the color ramps on behalf of RandR */
5553void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5554 u16 blue, int regno)
5555{
5556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5557
5558 intel_crtc->lut_r[regno] = red >> 8;
5559 intel_crtc->lut_g[regno] = green >> 8;
5560 intel_crtc->lut_b[regno] = blue >> 8;
5561}
5562
b8c00ac5
DA		 5563void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5564 u16 *blue, int regno)
5565{
5566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5567
5568 *red = intel_crtc->lut_r[regno] << 8;
5569 *green = intel_crtc->lut_g[regno] << 8;
5570 *blue = intel_crtc->lut_b[regno] << 8;
5571}
5572
79e53945 5573static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5574 u16 *blue, uint32_t start, uint32_t size)
79e53945 5575{
7203425a 5576 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5578
7203425a 5579 for (i = start; i < end; i++) {
79e53945
JB		 5580 intel_crtc->lut_r[i] = red[i] >> 8;
5581 intel_crtc->lut_g[i] = green[i] >> 8;
5582 intel_crtc->lut_b[i] = blue[i] >> 8;
5583 }
5584
5585 intel_crtc_load_lut(crtc);
5586}
5587
5588/**
5589 * Get a pipe with a simple mode set on it for doing load-based monitor
5590 * detection.
5591 *
5592 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5593 * its requirements. The pipe will be connected to no other encoders.
79e53945 5594 *
c751ce4f 5595 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5596 * configured for it. In the future, it could choose to temporarily disable
5597 * some outputs to free up a pipe for its use.
5598 *
5599 * \return crtc, or NULL if no pipes are available.
5600 */
5601
5602/* VESA 640x480x72Hz mode to set on the pipe */
5603static struct drm_display_mode load_detect_mode = {
5604 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5605 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5606};
5607
d2dff872
CW		 5608static struct drm_framebuffer *
5609intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5610 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5611 struct drm_i915_gem_object *obj)
5612{
5613 struct intel_framebuffer *intel_fb;
5614 int ret;
5615
5616 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5617 if (!intel_fb) {
5618 drm_gem_object_unreference_unlocked(&obj->base);
5619 return ERR_PTR(-ENOMEM);
5620 }
5621
5622 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5623 if (ret) {
5624 drm_gem_object_unreference_unlocked(&obj->base);
5625 kfree(intel_fb);
5626 return ERR_PTR(ret);
5627 }
5628
5629 return &intel_fb->base;
5630}
5631
5632static u32
5633intel_framebuffer_pitch_for_width(int width, int bpp)
5634{
5635 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5636 return ALIGN(pitch, 64);
5637}
5638
5639static u32
5640intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5641{
5642 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5643 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5644}
5645
5646static struct drm_framebuffer *
5647intel_framebuffer_create_for_mode(struct drm_device *dev,
5648 struct drm_display_mode *mode,
5649 int depth, int bpp)
5650{
5651 struct drm_i915_gem_object *obj;
308e5bcb 5652 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5653
5654 obj = i915_gem_alloc_object(dev,
5655 intel_framebuffer_size_for_mode(mode, bpp));
5656 if (obj == NULL)
5657 return ERR_PTR(-ENOMEM);
5658
5659 mode_cmd.width = mode->hdisplay;
5660 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5661 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5662 bpp);
5ca0c34a 5663 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5664
5665 return intel_framebuffer_create(dev, &mode_cmd, obj);
5666}
5667
5668static struct drm_framebuffer *
5669mode_fits_in_fbdev(struct drm_device *dev,
5670 struct drm_display_mode *mode)
5671{
5672 struct drm_i915_private *dev_priv = dev->dev_private;
5673 struct drm_i915_gem_object *obj;
5674 struct drm_framebuffer *fb;
5675
5676 if (dev_priv->fbdev == NULL)
5677 return NULL;
5678
5679 obj = dev_priv->fbdev->ifb.obj;
5680 if (obj == NULL)
5681 return NULL;
5682
5683 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5684 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5685 fb->bits_per_pixel))
d2dff872
CW		 5686 return NULL;
5687
01f2c773 5688 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5689 return NULL;
5690
5691 return fb;
5692}
5693
d2434ab7 5694bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5695 struct drm_display_mode *mode,
8261b191 5696 struct intel_load_detect_pipe *old)
79e53945
JB		 5697{
5698 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5699 struct intel_encoder *intel_encoder =
5700 intel_attached_encoder(connector);
79e53945 5701 struct drm_crtc *possible_crtc;
4ef69c7a 5702 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5703 struct drm_crtc *crtc = NULL;
5704 struct drm_device *dev = encoder->dev;
d2dff872 5705 struct drm_framebuffer *old_fb;
79e53945
JB		 5706 int i = -1;
5707
d2dff872
CW		 5708 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5709 connector->base.id, drm_get_connector_name(connector),
5710 encoder->base.id, drm_get_encoder_name(encoder));
5711
79e53945
JB		 5712 /*
5713 * Algorithm gets a little messy:
7a5e4805 5714 *
79e53945
JB		 5715 * - if the connector already has an assigned crtc, use it (but make
5716 * sure it's on first)
7a5e4805 5717 *
79e53945
JB		 5718 * - try to find the first unused crtc that can drive this connector,
5719 * and use that if we find one
79e53945
JB		 5720 */
5721
5722 /* See if we already have a CRTC for this connector */
5723 if (encoder->crtc) {
5724 crtc = encoder->crtc;
8261b191 5725
24218aac 5726 old->dpms_mode = connector->dpms;
8261b191
CW		 5727 old->load_detect_temp = false;
5728
5729 /* Make sure the crtc and connector are running */
24218aac
DV		 5730 if (connector->dpms != DRM_MODE_DPMS_ON)
5731 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5732
7173188d 5733 return true;
79e53945
JB		 5734 }
5735
5736 /* Find an unused one (if possible) */
5737 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5738 i++;
5739 if (!(encoder->possible_crtcs & (1 << i)))
5740 continue;
5741 if (!possible_crtc->enabled) {
5742 crtc = possible_crtc;
5743 break;
5744 }
79e53945
JB		 5745 }
5746
5747 /*
5748 * If we didn't find an unused CRTC, don't use any.
5749 */
5750 if (!crtc) {
7173188d
CW		 5751 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5752 return false;
79e53945
JB		 5753 }
5754
5755 encoder->crtc = crtc;
c1c43977 5756 connector->encoder = encoder;
79e53945
JB		 5757
5758 intel_crtc = to_intel_crtc(crtc);
24218aac 5759 old->dpms_mode = connector->dpms;
8261b191 5760 old->load_detect_temp = true;
d2dff872 5761 old->release_fb = NULL;
79e53945 5762
6492711d
CW		 5763 if (!mode)
5764 mode = &load_detect_mode;
79e53945 5765
d2dff872
CW		 5766 old_fb = crtc->fb;
5767
5768 /* We need a framebuffer large enough to accommodate all accesses
5769 * that the plane may generate whilst we perform load detection.
5770 * We can not rely on the fbcon either being present (we get called
5771 * during its initialisation to detect all boot displays, or it may
5772 * not even exist) or that it is large enough to satisfy the
5773 * requested mode.
5774 */
5775 crtc->fb = mode_fits_in_fbdev(dev, mode);
5776 if (crtc->fb == NULL) {
5777 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5778 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5779 old->release_fb = crtc->fb;
5780 } else
5781 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5782 if (IS_ERR(crtc->fb)) {
5783 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5784 goto fail;
79e53945 5785 }
79e53945 5786
d2dff872 5787 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5788 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5789 if (old->release_fb)
5790 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5791 goto fail;
79e53945 5792 }
7173188d 5793
79e53945 5794 /* let the connector get through one full cycle before testing */
9d0498a2 5795 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5796
7173188d 5797 return true;
24218aac
DV		 5798fail:
5799 connector->encoder = NULL;
5800 encoder->crtc = NULL;
5801 crtc->fb = old_fb;
5802 return false;
79e53945
JB		 5803}
5804
d2434ab7 5805void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5806 struct intel_load_detect_pipe *old)
79e53945 5807{
d2434ab7
DV		 5808 struct intel_encoder *intel_encoder =
5809 intel_attached_encoder(connector);
4ef69c7a 5810 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5811 struct drm_device *dev = encoder->dev;
79e53945 5812
d2dff872
CW		 5813 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5814 connector->base.id, drm_get_connector_name(connector),
5815 encoder->base.id, drm_get_encoder_name(encoder));
5816
8261b191 5817 if (old->load_detect_temp) {
c1c43977 5818 connector->encoder = NULL;
24218aac 5819 encoder->crtc = NULL;
79e53945 5820 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5821
5822 if (old->release_fb)
5823 old->release_fb->funcs->destroy(old->release_fb);
5824
0622a53c 5825 return;
79e53945
JB		 5826 }
5827
c751ce4f 5828 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5829 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5830 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5831}
5832
5833/* Returns the clock of the currently programmed mode of the given pipe. */
5834static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5835{
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5838 int pipe = intel_crtc->pipe;
548f245b 5839 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5840 u32 fp;
5841 intel_clock_t clock;
5842
5843 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5844 fp = I915_READ(FP0(pipe));
79e53945 5845 else
39adb7a5 5846 fp = I915_READ(FP1(pipe));
79e53945
JB		 5847
5848 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5849 if (IS_PINEVIEW(dev)) {
5850 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5851 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5852 } else {
5853 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5854 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5855 }
5856
a6c45cf0 5857 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5858 if (IS_PINEVIEW(dev))
5859 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5860 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5861 else
5862 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5863 DPLL_FPA01_P1_POST_DIV_SHIFT);
5864
5865 switch (dpll & DPLL_MODE_MASK) {
5866 case DPLLB_MODE_DAC_SERIAL:
5867 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5868 5 : 10;
5869 break;
5870 case DPLLB_MODE_LVDS:
5871 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5872 7 : 14;
5873 break;
5874 default:
28c97730 5875 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5876 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5877 return 0;
5878 }
5879
5880 /* XXX: Handle the 100Mhz refclk */
2177832f 5881 intel_clock(dev, 96000, &clock);
79e53945
JB		 5882 } else {
5883 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5884
5885 if (is_lvds) {
5886 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5887 DPLL_FPA01_P1_POST_DIV_SHIFT);
5888 clock.p2 = 14;
5889
5890 if ((dpll & PLL_REF_INPUT_MASK) ==
5891 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5892 /* XXX: might not be 66MHz */
2177832f 5893 intel_clock(dev, 66000, &clock);
79e53945 5894 } else
2177832f 5895 intel_clock(dev, 48000, &clock);
79e53945
JB		 5896 } else {
5897 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5898 clock.p1 = 2;
5899 else {
5900 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5901 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5902 }
5903 if (dpll & PLL_P2_DIVIDE_BY_4)
5904 clock.p2 = 4;
5905 else
5906 clock.p2 = 2;
5907
2177832f 5908 intel_clock(dev, 48000, &clock);
79e53945
JB		 5909 }
5910 }
5911
5912 /* XXX: It would be nice to validate the clocks, but we can't reuse
5913 * i830PllIsValid() because it relies on the xf86_config connector
5914 * configuration being accurate, which it isn't necessarily.
5915 */
5916
5917 return clock.dot;
5918}
5919
5920/** Returns the currently programmed mode of the given pipe. */
5921struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5922 struct drm_crtc *crtc)
5923{
548f245b 5924 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5926 int pipe = intel_crtc->pipe;
5927 struct drm_display_mode *mode;
548f245b
JB		 5928 int htot = I915_READ(HTOTAL(pipe));
5929 int hsync = I915_READ(HSYNC(pipe));
5930 int vtot = I915_READ(VTOTAL(pipe));
5931 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5932
5933 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5934 if (!mode)
5935 return NULL;
5936
5937 mode->clock = intel_crtc_clock_get(dev, crtc);
5938 mode->hdisplay = (htot & 0xffff) + 1;
5939 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5940 mode->hsync_start = (hsync & 0xffff) + 1;
5941 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5942 mode->vdisplay = (vtot & 0xffff) + 1;
5943 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5944 mode->vsync_start = (vsync & 0xffff) + 1;
5945 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5946
5947 drm_mode_set_name(mode);
79e53945
JB		 5948
5949 return mode;
5950}
5951
3dec0095 5952static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5953{
5954 struct drm_device *dev = crtc->dev;
5955 drm_i915_private_t *dev_priv = dev->dev_private;
5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5958 int dpll_reg = DPLL(pipe);
5959 int dpll;
652c393a 5960
bad720ff 5961 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5962 return;
5963
5964 if (!dev_priv->lvds_downclock_avail)
5965 return;
5966
dbdc6479 5967 dpll = I915_READ(dpll_reg);
652c393a 5968 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5969 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5970
8ac5a6d5 5971 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5972
5973 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5974 I915_WRITE(dpll_reg, dpll);
9d0498a2 5975 intel_wait_for_vblank(dev, pipe);
dbdc6479 5976
652c393a
JB		 5977 dpll = I915_READ(dpll_reg);
5978 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5979 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 5980 }
652c393a
JB		 5981}
5982
5983static void intel_decrease_pllclock(struct drm_crtc *crtc)
5984{
5985 struct drm_device *dev = crtc->dev;
5986 drm_i915_private_t *dev_priv = dev->dev_private;
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5988
bad720ff 5989 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5990 return;
5991
5992 if (!dev_priv->lvds_downclock_avail)
5993 return;
5994
5995 /*
5996 * Since this is called by a timer, we should never get here in
5997 * the manual case.
5998 */
5999 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6000 int pipe = intel_crtc->pipe;
6001 int dpll_reg = DPLL(pipe);
6002 int dpll;
f6e5b160 6003
44d98a61 6004 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6005
8ac5a6d5 6006 assert_panel_unlocked(dev_priv, pipe);
652c393a 6007
dc257cf1 6008 dpll = I915_READ(dpll_reg);
652c393a
JB		 6009 dpll |= DISPLAY_RATE_SELECT_FPA1;
6010 I915_WRITE(dpll_reg, dpll);
9d0498a2 6011 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6012 dpll = I915_READ(dpll_reg);
6013 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6014 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6015 }
6016
6017}
6018
f047e395
CW		 6019void intel_mark_busy(struct drm_device *dev)
6020{
f047e395
CW		 6021 i915_update_gfx_val(dev->dev_private);
6022}
6023
6024void intel_mark_idle(struct drm_device *dev)
652c393a 6025{
f047e395
CW		 6026}
6027
6028void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6029{
6030 struct drm_device *dev = obj->base.dev;
652c393a 6031 struct drm_crtc *crtc;
652c393a
JB		 6032
6033 if (!i915_powersave)
6034 return;
6035
652c393a 6036 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6037 if (!crtc->fb)
6038 continue;
6039
f047e395
CW		 6040 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6041 intel_increase_pllclock(crtc);
652c393a 6042 }
652c393a
JB		 6043}
6044
f047e395 6045void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6046{
f047e395
CW		 6047 struct drm_device *dev = obj->base.dev;
6048 struct drm_crtc *crtc;
652c393a 6049
f047e395 6050 if (!i915_powersave)
acb87dfb
CW		 6051 return;
6052
652c393a
JB		 6053 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6054 if (!crtc->fb)
6055 continue;
6056
f047e395
CW		 6057 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6058 intel_decrease_pllclock(crtc);
652c393a
JB		 6059 }
6060}
6061
79e53945
JB		 6062static void intel_crtc_destroy(struct drm_crtc *crtc)
6063{
6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6065 struct drm_device *dev = crtc->dev;
6066 struct intel_unpin_work *work;
6067 unsigned long flags;
6068
6069 spin_lock_irqsave(&dev->event_lock, flags);
6070 work = intel_crtc->unpin_work;
6071 intel_crtc->unpin_work = NULL;
6072 spin_unlock_irqrestore(&dev->event_lock, flags);
6073
6074 if (work) {
6075 cancel_work_sync(&work->work);
6076 kfree(work);
6077 }
79e53945
JB		 6078
6079 drm_crtc_cleanup(crtc);
67e77c5a 6080
79e53945
JB		 6081 kfree(intel_crtc);
6082}
6083
6b95a207
KH		 6084static void intel_unpin_work_fn(struct work_struct *__work)
6085{
6086 struct intel_unpin_work *work =
6087 container_of(__work, struct intel_unpin_work, work);
6088
6089 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6090 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6091 drm_gem_object_unreference(&work->pending_flip_obj->base);
6092 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6093
7782de3b 6094 intel_update_fbc(work->dev);
6b95a207
KH		 6095 mutex_unlock(&work->dev->struct_mutex);
6096 kfree(work);
6097}
6098
1afe3e9d 6099static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6100 struct drm_crtc *crtc)
6b95a207
KH		 6101{
6102 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6104 struct intel_unpin_work *work;
05394f39 6105 struct drm_i915_gem_object *obj;
6b95a207 6106 struct drm_pending_vblank_event *e;
49b14a5c 6107 struct timeval tnow, tvbl;
6b95a207
KH		 6108 unsigned long flags;
6109
6110 /* Ignore early vblank irqs */
6111 if (intel_crtc == NULL)
6112 return;
6113
49b14a5c
MK		 6114 do_gettimeofday(&tnow);
6115
6b95a207
KH		 6116 spin_lock_irqsave(&dev->event_lock, flags);
6117 work = intel_crtc->unpin_work;
6118 if (work == NULL || !work->pending) {
6119 spin_unlock_irqrestore(&dev->event_lock, flags);
6120 return;
6121 }
6122
6123 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6124
6125 if (work->event) {
6126 e = work->event;
49b14a5c 6127 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6128
6129 /* Called before vblank count and timestamps have
6130 * been updated for the vblank interval of flip
6131 * completion? Need to increment vblank count and
6132 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6133 * to account for this. We assume this happened if we
6134 * get called over 0.9 frame durations after the last
6135 * timestamped vblank.
6136 *
6137 * This calculation can not be used with vrefresh rates
6138 * below 5Hz (10Hz to be on the safe side) without
6139 * promoting to 64 integers.
0af7e4df 6140 */
49b14a5c
MK		 6141 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6142 9 * crtc->framedur_ns) {
0af7e4df 6143 e->event.sequence++;
49b14a5c
MK		 6144 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6145 crtc->framedur_ns);
0af7e4df
MK		 6146 }
6147
49b14a5c
MK		 6148 e->event.tv_sec = tvbl.tv_sec;
6149 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6150
6b95a207
KH		 6151 list_add_tail(&e->base.link,
6152 &e->base.file_priv->event_list);
6153 wake_up_interruptible(&e->base.file_priv->event_wait);
6154 }
6155
0af7e4df
MK		 6156 drm_vblank_put(dev, intel_crtc->pipe);
6157
6b95a207
KH		 6158 spin_unlock_irqrestore(&dev->event_lock, flags);
6159
05394f39 6160 obj = work->old_fb_obj;
d9e86c0e 6161
e59f2bac 6162 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6163 &obj->pending_flip.counter);
6164 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6165 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6166
6b95a207 6167 schedule_work(&work->work);
e5510fac
JB		 6168
6169 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6170}
6171
1afe3e9d
JB		 6172void intel_finish_page_flip(struct drm_device *dev, int pipe)
6173{
6174 drm_i915_private_t *dev_priv = dev->dev_private;
6175 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6176
49b14a5c 6177 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6178}
6179
6180void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6181{
6182 drm_i915_private_t *dev_priv = dev->dev_private;
6183 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6184
49b14a5c 6185 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6186}
6187
6b95a207
KH		 6188void intel_prepare_page_flip(struct drm_device *dev, int plane)
6189{
6190 drm_i915_private_t *dev_priv = dev->dev_private;
6191 struct intel_crtc *intel_crtc =
6192 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6193 unsigned long flags;
6194
6195 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6196 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6197 if ((++intel_crtc->unpin_work->pending) > 1)
6198 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6199 } else {
6200 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6201 }
6b95a207
KH		 6202 spin_unlock_irqrestore(&dev->event_lock, flags);
6203}
6204
8c9f3aaf
JB		 6205static int intel_gen2_queue_flip(struct drm_device *dev,
6206 struct drm_crtc *crtc,
6207 struct drm_framebuffer *fb,
6208 struct drm_i915_gem_object *obj)
6209{
6210 struct drm_i915_private *dev_priv = dev->dev_private;
6211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6212 u32 flip_mask;
6d90c952 6213 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6214 int ret;
6215
6d90c952 6216 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6217 if (ret)
83d4092b 6218 goto err;
8c9f3aaf 6219
6d90c952 6220 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6221 if (ret)
83d4092b 6222 goto err_unpin;
8c9f3aaf
JB		 6223
6224 /* Can't queue multiple flips, so wait for the previous
6225 * one to finish before executing the next.
6226 */
6227 if (intel_crtc->plane)
6228 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6229 else
6230 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6231 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6232 intel_ring_emit(ring, MI_NOOP);
6233 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6234 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6235 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6236 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6237 intel_ring_emit(ring, 0); /* aux display base address, unused */
6238 intel_ring_advance(ring);
83d4092b
CW		 6239 return 0;
6240
6241err_unpin:
6242 intel_unpin_fb_obj(obj);
6243err:
8c9f3aaf
JB		 6244 return ret;
6245}
6246
6247static int intel_gen3_queue_flip(struct drm_device *dev,
6248 struct drm_crtc *crtc,
6249 struct drm_framebuffer *fb,
6250 struct drm_i915_gem_object *obj)
6251{
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6254 u32 flip_mask;
6d90c952 6255 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6256 int ret;
6257
6d90c952 6258 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6259 if (ret)
83d4092b 6260 goto err;
8c9f3aaf 6261
6d90c952 6262 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6263 if (ret)
83d4092b 6264 goto err_unpin;
8c9f3aaf
JB		 6265
6266 if (intel_crtc->plane)
6267 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6268 else
6269 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6270 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6271 intel_ring_emit(ring, MI_NOOP);
6272 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6273 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6274 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6275 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6276 intel_ring_emit(ring, MI_NOOP);
6277
6278 intel_ring_advance(ring);
83d4092b
CW		 6279 return 0;
6280
6281err_unpin:
6282 intel_unpin_fb_obj(obj);
6283err:
8c9f3aaf
JB		 6284 return ret;
6285}
6286
6287static int intel_gen4_queue_flip(struct drm_device *dev,
6288 struct drm_crtc *crtc,
6289 struct drm_framebuffer *fb,
6290 struct drm_i915_gem_object *obj)
6291{
6292 struct drm_i915_private *dev_priv = dev->dev_private;
6293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6294 uint32_t pf, pipesrc;
6d90c952 6295 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6296 int ret;
6297
6d90c952 6298 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6299 if (ret)
83d4092b 6300 goto err;
8c9f3aaf 6301
6d90c952 6302 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6303 if (ret)
83d4092b 6304 goto err_unpin;
8c9f3aaf
JB		 6305
6306 /* i965+ uses the linear or tiled offsets from the
6307 * Display Registers (which do not change across a page-flip)
6308 * so we need only reprogram the base address.
6309 */
6d90c952
DV		 6310 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6311 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6312 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6313 intel_ring_emit(ring,
6314 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6315 obj->tiling_mode);
8c9f3aaf
JB		 6316
6317 /* XXX Enabling the panel-fitter across page-flip is so far
6318 * untested on non-native modes, so ignore it for now.
6319 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6320 */
6321 pf = 0;
6322 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6323 intel_ring_emit(ring, pf | pipesrc);
6324 intel_ring_advance(ring);
83d4092b
CW		 6325 return 0;
6326
6327err_unpin:
6328 intel_unpin_fb_obj(obj);
6329err:
8c9f3aaf
JB		 6330 return ret;
6331}
6332
6333static int intel_gen6_queue_flip(struct drm_device *dev,
6334 struct drm_crtc *crtc,
6335 struct drm_framebuffer *fb,
6336 struct drm_i915_gem_object *obj)
6337{
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6340 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6341 uint32_t pf, pipesrc;
6342 int ret;
6343
6d90c952 6344 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6345 if (ret)
83d4092b 6346 goto err;
8c9f3aaf 6347
6d90c952 6348 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6349 if (ret)
83d4092b 6350 goto err_unpin;
8c9f3aaf 6351
6d90c952
DV		 6352 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6353 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6354 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6355 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6356
dc257cf1
DV		 6357 /* Contrary to the suggestions in the documentation,
6358 * "Enable Panel Fitter" does not seem to be required when page
6359 * flipping with a non-native mode, and worse causes a normal
6360 * modeset to fail.
6361 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6362 */
6363 pf = 0;
8c9f3aaf 6364 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6365 intel_ring_emit(ring, pf | pipesrc);
6366 intel_ring_advance(ring);
83d4092b
CW		 6367 return 0;
6368
6369err_unpin:
6370 intel_unpin_fb_obj(obj);
6371err:
8c9f3aaf
JB		 6372 return ret;
6373}
6374
7c9017e5
JB		 6375/*
6376 * On gen7 we currently use the blit ring because (in early silicon at least)
6377 * the render ring doesn't give us interrpts for page flip completion, which
6378 * means clients will hang after the first flip is queued. Fortunately the
6379 * blit ring generates interrupts properly, so use it instead.
6380 */
6381static int intel_gen7_queue_flip(struct drm_device *dev,
6382 struct drm_crtc *crtc,
6383 struct drm_framebuffer *fb,
6384 struct drm_i915_gem_object *obj)
6385{
6386 struct drm_i915_private *dev_priv = dev->dev_private;
6387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6389 uint32_t plane_bit = 0;
7c9017e5
JB		 6390 int ret;
6391
6392 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6393 if (ret)
83d4092b 6394 goto err;
7c9017e5 6395
cb05d8de
DV		 6396 switch(intel_crtc->plane) {
6397 case PLANE_A:
6398 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6399 break;
6400 case PLANE_B:
6401 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6402 break;
6403 case PLANE_C:
6404 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6405 break;
6406 default:
6407 WARN_ONCE(1, "unknown plane in flip command\n");
6408 ret = -ENODEV;
ab3951eb 6409 goto err_unpin;
cb05d8de
DV		 6410 }
6411
7c9017e5
JB		 6412 ret = intel_ring_begin(ring, 4);
6413 if (ret)
83d4092b 6414 goto err_unpin;
7c9017e5 6415
cb05d8de 6416 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6417 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6418 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6419 intel_ring_emit(ring, (MI_NOOP));
6420 intel_ring_advance(ring);
83d4092b
CW		 6421 return 0;
6422
6423err_unpin:
6424 intel_unpin_fb_obj(obj);
6425err:
7c9017e5
JB		 6426 return ret;
6427}
6428
8c9f3aaf
JB		 6429static int intel_default_queue_flip(struct drm_device *dev,
6430 struct drm_crtc *crtc,
6431 struct drm_framebuffer *fb,
6432 struct drm_i915_gem_object *obj)
6433{
6434 return -ENODEV;
6435}
6436
6b95a207
KH		 6437static int intel_crtc_page_flip(struct drm_crtc *crtc,
6438 struct drm_framebuffer *fb,
6439 struct drm_pending_vblank_event *event)
6440{
6441 struct drm_device *dev = crtc->dev;
6442 struct drm_i915_private *dev_priv = dev->dev_private;
6443 struct intel_framebuffer *intel_fb;
05394f39 6444 struct drm_i915_gem_object *obj;
6b95a207
KH		 6445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6446 struct intel_unpin_work *work;
8c9f3aaf 6447 unsigned long flags;
52e68630 6448 int ret;
6b95a207 6449
e6a595d2
VS		 6450 /* Can't change pixel format via MI display flips. */
6451 if (fb->pixel_format != crtc->fb->pixel_format)
6452 return -EINVAL;
6453
6454 /*
6455 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6456 * Note that pitch changes could also affect these register.
6457 */
6458 if (INTEL_INFO(dev)->gen > 3 &&
6459 (fb->offsets[0] != crtc->fb->offsets[0] ||
6460 fb->pitches[0] != crtc->fb->pitches[0]))
6461 return -EINVAL;
6462
6b95a207
KH		 6463 work = kzalloc(sizeof *work, GFP_KERNEL);
6464 if (work == NULL)
6465 return -ENOMEM;
6466
6b95a207
KH		 6467 work->event = event;
6468 work->dev = crtc->dev;
6469 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6470 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6471 INIT_WORK(&work->work, intel_unpin_work_fn);
6472
7317c75e
JB		 6473 ret = drm_vblank_get(dev, intel_crtc->pipe);
6474 if (ret)
6475 goto free_work;
6476
6b95a207
KH		 6477 /* We borrow the event spin lock for protecting unpin_work */
6478 spin_lock_irqsave(&dev->event_lock, flags);
6479 if (intel_crtc->unpin_work) {
6480 spin_unlock_irqrestore(&dev->event_lock, flags);
6481 kfree(work);
7317c75e 6482 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6483
6484 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6485 return -EBUSY;
6486 }
6487 intel_crtc->unpin_work = work;
6488 spin_unlock_irqrestore(&dev->event_lock, flags);
6489
6490 intel_fb = to_intel_framebuffer(fb);
6491 obj = intel_fb->obj;
6492
79158103
CW		 6493 ret = i915_mutex_lock_interruptible(dev);
6494 if (ret)
6495 goto cleanup;
6b95a207 6496
75dfca80 6497 /* Reference the objects for the scheduled work. */
05394f39
CW		 6498 drm_gem_object_reference(&work->old_fb_obj->base);
6499 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6500
6501 crtc->fb = fb;
96b099fd 6502
e1f99ce6 6503 work->pending_flip_obj = obj;
e1f99ce6 6504
4e5359cd
SF		 6505 work->enable_stall_check = true;
6506
e1f99ce6
CW		 6507 /* Block clients from rendering to the new back buffer until
6508 * the flip occurs and the object is no longer visible.
6509 */
05394f39 6510 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6511
8c9f3aaf
JB		 6512 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6513 if (ret)
6514 goto cleanup_pending;
6b95a207 6515
7782de3b 6516 intel_disable_fbc(dev);
f047e395 6517 intel_mark_fb_busy(obj);
6b95a207
KH		 6518 mutex_unlock(&dev->struct_mutex);
6519
e5510fac
JB		 6520 trace_i915_flip_request(intel_crtc->plane, obj);
6521
6b95a207 6522 return 0;
96b099fd 6523
8c9f3aaf
JB		 6524cleanup_pending:
6525 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6526 drm_gem_object_unreference(&work->old_fb_obj->base);
6527 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6528 mutex_unlock(&dev->struct_mutex);
6529
79158103 6530cleanup:
96b099fd
CW		 6531 spin_lock_irqsave(&dev->event_lock, flags);
6532 intel_crtc->unpin_work = NULL;
6533 spin_unlock_irqrestore(&dev->event_lock, flags);
6534
7317c75e
JB		 6535 drm_vblank_put(dev, intel_crtc->pipe);
6536free_work:
96b099fd
CW		 6537 kfree(work);
6538
6539 return ret;
6b95a207
KH		 6540}
6541
47f1c6c9
CW		 6542static void intel_sanitize_modesetting(struct drm_device *dev,
6543 int pipe, int plane)
6544{
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546 u32 reg, val;
a9dcf84b 6547 int i;
47f1c6c9 6548
f47166d2 6549 /* Clear any frame start delays used for debugging left by the BIOS */
a9dcf84b
DV		 6550 for_each_pipe(i) {
6551 reg = PIPECONF(i);
f47166d2
CW		 6552 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6553 }
6554
47f1c6c9
CW		 6555 if (HAS_PCH_SPLIT(dev))
6556 return;
6557
6558 /* Who knows what state these registers were left in by the BIOS or
6559 * grub?
6560 *
6561 * If we leave the registers in a conflicting state (e.g. with the
6562 * display plane reading from the other pipe than the one we intend
6563 * to use) then when we attempt to teardown the active mode, we will
6564 * not disable the pipes and planes in the correct order -- leaving
6565 * a plane reading from a disabled pipe and possibly leading to
6566 * undefined behaviour.
6567 */
6568
6569 reg = DSPCNTR(plane);
6570 val = I915_READ(reg);
6571
6572 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6573 return;
6574 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6575 return;
6576
6577 /* This display plane is active and attached to the other CPU pipe. */
6578 pipe = !pipe;
6579
6580 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6581 intel_disable_plane(dev_priv, plane, pipe);
6582 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6583}
79e53945 6584
f6e5b160
CW		 6585static void intel_crtc_reset(struct drm_crtc *crtc)
6586{
6587 struct drm_device *dev = crtc->dev;
6588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6589
6590 /* Reset flags back to the 'unknown' status so that they
6591 * will be correctly set on the initial modeset.
6592 */
6593 intel_crtc->dpms_mode = -1;
6594
6595 /* We need to fix up any BIOS configuration that conflicts with
6596 * our expectations.
6597 */
6598 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6599}
6600
6601static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6602 .mode_fixup = intel_crtc_mode_fixup,
6603 .mode_set = intel_crtc_mode_set,
6604 .mode_set_base = intel_pipe_set_base,
6605 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6606 .load_lut = intel_crtc_load_lut,
6607 .disable = intel_crtc_disable,
6608};
6609
6610static const struct drm_crtc_funcs intel_crtc_funcs = {
6611 .reset = intel_crtc_reset,
6612 .cursor_set = intel_crtc_cursor_set,
6613 .cursor_move = intel_crtc_cursor_move,
6614 .gamma_set = intel_crtc_gamma_set,
6615 .set_config = drm_crtc_helper_set_config,
6616 .destroy = intel_crtc_destroy,
6617 .page_flip = intel_crtc_page_flip,
6618};
6619
ee7b9f93
JB		 6620static void intel_pch_pll_init(struct drm_device *dev)
6621{
6622 drm_i915_private_t *dev_priv = dev->dev_private;
6623 int i;
6624
6625 if (dev_priv->num_pch_pll == 0) {
6626 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6627 return;
6628 }
6629
6630 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6631 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6632 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6633 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6634 }
6635}
6636
b358d0a6 6637static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6638{
22fd0fab 6639 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6640 struct intel_crtc *intel_crtc;
6641 int i;
6642
6643 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6644 if (intel_crtc == NULL)
6645 return;
6646
6647 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6648
6649 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6650 for (i = 0; i < 256; i++) {
6651 intel_crtc->lut_r[i] = i;
6652 intel_crtc->lut_g[i] = i;
6653 intel_crtc->lut_b[i] = i;
6654 }
6655
80824003
JB		 6656 /* Swap pipes & planes for FBC on pre-965 */
6657 intel_crtc->pipe = pipe;
6658 intel_crtc->plane = pipe;
e2e767ab 6659 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6660 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6661 intel_crtc->plane = !pipe;
80824003
JB		 6662 }
6663
22fd0fab
JB		 6664 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6665 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6666 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6667 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6668
5d1d0cc8 6669 intel_crtc_reset(&intel_crtc->base);
04dbff52 6670 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6671 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 6672
eae307a5
DV		 6673 intel_helper_funcs.prepare = dev_priv->display.crtc_disable;
6674 intel_helper_funcs.commit = dev_priv->display.crtc_enable;
7e7d76c3 6675
79e53945 6676 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 6677}
6678
08d7b3d1 6679int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6680 struct drm_file *file)
08d7b3d1 6681{
08d7b3d1 6682 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6683 struct drm_mode_object *drmmode_obj;
6684 struct intel_crtc *crtc;
08d7b3d1 6685
1cff8f6b
DV		 6686 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6687 return -ENODEV;
08d7b3d1 6688
c05422d5
DV		 6689 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6690 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6691
c05422d5 6692 if (!drmmode_obj) {
08d7b3d1
CW		 6693 DRM_ERROR("no such CRTC id\n");
6694 return -EINVAL;
6695 }
6696
c05422d5
DV		 6697 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6698 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6699
c05422d5 6700 return 0;
08d7b3d1
CW		 6701}
6702
66a9278e 6703static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 6704{
66a9278e
DV		 6705 struct drm_device *dev = encoder->base.dev;
6706 struct intel_encoder *source_encoder;
79e53945 6707 int index_mask = 0;
79e53945
JB		 6708 int entry = 0;
6709
66a9278e
DV		 6710 list_for_each_entry(source_encoder,
6711 &dev->mode_config.encoder_list, base.head) {
6712
6713 if (encoder == source_encoder)
79e53945 6714 index_mask |= (1 << entry);
66a9278e
DV		 6715
6716 /* Intel hw has only one MUX where enocoders could be cloned. */
6717 if (encoder->cloneable && source_encoder->cloneable)
6718 index_mask |= (1 << entry);
6719
79e53945
JB		 6720 entry++;
6721 }
4ef69c7a 6722
79e53945
JB		 6723 return index_mask;
6724}
6725
4d302442
CW		 6726static bool has_edp_a(struct drm_device *dev)
6727{
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729
6730 if (!IS_MOBILE(dev))
6731 return false;
6732
6733 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6734 return false;
6735
6736 if (IS_GEN5(dev) &&
6737 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6738 return false;
6739
6740 return true;
6741}
6742
79e53945
JB		 6743static void intel_setup_outputs(struct drm_device *dev)
6744{
725e30ad 6745 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6746 struct intel_encoder *encoder;
cb0953d7 6747 bool dpd_is_edp = false;
f3cfcba6 6748 bool has_lvds;
79e53945 6749
f3cfcba6 6750 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6751 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6752 /* disable the panel fitter on everything but LVDS */
6753 I915_WRITE(PFIT_CONTROL, 0);
6754 }
79e53945 6755
bad720ff 6756 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6757 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6758
4d302442 6759 if (has_edp_a(dev))
ab9d7c30 6760 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 6761
cb0953d7 6762 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 6763 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 6764 }
6765
6766 intel_crt_init(dev);
6767
0e72a5b5
ED		 6768 if (IS_HASWELL(dev)) {
6769 int found;
6770
6771 /* Haswell uses DDI functions to detect digital outputs */
6772 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6773 /* DDI A only supports eDP */
6774 if (found)
6775 intel_ddi_init(dev, PORT_A);
6776
6777 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6778 * register */
6779 found = I915_READ(SFUSE_STRAP);
6780
6781 if (found & SFUSE_STRAP_DDIB_DETECTED)
6782 intel_ddi_init(dev, PORT_B);
6783 if (found & SFUSE_STRAP_DDIC_DETECTED)
6784 intel_ddi_init(dev, PORT_C);
6785 if (found & SFUSE_STRAP_DDID_DETECTED)
6786 intel_ddi_init(dev, PORT_D);
6787 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 6788 int found;
6789
30ad48b7 6790 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6791 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6792 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 6793 if (!found)
08d644ad 6794 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 6795 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 6796 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 6797 }
6798
6799 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 6800 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 6801
b708a1d5 6802 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 6803 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 6804
5eb08b69 6805 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 6806 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 6807
cb0953d7 6808 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 6809 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 6810 } else if (IS_VALLEYVIEW(dev)) {
6811 int found;
6812
6813 if (I915_READ(SDVOB) & PORT_DETECTED) {
6814 /* SDVOB multiplex with HDMIB */
6815 found = intel_sdvo_init(dev, SDVOB, true);
6816 if (!found)
08d644ad 6817 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 6818 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 6819 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 6820 }
6821
6822 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 6823 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 6824
4a87d65d
JB		 6825 /* Shares lanes with HDMI on SDVOC */
6826 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 6827 intel_dp_init(dev, DP_C, PORT_C);
103a196f 6828 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6829 bool found = false;
7d57382e 6830
725e30ad 6831 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6832 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6833 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6834 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6835 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 6836 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 6837 }
27185ae1 6838
b01f2c3a
JB		 6839 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6840 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 6841 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 6842 }
725e30ad 6843 }
13520b05
KH		 6844
6845 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6846
b01f2c3a
JB		 6847 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6848 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6849 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6850 }
27185ae1
ML		 6851
6852 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6853
b01f2c3a
JB		 6854 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6855 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 6856 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 6857 }
6858 if (SUPPORTS_INTEGRATED_DP(dev)) {
6859 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 6860 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 6861 }
725e30ad 6862 }
27185ae1 6863
b01f2c3a
JB		 6864 if (SUPPORTS_INTEGRATED_DP(dev) &&
6865 (I915_READ(DP_D) & DP_DETECTED)) {
6866 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 6867 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 6868 }
bad720ff 6869 } else if (IS_GEN2(dev))
79e53945
JB		 6870 intel_dvo_init(dev);
6871
103a196f 6872 if (SUPPORTS_TV(dev))
79e53945
JB		 6873 intel_tv_init(dev);
6874
4ef69c7a
CW		 6875 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6876 encoder->base.possible_crtcs = encoder->crtc_mask;
6877 encoder->base.possible_clones =
66a9278e 6878 intel_encoder_clones(encoder);
79e53945 6879 }
47356eb6 6880
2c7111db
CW		 6881 /* disable all the possible outputs/crtcs before entering KMS mode */
6882 drm_helper_disable_unused_functions(dev);
9fb526db 6883
40579abe 6884 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 6885 ironlake_init_pch_refclk(dev);
79e53945
JB		 6886}
6887
6888static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6889{
6890 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6891
6892 drm_framebuffer_cleanup(fb);
05394f39 6893 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6894
6895 kfree(intel_fb);
6896}
6897
6898static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6899 struct drm_file *file,
79e53945
JB		 6900 unsigned int *handle)
6901{
6902 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6903 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6904
05394f39 6905 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6906}
6907
6908static const struct drm_framebuffer_funcs intel_fb_funcs = {
6909 .destroy = intel_user_framebuffer_destroy,
6910 .create_handle = intel_user_framebuffer_create_handle,
6911};
6912
38651674
DA		 6913int intel_framebuffer_init(struct drm_device *dev,
6914 struct intel_framebuffer *intel_fb,
308e5bcb 6915 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6916 struct drm_i915_gem_object *obj)
79e53945 6917{
79e53945
JB		 6918 int ret;
6919
05394f39 6920 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6921 return -EINVAL;
6922
308e5bcb 6923 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6924 return -EINVAL;
6925
308e5bcb 6926 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6927 case DRM_FORMAT_RGB332:
6928 case DRM_FORMAT_RGB565:
6929 case DRM_FORMAT_XRGB8888:
b250da79 6930 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6931 case DRM_FORMAT_ARGB8888:
6932 case DRM_FORMAT_XRGB2101010:
6933 case DRM_FORMAT_ARGB2101010:
308e5bcb 6934 /* RGB formats are common across chipsets */
b5626747 6935 break;
04b3924d
VS		 6936 case DRM_FORMAT_YUYV:
6937 case DRM_FORMAT_UYVY:
6938 case DRM_FORMAT_YVYU:
6939 case DRM_FORMAT_VYUY:
57cd6508
CW		 6940 break;
6941 default:
aca25848
ED		 6942 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6943 mode_cmd->pixel_format);
57cd6508
CW		 6944 return -EINVAL;
6945 }
6946
79e53945
JB		 6947 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6948 if (ret) {
6949 DRM_ERROR("framebuffer init failed %d\n", ret);
6950 return ret;
6951 }
6952
6953 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6954 intel_fb->obj = obj;
79e53945
JB		 6955 return 0;
6956}
6957
79e53945
JB		 6958static struct drm_framebuffer *
6959intel_user_framebuffer_create(struct drm_device *dev,
6960 struct drm_file *filp,
308e5bcb 6961 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6962{
05394f39 6963 struct drm_i915_gem_object *obj;
79e53945 6964
308e5bcb
JB		 6965 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6966 mode_cmd->handles[0]));
c8725226 6967 if (&obj->base == NULL)
cce13ff7 6968 return ERR_PTR(-ENOENT);
79e53945 6969
d2dff872 6970 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6971}
6972
79e53945 6973static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6974 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6975 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6976};
6977
e70236a8
JB		 6978/* Set up chip specific display functions */
6979static void intel_init_display(struct drm_device *dev)
6980{
6981 struct drm_i915_private *dev_priv = dev->dev_private;
6982
6983 /* We always want a DPMS function */
f564048e 6984 if (HAS_PCH_SPLIT(dev)) {
f564048e 6985 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 6986 dev_priv->display.crtc_enable = ironlake_crtc_enable;
6987 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 6988 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6989 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6990 } else {
f564048e 6991 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 6992 dev_priv->display.crtc_enable = i9xx_crtc_enable;
6993 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 6994 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6995 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6996 }
e70236a8 6997
e70236a8 6998 /* Returns the core display clock speed */
25eb05fc
JB		 6999 if (IS_VALLEYVIEW(dev))
7000 dev_priv->display.get_display_clock_speed =
7001 valleyview_get_display_clock_speed;
7002 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7003 dev_priv->display.get_display_clock_speed =
7004 i945_get_display_clock_speed;
7005 else if (IS_I915G(dev))
7006 dev_priv->display.get_display_clock_speed =
7007 i915_get_display_clock_speed;
f2b115e6 7008 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7009 dev_priv->display.get_display_clock_speed =
7010 i9xx_misc_get_display_clock_speed;
7011 else if (IS_I915GM(dev))
7012 dev_priv->display.get_display_clock_speed =
7013 i915gm_get_display_clock_speed;
7014 else if (IS_I865G(dev))
7015 dev_priv->display.get_display_clock_speed =
7016 i865_get_display_clock_speed;
f0f8a9ce 7017 else if (IS_I85X(dev))
e70236a8
JB		 7018 dev_priv->display.get_display_clock_speed =
7019 i855_get_display_clock_speed;
7020 else /* 852, 830 */
7021 dev_priv->display.get_display_clock_speed =
7022 i830_get_display_clock_speed;
7023
7f8a8569 7024 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7025 if (IS_GEN5(dev)) {
674cf967 7026 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7027 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7028 } else if (IS_GEN6(dev)) {
674cf967 7029 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7030 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7031 } else if (IS_IVYBRIDGE(dev)) {
7032 /* FIXME: detect B0+ stepping and use auto training */
7033 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7034 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7035 } else if (IS_HASWELL(dev)) {
7036 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7037 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7038 } else
7039 dev_priv->display.update_wm = NULL;
6067aaea 7040 } else if (IS_G4X(dev)) {
e0dac65e 7041 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7042 }
8c9f3aaf
JB		 7043
7044 /* Default just returns -ENODEV to indicate unsupported */
7045 dev_priv->display.queue_flip = intel_default_queue_flip;
7046
7047 switch (INTEL_INFO(dev)->gen) {
7048 case 2:
7049 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7050 break;
7051
7052 case 3:
7053 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7054 break;
7055
7056 case 4:
7057 case 5:
7058 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7059 break;
7060
7061 case 6:
7062 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7063 break;
7c9017e5
JB		 7064 case 7:
7065 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7066 break;
8c9f3aaf 7067 }
e70236a8
JB		 7068}
7069
b690e96c
JB		 7070/*
7071 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7072 * resume, or other times. This quirk makes sure that's the case for
7073 * affected systems.
7074 */
0206e353 7075static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7076{
7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078
7079 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7080 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7081}
7082
435793df
KP		 7083/*
7084 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7085 */
7086static void quirk_ssc_force_disable(struct drm_device *dev)
7087{
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7090 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7091}
7092
4dca20ef 7093/*
5a15ab5b
CE		 7094 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7095 * brightness value
4dca20ef
CE		 7096 */
7097static void quirk_invert_brightness(struct drm_device *dev)
7098{
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7101 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7102}
7103
b690e96c
JB		 7104struct intel_quirk {
7105 int device;
7106 int subsystem_vendor;
7107 int subsystem_device;
7108 void (*hook)(struct drm_device *dev);
7109};
7110
c43b5634 7111static struct intel_quirk intel_quirks[] = {
b690e96c 7112 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7113 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7114
b690e96c
JB		 7115 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7116 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7117
b690e96c
JB		 7118 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7119 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7120
7121 /* 855 & before need to leave pipe A & dpll A up */
7122 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7123 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7124 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7125
7126 /* Lenovo U160 cannot use SSC on LVDS */
7127 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7128
7129 /* Sony Vaio Y cannot use SSC on LVDS */
7130 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7131
7132 /* Acer Aspire 5734Z must invert backlight brightness */
7133 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7134};
7135
7136static void intel_init_quirks(struct drm_device *dev)
7137{
7138 struct pci_dev *d = dev->pdev;
7139 int i;
7140
7141 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7142 struct intel_quirk *q = &intel_quirks[i];
7143
7144 if (d->device == q->device &&
7145 (d->subsystem_vendor == q->subsystem_vendor ||
7146 q->subsystem_vendor == PCI_ANY_ID) &&
7147 (d->subsystem_device == q->subsystem_device ||
7148 q->subsystem_device == PCI_ANY_ID))
7149 q->hook(dev);
7150 }
7151}
7152
9cce37f4
JB		 7153/* Disable the VGA plane that we never use */
7154static void i915_disable_vga(struct drm_device *dev)
7155{
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 u8 sr1;
7158 u32 vga_reg;
7159
7160 if (HAS_PCH_SPLIT(dev))
7161 vga_reg = CPU_VGACNTRL;
7162 else
7163 vga_reg = VGACNTRL;
7164
7165 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7166 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7167 sr1 = inb(VGA_SR_DATA);
7168 outb(sr1 | 1<<5, VGA_SR_DATA);
7169 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7170 udelay(300);
7171
7172 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7173 POSTING_READ(vga_reg);
7174}
7175
f817586c
DV		 7176void intel_modeset_init_hw(struct drm_device *dev)
7177{
0232e927
ED		 7178 /* We attempt to init the necessary power wells early in the initialization
7179 * time, so the subsystems that expect power to be enabled can work.
7180 */
7181 intel_init_power_wells(dev);
7182
a8f78b58
ED		 7183 intel_prepare_ddi(dev);
7184
f817586c
DV		 7185 intel_init_clock_gating(dev);
7186
79f5b2c7 7187 mutex_lock(&dev->struct_mutex);
8090c6b9 7188 intel_enable_gt_powersave(dev);
79f5b2c7 7189 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7190}
7191
79e53945
JB		 7192void intel_modeset_init(struct drm_device *dev)
7193{
652c393a 7194 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7195 int i, ret;
79e53945
JB		 7196
7197 drm_mode_config_init(dev);
7198
7199 dev->mode_config.min_width = 0;
7200 dev->mode_config.min_height = 0;
7201
019d96cb
DA		 7202 dev->mode_config.preferred_depth = 24;
7203 dev->mode_config.prefer_shadow = 1;
7204
e6ecefaa 7205 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7206
b690e96c
JB		 7207 intel_init_quirks(dev);
7208
1fa61106
ED		 7209 intel_init_pm(dev);
7210
e70236a8
JB		 7211 intel_init_display(dev);
7212
a6c45cf0
CW		 7213 if (IS_GEN2(dev)) {
7214 dev->mode_config.max_width = 2048;
7215 dev->mode_config.max_height = 2048;
7216 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7217 dev->mode_config.max_width = 4096;
7218 dev->mode_config.max_height = 4096;
79e53945 7219 } else {
a6c45cf0
CW		 7220 dev->mode_config.max_width = 8192;
7221 dev->mode_config.max_height = 8192;
79e53945 7222 }
dd2757f8 7223 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7224
28c97730 7225 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7226 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7227
a3524f1b 7228 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7229 intel_crtc_init(dev, i);
00c2064b
JB		 7230 ret = intel_plane_init(dev, i);
7231 if (ret)
7232 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7233 }
7234
ee7b9f93
JB		 7235 intel_pch_pll_init(dev);
7236
9cce37f4
JB		 7237 /* Just disable it once at startup */
7238 i915_disable_vga(dev);
79e53945 7239 intel_setup_outputs(dev);
2c7111db
CW		 7240}
7241
7242void intel_modeset_gem_init(struct drm_device *dev)
7243{
1833b134 7244 intel_modeset_init_hw(dev);
02e792fb
DV		 7245
7246 intel_setup_overlay(dev);
79e53945
JB		 7247}
7248
7249void intel_modeset_cleanup(struct drm_device *dev)
7250{
652c393a
JB		 7251 struct drm_i915_private *dev_priv = dev->dev_private;
7252 struct drm_crtc *crtc;
7253 struct intel_crtc *intel_crtc;
7254
f87ea761 7255 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7256 mutex_lock(&dev->struct_mutex);
7257
723bfd70
JB		 7258 intel_unregister_dsm_handler();
7259
7260
652c393a
JB		 7261 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7262 /* Skip inactive CRTCs */
7263 if (!crtc->fb)
7264 continue;
7265
7266 intel_crtc = to_intel_crtc(crtc);
3dec0095 7267 intel_increase_pllclock(crtc);
652c393a
JB		 7268 }
7269
973d04f9 7270 intel_disable_fbc(dev);
e70236a8 7271
8090c6b9 7272 intel_disable_gt_powersave(dev);
0cdab21f 7273
930ebb46
DV		 7274 ironlake_teardown_rc6(dev);
7275
57f350b6
JB		 7276 if (IS_VALLEYVIEW(dev))
7277 vlv_init_dpio(dev);
7278
69341a5e
KH		 7279 mutex_unlock(&dev->struct_mutex);
7280
6c0d9350
DV		 7281 /* Disable the irq before mode object teardown, for the irq might
7282 * enqueue unpin/hotplug work. */
7283 drm_irq_uninstall(dev);
7284 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 7285 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 7286
1630fe75
CW		 7287 /* flush any delayed tasks or pending work */
7288 flush_scheduled_work();
7289
79e53945
JB		 7290 drm_mode_config_cleanup(dev);
7291}
7292
f1c79df3
ZW		 7293/*
7294 * Return which encoder is currently attached for connector.
7295 */
df0e9248 7296struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7297{
df0e9248
CW		 7298 return &intel_attached_encoder(connector)->base;
7299}
f1c79df3 7300
df0e9248
CW		 7301void intel_connector_attach_encoder(struct intel_connector *connector,
7302 struct intel_encoder *encoder)
7303{
7304 connector->encoder = encoder;
7305 drm_mode_connector_attach_encoder(&connector->base,
7306 &encoder->base);
79e53945 7307}
28d52043
DA		 7308
7309/*
7310 * set vga decode state - true == enable VGA decode
7311 */
7312int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7313{
7314 struct drm_i915_private *dev_priv = dev->dev_private;
7315 u16 gmch_ctrl;
7316
7317 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7318 if (state)
7319 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7320 else
7321 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7322 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7323 return 0;
7324}
c4a1d9e4
CW		 7325
7326#ifdef CONFIG_DEBUG_FS
7327#include <linux/seq_file.h>
7328
7329struct intel_display_error_state {
7330 struct intel_cursor_error_state {
7331 u32 control;
7332 u32 position;
7333 u32 base;
7334 u32 size;
52331309 7335 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 7336
7337 struct intel_pipe_error_state {
7338 u32 conf;
7339 u32 source;
7340
7341 u32 htotal;
7342 u32 hblank;
7343 u32 hsync;
7344 u32 vtotal;
7345 u32 vblank;
7346 u32 vsync;
52331309 7347 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 7348
7349 struct intel_plane_error_state {
7350 u32 control;
7351 u32 stride;
7352 u32 size;
7353 u32 pos;
7354 u32 addr;
7355 u32 surface;
7356 u32 tile_offset;
52331309 7357 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 7358};
7359
7360struct intel_display_error_state *
7361intel_display_capture_error_state(struct drm_device *dev)
7362{
0206e353 7363 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7364 struct intel_display_error_state *error;
7365 int i;
7366
7367 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7368 if (error == NULL)
7369 return NULL;
7370
52331309 7371 for_each_pipe(i) {
c4a1d9e4
CW		 7372 error->cursor[i].control = I915_READ(CURCNTR(i));
7373 error->cursor[i].position = I915_READ(CURPOS(i));
7374 error->cursor[i].base = I915_READ(CURBASE(i));
7375
7376 error->plane[i].control = I915_READ(DSPCNTR(i));
7377 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7378 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7379 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7380 error->plane[i].addr = I915_READ(DSPADDR(i));
7381 if (INTEL_INFO(dev)->gen >= 4) {
7382 error->plane[i].surface = I915_READ(DSPSURF(i));
7383 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7384 }
7385
7386 error->pipe[i].conf = I915_READ(PIPECONF(i));
7387 error->pipe[i].source = I915_READ(PIPESRC(i));
7388 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7389 error->pipe[i].hblank = I915_READ(HBLANK(i));
7390 error->pipe[i].hsync = I915_READ(HSYNC(i));
7391 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7392 error->pipe[i].vblank = I915_READ(VBLANK(i));
7393 error->pipe[i].vsync = I915_READ(VSYNC(i));
7394 }
7395
7396 return error;
7397}
7398
7399void
7400intel_display_print_error_state(struct seq_file *m,
7401 struct drm_device *dev,
7402 struct intel_display_error_state *error)
7403{
52331309 7404 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7405 int i;
7406
52331309
DL		 7407 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7408 for_each_pipe(i) {
c4a1d9e4
CW		 7409 seq_printf(m, "Pipe [%d]:\n", i);
7410 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7411 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7412 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7413 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7414 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7415 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7416 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7417 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7418
7419 seq_printf(m, "Plane [%d]:\n", i);
7420 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7421 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7422 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7423 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7424 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7425 if (INTEL_INFO(dev)->gen >= 4) {
7426 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7427 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7428 }
7429
7430 seq_printf(m, "Cursor [%d]:\n", i);
7431 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7432 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7433 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7434 }
7435}
7436#endif
Linux kernel - Deliverables
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