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drm/i915: Move DP port disable to post_disable for pch platforms
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
451 }
452
453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
488}
489
bf13e81b
JN		 490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
5ed12a19
DL		 664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq,
666 int send_bytes,
667 uint32_t aux_clock_divider)
668{
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
672
673 if (IS_GEN6(dev))
674 precharge = 3;
675 else
676 precharge = 5;
677
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
680 else
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
682
683 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 684 DP_AUX_CH_CTL_DONE |
5ed12a19 685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 687 timeout |
788d4433 688 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 692}
693
b84a1cf8
RV		 694static int
695intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
bc86625a 704 uint32_t aux_clock_divider;
b84a1cf8
RV		 705 int i, ret, recv_bytes;
706 uint32_t status;
5ed12a19 707 int try, clock = 0;
4e6b788c 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 709 bool vdd;
710
773538e8 711 pps_lock(intel_dp);
e39b999a 712
72c3500a
VS		 713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
1e0560e0 719 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 720
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
723 * deep sleep states.
724 */
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
726
727 intel_dp_check_edp(intel_dp);
5eb08b69 728
c67a470b
PZ		 729 intel_aux_display_runtime_get(dev_priv);
730
11bee43e
JB		 731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
ef04f00d 733 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
735 break;
736 msleep(1);
737 }
738
739 if (try == 3) {
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
741 I915_READ(ch_ctl));
9ee32fea
DV		 742 ret = -EBUSY;
743 goto out;
4f7f7b7e
CW		 744 }
745
46a5ae9f
PZ		 746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
748 ret = -E2BIG;
749 goto out;
750 }
751
ec5b01dd 752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
754 has_aux_irq,
755 send_bytes,
756 aux_clock_divider);
5ed12a19 757
bc86625a
CW		 758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
764
765 /* Send the command and wait for it to complete */
5ed12a19 766 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 767
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
769
770 /* Clear done status and any errors */
771 I915_WRITE(ch_ctl,
772 status |
773 DP_AUX_CH_CTL_DONE |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
776
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
779 continue;
780 if (status & DP_AUX_CH_CTL_DONE)
781 break;
782 }
4f7f7b7e 783 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 784 break;
785 }
786
a4fc5ed6 787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 789 ret = -EBUSY;
790 goto out;
a4fc5ed6
KP		 791 }
792
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
795 */
a5b3da54 796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 798 ret = -EIO;
799 goto out;
a5b3da54 800 }
1ae8c0a5
KP		 801
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
a5b3da54 804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 806 ret = -ETIMEDOUT;
807 goto out;
a4fc5ed6
KP		 808 }
809
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
0206e353 815
4f7f7b7e
CW		 816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
a4fc5ed6 819
9ee32fea
DV		 820 ret = recv_bytes;
821out:
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 823 intel_aux_display_runtime_put(dev_priv);
9ee32fea 824
884f19e9
JN		 825 if (vdd)
826 edp_panel_vdd_off(intel_dp, false);
827
773538e8 828 pps_unlock(intel_dp);
e39b999a 829
9ee32fea 830 return ret;
a4fc5ed6
KP		 831}
832
a6c8aff0
JN		 833#define BARE_ADDRESS_SIZE 3
834#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 835static ssize_t
836intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 837{
9d1a1031
JN		 838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
a4fc5ed6 841 int ret;
a4fc5ed6 842
9d1a1031
JN		 843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
46a5ae9f 847
9d1a1031
JN		 848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
a6c8aff0 851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 852 rxsize = 1;
f51a44b9 853
9d1a1031
JN		 854 if (WARN_ON(txsize > 20))
855 return -E2BIG;
a4fc5ed6 856
9d1a1031 857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 858
9d1a1031
JN		 859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
860 if (ret > 0) {
861 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 862
9d1a1031
JN		 863 /* Return payload size. */
864 ret = msg->size;
865 }
866 break;
46a5ae9f 867
9d1a1031
JN		 868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = msg->size + 1;
a4fc5ed6 872
9d1a1031
JN		 873 if (WARN_ON(rxsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031
JN		 876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
877 if (ret > 0) {
878 msg->reply = rxbuf[0] >> 4;
879 /*
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
882 *
883 * Return payload size.
884 */
885 ret--;
886 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 887 }
9d1a1031
JN		 888 break;
889
890 default:
891 ret = -EINVAL;
892 break;
a4fc5ed6 893 }
f51a44b9 894
9d1a1031 895 return ret;
a4fc5ed6
KP		 896}
897
9d1a1031
JN		 898static void
899intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
900{
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
0b99836f 904 const char *name = NULL;
ab2c0672
DA		 905 int ret;
906
33ad6626
JN		 907 switch (port) {
908 case PORT_A:
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 910 name = "DPDDC-A";
ab2c0672 911 break;
33ad6626
JN		 912 case PORT_B:
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 914 name = "DPDDC-B";
ab2c0672 915 break;
33ad6626
JN		 916 case PORT_C:
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 918 name = "DPDDC-C";
ab2c0672 919 break;
33ad6626
JN		 920 case PORT_D:
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 922 name = "DPDDC-D";
33ad6626
JN		 923 break;
924 default:
925 BUG();
ab2c0672
DA		 926 }
927
33ad6626
JN		 928 if (!HAS_DDI(dev))
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 930
0b99836f 931 intel_dp->aux.name = name;
9d1a1031
JN		 932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 934
0b99836f
JN		 935 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
936 connector->base.kdev->kobj.name);
8316f337 937
4f71d0cb 938 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 939 if (ret < 0) {
4f71d0cb 940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 941 name, ret);
942 return;
ab2c0672 943 }
8a5e6aeb 944
0b99836f
JN		 945 ret = sysfs_create_link(&connector->base.kdev->kobj,
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
948 if (ret < 0) {
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 950 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 951 }
a4fc5ed6
KP		 952}
953
80f65de3
ID		 954static void
955intel_dp_connector_unregister(struct intel_connector *intel_connector)
956{
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
958
0e32b39c
DA		 959 if (!intel_connector->mst_port)
960 sysfs_remove_link(&intel_connector->base.kdev->kobj,
961 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 962 intel_connector_unregister(intel_connector);
963}
964
0e50338c
DV		 965static void
966hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
967{
968 switch (link_bw) {
969 case DP_LINK_BW_1_62:
970 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
971 break;
972 case DP_LINK_BW_2_7:
973 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
974 break;
975 case DP_LINK_BW_5_4:
976 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
977 break;
978 }
979}
980
c6bb3538
DV		 981static void
982intel_dp_set_clock(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config, int link_bw)
984{
985 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 986 const struct dp_link_dpll *divisor = NULL;
987 int i, count = 0;
c6bb3538
DV		 988
989 if (IS_G4X(dev)) {
9dd4ffdf
CML		 990 divisor = gen4_dpll;
991 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 992 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 993 divisor = pch_dpll;
994 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 995 } else if (IS_CHERRYVIEW(dev)) {
996 divisor = chv_dpll;
997 count = ARRAY_SIZE(chv_dpll);
c6bb3538 998 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 999 divisor = vlv_dpll;
1000 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1001 }
9dd4ffdf
CML		 1002
1003 if (divisor && count) {
1004 for (i = 0; i < count; i++) {
1005 if (link_bw == divisor[i].link_bw) {
1006 pipe_config->dpll = divisor[i].dpll;
1007 pipe_config->clock_set = true;
1008 break;
1009 }
1010 }
c6bb3538
DV		 1011 }
1012}
1013
00c09d70 1014bool
5bfe2ac0
DV		 1015intel_dp_compute_config(struct intel_encoder *encoder,
1016 struct intel_crtc_config *pipe_config)
a4fc5ed6 1017{
5bfe2ac0 1018 struct drm_device *dev = encoder->base.dev;
36008365 1019 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1020 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1023 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1025 int lane_count, clock;
56071a20 1026 int min_lane_count = 1;
eeb6324d 1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1028 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1029 int min_clock = 0;
06ea66b6 1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1031 int bpp, mode_rate;
06ea66b6 1032 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1033 int link_avail, link_clock;
a4fc5ed6 1034
bc7d38a4 1035 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1036 pipe_config->has_pch_encoder = true;
1037
03afc4a2 1038 pipe_config->has_dp_encoder = true;
f769cd24 1039 pipe_config->has_drrs = false;
9ed109a7 1040 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1041
dd06f90e
JN		 1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1044 adjusted_mode);
2dd24552
JB		 1045 if (!HAS_PCH_SPLIT(dev))
1046 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047 intel_connector->panel.fitting_mode);
1048 else
b074cec8
JB		 1049 intel_pch_panel_fitting(intel_crtc, pipe_config,
1050 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1051 }
1052
cb1793ce 1053 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1054 return false;
1055
083f9560
DV		 1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1058 max_lane_count, bws[max_clock],
1059 adjusted_mode->crtc_clock);
083f9560 1060
36008365
DV		 1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
3e7ca985 1063 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1064 if (is_edp(intel_dp)) {
1065 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv->vbt.edp_bpp);
1068 bpp = dev_priv->vbt.edp_bpp;
1069 }
1070
f4cdbc21
JN		 1071 if (IS_BROADWELL(dev)) {
1072 /* Yes, it's an ugly hack. */
1073 min_lane_count = max_lane_count;
1074 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1075 min_lane_count);
1076 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 1077 min_lane_count = min(dev_priv->vbt.edp_lanes,
1078 max_lane_count);
1079 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1080 min_lane_count);
1081 }
1082
1083 if (dev_priv->vbt.edp_rate) {
1084 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
1085 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1086 bws[min_clock]);
1087 }
7984211e 1088 }
657445fe 1089
36008365 1090 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1091 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1092 bpp);
36008365 1093
c6930992
DA		 1094 for (clock = min_clock; clock <= max_clock; clock++) {
1095 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1096 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1097 link_avail = intel_dp_max_data_rate(link_clock,
1098 lane_count);
1099
1100 if (mode_rate <= link_avail) {
1101 goto found;
1102 }
1103 }
1104 }
1105 }
c4867936 1106
36008365 1107 return false;
3685a8f3 1108
36008365 1109found:
55bc60db
VS		 1110 if (intel_dp->color_range_auto) {
1111 /*
1112 * See:
1113 * CEA-861-E - 5.1 Default Encoding Parameters
1114 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1115 */
18316c8c 1116 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1117 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1118 else
1119 intel_dp->color_range = 0;
1120 }
1121
3685a8f3 1122 if (intel_dp->color_range)
50f3b016 1123 pipe_config->limited_color_range = true;
a4fc5ed6 1124
36008365
DV		 1125 intel_dp->link_bw = bws[clock];
1126 intel_dp->lane_count = lane_count;
657445fe 1127 pipe_config->pipe_bpp = bpp;
ff9a6750 1128 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1129
36008365
DV		 1130 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1131 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1132 pipe_config->port_clock, bpp);
36008365
DV		 1133 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1134 mode_rate, link_avail);
a4fc5ed6 1135
03afc4a2 1136 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1137 adjusted_mode->crtc_clock,
1138 pipe_config->port_clock,
03afc4a2 1139 &pipe_config->dp_m_n);
9d1a455b 1140
439d7ac0
PB		 1141 if (intel_connector->panel.downclock_mode != NULL &&
1142 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1143 pipe_config->has_drrs = true;
439d7ac0
PB		 1144 intel_link_compute_m_n(bpp, lane_count,
1145 intel_connector->panel.downclock_mode->clock,
1146 pipe_config->port_clock,
1147 &pipe_config->dp_m2_n2);
1148 }
1149
ea155f32 1150 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1151 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1152 else
1153 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1154
03afc4a2 1155 return true;
a4fc5ed6
KP		 1156}
1157
7c62a164 1158static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1159{
7c62a164
DV		 1160 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1161 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1162 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1163 struct drm_i915_private *dev_priv = dev->dev_private;
1164 u32 dpa_ctl;
1165
ff9a6750 1166 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1167 dpa_ctl = I915_READ(DP_A);
1168 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1169
ff9a6750 1170 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1171 /* For a long time we've carried around a ILK-DevA w/a for the
1172 * 160MHz clock. If we're really unlucky, it's still required.
1173 */
1174 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1175 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1176 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1177 } else {
1178 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1179 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1180 }
1ce17038 1181
ea9b6006
DV		 1182 I915_WRITE(DP_A, dpa_ctl);
1183
1184 POSTING_READ(DP_A);
1185 udelay(500);
1186}
1187
8ac33ed3 1188static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1189{
b934223d 1190 struct drm_device *dev = encoder->base.dev;
417e822d 1191 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1192 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1193 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1194 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1195 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1196
417e822d 1197 /*
1a2eb460 1198 * There are four kinds of DP registers:
417e822d
KP		 1199 *
1200 * IBX PCH
1a2eb460
KP		 1201 * SNB CPU
1202 * IVB CPU
417e822d
KP		 1203 * CPT PCH
1204 *
1205 * IBX PCH and CPU are the same for almost everything,
1206 * except that the CPU DP PLL is configured in this
1207 * register
1208 *
1209 * CPT PCH is quite different, having many bits moved
1210 * to the TRANS_DP_CTL register instead. That
1211 * configuration happens (oddly) in ironlake_pch_enable
1212 */
9c9e7927 1213
417e822d
KP		 1214 /* Preserve the BIOS-computed detected bit. This is
1215 * supposed to be read-only.
1216 */
1217 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1218
417e822d 1219 /* Handle DP bits in common between all three register formats */
417e822d 1220 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1221 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1222
9ed109a7 1223 if (crtc->config.has_audio) {
e0dac65e 1224 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1225 pipe_name(crtc->pipe));
ea5b213a 1226 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1227 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1228 }
247d89f6 1229
417e822d 1230 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1231
bc7d38a4 1232 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1233 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1234 intel_dp->DP |= DP_SYNC_HS_HIGH;
1235 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1236 intel_dp->DP |= DP_SYNC_VS_HIGH;
1237 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1238
6aba5b6c 1239 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1240 intel_dp->DP |= DP_ENHANCED_FRAMING;
1241
7c62a164 1242 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1243 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1244 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1245 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1246
1247 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1248 intel_dp->DP |= DP_SYNC_HS_HIGH;
1249 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1250 intel_dp->DP |= DP_SYNC_VS_HIGH;
1251 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1252
6aba5b6c 1253 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1254 intel_dp->DP |= DP_ENHANCED_FRAMING;
1255
44f37d1f
CML		 1256 if (!IS_CHERRYVIEW(dev)) {
1257 if (crtc->pipe == 1)
1258 intel_dp->DP |= DP_PIPEB_SELECT;
1259 } else {
1260 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1261 }
417e822d
KP		 1262 } else {
1263 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1264 }
a4fc5ed6
KP		 1265}
1266
ffd6749d
PZ		 1267#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1268#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1269
1a5ef5b7
PZ		 1270#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1271#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1272
ffd6749d
PZ		 1273#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1274#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1275
4be73780 1276static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1277 u32 mask,
1278 u32 value)
bd943159 1279{
30add22d 1280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1281 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1282 u32 pp_stat_reg, pp_ctrl_reg;
1283
e39b999a
VS		 1284 lockdep_assert_held(&dev_priv->pps_mutex);
1285
bf13e81b
JN		 1286 pp_stat_reg = _pp_stat_reg(intel_dp);
1287 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1288
99ea7127 1289 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1290 mask, value,
1291 I915_READ(pp_stat_reg),
1292 I915_READ(pp_ctrl_reg));
32ce697c 1293
453c5420 1294 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1295 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1296 I915_READ(pp_stat_reg),
1297 I915_READ(pp_ctrl_reg));
32ce697c 1298 }
54c136d4
CW		 1299
1300 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1301}
32ce697c 1302
4be73780 1303static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1304{
1305 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1306 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1307}
1308
4be73780 1309static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1310{
1311 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1312 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1313}
1314
4be73780 1315static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1316{
1317 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1318
1319 /* When we disable the VDD override bit last we have to do the manual
1320 * wait. */
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1322 intel_dp->panel_power_cycle_delay);
1323
4be73780 1324 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1325}
1326
4be73780 1327static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1328{
1329 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1330 intel_dp->backlight_on_delay);
1331}
1332
4be73780 1333static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1334{
1335 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1336 intel_dp->backlight_off_delay);
1337}
99ea7127 1338
832dd3c1
KP		 1339/* Read the current pp_control value, unlocking the register if it
1340 * is locked
1341 */
1342
453c5420 1343static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1344{
453c5420
JB		 1345 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 u32 control;
832dd3c1 1348
e39b999a
VS		 1349 lockdep_assert_held(&dev_priv->pps_mutex);
1350
bf13e81b 1351 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1352 control &= ~PANEL_UNLOCK_MASK;
1353 control |= PANEL_UNLOCK_REGS;
1354 return control;
bd943159
KP		 1355}
1356
1e0560e0 1357static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1358{
30add22d 1359 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1360 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1361 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1362 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1363 enum intel_display_power_domain power_domain;
5d613501 1364 u32 pp;
453c5420 1365 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1366 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1367
e39b999a
VS		 1368 lockdep_assert_held(&dev_priv->pps_mutex);
1369
97af61f5 1370 if (!is_edp(intel_dp))
adddaaf4 1371 return false;
bd943159
KP		 1372
1373 intel_dp->want_panel_vdd = true;
99ea7127 1374
4be73780 1375 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1376 return need_to_disable;
b0665d57 1377
4e6e1a54
ID		 1378 power_domain = intel_display_port_power_domain(intel_encoder);
1379 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1380
b0665d57 1381 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1382
4be73780
DV		 1383 if (!edp_have_panel_power(intel_dp))
1384 wait_panel_power_cycle(intel_dp);
99ea7127 1385
453c5420 1386 pp = ironlake_get_pp_control(intel_dp);
5d613501 1387 pp |= EDP_FORCE_VDD;
ebf33b18 1388
bf13e81b
JN		 1389 pp_stat_reg = _pp_stat_reg(intel_dp);
1390 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1391
1392 I915_WRITE(pp_ctrl_reg, pp);
1393 POSTING_READ(pp_ctrl_reg);
1394 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1395 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1396 /*
1397 * If the panel wasn't on, delay before accessing aux channel
1398 */
4be73780 1399 if (!edp_have_panel_power(intel_dp)) {
bd943159 1400 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1401 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1402 }
adddaaf4
JN		 1403
1404 return need_to_disable;
1405}
1406
b80d6c78 1407void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1408{
c695b6b6 1409 bool vdd;
adddaaf4 1410
c695b6b6
VS		 1411 if (!is_edp(intel_dp))
1412 return;
1413
773538e8 1414 pps_lock(intel_dp);
c695b6b6 1415 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1416 pps_unlock(intel_dp);
c695b6b6
VS		 1417
1418 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1419}
1420
4be73780 1421static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1422{
30add22d 1423 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1424 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1425 struct intel_digital_port *intel_dig_port =
1426 dp_to_dig_port(intel_dp);
1427 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1428 enum intel_display_power_domain power_domain;
5d613501 1429 u32 pp;
453c5420 1430 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1431
e39b999a 1432 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1433
15e899a0
VS		 1434 WARN_ON(intel_dp->want_panel_vdd);
1435
1436 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1437 return;
4e6e1a54 1438
be2c9196 1439 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1440
be2c9196
VS		 1441 pp = ironlake_get_pp_control(intel_dp);
1442 pp &= ~EDP_FORCE_VDD;
bd943159 1443
be2c9196
VS		 1444 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1445 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1446
be2c9196
VS		 1447 I915_WRITE(pp_ctrl_reg, pp);
1448 POSTING_READ(pp_ctrl_reg);
99ea7127 1449
be2c9196
VS		 1450 /* Make sure sequencer is idle before allowing subsequent activity */
1451 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1452 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1453
be2c9196
VS		 1454 if ((pp & POWER_TARGET_ON) == 0)
1455 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1456
be2c9196
VS		 1457 power_domain = intel_display_port_power_domain(intel_encoder);
1458 intel_display_power_put(dev_priv, power_domain);
bd943159 1459}
5d613501 1460
4be73780 1461static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1462{
1463 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1464 struct intel_dp, panel_vdd_work);
bd943159 1465
773538e8 1466 pps_lock(intel_dp);
15e899a0
VS		 1467 if (!intel_dp->want_panel_vdd)
1468 edp_panel_vdd_off_sync(intel_dp);
773538e8 1469 pps_unlock(intel_dp);
bd943159
KP		 1470}
1471
aba86890
ID		 1472static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1473{
1474 unsigned long delay;
1475
1476 /*
1477 * Queue the timer to fire a long time from now (relative to the power
1478 * down delay) to keep the panel power up across a sequence of
1479 * operations.
1480 */
1481 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1482 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1483}
1484
4be73780 1485static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1486{
e39b999a
VS		 1487 struct drm_i915_private *dev_priv =
1488 intel_dp_to_dev(intel_dp)->dev_private;
1489
1490 lockdep_assert_held(&dev_priv->pps_mutex);
1491
97af61f5
KP		 1492 if (!is_edp(intel_dp))
1493 return;
5d613501 1494
bd943159 1495 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1496
bd943159
KP		 1497 intel_dp->want_panel_vdd = false;
1498
aba86890 1499 if (sync)
4be73780 1500 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1501 else
1502 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1503}
1504
1e0560e0
VS		 1505static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1506{
e39b999a
VS		 1507 if (!is_edp(intel_dp))
1508 return;
1509
773538e8 1510 pps_lock(intel_dp);
1e0560e0 1511 edp_panel_vdd_off(intel_dp, sync);
773538e8 1512 pps_unlock(intel_dp);
1e0560e0
VS		 1513}
1514
4be73780 1515void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1516{
30add22d 1517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1518 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1519 u32 pp;
453c5420 1520 u32 pp_ctrl_reg;
9934c132 1521
97af61f5 1522 if (!is_edp(intel_dp))
bd943159 1523 return;
99ea7127
KP		 1524
1525 DRM_DEBUG_KMS("Turn eDP power on\n");
1526
773538e8 1527 pps_lock(intel_dp);
e39b999a 1528
4be73780 1529 if (edp_have_panel_power(intel_dp)) {
99ea7127 1530 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1531 goto out;
99ea7127 1532 }
9934c132 1533
4be73780 1534 wait_panel_power_cycle(intel_dp);
37c6c9b0 1535
bf13e81b 1536 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1537 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1538 if (IS_GEN5(dev)) {
1539 /* ILK workaround: disable reset around power sequence */
1540 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1541 I915_WRITE(pp_ctrl_reg, pp);
1542 POSTING_READ(pp_ctrl_reg);
05ce1a49 1543 }
37c6c9b0 1544
1c0ae80a 1545 pp |= POWER_TARGET_ON;
99ea7127
KP		 1546 if (!IS_GEN5(dev))
1547 pp |= PANEL_POWER_RESET;
1548
453c5420
JB		 1549 I915_WRITE(pp_ctrl_reg, pp);
1550 POSTING_READ(pp_ctrl_reg);
9934c132 1551
4be73780 1552 wait_panel_on(intel_dp);
dce56b3c 1553 intel_dp->last_power_on = jiffies;
9934c132 1554
05ce1a49
KP		 1555 if (IS_GEN5(dev)) {
1556 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1557 I915_WRITE(pp_ctrl_reg, pp);
1558 POSTING_READ(pp_ctrl_reg);
05ce1a49 1559 }
e39b999a
VS		 1560
1561 out:
773538e8 1562 pps_unlock(intel_dp);
9934c132
JB		 1563}
1564
4be73780 1565void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1566{
4e6e1a54
ID		 1567 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1568 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1570 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1571 enum intel_display_power_domain power_domain;
99ea7127 1572 u32 pp;
453c5420 1573 u32 pp_ctrl_reg;
9934c132 1574
97af61f5
KP		 1575 if (!is_edp(intel_dp))
1576 return;
37c6c9b0 1577
99ea7127 1578 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1579
773538e8 1580 pps_lock(intel_dp);
e39b999a 1581
24f3e092
JN		 1582 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1583
453c5420 1584 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1585 /* We need to switch off panel power _and_ force vdd, for otherwise some
1586 * panels get very unhappy and cease to work. */
b3064154
PJ		 1587 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1588 EDP_BLC_ENABLE);
453c5420 1589
bf13e81b 1590 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1591
849e39f5
PZ		 1592 intel_dp->want_panel_vdd = false;
1593
453c5420
JB		 1594 I915_WRITE(pp_ctrl_reg, pp);
1595 POSTING_READ(pp_ctrl_reg);
9934c132 1596
dce56b3c 1597 intel_dp->last_power_cycle = jiffies;
4be73780 1598 wait_panel_off(intel_dp);
849e39f5
PZ		 1599
1600 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1601 power_domain = intel_display_port_power_domain(intel_encoder);
1602 intel_display_power_put(dev_priv, power_domain);
e39b999a 1603
773538e8 1604 pps_unlock(intel_dp);
9934c132
JB		 1605}
1606
1250d107
JN		 1607/* Enable backlight in the panel power control. */
1608static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1609{
da63a9f2
PZ		 1610 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1611 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 u32 pp;
453c5420 1614 u32 pp_ctrl_reg;
32f9d658 1615
01cb9ea6
JB		 1616 /*
1617 * If we enable the backlight right away following a panel power
1618 * on, we may see slight flicker as the panel syncs with the eDP
1619 * link. So delay a bit to make sure the image is solid before
1620 * allowing it to appear.
1621 */
4be73780 1622 wait_backlight_on(intel_dp);
e39b999a 1623
773538e8 1624 pps_lock(intel_dp);
e39b999a 1625
453c5420 1626 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1627 pp |= EDP_BLC_ENABLE;
453c5420 1628
bf13e81b 1629 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1630
1631 I915_WRITE(pp_ctrl_reg, pp);
1632 POSTING_READ(pp_ctrl_reg);
e39b999a 1633
773538e8 1634 pps_unlock(intel_dp);
32f9d658
ZW		 1635}
1636
1250d107
JN		 1637/* Enable backlight PWM and backlight PP control. */
1638void intel_edp_backlight_on(struct intel_dp *intel_dp)
1639{
1640 if (!is_edp(intel_dp))
1641 return;
1642
1643 DRM_DEBUG_KMS("\n");
1644
1645 intel_panel_enable_backlight(intel_dp->attached_connector);
1646 _intel_edp_backlight_on(intel_dp);
1647}
1648
1649/* Disable backlight in the panel power control. */
1650static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1651{
30add22d 1652 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 u32 pp;
453c5420 1655 u32 pp_ctrl_reg;
32f9d658 1656
e39b999a
VS		 1657 if (!is_edp(intel_dp))
1658 return;
1659
773538e8 1660 pps_lock(intel_dp);
e39b999a 1661
453c5420 1662 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1663 pp &= ~EDP_BLC_ENABLE;
453c5420 1664
bf13e81b 1665 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1666
1667 I915_WRITE(pp_ctrl_reg, pp);
1668 POSTING_READ(pp_ctrl_reg);
f7d2323c 1669
773538e8 1670 pps_unlock(intel_dp);
e39b999a
VS		 1671
1672 intel_dp->last_backlight_off = jiffies;
f7d2323c 1673 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1674}
1675
1676/* Disable backlight PP control and backlight PWM. */
1677void intel_edp_backlight_off(struct intel_dp *intel_dp)
1678{
1679 if (!is_edp(intel_dp))
1680 return;
1681
1682 DRM_DEBUG_KMS("\n");
f7d2323c 1683
1250d107 1684 _intel_edp_backlight_off(intel_dp);
f7d2323c 1685 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1686}
a4fc5ed6 1687
73580fb7
JN		 1688/*
1689 * Hook for controlling the panel power control backlight through the bl_power
1690 * sysfs attribute. Take care to handle multiple calls.
1691 */
1692static void intel_edp_backlight_power(struct intel_connector *connector,
1693 bool enable)
1694{
1695 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1696 bool is_enabled;
1697
773538e8 1698 pps_lock(intel_dp);
e39b999a 1699 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1700 pps_unlock(intel_dp);
73580fb7
JN		 1701
1702 if (is_enabled == enable)
1703 return;
1704
23ba9373
JN		 1705 DRM_DEBUG_KMS("panel power control backlight %s\n",
1706 enable ? "enable" : "disable");
73580fb7
JN		 1707
1708 if (enable)
1709 _intel_edp_backlight_on(intel_dp);
1710 else
1711 _intel_edp_backlight_off(intel_dp);
1712}
1713
2bd2ad64 1714static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1715{
da63a9f2
PZ		 1716 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1717 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1718 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720 u32 dpa_ctl;
1721
2bd2ad64
DV		 1722 assert_pipe_disabled(dev_priv,
1723 to_intel_crtc(crtc)->pipe);
1724
d240f20f
JB		 1725 DRM_DEBUG_KMS("\n");
1726 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1727 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1728 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1729
1730 /* We don't adjust intel_dp->DP while tearing down the link, to
1731 * facilitate link retraining (e.g. after hotplug). Hence clear all
1732 * enable bits here to ensure that we don't enable too much. */
1733 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1734 intel_dp->DP |= DP_PLL_ENABLE;
1735 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1736 POSTING_READ(DP_A);
1737 udelay(200);
d240f20f
JB		 1738}
1739
2bd2ad64 1740static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1741{
da63a9f2
PZ		 1742 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1743 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1744 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 u32 dpa_ctl;
1747
2bd2ad64
DV		 1748 assert_pipe_disabled(dev_priv,
1749 to_intel_crtc(crtc)->pipe);
1750
d240f20f 1751 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1752 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1753 "dp pll off, should be on\n");
1754 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1755
1756 /* We can't rely on the value tracked for the DP register in
1757 * intel_dp->DP because link_down must not change that (otherwise link
1758 * re-training will fail. */
298b0b39 1759 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1760 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1761 POSTING_READ(DP_A);
d240f20f
JB		 1762 udelay(200);
1763}
1764
c7ad3810 1765/* If the sink supports it, try to set the power state appropriately */
c19b0669 1766void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1767{
1768 int ret, i;
1769
1770 /* Should have a valid DPCD by this point */
1771 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1772 return;
1773
1774 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1775 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1776 DP_SET_POWER_D3);
c7ad3810
JB		 1777 } else {
1778 /*
1779 * When turning on, we need to retry for 1ms to give the sink
1780 * time to wake up.
1781 */
1782 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1783 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1784 DP_SET_POWER_D0);
c7ad3810
JB		 1785 if (ret == 1)
1786 break;
1787 msleep(1);
1788 }
1789 }
f9cac721
JN		 1790
1791 if (ret != 1)
1792 DRM_DEBUG_KMS("failed to %s sink power state\n",
1793 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1794}
1795
19d8fe15
DV		 1796static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1797 enum pipe *pipe)
d240f20f 1798{
19d8fe15 1799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1800 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1801 struct drm_device *dev = encoder->base.dev;
1802 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1803 enum intel_display_power_domain power_domain;
1804 u32 tmp;
1805
1806 power_domain = intel_display_port_power_domain(encoder);
1807 if (!intel_display_power_enabled(dev_priv, power_domain))
1808 return false;
1809
1810 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1811
1812 if (!(tmp & DP_PORT_EN))
1813 return false;
1814
bc7d38a4 1815 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1816 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1817 } else if (IS_CHERRYVIEW(dev)) {
1818 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1819 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1820 *pipe = PORT_TO_PIPE(tmp);
1821 } else {
1822 u32 trans_sel;
1823 u32 trans_dp;
1824 int i;
1825
1826 switch (intel_dp->output_reg) {
1827 case PCH_DP_B:
1828 trans_sel = TRANS_DP_PORT_SEL_B;
1829 break;
1830 case PCH_DP_C:
1831 trans_sel = TRANS_DP_PORT_SEL_C;
1832 break;
1833 case PCH_DP_D:
1834 trans_sel = TRANS_DP_PORT_SEL_D;
1835 break;
1836 default:
1837 return true;
1838 }
1839
055e393f 1840 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1841 trans_dp = I915_READ(TRANS_DP_CTL(i));
1842 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1843 *pipe = i;
1844 return true;
1845 }
1846 }
19d8fe15 1847
4a0833ec
DV		 1848 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1849 intel_dp->output_reg);
1850 }
d240f20f 1851
19d8fe15
DV		 1852 return true;
1853}
d240f20f 1854
045ac3b5
JB		 1855static void intel_dp_get_config(struct intel_encoder *encoder,
1856 struct intel_crtc_config *pipe_config)
1857{
1858 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1859 u32 tmp, flags = 0;
63000ef6
XZ		 1860 struct drm_device *dev = encoder->base.dev;
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1862 enum port port = dp_to_dig_port(intel_dp)->port;
1863 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1864 int dotclock;
045ac3b5 1865
9ed109a7
DV		 1866 tmp = I915_READ(intel_dp->output_reg);
1867 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1868 pipe_config->has_audio = true;
1869
63000ef6 1870 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1871 if (tmp & DP_SYNC_HS_HIGH)
1872 flags |= DRM_MODE_FLAG_PHSYNC;
1873 else
1874 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1875
63000ef6
XZ		 1876 if (tmp & DP_SYNC_VS_HIGH)
1877 flags |= DRM_MODE_FLAG_PVSYNC;
1878 else
1879 flags |= DRM_MODE_FLAG_NVSYNC;
1880 } else {
1881 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1882 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1883 flags |= DRM_MODE_FLAG_PHSYNC;
1884 else
1885 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1886
63000ef6
XZ		 1887 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1888 flags |= DRM_MODE_FLAG_PVSYNC;
1889 else
1890 flags |= DRM_MODE_FLAG_NVSYNC;
1891 }
045ac3b5
JB		 1892
1893 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1894
eb14cb74
VS		 1895 pipe_config->has_dp_encoder = true;
1896
1897 intel_dp_get_m_n(crtc, pipe_config);
1898
18442d08 1899 if (port == PORT_A) {
f1f644dc
JB		 1900 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1901 pipe_config->port_clock = 162000;
1902 else
1903 pipe_config->port_clock = 270000;
1904 }
18442d08
VS		 1905
1906 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1907 &pipe_config->dp_m_n);
1908
1909 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1910 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1911
241bfc38 1912 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1913
c6cd2ee2
JN		 1914 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1915 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1916 /*
1917 * This is a big fat ugly hack.
1918 *
1919 * Some machines in UEFI boot mode provide us a VBT that has 18
1920 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1921 * unknown we fail to light up. Yet the same BIOS boots up with
1922 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1923 * max, not what it tells us to use.
1924 *
1925 * Note: This will still be broken if the eDP panel is not lit
1926 * up by the BIOS, and thus we can't get the mode at module
1927 * load.
1928 */
1929 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1930 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1931 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1932 }
045ac3b5
JB		 1933}
1934
34eb7579 1935static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1936{
34eb7579 1937 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1938}
1939
2b28bb1b
RV		 1940static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1941{
1942 struct drm_i915_private *dev_priv = dev->dev_private;
1943
18b5992c 1944 if (!HAS_PSR(dev))
2b28bb1b
RV		 1945 return false;
1946
18b5992c 1947 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1948}
1949
1950static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1951 struct edp_vsc_psr *vsc_psr)
1952{
1953 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1954 struct drm_device *dev = dig_port->base.base.dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1957 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1958 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1959 uint32_t *data = (uint32_t *) vsc_psr;
1960 unsigned int i;
1961
1962 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1963 the video DIP being updated before program video DIP data buffer
1964 registers for DIP being updated. */
1965 I915_WRITE(ctl_reg, 0);
1966 POSTING_READ(ctl_reg);
1967
1968 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1969 if (i < sizeof(struct edp_vsc_psr))
1970 I915_WRITE(data_reg + i, *data++);
1971 else
1972 I915_WRITE(data_reg + i, 0);
1973 }
1974
1975 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1976 POSTING_READ(ctl_reg);
1977}
1978
1979static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1980{
1981 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct edp_vsc_psr psr_vsc;
1984
2b28bb1b
RV		 1985 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1986 memset(&psr_vsc, 0, sizeof(psr_vsc));
1987 psr_vsc.sdp_header.HB0 = 0;
1988 psr_vsc.sdp_header.HB1 = 0x7;
1989 psr_vsc.sdp_header.HB2 = 0x2;
1990 psr_vsc.sdp_header.HB3 = 0x8;
1991 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1992
1993 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1994 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1995 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1996}
1997
1998static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1999{
0e0ae652
RV		 2000 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2001 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2002 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2003 uint32_t aux_clock_divider;
2b28bb1b
RV		 2004 int precharge = 0x3;
2005 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2006 bool only_standby = false;
2b28bb1b 2007
ec5b01dd
DL		 2008 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2009
0e0ae652
RV		 2010 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2011 only_standby = true;
2012
2b28bb1b 2013 /* Enable PSR in sink */
0e0ae652 2014 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2015 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2016 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2017 else
9d1a1031
JN		 2018 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2019 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2020
2021 /* Setup AUX registers */
18b5992c
BW		 2022 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2023 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2024 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2025 DP_AUX_CH_CTL_TIME_OUT_400us |
2026 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2027 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2028 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2029}
2030
2031static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2032{
0e0ae652
RV		 2033 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2034 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2035 struct drm_i915_private *dev_priv = dev->dev_private;
2036 uint32_t max_sleep_time = 0x1f;
2037 uint32_t idle_frames = 1;
2038 uint32_t val = 0x0;
ed8546ac 2039 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2040 bool only_standby = false;
2041
2042 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2043 only_standby = true;
2b28bb1b 2044
0e0ae652 2045 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2046 val |= EDP_PSR_LINK_STANDBY;
2047 val |= EDP_PSR_TP2_TP3_TIME_0us;
2048 val |= EDP_PSR_TP1_TIME_0us;
2049 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2050 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2051 } else
2052 val |= EDP_PSR_LINK_DISABLE;
2053
18b5992c 2054 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2055 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2056 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2057 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2058 EDP_PSR_ENABLE);
2059}
2060
3f51e471
RV		 2061static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2062{
2063 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2064 struct drm_device *dev = dig_port->base.base.dev;
2065 struct drm_i915_private *dev_priv = dev->dev_private;
2066 struct drm_crtc *crtc = dig_port->base.base.crtc;
2067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2068
f0355c4a 2069 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2070 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2071 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2072
a031d709
RV		 2073 dev_priv->psr.source_ok = false;
2074
9ca15301 2075 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2076 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2077 return false;
2078 }
2079
d330a953 2080 if (!i915.enable_psr) {
105b7c11 2081 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2082 return false;
2083 }
2084
4c8c7000
RV		 2085 /* Below limitations aren't valid for Broadwell */
2086 if (IS_BROADWELL(dev))
2087 goto out;
2088
3f51e471
RV		 2089 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2090 S3D_ENABLE) {
2091 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2092 return false;
2093 }
2094
ca73b4f0 2095 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2096 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2097 return false;
2098 }
2099
4c8c7000 2100 out:
a031d709 2101 dev_priv->psr.source_ok = true;
3f51e471
RV		 2102 return true;
2103}
2104
3d739d92 2105static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2106{
7c8f8a70
RV		 2107 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2108 struct drm_device *dev = intel_dig_port->base.base.dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2110
3638379c
DV		 2111 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2112 WARN_ON(dev_priv->psr.active);
f0355c4a 2113 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2114
2b28bb1b
RV		 2115 /* Enable PSR on the panel */
2116 intel_edp_psr_enable_sink(intel_dp);
2117
2118 /* Enable PSR on the host */
2119 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2120
7c8f8a70 2121 dev_priv->psr.active = true;
2b28bb1b
RV		 2122}
2123
3d739d92
RV		 2124void intel_edp_psr_enable(struct intel_dp *intel_dp)
2125{
2126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2127 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2128
4704c573
RV		 2129 if (!HAS_PSR(dev)) {
2130 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2131 return;
2132 }
2133
34eb7579
RV		 2134 if (!is_edp_psr(intel_dp)) {
2135 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2136 return;
2137 }
2138
f0355c4a 2139 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2140 if (dev_priv->psr.enabled) {
2141 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2142 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2143 return;
2144 }
2145
9ca15301
DV		 2146 dev_priv->psr.busy_frontbuffer_bits = 0;
2147
16487254
RV		 2148 /* Setup PSR once */
2149 intel_edp_psr_setup(intel_dp);
2150
7c8f8a70 2151 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2152 dev_priv->psr.enabled = intel_dp;
f0355c4a 2153 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2154}
2155
2b28bb1b
RV		 2156void intel_edp_psr_disable(struct intel_dp *intel_dp)
2157{
2158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160
f0355c4a
DV		 2161 mutex_lock(&dev_priv->psr.lock);
2162 if (!dev_priv->psr.enabled) {
2163 mutex_unlock(&dev_priv->psr.lock);
2164 return;
2165 }
2166
3638379c
DV		 2167 if (dev_priv->psr.active) {
2168 I915_WRITE(EDP_PSR_CTL(dev),
2169 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2170
2171 /* Wait till PSR is idle */
2172 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2173 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2174 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2175
3638379c
DV		 2176 dev_priv->psr.active = false;
2177 } else {
2178 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2179 }
7c8f8a70 2180
2807cf69 2181 dev_priv->psr.enabled = NULL;
f0355c4a 2182 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2183
2184 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2185}
2186
f02a326e 2187static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2188{
2189 struct drm_i915_private *dev_priv =
2190 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2191 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2192
f0355c4a
DV		 2193 mutex_lock(&dev_priv->psr.lock);
2194 intel_dp = dev_priv->psr.enabled;
2195
2807cf69 2196 if (!intel_dp)
f0355c4a 2197 goto unlock;
2807cf69 2198
9ca15301
DV		 2199 /*
2200 * The delayed work can race with an invalidate hence we need to
2201 * recheck. Since psr_flush first clears this and then reschedules we
2202 * won't ever miss a flush when bailing out here.
2203 */
2204 if (dev_priv->psr.busy_frontbuffer_bits)
2205 goto unlock;
2206
2207 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2208unlock:
2209 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2210}
2211
9ca15301 2212static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2213{
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215
3638379c
DV		 2216 if (dev_priv->psr.active) {
2217 u32 val = I915_READ(EDP_PSR_CTL(dev));
2218
2219 WARN_ON(!(val & EDP_PSR_ENABLE));
2220
2221 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2222
2223 dev_priv->psr.active = false;
2224 }
7c8f8a70 2225
9ca15301
DV		 2226}
2227
2228void intel_edp_psr_invalidate(struct drm_device *dev,
2229 unsigned frontbuffer_bits)
2230{
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 struct drm_crtc *crtc;
2233 enum pipe pipe;
2234
9ca15301
DV		 2235 mutex_lock(&dev_priv->psr.lock);
2236 if (!dev_priv->psr.enabled) {
2237 mutex_unlock(&dev_priv->psr.lock);
2238 return;
2239 }
2240
2241 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2242 pipe = to_intel_crtc(crtc)->pipe;
2243
2244 intel_edp_psr_do_exit(dev);
2245
2246 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2247
2248 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2249 mutex_unlock(&dev_priv->psr.lock);
2250}
2251
2252void intel_edp_psr_flush(struct drm_device *dev,
2253 unsigned frontbuffer_bits)
2254{
2255 struct drm_i915_private *dev_priv = dev->dev_private;
2256 struct drm_crtc *crtc;
2257 enum pipe pipe;
2258
9ca15301
DV		 2259 mutex_lock(&dev_priv->psr.lock);
2260 if (!dev_priv->psr.enabled) {
2261 mutex_unlock(&dev_priv->psr.lock);
2262 return;
2263 }
2264
2265 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2266 pipe = to_intel_crtc(crtc)->pipe;
2267 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2268
2269 /*
2270 * On Haswell sprite plane updates don't result in a psr invalidating
2271 * signal in the hardware. Which means we need to manually fake this in
2272 * software for all flushes, not just when we've seen a preceding
2273 * invalidation through frontbuffer rendering.
2274 */
2275 if (IS_HASWELL(dev) &&
2276 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2277 intel_edp_psr_do_exit(dev);
2278
2279 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2280 schedule_delayed_work(&dev_priv->psr.work,
2281 msecs_to_jiffies(100));
f0355c4a 2282 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2283}
2284
2285void intel_edp_psr_init(struct drm_device *dev)
2286{
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288
7c8f8a70 2289 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2290 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2291}
2292
e8cb4558 2293static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2294{
e8cb4558 2295 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2296 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2297
2298 /* Make sure the panel is off before trying to change the mode. But also
2299 * ensure that we have vdd while we switch off the panel. */
24f3e092 2300 intel_edp_panel_vdd_on(intel_dp);
4be73780 2301 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2302 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2303 intel_edp_panel_off(intel_dp);
3739850b 2304
08aff3fe
VS		 2305 /* disable the port before the pipe on g4x */
2306 if (INTEL_INFO(dev)->gen < 5)
3739850b 2307 intel_dp_link_down(intel_dp);
d240f20f
JB		 2308}
2309
08aff3fe 2310static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2311{
2bd2ad64 2312 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2313 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2314
49277c31 2315 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2316 if (port == PORT_A)
2317 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2318}
2319
2320static void vlv_post_disable_dp(struct intel_encoder *encoder)
2321{
2322 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2323
2324 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2325}
2326
580d3811
VS		 2327static void chv_post_disable_dp(struct intel_encoder *encoder)
2328{
2329 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2330 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2331 struct drm_device *dev = encoder->base.dev;
2332 struct drm_i915_private *dev_priv = dev->dev_private;
2333 struct intel_crtc *intel_crtc =
2334 to_intel_crtc(encoder->base.crtc);
2335 enum dpio_channel ch = vlv_dport_to_channel(dport);
2336 enum pipe pipe = intel_crtc->pipe;
2337 u32 val;
2338
2339 intel_dp_link_down(intel_dp);
2340
2341 mutex_lock(&dev_priv->dpio_lock);
2342
2343 /* Propagate soft reset to data lane reset */
97fd4d5c 2344 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2345 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2346 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2347
97fd4d5c
VS		 2348 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2349 val |= CHV_PCS_REQ_SOFTRESET_EN;
2350 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2351
2352 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2353 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2354 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2355
2356 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2357 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2358 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2359
2360 mutex_unlock(&dev_priv->dpio_lock);
2361}
2362
7b13b58a
VS		 2363static void
2364_intel_dp_set_link_train(struct intel_dp *intel_dp,
2365 uint32_t *DP,
2366 uint8_t dp_train_pat)
2367{
2368 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2369 struct drm_device *dev = intel_dig_port->base.base.dev;
2370 struct drm_i915_private *dev_priv = dev->dev_private;
2371 enum port port = intel_dig_port->port;
2372
2373 if (HAS_DDI(dev)) {
2374 uint32_t temp = I915_READ(DP_TP_CTL(port));
2375
2376 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2377 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2378 else
2379 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2380
2381 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2382 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2383 case DP_TRAINING_PATTERN_DISABLE:
2384 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2385
2386 break;
2387 case DP_TRAINING_PATTERN_1:
2388 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2389 break;
2390 case DP_TRAINING_PATTERN_2:
2391 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2392 break;
2393 case DP_TRAINING_PATTERN_3:
2394 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2395 break;
2396 }
2397 I915_WRITE(DP_TP_CTL(port), temp);
2398
2399 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2400 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2401
2402 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2403 case DP_TRAINING_PATTERN_DISABLE:
2404 *DP |= DP_LINK_TRAIN_OFF_CPT;
2405 break;
2406 case DP_TRAINING_PATTERN_1:
2407 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2408 break;
2409 case DP_TRAINING_PATTERN_2:
2410 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2411 break;
2412 case DP_TRAINING_PATTERN_3:
2413 DRM_ERROR("DP training pattern 3 not supported\n");
2414 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2415 break;
2416 }
2417
2418 } else {
2419 if (IS_CHERRYVIEW(dev))
2420 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2421 else
2422 *DP &= ~DP_LINK_TRAIN_MASK;
2423
2424 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2425 case DP_TRAINING_PATTERN_DISABLE:
2426 *DP |= DP_LINK_TRAIN_OFF;
2427 break;
2428 case DP_TRAINING_PATTERN_1:
2429 *DP |= DP_LINK_TRAIN_PAT_1;
2430 break;
2431 case DP_TRAINING_PATTERN_2:
2432 *DP |= DP_LINK_TRAIN_PAT_2;
2433 break;
2434 case DP_TRAINING_PATTERN_3:
2435 if (IS_CHERRYVIEW(dev)) {
2436 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2437 } else {
2438 DRM_ERROR("DP training pattern 3 not supported\n");
2439 *DP |= DP_LINK_TRAIN_PAT_2;
2440 }
2441 break;
2442 }
2443 }
2444}
2445
2446static void intel_dp_enable_port(struct intel_dp *intel_dp)
2447{
2448 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450
2451 intel_dp->DP |= DP_PORT_EN;
2452
2453 /* enable with pattern 1 (as per spec) */
2454 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2455 DP_TRAINING_PATTERN_1);
2456
2457 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2458 POSTING_READ(intel_dp->output_reg);
2459}
2460
e8cb4558 2461static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2462{
e8cb4558
DV		 2463 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2464 struct drm_device *dev = encoder->base.dev;
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2466 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2467
0c33d8d7
DV		 2468 if (WARN_ON(dp_reg & DP_PORT_EN))
2469 return;
5d613501 2470
7b13b58a 2471 intel_dp_enable_port(intel_dp);
24f3e092 2472 intel_edp_panel_vdd_on(intel_dp);
4be73780 2473 intel_edp_panel_on(intel_dp);
1e0560e0 2474 intel_edp_panel_vdd_off(intel_dp, true);
43072a45
VS		 2475 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2476 intel_dp_start_link_train(intel_dp);
33a34e4e 2477 intel_dp_complete_link_train(intel_dp);
3ab9c637 2478 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2479}
89b667f8 2480
ecff4f3b
JN		 2481static void g4x_enable_dp(struct intel_encoder *encoder)
2482{
828f5c6e
JN		 2483 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484
ecff4f3b 2485 intel_enable_dp(encoder);
4be73780 2486 intel_edp_backlight_on(intel_dp);
ab1f90f9 2487}
89b667f8 2488
ab1f90f9
JN		 2489static void vlv_enable_dp(struct intel_encoder *encoder)
2490{
828f5c6e
JN		 2491 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2492
4be73780 2493 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2494}
2495
ecff4f3b 2496static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2497{
2498 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2499 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2500
8ac33ed3
DV		 2501 intel_dp_prepare(encoder);
2502
d41f1efb
DV		 2503 /* Only ilk+ has port A */
2504 if (dport->port == PORT_A) {
2505 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2506 ironlake_edp_pll_on(intel_dp);
d41f1efb 2507 }
ab1f90f9
JN		 2508}
2509
a4a5d2f8
VS		 2510static void vlv_steal_power_sequencer(struct drm_device *dev,
2511 enum pipe pipe)
2512{
2513 struct drm_i915_private *dev_priv = dev->dev_private;
2514 struct intel_encoder *encoder;
2515
2516 lockdep_assert_held(&dev_priv->pps_mutex);
2517
2518 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2519 base.head) {
2520 struct intel_dp *intel_dp;
773538e8 2521 enum port port;
a4a5d2f8
VS		 2522
2523 if (encoder->type != INTEL_OUTPUT_EDP)
2524 continue;
2525
2526 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2527 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2528
2529 if (intel_dp->pps_pipe != pipe)
2530 continue;
2531
2532 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2533 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2534
2535 /* make sure vdd is off before we steal it */
2536 edp_panel_vdd_off_sync(intel_dp);
2537
2538 intel_dp->pps_pipe = INVALID_PIPE;
2539 }
2540}
2541
2542static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2543{
2544 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2545 struct intel_encoder *encoder = &intel_dig_port->base;
2546 struct drm_device *dev = encoder->base.dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2549 struct edp_power_seq power_seq;
2550
2551 lockdep_assert_held(&dev_priv->pps_mutex);
2552
2553 if (intel_dp->pps_pipe == crtc->pipe)
2554 return;
2555
2556 /*
2557 * If another power sequencer was being used on this
2558 * port previously make sure to turn off vdd there while
2559 * we still have control of it.
2560 */
2561 if (intel_dp->pps_pipe != INVALID_PIPE)
2562 edp_panel_vdd_off_sync(intel_dp);
2563
2564 /*
2565 * We may be stealing the power
2566 * sequencer from another port.
2567 */
2568 vlv_steal_power_sequencer(dev, crtc->pipe);
2569
2570 /* now it's all ours */
2571 intel_dp->pps_pipe = crtc->pipe;
2572
2573 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2574 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2575
2576 /* init power sequencer on this pipe and port */
2577 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2578 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2579 &power_seq);
2580}
2581
ab1f90f9 2582static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2583{
2bd2ad64 2584 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2585 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2586 struct drm_device *dev = encoder->base.dev;
89b667f8 2587 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2588 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2589 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2590 int pipe = intel_crtc->pipe;
2591 u32 val;
a4fc5ed6 2592
ab1f90f9 2593 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2594
ab3c759a 2595 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2596 val = 0;
2597 if (pipe)
2598 val |= (1<<21);
2599 else
2600 val &= ~(1<<21);
2601 val |= 0x001000c4;
ab3c759a
CML		 2602 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2603 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2604 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2605
ab1f90f9
JN		 2606 mutex_unlock(&dev_priv->dpio_lock);
2607
2cac613b 2608 if (is_edp(intel_dp)) {
773538e8 2609 pps_lock(intel_dp);
a4a5d2f8 2610 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2611 pps_unlock(intel_dp);
2cac613b 2612 }
bf13e81b 2613
ab1f90f9
JN		 2614 intel_enable_dp(encoder);
2615
e4607fcf 2616 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2617}
2618
ecff4f3b 2619static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2620{
2621 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2622 struct drm_device *dev = encoder->base.dev;
2623 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2624 struct intel_crtc *intel_crtc =
2625 to_intel_crtc(encoder->base.crtc);
e4607fcf 2626 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2627 int pipe = intel_crtc->pipe;
89b667f8 2628
8ac33ed3
DV		 2629 intel_dp_prepare(encoder);
2630
89b667f8 2631 /* Program Tx lane resets to default */
0980a60f 2632 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2633 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2634 DPIO_PCS_TX_LANE2_RESET |
2635 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2636 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2637 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2638 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2639 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2640 DPIO_PCS_CLK_SOFT_RESET);
2641
2642 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2643 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2644 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2645 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2646 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2647}
2648
e4a1d846
CML		 2649static void chv_pre_enable_dp(struct intel_encoder *encoder)
2650{
2651 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2652 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2653 struct drm_device *dev = encoder->base.dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2655 struct intel_crtc *intel_crtc =
2656 to_intel_crtc(encoder->base.crtc);
2657 enum dpio_channel ch = vlv_dport_to_channel(dport);
2658 int pipe = intel_crtc->pipe;
2659 int data, i;
949c1d43 2660 u32 val;
e4a1d846 2661
e4a1d846 2662 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2663
2664 /* Deassert soft data lane reset*/
97fd4d5c 2665 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2666 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2667 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2668
2669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2670 val |= CHV_PCS_REQ_SOFTRESET_EN;
2671 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2672
2673 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2674 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2675 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2676
97fd4d5c 2677 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2678 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2679 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2680
2681 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2682 for (i = 0; i < 4; i++) {
2683 /* Set the latency optimal bit */
2684 data = (i == 1) ? 0x0 : 0x6;
2685 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2686 data << DPIO_FRC_LATENCY_SHFIT);
2687
2688 /* Set the upar bit */
2689 data = (i == 1) ? 0x0 : 0x1;
2690 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2691 data << DPIO_UPAR_SHIFT);
2692 }
2693
2694 /* Data lane stagger programming */
2695 /* FIXME: Fix up value only after power analysis */
2696
2697 mutex_unlock(&dev_priv->dpio_lock);
2698
2699 if (is_edp(intel_dp)) {
773538e8 2700 pps_lock(intel_dp);
a4a5d2f8 2701 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2702 pps_unlock(intel_dp);
e4a1d846
CML		 2703 }
2704
2705 intel_enable_dp(encoder);
2706
2707 vlv_wait_port_ready(dev_priv, dport);
2708}
2709
9197c88b
VS		 2710static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2711{
2712 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2713 struct drm_device *dev = encoder->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 struct intel_crtc *intel_crtc =
2716 to_intel_crtc(encoder->base.crtc);
2717 enum dpio_channel ch = vlv_dport_to_channel(dport);
2718 enum pipe pipe = intel_crtc->pipe;
2719 u32 val;
2720
625695f8
VS		 2721 intel_dp_prepare(encoder);
2722
9197c88b
VS		 2723 mutex_lock(&dev_priv->dpio_lock);
2724
b9e5ac3c
VS		 2725 /* program left/right clock distribution */
2726 if (pipe != PIPE_B) {
2727 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2728 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2729 if (ch == DPIO_CH0)
2730 val |= CHV_BUFLEFTENA1_FORCE;
2731 if (ch == DPIO_CH1)
2732 val |= CHV_BUFRIGHTENA1_FORCE;
2733 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2734 } else {
2735 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2736 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2737 if (ch == DPIO_CH0)
2738 val |= CHV_BUFLEFTENA2_FORCE;
2739 if (ch == DPIO_CH1)
2740 val |= CHV_BUFRIGHTENA2_FORCE;
2741 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2742 }
2743
9197c88b
VS		 2744 /* program clock channel usage */
2745 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2746 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2747 if (pipe != PIPE_B)
2748 val &= ~CHV_PCS_USEDCLKCHANNEL;
2749 else
2750 val |= CHV_PCS_USEDCLKCHANNEL;
2751 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2752
2753 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2754 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2755 if (pipe != PIPE_B)
2756 val &= ~CHV_PCS_USEDCLKCHANNEL;
2757 else
2758 val |= CHV_PCS_USEDCLKCHANNEL;
2759 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2760
2761 /*
2762 * This a a bit weird since generally CL
2763 * matches the pipe, but here we need to
2764 * pick the CL based on the port.
2765 */
2766 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2767 if (pipe != PIPE_B)
2768 val &= ~CHV_CMN_USEDCLKCHANNEL;
2769 else
2770 val |= CHV_CMN_USEDCLKCHANNEL;
2771 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2772
2773 mutex_unlock(&dev_priv->dpio_lock);
2774}
2775
a4fc5ed6 2776/*
df0c237d
JB		 2777 * Native read with retry for link status and receiver capability reads for
2778 * cases where the sink may still be asleep.
9d1a1031
JN		 2779 *
2780 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2781 * supposed to retry 3 times per the spec.
a4fc5ed6 2782 */
9d1a1031
JN		 2783static ssize_t
2784intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2785 void *buffer, size_t size)
a4fc5ed6 2786{
9d1a1031
JN		 2787 ssize_t ret;
2788 int i;
61da5fab 2789
61da5fab 2790 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2791 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2792 if (ret == size)
2793 return ret;
61da5fab
JB		 2794 msleep(1);
2795 }
a4fc5ed6 2796
9d1a1031 2797 return ret;
a4fc5ed6
KP		 2798}
2799
2800/*
2801 * Fetch AUX CH registers 0x202 - 0x207 which contain
2802 * link status information
2803 */
2804static bool
93f62dad 2805intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2806{
9d1a1031
JN		 2807 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2808 DP_LANE0_1_STATUS,
2809 link_status,
2810 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2811}
2812
1100244e 2813/* These are source-specific values. */
a4fc5ed6 2814static uint8_t
1a2eb460 2815intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2816{
30add22d 2817 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2818 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2819
9576c27f 2820 if (IS_VALLEYVIEW(dev))
bd60018a 2821 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2822 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2823 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2824 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2825 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2826 else
bd60018a 2827 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2828}
2829
2830static uint8_t
2831intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2832{
30add22d 2833 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2834 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2835
9576c27f 2836 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2837 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2838 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2839 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2840 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2841 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2842 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2843 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2844 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2845 default:
bd60018a 2846 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2847 }
e2fa6fba
P		 2848 } else if (IS_VALLEYVIEW(dev)) {
2849 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2850 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2851 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2853 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2854 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2855 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2856 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2857 default:
bd60018a 2858 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2859 }
bc7d38a4 2860 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2861 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2862 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2863 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2866 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2867 default:
bd60018a 2868 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2869 }
2870 } else {
2871 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2872 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2873 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2874 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2875 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2877 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2878 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2879 default:
bd60018a 2880 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2881 }
a4fc5ed6
KP		 2882 }
2883}
2884
e2fa6fba
P		 2885static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2886{
2887 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2888 struct drm_i915_private *dev_priv = dev->dev_private;
2889 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2890 struct intel_crtc *intel_crtc =
2891 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2892 unsigned long demph_reg_value, preemph_reg_value,
2893 uniqtranscale_reg_value;
2894 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2895 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2896 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2897
2898 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2899 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2900 preemph_reg_value = 0x0004000;
2901 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2902 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2903 demph_reg_value = 0x2B405555;
2904 uniqtranscale_reg_value = 0x552AB83A;
2905 break;
bd60018a 2906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2907 demph_reg_value = 0x2B404040;
2908 uniqtranscale_reg_value = 0x5548B83A;
2909 break;
bd60018a 2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2911 demph_reg_value = 0x2B245555;
2912 uniqtranscale_reg_value = 0x5560B83A;
2913 break;
bd60018a 2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2915 demph_reg_value = 0x2B405555;
2916 uniqtranscale_reg_value = 0x5598DA3A;
2917 break;
2918 default:
2919 return 0;
2920 }
2921 break;
bd60018a 2922 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2923 preemph_reg_value = 0x0002000;
2924 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2926 demph_reg_value = 0x2B404040;
2927 uniqtranscale_reg_value = 0x5552B83A;
2928 break;
bd60018a 2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2930 demph_reg_value = 0x2B404848;
2931 uniqtranscale_reg_value = 0x5580B83A;
2932 break;
bd60018a 2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2934 demph_reg_value = 0x2B404040;
2935 uniqtranscale_reg_value = 0x55ADDA3A;
2936 break;
2937 default:
2938 return 0;
2939 }
2940 break;
bd60018a 2941 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2942 preemph_reg_value = 0x0000000;
2943 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2945 demph_reg_value = 0x2B305555;
2946 uniqtranscale_reg_value = 0x5570B83A;
2947 break;
bd60018a 2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2949 demph_reg_value = 0x2B2B4040;
2950 uniqtranscale_reg_value = 0x55ADDA3A;
2951 break;
2952 default:
2953 return 0;
2954 }
2955 break;
bd60018a 2956 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2957 preemph_reg_value = 0x0006000;
2958 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2960 demph_reg_value = 0x1B405555;
2961 uniqtranscale_reg_value = 0x55ADDA3A;
2962 break;
2963 default:
2964 return 0;
2965 }
2966 break;
2967 default:
2968 return 0;
2969 }
2970
0980a60f 2971 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2972 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2973 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2974 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2975 uniqtranscale_reg_value);
ab3c759a
CML		 2976 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2977 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2978 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2979 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2980 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2981
2982 return 0;
2983}
2984
e4a1d846
CML		 2985static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2986{
2987 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2990 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2991 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2992 uint8_t train_set = intel_dp->train_set[0];
2993 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2994 enum pipe pipe = intel_crtc->pipe;
2995 int i;
e4a1d846
CML		 2996
2997 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2998 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2999 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3000 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3001 deemph_reg_value = 128;
3002 margin_reg_value = 52;
3003 break;
bd60018a 3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3005 deemph_reg_value = 128;
3006 margin_reg_value = 77;
3007 break;
bd60018a 3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3009 deemph_reg_value = 128;
3010 margin_reg_value = 102;
3011 break;
bd60018a 3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3013 deemph_reg_value = 128;
3014 margin_reg_value = 154;
3015 /* FIXME extra to set for 1200 */
3016 break;
3017 default:
3018 return 0;
3019 }
3020 break;
bd60018a 3021 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3022 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3024 deemph_reg_value = 85;
3025 margin_reg_value = 78;
3026 break;
bd60018a 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3028 deemph_reg_value = 85;
3029 margin_reg_value = 116;
3030 break;
bd60018a 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3032 deemph_reg_value = 85;
3033 margin_reg_value = 154;
3034 break;
3035 default:
3036 return 0;
3037 }
3038 break;
bd60018a 3039 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3040 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3042 deemph_reg_value = 64;
3043 margin_reg_value = 104;
3044 break;
bd60018a 3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3046 deemph_reg_value = 64;
3047 margin_reg_value = 154;
3048 break;
3049 default:
3050 return 0;
3051 }
3052 break;
bd60018a 3053 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3054 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3056 deemph_reg_value = 43;
3057 margin_reg_value = 154;
3058 break;
3059 default:
3060 return 0;
3061 }
3062 break;
3063 default:
3064 return 0;
3065 }
3066
3067 mutex_lock(&dev_priv->dpio_lock);
3068
3069 /* Clear calc init */
1966e59e
VS		 3070 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3071 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3072 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3073
3074 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3075 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3076 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3077
3078 /* Program swing deemph */
f72df8db
VS		 3079 for (i = 0; i < 4; i++) {
3080 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3081 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3082 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3083 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3084 }
e4a1d846
CML		 3085
3086 /* Program swing margin */
f72df8db
VS		 3087 for (i = 0; i < 4; i++) {
3088 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3089 val &= ~DPIO_SWING_MARGIN000_MASK;
3090 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3091 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3092 }
e4a1d846
CML		 3093
3094 /* Disable unique transition scale */
f72df8db
VS		 3095 for (i = 0; i < 4; i++) {
3096 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3097 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3098 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3099 }
e4a1d846
CML		 3100
3101 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3102 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3103 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3104 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3105
3106 /*
3107 * The document said it needs to set bit 27 for ch0 and bit 26
3108 * for ch1. Might be a typo in the doc.
3109 * For now, for this unique transition scale selection, set bit
3110 * 27 for ch0 and ch1.
3111 */
f72df8db
VS		 3112 for (i = 0; i < 4; i++) {
3113 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3114 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3115 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3116 }
e4a1d846 3117
f72df8db
VS		 3118 for (i = 0; i < 4; i++) {
3119 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3120 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3121 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3122 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3123 }
e4a1d846
CML		 3124 }
3125
3126 /* Start swing calculation */
1966e59e
VS		 3127 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3128 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3129 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3130
3131 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3132 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3133 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3134
3135 /* LRC Bypass */
3136 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3137 val |= DPIO_LRC_BYPASS;
3138 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3139
3140 mutex_unlock(&dev_priv->dpio_lock);
3141
3142 return 0;
3143}
3144
a4fc5ed6 3145static void
0301b3ac
JN		 3146intel_get_adjust_train(struct intel_dp *intel_dp,
3147 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3148{
3149 uint8_t v = 0;
3150 uint8_t p = 0;
3151 int lane;
1a2eb460
KP		 3152 uint8_t voltage_max;
3153 uint8_t preemph_max;
a4fc5ed6 3154
33a34e4e 3155 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3156 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3157 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3158
3159 if (this_v > v)
3160 v = this_v;
3161 if (this_p > p)
3162 p = this_p;
3163 }
3164
1a2eb460 3165 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3166 if (v >= voltage_max)
3167 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3168
1a2eb460
KP		 3169 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3170 if (p >= preemph_max)
3171 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3172
3173 for (lane = 0; lane < 4; lane++)
33a34e4e 3174 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3175}
3176
3177static uint32_t
f0a3424e 3178intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3179{
3cf2efb1 3180 uint32_t signal_levels = 0;
a4fc5ed6 3181
3cf2efb1 3182 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3184 default:
3185 signal_levels |= DP_VOLTAGE_0_4;
3186 break;
bd60018a 3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3188 signal_levels |= DP_VOLTAGE_0_6;
3189 break;
bd60018a 3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3191 signal_levels |= DP_VOLTAGE_0_8;
3192 break;
bd60018a 3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3194 signal_levels |= DP_VOLTAGE_1_2;
3195 break;
3196 }
3cf2efb1 3197 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3198 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3199 default:
3200 signal_levels |= DP_PRE_EMPHASIS_0;
3201 break;
bd60018a 3202 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3203 signal_levels |= DP_PRE_EMPHASIS_3_5;
3204 break;
bd60018a 3205 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3206 signal_levels |= DP_PRE_EMPHASIS_6;
3207 break;
bd60018a 3208 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3209 signal_levels |= DP_PRE_EMPHASIS_9_5;
3210 break;
3211 }
3212 return signal_levels;
3213}
3214
e3421a18
ZW		 3215/* Gen6's DP voltage swing and pre-emphasis control */
3216static uint32_t
3217intel_gen6_edp_signal_levels(uint8_t train_set)
3218{
3c5a62b5
YL		 3219 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3220 DP_TRAIN_PRE_EMPHASIS_MASK);
3221 switch (signal_levels) {
bd60018a
SJ		 3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3224 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3226 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3229 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3232 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3235 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3236 default:
3c5a62b5
YL		 3237 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3238 "0x%x\n", signal_levels);
3239 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3240 }
3241}
3242
1a2eb460
KP		 3243/* Gen7's DP voltage swing and pre-emphasis control */
3244static uint32_t
3245intel_gen7_edp_signal_levels(uint8_t train_set)
3246{
3247 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3248 DP_TRAIN_PRE_EMPHASIS_MASK);
3249 switch (signal_levels) {
bd60018a 3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3251 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3253 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3255 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3256
bd60018a 3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3258 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3260 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3261
bd60018a 3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3263 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3265 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3266
3267 default:
3268 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3269 "0x%x\n", signal_levels);
3270 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3271 }
3272}
3273
d6c0d722
PZ		 3274/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3275static uint32_t
f0a3424e 3276intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3277{
d6c0d722
PZ		 3278 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3279 DP_TRAIN_PRE_EMPHASIS_MASK);
3280 switch (signal_levels) {
bd60018a 3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3282 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3284 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3286 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3288 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3289
bd60018a 3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3291 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3293 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3295 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3296
bd60018a 3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3298 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3300 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3301 default:
3302 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3303 "0x%x\n", signal_levels);
c5fe6a06 3304 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3305 }
a4fc5ed6
KP		 3306}
3307
f0a3424e
PZ		 3308/* Properly updates "DP" with the correct signal levels. */
3309static void
3310intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3311{
3312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3313 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3314 struct drm_device *dev = intel_dig_port->base.base.dev;
3315 uint32_t signal_levels, mask;
3316 uint8_t train_set = intel_dp->train_set[0];
3317
9576c27f 3318 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3319 signal_levels = intel_hsw_signal_levels(train_set);
3320 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3321 } else if (IS_CHERRYVIEW(dev)) {
3322 signal_levels = intel_chv_signal_levels(intel_dp);
3323 mask = 0;
e2fa6fba
P		 3324 } else if (IS_VALLEYVIEW(dev)) {
3325 signal_levels = intel_vlv_signal_levels(intel_dp);
3326 mask = 0;
bc7d38a4 3327 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3328 signal_levels = intel_gen7_edp_signal_levels(train_set);
3329 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3330 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3331 signal_levels = intel_gen6_edp_signal_levels(train_set);
3332 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3333 } else {
3334 signal_levels = intel_gen4_signal_levels(train_set);
3335 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3336 }
3337
3338 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3339
3340 *DP = (*DP & ~mask) | signal_levels;
3341}
3342
a4fc5ed6 3343static bool
ea5b213a 3344intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3345 uint32_t *DP,
58e10eb9 3346 uint8_t dp_train_pat)
a4fc5ed6 3347{
174edf1f
PZ		 3348 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3349 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3350 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3351 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3352 int ret, len;
a4fc5ed6 3353
7b13b58a 3354 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3355
70aff66c 3356 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3357 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3358
2cdfe6c8
JN		 3359 buf[0] = dp_train_pat;
3360 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3361 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3362 /* don't write DP_TRAINING_LANEx_SET on disable */
3363 len = 1;
3364 } else {
3365 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3366 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3367 len = intel_dp->lane_count + 1;
47ea7542 3368 }
a4fc5ed6 3369
9d1a1031
JN		 3370 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3371 buf, len);
2cdfe6c8
JN		 3372
3373 return ret == len;
a4fc5ed6
KP		 3374}
3375
70aff66c
JN		 3376static bool
3377intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3378 uint8_t dp_train_pat)
3379{
953d22e8 3380 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3381 intel_dp_set_signal_levels(intel_dp, DP);
3382 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3383}
3384
3385static bool
3386intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3387 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3388{
3389 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3390 struct drm_device *dev = intel_dig_port->base.base.dev;
3391 struct drm_i915_private *dev_priv = dev->dev_private;
3392 int ret;
3393
3394 intel_get_adjust_train(intel_dp, link_status);
3395 intel_dp_set_signal_levels(intel_dp, DP);
3396
3397 I915_WRITE(intel_dp->output_reg, *DP);
3398 POSTING_READ(intel_dp->output_reg);
3399
9d1a1031
JN		 3400 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3401 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3402
3403 return ret == intel_dp->lane_count;
3404}
3405
3ab9c637
ID		 3406static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3407{
3408 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3409 struct drm_device *dev = intel_dig_port->base.base.dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411 enum port port = intel_dig_port->port;
3412 uint32_t val;
3413
3414 if (!HAS_DDI(dev))
3415 return;
3416
3417 val = I915_READ(DP_TP_CTL(port));
3418 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3419 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3420 I915_WRITE(DP_TP_CTL(port), val);
3421
3422 /*
3423 * On PORT_A we can have only eDP in SST mode. There the only reason
3424 * we need to set idle transmission mode is to work around a HW issue
3425 * where we enable the pipe while not in idle link-training mode.
3426 * In this case there is requirement to wait for a minimum number of
3427 * idle patterns to be sent.
3428 */
3429 if (port == PORT_A)
3430 return;
3431
3432 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3433 1))
3434 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3435}
3436
33a34e4e 3437/* Enable corresponding port and start training pattern 1 */
c19b0669 3438void
33a34e4e 3439intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3440{
da63a9f2 3441 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3442 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3443 int i;
3444 uint8_t voltage;
cdb0e95b 3445 int voltage_tries, loop_tries;
ea5b213a 3446 uint32_t DP = intel_dp->DP;
6aba5b6c 3447 uint8_t link_config[2];
a4fc5ed6 3448
affa9354 3449 if (HAS_DDI(dev))
c19b0669
PZ		 3450 intel_ddi_prepare_link_retrain(encoder);
3451
3cf2efb1 3452 /* Write the link configuration data */
6aba5b6c
JN		 3453 link_config[0] = intel_dp->link_bw;
3454 link_config[1] = intel_dp->lane_count;
3455 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3456 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3457 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3458
3459 link_config[0] = 0;
3460 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3461 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3462
3463 DP |= DP_PORT_EN;
1a2eb460 3464
70aff66c
JN		 3465 /* clock recovery */
3466 if (!intel_dp_reset_link_train(intel_dp, &DP,
3467 DP_TRAINING_PATTERN_1 |
3468 DP_LINK_SCRAMBLING_DISABLE)) {
3469 DRM_ERROR("failed to enable link training\n");
3470 return;
3471 }
3472
a4fc5ed6 3473 voltage = 0xff;
cdb0e95b
KP		 3474 voltage_tries = 0;
3475 loop_tries = 0;
a4fc5ed6 3476 for (;;) {
70aff66c 3477 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3478
a7c9655f 3479 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3480 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3481 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3482 break;
93f62dad 3483 }
a4fc5ed6 3484
01916270 3485 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3486 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3487 break;
3488 }
3489
3490 /* Check to see if we've tried the max voltage */
3491 for (i = 0; i < intel_dp->lane_count; i++)
3492 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3493 break;
3b4f819d 3494 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3495 ++loop_tries;
3496 if (loop_tries == 5) {
3def84b3 3497 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3498 break;
3499 }
70aff66c
JN		 3500 intel_dp_reset_link_train(intel_dp, &DP,
3501 DP_TRAINING_PATTERN_1 |
3502 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3503 voltage_tries = 0;
3504 continue;
3505 }
a4fc5ed6 3506
3cf2efb1 3507 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3508 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3509 ++voltage_tries;
b06fbda3 3510 if (voltage_tries == 5) {
3def84b3 3511 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3512 break;
3513 }
3514 } else
3515 voltage_tries = 0;
3516 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3517
70aff66c
JN		 3518 /* Update training set as requested by target */
3519 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3520 DRM_ERROR("failed to update link training\n");
3521 break;
3522 }
a4fc5ed6
KP		 3523 }
3524
33a34e4e
JB		 3525 intel_dp->DP = DP;
3526}
3527
c19b0669 3528void
33a34e4e
JB		 3529intel_dp_complete_link_train(struct intel_dp *intel_dp)
3530{
33a34e4e 3531 bool channel_eq = false;
37f80975 3532 int tries, cr_tries;
33a34e4e 3533 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3534 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3535
3536 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3537 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3538 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3539
a4fc5ed6 3540 /* channel equalization */
70aff66c 3541 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3542 training_pattern |
70aff66c
JN		 3543 DP_LINK_SCRAMBLING_DISABLE)) {
3544 DRM_ERROR("failed to start channel equalization\n");
3545 return;
3546 }
3547
a4fc5ed6 3548 tries = 0;
37f80975 3549 cr_tries = 0;
a4fc5ed6
KP		 3550 channel_eq = false;
3551 for (;;) {
70aff66c 3552 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3553
37f80975
JB		 3554 if (cr_tries > 5) {
3555 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3556 break;
3557 }
3558
a7c9655f 3559 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3560 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3561 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3562 break;
70aff66c 3563 }
a4fc5ed6 3564
37f80975 3565 /* Make sure clock is still ok */
01916270 3566 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3567 intel_dp_start_link_train(intel_dp);
70aff66c 3568 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3569 training_pattern |
70aff66c 3570 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3571 cr_tries++;
3572 continue;
3573 }
3574
1ffdff13 3575 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3576 channel_eq = true;
3577 break;
3578 }
a4fc5ed6 3579
37f80975
JB		 3580 /* Try 5 times, then try clock recovery if that fails */
3581 if (tries > 5) {
3582 intel_dp_link_down(intel_dp);
3583 intel_dp_start_link_train(intel_dp);
70aff66c 3584 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3585 training_pattern |
70aff66c 3586 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3587 tries = 0;
3588 cr_tries++;
3589 continue;
3590 }
a4fc5ed6 3591
70aff66c
JN		 3592 /* Update training set as requested by target */
3593 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3594 DRM_ERROR("failed to update link training\n");
3595 break;
3596 }
3cf2efb1 3597 ++tries;
869184a6 3598 }
3cf2efb1 3599
3ab9c637
ID		 3600 intel_dp_set_idle_link_train(intel_dp);
3601
3602 intel_dp->DP = DP;
3603
d6c0d722 3604 if (channel_eq)
07f42258 3605 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3606
3ab9c637
ID		 3607}
3608
3609void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3610{
70aff66c 3611 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3612 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3613}
3614
3615static void
ea5b213a 3616intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3617{
da63a9f2 3618 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3619 enum port port = intel_dig_port->port;
da63a9f2 3620 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3621 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3622 struct intel_crtc *intel_crtc =
3623 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3624 uint32_t DP = intel_dp->DP;
a4fc5ed6 3625
bc76e320 3626 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3627 return;
3628
0c33d8d7 3629 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3630 return;
3631
28c97730 3632 DRM_DEBUG_KMS("\n");
32f9d658 3633
bc7d38a4 3634 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3635 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3636 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3637 } else {
aad3d14d
VS		 3638 if (IS_CHERRYVIEW(dev))
3639 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3640 else
3641 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3642 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3643 }
fe255d00 3644 POSTING_READ(intel_dp->output_reg);
5eb08b69 3645
493a7081 3646 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3647 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3648 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3649
5bddd17f
EA		 3650 /* Hardware workaround: leaving our transcoder select
3651 * set to transcoder B while it's off will prevent the
3652 * corresponding HDMI output on transcoder A.
3653 *
3654 * Combine this with another hardware workaround:
3655 * transcoder select bit can only be cleared while the
3656 * port is enabled.
3657 */
3658 DP &= ~DP_PIPEB_SELECT;
3659 I915_WRITE(intel_dp->output_reg, DP);
3660
3661 /* Changes to enable or select take place the vblank
3662 * after being written.
3663 */
ff50afe9
DV		 3664 if (WARN_ON(crtc == NULL)) {
3665 /* We should never try to disable a port without a crtc
3666 * attached. For paranoia keep the code around for a
3667 * bit. */
31acbcc4
CW		 3668 POSTING_READ(intel_dp->output_reg);
3669 msleep(50);
3670 } else
ab527efc 3671 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3672 }
3673
832afda6 3674 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3675 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3676 POSTING_READ(intel_dp->output_reg);
f01eca2e 3677 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3678}
3679
26d61aad
KP		 3680static bool
3681intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3682{
a031d709
RV		 3683 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3684 struct drm_device *dev = dig_port->base.base.dev;
3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686
9d1a1031
JN		 3687 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3688 sizeof(intel_dp->dpcd)) < 0)
edb39244 3689 return false; /* aux transfer failed */
92fd8fd1 3690
a8e98153 3691 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3692
edb39244
AJ		 3693 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3694 return false; /* DPCD not present */
3695
2293bb5c
SK		 3696 /* Check if the panel supports PSR */
3697 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3698 if (is_edp(intel_dp)) {
9d1a1031
JN		 3699 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3700 intel_dp->psr_dpcd,
3701 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3702 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3703 dev_priv->psr.sink_support = true;
50003939 3704 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3705 }
50003939
JN		 3706 }
3707
06ea66b6
TP		 3708 /* Training Pattern 3 support */
3709 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3710 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3711 intel_dp->use_tps3 = true;
3712 DRM_DEBUG_KMS("Displayport TPS3 supported");
3713 } else
3714 intel_dp->use_tps3 = false;
3715
edb39244
AJ		 3716 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3717 DP_DWN_STRM_PORT_PRESENT))
3718 return true; /* native DP sink */
3719
3720 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3721 return true; /* no per-port downstream info */
3722
9d1a1031
JN		 3723 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3724 intel_dp->downstream_ports,
3725 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3726 return false; /* downstream port status fetch failed */
3727
3728 return true;
92fd8fd1
KP		 3729}
3730
0d198328
AJ		 3731static void
3732intel_dp_probe_oui(struct intel_dp *intel_dp)
3733{
3734 u8 buf[3];
3735
3736 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3737 return;
3738
24f3e092 3739 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3740
9d1a1031 3741 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3742 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3743 buf[0], buf[1], buf[2]);
3744
9d1a1031 3745 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3746 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3747 buf[0], buf[1], buf[2]);
351cfc34 3748
1e0560e0 3749 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3750}
3751
0e32b39c
DA		 3752static bool
3753intel_dp_probe_mst(struct intel_dp *intel_dp)
3754{
3755 u8 buf[1];
3756
3757 if (!intel_dp->can_mst)
3758 return false;
3759
3760 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3761 return false;
3762
d337a341 3763 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3764 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3765 if (buf[0] & DP_MST_CAP) {
3766 DRM_DEBUG_KMS("Sink is MST capable\n");
3767 intel_dp->is_mst = true;
3768 } else {
3769 DRM_DEBUG_KMS("Sink is not MST capable\n");
3770 intel_dp->is_mst = false;
3771 }
3772 }
1e0560e0 3773 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3774
3775 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3776 return intel_dp->is_mst;
3777}
3778
d2e216d0
RV		 3779int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3780{
3781 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3782 struct drm_device *dev = intel_dig_port->base.base.dev;
3783 struct intel_crtc *intel_crtc =
3784 to_intel_crtc(intel_dig_port->base.base.crtc);
3785 u8 buf[1];
3786
9d1a1031 3787 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3788 return -EAGAIN;
3789
3790 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3791 return -ENOTTY;
3792
9d1a1031
JN		 3793 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3794 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3795 return -EAGAIN;
3796
3797 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3798 intel_wait_for_vblank(dev, intel_crtc->pipe);
3799 intel_wait_for_vblank(dev, intel_crtc->pipe);
3800
9d1a1031 3801 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3802 return -EAGAIN;
3803
9d1a1031 3804 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3805 return 0;
3806}
3807
a60f0e38
JB		 3808static bool
3809intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3810{
9d1a1031
JN		 3811 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3812 DP_DEVICE_SERVICE_IRQ_VECTOR,
3813 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3814}
3815
0e32b39c
DA		 3816static bool
3817intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3818{
3819 int ret;
3820
3821 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3822 DP_SINK_COUNT_ESI,
3823 sink_irq_vector, 14);
3824 if (ret != 14)
3825 return false;
3826
3827 return true;
3828}
3829
a60f0e38
JB		 3830static void
3831intel_dp_handle_test_request(struct intel_dp *intel_dp)
3832{
3833 /* NAK by default */
9d1a1031 3834 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3835}
3836
0e32b39c
DA		 3837static int
3838intel_dp_check_mst_status(struct intel_dp *intel_dp)
3839{
3840 bool bret;
3841
3842 if (intel_dp->is_mst) {
3843 u8 esi[16] = { 0 };
3844 int ret = 0;
3845 int retry;
3846 bool handled;
3847 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3848go_again:
3849 if (bret == true) {
3850
3851 /* check link status - esi[10] = 0x200c */
3852 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3853 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3854 intel_dp_start_link_train(intel_dp);
3855 intel_dp_complete_link_train(intel_dp);
3856 intel_dp_stop_link_train(intel_dp);
3857 }
3858
3859 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3860 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3861
3862 if (handled) {
3863 for (retry = 0; retry < 3; retry++) {
3864 int wret;
3865 wret = drm_dp_dpcd_write(&intel_dp->aux,
3866 DP_SINK_COUNT_ESI+1,
3867 &esi[1], 3);
3868 if (wret == 3) {
3869 break;
3870 }
3871 }
3872
3873 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3874 if (bret == true) {
3875 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3876 goto go_again;
3877 }
3878 } else
3879 ret = 0;
3880
3881 return ret;
3882 } else {
3883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3884 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3885 intel_dp->is_mst = false;
3886 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3887 /* send a hotplug event */
3888 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3889 }
3890 }
3891 return -EINVAL;
3892}
3893
a4fc5ed6
KP		 3894/*
3895 * According to DP spec
3896 * 5.1.2:
3897 * 1. Read DPCD
3898 * 2. Configure link according to Receiver Capabilities
3899 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3900 * 4. Check link status on receipt of hot-plug interrupt
3901 */
00c09d70 3902void
ea5b213a 3903intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3904{
5b215bcf 3905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3906 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3907 u8 sink_irq_vector;
93f62dad 3908 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3909
5b215bcf
DA		 3910 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3911
da63a9f2 3912 if (!intel_encoder->connectors_active)
d2b996ac 3913 return;
59cd09e1 3914
da63a9f2 3915 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3916 return;
3917
1a125d8a
ID		 3918 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3919 return;
3920
92fd8fd1 3921 /* Try to read receiver status if the link appears to be up */
93f62dad 3922 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3923 return;
3924 }
3925
92fd8fd1 3926 /* Now read the DPCD to see if it's actually running */
26d61aad 3927 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3928 return;
3929 }
3930
a60f0e38
JB		 3931 /* Try to read the source of the interrupt */
3932 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3933 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3934 /* Clear interrupt source */
9d1a1031
JN		 3935 drm_dp_dpcd_writeb(&intel_dp->aux,
3936 DP_DEVICE_SERVICE_IRQ_VECTOR,
3937 sink_irq_vector);
a60f0e38
JB		 3938
3939 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3940 intel_dp_handle_test_request(intel_dp);
3941 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3942 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3943 }
3944
1ffdff13 3945 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3946 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3947 intel_encoder->base.name);
33a34e4e
JB		 3948 intel_dp_start_link_train(intel_dp);
3949 intel_dp_complete_link_train(intel_dp);
3ab9c637 3950 intel_dp_stop_link_train(intel_dp);
33a34e4e 3951 }
a4fc5ed6 3952}
a4fc5ed6 3953
caf9ab24 3954/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3955static enum drm_connector_status
26d61aad 3956intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3957{
caf9ab24 3958 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3959 uint8_t type;
3960
3961 if (!intel_dp_get_dpcd(intel_dp))
3962 return connector_status_disconnected;
3963
3964 /* if there's no downstream port, we're done */
3965 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3966 return connector_status_connected;
caf9ab24
AJ		 3967
3968 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3969 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3970 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3971 uint8_t reg;
9d1a1031
JN		 3972
3973 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3974 &reg, 1) < 0)
caf9ab24 3975 return connector_status_unknown;
9d1a1031 3976
23235177
AJ		 3977 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3978 : connector_status_disconnected;
caf9ab24
AJ		 3979 }
3980
3981 /* If no HPD, poke DDC gently */
0b99836f 3982 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3983 return connector_status_connected;
caf9ab24
AJ		 3984
3985 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3986 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3987 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3988 if (type == DP_DS_PORT_TYPE_VGA ||
3989 type == DP_DS_PORT_TYPE_NON_EDID)
3990 return connector_status_unknown;
3991 } else {
3992 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3993 DP_DWN_STRM_PORT_TYPE_MASK;
3994 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3995 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3996 return connector_status_unknown;
3997 }
caf9ab24
AJ		 3998
3999 /* Anything else is out of spec, warn and ignore */
4000 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4001 return connector_status_disconnected;
71ba9000
AJ		 4002}
4003
d410b56d
CW		 4004static enum drm_connector_status
4005edp_detect(struct intel_dp *intel_dp)
4006{
4007 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4008 enum drm_connector_status status;
4009
4010 status = intel_panel_detect(dev);
4011 if (status == connector_status_unknown)
4012 status = connector_status_connected;
4013
4014 return status;
4015}
4016
5eb08b69 4017static enum drm_connector_status
a9756bb5 4018ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4019{
30add22d 4020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4021 struct drm_i915_private *dev_priv = dev->dev_private;
4022 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4023
1b469639
DL		 4024 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4025 return connector_status_disconnected;
4026
26d61aad 4027 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4028}
4029
a4fc5ed6 4030static enum drm_connector_status
a9756bb5 4031g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 4032{
30add22d 4033 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 4034 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 4035 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 4036 uint32_t bit;
5eb08b69 4037
232a6ee9
TP		 4038 if (IS_VALLEYVIEW(dev)) {
4039 switch (intel_dig_port->port) {
4040 case PORT_B:
4041 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4042 break;
4043 case PORT_C:
4044 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4045 break;
4046 case PORT_D:
4047 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4048 break;
4049 default:
4050 return connector_status_unknown;
4051 }
4052 } else {
4053 switch (intel_dig_port->port) {
4054 case PORT_B:
4055 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4056 break;
4057 case PORT_C:
4058 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4059 break;
4060 case PORT_D:
4061 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4062 break;
4063 default:
4064 return connector_status_unknown;
4065 }
a4fc5ed6
KP		 4066 }
4067
10f76a38 4068 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 4069 return connector_status_disconnected;
4070
26d61aad 4071 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4072}
4073
8c241fef 4074static struct edid *
beb60608 4075intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4076{
beb60608 4077 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4078
9cd300e0
JN		 4079 /* use cached edid if we have one */
4080 if (intel_connector->edid) {
9cd300e0
JN		 4081 /* invalid edid */
4082 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4083 return NULL;
4084
55e9edeb 4085 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4086 } else
4087 return drm_get_edid(&intel_connector->base,
4088 &intel_dp->aux.ddc);
4089}
8c241fef 4090
beb60608
CW		 4091static void
4092intel_dp_set_edid(struct intel_dp *intel_dp)
4093{
4094 struct intel_connector *intel_connector = intel_dp->attached_connector;
4095 struct edid *edid;
4096
4097 edid = intel_dp_get_edid(intel_dp);
4098 intel_connector->detect_edid = edid;
4099
4100 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4101 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4102 else
4103 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4104}
4105
beb60608
CW		 4106static void
4107intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4108{
beb60608 4109 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4110
beb60608
CW		 4111 kfree(intel_connector->detect_edid);
4112 intel_connector->detect_edid = NULL;
9cd300e0 4113
beb60608
CW		 4114 intel_dp->has_audio = false;
4115}
d6f24d0f 4116
beb60608
CW		 4117static enum intel_display_power_domain
4118intel_dp_power_get(struct intel_dp *dp)
4119{
4120 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4121 enum intel_display_power_domain power_domain;
4122
4123 power_domain = intel_display_port_power_domain(encoder);
4124 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4125
4126 return power_domain;
4127}
4128
4129static void
4130intel_dp_power_put(struct intel_dp *dp,
4131 enum intel_display_power_domain power_domain)
4132{
4133 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4134 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4135}
4136
a9756bb5
ZW		 4137static enum drm_connector_status
4138intel_dp_detect(struct drm_connector *connector, bool force)
4139{
4140 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4141 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4142 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4143 struct drm_device *dev = connector->dev;
a9756bb5 4144 enum drm_connector_status status;
671dedd2 4145 enum intel_display_power_domain power_domain;
0e32b39c 4146 bool ret;
a9756bb5 4147
164c8598 4148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4149 connector->base.id, connector->name);
beb60608 4150 intel_dp_unset_edid(intel_dp);
164c8598 4151
0e32b39c
DA		 4152 if (intel_dp->is_mst) {
4153 /* MST devices are disconnected from a monitor POV */
4154 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4155 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4156 return connector_status_disconnected;
0e32b39c
DA		 4157 }
4158
beb60608 4159 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4160
d410b56d
CW		 4161 /* Can't disconnect eDP, but you can close the lid... */
4162 if (is_edp(intel_dp))
4163 status = edp_detect(intel_dp);
4164 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4165 status = ironlake_dp_detect(intel_dp);
4166 else
4167 status = g4x_dp_detect(intel_dp);
4168 if (status != connector_status_connected)
c8c8fb33 4169 goto out;
a9756bb5 4170
0d198328
AJ		 4171 intel_dp_probe_oui(intel_dp);
4172
0e32b39c
DA		 4173 ret = intel_dp_probe_mst(intel_dp);
4174 if (ret) {
4175 /* if we are in MST mode then this connector
4176 won't appear connected or have anything with EDID on it */
4177 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4178 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4179 status = connector_status_disconnected;
4180 goto out;
4181 }
4182
beb60608 4183 intel_dp_set_edid(intel_dp);
a9756bb5 4184
d63885da
PZ		 4185 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4186 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4187 status = connector_status_connected;
4188
4189out:
beb60608 4190 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4191 return status;
a4fc5ed6
KP		 4192}
4193
beb60608
CW		 4194static void
4195intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4196{
df0e9248 4197 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4198 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4199 enum intel_display_power_domain power_domain;
a4fc5ed6 4200
beb60608
CW		 4201 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4202 connector->base.id, connector->name);
4203 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4204
beb60608
CW		 4205 if (connector->status != connector_status_connected)
4206 return;
671dedd2 4207
beb60608
CW		 4208 power_domain = intel_dp_power_get(intel_dp);
4209
4210 intel_dp_set_edid(intel_dp);
4211
4212 intel_dp_power_put(intel_dp, power_domain);
4213
4214 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4215 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4216}
4217
4218static int intel_dp_get_modes(struct drm_connector *connector)
4219{
4220 struct intel_connector *intel_connector = to_intel_connector(connector);
4221 struct edid *edid;
4222
4223 edid = intel_connector->detect_edid;
4224 if (edid) {
4225 int ret = intel_connector_update_modes(connector, edid);
4226 if (ret)
4227 return ret;
4228 }
32f9d658 4229
f8779fda 4230 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4231 if (is_edp(intel_attached_dp(connector)) &&
4232 intel_connector->panel.fixed_mode) {
f8779fda 4233 struct drm_display_mode *mode;
beb60608
CW		 4234
4235 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4236 intel_connector->panel.fixed_mode);
f8779fda 4237 if (mode) {
32f9d658
ZW		 4238 drm_mode_probed_add(connector, mode);
4239 return 1;
4240 }
4241 }
beb60608 4242
32f9d658 4243 return 0;
a4fc5ed6
KP		 4244}
4245
1aad7ac0
CW		 4246static bool
4247intel_dp_detect_audio(struct drm_connector *connector)
4248{
1aad7ac0 4249 bool has_audio = false;
beb60608 4250 struct edid *edid;
1aad7ac0 4251
beb60608
CW		 4252 edid = to_intel_connector(connector)->detect_edid;
4253 if (edid)
1aad7ac0 4254 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4255
1aad7ac0
CW		 4256 return has_audio;
4257}
4258
f684960e
CW		 4259static int
4260intel_dp_set_property(struct drm_connector *connector,
4261 struct drm_property *property,
4262 uint64_t val)
4263{
e953fd7b 4264 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4265 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4266 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4267 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4268 int ret;
4269
662595df 4270 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4271 if (ret)
4272 return ret;
4273
3f43c48d 4274 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4275 int i = val;
4276 bool has_audio;
4277
4278 if (i == intel_dp->force_audio)
f684960e
CW		 4279 return 0;
4280
1aad7ac0 4281 intel_dp->force_audio = i;
f684960e 4282
c3e5f67b 4283 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4284 has_audio = intel_dp_detect_audio(connector);
4285 else
c3e5f67b 4286 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4287
4288 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4289 return 0;
4290
1aad7ac0 4291 intel_dp->has_audio = has_audio;
f684960e
CW		 4292 goto done;
4293 }
4294
e953fd7b 4295 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4296 bool old_auto = intel_dp->color_range_auto;
4297 uint32_t old_range = intel_dp->color_range;
4298
55bc60db
VS		 4299 switch (val) {
4300 case INTEL_BROADCAST_RGB_AUTO:
4301 intel_dp->color_range_auto = true;
4302 break;
4303 case INTEL_BROADCAST_RGB_FULL:
4304 intel_dp->color_range_auto = false;
4305 intel_dp->color_range = 0;
4306 break;
4307 case INTEL_BROADCAST_RGB_LIMITED:
4308 intel_dp->color_range_auto = false;
4309 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4310 break;
4311 default:
4312 return -EINVAL;
4313 }
ae4edb80
DV		 4314
4315 if (old_auto == intel_dp->color_range_auto &&
4316 old_range == intel_dp->color_range)
4317 return 0;
4318
e953fd7b
CW		 4319 goto done;
4320 }
4321
53b41837
YN		 4322 if (is_edp(intel_dp) &&
4323 property == connector->dev->mode_config.scaling_mode_property) {
4324 if (val == DRM_MODE_SCALE_NONE) {
4325 DRM_DEBUG_KMS("no scaling not supported\n");
4326 return -EINVAL;
4327 }
4328
4329 if (intel_connector->panel.fitting_mode == val) {
4330 /* the eDP scaling property is not changed */
4331 return 0;
4332 }
4333 intel_connector->panel.fitting_mode = val;
4334
4335 goto done;
4336 }
4337
f684960e
CW		 4338 return -EINVAL;
4339
4340done:
c0c36b94
CW		 4341 if (intel_encoder->base.crtc)
4342 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4343
4344 return 0;
4345}
4346
a4fc5ed6 4347static void
73845adf 4348intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4349{
1d508706 4350 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4351
beb60608
CW		 4352 intel_dp_unset_edid(intel_attached_dp(connector));
4353
9cd300e0
JN		 4354 if (!IS_ERR_OR_NULL(intel_connector->edid))
4355 kfree(intel_connector->edid);
4356
acd8db10
PZ		 4357 /* Can't call is_edp() since the encoder may have been destroyed
4358 * already. */
4359 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4360 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4361
a4fc5ed6 4362 drm_connector_cleanup(connector);
55f78c43 4363 kfree(connector);
a4fc5ed6
KP		 4364}
4365
00c09d70 4366void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4367{
da63a9f2
PZ		 4368 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4369 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4370
4f71d0cb 4371 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4372 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4373 drm_encoder_cleanup(encoder);
bd943159
KP		 4374 if (is_edp(intel_dp)) {
4375 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4376 pps_lock(intel_dp);
4be73780 4377 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4378 pps_unlock(intel_dp);
4379
01527b31
CT		 4380 if (intel_dp->edp_notifier.notifier_call) {
4381 unregister_reboot_notifier(&intel_dp->edp_notifier);
4382 intel_dp->edp_notifier.notifier_call = NULL;
4383 }
bd943159 4384 }
da63a9f2 4385 kfree(intel_dig_port);
24d05927
DV		 4386}
4387
07f9cd0b
ID		 4388static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4389{
4390 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4391
4392 if (!is_edp(intel_dp))
4393 return;
4394
773538e8 4395 pps_lock(intel_dp);
07f9cd0b 4396 edp_panel_vdd_off_sync(intel_dp);
773538e8 4397 pps_unlock(intel_dp);
07f9cd0b
ID		 4398}
4399
6d93c0c4
ID		 4400static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4401{
4402 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4403}
4404
a4fc5ed6 4405static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4406 .dpms = intel_connector_dpms,
a4fc5ed6 4407 .detect = intel_dp_detect,
beb60608 4408 .force = intel_dp_force,
a4fc5ed6 4409 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4410 .set_property = intel_dp_set_property,
73845adf 4411 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4412};
4413
4414static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4415 .get_modes = intel_dp_get_modes,
4416 .mode_valid = intel_dp_mode_valid,
df0e9248 4417 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4418};
4419
a4fc5ed6 4420static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4421 .reset = intel_dp_encoder_reset,
24d05927 4422 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4423};
4424
0e32b39c 4425void
21d40d37 4426intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4427{
0e32b39c 4428 return;
c8110e52 4429}
6207937d 4430
13cf5504
DA		 4431bool
4432intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4433{
4434 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4435 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4436 struct drm_device *dev = intel_dig_port->base.base.dev;
4437 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4438 enum intel_display_power_domain power_domain;
4439 bool ret = true;
4440
0e32b39c
DA		 4441 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4442 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4443
26fbb774
VS		 4444 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4445 port_name(intel_dig_port->port),
0e32b39c 4446 long_hpd ? "long" : "short");
13cf5504 4447
1c767b33
ID		 4448 power_domain = intel_display_port_power_domain(intel_encoder);
4449 intel_display_power_get(dev_priv, power_domain);
4450
0e32b39c
DA		 4451 if (long_hpd) {
4452 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4453 goto mst_fail;
4454
4455 if (!intel_dp_get_dpcd(intel_dp)) {
4456 goto mst_fail;
4457 }
4458
4459 intel_dp_probe_oui(intel_dp);
4460
4461 if (!intel_dp_probe_mst(intel_dp))
4462 goto mst_fail;
4463
4464 } else {
4465 if (intel_dp->is_mst) {
1c767b33 4466 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4467 goto mst_fail;
4468 }
4469
4470 if (!intel_dp->is_mst) {
4471 /*
4472 * we'll check the link status via the normal hot plug path later -
4473 * but for short hpds we should check it now
4474 */
5b215bcf 4475 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4476 intel_dp_check_link_status(intel_dp);
5b215bcf 4477 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4478 }
4479 }
1c767b33
ID		 4480 ret = false;
4481 goto put_power;
0e32b39c
DA		 4482mst_fail:
4483 /* if we were in MST mode, and device is not there get out of MST mode */
4484 if (intel_dp->is_mst) {
4485 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4486 intel_dp->is_mst = false;
4487 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4488 }
1c767b33
ID		 4489put_power:
4490 intel_display_power_put(dev_priv, power_domain);
4491
4492 return ret;
13cf5504
DA		 4493}
4494
e3421a18
ZW		 4495/* Return which DP Port should be selected for Transcoder DP control */
4496int
0206e353 4497intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4498{
4499 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4500 struct intel_encoder *intel_encoder;
4501 struct intel_dp *intel_dp;
e3421a18 4502
fa90ecef
PZ		 4503 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4504 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4505
fa90ecef
PZ		 4506 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4507 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4508 return intel_dp->output_reg;
e3421a18 4509 }
ea5b213a 4510
e3421a18
ZW		 4511 return -1;
4512}
4513
36e83a18 4514/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4515bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4516{
4517 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4518 union child_device_config *p_child;
36e83a18 4519 int i;
5d8a7752
VS		 4520 static const short port_mapping[] = {
4521 [PORT_B] = PORT_IDPB,
4522 [PORT_C] = PORT_IDPC,
4523 [PORT_D] = PORT_IDPD,
4524 };
36e83a18 4525
3b32a35b
VS		 4526 if (port == PORT_A)
4527 return true;
4528
41aa3448 4529 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4530 return false;
4531
41aa3448
RV		 4532 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4533 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4534
5d8a7752 4535 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4536 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4537 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4538 return true;
4539 }
4540 return false;
4541}
4542
0e32b39c 4543void
f684960e
CW		 4544intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4545{
53b41837
YN		 4546 struct intel_connector *intel_connector = to_intel_connector(connector);
4547
3f43c48d 4548 intel_attach_force_audio_property(connector);
e953fd7b 4549 intel_attach_broadcast_rgb_property(connector);
55bc60db 4550 intel_dp->color_range_auto = true;
53b41837
YN		 4551
4552 if (is_edp(intel_dp)) {
4553 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4554 drm_object_attach_property(
4555 &connector->base,
53b41837 4556 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4557 DRM_MODE_SCALE_ASPECT);
4558 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4559 }
f684960e
CW		 4560}
4561
dada1a9f
ID		 4562static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4563{
4564 intel_dp->last_power_cycle = jiffies;
4565 intel_dp->last_power_on = jiffies;
4566 intel_dp->last_backlight_off = jiffies;
4567}
4568
67a54566
DV		 4569static void
4570intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4571 struct intel_dp *intel_dp,
4572 struct edp_power_seq *out)
67a54566
DV		 4573{
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 struct edp_power_seq cur, vbt, spec, final;
4576 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4577 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4578
e39b999a
VS		 4579 lockdep_assert_held(&dev_priv->pps_mutex);
4580
453c5420 4581 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4582 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4583 pp_on_reg = PCH_PP_ON_DELAYS;
4584 pp_off_reg = PCH_PP_OFF_DELAYS;
4585 pp_div_reg = PCH_PP_DIVISOR;
4586 } else {
bf13e81b
JN		 4587 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4588
4589 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4590 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4591 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4592 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4593 }
67a54566
DV		 4594
4595 /* Workaround: Need to write PP_CONTROL with the unlock key as
4596 * the very first thing. */
453c5420 4597 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4598 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4599
453c5420
JB		 4600 pp_on = I915_READ(pp_on_reg);
4601 pp_off = I915_READ(pp_off_reg);
4602 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4603
4604 /* Pull timing values out of registers */
4605 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4606 PANEL_POWER_UP_DELAY_SHIFT;
4607
4608 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4609 PANEL_LIGHT_ON_DELAY_SHIFT;
4610
4611 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4612 PANEL_LIGHT_OFF_DELAY_SHIFT;
4613
4614 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4615 PANEL_POWER_DOWN_DELAY_SHIFT;
4616
4617 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4618 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4619
4620 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4621 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4622
41aa3448 4623 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4624
4625 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4626 * our hw here, which are all in 100usec. */
4627 spec.t1_t3 = 210 * 10;
4628 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4629 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4630 spec.t10 = 500 * 10;
4631 /* This one is special and actually in units of 100ms, but zero
4632 * based in the hw (so we need to add 100 ms). But the sw vbt
4633 * table multiplies it with 1000 to make it in units of 100usec,
4634 * too. */
4635 spec.t11_t12 = (510 + 100) * 10;
4636
4637 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4638 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4639
4640 /* Use the max of the register settings and vbt. If both are
4641 * unset, fall back to the spec limits. */
4642#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4643 spec.field : \
4644 max(cur.field, vbt.field))
4645 assign_final(t1_t3);
4646 assign_final(t8);
4647 assign_final(t9);
4648 assign_final(t10);
4649 assign_final(t11_t12);
4650#undef assign_final
4651
4652#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4653 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4654 intel_dp->backlight_on_delay = get_delay(t8);
4655 intel_dp->backlight_off_delay = get_delay(t9);
4656 intel_dp->panel_power_down_delay = get_delay(t10);
4657 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4658#undef get_delay
4659
f30d26e4
JN		 4660 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4661 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4662 intel_dp->panel_power_cycle_delay);
4663
4664 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4665 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4666
4667 if (out)
4668 *out = final;
4669}
4670
4671static void
4672intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4673 struct intel_dp *intel_dp,
4674 struct edp_power_seq *seq)
4675{
4676 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4677 u32 pp_on, pp_off, pp_div, port_sel = 0;
4678 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4679 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4680 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4681
e39b999a
VS		 4682 lockdep_assert_held(&dev_priv->pps_mutex);
4683
453c5420
JB		 4684 if (HAS_PCH_SPLIT(dev)) {
4685 pp_on_reg = PCH_PP_ON_DELAYS;
4686 pp_off_reg = PCH_PP_OFF_DELAYS;
4687 pp_div_reg = PCH_PP_DIVISOR;
4688 } else {
bf13e81b
JN		 4689 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4690
4691 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4692 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4693 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4694 }
4695
b2f19d1a
PZ		 4696 /*
4697 * And finally store the new values in the power sequencer. The
4698 * backlight delays are set to 1 because we do manual waits on them. For
4699 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4700 * we'll end up waiting for the backlight off delay twice: once when we
4701 * do the manual sleep, and once when we disable the panel and wait for
4702 * the PP_STATUS bit to become zero.
4703 */
f30d26e4 4704 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4705 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4706 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4707 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4708 /* Compute the divisor for the pp clock, simply match the Bspec
4709 * formula. */
453c5420 4710 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4711 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4712 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4713
4714 /* Haswell doesn't have any port selection bits for the panel
4715 * power sequencer any more. */
bc7d38a4 4716 if (IS_VALLEYVIEW(dev)) {
ad933b56 4717 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4718 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4719 if (port == PORT_A)
a24c144c 4720 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4721 else
a24c144c 4722 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4723 }
4724
453c5420
JB		 4725 pp_on |= port_sel;
4726
4727 I915_WRITE(pp_on_reg, pp_on);
4728 I915_WRITE(pp_off_reg, pp_off);
4729 I915_WRITE(pp_div_reg, pp_div);
67a54566 4730
67a54566 4731 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4732 I915_READ(pp_on_reg),
4733 I915_READ(pp_off_reg),
4734 I915_READ(pp_div_reg));
f684960e
CW		 4735}
4736
439d7ac0
PB		 4737void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4738{
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 struct intel_encoder *encoder;
4741 struct intel_dp *intel_dp = NULL;
4742 struct intel_crtc_config *config = NULL;
4743 struct intel_crtc *intel_crtc = NULL;
4744 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4745 u32 reg, val;
4746 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4747
4748 if (refresh_rate <= 0) {
4749 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4750 return;
4751 }
4752
4753 if (intel_connector == NULL) {
4754 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4755 return;
4756 }
4757
1fcc9d1c
DV		 4758 /*
4759 * FIXME: This needs proper synchronization with psr state. But really
4760 * hard to tell without seeing the user of this function of this code.
4761 * Check locking and ordering once that lands.
4762 */
439d7ac0
PB		 4763 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4764 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4765 return;
4766 }
4767
4768 encoder = intel_attached_encoder(&intel_connector->base);
4769 intel_dp = enc_to_intel_dp(&encoder->base);
4770 intel_crtc = encoder->new_crtc;
4771
4772 if (!intel_crtc) {
4773 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4774 return;
4775 }
4776
4777 config = &intel_crtc->config;
4778
4779 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4780 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4781 return;
4782 }
4783
4784 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4785 index = DRRS_LOW_RR;
4786
4787 if (index == intel_dp->drrs_state.refresh_rate_type) {
4788 DRM_DEBUG_KMS(
4789 "DRRS requested for previously set RR...ignoring\n");
4790 return;
4791 }
4792
4793 if (!intel_crtc->active) {
4794 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4795 return;
4796 }
4797
4798 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4799 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4800 val = I915_READ(reg);
4801 if (index > DRRS_HIGH_RR) {
4802 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4803 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4804 } else {
4805 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4806 }
4807 I915_WRITE(reg, val);
4808 }
4809
4810 /*
4811 * mutex taken to ensure that there is no race between differnt
4812 * drrs calls trying to update refresh rate. This scenario may occur
4813 * in future when idleness detection based DRRS in kernel and
4814 * possible calls from user space to set differnt RR are made.
4815 */
4816
4817 mutex_lock(&intel_dp->drrs_state.mutex);
4818
4819 intel_dp->drrs_state.refresh_rate_type = index;
4820
4821 mutex_unlock(&intel_dp->drrs_state.mutex);
4822
4823 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4824}
4825
4f9db5b5
PB		 4826static struct drm_display_mode *
4827intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4828 struct intel_connector *intel_connector,
4829 struct drm_display_mode *fixed_mode)
4830{
4831 struct drm_connector *connector = &intel_connector->base;
4832 struct intel_dp *intel_dp = &intel_dig_port->dp;
4833 struct drm_device *dev = intel_dig_port->base.base.dev;
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 struct drm_display_mode *downclock_mode = NULL;
4836
4837 if (INTEL_INFO(dev)->gen <= 6) {
4838 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4839 return NULL;
4840 }
4841
4842 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4843 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4844 return NULL;
4845 }
4846
4847 downclock_mode = intel_find_panel_downclock
4848 (dev, fixed_mode, connector);
4849
4850 if (!downclock_mode) {
4079b8d1 4851 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4852 return NULL;
4853 }
4854
439d7ac0
PB		 4855 dev_priv->drrs.connector = intel_connector;
4856
4857 mutex_init(&intel_dp->drrs_state.mutex);
4858
4f9db5b5
PB		 4859 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4860
4861 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4862 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4863 return downclock_mode;
4864}
4865
aba86890
ID		 4866void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4867{
4868 struct drm_device *dev = intel_encoder->base.dev;
4869 struct drm_i915_private *dev_priv = dev->dev_private;
4870 struct intel_dp *intel_dp;
4871 enum intel_display_power_domain power_domain;
4872
4873 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4874 return;
4875
4876 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4877
4878 pps_lock(intel_dp);
4879
aba86890 4880 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4881 goto out;
aba86890
ID		 4882 /*
4883 * The VDD bit needs a power domain reference, so if the bit is
4884 * already enabled when we boot or resume, grab this reference and
4885 * schedule a vdd off, so we don't hold on to the reference
4886 * indefinitely.
4887 */
4888 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4889 power_domain = intel_display_port_power_domain(intel_encoder);
4890 intel_display_power_get(dev_priv, power_domain);
4891
4892 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4893 out:
773538e8 4894 pps_unlock(intel_dp);
aba86890
ID		 4895}
4896
ed92f0b2 4897static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4898 struct intel_connector *intel_connector,
4899 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4900{
4901 struct drm_connector *connector = &intel_connector->base;
4902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4903 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4904 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4907 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4908 bool has_dpcd;
4909 struct drm_display_mode *scan;
4910 struct edid *edid;
4911
4f9db5b5
PB		 4912 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4913
ed92f0b2
PZ		 4914 if (!is_edp(intel_dp))
4915 return true;
4916
aba86890 4917 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4918
ed92f0b2 4919 /* Cache DPCD and EDID for edp. */
24f3e092 4920 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4921 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4922 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4923
4924 if (has_dpcd) {
4925 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4926 dev_priv->no_aux_handshake =
4927 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4928 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4929 } else {
4930 /* if this fails, presume the device is a ghost */
4931 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4932 return false;
4933 }
4934
4935 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4936 pps_lock(intel_dp);
0095e6dc 4937 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 4938 pps_unlock(intel_dp);
ed92f0b2 4939
060c8778 4940 mutex_lock(&dev->mode_config.mutex);
0b99836f 4941 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4942 if (edid) {
4943 if (drm_add_edid_modes(connector, edid)) {
4944 drm_mode_connector_update_edid_property(connector,
4945 edid);
4946 drm_edid_to_eld(connector, edid);
4947 } else {
4948 kfree(edid);
4949 edid = ERR_PTR(-EINVAL);
4950 }
4951 } else {
4952 edid = ERR_PTR(-ENOENT);
4953 }
4954 intel_connector->edid = edid;
4955
4956 /* prefer fixed mode from EDID if available */
4957 list_for_each_entry(scan, &connector->probed_modes, head) {
4958 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4959 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4960 downclock_mode = intel_dp_drrs_init(
4961 intel_dig_port,
4962 intel_connector, fixed_mode);
ed92f0b2
PZ		 4963 break;
4964 }
4965 }
4966
4967 /* fallback to VBT if available for eDP */
4968 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4969 fixed_mode = drm_mode_duplicate(dev,
4970 dev_priv->vbt.lfp_lvds_vbt_mode);
4971 if (fixed_mode)
4972 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4973 }
060c8778 4974 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4975
01527b31
CT		 4976 if (IS_VALLEYVIEW(dev)) {
4977 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4978 register_reboot_notifier(&intel_dp->edp_notifier);
4979 }
4980
4f9db5b5 4981 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4982 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4983 intel_panel_setup_backlight(connector);
4984
4985 return true;
4986}
4987
16c25533 4988bool
f0fec3f2
PZ		 4989intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4990 struct intel_connector *intel_connector)
a4fc5ed6 4991{
f0fec3f2
PZ		 4992 struct drm_connector *connector = &intel_connector->base;
4993 struct intel_dp *intel_dp = &intel_dig_port->dp;
4994 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4995 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4996 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4997 enum port port = intel_dig_port->port;
0095e6dc 4998 struct edp_power_seq power_seq = { 0 };
0b99836f 4999 int type;
a4fc5ed6 5000
a4a5d2f8
VS		 5001 intel_dp->pps_pipe = INVALID_PIPE;
5002
ec5b01dd
DL		 5003 /* intel_dp vfuncs */
5004 if (IS_VALLEYVIEW(dev))
5005 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5006 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5007 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5008 else if (HAS_PCH_SPLIT(dev))
5009 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5010 else
5011 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5012
153b1100
DL		 5013 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5014
0767935e
DV		 5015 /* Preserve the current hw state. */
5016 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5017 intel_dp->attached_connector = intel_connector;
3d3dc149 5018
3b32a35b 5019 if (intel_dp_is_edp(dev, port))
b329530c 5020 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5021 else
5022 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5023
f7d24902
ID		 5024 /*
5025 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5026 * for DP the encoder type can be set by the caller to
5027 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5028 */
5029 if (type == DRM_MODE_CONNECTOR_eDP)
5030 intel_encoder->type = INTEL_OUTPUT_EDP;
5031
e7281eab
ID		 5032 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5033 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5034 port_name(port));
5035
b329530c 5036 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5037 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5038
a4fc5ed6
KP		 5039 connector->interlace_allowed = true;
5040 connector->doublescan_allowed = 0;
5041
f0fec3f2 5042 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5043 edp_panel_vdd_work);
a4fc5ed6 5044
df0e9248 5045 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5046 drm_connector_register(connector);
a4fc5ed6 5047
affa9354 5048 if (HAS_DDI(dev))
bcbc889b
PZ		 5049 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5050 else
5051 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5052 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5053
0b99836f 5054 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5055 switch (port) {
5056 case PORT_A:
1d843f9d 5057 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5058 break;
5059 case PORT_B:
1d843f9d 5060 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5061 break;
5062 case PORT_C:
1d843f9d 5063 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5064 break;
5065 case PORT_D:
1d843f9d 5066 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5067 break;
5068 default:
ad1c0b19 5069 BUG();
5eb08b69
ZW		 5070 }
5071
dada1a9f 5072 if (is_edp(intel_dp)) {
773538e8 5073 pps_lock(intel_dp);
a4a5d2f8
VS		 5074 if (IS_VALLEYVIEW(dev)) {
5075 vlv_initial_power_sequencer_setup(intel_dp);
5076 } else {
5077 intel_dp_init_panel_power_timestamps(intel_dp);
5078 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5079 &power_seq);
5080 }
773538e8 5081 pps_unlock(intel_dp);
dada1a9f 5082 }
0095e6dc 5083
9d1a1031 5084 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5085
0e32b39c
DA		 5086 /* init MST on ports that can support it */
5087 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5088 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5089 intel_dp_mst_encoder_init(intel_dig_port,
5090 intel_connector->base.base.id);
0e32b39c
DA		 5091 }
5092 }
5093
0095e6dc 5094 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5095 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5096 if (is_edp(intel_dp)) {
5097 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 5098 pps_lock(intel_dp);
4be73780 5099 edp_panel_vdd_off_sync(intel_dp);
773538e8 5100 pps_unlock(intel_dp);
15b1d171 5101 }
34ea3d38 5102 drm_connector_unregister(connector);
b2f246a8 5103 drm_connector_cleanup(connector);
16c25533 5104 return false;
b2f246a8 5105 }
32f9d658 5106
f684960e
CW		 5107 intel_dp_add_properties(intel_dp, connector);
5108
a4fc5ed6
KP		 5109 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5110 * 0xd. Failure to do so will result in spurious interrupts being
5111 * generated on the port when a cable is not attached.
5112 */
5113 if (IS_G4X(dev) && !IS_GM45(dev)) {
5114 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5115 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5116 }
16c25533
PZ		 5117
5118 return true;
a4fc5ed6 5119}
f0fec3f2
PZ		 5120
5121void
5122intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5123{
13cf5504 5124 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5125 struct intel_digital_port *intel_dig_port;
5126 struct intel_encoder *intel_encoder;
5127 struct drm_encoder *encoder;
5128 struct intel_connector *intel_connector;
5129
b14c5679 5130 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5131 if (!intel_dig_port)
5132 return;
5133
b14c5679 5134 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5135 if (!intel_connector) {
5136 kfree(intel_dig_port);
5137 return;
5138 }
5139
5140 intel_encoder = &intel_dig_port->base;
5141 encoder = &intel_encoder->base;
5142
5143 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5144 DRM_MODE_ENCODER_TMDS);
5145
5bfe2ac0 5146 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5147 intel_encoder->disable = intel_disable_dp;
00c09d70 5148 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5149 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5150 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5151 if (IS_CHERRYVIEW(dev)) {
9197c88b 5152 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5153 intel_encoder->pre_enable = chv_pre_enable_dp;
5154 intel_encoder->enable = vlv_enable_dp;
580d3811 5155 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5156 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5157 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5158 intel_encoder->pre_enable = vlv_pre_enable_dp;
5159 intel_encoder->enable = vlv_enable_dp;
49277c31 5160 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5161 } else {
ecff4f3b
JN		 5162 intel_encoder->pre_enable = g4x_pre_enable_dp;
5163 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5164 if (INTEL_INFO(dev)->gen >= 5)
5165 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5166 }
f0fec3f2 5167
174edf1f 5168 intel_dig_port->port = port;
f0fec3f2
PZ		 5169 intel_dig_port->dp.output_reg = output_reg;
5170
00c09d70 5171 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5172 if (IS_CHERRYVIEW(dev)) {
5173 if (port == PORT_D)
5174 intel_encoder->crtc_mask = 1 << 2;
5175 else
5176 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5177 } else {
5178 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5179 }
bc079e8b 5180 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5181 intel_encoder->hot_plug = intel_dp_hot_plug;
5182
13cf5504
DA		 5183 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5184 dev_priv->hpd_irq_port[port] = intel_dig_port;
5185
15b1d171
PZ		 5186 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5187 drm_encoder_cleanup(encoder);
5188 kfree(intel_dig_port);
b2f246a8 5189 kfree(intel_connector);
15b1d171 5190 }
f0fec3f2 5191}
0e32b39c
DA		 5192
5193void intel_dp_mst_suspend(struct drm_device *dev)
5194{
5195 struct drm_i915_private *dev_priv = dev->dev_private;
5196 int i;
5197
5198 /* disable MST */
5199 for (i = 0; i < I915_MAX_PORTS; i++) {
5200 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5201 if (!intel_dig_port)
5202 continue;
5203
5204 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5205 if (!intel_dig_port->dp.can_mst)
5206 continue;
5207 if (intel_dig_port->dp.is_mst)
5208 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5209 }
5210 }
5211}
5212
5213void intel_dp_mst_resume(struct drm_device *dev)
5214{
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216 int i;
5217
5218 for (i = 0; i < I915_MAX_PORTS; i++) {
5219 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5220 if (!intel_dig_port)
5221 continue;
5222 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5223 int ret;
5224
5225 if (!intel_dig_port->dp.can_mst)
5226 continue;
5227
5228 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5229 if (ret != 0) {
5230 intel_dp_check_mst_status(&intel_dig_port->dp);
5231 }
5232 }
5233 }
5234}
Linux kernel - Deliverables
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