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drm/i915/dp: Use auxch precharge value of 5 everywhere
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
ab2c0672 38#include "drm_dp_helper.h"
a4fc5ed6 39
a2006cf5 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44#define DP_LINK_CONFIGURATION_SIZE 9
45
ea5b213a
CW		 46struct intel_dp {
47 struct intel_encoder base;
a4fc5ed6
KP		 48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 51 bool has_audio;
f684960e 52 int force_audio;
e953fd7b 53 uint32_t color_range;
d2b996ac 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
a2006cf5 57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
33a34e4e 61 uint8_t train_set[4];
f01eca2e
KP		 62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
d15456de 67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
bd943159
KP		 68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
a4fc5ed6
KP		 70};
71
cfcb0fc9
JB		 72/**
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
75 *
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
78 */
79static bool is_edp(struct intel_dp *intel_dp)
80{
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
82}
83
84/**
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
87 *
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
91 */
92static bool is_pch_edp(struct intel_dp *intel_dp)
93{
94 return intel_dp->is_pch_edp;
95}
96
1c95822a
AJ		 97/**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
103static bool is_cpu_edp(struct intel_dp *intel_dp)
104{
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106}
107
ea5b213a
CW		 108static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
109{
4ef69c7a 110 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 111}
a4fc5ed6 112
df0e9248
CW		 113static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
114{
115 return container_of(intel_attached_encoder(connector),
116 struct intel_dp, base);
117}
118
814948ad
JB		 119/**
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
122 *
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
125 */
126bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
127{
128 struct intel_dp *intel_dp;
129
130 if (!encoder)
131 return false;
132
133 intel_dp = enc_to_intel_dp(encoder);
134
135 return is_pch_edp(intel_dp);
136}
137
33a34e4e
JB		 138static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 140static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 141
32f9d658 142void
0206e353 143intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 144 int *lane_num, int *link_bw)
32f9d658 145{
ea5b213a 146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 147
ea5b213a
CW		 148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 150 *link_bw = 162000;
ea5b213a 151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 152 *link_bw = 270000;
153}
154
a4fc5ed6 155static int
ea5b213a 156intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 157{
9a10f401
KP		 158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
159 switch (max_lane_count) {
160 case 1: case 2: case 4:
161 break;
162 default:
163 max_lane_count = 4;
a4fc5ed6
KP		 164 }
165 return max_lane_count;
166}
167
168static int
ea5b213a 169intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 170{
7183dc29 171 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 172
173 switch (max_link_bw) {
174 case DP_LINK_BW_1_62:
175 case DP_LINK_BW_2_7:
176 break;
177 default:
178 max_link_bw = DP_LINK_BW_1_62;
179 break;
180 }
181 return max_link_bw;
182}
183
184static int
185intel_dp_link_clock(uint8_t link_bw)
186{
187 if (link_bw == DP_LINK_BW_2_7)
188 return 270000;
189 else
190 return 162000;
191}
192
cd9dde44
AJ		 193/*
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
196 *
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
198 *
199 * 270000 * 1 * 8 / 10 == 216000
200 *
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
205 *
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
208 */
209
a4fc5ed6 210static int
3b5c78a3 211intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)
a4fc5ed6 212{
89c61432
JB		 213 struct drm_crtc *crtc = intel_dp->base.base.crtc;
214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
215 int bpp = 24;
885a5fb5 216
3b5c78a3
AJ		 217 if (check_bpp)
218 bpp = check_bpp;
219 else if (intel_crtc)
89c61432
JB		 220 bpp = intel_crtc->bpp;
221
cd9dde44 222 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 223}
224
fe27d53e
DA		 225static int
226intel_dp_max_data_rate(int max_link_clock, int max_lanes)
227{
228 return (max_link_clock * max_lanes * 8) / 10;
229}
230
a4fc5ed6
KP		 231static int
232intel_dp_mode_valid(struct drm_connector *connector,
233 struct drm_display_mode *mode)
234{
df0e9248 235 struct intel_dp *intel_dp = intel_attached_dp(connector);
ea5b213a
CW		 236 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
237 int max_lanes = intel_dp_max_lane_count(intel_dp);
3b5c78a3 238 int max_rate, mode_rate;
a4fc5ed6 239
d15456de
KP		 240 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
241 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 242 return MODE_PANEL;
243
d15456de 244 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 245 return MODE_PANEL;
246 }
247
3b5c78a3
AJ		 248 mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);
249 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
250
251 if (mode_rate > max_rate) {
252 mode_rate = intel_dp_link_required(intel_dp,
253 mode->clock, 18);
254 if (mode_rate > max_rate)
255 return MODE_CLOCK_HIGH;
256 else
257 mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
258 }
a4fc5ed6
KP		 259
260 if (mode->clock < 10000)
261 return MODE_CLOCK_LOW;
262
263 return MODE_OK;
264}
265
266static uint32_t
267pack_aux(uint8_t *src, int src_bytes)
268{
269 int i;
270 uint32_t v = 0;
271
272 if (src_bytes > 4)
273 src_bytes = 4;
274 for (i = 0; i < src_bytes; i++)
275 v |= ((uint32_t) src[i]) << ((3-i) * 8);
276 return v;
277}
278
279static void
280unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
281{
282 int i;
283 if (dst_bytes > 4)
284 dst_bytes = 4;
285 for (i = 0; i < dst_bytes; i++)
286 dst[i] = src >> ((3-i) * 8);
287}
288
fb0f8fbf
KP		 289/* hrawclock is 1/4 the FSB frequency */
290static int
291intel_hrawclk(struct drm_device *dev)
292{
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 uint32_t clkcfg;
295
296 clkcfg = I915_READ(CLKCFG);
297 switch (clkcfg & CLKCFG_FSB_MASK) {
298 case CLKCFG_FSB_400:
299 return 100;
300 case CLKCFG_FSB_533:
301 return 133;
302 case CLKCFG_FSB_667:
303 return 166;
304 case CLKCFG_FSB_800:
305 return 200;
306 case CLKCFG_FSB_1067:
307 return 266;
308 case CLKCFG_FSB_1333:
309 return 333;
310 /* these two are just a guess; one of them might be right */
311 case CLKCFG_FSB_1600:
312 case CLKCFG_FSB_1600_ALT:
313 return 400;
314 default:
315 return 133;
316 }
317}
318
ebf33b18
KP		 319static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
325}
326
327static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
328{
329 struct drm_device *dev = intel_dp->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331
332 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
333}
334
9b984dae
KP		 335static void
336intel_dp_check_edp(struct intel_dp *intel_dp)
337{
338 struct drm_device *dev = intel_dp->base.base.dev;
339 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 340
9b984dae
KP		 341 if (!is_edp(intel_dp))
342 return;
ebf33b18 343 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 344 WARN(1, "eDP powered off while attempting aux channel communication.\n");
345 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 346 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 347 I915_READ(PCH_PP_CONTROL));
348 }
349}
350
a4fc5ed6 351static int
ea5b213a 352intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 353 uint8_t *send, int send_bytes,
354 uint8_t *recv, int recv_size)
355{
ea5b213a 356 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 357 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 358 struct drm_i915_private *dev_priv = dev->dev_private;
359 uint32_t ch_ctl = output_reg + 0x10;
360 uint32_t ch_data = ch_ctl + 4;
361 int i;
362 int recv_bytes;
a4fc5ed6 363 uint32_t status;
fb0f8fbf 364 uint32_t aux_clock_divider;
092945e1 365 int try, precharge = 5;
a4fc5ed6 366
9b984dae 367 intel_dp_check_edp(intel_dp);
a4fc5ed6 368 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 369 * and would like to run at 2MHz. So, take the
370 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 371 *
372 * Note that PCH attached eDP panels should use a 125MHz input
373 * clock divider.
a4fc5ed6 374 */
1c95822a 375 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 376 if (IS_GEN6(dev) || IS_GEN7(dev))
377 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 378 else
379 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
380 } else if (HAS_PCH_SPLIT(dev))
6919132e 381 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 382 else
383 aux_clock_divider = intel_hrawclk(dev) / 2;
384
11bee43e
JB		 385 /* Try to wait for any previous AUX channel activity */
386 for (try = 0; try < 3; try++) {
387 status = I915_READ(ch_ctl);
388 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
389 break;
390 msleep(1);
391 }
392
393 if (try == 3) {
394 WARN(1, "dp_aux_ch not started status 0x%08x\n",
395 I915_READ(ch_ctl));
4f7f7b7e
CW		 396 return -EBUSY;
397 }
398
fb0f8fbf
KP		 399 /* Must try at least 3 times according to DP spec */
400 for (try = 0; try < 5; try++) {
401 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 402 for (i = 0; i < send_bytes; i += 4)
403 I915_WRITE(ch_data + i,
404 pack_aux(send + i, send_bytes - i));
0206e353 405
fb0f8fbf 406 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 407 I915_WRITE(ch_ctl,
408 DP_AUX_CH_CTL_SEND_BUSY |
409 DP_AUX_CH_CTL_TIME_OUT_400us |
410 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
411 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
412 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
413 DP_AUX_CH_CTL_DONE |
414 DP_AUX_CH_CTL_TIME_OUT_ERROR |
415 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 416 for (;;) {
fb0f8fbf
KP		 417 status = I915_READ(ch_ctl);
418 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
419 break;
4f7f7b7e 420 udelay(100);
fb0f8fbf 421 }
0206e353 422
fb0f8fbf 423 /* Clear done status and any errors */
4f7f7b7e
CW		 424 I915_WRITE(ch_ctl,
425 status |
426 DP_AUX_CH_CTL_DONE |
427 DP_AUX_CH_CTL_TIME_OUT_ERROR |
428 DP_AUX_CH_CTL_RECEIVE_ERROR);
429 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 430 break;
431 }
432
a4fc5ed6 433 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 434 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 435 return -EBUSY;
a4fc5ed6
KP		 436 }
437
438 /* Check for timeout or receive error.
439 * Timeouts occur when the sink is not connected
440 */
a5b3da54 441 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 442 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 443 return -EIO;
444 }
1ae8c0a5
KP		 445
446 /* Timeouts occur when the device isn't connected, so they're
447 * "normal" -- don't fill the kernel log with these */
a5b3da54 448 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 449 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 450 return -ETIMEDOUT;
a4fc5ed6
KP		 451 }
452
453 /* Unload any bytes sent back from the other side */
454 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
455 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 456 if (recv_bytes > recv_size)
457 recv_bytes = recv_size;
0206e353 458
4f7f7b7e
CW		 459 for (i = 0; i < recv_bytes; i += 4)
460 unpack_aux(I915_READ(ch_data + i),
461 recv + i, recv_bytes - i);
a4fc5ed6
KP		 462
463 return recv_bytes;
464}
465
466/* Write data to the aux channel in native mode */
467static int
ea5b213a 468intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 469 uint16_t address, uint8_t *send, int send_bytes)
470{
471 int ret;
472 uint8_t msg[20];
473 int msg_bytes;
474 uint8_t ack;
475
9b984dae 476 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 477 if (send_bytes > 16)
478 return -1;
479 msg[0] = AUX_NATIVE_WRITE << 4;
480 msg[1] = address >> 8;
eebc863e 481 msg[2] = address & 0xff;
a4fc5ed6
KP		 482 msg[3] = send_bytes - 1;
483 memcpy(&msg[4], send, send_bytes);
484 msg_bytes = send_bytes + 4;
485 for (;;) {
ea5b213a 486 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 487 if (ret < 0)
488 return ret;
489 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
490 break;
491 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
492 udelay(100);
493 else
a5b3da54 494 return -EIO;
a4fc5ed6
KP		 495 }
496 return send_bytes;
497}
498
499/* Write a single byte to the aux channel in native mode */
500static int
ea5b213a 501intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 502 uint16_t address, uint8_t byte)
503{
ea5b213a 504 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 505}
506
507/* read bytes from a native aux channel */
508static int
ea5b213a 509intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 510 uint16_t address, uint8_t *recv, int recv_bytes)
511{
512 uint8_t msg[4];
513 int msg_bytes;
514 uint8_t reply[20];
515 int reply_bytes;
516 uint8_t ack;
517 int ret;
518
9b984dae 519 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 520 msg[0] = AUX_NATIVE_READ << 4;
521 msg[1] = address >> 8;
522 msg[2] = address & 0xff;
523 msg[3] = recv_bytes - 1;
524
525 msg_bytes = 4;
526 reply_bytes = recv_bytes + 1;
527
528 for (;;) {
ea5b213a 529 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 530 reply, reply_bytes);
a5b3da54
KP		 531 if (ret == 0)
532 return -EPROTO;
533 if (ret < 0)
a4fc5ed6
KP		 534 return ret;
535 ack = reply[0];
536 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
537 memcpy(recv, reply + 1, ret - 1);
538 return ret - 1;
539 }
540 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
541 udelay(100);
542 else
a5b3da54 543 return -EIO;
a4fc5ed6
KP		 544 }
545}
546
547static int
ab2c0672
DA		 548intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
549 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 550{
ab2c0672 551 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 552 struct intel_dp *intel_dp = container_of(adapter,
553 struct intel_dp,
554 adapter);
ab2c0672
DA		 555 uint16_t address = algo_data->address;
556 uint8_t msg[5];
557 uint8_t reply[2];
8316f337 558 unsigned retry;
ab2c0672
DA		 559 int msg_bytes;
560 int reply_bytes;
561 int ret;
562
9b984dae 563 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 564 /* Set up the command byte */
565 if (mode & MODE_I2C_READ)
566 msg[0] = AUX_I2C_READ << 4;
567 else
568 msg[0] = AUX_I2C_WRITE << 4;
569
570 if (!(mode & MODE_I2C_STOP))
571 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 572
ab2c0672
DA		 573 msg[1] = address >> 8;
574 msg[2] = address;
575
576 switch (mode) {
577 case MODE_I2C_WRITE:
578 msg[3] = 0;
579 msg[4] = write_byte;
580 msg_bytes = 5;
581 reply_bytes = 1;
582 break;
583 case MODE_I2C_READ:
584 msg[3] = 0;
585 msg_bytes = 4;
586 reply_bytes = 2;
587 break;
588 default:
589 msg_bytes = 3;
590 reply_bytes = 1;
591 break;
592 }
593
8316f337
DF		 594 for (retry = 0; retry < 5; retry++) {
595 ret = intel_dp_aux_ch(intel_dp,
596 msg, msg_bytes,
597 reply, reply_bytes);
ab2c0672 598 if (ret < 0) {
3ff99164 599 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 600 return ret;
601 }
8316f337
DF		 602
603 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
604 case AUX_NATIVE_REPLY_ACK:
605 /* I2C-over-AUX Reply field is only valid
606 * when paired with AUX ACK.
607 */
608 break;
609 case AUX_NATIVE_REPLY_NACK:
610 DRM_DEBUG_KMS("aux_ch native nack\n");
611 return -EREMOTEIO;
612 case AUX_NATIVE_REPLY_DEFER:
613 udelay(100);
614 continue;
615 default:
616 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
617 reply[0]);
618 return -EREMOTEIO;
619 }
620
ab2c0672
DA		 621 switch (reply[0] & AUX_I2C_REPLY_MASK) {
622 case AUX_I2C_REPLY_ACK:
623 if (mode == MODE_I2C_READ) {
624 *read_byte = reply[1];
625 }
626 return reply_bytes - 1;
627 case AUX_I2C_REPLY_NACK:
8316f337 628 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 629 return -EREMOTEIO;
630 case AUX_I2C_REPLY_DEFER:
8316f337 631 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 632 udelay(100);
633 break;
634 default:
8316f337 635 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 636 return -EREMOTEIO;
637 }
638 }
8316f337
DF		 639
640 DRM_ERROR("too many retries, giving up\n");
641 return -EREMOTEIO;
a4fc5ed6
KP		 642}
643
0b5c541b 644static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 645static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 646
a4fc5ed6 647static int
ea5b213a 648intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 649 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 650{
0b5c541b
KP		 651 int ret;
652
d54e9d28 653 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 654 intel_dp->algo.running = false;
655 intel_dp->algo.address = 0;
656 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
657
0206e353 658 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 659 intel_dp->adapter.owner = THIS_MODULE;
660 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 661 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 662 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
663 intel_dp->adapter.algo_data = &intel_dp->algo;
664 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
665
0b5c541b
KP		 666 ironlake_edp_panel_vdd_on(intel_dp);
667 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 668 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 669 return ret;
a4fc5ed6
KP		 670}
671
672static bool
673intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
674 struct drm_display_mode *adjusted_mode)
675{
0d3a1bee 676 struct drm_device *dev = encoder->dev;
ea5b213a 677 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 678 int lane_count, clock;
ea5b213a
CW		 679 int max_lane_count = intel_dp_max_lane_count(intel_dp);
680 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
3b5c78a3 681 int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;
a4fc5ed6
KP		 682 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
683
d15456de
KP		 684 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
685 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 686 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
687 mode, adjusted_mode);
0d3a1bee
ZY		 688 /*
689 * the mode->clock is used to calculate the Data&Link M/N
690 * of the pipe. For the eDP the fixed clock should be used.
691 */
d15456de 692 mode->clock = intel_dp->panel_fixed_mode->clock;
0d3a1bee
ZY		 693 }
694
a4fc5ed6
KP		 695 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
696 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 697 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 698
3b5c78a3 699 if (intel_dp_link_required(intel_dp, mode->clock, bpp)
885a5fb5 700 <= link_avail) {
ea5b213a
CW		 701 intel_dp->link_bw = bws[clock];
702 intel_dp->lane_count = lane_count;
703 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
28c97730
ZY		 704 DRM_DEBUG_KMS("Display port link bw %02x lane "
705 "count %d clock %d\n",
ea5b213a 706 intel_dp->link_bw, intel_dp->lane_count,
a4fc5ed6
KP		 707 adjusted_mode->clock);
708 return true;
709 }
710 }
711 }
fe27d53e 712
a4fc5ed6
KP		 713 return false;
714}
715
716struct intel_dp_m_n {
717 uint32_t tu;
718 uint32_t gmch_m;
719 uint32_t gmch_n;
720 uint32_t link_m;
721 uint32_t link_n;
722};
723
724static void
725intel_reduce_ratio(uint32_t *num, uint32_t *den)
726{
727 while (*num > 0xffffff || *den > 0xffffff) {
728 *num >>= 1;
729 *den >>= 1;
730 }
731}
732
733static void
36e83a18 734intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 735 int nlanes,
736 int pixel_clock,
737 int link_clock,
738 struct intel_dp_m_n *m_n)
739{
740 m_n->tu = 64;
36e83a18 741 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 742 m_n->gmch_n = link_clock * nlanes;
743 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
744 m_n->link_m = pixel_clock;
745 m_n->link_n = link_clock;
746 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
747}
748
749void
750intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
751 struct drm_display_mode *adjusted_mode)
752{
753 struct drm_device *dev = crtc->dev;
754 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 755 struct drm_encoder *encoder;
a4fc5ed6
KP		 756 struct drm_i915_private *dev_priv = dev->dev_private;
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 758 int lane_count = 4;
a4fc5ed6 759 struct intel_dp_m_n m_n;
9db4a9c7 760 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 761
762 /*
21d40d37 763 * Find the lane count in the intel_encoder private
a4fc5ed6 764 */
55f78c43 765 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 766 struct intel_dp *intel_dp;
a4fc5ed6 767
d8201ab6 768 if (encoder->crtc != crtc)
a4fc5ed6
KP		 769 continue;
770
ea5b213a 771 intel_dp = enc_to_intel_dp(encoder);
9a10f401
KP		 772 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
773 intel_dp->base.type == INTEL_OUTPUT_EDP)
774 {
ea5b213a 775 lane_count = intel_dp->lane_count;
51190667 776 break;
a4fc5ed6
KP		 777 }
778 }
779
780 /*
781 * Compute the GMCH and Link ratios. The '3' here is
782 * the number of bytes_per_pixel post-LUT, which we always
783 * set up for 8-bits of R/G/B, or 3 bytes total.
784 */
858fa035 785 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 786 mode->clock, adjusted_mode->clock, &m_n);
787
c619eed4 788 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 789 I915_WRITE(TRANSDATA_M1(pipe),
790 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
791 m_n.gmch_m);
792 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
793 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
794 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 795 } else {
9db4a9c7
JB		 796 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
797 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
798 m_n.gmch_m);
799 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
800 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
801 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 802 }
803}
804
f01eca2e
KP		 805static void ironlake_edp_pll_on(struct drm_encoder *encoder);
806static void ironlake_edp_pll_off(struct drm_encoder *encoder);
807
a4fc5ed6
KP		 808static void
809intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
810 struct drm_display_mode *adjusted_mode)
811{
e3421a18 812 struct drm_device *dev = encoder->dev;
417e822d 813 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 814 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 815 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
817
f01eca2e
KP		 818 /* Turn on the eDP PLL if needed */
819 if (is_edp(intel_dp)) {
820 if (!is_pch_edp(intel_dp))
821 ironlake_edp_pll_on(encoder);
822 else
823 ironlake_edp_pll_off(encoder);
824 }
825
417e822d 826 /*
1a2eb460 827 * There are four kinds of DP registers:
417e822d
KP		 828 *
829 * IBX PCH
1a2eb460
KP		 830 * SNB CPU
831 * IVB CPU
417e822d
KP		 832 * CPT PCH
833 *
834 * IBX PCH and CPU are the same for almost everything,
835 * except that the CPU DP PLL is configured in this
836 * register
837 *
838 * CPT PCH is quite different, having many bits moved
839 * to the TRANS_DP_CTL register instead. That
840 * configuration happens (oddly) in ironlake_pch_enable
841 */
9c9e7927 842
417e822d
KP		 843 /* Preserve the BIOS-computed detected bit. This is
844 * supposed to be read-only.
845 */
846 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
847 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 848
417e822d
KP		 849 /* Handle DP bits in common between all three register formats */
850
851 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 852
ea5b213a 853 switch (intel_dp->lane_count) {
a4fc5ed6 854 case 1:
ea5b213a 855 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 856 break;
857 case 2:
ea5b213a 858 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 859 break;
860 case 4:
ea5b213a 861 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 862 break;
863 }
e0dac65e
WF		 864 if (intel_dp->has_audio) {
865 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
866 pipe_name(intel_crtc->pipe));
ea5b213a 867 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 868 intel_write_eld(encoder, adjusted_mode);
869 }
ea5b213a
CW		 870 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
871 intel_dp->link_configuration[0] = intel_dp->link_bw;
872 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 873 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 874 /*
9962c925 875 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 876 */
7183dc29
JB		 877 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
878 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 879 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 880 }
881
417e822d 882 /* Split out the IBX/CPU vs CPT settings */
32f9d658 883
1a2eb460
KP		 884 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
885 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
886 intel_dp->DP |= DP_SYNC_HS_HIGH;
887 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
888 intel_dp->DP |= DP_SYNC_VS_HIGH;
889 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
890
891 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
892 intel_dp->DP |= DP_ENHANCED_FRAMING;
893
894 intel_dp->DP |= intel_crtc->pipe << 29;
895
896 /* don't miss out required setting for eDP */
897 intel_dp->DP |= DP_PLL_ENABLE;
898 if (adjusted_mode->clock < 200000)
899 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
900 else
901 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
902 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 903 intel_dp->DP |= intel_dp->color_range;
904
905 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
906 intel_dp->DP |= DP_SYNC_HS_HIGH;
907 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
908 intel_dp->DP |= DP_SYNC_VS_HIGH;
909 intel_dp->DP |= DP_LINK_TRAIN_OFF;
910
911 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
912 intel_dp->DP |= DP_ENHANCED_FRAMING;
913
914 if (intel_crtc->pipe == 1)
915 intel_dp->DP |= DP_PIPEB_SELECT;
916
917 if (is_cpu_edp(intel_dp)) {
918 /* don't miss out required setting for eDP */
919 intel_dp->DP |= DP_PLL_ENABLE;
920 if (adjusted_mode->clock < 200000)
921 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
922 else
923 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
924 }
925 } else {
926 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 927 }
a4fc5ed6
KP		 928}
929
99ea7127
KP		 930#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
931#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
932
933#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
934#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
935
936#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
937#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
938
939static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
940 u32 mask,
941 u32 value)
bd943159 942{
99ea7127
KP		 943 struct drm_device *dev = intel_dp->base.base.dev;
944 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 945
99ea7127
KP		 946 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
947 mask, value,
948 I915_READ(PCH_PP_STATUS),
949 I915_READ(PCH_PP_CONTROL));
32ce697c 950
99ea7127
KP		 951 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
952 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
953 I915_READ(PCH_PP_STATUS),
954 I915_READ(PCH_PP_CONTROL));
32ce697c 955 }
99ea7127 956}
32ce697c 957
99ea7127
KP		 958static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
959{
960 DRM_DEBUG_KMS("Wait for panel power on\n");
961 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 962}
963
99ea7127
KP		 964static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
965{
966 DRM_DEBUG_KMS("Wait for panel power off time\n");
967 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
968}
969
970static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
971{
972 DRM_DEBUG_KMS("Wait for panel power cycle\n");
973 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
974}
975
976
832dd3c1
KP		 977/* Read the current pp_control value, unlocking the register if it
978 * is locked
979 */
980
981static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
982{
983 u32 control = I915_READ(PCH_PP_CONTROL);
984
985 control &= ~PANEL_UNLOCK_MASK;
986 control |= PANEL_UNLOCK_REGS;
987 return control;
bd943159
KP		 988}
989
5d613501
JB		 990static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
991{
992 struct drm_device *dev = intel_dp->base.base.dev;
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 u32 pp;
995
97af61f5
KP		 996 if (!is_edp(intel_dp))
997 return;
f01eca2e 998 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 999
bd943159
KP		 1000 WARN(intel_dp->want_panel_vdd,
1001 "eDP VDD already requested on\n");
1002
1003 intel_dp->want_panel_vdd = true;
99ea7127 1004
bd943159
KP		 1005 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1006 DRM_DEBUG_KMS("eDP VDD already on\n");
1007 return;
1008 }
1009
99ea7127
KP		 1010 if (!ironlake_edp_have_panel_power(intel_dp))
1011 ironlake_wait_panel_power_cycle(intel_dp);
1012
832dd3c1 1013 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1014 pp |= EDP_FORCE_VDD;
1015 I915_WRITE(PCH_PP_CONTROL, pp);
1016 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1017 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1018 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1019
1020 /*
1021 * If the panel wasn't on, delay before accessing aux channel
1022 */
1023 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1024 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1025 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1026 }
5d613501
JB		 1027}
1028
bd943159 1029static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1030{
1031 struct drm_device *dev = intel_dp->base.base.dev;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 u32 pp;
1034
bd943159 1035 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1036 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1037 pp &= ~EDP_FORCE_VDD;
1038 I915_WRITE(PCH_PP_CONTROL, pp);
1039 POSTING_READ(PCH_PP_CONTROL);
1040
1041 /* Make sure sequencer is idle before allowing subsequent activity */
1042 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1043 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1044
1045 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1046 }
1047}
5d613501 1048
bd943159
KP		 1049static void ironlake_panel_vdd_work(struct work_struct *__work)
1050{
1051 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1052 struct intel_dp, panel_vdd_work);
1053 struct drm_device *dev = intel_dp->base.base.dev;
1054
627f7675 1055 mutex_lock(&dev->mode_config.mutex);
bd943159 1056 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1057 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1058}
1059
1060static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1061{
97af61f5
KP		 1062 if (!is_edp(intel_dp))
1063 return;
5d613501 1064
bd943159
KP		 1065 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1066 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1067
bd943159
KP		 1068 intel_dp->want_panel_vdd = false;
1069
1070 if (sync) {
1071 ironlake_panel_vdd_off_sync(intel_dp);
1072 } else {
1073 /*
1074 * Queue the timer to fire a long
1075 * time from now (relative to the power down delay)
1076 * to keep the panel power up across a sequence of operations
1077 */
1078 schedule_delayed_work(&intel_dp->panel_vdd_work,
1079 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1080 }
5d613501
JB		 1081}
1082
86a3073e 1083static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1084{
01cb9ea6 1085 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1086 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1087 u32 pp;
9934c132 1088
97af61f5 1089 if (!is_edp(intel_dp))
bd943159 1090 return;
99ea7127
KP		 1091
1092 DRM_DEBUG_KMS("Turn eDP power on\n");
1093
1094 if (ironlake_edp_have_panel_power(intel_dp)) {
1095 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1096 return;
99ea7127 1097 }
9934c132 1098
99ea7127 1099 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1100
99ea7127 1101 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1102 if (IS_GEN5(dev)) {
1103 /* ILK workaround: disable reset around power sequence */
1104 pp &= ~PANEL_POWER_RESET;
1105 I915_WRITE(PCH_PP_CONTROL, pp);
1106 POSTING_READ(PCH_PP_CONTROL);
1107 }
37c6c9b0 1108
1c0ae80a 1109 pp |= POWER_TARGET_ON;
99ea7127
KP		 1110 if (!IS_GEN5(dev))
1111 pp |= PANEL_POWER_RESET;
1112
9934c132 1113 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1114 POSTING_READ(PCH_PP_CONTROL);
9934c132 1115
99ea7127 1116 ironlake_wait_panel_on(intel_dp);
9934c132 1117
05ce1a49
KP		 1118 if (IS_GEN5(dev)) {
1119 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1120 I915_WRITE(PCH_PP_CONTROL, pp);
1121 POSTING_READ(PCH_PP_CONTROL);
1122 }
9934c132
JB		 1123}
1124
99ea7127 1125static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1126{
99ea7127 1127 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1128 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1129 u32 pp;
9934c132 1130
97af61f5
KP		 1131 if (!is_edp(intel_dp))
1132 return;
37c6c9b0 1133
99ea7127 1134 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1135
99ea7127 1136 WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
37c6c9b0 1137
99ea7127
KP		 1138 pp = ironlake_get_pp_control(dev_priv);
1139 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1140 I915_WRITE(PCH_PP_CONTROL, pp);
1141 POSTING_READ(PCH_PP_CONTROL);
9934c132 1142
99ea7127 1143 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1144}
1145
86a3073e 1146static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1147{
f01eca2e 1148 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 u32 pp;
1151
f01eca2e
KP		 1152 if (!is_edp(intel_dp))
1153 return;
1154
28c97730 1155 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1156 /*
1157 * If we enable the backlight right away following a panel power
1158 * on, we may see slight flicker as the panel syncs with the eDP
1159 * link. So delay a bit to make sure the image is solid before
1160 * allowing it to appear.
1161 */
f01eca2e 1162 msleep(intel_dp->backlight_on_delay);
832dd3c1 1163 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1164 pp |= EDP_BLC_ENABLE;
1165 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1166 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1167}
1168
86a3073e 1169static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1170{
f01eca2e 1171 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 pp;
1174
f01eca2e
KP		 1175 if (!is_edp(intel_dp))
1176 return;
1177
28c97730 1178 DRM_DEBUG_KMS("\n");
832dd3c1 1179 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1180 pp &= ~EDP_BLC_ENABLE;
1181 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1182 POSTING_READ(PCH_PP_CONTROL);
1183 msleep(intel_dp->backlight_off_delay);
32f9d658 1184}
a4fc5ed6 1185
d240f20f
JB		 1186static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1187{
1188 struct drm_device *dev = encoder->dev;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 u32 dpa_ctl;
1191
1192 DRM_DEBUG_KMS("\n");
1193 dpa_ctl = I915_READ(DP_A);
298b0b39 1194 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1195 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1196 POSTING_READ(DP_A);
1197 udelay(200);
d240f20f
JB		 1198}
1199
1200static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1201{
1202 struct drm_device *dev = encoder->dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 u32 dpa_ctl;
1205
1206 dpa_ctl = I915_READ(DP_A);
298b0b39 1207 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1208 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1209 POSTING_READ(DP_A);
d240f20f
JB		 1210 udelay(200);
1211}
1212
c7ad3810
JB		 1213/* If the sink supports it, try to set the power state appropriately */
1214static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1215{
1216 int ret, i;
1217
1218 /* Should have a valid DPCD by this point */
1219 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1220 return;
1221
1222 if (mode != DRM_MODE_DPMS_ON) {
1223 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1224 DP_SET_POWER_D3);
1225 if (ret != 1)
1226 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1227 } else {
1228 /*
1229 * When turning on, we need to retry for 1ms to give the sink
1230 * time to wake up.
1231 */
1232 for (i = 0; i < 3; i++) {
1233 ret = intel_dp_aux_native_write_1(intel_dp,
1234 DP_SET_POWER,
1235 DP_SET_POWER_D0);
1236 if (ret == 1)
1237 break;
1238 msleep(1);
1239 }
1240 }
1241}
1242
d240f20f
JB		 1243static void intel_dp_prepare(struct drm_encoder *encoder)
1244{
1245 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d240f20f 1246
21264c63
KP		 1247 ironlake_edp_backlight_off(intel_dp);
1248 ironlake_edp_panel_off(intel_dp);
1249
c7ad3810 1250 /* Wake up the sink first */
f58ff854 1251 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1252 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
21264c63 1253 intel_dp_link_down(intel_dp);
bd943159 1254 ironlake_edp_panel_vdd_off(intel_dp, false);
c7ad3810 1255
f01eca2e
KP		 1256 /* Make sure the panel is off before trying to
1257 * change the mode
1258 */
d240f20f
JB		 1259}
1260
1261static void intel_dp_commit(struct drm_encoder *encoder)
1262{
1263 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d4270e57
JB		 1264 struct drm_device *dev = encoder->dev;
1265 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
5d613501 1266
97af61f5 1267 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1268 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1269 intel_dp_start_link_train(intel_dp);
97af61f5 1270 ironlake_edp_panel_on(intel_dp);
bd943159 1271 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1272 intel_dp_complete_link_train(intel_dp);
f01eca2e 1273 ironlake_edp_backlight_on(intel_dp);
d2b996ac
KP		 1274
1275 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
d4270e57
JB		 1276
1277 if (HAS_PCH_CPT(dev))
1278 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
d240f20f
JB		 1279}
1280
a4fc5ed6
KP		 1281static void
1282intel_dp_dpms(struct drm_encoder *encoder, int mode)
1283{
ea5b213a 1284 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 1285 struct drm_device *dev = encoder->dev;
a4fc5ed6 1286 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1287 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1288
1289 if (mode != DRM_MODE_DPMS_ON) {
21264c63
KP		 1290 ironlake_edp_backlight_off(intel_dp);
1291 ironlake_edp_panel_off(intel_dp);
1292
245e2708 1293 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1294 intel_dp_sink_dpms(intel_dp, mode);
736085bc 1295 intel_dp_link_down(intel_dp);
bd943159 1296 ironlake_edp_panel_vdd_off(intel_dp, false);
21264c63
KP		 1297
1298 if (is_cpu_edp(intel_dp))
1299 ironlake_edp_pll_off(encoder);
a4fc5ed6 1300 } else {
21264c63
KP		 1301 if (is_cpu_edp(intel_dp))
1302 ironlake_edp_pll_on(encoder);
1303
97af61f5 1304 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1305 intel_dp_sink_dpms(intel_dp, mode);
32f9d658 1306 if (!(dp_reg & DP_PORT_EN)) {
01cb9ea6 1307 intel_dp_start_link_train(intel_dp);
97af61f5 1308 ironlake_edp_panel_on(intel_dp);
bd943159 1309 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1310 intel_dp_complete_link_train(intel_dp);
bee7eb2d 1311 } else
bd943159
KP		 1312 ironlake_edp_panel_vdd_off(intel_dp, false);
1313 ironlake_edp_backlight_on(intel_dp);
a4fc5ed6 1314 }
d2b996ac 1315 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 1316}
1317
1318/*
df0c237d
JB		 1319 * Native read with retry for link status and receiver capability reads for
1320 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1321 */
1322static bool
df0c237d
JB		 1323intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1324 uint8_t *recv, int recv_bytes)
a4fc5ed6 1325{
61da5fab
JB		 1326 int ret, i;
1327
df0c237d
JB		 1328 /*
1329 * Sinks are *supposed* to come up within 1ms from an off state,
1330 * but we're also supposed to retry 3 times per the spec.
1331 */
61da5fab 1332 for (i = 0; i < 3; i++) {
df0c237d
JB		 1333 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1334 recv_bytes);
1335 if (ret == recv_bytes)
61da5fab
JB		 1336 return true;
1337 msleep(1);
1338 }
a4fc5ed6 1339
61da5fab 1340 return false;
a4fc5ed6
KP		 1341}
1342
1343/*
1344 * Fetch AUX CH registers 0x202 - 0x207 which contain
1345 * link status information
1346 */
1347static bool
93f62dad 1348intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1349{
df0c237d
JB		 1350 return intel_dp_aux_native_read_retry(intel_dp,
1351 DP_LANE0_1_STATUS,
93f62dad 1352 link_status,
df0c237d 1353 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1354}
1355
1356static uint8_t
1357intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1358 int r)
1359{
1360 return link_status[r - DP_LANE0_1_STATUS];
1361}
1362
a4fc5ed6 1363static uint8_t
93f62dad 1364intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1365 int lane)
1366{
a4fc5ed6
KP		 1367 int s = ((lane & 1) ?
1368 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1369 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1370 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1371
1372 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1373}
1374
1375static uint8_t
93f62dad 1376intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1377 int lane)
1378{
a4fc5ed6
KP		 1379 int s = ((lane & 1) ?
1380 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1381 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1382 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1383
1384 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1385}
1386
1387
1388#if 0
1389static char *voltage_names[] = {
1390 "0.4V", "0.6V", "0.8V", "1.2V"
1391};
1392static char *pre_emph_names[] = {
1393 "0dB", "3.5dB", "6dB", "9.5dB"
1394};
1395static char *link_train_names[] = {
1396 "pattern 1", "pattern 2", "idle", "off"
1397};
1398#endif
1399
1400/*
1401 * These are source-specific values; current Intel hardware supports
1402 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1403 */
a4fc5ed6
KP		 1404
1405static uint8_t
1a2eb460 1406intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1407{
1a2eb460
KP		 1408 struct drm_device *dev = intel_dp->base.base.dev;
1409
1410 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1411 return DP_TRAIN_VOLTAGE_SWING_800;
1412 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1413 return DP_TRAIN_VOLTAGE_SWING_1200;
1414 else
1415 return DP_TRAIN_VOLTAGE_SWING_800;
1416}
1417
1418static uint8_t
1419intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1420{
1421 struct drm_device *dev = intel_dp->base.base.dev;
1422
1423 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1424 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1425 case DP_TRAIN_VOLTAGE_SWING_400:
1426 return DP_TRAIN_PRE_EMPHASIS_6;
1427 case DP_TRAIN_VOLTAGE_SWING_600:
1428 case DP_TRAIN_VOLTAGE_SWING_800:
1429 return DP_TRAIN_PRE_EMPHASIS_3_5;
1430 default:
1431 return DP_TRAIN_PRE_EMPHASIS_0;
1432 }
1433 } else {
1434 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1435 case DP_TRAIN_VOLTAGE_SWING_400:
1436 return DP_TRAIN_PRE_EMPHASIS_6;
1437 case DP_TRAIN_VOLTAGE_SWING_600:
1438 return DP_TRAIN_PRE_EMPHASIS_6;
1439 case DP_TRAIN_VOLTAGE_SWING_800:
1440 return DP_TRAIN_PRE_EMPHASIS_3_5;
1441 case DP_TRAIN_VOLTAGE_SWING_1200:
1442 default:
1443 return DP_TRAIN_PRE_EMPHASIS_0;
1444 }
a4fc5ed6
KP		 1445 }
1446}
1447
1448static void
93f62dad 1449intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1450{
1451 uint8_t v = 0;
1452 uint8_t p = 0;
1453 int lane;
93f62dad 1454 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1455 uint8_t voltage_max;
1456 uint8_t preemph_max;
a4fc5ed6 1457
33a34e4e 1458 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1459 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1460 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1461
1462 if (this_v > v)
1463 v = this_v;
1464 if (this_p > p)
1465 p = this_p;
1466 }
1467
1a2eb460 1468 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1469 if (v >= voltage_max)
1470 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1471
1a2eb460
KP		 1472 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1473 if (p >= preemph_max)
1474 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1475
1476 for (lane = 0; lane < 4; lane++)
33a34e4e 1477 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1478}
1479
1480static uint32_t
93f62dad 1481intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1482{
3cf2efb1 1483 uint32_t signal_levels = 0;
a4fc5ed6 1484
3cf2efb1 1485 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1486 case DP_TRAIN_VOLTAGE_SWING_400:
1487 default:
1488 signal_levels |= DP_VOLTAGE_0_4;
1489 break;
1490 case DP_TRAIN_VOLTAGE_SWING_600:
1491 signal_levels |= DP_VOLTAGE_0_6;
1492 break;
1493 case DP_TRAIN_VOLTAGE_SWING_800:
1494 signal_levels |= DP_VOLTAGE_0_8;
1495 break;
1496 case DP_TRAIN_VOLTAGE_SWING_1200:
1497 signal_levels |= DP_VOLTAGE_1_2;
1498 break;
1499 }
3cf2efb1 1500 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1501 case DP_TRAIN_PRE_EMPHASIS_0:
1502 default:
1503 signal_levels |= DP_PRE_EMPHASIS_0;
1504 break;
1505 case DP_TRAIN_PRE_EMPHASIS_3_5:
1506 signal_levels |= DP_PRE_EMPHASIS_3_5;
1507 break;
1508 case DP_TRAIN_PRE_EMPHASIS_6:
1509 signal_levels |= DP_PRE_EMPHASIS_6;
1510 break;
1511 case DP_TRAIN_PRE_EMPHASIS_9_5:
1512 signal_levels |= DP_PRE_EMPHASIS_9_5;
1513 break;
1514 }
1515 return signal_levels;
1516}
1517
e3421a18
ZW		 1518/* Gen6's DP voltage swing and pre-emphasis control */
1519static uint32_t
1520intel_gen6_edp_signal_levels(uint8_t train_set)
1521{
3c5a62b5
YL		 1522 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1523 DP_TRAIN_PRE_EMPHASIS_MASK);
1524 switch (signal_levels) {
e3421a18 1525 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1526 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1527 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1528 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1529 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1530 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1531 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1532 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1533 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1534 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1535 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1536 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1537 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1538 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1539 default:
3c5a62b5
YL		 1540 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1541 "0x%x\n", signal_levels);
1542 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1543 }
1544}
1545
1a2eb460
KP		 1546/* Gen7's DP voltage swing and pre-emphasis control */
1547static uint32_t
1548intel_gen7_edp_signal_levels(uint8_t train_set)
1549{
1550 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1551 DP_TRAIN_PRE_EMPHASIS_MASK);
1552 switch (signal_levels) {
1553 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1554 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1555 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1556 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1557 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1558 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1559
1560 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1561 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1562 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1563 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1564
1565 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1566 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1567 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1568 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1569
1570 default:
1571 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1572 "0x%x\n", signal_levels);
1573 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1574 }
1575}
1576
a4fc5ed6
KP		 1577static uint8_t
1578intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1579 int lane)
1580{
a4fc5ed6 1581 int s = (lane & 1) * 4;
93f62dad 1582 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1583
1584 return (l >> s) & 0xf;
1585}
1586
1587/* Check for clock recovery is done on all channels */
1588static bool
1589intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1590{
1591 int lane;
1592 uint8_t lane_status;
1593
1594 for (lane = 0; lane < lane_count; lane++) {
1595 lane_status = intel_get_lane_status(link_status, lane);
1596 if ((lane_status & DP_LANE_CR_DONE) == 0)
1597 return false;
1598 }
1599 return true;
1600}
1601
1602/* Check to see if channel eq is done on all channels */
1603#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1604 DP_LANE_CHANNEL_EQ_DONE|\
1605 DP_LANE_SYMBOL_LOCKED)
1606static bool
93f62dad 1607intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1608{
1609 uint8_t lane_align;
1610 uint8_t lane_status;
1611 int lane;
1612
93f62dad 1613 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1614 DP_LANE_ALIGN_STATUS_UPDATED);
1615 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1616 return false;
33a34e4e 1617 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1618 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1619 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1620 return false;
1621 }
1622 return true;
1623}
1624
1625static bool
ea5b213a 1626intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1627 uint32_t dp_reg_value,
58e10eb9 1628 uint8_t dp_train_pat)
a4fc5ed6 1629{
4ef69c7a 1630 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1631 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1632 int ret;
1633
ea5b213a
CW		 1634 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1635 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1636
ea5b213a 1637 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1638 DP_TRAINING_PATTERN_SET,
1639 dp_train_pat);
1640
ea5b213a 1641 ret = intel_dp_aux_native_write(intel_dp,
58e10eb9 1642 DP_TRAINING_LANE0_SET,
b34f1f09
KP		 1643 intel_dp->train_set,
1644 intel_dp->lane_count);
1645 if (ret != intel_dp->lane_count)
a4fc5ed6
KP		 1646 return false;
1647
1648 return true;
1649}
1650
33a34e4e 1651/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1652static void
33a34e4e 1653intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1654{
4ef69c7a 1655 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1656 struct drm_i915_private *dev_priv = dev->dev_private;
58e10eb9 1657 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
a4fc5ed6
KP		 1658 int i;
1659 uint8_t voltage;
1660 bool clock_recovery = false;
cdb0e95b 1661 int voltage_tries, loop_tries;
e3421a18 1662 u32 reg;
ea5b213a 1663 uint32_t DP = intel_dp->DP;
a4fc5ed6 1664
e8519464
AJ		 1665 /*
1666 * On CPT we have to enable the port in training pattern 1, which
1667 * will happen below in intel_dp_set_link_train. Otherwise, enable
1668 * the port and wait for it to become active.
1669 */
1670 if (!HAS_PCH_CPT(dev)) {
1671 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1672 POSTING_READ(intel_dp->output_reg);
1673 intel_wait_for_vblank(dev, intel_crtc->pipe);
1674 }
a4fc5ed6 1675
3cf2efb1
CW		 1676 /* Write the link configuration data */
1677 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1678 intel_dp->link_configuration,
1679 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1680
1681 DP |= DP_PORT_EN;
1a2eb460
KP		 1682
1683 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1684 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1685 else
1686 DP &= ~DP_LINK_TRAIN_MASK;
33a34e4e 1687 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1688 voltage = 0xff;
cdb0e95b
KP		 1689 voltage_tries = 0;
1690 loop_tries = 0;
a4fc5ed6
KP		 1691 clock_recovery = false;
1692 for (;;) {
33a34e4e 1693 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1694 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1695 uint32_t signal_levels;
417e822d 1696
1a2eb460
KP		 1697
1698 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1699 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1700 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1701 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1702 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1703 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1704 } else {
93f62dad
KP		 1705 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1706 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1707 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1708 }
a4fc5ed6 1709
1a2eb460 1710 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1711 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1712 else
1713 reg = DP | DP_LINK_TRAIN_PAT_1;
1714
ea5b213a 1715 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1716 DP_TRAINING_PATTERN_1 |
1717 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1718 break;
a4fc5ed6
KP		 1719 /* Set training pattern 1 */
1720
3cf2efb1 1721 udelay(100);
93f62dad
KP		 1722 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1723 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1724 break;
93f62dad 1725 }
a4fc5ed6 1726
93f62dad
KP		 1727 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1728 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1729 clock_recovery = true;
1730 break;
1731 }
1732
1733 /* Check to see if we've tried the max voltage */
1734 for (i = 0; i < intel_dp->lane_count; i++)
1735 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1736 break;
cdb0e95b
KP		 1737 if (i == intel_dp->lane_count) {
1738 ++loop_tries;
1739 if (loop_tries == 5) {
1740 DRM_DEBUG_KMS("too many full retries, give up\n");
1741 break;
1742 }
1743 memset(intel_dp->train_set, 0, 4);
1744 voltage_tries = 0;
1745 continue;
1746 }
a4fc5ed6 1747
3cf2efb1
CW		 1748 /* Check to see if we've tried the same voltage 5 times */
1749 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1750 ++voltage_tries;
1751 if (voltage_tries == 5) {
1752 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1753 break;
cdb0e95b 1754 }
3cf2efb1 1755 } else
cdb0e95b 1756 voltage_tries = 0;
3cf2efb1 1757 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1758
3cf2efb1 1759 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1760 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1761 }
1762
33a34e4e
JB		 1763 intel_dp->DP = DP;
1764}
1765
1766static void
1767intel_dp_complete_link_train(struct intel_dp *intel_dp)
1768{
4ef69c7a 1769 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e
JB		 1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 bool channel_eq = false;
37f80975 1772 int tries, cr_tries;
33a34e4e
JB		 1773 u32 reg;
1774 uint32_t DP = intel_dp->DP;
1775
a4fc5ed6
KP		 1776 /* channel equalization */
1777 tries = 0;
37f80975 1778 cr_tries = 0;
a4fc5ed6
KP		 1779 channel_eq = false;
1780 for (;;) {
33a34e4e 1781 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1782 uint32_t signal_levels;
93f62dad 1783 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1784
37f80975
JB		 1785 if (cr_tries > 5) {
1786 DRM_ERROR("failed to train DP, aborting\n");
1787 intel_dp_link_down(intel_dp);
1788 break;
1789 }
1790
1a2eb460
KP		 1791 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1792 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1793 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1794 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1795 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1796 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1797 } else {
93f62dad 1798 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1799 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1800 }
1801
1a2eb460 1802 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1803 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1804 else
1805 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1806
1807 /* channel eq pattern */
ea5b213a 1808 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1809 DP_TRAINING_PATTERN_2 |
1810 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1811 break;
1812
3cf2efb1 1813 udelay(400);
93f62dad 1814 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1815 break;
a4fc5ed6 1816
37f80975 1817 /* Make sure clock is still ok */
93f62dad 1818 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1819 intel_dp_start_link_train(intel_dp);
1820 cr_tries++;
1821 continue;
1822 }
1823
93f62dad 1824 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1825 channel_eq = true;
1826 break;
1827 }
a4fc5ed6 1828
37f80975
JB		 1829 /* Try 5 times, then try clock recovery if that fails */
1830 if (tries > 5) {
1831 intel_dp_link_down(intel_dp);
1832 intel_dp_start_link_train(intel_dp);
1833 tries = 0;
1834 cr_tries++;
1835 continue;
1836 }
a4fc5ed6 1837
3cf2efb1 1838 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1839 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1840 ++tries;
869184a6 1841 }
3cf2efb1 1842
1a2eb460 1843 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1844 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1845 else
1846 reg = DP | DP_LINK_TRAIN_OFF;
1847
ea5b213a
CW		 1848 I915_WRITE(intel_dp->output_reg, reg);
1849 POSTING_READ(intel_dp->output_reg);
1850 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1851 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1852}
1853
1854static void
ea5b213a 1855intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1856{
4ef69c7a 1857 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1858 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1859 uint32_t DP = intel_dp->DP;
a4fc5ed6 1860
1b39d6f3
CW		 1861 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1862 return;
1863
28c97730 1864 DRM_DEBUG_KMS("\n");
32f9d658 1865
cfcb0fc9 1866 if (is_edp(intel_dp)) {
32f9d658 1867 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1868 I915_WRITE(intel_dp->output_reg, DP);
1869 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1870 udelay(100);
1871 }
1872
1a2eb460 1873 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1874 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1875 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1876 } else {
1877 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1878 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1879 }
fe255d00 1880 POSTING_READ(intel_dp->output_reg);
5eb08b69 1881
fe255d00 1882 msleep(17);
5eb08b69 1883
417e822d 1884 if (is_edp(intel_dp)) {
1a2eb460 1885 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1886 DP |= DP_LINK_TRAIN_OFF_CPT;
1887 else
1888 DP |= DP_LINK_TRAIN_OFF;
1889 }
5bddd17f 1890
1b39d6f3
CW		 1891 if (!HAS_PCH_CPT(dev) &&
1892 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1893 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1894
5bddd17f
EA		 1895 /* Hardware workaround: leaving our transcoder select
1896 * set to transcoder B while it's off will prevent the
1897 * corresponding HDMI output on transcoder A.
1898 *
1899 * Combine this with another hardware workaround:
1900 * transcoder select bit can only be cleared while the
1901 * port is enabled.
1902 */
1903 DP &= ~DP_PIPEB_SELECT;
1904 I915_WRITE(intel_dp->output_reg, DP);
1905
1906 /* Changes to enable or select take place the vblank
1907 * after being written.
1908 */
31acbcc4
CW		 1909 if (crtc == NULL) {
1910 /* We can arrive here never having been attached
1911 * to a CRTC, for instance, due to inheriting
1912 * random state from the BIOS.
1913 *
1914 * If the pipe is not running, play safe and
1915 * wait for the clocks to stabilise before
1916 * continuing.
1917 */
1918 POSTING_READ(intel_dp->output_reg);
1919 msleep(50);
1920 } else
1921 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1922 }
1923
832afda6 1924 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1925 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1926 POSTING_READ(intel_dp->output_reg);
f01eca2e 1927 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1928}
1929
26d61aad
KP		 1930static bool
1931intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1932{
92fd8fd1 1933 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 1934 sizeof(intel_dp->dpcd)) &&
92fd8fd1 1935 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1936 return true;
92fd8fd1
KP		 1937 }
1938
26d61aad 1939 return false;
92fd8fd1
KP		 1940}
1941
a60f0e38
JB		 1942static bool
1943intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1944{
1945 int ret;
1946
1947 ret = intel_dp_aux_native_read_retry(intel_dp,
1948 DP_DEVICE_SERVICE_IRQ_VECTOR,
1949 sink_irq_vector, 1);
1950 if (!ret)
1951 return false;
1952
1953 return true;
1954}
1955
1956static void
1957intel_dp_handle_test_request(struct intel_dp *intel_dp)
1958{
1959 /* NAK by default */
1960 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1961}
1962
a4fc5ed6
KP		 1963/*
1964 * According to DP spec
1965 * 5.1.2:
1966 * 1. Read DPCD
1967 * 2. Configure link according to Receiver Capabilities
1968 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1969 * 4. Check link status on receipt of hot-plug interrupt
1970 */
1971
1972static void
ea5b213a 1973intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 1974{
a60f0e38 1975 u8 sink_irq_vector;
93f62dad 1976 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 1977
d2b996ac
KP		 1978 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1979 return;
59cd09e1 1980
4ef69c7a 1981 if (!intel_dp->base.base.crtc)
a4fc5ed6
KP		 1982 return;
1983
92fd8fd1 1984 /* Try to read receiver status if the link appears to be up */
93f62dad 1985 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 1986 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 1987 return;
1988 }
1989
92fd8fd1 1990 /* Now read the DPCD to see if it's actually running */
26d61aad 1991 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 1992 intel_dp_link_down(intel_dp);
1993 return;
1994 }
1995
a60f0e38
JB		 1996 /* Try to read the source of the interrupt */
1997 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1998 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1999 /* Clear interrupt source */
2000 intel_dp_aux_native_write_1(intel_dp,
2001 DP_DEVICE_SERVICE_IRQ_VECTOR,
2002 sink_irq_vector);
2003
2004 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2005 intel_dp_handle_test_request(intel_dp);
2006 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2007 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2008 }
2009
93f62dad 2010 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2011 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2012 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2013 intel_dp_start_link_train(intel_dp);
2014 intel_dp_complete_link_train(intel_dp);
2015 }
a4fc5ed6 2016}
a4fc5ed6 2017
71ba9000 2018static enum drm_connector_status
26d61aad 2019intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2020{
26d61aad
KP		 2021 if (intel_dp_get_dpcd(intel_dp))
2022 return connector_status_connected;
2023 return connector_status_disconnected;
71ba9000
AJ		 2024}
2025
5eb08b69 2026static enum drm_connector_status
a9756bb5 2027ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2028{
5eb08b69
ZW		 2029 enum drm_connector_status status;
2030
fe16d949
CW		 2031 /* Can't disconnect eDP, but you can close the lid... */
2032 if (is_edp(intel_dp)) {
2033 status = intel_panel_detect(intel_dp->base.base.dev);
2034 if (status == connector_status_unknown)
2035 status = connector_status_connected;
2036 return status;
2037 }
01cb9ea6 2038
26d61aad 2039 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2040}
2041
a4fc5ed6 2042static enum drm_connector_status
a9756bb5 2043g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2044{
4ef69c7a 2045 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2046 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 2047 uint32_t temp, bit;
5eb08b69 2048
ea5b213a 2049 switch (intel_dp->output_reg) {
a4fc5ed6
KP		 2050 case DP_B:
2051 bit = DPB_HOTPLUG_INT_STATUS;
2052 break;
2053 case DP_C:
2054 bit = DPC_HOTPLUG_INT_STATUS;
2055 break;
2056 case DP_D:
2057 bit = DPD_HOTPLUG_INT_STATUS;
2058 break;
2059 default:
2060 return connector_status_unknown;
2061 }
2062
2063 temp = I915_READ(PORT_HOTPLUG_STAT);
2064
2065 if ((temp & bit) == 0)
2066 return connector_status_disconnected;
2067
26d61aad 2068 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2069}
2070
8c241fef
KP		 2071static struct edid *
2072intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2073{
2074 struct intel_dp *intel_dp = intel_attached_dp(connector);
2075 struct edid *edid;
2076
2077 ironlake_edp_panel_vdd_on(intel_dp);
2078 edid = drm_get_edid(connector, adapter);
bd943159 2079 ironlake_edp_panel_vdd_off(intel_dp, false);
8c241fef
KP		 2080 return edid;
2081}
2082
2083static int
2084intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2085{
2086 struct intel_dp *intel_dp = intel_attached_dp(connector);
2087 int ret;
2088
2089 ironlake_edp_panel_vdd_on(intel_dp);
2090 ret = intel_ddc_get_modes(connector, adapter);
bd943159 2091 ironlake_edp_panel_vdd_off(intel_dp, false);
8c241fef
KP		 2092 return ret;
2093}
2094
2095
a9756bb5
ZW		 2096/**
2097 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2098 *
2099 * \return true if DP port is connected.
2100 * \return false if DP port is disconnected.
2101 */
2102static enum drm_connector_status
2103intel_dp_detect(struct drm_connector *connector, bool force)
2104{
2105 struct intel_dp *intel_dp = intel_attached_dp(connector);
2106 struct drm_device *dev = intel_dp->base.base.dev;
2107 enum drm_connector_status status;
2108 struct edid *edid = NULL;
2109
2110 intel_dp->has_audio = false;
2111
2112 if (HAS_PCH_SPLIT(dev))
2113 status = ironlake_dp_detect(intel_dp);
2114 else
2115 status = g4x_dp_detect(intel_dp);
1b9be9d0 2116
ac66ae83
AJ		 2117 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2118 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2119 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2120 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2121
a9756bb5
ZW		 2122 if (status != connector_status_connected)
2123 return status;
2124
f684960e
CW		 2125 if (intel_dp->force_audio) {
2126 intel_dp->has_audio = intel_dp->force_audio > 0;
2127 } else {
8c241fef 2128 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2129 if (edid) {
2130 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2131 connector->display_info.raw_edid = NULL;
2132 kfree(edid);
2133 }
a9756bb5
ZW		 2134 }
2135
2136 return connector_status_connected;
a4fc5ed6
KP		 2137}
2138
2139static int intel_dp_get_modes(struct drm_connector *connector)
2140{
df0e9248 2141 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2142 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 int ret;
a4fc5ed6
KP		 2145
2146 /* We should parse the EDID data and find out if it has an audio sink
2147 */
2148
8c241fef 2149 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2150 if (ret) {
d15456de 2151 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2152 struct drm_display_mode *newmode;
2153 list_for_each_entry(newmode, &connector->probed_modes,
2154 head) {
d15456de
KP		 2155 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2156 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2157 drm_mode_duplicate(dev, newmode);
2158 break;
2159 }
2160 }
2161 }
32f9d658 2162 return ret;
b9efc480 2163 }
32f9d658
ZW		 2164
2165 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2166 if (is_edp(intel_dp)) {
47f0eb22 2167 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2168 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2169 intel_dp->panel_fixed_mode =
47f0eb22 2170 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2171 if (intel_dp->panel_fixed_mode) {
2172 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2173 DRM_MODE_TYPE_PREFERRED;
2174 }
2175 }
d15456de 2176 if (intel_dp->panel_fixed_mode) {
32f9d658 2177 struct drm_display_mode *mode;
d15456de 2178 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2179 drm_mode_probed_add(connector, mode);
2180 return 1;
2181 }
2182 }
2183 return 0;
a4fc5ed6
KP		 2184}
2185
1aad7ac0
CW		 2186static bool
2187intel_dp_detect_audio(struct drm_connector *connector)
2188{
2189 struct intel_dp *intel_dp = intel_attached_dp(connector);
2190 struct edid *edid;
2191 bool has_audio = false;
2192
8c241fef 2193 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2194 if (edid) {
2195 has_audio = drm_detect_monitor_audio(edid);
2196
2197 connector->display_info.raw_edid = NULL;
2198 kfree(edid);
2199 }
2200
2201 return has_audio;
2202}
2203
f684960e
CW		 2204static int
2205intel_dp_set_property(struct drm_connector *connector,
2206 struct drm_property *property,
2207 uint64_t val)
2208{
e953fd7b 2209 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2210 struct intel_dp *intel_dp = intel_attached_dp(connector);
2211 int ret;
2212
2213 ret = drm_connector_property_set_value(connector, property, val);
2214 if (ret)
2215 return ret;
2216
3f43c48d 2217 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2218 int i = val;
2219 bool has_audio;
2220
2221 if (i == intel_dp->force_audio)
f684960e
CW		 2222 return 0;
2223
1aad7ac0 2224 intel_dp->force_audio = i;
f684960e 2225
1aad7ac0
CW		 2226 if (i == 0)
2227 has_audio = intel_dp_detect_audio(connector);
2228 else
2229 has_audio = i > 0;
2230
2231 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2232 return 0;
2233
1aad7ac0 2234 intel_dp->has_audio = has_audio;
f684960e
CW		 2235 goto done;
2236 }
2237
e953fd7b
CW		 2238 if (property == dev_priv->broadcast_rgb_property) {
2239 if (val == !!intel_dp->color_range)
2240 return 0;
2241
2242 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2243 goto done;
2244 }
2245
f684960e
CW		 2246 return -EINVAL;
2247
2248done:
2249 if (intel_dp->base.base.crtc) {
2250 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2251 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2252 crtc->x, crtc->y,
2253 crtc->fb);
2254 }
2255
2256 return 0;
2257}
2258
a4fc5ed6 2259static void
0206e353 2260intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2261{
aaa6fd2a
MG		 2262 struct drm_device *dev = connector->dev;
2263
2264 if (intel_dpd_is_edp(dev))
2265 intel_panel_destroy_backlight(dev);
2266
a4fc5ed6
KP		 2267 drm_sysfs_connector_remove(connector);
2268 drm_connector_cleanup(connector);
55f78c43 2269 kfree(connector);
a4fc5ed6
KP		 2270}
2271
24d05927
DV		 2272static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2273{
2274 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2275
2276 i2c_del_adapter(&intel_dp->adapter);
2277 drm_encoder_cleanup(encoder);
bd943159
KP		 2278 if (is_edp(intel_dp)) {
2279 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2280 ironlake_panel_vdd_off_sync(intel_dp);
2281 }
24d05927
DV		 2282 kfree(intel_dp);
2283}
2284
a4fc5ed6
KP		 2285static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2286 .dpms = intel_dp_dpms,
2287 .mode_fixup = intel_dp_mode_fixup,
d240f20f 2288 .prepare = intel_dp_prepare,
a4fc5ed6 2289 .mode_set = intel_dp_mode_set,
d240f20f 2290 .commit = intel_dp_commit,
a4fc5ed6
KP		 2291};
2292
2293static const struct drm_connector_funcs intel_dp_connector_funcs = {
2294 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 2295 .detect = intel_dp_detect,
2296 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2297 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2298 .destroy = intel_dp_destroy,
2299};
2300
2301static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2302 .get_modes = intel_dp_get_modes,
2303 .mode_valid = intel_dp_mode_valid,
df0e9248 2304 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2305};
2306
a4fc5ed6 2307static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2308 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2309};
2310
995b6762 2311static void
21d40d37 2312intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2313{
ea5b213a 2314 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2315
885a5014 2316 intel_dp_check_link_status(intel_dp);
c8110e52 2317}
6207937d 2318
e3421a18
ZW		 2319/* Return which DP Port should be selected for Transcoder DP control */
2320int
0206e353 2321intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2322{
2323 struct drm_device *dev = crtc->dev;
2324 struct drm_mode_config *mode_config = &dev->mode_config;
2325 struct drm_encoder *encoder;
e3421a18
ZW		 2326
2327 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 2328 struct intel_dp *intel_dp;
2329
d8201ab6 2330 if (encoder->crtc != crtc)
e3421a18
ZW		 2331 continue;
2332
ea5b213a 2333 intel_dp = enc_to_intel_dp(encoder);
417e822d
KP		 2334 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2335 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2336 return intel_dp->output_reg;
e3421a18 2337 }
ea5b213a 2338
e3421a18
ZW		 2339 return -1;
2340}
2341
36e83a18 2342/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2343bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2344{
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2346 struct child_device_config *p_child;
2347 int i;
2348
2349 if (!dev_priv->child_dev_num)
2350 return false;
2351
2352 for (i = 0; i < dev_priv->child_dev_num; i++) {
2353 p_child = dev_priv->child_dev + i;
2354
2355 if (p_child->dvo_port == PORT_IDPD &&
2356 p_child->device_type == DEVICE_TYPE_eDP)
2357 return true;
2358 }
2359 return false;
2360}
2361
f684960e
CW		 2362static void
2363intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2364{
3f43c48d 2365 intel_attach_force_audio_property(connector);
e953fd7b 2366 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2367}
2368
a4fc5ed6
KP		 2369void
2370intel_dp_init(struct drm_device *dev, int output_reg)
2371{
2372 struct drm_i915_private *dev_priv = dev->dev_private;
2373 struct drm_connector *connector;
ea5b213a 2374 struct intel_dp *intel_dp;
21d40d37 2375 struct intel_encoder *intel_encoder;
55f78c43 2376 struct intel_connector *intel_connector;
5eb08b69 2377 const char *name = NULL;
b329530c 2378 int type;
a4fc5ed6 2379
ea5b213a
CW		 2380 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2381 if (!intel_dp)
a4fc5ed6
KP		 2382 return;
2383
3d3dc149 2384 intel_dp->output_reg = output_reg;
d2b996ac 2385 intel_dp->dpms_mode = -1;
3d3dc149 2386
55f78c43
ZW		 2387 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2388 if (!intel_connector) {
ea5b213a 2389 kfree(intel_dp);
55f78c43
ZW		 2390 return;
2391 }
ea5b213a 2392 intel_encoder = &intel_dp->base;
55f78c43 2393
ea5b213a 2394 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2395 if (intel_dpd_is_edp(dev))
ea5b213a 2396 intel_dp->is_pch_edp = true;
b329530c 2397
cfcb0fc9 2398 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2399 type = DRM_MODE_CONNECTOR_eDP;
2400 intel_encoder->type = INTEL_OUTPUT_EDP;
2401 } else {
2402 type = DRM_MODE_CONNECTOR_DisplayPort;
2403 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2404 }
2405
55f78c43 2406 connector = &intel_connector->base;
b329530c 2407 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2408 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2409
eb1f8e4f
DA		 2410 connector->polled = DRM_CONNECTOR_POLL_HPD;
2411
652af9d7 2412 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 2413 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 2414 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 2415 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 2416 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 2417 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 2418
bd943159 2419 if (is_edp(intel_dp)) {
21d40d37 2420 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
bd943159
KP		 2421 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2422 ironlake_panel_vdd_work);
2423 }
6251ec0a 2424
27f8227b 2425 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
a4fc5ed6
KP		 2426 connector->interlace_allowed = true;
2427 connector->doublescan_allowed = 0;
2428
4ef69c7a 2429 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2430 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2431 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2432
df0e9248 2433 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2434 drm_sysfs_connector_add(connector);
2435
2436 /* Set up the DDC bus. */
5eb08b69 2437 switch (output_reg) {
32f9d658
ZW		 2438 case DP_A:
2439 name = "DPDDC-A";
2440 break;
5eb08b69
ZW		 2441 case DP_B:
2442 case PCH_DP_B:
b01f2c3a
JB		 2443 dev_priv->hotplug_supported_mask |=
2444 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2445 name = "DPDDC-B";
2446 break;
2447 case DP_C:
2448 case PCH_DP_C:
b01f2c3a
JB		 2449 dev_priv->hotplug_supported_mask |=
2450 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2451 name = "DPDDC-C";
2452 break;
2453 case DP_D:
2454 case PCH_DP_D:
b01f2c3a
JB		 2455 dev_priv->hotplug_supported_mask |=
2456 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2457 name = "DPDDC-D";
2458 break;
2459 }
2460
89667383
JB		 2461 /* Cache some DPCD data in the eDP case */
2462 if (is_edp(intel_dp)) {
59f3e272 2463 bool ret;
f01eca2e
KP		 2464 struct edp_power_seq cur, vbt;
2465 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2466
2467 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2468 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2469 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2470
f01eca2e
KP		 2471 /* Pull timing values out of registers */
2472 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2473 PANEL_POWER_UP_DELAY_SHIFT;
2474
2475 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2476 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2477
f01eca2e
KP		 2478 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2479 PANEL_LIGHT_OFF_DELAY_SHIFT;
2480
2481 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2482 PANEL_POWER_DOWN_DELAY_SHIFT;
2483
2484 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2485 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2486
2487 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2488 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2489
2490 vbt = dev_priv->edp.pps;
2491
2492 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2493 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2494
2495#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2496
2497 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2498 intel_dp->backlight_on_delay = get_delay(t8);
2499 intel_dp->backlight_off_delay = get_delay(t9);
2500 intel_dp->panel_power_down_delay = get_delay(t10);
2501 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2502
2503 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2504 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2505 intel_dp->panel_power_cycle_delay);
2506
2507 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2508 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2509
2510 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2511 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2512 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2513
59f3e272 2514 if (ret) {
7183dc29
JB		 2515 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2516 dev_priv->no_aux_handshake =
2517 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2518 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2519 } else {
3d3dc149 2520 /* if this fails, presume the device is a ghost */
48898b03 2521 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2522 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2523 intel_dp_destroy(&intel_connector->base);
3d3dc149 2524 return;
89667383 2525 }
89667383
JB		 2526 }
2527
552fb0b7
KP		 2528 intel_dp_i2c_init(intel_dp, intel_connector, name);
2529
21d40d37 2530 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2531
4d926461 2532 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2533 dev_priv->int_edp_connector = connector;
2534 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2535 }
2536
f684960e
CW		 2537 intel_dp_add_properties(intel_dp, connector);
2538
a4fc5ed6
KP		 2539 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2540 * 0xd. Failure to do so will result in spurious interrupts being
2541 * generated on the port when a cable is not attached.
2542 */
2543 if (IS_G4X(dev) && !IS_GM45(dev)) {
2544 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2545 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2546 }
2547}
Linux kernel - Deliverables
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