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drm/i915: add sprite assertion function for VLV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
a4fc5ed6
KP		 180static int
181intel_dp_mode_valid(struct drm_connector *connector,
182 struct drm_display_mode *mode)
183{
df0e9248 184 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 185 struct intel_connector *intel_connector = to_intel_connector(connector);
186 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 187 int target_clock = mode->clock;
188 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 189
dd06f90e
JN		 190 if (is_edp(intel_dp) && fixed_mode) {
191 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 192 return MODE_PANEL;
193
dd06f90e 194 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 195 return MODE_PANEL;
196 }
197
36008365
DV		 198 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
199 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
200
201 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
202 mode_rate = intel_dp_link_required(target_clock, 18);
203
204 if (mode_rate > max_rate)
c4867936 205 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 206
207 if (mode->clock < 10000)
208 return MODE_CLOCK_LOW;
209
0af78a2b
DV		 210 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
211 return MODE_H_ILLEGAL;
212
a4fc5ed6
KP		 213 return MODE_OK;
214}
215
216static uint32_t
217pack_aux(uint8_t *src, int src_bytes)
218{
219 int i;
220 uint32_t v = 0;
221
222 if (src_bytes > 4)
223 src_bytes = 4;
224 for (i = 0; i < src_bytes; i++)
225 v |= ((uint32_t) src[i]) << ((3-i) * 8);
226 return v;
227}
228
229static void
230unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
231{
232 int i;
233 if (dst_bytes > 4)
234 dst_bytes = 4;
235 for (i = 0; i < dst_bytes; i++)
236 dst[i] = src >> ((3-i) * 8);
237}
238
fb0f8fbf
KP		 239/* hrawclock is 1/4 the FSB frequency */
240static int
241intel_hrawclk(struct drm_device *dev)
242{
243 struct drm_i915_private *dev_priv = dev->dev_private;
244 uint32_t clkcfg;
245
9473c8f4
VP		 246 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
247 if (IS_VALLEYVIEW(dev))
248 return 200;
249
fb0f8fbf
KP		 250 clkcfg = I915_READ(CLKCFG);
251 switch (clkcfg & CLKCFG_FSB_MASK) {
252 case CLKCFG_FSB_400:
253 return 100;
254 case CLKCFG_FSB_533:
255 return 133;
256 case CLKCFG_FSB_667:
257 return 166;
258 case CLKCFG_FSB_800:
259 return 200;
260 case CLKCFG_FSB_1067:
261 return 266;
262 case CLKCFG_FSB_1333:
263 return 333;
264 /* these two are just a guess; one of them might be right */
265 case CLKCFG_FSB_1600:
266 case CLKCFG_FSB_1600_ALT:
267 return 400;
268 default:
269 return 133;
270 }
271}
272
ebf33b18
KP		 273static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 276 struct drm_i915_private *dev_priv = dev->dev_private;
277
278 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
279}
280
281static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
282{
30add22d 283 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 284 struct drm_i915_private *dev_priv = dev->dev_private;
285
286 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
287}
288
9b984dae
KP		 289static void
290intel_dp_check_edp(struct intel_dp *intel_dp)
291{
30add22d 292 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 293 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 294
9b984dae
KP		 295 if (!is_edp(intel_dp))
296 return;
ebf33b18 297 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 298 WARN(1, "eDP powered off while attempting aux channel communication.\n");
299 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 300 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 301 I915_READ(PCH_PP_CONTROL));
302 }
303}
304
9ee32fea
DV		 305static uint32_t
306intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
307{
308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
309 struct drm_device *dev = intel_dig_port->base.base.dev;
310 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 311 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 312 uint32_t status;
313 bool done;
314
ef04f00d 315#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 316 if (has_aux_irq)
b90f5176
PZ		 317 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
318 msecs_to_jiffies(10));
9ee32fea
DV		 319 else
320 done = wait_for_atomic(C, 10) == 0;
321 if (!done)
322 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
323 has_aux_irq);
324#undef C
325
326 return status;
327}
328
a4fc5ed6 329static int
ea5b213a 330intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 331 uint8_t *send, int send_bytes,
332 uint8_t *recv, int recv_size)
333{
174edf1f
PZ		 334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 336 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 337 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 338 uint32_t ch_data = ch_ctl + 4;
9ee32fea 339 int i, ret, recv_bytes;
a4fc5ed6 340 uint32_t status;
fb0f8fbf 341 uint32_t aux_clock_divider;
6b4e0a93 342 int try, precharge;
9ee32fea
DV		 343 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
344
345 /* dp aux is extremely sensitive to irq latency, hence request the
346 * lowest possible wakeup latency and so prevent the cpu from going into
347 * deep sleep states.
348 */
349 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 350
9b984dae 351 intel_dp_check_edp(intel_dp);
a4fc5ed6 352 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 353 * and would like to run at 2MHz. So, take the
354 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 355 *
356 * Note that PCH attached eDP panels should use a 125MHz input
357 * clock divider.
a4fc5ed6 358 */
1c95822a 359 if (is_cpu_edp(intel_dp)) {
affa9354 360 if (HAS_DDI(dev))
b8fc2f6a
PZ		 361 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
362 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 363 aux_clock_divider = 100;
364 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 365 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 366 else
367 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
368 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 369 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 370 else
371 aux_clock_divider = intel_hrawclk(dev) / 2;
372
6b4e0a93
DV		 373 if (IS_GEN6(dev))
374 precharge = 3;
375 else
376 precharge = 5;
377
11bee43e
JB		 378 /* Try to wait for any previous AUX channel activity */
379 for (try = 0; try < 3; try++) {
ef04f00d 380 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 381 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
382 break;
383 msleep(1);
384 }
385
386 if (try == 3) {
387 WARN(1, "dp_aux_ch not started status 0x%08x\n",
388 I915_READ(ch_ctl));
9ee32fea
DV		 389 ret = -EBUSY;
390 goto out;
4f7f7b7e
CW		 391 }
392
fb0f8fbf
KP		 393 /* Must try at least 3 times according to DP spec */
394 for (try = 0; try < 5; try++) {
395 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 396 for (i = 0; i < send_bytes; i += 4)
397 I915_WRITE(ch_data + i,
398 pack_aux(send + i, send_bytes - i));
0206e353 399
fb0f8fbf 400 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 401 I915_WRITE(ch_ctl,
402 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 403 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 404 DP_AUX_CH_CTL_TIME_OUT_400us |
405 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
406 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
407 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
408 DP_AUX_CH_CTL_DONE |
409 DP_AUX_CH_CTL_TIME_OUT_ERROR |
410 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 411
412 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 413
fb0f8fbf 414 /* Clear done status and any errors */
4f7f7b7e
CW		 415 I915_WRITE(ch_ctl,
416 status |
417 DP_AUX_CH_CTL_DONE |
418 DP_AUX_CH_CTL_TIME_OUT_ERROR |
419 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 420
421 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
422 DP_AUX_CH_CTL_RECEIVE_ERROR))
423 continue;
4f7f7b7e 424 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 425 break;
426 }
427
a4fc5ed6 428 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 429 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 430 ret = -EBUSY;
431 goto out;
a4fc5ed6
KP		 432 }
433
434 /* Check for timeout or receive error.
435 * Timeouts occur when the sink is not connected
436 */
a5b3da54 437 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 438 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 439 ret = -EIO;
440 goto out;
a5b3da54 441 }
1ae8c0a5
KP		 442
443 /* Timeouts occur when the device isn't connected, so they're
444 * "normal" -- don't fill the kernel log with these */
a5b3da54 445 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 446 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 447 ret = -ETIMEDOUT;
448 goto out;
a4fc5ed6
KP		 449 }
450
451 /* Unload any bytes sent back from the other side */
452 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
453 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 454 if (recv_bytes > recv_size)
455 recv_bytes = recv_size;
0206e353 456
4f7f7b7e
CW		 457 for (i = 0; i < recv_bytes; i += 4)
458 unpack_aux(I915_READ(ch_data + i),
459 recv + i, recv_bytes - i);
a4fc5ed6 460
9ee32fea
DV		 461 ret = recv_bytes;
462out:
463 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
464
465 return ret;
a4fc5ed6
KP		 466}
467
468/* Write data to the aux channel in native mode */
469static int
ea5b213a 470intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 471 uint16_t address, uint8_t *send, int send_bytes)
472{
473 int ret;
474 uint8_t msg[20];
475 int msg_bytes;
476 uint8_t ack;
477
9b984dae 478 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 479 if (send_bytes > 16)
480 return -1;
481 msg[0] = AUX_NATIVE_WRITE << 4;
482 msg[1] = address >> 8;
eebc863e 483 msg[2] = address & 0xff;
a4fc5ed6
KP		 484 msg[3] = send_bytes - 1;
485 memcpy(&msg[4], send, send_bytes);
486 msg_bytes = send_bytes + 4;
487 for (;;) {
ea5b213a 488 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 489 if (ret < 0)
490 return ret;
491 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
492 break;
493 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
494 udelay(100);
495 else
a5b3da54 496 return -EIO;
a4fc5ed6
KP		 497 }
498 return send_bytes;
499}
500
501/* Write a single byte to the aux channel in native mode */
502static int
ea5b213a 503intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 504 uint16_t address, uint8_t byte)
505{
ea5b213a 506 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 507}
508
509/* read bytes from a native aux channel */
510static int
ea5b213a 511intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 512 uint16_t address, uint8_t *recv, int recv_bytes)
513{
514 uint8_t msg[4];
515 int msg_bytes;
516 uint8_t reply[20];
517 int reply_bytes;
518 uint8_t ack;
519 int ret;
520
9b984dae 521 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 522 msg[0] = AUX_NATIVE_READ << 4;
523 msg[1] = address >> 8;
524 msg[2] = address & 0xff;
525 msg[3] = recv_bytes - 1;
526
527 msg_bytes = 4;
528 reply_bytes = recv_bytes + 1;
529
530 for (;;) {
ea5b213a 531 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 532 reply, reply_bytes);
a5b3da54
KP		 533 if (ret == 0)
534 return -EPROTO;
535 if (ret < 0)
a4fc5ed6
KP		 536 return ret;
537 ack = reply[0];
538 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
539 memcpy(recv, reply + 1, ret - 1);
540 return ret - 1;
541 }
542 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
543 udelay(100);
544 else
a5b3da54 545 return -EIO;
a4fc5ed6
KP		 546 }
547}
548
549static int
ab2c0672
DA		 550intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
551 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 552{
ab2c0672 553 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 554 struct intel_dp *intel_dp = container_of(adapter,
555 struct intel_dp,
556 adapter);
ab2c0672
DA		 557 uint16_t address = algo_data->address;
558 uint8_t msg[5];
559 uint8_t reply[2];
8316f337 560 unsigned retry;
ab2c0672
DA		 561 int msg_bytes;
562 int reply_bytes;
563 int ret;
564
9b984dae 565 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 566 /* Set up the command byte */
567 if (mode & MODE_I2C_READ)
568 msg[0] = AUX_I2C_READ << 4;
569 else
570 msg[0] = AUX_I2C_WRITE << 4;
571
572 if (!(mode & MODE_I2C_STOP))
573 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 574
ab2c0672
DA		 575 msg[1] = address >> 8;
576 msg[2] = address;
577
578 switch (mode) {
579 case MODE_I2C_WRITE:
580 msg[3] = 0;
581 msg[4] = write_byte;
582 msg_bytes = 5;
583 reply_bytes = 1;
584 break;
585 case MODE_I2C_READ:
586 msg[3] = 0;
587 msg_bytes = 4;
588 reply_bytes = 2;
589 break;
590 default:
591 msg_bytes = 3;
592 reply_bytes = 1;
593 break;
594 }
595
8316f337
DF		 596 for (retry = 0; retry < 5; retry++) {
597 ret = intel_dp_aux_ch(intel_dp,
598 msg, msg_bytes,
599 reply, reply_bytes);
ab2c0672 600 if (ret < 0) {
3ff99164 601 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 602 return ret;
603 }
8316f337
DF		 604
605 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
606 case AUX_NATIVE_REPLY_ACK:
607 /* I2C-over-AUX Reply field is only valid
608 * when paired with AUX ACK.
609 */
610 break;
611 case AUX_NATIVE_REPLY_NACK:
612 DRM_DEBUG_KMS("aux_ch native nack\n");
613 return -EREMOTEIO;
614 case AUX_NATIVE_REPLY_DEFER:
615 udelay(100);
616 continue;
617 default:
618 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
619 reply[0]);
620 return -EREMOTEIO;
621 }
622
ab2c0672
DA		 623 switch (reply[0] & AUX_I2C_REPLY_MASK) {
624 case AUX_I2C_REPLY_ACK:
625 if (mode == MODE_I2C_READ) {
626 *read_byte = reply[1];
627 }
628 return reply_bytes - 1;
629 case AUX_I2C_REPLY_NACK:
8316f337 630 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 631 return -EREMOTEIO;
632 case AUX_I2C_REPLY_DEFER:
8316f337 633 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 634 udelay(100);
635 break;
636 default:
8316f337 637 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 638 return -EREMOTEIO;
639 }
640 }
8316f337
DF		 641
642 DRM_ERROR("too many retries, giving up\n");
643 return -EREMOTEIO;
a4fc5ed6
KP		 644}
645
646static int
ea5b213a 647intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 648 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 649{
0b5c541b
KP		 650 int ret;
651
d54e9d28 652 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 653 intel_dp->algo.running = false;
654 intel_dp->algo.address = 0;
655 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
656
0206e353 657 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 658 intel_dp->adapter.owner = THIS_MODULE;
659 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 660 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 661 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
662 intel_dp->adapter.algo_data = &intel_dp->algo;
663 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
664
0b5c541b
KP		 665 ironlake_edp_panel_vdd_on(intel_dp);
666 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 667 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 668 return ret;
a4fc5ed6
KP		 669}
670
00c09d70 671bool
5bfe2ac0
DV		 672intel_dp_compute_config(struct intel_encoder *encoder,
673 struct intel_crtc_config *pipe_config)
a4fc5ed6 674{
5bfe2ac0 675 struct drm_device *dev = encoder->base.dev;
36008365 676 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV		 677 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
678 struct drm_display_mode *mode = &pipe_config->requested_mode;
679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
dd06f90e 680 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 681 int lane_count, clock;
397fe157 682 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 683 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 684 int bpp, mode_rate;
a4fc5ed6 685 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 686 int target_clock, link_avail, link_clock;
a4fc5ed6 687
5bfe2ac0
DV		 688 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
689 pipe_config->has_pch_encoder = true;
690
dd06f90e
JN		 691 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
692 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
693 adjusted_mode);
53b41837
YN		 694 intel_pch_panel_fitting(dev,
695 intel_connector->panel.fitting_mode,
1d8e1c75 696 mode, adjusted_mode);
0d3a1bee 697 }
36008365
DV		 698 /* We need to take the panel's fixed mode into account. */
699 target_clock = adjusted_mode->clock;
0d3a1bee 700
cb1793ce 701 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 702 return false;
703
083f9560
DV		 704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
705 "max bw %02x pixel clock %iKHz\n",
71244653 706 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 707
36008365
DV		 708 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
709 * bpc in between. */
710 bpp = 8*3;
711 if (is_edp(intel_dp) && dev_priv->edp.bpp)
712 bpp = min_t(int, bpp, dev_priv->edp.bpp);
713
714 for (; bpp >= 6*3; bpp -= 2*3) {
715 mode_rate = intel_dp_link_required(target_clock, bpp);
716
717 for (clock = 0; clock <= max_clock; clock++) {
718 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
719 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
720 link_avail = intel_dp_max_data_rate(link_clock,
721 lane_count);
722
723 if (mode_rate <= link_avail) {
724 goto found;
725 }
726 }
727 }
728 }
c4867936 729
36008365 730 return false;
3685a8f3 731
36008365 732found:
55bc60db
VS		 733 if (intel_dp->color_range_auto) {
734 /*
735 * See:
736 * CEA-861-E - 5.1 Default Encoding Parameters
737 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
738 */
18316c8c 739 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 740 intel_dp->color_range = DP_COLOR_RANGE_16_235;
741 else
742 intel_dp->color_range = 0;
743 }
744
3685a8f3 745 if (intel_dp->color_range)
50f3b016 746 pipe_config->limited_color_range = true;
3685a8f3 747
36008365
DV		 748 intel_dp->link_bw = bws[clock];
749 intel_dp->lane_count = lane_count;
750 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
751 pipe_config->pipe_bpp = bpp;
fe27d53e 752
36008365
DV		 753 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
754 intel_dp->link_bw, intel_dp->lane_count,
755 adjusted_mode->clock, bpp);
756 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
757 mode_rate, link_avail);
758
759 return true;
a4fc5ed6
KP		 760}
761
a4fc5ed6
KP		 762void
763intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
764 struct drm_display_mode *adjusted_mode)
765{
766 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 767 struct intel_encoder *intel_encoder;
768 struct intel_dp *intel_dp;
a4fc5ed6
KP		 769 struct drm_i915_private *dev_priv = dev->dev_private;
770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 771 int lane_count = 4;
e69d0bc1 772 struct intel_link_m_n m_n;
9db4a9c7 773 int pipe = intel_crtc->pipe;
afe2fcf5 774 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 775
776 /*
21d40d37 777 * Find the lane count in the intel_encoder private
a4fc5ed6 778 */
fa90ecef
PZ		 779 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
780 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 781
fa90ecef
PZ		 782 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
783 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 784 {
ea5b213a 785 lane_count = intel_dp->lane_count;
51190667 786 break;
a4fc5ed6
KP		 787 }
788 }
789
790 /*
791 * Compute the GMCH and Link ratios. The '3' here is
792 * the number of bytes_per_pixel post-LUT, which we always
793 * set up for 8-bits of R/G/B, or 3 bytes total.
794 */
965e0c48 795 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane_count,
e69d0bc1 796 mode->clock, adjusted_mode->clock, &m_n);
a4fc5ed6 797
22b8bf17 798 if (HAS_DDI(dev)) {
afe2fcf5
PZ		 799 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
800 TU_SIZE(m_n.tu) | m_n.gmch_m);
801 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
802 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
803 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 804 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 805 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 806 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
807 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
808 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 809 } else if (IS_VALLEYVIEW(dev)) {
810 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
811 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
812 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
813 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 814 } else {
9db4a9c7 815 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 816 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 817 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
818 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
819 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 820 }
821}
822
247d89f6
PZ		 823void intel_dp_init_link_config(struct intel_dp *intel_dp)
824{
825 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
826 intel_dp->link_configuration[0] = intel_dp->link_bw;
827 intel_dp->link_configuration[1] = intel_dp->lane_count;
828 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
829 /*
830 * Check for DPCD version > 1.1 and enhanced framing support
831 */
832 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
833 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
834 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
835 }
836}
837
ea9b6006
DV		 838static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
839{
840 struct drm_device *dev = crtc->dev;
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 u32 dpa_ctl;
843
844 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
845 dpa_ctl = I915_READ(DP_A);
846 dpa_ctl &= ~DP_PLL_FREQ_MASK;
847
848 if (clock < 200000) {
1ce17038
DV		 849 /* For a long time we've carried around a ILK-DevA w/a for the
850 * 160MHz clock. If we're really unlucky, it's still required.
851 */
852 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 853 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 854 } else {
855 dpa_ctl |= DP_PLL_FREQ_270MHZ;
856 }
1ce17038 857
ea9b6006
DV		 858 I915_WRITE(DP_A, dpa_ctl);
859
860 POSTING_READ(DP_A);
861 udelay(500);
862}
863
a4fc5ed6
KP		 864static void
865intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
866 struct drm_display_mode *adjusted_mode)
867{
e3421a18 868 struct drm_device *dev = encoder->dev;
417e822d 869 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 870 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 871 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
873
417e822d 874 /*
1a2eb460 875 * There are four kinds of DP registers:
417e822d
KP		 876 *
877 * IBX PCH
1a2eb460
KP		 878 * SNB CPU
879 * IVB CPU
417e822d
KP		 880 * CPT PCH
881 *
882 * IBX PCH and CPU are the same for almost everything,
883 * except that the CPU DP PLL is configured in this
884 * register
885 *
886 * CPT PCH is quite different, having many bits moved
887 * to the TRANS_DP_CTL register instead. That
888 * configuration happens (oddly) in ironlake_pch_enable
889 */
9c9e7927 890
417e822d
KP		 891 /* Preserve the BIOS-computed detected bit. This is
892 * supposed to be read-only.
893 */
894 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 895
417e822d 896 /* Handle DP bits in common between all three register formats */
417e822d 897 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 898
ea5b213a 899 switch (intel_dp->lane_count) {
a4fc5ed6 900 case 1:
ea5b213a 901 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 902 break;
903 case 2:
ea5b213a 904 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 905 break;
906 case 4:
ea5b213a 907 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 908 break;
909 }
e0dac65e
WF		 910 if (intel_dp->has_audio) {
911 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
912 pipe_name(intel_crtc->pipe));
ea5b213a 913 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 914 intel_write_eld(encoder, adjusted_mode);
915 }
247d89f6
PZ		 916
917 intel_dp_init_link_config(intel_dp);
a4fc5ed6 918
417e822d 919 /* Split out the IBX/CPU vs CPT settings */
32f9d658 920
19c03924 921 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 922 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
923 intel_dp->DP |= DP_SYNC_HS_HIGH;
924 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
925 intel_dp->DP |= DP_SYNC_VS_HIGH;
926 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
927
928 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
929 intel_dp->DP |= DP_ENHANCED_FRAMING;
930
931 intel_dp->DP |= intel_crtc->pipe << 29;
932
933 /* don't miss out required setting for eDP */
1a2eb460
KP		 934 if (adjusted_mode->clock < 200000)
935 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
936 else
937 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
938 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
3685a8f3
VS		 939 if (!HAS_PCH_SPLIT(dev))
940 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 941
942 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
943 intel_dp->DP |= DP_SYNC_HS_HIGH;
944 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
945 intel_dp->DP |= DP_SYNC_VS_HIGH;
946 intel_dp->DP |= DP_LINK_TRAIN_OFF;
947
948 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
949 intel_dp->DP |= DP_ENHANCED_FRAMING;
950
951 if (intel_crtc->pipe == 1)
952 intel_dp->DP |= DP_PIPEB_SELECT;
953
954 if (is_cpu_edp(intel_dp)) {
955 /* don't miss out required setting for eDP */
417e822d
KP		 956 if (adjusted_mode->clock < 200000)
957 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
958 else
959 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
960 }
961 } else {
962 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 963 }
ea9b6006 964
5d66d5b6 965 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 966 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 967}
968
99ea7127
KP		 969#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
970#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
971
972#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
973#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
974
975#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
976#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
977
978static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
979 u32 mask,
980 u32 value)
bd943159 981{
30add22d 982 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 983 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 984
99ea7127
KP		 985 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
986 mask, value,
987 I915_READ(PCH_PP_STATUS),
988 I915_READ(PCH_PP_CONTROL));
32ce697c 989
99ea7127
KP		 990 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
991 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
992 I915_READ(PCH_PP_STATUS),
993 I915_READ(PCH_PP_CONTROL));
32ce697c 994 }
99ea7127 995}
32ce697c 996
99ea7127
KP		 997static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
998{
999 DRM_DEBUG_KMS("Wait for panel power on\n");
1000 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1001}
1002
99ea7127
KP		 1003static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1004{
1005 DRM_DEBUG_KMS("Wait for panel power off time\n");
1006 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1007}
1008
1009static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1010{
1011 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1012 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1013}
1014
1015
832dd3c1
KP		 1016/* Read the current pp_control value, unlocking the register if it
1017 * is locked
1018 */
1019
1020static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1021{
1022 u32 control = I915_READ(PCH_PP_CONTROL);
1023
1024 control &= ~PANEL_UNLOCK_MASK;
1025 control |= PANEL_UNLOCK_REGS;
1026 return control;
bd943159
KP		 1027}
1028
82a4d9c0 1029void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1030{
30add22d 1031 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 u32 pp;
1034
97af61f5
KP		 1035 if (!is_edp(intel_dp))
1036 return;
f01eca2e 1037 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1038
bd943159
KP		 1039 WARN(intel_dp->want_panel_vdd,
1040 "eDP VDD already requested on\n");
1041
1042 intel_dp->want_panel_vdd = true;
99ea7127 1043
bd943159
KP		 1044 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1045 DRM_DEBUG_KMS("eDP VDD already on\n");
1046 return;
1047 }
1048
99ea7127
KP		 1049 if (!ironlake_edp_have_panel_power(intel_dp))
1050 ironlake_wait_panel_power_cycle(intel_dp);
1051
832dd3c1 1052 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1053 pp |= EDP_FORCE_VDD;
1054 I915_WRITE(PCH_PP_CONTROL, pp);
1055 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1056 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1057 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1058
1059 /*
1060 * If the panel wasn't on, delay before accessing aux channel
1061 */
1062 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1063 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1064 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1065 }
5d613501
JB		 1066}
1067
bd943159 1068static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1069{
30add22d 1070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 u32 pp;
1073
a0e99e68
DV		 1074 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1075
bd943159 1076 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1077 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1078 pp &= ~EDP_FORCE_VDD;
1079 I915_WRITE(PCH_PP_CONTROL, pp);
1080 POSTING_READ(PCH_PP_CONTROL);
1081
1082 /* Make sure sequencer is idle before allowing subsequent activity */
1083 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1084 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1085
1086 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1087 }
1088}
5d613501 1089
bd943159
KP		 1090static void ironlake_panel_vdd_work(struct work_struct *__work)
1091{
1092 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1093 struct intel_dp, panel_vdd_work);
30add22d 1094 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1095
627f7675 1096 mutex_lock(&dev->mode_config.mutex);
bd943159 1097 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1098 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1099}
1100
82a4d9c0 1101void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1102{
97af61f5
KP		 1103 if (!is_edp(intel_dp))
1104 return;
5d613501 1105
bd943159
KP		 1106 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1107 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1108
bd943159
KP		 1109 intel_dp->want_panel_vdd = false;
1110
1111 if (sync) {
1112 ironlake_panel_vdd_off_sync(intel_dp);
1113 } else {
1114 /*
1115 * Queue the timer to fire a long
1116 * time from now (relative to the power down delay)
1117 * to keep the panel power up across a sequence of operations
1118 */
1119 schedule_delayed_work(&intel_dp->panel_vdd_work,
1120 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1121 }
5d613501
JB		 1122}
1123
82a4d9c0 1124void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1125{
30add22d 1126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1127 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1128 u32 pp;
9934c132 1129
97af61f5 1130 if (!is_edp(intel_dp))
bd943159 1131 return;
99ea7127
KP		 1132
1133 DRM_DEBUG_KMS("Turn eDP power on\n");
1134
1135 if (ironlake_edp_have_panel_power(intel_dp)) {
1136 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1137 return;
99ea7127 1138 }
9934c132 1139
99ea7127 1140 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1141
99ea7127 1142 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1143 if (IS_GEN5(dev)) {
1144 /* ILK workaround: disable reset around power sequence */
1145 pp &= ~PANEL_POWER_RESET;
1146 I915_WRITE(PCH_PP_CONTROL, pp);
1147 POSTING_READ(PCH_PP_CONTROL);
1148 }
37c6c9b0 1149
1c0ae80a 1150 pp |= POWER_TARGET_ON;
99ea7127
KP		 1151 if (!IS_GEN5(dev))
1152 pp |= PANEL_POWER_RESET;
1153
9934c132 1154 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1155 POSTING_READ(PCH_PP_CONTROL);
9934c132 1156
99ea7127 1157 ironlake_wait_panel_on(intel_dp);
9934c132 1158
05ce1a49
KP		 1159 if (IS_GEN5(dev)) {
1160 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1161 I915_WRITE(PCH_PP_CONTROL, pp);
1162 POSTING_READ(PCH_PP_CONTROL);
1163 }
9934c132
JB		 1164}
1165
82a4d9c0 1166void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1167{
30add22d 1168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1169 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1170 u32 pp;
9934c132 1171
97af61f5
KP		 1172 if (!is_edp(intel_dp))
1173 return;
37c6c9b0 1174
99ea7127 1175 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1176
6cb49835 1177 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1178
99ea7127 1179 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1180 /* We need to switch off panel power _and_ force vdd, for otherwise some
1181 * panels get very unhappy and cease to work. */
1182 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1183 I915_WRITE(PCH_PP_CONTROL, pp);
1184 POSTING_READ(PCH_PP_CONTROL);
9934c132 1185
35a38556
DV		 1186 intel_dp->want_panel_vdd = false;
1187
99ea7127 1188 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1189}
1190
d6c50ff8 1191void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1192{
da63a9f2
PZ		 1193 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1194 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1195 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1196 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1197 u32 pp;
1198
f01eca2e
KP		 1199 if (!is_edp(intel_dp))
1200 return;
1201
28c97730 1202 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1203 /*
1204 * If we enable the backlight right away following a panel power
1205 * on, we may see slight flicker as the panel syncs with the eDP
1206 * link. So delay a bit to make sure the image is solid before
1207 * allowing it to appear.
1208 */
f01eca2e 1209 msleep(intel_dp->backlight_on_delay);
832dd3c1 1210 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1211 pp |= EDP_BLC_ENABLE;
1212 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1213 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1214
1215 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1216}
1217
d6c50ff8 1218void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1219{
30add22d 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 u32 pp;
1223
f01eca2e
KP		 1224 if (!is_edp(intel_dp))
1225 return;
1226
035aa3de
DV		 1227 intel_panel_disable_backlight(dev);
1228
28c97730 1229 DRM_DEBUG_KMS("\n");
832dd3c1 1230 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1231 pp &= ~EDP_BLC_ENABLE;
1232 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1233 POSTING_READ(PCH_PP_CONTROL);
1234 msleep(intel_dp->backlight_off_delay);
32f9d658 1235}
a4fc5ed6 1236
2bd2ad64 1237static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1238{
da63a9f2
PZ		 1239 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1240 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1241 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 dpa_ctl;
1244
2bd2ad64
DV		 1245 assert_pipe_disabled(dev_priv,
1246 to_intel_crtc(crtc)->pipe);
1247
d240f20f
JB		 1248 DRM_DEBUG_KMS("\n");
1249 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1250 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1251 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1252
1253 /* We don't adjust intel_dp->DP while tearing down the link, to
1254 * facilitate link retraining (e.g. after hotplug). Hence clear all
1255 * enable bits here to ensure that we don't enable too much. */
1256 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1257 intel_dp->DP |= DP_PLL_ENABLE;
1258 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1259 POSTING_READ(DP_A);
1260 udelay(200);
d240f20f
JB		 1261}
1262
2bd2ad64 1263static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1264{
da63a9f2
PZ		 1265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1266 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1267 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1268 struct drm_i915_private *dev_priv = dev->dev_private;
1269 u32 dpa_ctl;
1270
2bd2ad64
DV		 1271 assert_pipe_disabled(dev_priv,
1272 to_intel_crtc(crtc)->pipe);
1273
d240f20f 1274 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1275 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1276 "dp pll off, should be on\n");
1277 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1278
1279 /* We can't rely on the value tracked for the DP register in
1280 * intel_dp->DP because link_down must not change that (otherwise link
1281 * re-training will fail. */
298b0b39 1282 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1283 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1284 POSTING_READ(DP_A);
d240f20f
JB		 1285 udelay(200);
1286}
1287
c7ad3810 1288/* If the sink supports it, try to set the power state appropriately */
c19b0669 1289void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1290{
1291 int ret, i;
1292
1293 /* Should have a valid DPCD by this point */
1294 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1295 return;
1296
1297 if (mode != DRM_MODE_DPMS_ON) {
1298 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1299 DP_SET_POWER_D3);
1300 if (ret != 1)
1301 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1302 } else {
1303 /*
1304 * When turning on, we need to retry for 1ms to give the sink
1305 * time to wake up.
1306 */
1307 for (i = 0; i < 3; i++) {
1308 ret = intel_dp_aux_native_write_1(intel_dp,
1309 DP_SET_POWER,
1310 DP_SET_POWER_D0);
1311 if (ret == 1)
1312 break;
1313 msleep(1);
1314 }
1315 }
1316}
1317
19d8fe15
DV		 1318static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1319 enum pipe *pipe)
d240f20f 1320{
19d8fe15
DV		 1321 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1322 struct drm_device *dev = encoder->base.dev;
1323 struct drm_i915_private *dev_priv = dev->dev_private;
1324 u32 tmp = I915_READ(intel_dp->output_reg);
1325
1326 if (!(tmp & DP_PORT_EN))
1327 return false;
1328
5d66d5b6 1329 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1330 *pipe = PORT_TO_PIPE_CPT(tmp);
1331 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1332 *pipe = PORT_TO_PIPE(tmp);
1333 } else {
1334 u32 trans_sel;
1335 u32 trans_dp;
1336 int i;
1337
1338 switch (intel_dp->output_reg) {
1339 case PCH_DP_B:
1340 trans_sel = TRANS_DP_PORT_SEL_B;
1341 break;
1342 case PCH_DP_C:
1343 trans_sel = TRANS_DP_PORT_SEL_C;
1344 break;
1345 case PCH_DP_D:
1346 trans_sel = TRANS_DP_PORT_SEL_D;
1347 break;
1348 default:
1349 return true;
1350 }
1351
1352 for_each_pipe(i) {
1353 trans_dp = I915_READ(TRANS_DP_CTL(i));
1354 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1355 *pipe = i;
1356 return true;
1357 }
1358 }
19d8fe15 1359
4a0833ec
DV		 1360 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1361 intel_dp->output_reg);
1362 }
d240f20f 1363
deb18211 1364 return false;
19d8fe15 1365}
d240f20f 1366
e8cb4558 1367static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1368{
e8cb4558 1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1370
1371 /* Make sure the panel is off before trying to change the mode. But also
1372 * ensure that we have vdd while we switch off the panel. */
1373 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1374 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1375 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1376 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1377
1378 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1379 if (!is_cpu_edp(intel_dp))
1380 intel_dp_link_down(intel_dp);
d240f20f
JB		 1381}
1382
2bd2ad64 1383static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1384{
2bd2ad64
DV		 1385 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1386
3739850b
DV		 1387 if (is_cpu_edp(intel_dp)) {
1388 intel_dp_link_down(intel_dp);
2bd2ad64 1389 ironlake_edp_pll_off(intel_dp);
3739850b 1390 }
2bd2ad64
DV		 1391}
1392
e8cb4558 1393static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1394{
e8cb4558
DV		 1395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1396 struct drm_device *dev = encoder->base.dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1399
0c33d8d7
DV		 1400 if (WARN_ON(dp_reg & DP_PORT_EN))
1401 return;
5d613501 1402
97af61f5 1403 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1404 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1405 intel_dp_start_link_train(intel_dp);
97af61f5 1406 ironlake_edp_panel_on(intel_dp);
bd943159 1407 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1408 intel_dp_complete_link_train(intel_dp);
f01eca2e 1409 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1410}
1411
2bd2ad64 1412static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1413{
2bd2ad64 1414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 1415
2bd2ad64
DV		 1416 if (is_cpu_edp(intel_dp))
1417 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1418}
1419
1420/*
df0c237d
JB		 1421 * Native read with retry for link status and receiver capability reads for
1422 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1423 */
1424static bool
df0c237d
JB		 1425intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1426 uint8_t *recv, int recv_bytes)
a4fc5ed6 1427{
61da5fab
JB		 1428 int ret, i;
1429
df0c237d
JB		 1430 /*
1431 * Sinks are *supposed* to come up within 1ms from an off state,
1432 * but we're also supposed to retry 3 times per the spec.
1433 */
61da5fab 1434 for (i = 0; i < 3; i++) {
df0c237d
JB		 1435 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1436 recv_bytes);
1437 if (ret == recv_bytes)
61da5fab
JB		 1438 return true;
1439 msleep(1);
1440 }
a4fc5ed6 1441
61da5fab 1442 return false;
a4fc5ed6
KP		 1443}
1444
1445/*
1446 * Fetch AUX CH registers 0x202 - 0x207 which contain
1447 * link status information
1448 */
1449static bool
93f62dad 1450intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1451{
df0c237d
JB		 1452 return intel_dp_aux_native_read_retry(intel_dp,
1453 DP_LANE0_1_STATUS,
93f62dad 1454 link_status,
df0c237d 1455 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1456}
1457
a4fc5ed6
KP		 1458#if 0
1459static char *voltage_names[] = {
1460 "0.4V", "0.6V", "0.8V", "1.2V"
1461};
1462static char *pre_emph_names[] = {
1463 "0dB", "3.5dB", "6dB", "9.5dB"
1464};
1465static char *link_train_names[] = {
1466 "pattern 1", "pattern 2", "idle", "off"
1467};
1468#endif
1469
1470/*
1471 * These are source-specific values; current Intel hardware supports
1472 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1473 */
a4fc5ed6
KP		 1474
1475static uint8_t
1a2eb460 1476intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1477{
30add22d 1478 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1479
1480 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1481 return DP_TRAIN_VOLTAGE_SWING_800;
1482 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1483 return DP_TRAIN_VOLTAGE_SWING_1200;
1484 else
1485 return DP_TRAIN_VOLTAGE_SWING_800;
1486}
1487
1488static uint8_t
1489intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1490{
30add22d 1491 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1492
22b8bf17 1493 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1494 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1495 case DP_TRAIN_VOLTAGE_SWING_400:
1496 return DP_TRAIN_PRE_EMPHASIS_9_5;
1497 case DP_TRAIN_VOLTAGE_SWING_600:
1498 return DP_TRAIN_PRE_EMPHASIS_6;
1499 case DP_TRAIN_VOLTAGE_SWING_800:
1500 return DP_TRAIN_PRE_EMPHASIS_3_5;
1501 case DP_TRAIN_VOLTAGE_SWING_1200:
1502 default:
1503 return DP_TRAIN_PRE_EMPHASIS_0;
1504 }
1505 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1506 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1507 case DP_TRAIN_VOLTAGE_SWING_400:
1508 return DP_TRAIN_PRE_EMPHASIS_6;
1509 case DP_TRAIN_VOLTAGE_SWING_600:
1510 case DP_TRAIN_VOLTAGE_SWING_800:
1511 return DP_TRAIN_PRE_EMPHASIS_3_5;
1512 default:
1513 return DP_TRAIN_PRE_EMPHASIS_0;
1514 }
1515 } else {
1516 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1517 case DP_TRAIN_VOLTAGE_SWING_400:
1518 return DP_TRAIN_PRE_EMPHASIS_6;
1519 case DP_TRAIN_VOLTAGE_SWING_600:
1520 return DP_TRAIN_PRE_EMPHASIS_6;
1521 case DP_TRAIN_VOLTAGE_SWING_800:
1522 return DP_TRAIN_PRE_EMPHASIS_3_5;
1523 case DP_TRAIN_VOLTAGE_SWING_1200:
1524 default:
1525 return DP_TRAIN_PRE_EMPHASIS_0;
1526 }
a4fc5ed6
KP		 1527 }
1528}
1529
1530static void
93f62dad 1531intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1532{
1533 uint8_t v = 0;
1534 uint8_t p = 0;
1535 int lane;
1a2eb460
KP		 1536 uint8_t voltage_max;
1537 uint8_t preemph_max;
a4fc5ed6 1538
33a34e4e 1539 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1540 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1541 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1542
1543 if (this_v > v)
1544 v = this_v;
1545 if (this_p > p)
1546 p = this_p;
1547 }
1548
1a2eb460 1549 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1550 if (v >= voltage_max)
1551 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1552
1a2eb460
KP		 1553 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1554 if (p >= preemph_max)
1555 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1556
1557 for (lane = 0; lane < 4; lane++)
33a34e4e 1558 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1559}
1560
1561static uint32_t
f0a3424e 1562intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1563{
3cf2efb1 1564 uint32_t signal_levels = 0;
a4fc5ed6 1565
3cf2efb1 1566 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1567 case DP_TRAIN_VOLTAGE_SWING_400:
1568 default:
1569 signal_levels |= DP_VOLTAGE_0_4;
1570 break;
1571 case DP_TRAIN_VOLTAGE_SWING_600:
1572 signal_levels |= DP_VOLTAGE_0_6;
1573 break;
1574 case DP_TRAIN_VOLTAGE_SWING_800:
1575 signal_levels |= DP_VOLTAGE_0_8;
1576 break;
1577 case DP_TRAIN_VOLTAGE_SWING_1200:
1578 signal_levels |= DP_VOLTAGE_1_2;
1579 break;
1580 }
3cf2efb1 1581 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1582 case DP_TRAIN_PRE_EMPHASIS_0:
1583 default:
1584 signal_levels |= DP_PRE_EMPHASIS_0;
1585 break;
1586 case DP_TRAIN_PRE_EMPHASIS_3_5:
1587 signal_levels |= DP_PRE_EMPHASIS_3_5;
1588 break;
1589 case DP_TRAIN_PRE_EMPHASIS_6:
1590 signal_levels |= DP_PRE_EMPHASIS_6;
1591 break;
1592 case DP_TRAIN_PRE_EMPHASIS_9_5:
1593 signal_levels |= DP_PRE_EMPHASIS_9_5;
1594 break;
1595 }
1596 return signal_levels;
1597}
1598
e3421a18
ZW		 1599/* Gen6's DP voltage swing and pre-emphasis control */
1600static uint32_t
1601intel_gen6_edp_signal_levels(uint8_t train_set)
1602{
3c5a62b5
YL		 1603 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1604 DP_TRAIN_PRE_EMPHASIS_MASK);
1605 switch (signal_levels) {
e3421a18 1606 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1607 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1608 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1609 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1610 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1611 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1612 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1613 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1614 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1615 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1616 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1617 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1618 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1619 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1620 default:
3c5a62b5
YL		 1621 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1622 "0x%x\n", signal_levels);
1623 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1624 }
1625}
1626
1a2eb460
KP		 1627/* Gen7's DP voltage swing and pre-emphasis control */
1628static uint32_t
1629intel_gen7_edp_signal_levels(uint8_t train_set)
1630{
1631 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1632 DP_TRAIN_PRE_EMPHASIS_MASK);
1633 switch (signal_levels) {
1634 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1635 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1636 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1637 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1638 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1639 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1640
1641 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1642 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1643 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1644 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1645
1646 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1647 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1648 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1649 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1650
1651 default:
1652 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1653 "0x%x\n", signal_levels);
1654 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1655 }
1656}
1657
d6c0d722
PZ		 1658/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1659static uint32_t
f0a3424e 1660intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1661{
d6c0d722
PZ		 1662 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1663 DP_TRAIN_PRE_EMPHASIS_MASK);
1664 switch (signal_levels) {
1665 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1666 return DDI_BUF_EMP_400MV_0DB_HSW;
1667 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1668 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1669 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1670 return DDI_BUF_EMP_400MV_6DB_HSW;
1671 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1672 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1673
d6c0d722
PZ		 1674 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1675 return DDI_BUF_EMP_600MV_0DB_HSW;
1676 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1678 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1679 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1680
d6c0d722
PZ		 1681 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1682 return DDI_BUF_EMP_800MV_0DB_HSW;
1683 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1684 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1685 default:
1686 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1687 "0x%x\n", signal_levels);
1688 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1689 }
a4fc5ed6
KP		 1690}
1691
f0a3424e
PZ		 1692/* Properly updates "DP" with the correct signal levels. */
1693static void
1694intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1695{
1696 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1697 struct drm_device *dev = intel_dig_port->base.base.dev;
1698 uint32_t signal_levels, mask;
1699 uint8_t train_set = intel_dp->train_set[0];
1700
22b8bf17 1701 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1702 signal_levels = intel_hsw_signal_levels(train_set);
1703 mask = DDI_BUF_EMP_MASK;
1704 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1705 signal_levels = intel_gen7_edp_signal_levels(train_set);
1706 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1707 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1708 signal_levels = intel_gen6_edp_signal_levels(train_set);
1709 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1710 } else {
1711 signal_levels = intel_gen4_signal_levels(train_set);
1712 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1713 }
1714
1715 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1716
1717 *DP = (*DP & ~mask) | signal_levels;
1718}
1719
a4fc5ed6 1720static bool
ea5b213a 1721intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1722 uint32_t dp_reg_value,
58e10eb9 1723 uint8_t dp_train_pat)
a4fc5ed6 1724{
174edf1f
PZ		 1725 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1726 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1727 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1728 enum port port = intel_dig_port->port;
a4fc5ed6 1729 int ret;
d6c0d722 1730 uint32_t temp;
a4fc5ed6 1731
22b8bf17 1732 if (HAS_DDI(dev)) {
174edf1f 1733 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1734
1735 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1736 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1737 else
1738 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1739
1740 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1741 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1742 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1743
10aa17c8
PZ		 1744 if (port != PORT_A) {
1745 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1746 I915_WRITE(DP_TP_CTL(port), temp);
1747
1748 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1749 DP_TP_STATUS_IDLE_DONE), 1))
1750 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1751
1752 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1753 }
d6c0d722 1754
d6c0d722
PZ		 1755 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1756
1757 break;
1758 case DP_TRAINING_PATTERN_1:
1759 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1760 break;
1761 case DP_TRAINING_PATTERN_2:
1762 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1763 break;
1764 case DP_TRAINING_PATTERN_3:
1765 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1766 break;
1767 }
174edf1f 1768 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1769
1770 } else if (HAS_PCH_CPT(dev) &&
1771 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1772 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1773
1774 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1775 case DP_TRAINING_PATTERN_DISABLE:
1776 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1777 break;
1778 case DP_TRAINING_PATTERN_1:
1779 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1780 break;
1781 case DP_TRAINING_PATTERN_2:
1782 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1783 break;
1784 case DP_TRAINING_PATTERN_3:
1785 DRM_ERROR("DP training pattern 3 not supported\n");
1786 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1787 break;
1788 }
1789
1790 } else {
1791 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1792
1793 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1794 case DP_TRAINING_PATTERN_DISABLE:
1795 dp_reg_value |= DP_LINK_TRAIN_OFF;
1796 break;
1797 case DP_TRAINING_PATTERN_1:
1798 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1799 break;
1800 case DP_TRAINING_PATTERN_2:
1801 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1802 break;
1803 case DP_TRAINING_PATTERN_3:
1804 DRM_ERROR("DP training pattern 3 not supported\n");
1805 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1806 break;
1807 }
1808 }
1809
ea5b213a
CW		 1810 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1811 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1812
ea5b213a 1813 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1814 DP_TRAINING_PATTERN_SET,
1815 dp_train_pat);
1816
47ea7542
PZ		 1817 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1818 DP_TRAINING_PATTERN_DISABLE) {
1819 ret = intel_dp_aux_native_write(intel_dp,
1820 DP_TRAINING_LANE0_SET,
1821 intel_dp->train_set,
1822 intel_dp->lane_count);
1823 if (ret != intel_dp->lane_count)
1824 return false;
1825 }
a4fc5ed6
KP		 1826
1827 return true;
1828}
1829
33a34e4e 1830/* Enable corresponding port and start training pattern 1 */
c19b0669 1831void
33a34e4e 1832intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1833{
da63a9f2 1834 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1835 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1836 int i;
1837 uint8_t voltage;
1838 bool clock_recovery = false;
cdb0e95b 1839 int voltage_tries, loop_tries;
ea5b213a 1840 uint32_t DP = intel_dp->DP;
a4fc5ed6 1841
affa9354 1842 if (HAS_DDI(dev))
c19b0669
PZ		 1843 intel_ddi_prepare_link_retrain(encoder);
1844
3cf2efb1
CW		 1845 /* Write the link configuration data */
1846 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1847 intel_dp->link_configuration,
1848 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1849
1850 DP |= DP_PORT_EN;
1a2eb460 1851
33a34e4e 1852 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1853 voltage = 0xff;
cdb0e95b
KP		 1854 voltage_tries = 0;
1855 loop_tries = 0;
a4fc5ed6
KP		 1856 clock_recovery = false;
1857 for (;;) {
33a34e4e 1858 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1859 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1860
1861 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1862
a7c9655f 1863 /* Set training pattern 1 */
47ea7542 1864 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1865 DP_TRAINING_PATTERN_1 |
1866 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1867 break;
a4fc5ed6 1868
a7c9655f 1869 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1870 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1871 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1872 break;
93f62dad 1873 }
a4fc5ed6 1874
01916270 1875 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1876 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1877 clock_recovery = true;
1878 break;
1879 }
1880
1881 /* Check to see if we've tried the max voltage */
1882 for (i = 0; i < intel_dp->lane_count; i++)
1883 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1884 break;
0d710688 1885 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1886 ++loop_tries;
1887 if (loop_tries == 5) {
cdb0e95b
KP		 1888 DRM_DEBUG_KMS("too many full retries, give up\n");
1889 break;
1890 }
1891 memset(intel_dp->train_set, 0, 4);
1892 voltage_tries = 0;
1893 continue;
1894 }
a4fc5ed6 1895
3cf2efb1 1896 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1897 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1898 ++voltage_tries;
b06fbda3
DV		 1899 if (voltage_tries == 5) {
1900 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1901 break;
1902 }
1903 } else
1904 voltage_tries = 0;
1905 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1906
3cf2efb1 1907 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1908 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1909 }
1910
33a34e4e
JB		 1911 intel_dp->DP = DP;
1912}
1913
c19b0669 1914void
33a34e4e
JB		 1915intel_dp_complete_link_train(struct intel_dp *intel_dp)
1916{
33a34e4e 1917 bool channel_eq = false;
37f80975 1918 int tries, cr_tries;
33a34e4e
JB		 1919 uint32_t DP = intel_dp->DP;
1920
a4fc5ed6
KP		 1921 /* channel equalization */
1922 tries = 0;
37f80975 1923 cr_tries = 0;
a4fc5ed6
KP		 1924 channel_eq = false;
1925 for (;;) {
93f62dad 1926 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1927
37f80975
JB		 1928 if (cr_tries > 5) {
1929 DRM_ERROR("failed to train DP, aborting\n");
1930 intel_dp_link_down(intel_dp);
1931 break;
1932 }
1933
f0a3424e 1934 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 1935
a4fc5ed6 1936 /* channel eq pattern */
47ea7542 1937 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1938 DP_TRAINING_PATTERN_2 |
1939 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1940 break;
1941
a7c9655f 1942 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1943 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1944 break;
a4fc5ed6 1945
37f80975 1946 /* Make sure clock is still ok */
01916270 1947 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1948 intel_dp_start_link_train(intel_dp);
1949 cr_tries++;
1950 continue;
1951 }
1952
1ffdff13 1953 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1954 channel_eq = true;
1955 break;
1956 }
a4fc5ed6 1957
37f80975
JB		 1958 /* Try 5 times, then try clock recovery if that fails */
1959 if (tries > 5) {
1960 intel_dp_link_down(intel_dp);
1961 intel_dp_start_link_train(intel_dp);
1962 tries = 0;
1963 cr_tries++;
1964 continue;
1965 }
a4fc5ed6 1966
3cf2efb1 1967 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1968 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1969 ++tries;
869184a6 1970 }
3cf2efb1 1971
d6c0d722
PZ		 1972 if (channel_eq)
1973 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1974
47ea7542 1975 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1976}
1977
1978static void
ea5b213a 1979intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1980{
da63a9f2
PZ		 1981 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1982 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1983 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 1984 struct intel_crtc *intel_crtc =
1985 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 1986 uint32_t DP = intel_dp->DP;
a4fc5ed6 1987
c19b0669
PZ		 1988 /*
1989 * DDI code has a strict mode set sequence and we should try to respect
1990 * it, otherwise we might hang the machine in many different ways. So we
1991 * really should be disabling the port only on a complete crtc_disable
1992 * sequence. This function is just called under two conditions on DDI
1993 * code:
1994 * - Link train failed while doing crtc_enable, and on this case we
1995 * really should respect the mode set sequence and wait for a
1996 * crtc_disable.
1997 * - Someone turned the monitor off and intel_dp_check_link_status
1998 * called us. We don't need to disable the whole port on this case, so
1999 * when someone turns the monitor on again,
2000 * intel_ddi_prepare_link_retrain will take care of redoing the link
2001 * train.
2002 */
affa9354 2003 if (HAS_DDI(dev))
c19b0669
PZ		 2004 return;
2005
0c33d8d7 2006 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2007 return;
2008
28c97730 2009 DRM_DEBUG_KMS("\n");
32f9d658 2010
1a2eb460 2011 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2012 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2013 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2014 } else {
2015 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2016 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2017 }
fe255d00 2018 POSTING_READ(intel_dp->output_reg);
5eb08b69 2019
ab527efc
DV		 2020 /* We don't really know why we're doing this */
2021 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2022
493a7081 2023 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2024 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2025 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2026
5bddd17f
EA		 2027 /* Hardware workaround: leaving our transcoder select
2028 * set to transcoder B while it's off will prevent the
2029 * corresponding HDMI output on transcoder A.
2030 *
2031 * Combine this with another hardware workaround:
2032 * transcoder select bit can only be cleared while the
2033 * port is enabled.
2034 */
2035 DP &= ~DP_PIPEB_SELECT;
2036 I915_WRITE(intel_dp->output_reg, DP);
2037
2038 /* Changes to enable or select take place the vblank
2039 * after being written.
2040 */
ff50afe9
DV		 2041 if (WARN_ON(crtc == NULL)) {
2042 /* We should never try to disable a port without a crtc
2043 * attached. For paranoia keep the code around for a
2044 * bit. */
31acbcc4
CW		 2045 POSTING_READ(intel_dp->output_reg);
2046 msleep(50);
2047 } else
ab527efc 2048 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2049 }
2050
832afda6 2051 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2052 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2053 POSTING_READ(intel_dp->output_reg);
f01eca2e 2054 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2055}
2056
26d61aad
KP		 2057static bool
2058intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2059{
577c7a50
DL		 2060 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2061
92fd8fd1 2062 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2063 sizeof(intel_dp->dpcd)) == 0)
2064 return false; /* aux transfer failed */
92fd8fd1 2065
577c7a50
DL		 2066 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2067 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2068 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2069
edb39244
AJ		 2070 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2071 return false; /* DPCD not present */
2072
2073 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2074 DP_DWN_STRM_PORT_PRESENT))
2075 return true; /* native DP sink */
2076
2077 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2078 return true; /* no per-port downstream info */
2079
2080 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2081 intel_dp->downstream_ports,
2082 DP_MAX_DOWNSTREAM_PORTS) == 0)
2083 return false; /* downstream port status fetch failed */
2084
2085 return true;
92fd8fd1
KP		 2086}
2087
0d198328
AJ		 2088static void
2089intel_dp_probe_oui(struct intel_dp *intel_dp)
2090{
2091 u8 buf[3];
2092
2093 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2094 return;
2095
351cfc34
DV		 2096 ironlake_edp_panel_vdd_on(intel_dp);
2097
0d198328
AJ		 2098 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2099 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2100 buf[0], buf[1], buf[2]);
2101
2102 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2103 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2104 buf[0], buf[1], buf[2]);
351cfc34
DV		 2105
2106 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2107}
2108
a60f0e38
JB		 2109static bool
2110intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2111{
2112 int ret;
2113
2114 ret = intel_dp_aux_native_read_retry(intel_dp,
2115 DP_DEVICE_SERVICE_IRQ_VECTOR,
2116 sink_irq_vector, 1);
2117 if (!ret)
2118 return false;
2119
2120 return true;
2121}
2122
2123static void
2124intel_dp_handle_test_request(struct intel_dp *intel_dp)
2125{
2126 /* NAK by default */
9324cf7f 2127 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2128}
2129
a4fc5ed6
KP		 2130/*
2131 * According to DP spec
2132 * 5.1.2:
2133 * 1. Read DPCD
2134 * 2. Configure link according to Receiver Capabilities
2135 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2136 * 4. Check link status on receipt of hot-plug interrupt
2137 */
2138
00c09d70 2139void
ea5b213a 2140intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2141{
da63a9f2 2142 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2143 u8 sink_irq_vector;
93f62dad 2144 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2145
da63a9f2 2146 if (!intel_encoder->connectors_active)
d2b996ac 2147 return;
59cd09e1 2148
da63a9f2 2149 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2150 return;
2151
92fd8fd1 2152 /* Try to read receiver status if the link appears to be up */
93f62dad 2153 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2154 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2155 return;
2156 }
2157
92fd8fd1 2158 /* Now read the DPCD to see if it's actually running */
26d61aad 2159 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2160 intel_dp_link_down(intel_dp);
2161 return;
2162 }
2163
a60f0e38
JB		 2164 /* Try to read the source of the interrupt */
2165 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2166 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2167 /* Clear interrupt source */
2168 intel_dp_aux_native_write_1(intel_dp,
2169 DP_DEVICE_SERVICE_IRQ_VECTOR,
2170 sink_irq_vector);
2171
2172 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2173 intel_dp_handle_test_request(intel_dp);
2174 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2175 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2176 }
2177
1ffdff13 2178 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2179 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2180 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2181 intel_dp_start_link_train(intel_dp);
2182 intel_dp_complete_link_train(intel_dp);
2183 }
a4fc5ed6 2184}
a4fc5ed6 2185
caf9ab24 2186/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2187static enum drm_connector_status
26d61aad 2188intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2189{
caf9ab24
AJ		 2190 uint8_t *dpcd = intel_dp->dpcd;
2191 bool hpd;
2192 uint8_t type;
2193
2194 if (!intel_dp_get_dpcd(intel_dp))
2195 return connector_status_disconnected;
2196
2197 /* if there's no downstream port, we're done */
2198 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2199 return connector_status_connected;
caf9ab24
AJ		 2200
2201 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2202 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2203 if (hpd) {
23235177 2204 uint8_t reg;
caf9ab24 2205 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2206 &reg, 1))
caf9ab24 2207 return connector_status_unknown;
23235177
AJ		 2208 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2209 : connector_status_disconnected;
caf9ab24
AJ		 2210 }
2211
2212 /* If no HPD, poke DDC gently */
2213 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2214 return connector_status_connected;
caf9ab24
AJ		 2215
2216 /* Well we tried, say unknown for unreliable port types */
2217 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2218 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2219 return connector_status_unknown;
2220
2221 /* Anything else is out of spec, warn and ignore */
2222 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2223 return connector_status_disconnected;
71ba9000
AJ		 2224}
2225
5eb08b69 2226static enum drm_connector_status
a9756bb5 2227ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2228{
30add22d 2229 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2232 enum drm_connector_status status;
2233
fe16d949
CW		 2234 /* Can't disconnect eDP, but you can close the lid... */
2235 if (is_edp(intel_dp)) {
30add22d 2236 status = intel_panel_detect(dev);
fe16d949
CW		 2237 if (status == connector_status_unknown)
2238 status = connector_status_connected;
2239 return status;
2240 }
01cb9ea6 2241
1b469639
DL		 2242 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2243 return connector_status_disconnected;
2244
26d61aad 2245 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2246}
2247
a4fc5ed6 2248static enum drm_connector_status
a9756bb5 2249g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2250{
30add22d 2251 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2252 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2254 uint32_t bit;
5eb08b69 2255
35aad75f
JB		 2256 /* Can't disconnect eDP, but you can close the lid... */
2257 if (is_edp(intel_dp)) {
2258 enum drm_connector_status status;
2259
2260 status = intel_panel_detect(dev);
2261 if (status == connector_status_unknown)
2262 status = connector_status_connected;
2263 return status;
2264 }
2265
34f2be46
VS		 2266 switch (intel_dig_port->port) {
2267 case PORT_B:
26739f12 2268 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2269 break;
34f2be46 2270 case PORT_C:
26739f12 2271 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2272 break;
34f2be46 2273 case PORT_D:
26739f12 2274 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2275 break;
2276 default:
2277 return connector_status_unknown;
2278 }
2279
10f76a38 2280 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2281 return connector_status_disconnected;
2282
26d61aad 2283 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2284}
2285
8c241fef
KP		 2286static struct edid *
2287intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2288{
9cd300e0 2289 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2290
9cd300e0
JN		 2291 /* use cached edid if we have one */
2292 if (intel_connector->edid) {
2293 struct edid *edid;
2294 int size;
2295
2296 /* invalid edid */
2297 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2298 return NULL;
2299
9cd300e0 2300 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2301 edid = kmalloc(size, GFP_KERNEL);
2302 if (!edid)
2303 return NULL;
2304
9cd300e0 2305 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2306 return edid;
2307 }
8c241fef 2308
9cd300e0 2309 return drm_get_edid(connector, adapter);
8c241fef
KP		 2310}
2311
2312static int
2313intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2314{
9cd300e0 2315 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2316
9cd300e0
JN		 2317 /* use cached edid if we have one */
2318 if (intel_connector->edid) {
2319 /* invalid edid */
2320 if (IS_ERR(intel_connector->edid))
2321 return 0;
2322
2323 return intel_connector_update_modes(connector,
2324 intel_connector->edid);
d6f24d0f
JB		 2325 }
2326
9cd300e0 2327 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2328}
2329
a9756bb5
ZW		 2330static enum drm_connector_status
2331intel_dp_detect(struct drm_connector *connector, bool force)
2332{
2333 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2336 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2337 enum drm_connector_status status;
2338 struct edid *edid = NULL;
2339
2340 intel_dp->has_audio = false;
2341
2342 if (HAS_PCH_SPLIT(dev))
2343 status = ironlake_dp_detect(intel_dp);
2344 else
2345 status = g4x_dp_detect(intel_dp);
1b9be9d0 2346
a9756bb5
ZW		 2347 if (status != connector_status_connected)
2348 return status;
2349
0d198328
AJ		 2350 intel_dp_probe_oui(intel_dp);
2351
c3e5f67b
DV		 2352 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2353 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2354 } else {
8c241fef 2355 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2356 if (edid) {
2357 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2358 kfree(edid);
2359 }
a9756bb5
ZW		 2360 }
2361
d63885da
PZ		 2362 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2363 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2364 return connector_status_connected;
a4fc5ed6
KP		 2365}
2366
2367static int intel_dp_get_modes(struct drm_connector *connector)
2368{
df0e9248 2369 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2370 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2371 struct drm_device *dev = connector->dev;
32f9d658 2372 int ret;
a4fc5ed6
KP		 2373
2374 /* We should parse the EDID data and find out if it has an audio sink
2375 */
2376
8c241fef 2377 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2378 if (ret)
32f9d658
ZW		 2379 return ret;
2380
f8779fda 2381 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2382 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2383 struct drm_display_mode *mode;
dd06f90e
JN		 2384 mode = drm_mode_duplicate(dev,
2385 intel_connector->panel.fixed_mode);
f8779fda 2386 if (mode) {
32f9d658
ZW		 2387 drm_mode_probed_add(connector, mode);
2388 return 1;
2389 }
2390 }
2391 return 0;
a4fc5ed6
KP		 2392}
2393
1aad7ac0
CW		 2394static bool
2395intel_dp_detect_audio(struct drm_connector *connector)
2396{
2397 struct intel_dp *intel_dp = intel_attached_dp(connector);
2398 struct edid *edid;
2399 bool has_audio = false;
2400
8c241fef 2401 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2402 if (edid) {
2403 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2404 kfree(edid);
2405 }
2406
2407 return has_audio;
2408}
2409
f684960e
CW		 2410static int
2411intel_dp_set_property(struct drm_connector *connector,
2412 struct drm_property *property,
2413 uint64_t val)
2414{
e953fd7b 2415 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2416 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2417 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2418 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2419 int ret;
2420
662595df 2421 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2422 if (ret)
2423 return ret;
2424
3f43c48d 2425 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2426 int i = val;
2427 bool has_audio;
2428
2429 if (i == intel_dp->force_audio)
f684960e
CW		 2430 return 0;
2431
1aad7ac0 2432 intel_dp->force_audio = i;
f684960e 2433
c3e5f67b 2434 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2435 has_audio = intel_dp_detect_audio(connector);
2436 else
c3e5f67b 2437 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2438
2439 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2440 return 0;
2441
1aad7ac0 2442 intel_dp->has_audio = has_audio;
f684960e
CW		 2443 goto done;
2444 }
2445
e953fd7b 2446 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2447 switch (val) {
2448 case INTEL_BROADCAST_RGB_AUTO:
2449 intel_dp->color_range_auto = true;
2450 break;
2451 case INTEL_BROADCAST_RGB_FULL:
2452 intel_dp->color_range_auto = false;
2453 intel_dp->color_range = 0;
2454 break;
2455 case INTEL_BROADCAST_RGB_LIMITED:
2456 intel_dp->color_range_auto = false;
2457 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2458 break;
2459 default:
2460 return -EINVAL;
2461 }
e953fd7b
CW		 2462 goto done;
2463 }
2464
53b41837
YN		 2465 if (is_edp(intel_dp) &&
2466 property == connector->dev->mode_config.scaling_mode_property) {
2467 if (val == DRM_MODE_SCALE_NONE) {
2468 DRM_DEBUG_KMS("no scaling not supported\n");
2469 return -EINVAL;
2470 }
2471
2472 if (intel_connector->panel.fitting_mode == val) {
2473 /* the eDP scaling property is not changed */
2474 return 0;
2475 }
2476 intel_connector->panel.fitting_mode = val;
2477
2478 goto done;
2479 }
2480
f684960e
CW		 2481 return -EINVAL;
2482
2483done:
c0c36b94
CW		 2484 if (intel_encoder->base.crtc)
2485 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2486
2487 return 0;
2488}
2489
a4fc5ed6 2490static void
0206e353 2491intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2492{
aaa6fd2a 2493 struct drm_device *dev = connector->dev;
be3cd5e3 2494 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2495 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2496
9cd300e0
JN		 2497 if (!IS_ERR_OR_NULL(intel_connector->edid))
2498 kfree(intel_connector->edid);
2499
1d508706 2500 if (is_edp(intel_dp)) {
aaa6fd2a 2501 intel_panel_destroy_backlight(dev);
1d508706
JN		 2502 intel_panel_fini(&intel_connector->panel);
2503 }
aaa6fd2a 2504
a4fc5ed6
KP		 2505 drm_sysfs_connector_remove(connector);
2506 drm_connector_cleanup(connector);
55f78c43 2507 kfree(connector);
a4fc5ed6
KP		 2508}
2509
00c09d70 2510void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2511{
da63a9f2
PZ		 2512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2513 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2514
2515 i2c_del_adapter(&intel_dp->adapter);
2516 drm_encoder_cleanup(encoder);
bd943159
KP		 2517 if (is_edp(intel_dp)) {
2518 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2519 ironlake_panel_vdd_off_sync(intel_dp);
2520 }
da63a9f2 2521 kfree(intel_dig_port);
24d05927
DV		 2522}
2523
a4fc5ed6 2524static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2525 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2526};
2527
2528static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2529 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2530 .detect = intel_dp_detect,
2531 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2532 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2533 .destroy = intel_dp_destroy,
2534};
2535
2536static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2537 .get_modes = intel_dp_get_modes,
2538 .mode_valid = intel_dp_mode_valid,
df0e9248 2539 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2540};
2541
a4fc5ed6 2542static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2543 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2544};
2545
995b6762 2546static void
21d40d37 2547intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2548{
fa90ecef 2549 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2550
885a5014 2551 intel_dp_check_link_status(intel_dp);
c8110e52 2552}
6207937d 2553
e3421a18
ZW		 2554/* Return which DP Port should be selected for Transcoder DP control */
2555int
0206e353 2556intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2557{
2558 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2559 struct intel_encoder *intel_encoder;
2560 struct intel_dp *intel_dp;
e3421a18 2561
fa90ecef
PZ		 2562 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2563 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2564
fa90ecef
PZ		 2565 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2566 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2567 return intel_dp->output_reg;
e3421a18 2568 }
ea5b213a 2569
e3421a18
ZW		 2570 return -1;
2571}
2572
36e83a18 2573/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2574bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2575{
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 struct child_device_config *p_child;
2578 int i;
2579
2580 if (!dev_priv->child_dev_num)
2581 return false;
2582
2583 for (i = 0; i < dev_priv->child_dev_num; i++) {
2584 p_child = dev_priv->child_dev + i;
2585
2586 if (p_child->dvo_port == PORT_IDPD &&
2587 p_child->device_type == DEVICE_TYPE_eDP)
2588 return true;
2589 }
2590 return false;
2591}
2592
f684960e
CW		 2593static void
2594intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2595{
53b41837
YN		 2596 struct intel_connector *intel_connector = to_intel_connector(connector);
2597
3f43c48d 2598 intel_attach_force_audio_property(connector);
e953fd7b 2599 intel_attach_broadcast_rgb_property(connector);
55bc60db 2600 intel_dp->color_range_auto = true;
53b41837
YN		 2601
2602 if (is_edp(intel_dp)) {
2603 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2604 drm_object_attach_property(
2605 &connector->base,
53b41837 2606 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2607 DRM_MODE_SCALE_ASPECT);
2608 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2609 }
f684960e
CW		 2610}
2611
67a54566
DV		 2612static void
2613intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2614 struct intel_dp *intel_dp,
2615 struct edp_power_seq *out)
67a54566
DV		 2616{
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618 struct edp_power_seq cur, vbt, spec, final;
2619 u32 pp_on, pp_off, pp_div, pp;
2620
2621 /* Workaround: Need to write PP_CONTROL with the unlock key as
2622 * the very first thing. */
2623 pp = ironlake_get_pp_control(dev_priv);
2624 I915_WRITE(PCH_PP_CONTROL, pp);
2625
2626 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2627 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2628 pp_div = I915_READ(PCH_PP_DIVISOR);
2629
2630 /* Pull timing values out of registers */
2631 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2632 PANEL_POWER_UP_DELAY_SHIFT;
2633
2634 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2635 PANEL_LIGHT_ON_DELAY_SHIFT;
2636
2637 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2638 PANEL_LIGHT_OFF_DELAY_SHIFT;
2639
2640 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2641 PANEL_POWER_DOWN_DELAY_SHIFT;
2642
2643 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2644 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2645
2646 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2647 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2648
2649 vbt = dev_priv->edp.pps;
2650
2651 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2652 * our hw here, which are all in 100usec. */
2653 spec.t1_t3 = 210 * 10;
2654 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2655 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2656 spec.t10 = 500 * 10;
2657 /* This one is special and actually in units of 100ms, but zero
2658 * based in the hw (so we need to add 100 ms). But the sw vbt
2659 * table multiplies it with 1000 to make it in units of 100usec,
2660 * too. */
2661 spec.t11_t12 = (510 + 100) * 10;
2662
2663 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2664 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2665
2666 /* Use the max of the register settings and vbt. If both are
2667 * unset, fall back to the spec limits. */
2668#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2669 spec.field : \
2670 max(cur.field, vbt.field))
2671 assign_final(t1_t3);
2672 assign_final(t8);
2673 assign_final(t9);
2674 assign_final(t10);
2675 assign_final(t11_t12);
2676#undef assign_final
2677
2678#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2679 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2680 intel_dp->backlight_on_delay = get_delay(t8);
2681 intel_dp->backlight_off_delay = get_delay(t9);
2682 intel_dp->panel_power_down_delay = get_delay(t10);
2683 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2684#undef get_delay
2685
f30d26e4
JN		 2686 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2687 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2688 intel_dp->panel_power_cycle_delay);
2689
2690 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2691 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2692
2693 if (out)
2694 *out = final;
2695}
2696
2697static void
2698intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2699 struct intel_dp *intel_dp,
2700 struct edp_power_seq *seq)
2701{
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 u32 pp_on, pp_off, pp_div;
2704
67a54566 2705 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2706 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2707 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2708 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2709 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2710 /* Compute the divisor for the pp clock, simply match the Bspec
2711 * formula. */
2712 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2713 << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2714 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2715 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2716
2717 /* Haswell doesn't have any port selection bits for the panel
2718 * power sequencer any more. */
2719 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2720 if (is_cpu_edp(intel_dp))
2721 pp_on |= PANEL_POWER_PORT_DP_A;
2722 else
2723 pp_on |= PANEL_POWER_PORT_DP_D;
2724 }
2725
2726 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2727 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2728 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2729
67a54566
DV		 2730 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2731 I915_READ(PCH_PP_ON_DELAYS),
2732 I915_READ(PCH_PP_OFF_DELAYS),
2733 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2734}
2735
a4fc5ed6 2736void
f0fec3f2
PZ		 2737intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2738 struct intel_connector *intel_connector)
a4fc5ed6 2739{
f0fec3f2
PZ		 2740 struct drm_connector *connector = &intel_connector->base;
2741 struct intel_dp *intel_dp = &intel_dig_port->dp;
2742 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2743 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2744 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2745 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2746 struct edp_power_seq power_seq = { 0 };
174edf1f 2747 enum port port = intel_dig_port->port;
5eb08b69 2748 const char *name = NULL;
b329530c 2749 int type;
a4fc5ed6 2750
0767935e
DV		 2751 /* Preserve the current hw state. */
2752 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2753 intel_dp->attached_connector = intel_connector;
3d3dc149 2754
f0fec3f2 2755 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2756 if (intel_dpd_is_edp(dev))
ea5b213a 2757 intel_dp->is_pch_edp = true;
b329530c 2758
19c03924
GB		 2759 /*
2760 * FIXME : We need to initialize built-in panels before external panels.
2761 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2762 */
f0fec3f2 2763 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2764 type = DRM_MODE_CONNECTOR_eDP;
2765 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2766 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2767 type = DRM_MODE_CONNECTOR_eDP;
2768 intel_encoder->type = INTEL_OUTPUT_EDP;
2769 } else {
00c09d70
PZ		 2770 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2771 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2772 * rewrite it.
2773 */
b329530c 2774 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2775 }
2776
b329530c 2777 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2778 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2779
eb1f8e4f 2780 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2781 connector->interlace_allowed = true;
2782 connector->doublescan_allowed = 0;
2783
f0fec3f2
PZ		 2784 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2785 ironlake_panel_vdd_work);
a4fc5ed6 2786
df0e9248 2787 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2788 drm_sysfs_connector_add(connector);
2789
affa9354 2790 if (HAS_DDI(dev))
bcbc889b
PZ		 2791 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2792 else
2793 intel_connector->get_hw_state = intel_connector_get_hw_state;
2794
9ed35ab1
PZ		 2795 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2796 if (HAS_DDI(dev)) {
2797 switch (intel_dig_port->port) {
2798 case PORT_A:
2799 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2800 break;
2801 case PORT_B:
2802 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2803 break;
2804 case PORT_C:
2805 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2806 break;
2807 case PORT_D:
2808 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2809 break;
2810 default:
2811 BUG();
2812 }
2813 }
e8cb4558 2814
a4fc5ed6 2815 /* Set up the DDC bus. */
ab9d7c30
PZ		 2816 switch (port) {
2817 case PORT_A:
1d843f9d 2818 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 2819 name = "DPDDC-A";
2820 break;
2821 case PORT_B:
1d843f9d 2822 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 2823 name = "DPDDC-B";
2824 break;
2825 case PORT_C:
1d843f9d 2826 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 2827 name = "DPDDC-C";
2828 break;
2829 case PORT_D:
1d843f9d 2830 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 2831 name = "DPDDC-D";
2832 break;
2833 default:
ad1c0b19 2834 BUG();
5eb08b69
ZW		 2835 }
2836
67a54566 2837 if (is_edp(intel_dp))
f30d26e4 2838 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 2839
2840 intel_dp_i2c_init(intel_dp, intel_connector, name);
2841
67a54566 2842 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2843 if (is_edp(intel_dp)) {
2844 bool ret;
f8779fda 2845 struct drm_display_mode *scan;
c1f05264 2846 struct edid *edid;
5d613501
JB		 2847
2848 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2849 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2850 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2851
59f3e272 2852 if (ret) {
7183dc29
JB		 2853 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2854 dev_priv->no_aux_handshake =
2855 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2856 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2857 } else {
3d3dc149 2858 /* if this fails, presume the device is a ghost */
48898b03 2859 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2860 intel_dp_encoder_destroy(&intel_encoder->base);
2861 intel_dp_destroy(connector);
3d3dc149 2862 return;
89667383 2863 }
89667383 2864
f30d26e4
JN		 2865 /* We now know it's not a ghost, init power sequence regs. */
2866 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2867 &power_seq);
2868
d6f24d0f
JB		 2869 ironlake_edp_panel_vdd_on(intel_dp);
2870 edid = drm_get_edid(connector, &intel_dp->adapter);
2871 if (edid) {
9cd300e0
JN		 2872 if (drm_add_edid_modes(connector, edid)) {
2873 drm_mode_connector_update_edid_property(connector, edid);
2874 drm_edid_to_eld(connector, edid);
2875 } else {
2876 kfree(edid);
2877 edid = ERR_PTR(-EINVAL);
2878 }
2879 } else {
2880 edid = ERR_PTR(-ENOENT);
d6f24d0f 2881 }
9cd300e0 2882 intel_connector->edid = edid;
f8779fda
JN		 2883
2884 /* prefer fixed mode from EDID if available */
2885 list_for_each_entry(scan, &connector->probed_modes, head) {
2886 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2887 fixed_mode = drm_mode_duplicate(dev, scan);
2888 break;
2889 }
d6f24d0f 2890 }
f8779fda
JN		 2891
2892 /* fallback to VBT if available for eDP */
2893 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2894 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2895 if (fixed_mode)
2896 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2897 }
f8779fda 2898
d6f24d0f
JB		 2899 ironlake_edp_panel_vdd_off(intel_dp, false);
2900 }
552fb0b7 2901
4d926461 2902 if (is_edp(intel_dp)) {
dd06f90e 2903 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2904 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2905 }
2906
f684960e
CW		 2907 intel_dp_add_properties(intel_dp, connector);
2908
a4fc5ed6
KP		 2909 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2910 * 0xd. Failure to do so will result in spurious interrupts being
2911 * generated on the port when a cable is not attached.
2912 */
2913 if (IS_G4X(dev) && !IS_GM45(dev)) {
2914 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2915 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2916 }
2917}
f0fec3f2
PZ		 2918
2919void
2920intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2921{
2922 struct intel_digital_port *intel_dig_port;
2923 struct intel_encoder *intel_encoder;
2924 struct drm_encoder *encoder;
2925 struct intel_connector *intel_connector;
2926
2927 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2928 if (!intel_dig_port)
2929 return;
2930
2931 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2932 if (!intel_connector) {
2933 kfree(intel_dig_port);
2934 return;
2935 }
2936
2937 intel_encoder = &intel_dig_port->base;
2938 encoder = &intel_encoder->base;
2939
2940 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2941 DRM_MODE_ENCODER_TMDS);
00c09d70 2942 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2943
5bfe2ac0 2944 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 2945 intel_encoder->enable = intel_enable_dp;
2946 intel_encoder->pre_enable = intel_pre_enable_dp;
2947 intel_encoder->disable = intel_disable_dp;
2948 intel_encoder->post_disable = intel_post_disable_dp;
2949 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2950
174edf1f 2951 intel_dig_port->port = port;
f0fec3f2
PZ		 2952 intel_dig_port->dp.output_reg = output_reg;
2953
00c09d70 2954 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2955 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2956 intel_encoder->cloneable = false;
2957 intel_encoder->hot_plug = intel_dp_hot_plug;
2958
2959 intel_dp_init_connector(intel_dig_port, intel_connector);
2960}
Linux kernel - Deliverables
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