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drm/i915: Fix HSW power well control state read
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
50 return intel_dp->base.type == INTEL_OUTPUT_EDP;
51}
52
53/**
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
56 *
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
60 */
61static bool is_pch_edp(struct intel_dp *intel_dp)
62{
63 return intel_dp->is_pch_edp;
64}
65
1c95822a
AJ		 66/**
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
69 *
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
71 */
72static bool is_cpu_edp(struct intel_dp *intel_dp)
73{
74 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
75}
76
df0e9248
CW		 77static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
78{
79 return container_of(intel_attached_encoder(connector),
80 struct intel_dp, base);
81}
82
814948ad
JB		 83/**
84 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
85 * @encoder: DRM encoder
86 *
87 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
88 * by intel_display.c.
89 */
90bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
91{
92 struct intel_dp *intel_dp;
93
94 if (!encoder)
95 return false;
96
97 intel_dp = enc_to_intel_dp(encoder);
98
99 return is_pch_edp(intel_dp);
100}
101
ea5b213a 102static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 103
32f9d658 104void
0206e353 105intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 106 int *lane_num, int *link_bw)
32f9d658 107{
ea5b213a 108 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 109
ea5b213a 110 *lane_num = intel_dp->lane_count;
3b5c662e 111 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 112}
113
94bf2ced
DV		 114int
115intel_edp_target_clock(struct intel_encoder *intel_encoder,
116 struct drm_display_mode *mode)
117{
118 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
dd06f90e 119 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 120
dd06f90e
JN		 121 if (intel_connector->panel.fixed_mode)
122 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 123 else
124 return mode->clock;
125}
126
a4fc5ed6 127static int
ea5b213a 128intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 129{
7183dc29 130 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 131
132 switch (max_link_bw) {
133 case DP_LINK_BW_1_62:
134 case DP_LINK_BW_2_7:
135 break;
136 default:
137 max_link_bw = DP_LINK_BW_1_62;
138 break;
139 }
140 return max_link_bw;
141}
142
143static int
144intel_dp_link_clock(uint8_t link_bw)
145{
146 if (link_bw == DP_LINK_BW_2_7)
147 return 270000;
148 else
149 return 162000;
150}
151
cd9dde44
AJ		 152/*
153 * The units on the numbers in the next two are... bizarre. Examples will
154 * make it clearer; this one parallels an example in the eDP spec.
155 *
156 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
157 *
158 * 270000 * 1 * 8 / 10 == 216000
159 *
160 * The actual data capacity of that configuration is 2.16Gbit/s, so the
161 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
162 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
163 * 119000. At 18bpp that's 2142000 kilobits per second.
164 *
165 * Thus the strange-looking division by 10 in intel_dp_link_required, to
166 * get the result in decakilobits instead of kilobits.
167 */
168
a4fc5ed6 169static int
c898261c 170intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 171{
cd9dde44 172 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 173}
174
fe27d53e
DA		 175static int
176intel_dp_max_data_rate(int max_link_clock, int max_lanes)
177{
178 return (max_link_clock * max_lanes * 8) / 10;
179}
180
c4867936
DV		 181static bool
182intel_dp_adjust_dithering(struct intel_dp *intel_dp,
183 struct drm_display_mode *mode,
cb1793ce 184 bool adjust_mode)
c4867936
DV		 185{
186 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
295 struct drm_device *dev = intel_dp->base.base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
303 struct drm_device *dev = intel_dp->base.base.dev;
304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
312 struct drm_device *dev = intel_dp->base.base.dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
a4fc5ed6 325static int
ea5b213a 326intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 327 uint8_t *send, int send_bytes,
328 uint8_t *recv, int recv_size)
329{
ea5b213a 330 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 331 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 332 struct drm_i915_private *dev_priv = dev->dev_private;
333 uint32_t ch_ctl = output_reg + 0x10;
334 uint32_t ch_data = ch_ctl + 4;
335 int i;
336 int recv_bytes;
a4fc5ed6 337 uint32_t status;
fb0f8fbf 338 uint32_t aux_clock_divider;
6b4e0a93 339 int try, precharge;
a4fc5ed6 340
750eb99e
PZ		 341 if (IS_HASWELL(dev)) {
342 switch (intel_dp->port) {
343 case PORT_A:
344 ch_ctl = DPA_AUX_CH_CTL;
345 ch_data = DPA_AUX_CH_DATA1;
346 break;
347 case PORT_B:
348 ch_ctl = PCH_DPB_AUX_CH_CTL;
349 ch_data = PCH_DPB_AUX_CH_DATA1;
350 break;
351 case PORT_C:
352 ch_ctl = PCH_DPC_AUX_CH_CTL;
353 ch_data = PCH_DPC_AUX_CH_DATA1;
354 break;
355 case PORT_D:
356 ch_ctl = PCH_DPD_AUX_CH_CTL;
357 ch_data = PCH_DPD_AUX_CH_DATA1;
358 break;
359 default:
360 BUG();
361 }
362 }
363
9b984dae 364 intel_dp_check_edp(intel_dp);
a4fc5ed6 365 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 368 *
369 * Note that PCH attached eDP panels should use a 125MHz input
370 * clock divider.
a4fc5ed6 371 */
1c95822a 372 if (is_cpu_edp(intel_dp)) {
b8fc2f6a
PZ		 373 if (IS_HASWELL(dev))
374 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
375 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 376 aux_clock_divider = 100;
377 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 378 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 379 else
380 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
381 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 382 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 383 else
384 aux_clock_divider = intel_hrawclk(dev) / 2;
385
6b4e0a93
DV		 386 if (IS_GEN6(dev))
387 precharge = 3;
388 else
389 precharge = 5;
390
11bee43e
JB		 391 /* Try to wait for any previous AUX channel activity */
392 for (try = 0; try < 3; try++) {
393 status = I915_READ(ch_ctl);
394 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
395 break;
396 msleep(1);
397 }
398
399 if (try == 3) {
400 WARN(1, "dp_aux_ch not started status 0x%08x\n",
401 I915_READ(ch_ctl));
4f7f7b7e
CW		 402 return -EBUSY;
403 }
404
fb0f8fbf
KP		 405 /* Must try at least 3 times according to DP spec */
406 for (try = 0; try < 5; try++) {
407 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 408 for (i = 0; i < send_bytes; i += 4)
409 I915_WRITE(ch_data + i,
410 pack_aux(send + i, send_bytes - i));
0206e353 411
fb0f8fbf 412 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 413 I915_WRITE(ch_ctl,
414 DP_AUX_CH_CTL_SEND_BUSY |
415 DP_AUX_CH_CTL_TIME_OUT_400us |
416 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
417 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
418 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
419 DP_AUX_CH_CTL_DONE |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR |
421 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 422 for (;;) {
fb0f8fbf
KP		 423 status = I915_READ(ch_ctl);
424 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
425 break;
4f7f7b7e 426 udelay(100);
fb0f8fbf 427 }
0206e353 428
fb0f8fbf 429 /* Clear done status and any errors */
4f7f7b7e
CW		 430 I915_WRITE(ch_ctl,
431 status |
432 DP_AUX_CH_CTL_DONE |
433 DP_AUX_CH_CTL_TIME_OUT_ERROR |
434 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 435
436 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR))
438 continue;
4f7f7b7e 439 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 440 break;
441 }
442
a4fc5ed6 443 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 444 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 445 return -EBUSY;
a4fc5ed6
KP		 446 }
447
448 /* Check for timeout or receive error.
449 * Timeouts occur when the sink is not connected
450 */
a5b3da54 451 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 452 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 453 return -EIO;
454 }
1ae8c0a5
KP		 455
456 /* Timeouts occur when the device isn't connected, so they're
457 * "normal" -- don't fill the kernel log with these */
a5b3da54 458 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 459 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 460 return -ETIMEDOUT;
a4fc5ed6
KP		 461 }
462
463 /* Unload any bytes sent back from the other side */
464 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
465 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 466 if (recv_bytes > recv_size)
467 recv_bytes = recv_size;
0206e353 468
4f7f7b7e
CW		 469 for (i = 0; i < recv_bytes; i += 4)
470 unpack_aux(I915_READ(ch_data + i),
471 recv + i, recv_bytes - i);
a4fc5ed6
KP		 472
473 return recv_bytes;
474}
475
476/* Write data to the aux channel in native mode */
477static int
ea5b213a 478intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 479 uint16_t address, uint8_t *send, int send_bytes)
480{
481 int ret;
482 uint8_t msg[20];
483 int msg_bytes;
484 uint8_t ack;
485
9b984dae 486 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 487 if (send_bytes > 16)
488 return -1;
489 msg[0] = AUX_NATIVE_WRITE << 4;
490 msg[1] = address >> 8;
eebc863e 491 msg[2] = address & 0xff;
a4fc5ed6
KP		 492 msg[3] = send_bytes - 1;
493 memcpy(&msg[4], send, send_bytes);
494 msg_bytes = send_bytes + 4;
495 for (;;) {
ea5b213a 496 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 497 if (ret < 0)
498 return ret;
499 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
500 break;
501 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
502 udelay(100);
503 else
a5b3da54 504 return -EIO;
a4fc5ed6
KP		 505 }
506 return send_bytes;
507}
508
509/* Write a single byte to the aux channel in native mode */
510static int
ea5b213a 511intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 512 uint16_t address, uint8_t byte)
513{
ea5b213a 514 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 515}
516
517/* read bytes from a native aux channel */
518static int
ea5b213a 519intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 520 uint16_t address, uint8_t *recv, int recv_bytes)
521{
522 uint8_t msg[4];
523 int msg_bytes;
524 uint8_t reply[20];
525 int reply_bytes;
526 uint8_t ack;
527 int ret;
528
9b984dae 529 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 530 msg[0] = AUX_NATIVE_READ << 4;
531 msg[1] = address >> 8;
532 msg[2] = address & 0xff;
533 msg[3] = recv_bytes - 1;
534
535 msg_bytes = 4;
536 reply_bytes = recv_bytes + 1;
537
538 for (;;) {
ea5b213a 539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 540 reply, reply_bytes);
a5b3da54
KP		 541 if (ret == 0)
542 return -EPROTO;
543 if (ret < 0)
a4fc5ed6
KP		 544 return ret;
545 ack = reply[0];
546 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
547 memcpy(recv, reply + 1, ret - 1);
548 return ret - 1;
549 }
550 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
551 udelay(100);
552 else
a5b3da54 553 return -EIO;
a4fc5ed6
KP		 554 }
555}
556
557static int
ab2c0672
DA		 558intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
559 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 560{
ab2c0672 561 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 562 struct intel_dp *intel_dp = container_of(adapter,
563 struct intel_dp,
564 adapter);
ab2c0672
DA		 565 uint16_t address = algo_data->address;
566 uint8_t msg[5];
567 uint8_t reply[2];
8316f337 568 unsigned retry;
ab2c0672
DA		 569 int msg_bytes;
570 int reply_bytes;
571 int ret;
572
9b984dae 573 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 574 /* Set up the command byte */
575 if (mode & MODE_I2C_READ)
576 msg[0] = AUX_I2C_READ << 4;
577 else
578 msg[0] = AUX_I2C_WRITE << 4;
579
580 if (!(mode & MODE_I2C_STOP))
581 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 582
ab2c0672
DA		 583 msg[1] = address >> 8;
584 msg[2] = address;
585
586 switch (mode) {
587 case MODE_I2C_WRITE:
588 msg[3] = 0;
589 msg[4] = write_byte;
590 msg_bytes = 5;
591 reply_bytes = 1;
592 break;
593 case MODE_I2C_READ:
594 msg[3] = 0;
595 msg_bytes = 4;
596 reply_bytes = 2;
597 break;
598 default:
599 msg_bytes = 3;
600 reply_bytes = 1;
601 break;
602 }
603
8316f337
DF		 604 for (retry = 0; retry < 5; retry++) {
605 ret = intel_dp_aux_ch(intel_dp,
606 msg, msg_bytes,
607 reply, reply_bytes);
ab2c0672 608 if (ret < 0) {
3ff99164 609 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 610 return ret;
611 }
8316f337
DF		 612
613 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
614 case AUX_NATIVE_REPLY_ACK:
615 /* I2C-over-AUX Reply field is only valid
616 * when paired with AUX ACK.
617 */
618 break;
619 case AUX_NATIVE_REPLY_NACK:
620 DRM_DEBUG_KMS("aux_ch native nack\n");
621 return -EREMOTEIO;
622 case AUX_NATIVE_REPLY_DEFER:
623 udelay(100);
624 continue;
625 default:
626 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
627 reply[0]);
628 return -EREMOTEIO;
629 }
630
ab2c0672
DA		 631 switch (reply[0] & AUX_I2C_REPLY_MASK) {
632 case AUX_I2C_REPLY_ACK:
633 if (mode == MODE_I2C_READ) {
634 *read_byte = reply[1];
635 }
636 return reply_bytes - 1;
637 case AUX_I2C_REPLY_NACK:
8316f337 638 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 639 return -EREMOTEIO;
640 case AUX_I2C_REPLY_DEFER:
8316f337 641 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 642 udelay(100);
643 break;
644 default:
8316f337 645 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 646 return -EREMOTEIO;
647 }
648 }
8316f337
DF		 649
650 DRM_ERROR("too many retries, giving up\n");
651 return -EREMOTEIO;
a4fc5ed6
KP		 652}
653
654static int
ea5b213a 655intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 656 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 657{
0b5c541b
KP		 658 int ret;
659
d54e9d28 660 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 661 intel_dp->algo.running = false;
662 intel_dp->algo.address = 0;
663 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
664
0206e353 665 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 666 intel_dp->adapter.owner = THIS_MODULE;
667 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 668 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 669 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
670 intel_dp->adapter.algo_data = &intel_dp->algo;
671 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
672
0b5c541b
KP		 673 ironlake_edp_panel_vdd_on(intel_dp);
674 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 675 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 676 return ret;
a4fc5ed6
KP		 677}
678
679static bool
e811f5ae
LP		 680intel_dp_mode_fixup(struct drm_encoder *encoder,
681 const struct drm_display_mode *mode,
a4fc5ed6
KP		 682 struct drm_display_mode *adjusted_mode)
683{
0d3a1bee 684 struct drm_device *dev = encoder->dev;
ea5b213a 685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 686 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 687 int lane_count, clock;
397fe157 688 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 689 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 690 int bpp, mode_rate;
a4fc5ed6
KP		 691 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
692
dd06f90e
JN		 693 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
694 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
695 adjusted_mode);
53b41837
YN		 696 intel_pch_panel_fitting(dev,
697 intel_connector->panel.fitting_mode,
1d8e1c75 698 mode, adjusted_mode);
0d3a1bee
ZY		 699 }
700
cb1793ce 701 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 702 return false;
703
083f9560
DV		 704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
705 "max bw %02x pixel clock %iKHz\n",
71244653 706 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 707
cb1793ce 708 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 709 return false;
710
711 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 713
2514bc51
JB		 714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 716 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 717
083f9560 718 if (mode_rate <= link_avail) {
ea5b213a
CW		 719 intel_dp->link_bw = bws[clock];
720 intel_dp->lane_count = lane_count;
721 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 722 DRM_DEBUG_KMS("DP link bw %02x lane "
723 "count %d clock %d bpp %d\n",
ea5b213a 724 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 725 adjusted_mode->clock, bpp);
726 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
727 mode_rate, link_avail);
a4fc5ed6
KP		 728 return true;
729 }
730 }
731 }
fe27d53e 732
a4fc5ed6
KP		 733 return false;
734}
735
736struct intel_dp_m_n {
737 uint32_t tu;
738 uint32_t gmch_m;
739 uint32_t gmch_n;
740 uint32_t link_m;
741 uint32_t link_n;
742};
743
744static void
745intel_reduce_ratio(uint32_t *num, uint32_t *den)
746{
747 while (*num > 0xffffff || *den > 0xffffff) {
748 *num >>= 1;
749 *den >>= 1;
750 }
751}
752
753static void
36e83a18 754intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 755 int nlanes,
756 int pixel_clock,
757 int link_clock,
758 struct intel_dp_m_n *m_n)
759{
760 m_n->tu = 64;
36e83a18 761 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 762 m_n->gmch_n = link_clock * nlanes;
763 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
764 m_n->link_m = pixel_clock;
765 m_n->link_n = link_clock;
766 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
767}
768
769void
770intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
771 struct drm_display_mode *adjusted_mode)
772{
773 struct drm_device *dev = crtc->dev;
6c2b7c12 774 struct intel_encoder *encoder;
a4fc5ed6
KP		 775 struct drm_i915_private *dev_priv = dev->dev_private;
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 777 int lane_count = 4;
a4fc5ed6 778 struct intel_dp_m_n m_n;
9db4a9c7 779 int pipe = intel_crtc->pipe;
afe2fcf5 780 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 781
782 /*
21d40d37 783 * Find the lane count in the intel_encoder private
a4fc5ed6 784 */
6c2b7c12
DV		 785 for_each_encoder_on_crtc(dev, crtc, encoder) {
786 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 787
9a10f401
KP		 788 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
789 intel_dp->base.type == INTEL_OUTPUT_EDP)
790 {
ea5b213a 791 lane_count = intel_dp->lane_count;
51190667 792 break;
a4fc5ed6
KP		 793 }
794 }
795
796 /*
797 * Compute the GMCH and Link ratios. The '3' here is
798 * the number of bytes_per_pixel post-LUT, which we always
799 * set up for 8-bits of R/G/B, or 3 bytes total.
800 */
858fa035 801 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 802 mode->clock, adjusted_mode->clock, &m_n);
803
1eb8dfec 804 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 805 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
806 TU_SIZE(m_n.tu) | m_n.gmch_m);
807 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
808 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
809 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 810 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 811 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 812 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
813 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
814 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 815 } else if (IS_VALLEYVIEW(dev)) {
816 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
817 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
818 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
819 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 820 } else {
9db4a9c7 821 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 822 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 823 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
824 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
825 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 826 }
827}
828
247d89f6
PZ		 829void intel_dp_init_link_config(struct intel_dp *intel_dp)
830{
831 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
832 intel_dp->link_configuration[0] = intel_dp->link_bw;
833 intel_dp->link_configuration[1] = intel_dp->lane_count;
834 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
835 /*
836 * Check for DPCD version > 1.1 and enhanced framing support
837 */
838 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
839 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
840 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
841 }
842}
843
a4fc5ed6
KP		 844static void
845intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
846 struct drm_display_mode *adjusted_mode)
847{
e3421a18 848 struct drm_device *dev = encoder->dev;
417e822d 849 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 850 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 851 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
853
417e822d 854 /*
1a2eb460 855 * There are four kinds of DP registers:
417e822d
KP		 856 *
857 * IBX PCH
1a2eb460
KP		 858 * SNB CPU
859 * IVB CPU
417e822d
KP		 860 * CPT PCH
861 *
862 * IBX PCH and CPU are the same for almost everything,
863 * except that the CPU DP PLL is configured in this
864 * register
865 *
866 * CPT PCH is quite different, having many bits moved
867 * to the TRANS_DP_CTL register instead. That
868 * configuration happens (oddly) in ironlake_pch_enable
869 */
9c9e7927 870
417e822d
KP		 871 /* Preserve the BIOS-computed detected bit. This is
872 * supposed to be read-only.
873 */
874 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 875
417e822d 876 /* Handle DP bits in common between all three register formats */
417e822d 877 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 878
ea5b213a 879 switch (intel_dp->lane_count) {
a4fc5ed6 880 case 1:
ea5b213a 881 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 882 break;
883 case 2:
ea5b213a 884 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 885 break;
886 case 4:
ea5b213a 887 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 888 break;
889 }
e0dac65e
WF		 890 if (intel_dp->has_audio) {
891 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
892 pipe_name(intel_crtc->pipe));
ea5b213a 893 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 894 intel_write_eld(encoder, adjusted_mode);
895 }
247d89f6
PZ		 896
897 intel_dp_init_link_config(intel_dp);
a4fc5ed6 898
417e822d 899 /* Split out the IBX/CPU vs CPT settings */
32f9d658 900
19c03924 901 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 902 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
903 intel_dp->DP |= DP_SYNC_HS_HIGH;
904 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
905 intel_dp->DP |= DP_SYNC_VS_HIGH;
906 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
907
908 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
909 intel_dp->DP |= DP_ENHANCED_FRAMING;
910
911 intel_dp->DP |= intel_crtc->pipe << 29;
912
913 /* don't miss out required setting for eDP */
1a2eb460
KP		 914 if (adjusted_mode->clock < 200000)
915 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
916 else
917 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
918 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 919 intel_dp->DP |= intel_dp->color_range;
920
921 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
922 intel_dp->DP |= DP_SYNC_HS_HIGH;
923 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
924 intel_dp->DP |= DP_SYNC_VS_HIGH;
925 intel_dp->DP |= DP_LINK_TRAIN_OFF;
926
927 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
928 intel_dp->DP |= DP_ENHANCED_FRAMING;
929
930 if (intel_crtc->pipe == 1)
931 intel_dp->DP |= DP_PIPEB_SELECT;
932
933 if (is_cpu_edp(intel_dp)) {
934 /* don't miss out required setting for eDP */
417e822d
KP		 935 if (adjusted_mode->clock < 200000)
936 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
937 else
938 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
939 }
940 } else {
941 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 942 }
a4fc5ed6
KP		 943}
944
99ea7127
KP		 945#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
946#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
947
948#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
949#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
950
951#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
952#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
953
954static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
955 u32 mask,
956 u32 value)
bd943159 957{
99ea7127
KP		 958 struct drm_device *dev = intel_dp->base.base.dev;
959 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 960
99ea7127
KP		 961 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
962 mask, value,
963 I915_READ(PCH_PP_STATUS),
964 I915_READ(PCH_PP_CONTROL));
32ce697c 965
99ea7127
KP		 966 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
967 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
968 I915_READ(PCH_PP_STATUS),
969 I915_READ(PCH_PP_CONTROL));
32ce697c 970 }
99ea7127 971}
32ce697c 972
99ea7127
KP		 973static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
974{
975 DRM_DEBUG_KMS("Wait for panel power on\n");
976 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 977}
978
99ea7127
KP		 979static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
980{
981 DRM_DEBUG_KMS("Wait for panel power off time\n");
982 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
983}
984
985static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
986{
987 DRM_DEBUG_KMS("Wait for panel power cycle\n");
988 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
989}
990
991
832dd3c1
KP		 992/* Read the current pp_control value, unlocking the register if it
993 * is locked
994 */
995
996static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
997{
998 u32 control = I915_READ(PCH_PP_CONTROL);
999
1000 control &= ~PANEL_UNLOCK_MASK;
1001 control |= PANEL_UNLOCK_REGS;
1002 return control;
bd943159
KP		 1003}
1004
82a4d9c0 1005void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501
JB		 1006{
1007 struct drm_device *dev = intel_dp->base.base.dev;
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009 u32 pp;
1010
97af61f5
KP		 1011 if (!is_edp(intel_dp))
1012 return;
f01eca2e 1013 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1014
bd943159
KP		 1015 WARN(intel_dp->want_panel_vdd,
1016 "eDP VDD already requested on\n");
1017
1018 intel_dp->want_panel_vdd = true;
99ea7127 1019
bd943159
KP		 1020 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1021 DRM_DEBUG_KMS("eDP VDD already on\n");
1022 return;
1023 }
1024
99ea7127
KP		 1025 if (!ironlake_edp_have_panel_power(intel_dp))
1026 ironlake_wait_panel_power_cycle(intel_dp);
1027
832dd3c1 1028 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1029 pp |= EDP_FORCE_VDD;
1030 I915_WRITE(PCH_PP_CONTROL, pp);
1031 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1032 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1033 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1034
1035 /*
1036 * If the panel wasn't on, delay before accessing aux channel
1037 */
1038 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1039 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1040 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1041 }
5d613501
JB		 1042}
1043
bd943159 1044static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1045{
1046 struct drm_device *dev = intel_dp->base.base.dev;
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 pp;
1049
bd943159 1050 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1051 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1052 pp &= ~EDP_FORCE_VDD;
1053 I915_WRITE(PCH_PP_CONTROL, pp);
1054 POSTING_READ(PCH_PP_CONTROL);
1055
1056 /* Make sure sequencer is idle before allowing subsequent activity */
1057 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1058 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1059
1060 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1061 }
1062}
5d613501 1063
bd943159
KP		 1064static void ironlake_panel_vdd_work(struct work_struct *__work)
1065{
1066 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1067 struct intel_dp, panel_vdd_work);
1068 struct drm_device *dev = intel_dp->base.base.dev;
1069
627f7675 1070 mutex_lock(&dev->mode_config.mutex);
bd943159 1071 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1072 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1073}
1074
82a4d9c0 1075void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1076{
97af61f5
KP		 1077 if (!is_edp(intel_dp))
1078 return;
5d613501 1079
bd943159
KP		 1080 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1081 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1082
bd943159
KP		 1083 intel_dp->want_panel_vdd = false;
1084
1085 if (sync) {
1086 ironlake_panel_vdd_off_sync(intel_dp);
1087 } else {
1088 /*
1089 * Queue the timer to fire a long
1090 * time from now (relative to the power down delay)
1091 * to keep the panel power up across a sequence of operations
1092 */
1093 schedule_delayed_work(&intel_dp->panel_vdd_work,
1094 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1095 }
5d613501
JB		 1096}
1097
82a4d9c0 1098void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1099{
01cb9ea6 1100 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1101 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1102 u32 pp;
9934c132 1103
97af61f5 1104 if (!is_edp(intel_dp))
bd943159 1105 return;
99ea7127
KP		 1106
1107 DRM_DEBUG_KMS("Turn eDP power on\n");
1108
1109 if (ironlake_edp_have_panel_power(intel_dp)) {
1110 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1111 return;
99ea7127 1112 }
9934c132 1113
99ea7127 1114 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1115
99ea7127 1116 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1117 if (IS_GEN5(dev)) {
1118 /* ILK workaround: disable reset around power sequence */
1119 pp &= ~PANEL_POWER_RESET;
1120 I915_WRITE(PCH_PP_CONTROL, pp);
1121 POSTING_READ(PCH_PP_CONTROL);
1122 }
37c6c9b0 1123
1c0ae80a 1124 pp |= POWER_TARGET_ON;
99ea7127
KP		 1125 if (!IS_GEN5(dev))
1126 pp |= PANEL_POWER_RESET;
1127
9934c132 1128 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1129 POSTING_READ(PCH_PP_CONTROL);
9934c132 1130
99ea7127 1131 ironlake_wait_panel_on(intel_dp);
9934c132 1132
05ce1a49
KP		 1133 if (IS_GEN5(dev)) {
1134 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1135 I915_WRITE(PCH_PP_CONTROL, pp);
1136 POSTING_READ(PCH_PP_CONTROL);
1137 }
9934c132
JB		 1138}
1139
82a4d9c0 1140void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1141{
99ea7127 1142 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1143 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1144 u32 pp;
9934c132 1145
97af61f5
KP		 1146 if (!is_edp(intel_dp))
1147 return;
37c6c9b0 1148
99ea7127 1149 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1150
6cb49835 1151 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1152
99ea7127 1153 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1154 /* We need to switch off panel power _and_ force vdd, for otherwise some
1155 * panels get very unhappy and cease to work. */
1156 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1157 I915_WRITE(PCH_PP_CONTROL, pp);
1158 POSTING_READ(PCH_PP_CONTROL);
9934c132 1159
35a38556
DV		 1160 intel_dp->want_panel_vdd = false;
1161
99ea7127 1162 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1163}
1164
d6c50ff8 1165void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1166{
f01eca2e 1167 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 1168 struct drm_i915_private *dev_priv = dev->dev_private;
035aa3de 1169 int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
32f9d658
ZW		 1170 u32 pp;
1171
f01eca2e
KP		 1172 if (!is_edp(intel_dp))
1173 return;
1174
28c97730 1175 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1176 /*
1177 * If we enable the backlight right away following a panel power
1178 * on, we may see slight flicker as the panel syncs with the eDP
1179 * link. So delay a bit to make sure the image is solid before
1180 * allowing it to appear.
1181 */
f01eca2e 1182 msleep(intel_dp->backlight_on_delay);
832dd3c1 1183 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1184 pp |= EDP_BLC_ENABLE;
1185 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1186 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1187
1188 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1189}
1190
d6c50ff8 1191void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1192{
f01eca2e 1193 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1194 struct drm_i915_private *dev_priv = dev->dev_private;
1195 u32 pp;
1196
f01eca2e
KP		 1197 if (!is_edp(intel_dp))
1198 return;
1199
035aa3de
DV		 1200 intel_panel_disable_backlight(dev);
1201
28c97730 1202 DRM_DEBUG_KMS("\n");
832dd3c1 1203 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1204 pp &= ~EDP_BLC_ENABLE;
1205 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1206 POSTING_READ(PCH_PP_CONTROL);
1207 msleep(intel_dp->backlight_off_delay);
32f9d658 1208}
a4fc5ed6 1209
2bd2ad64 1210static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1211{
2bd2ad64
DV		 1212 struct drm_device *dev = intel_dp->base.base.dev;
1213 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 u32 dpa_ctl;
1216
2bd2ad64
DV		 1217 assert_pipe_disabled(dev_priv,
1218 to_intel_crtc(crtc)->pipe);
1219
d240f20f
JB		 1220 DRM_DEBUG_KMS("\n");
1221 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1222 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1223 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1224
1225 /* We don't adjust intel_dp->DP while tearing down the link, to
1226 * facilitate link retraining (e.g. after hotplug). Hence clear all
1227 * enable bits here to ensure that we don't enable too much. */
1228 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1229 intel_dp->DP |= DP_PLL_ENABLE;
1230 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1231 POSTING_READ(DP_A);
1232 udelay(200);
d240f20f
JB		 1233}
1234
2bd2ad64 1235static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1236{
2bd2ad64
DV		 1237 struct drm_device *dev = intel_dp->base.base.dev;
1238 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1239 struct drm_i915_private *dev_priv = dev->dev_private;
1240 u32 dpa_ctl;
1241
2bd2ad64
DV		 1242 assert_pipe_disabled(dev_priv,
1243 to_intel_crtc(crtc)->pipe);
1244
d240f20f 1245 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1246 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1247 "dp pll off, should be on\n");
1248 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1249
1250 /* We can't rely on the value tracked for the DP register in
1251 * intel_dp->DP because link_down must not change that (otherwise link
1252 * re-training will fail. */
298b0b39 1253 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1254 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1255 POSTING_READ(DP_A);
d240f20f
JB		 1256 udelay(200);
1257}
1258
c7ad3810 1259/* If the sink supports it, try to set the power state appropriately */
c19b0669 1260void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1261{
1262 int ret, i;
1263
1264 /* Should have a valid DPCD by this point */
1265 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1266 return;
1267
1268 if (mode != DRM_MODE_DPMS_ON) {
1269 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1270 DP_SET_POWER_D3);
1271 if (ret != 1)
1272 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1273 } else {
1274 /*
1275 * When turning on, we need to retry for 1ms to give the sink
1276 * time to wake up.
1277 */
1278 for (i = 0; i < 3; i++) {
1279 ret = intel_dp_aux_native_write_1(intel_dp,
1280 DP_SET_POWER,
1281 DP_SET_POWER_D0);
1282 if (ret == 1)
1283 break;
1284 msleep(1);
1285 }
1286 }
1287}
1288
19d8fe15
DV		 1289static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1290 enum pipe *pipe)
d240f20f 1291{
19d8fe15
DV		 1292 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1293 struct drm_device *dev = encoder->base.dev;
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 u32 tmp = I915_READ(intel_dp->output_reg);
1296
1297 if (!(tmp & DP_PORT_EN))
1298 return false;
1299
1300 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1301 *pipe = PORT_TO_PIPE_CPT(tmp);
1302 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1303 *pipe = PORT_TO_PIPE(tmp);
1304 } else {
1305 u32 trans_sel;
1306 u32 trans_dp;
1307 int i;
1308
1309 switch (intel_dp->output_reg) {
1310 case PCH_DP_B:
1311 trans_sel = TRANS_DP_PORT_SEL_B;
1312 break;
1313 case PCH_DP_C:
1314 trans_sel = TRANS_DP_PORT_SEL_C;
1315 break;
1316 case PCH_DP_D:
1317 trans_sel = TRANS_DP_PORT_SEL_D;
1318 break;
1319 default:
1320 return true;
1321 }
1322
1323 for_each_pipe(i) {
1324 trans_dp = I915_READ(TRANS_DP_CTL(i));
1325 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1326 *pipe = i;
1327 return true;
1328 }
1329 }
19d8fe15 1330
4a0833ec
DV		 1331 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1332 intel_dp->output_reg);
1333 }
d240f20f 1334
19d8fe15
DV		 1335 return true;
1336}
1337
e8cb4558 1338static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1339{
e8cb4558 1340 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1341
1342 /* Make sure the panel is off before trying to change the mode. But also
1343 * ensure that we have vdd while we switch off the panel. */
1344 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1345 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1346 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1347 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1348
1349 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1350 if (!is_cpu_edp(intel_dp))
1351 intel_dp_link_down(intel_dp);
d240f20f
JB		 1352}
1353
2bd2ad64
DV		 1354static void intel_post_disable_dp(struct intel_encoder *encoder)
1355{
1356 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1357
3739850b
DV		 1358 if (is_cpu_edp(intel_dp)) {
1359 intel_dp_link_down(intel_dp);
2bd2ad64 1360 ironlake_edp_pll_off(intel_dp);
3739850b 1361 }
2bd2ad64
DV		 1362}
1363
e8cb4558 1364static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1365{
e8cb4558
DV		 1366 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1367 struct drm_device *dev = encoder->base.dev;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1370
0c33d8d7
DV		 1371 if (WARN_ON(dp_reg & DP_PORT_EN))
1372 return;
1373
97af61f5 1374 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1375 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1376 intel_dp_start_link_train(intel_dp);
1377 ironlake_edp_panel_on(intel_dp);
1378 ironlake_edp_panel_vdd_off(intel_dp, true);
1379 intel_dp_complete_link_train(intel_dp);
f01eca2e 1380 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1381}
1382
2bd2ad64 1383static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1384{
2bd2ad64 1385 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1386
2bd2ad64
DV		 1387 if (is_cpu_edp(intel_dp))
1388 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1389}
1390
1391/*
df0c237d
JB		 1392 * Native read with retry for link status and receiver capability reads for
1393 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1394 */
1395static bool
df0c237d
JB		 1396intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1397 uint8_t *recv, int recv_bytes)
a4fc5ed6 1398{
61da5fab
JB		 1399 int ret, i;
1400
df0c237d
JB		 1401 /*
1402 * Sinks are *supposed* to come up within 1ms from an off state,
1403 * but we're also supposed to retry 3 times per the spec.
1404 */
61da5fab 1405 for (i = 0; i < 3; i++) {
df0c237d
JB		 1406 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1407 recv_bytes);
1408 if (ret == recv_bytes)
61da5fab
JB		 1409 return true;
1410 msleep(1);
1411 }
a4fc5ed6 1412
61da5fab 1413 return false;
a4fc5ed6
KP		 1414}
1415
1416/*
1417 * Fetch AUX CH registers 0x202 - 0x207 which contain
1418 * link status information
1419 */
1420static bool
93f62dad 1421intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1422{
df0c237d
JB		 1423 return intel_dp_aux_native_read_retry(intel_dp,
1424 DP_LANE0_1_STATUS,
93f62dad 1425 link_status,
df0c237d 1426 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1427}
1428
a4fc5ed6
KP		 1429#if 0
1430static char *voltage_names[] = {
1431 "0.4V", "0.6V", "0.8V", "1.2V"
1432};
1433static char *pre_emph_names[] = {
1434 "0dB", "3.5dB", "6dB", "9.5dB"
1435};
1436static char *link_train_names[] = {
1437 "pattern 1", "pattern 2", "idle", "off"
1438};
1439#endif
1440
1441/*
1442 * These are source-specific values; current Intel hardware supports
1443 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1444 */
a4fc5ed6
KP		 1445
1446static uint8_t
1a2eb460 1447intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1448{
1a2eb460
KP		 1449 struct drm_device *dev = intel_dp->base.base.dev;
1450
1451 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1452 return DP_TRAIN_VOLTAGE_SWING_800;
1453 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1454 return DP_TRAIN_VOLTAGE_SWING_1200;
1455 else
1456 return DP_TRAIN_VOLTAGE_SWING_800;
1457}
1458
1459static uint8_t
1460intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1461{
1462 struct drm_device *dev = intel_dp->base.base.dev;
1463
d6c0d722
PZ		 1464 if (IS_HASWELL(dev)) {
1465 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1466 case DP_TRAIN_VOLTAGE_SWING_400:
1467 return DP_TRAIN_PRE_EMPHASIS_9_5;
1468 case DP_TRAIN_VOLTAGE_SWING_600:
1469 return DP_TRAIN_PRE_EMPHASIS_6;
1470 case DP_TRAIN_VOLTAGE_SWING_800:
1471 return DP_TRAIN_PRE_EMPHASIS_3_5;
1472 case DP_TRAIN_VOLTAGE_SWING_1200:
1473 default:
1474 return DP_TRAIN_PRE_EMPHASIS_0;
1475 }
1476 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1477 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1478 case DP_TRAIN_VOLTAGE_SWING_400:
1479 return DP_TRAIN_PRE_EMPHASIS_6;
1480 case DP_TRAIN_VOLTAGE_SWING_600:
1481 case DP_TRAIN_VOLTAGE_SWING_800:
1482 return DP_TRAIN_PRE_EMPHASIS_3_5;
1483 default:
1484 return DP_TRAIN_PRE_EMPHASIS_0;
1485 }
1486 } else {
1487 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1488 case DP_TRAIN_VOLTAGE_SWING_400:
1489 return DP_TRAIN_PRE_EMPHASIS_6;
1490 case DP_TRAIN_VOLTAGE_SWING_600:
1491 return DP_TRAIN_PRE_EMPHASIS_6;
1492 case DP_TRAIN_VOLTAGE_SWING_800:
1493 return DP_TRAIN_PRE_EMPHASIS_3_5;
1494 case DP_TRAIN_VOLTAGE_SWING_1200:
1495 default:
1496 return DP_TRAIN_PRE_EMPHASIS_0;
1497 }
a4fc5ed6
KP		 1498 }
1499}
1500
1501static void
93f62dad 1502intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1503{
1504 uint8_t v = 0;
1505 uint8_t p = 0;
1506 int lane;
1a2eb460
KP		 1507 uint8_t voltage_max;
1508 uint8_t preemph_max;
a4fc5ed6 1509
33a34e4e 1510 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1511 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1512 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1513
1514 if (this_v > v)
1515 v = this_v;
1516 if (this_p > p)
1517 p = this_p;
1518 }
1519
1a2eb460 1520 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1521 if (v >= voltage_max)
1522 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1523
1a2eb460
KP		 1524 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1525 if (p >= preemph_max)
1526 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1527
1528 for (lane = 0; lane < 4; lane++)
33a34e4e 1529 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1530}
1531
1532static uint32_t
93f62dad 1533intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1534{
3cf2efb1 1535 uint32_t signal_levels = 0;
a4fc5ed6 1536
3cf2efb1 1537 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1538 case DP_TRAIN_VOLTAGE_SWING_400:
1539 default:
1540 signal_levels |= DP_VOLTAGE_0_4;
1541 break;
1542 case DP_TRAIN_VOLTAGE_SWING_600:
1543 signal_levels |= DP_VOLTAGE_0_6;
1544 break;
1545 case DP_TRAIN_VOLTAGE_SWING_800:
1546 signal_levels |= DP_VOLTAGE_0_8;
1547 break;
1548 case DP_TRAIN_VOLTAGE_SWING_1200:
1549 signal_levels |= DP_VOLTAGE_1_2;
1550 break;
1551 }
3cf2efb1 1552 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1553 case DP_TRAIN_PRE_EMPHASIS_0:
1554 default:
1555 signal_levels |= DP_PRE_EMPHASIS_0;
1556 break;
1557 case DP_TRAIN_PRE_EMPHASIS_3_5:
1558 signal_levels |= DP_PRE_EMPHASIS_3_5;
1559 break;
1560 case DP_TRAIN_PRE_EMPHASIS_6:
1561 signal_levels |= DP_PRE_EMPHASIS_6;
1562 break;
1563 case DP_TRAIN_PRE_EMPHASIS_9_5:
1564 signal_levels |= DP_PRE_EMPHASIS_9_5;
1565 break;
1566 }
1567 return signal_levels;
1568}
1569
e3421a18
ZW		 1570/* Gen6's DP voltage swing and pre-emphasis control */
1571static uint32_t
1572intel_gen6_edp_signal_levels(uint8_t train_set)
1573{
3c5a62b5
YL		 1574 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1575 DP_TRAIN_PRE_EMPHASIS_MASK);
1576 switch (signal_levels) {
e3421a18 1577 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1578 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1579 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1580 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1581 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1582 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1583 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1584 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1585 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1586 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1587 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1588 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1589 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1590 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1591 default:
3c5a62b5
YL		 1592 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1593 "0x%x\n", signal_levels);
1594 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1595 }
1596}
1597
1a2eb460
KP		 1598/* Gen7's DP voltage swing and pre-emphasis control */
1599static uint32_t
1600intel_gen7_edp_signal_levels(uint8_t train_set)
1601{
1602 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1603 DP_TRAIN_PRE_EMPHASIS_MASK);
1604 switch (signal_levels) {
1605 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1606 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1607 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1608 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1609 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1610 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1611
1612 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1613 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1614 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1615 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1616
1617 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1618 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1619 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1620 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1621
1622 default:
1623 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1624 "0x%x\n", signal_levels);
1625 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1626 }
1627}
1628
d6c0d722
PZ		 1629/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1630static uint32_t
1631intel_dp_signal_levels_hsw(uint8_t train_set)
1632{
1633 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1634 DP_TRAIN_PRE_EMPHASIS_MASK);
1635 switch (signal_levels) {
1636 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1637 return DDI_BUF_EMP_400MV_0DB_HSW;
1638 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1639 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1640 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1641 return DDI_BUF_EMP_400MV_6DB_HSW;
1642 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1643 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1644
1645 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1646 return DDI_BUF_EMP_600MV_0DB_HSW;
1647 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1648 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1649 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1650 return DDI_BUF_EMP_600MV_6DB_HSW;
1651
1652 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1653 return DDI_BUF_EMP_800MV_0DB_HSW;
1654 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1655 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1656 default:
1657 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1658 "0x%x\n", signal_levels);
1659 return DDI_BUF_EMP_400MV_0DB_HSW;
1660 }
1661}
1662
a4fc5ed6 1663static bool
ea5b213a 1664intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1665 uint32_t dp_reg_value,
58e10eb9 1666 uint8_t dp_train_pat)
a4fc5ed6 1667{
4ef69c7a 1668 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1669 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1670 int ret;
d6c0d722 1671 uint32_t temp;
a4fc5ed6 1672
d6c0d722
PZ		 1673 if (IS_HASWELL(dev)) {
1674 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1675
1676 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1677 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1678 else
1679 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1680
1681 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1682 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1683 case DP_TRAINING_PATTERN_DISABLE:
1684 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1685 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1686
1687 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1688 DP_TP_STATUS_IDLE_DONE), 1))
1689 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1690
1691 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1692 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1693
1694 break;
1695 case DP_TRAINING_PATTERN_1:
1696 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1697 break;
1698 case DP_TRAINING_PATTERN_2:
1699 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1700 break;
1701 case DP_TRAINING_PATTERN_3:
1702 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1703 break;
1704 }
1705 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1706
1707 } else if (HAS_PCH_CPT(dev) &&
1708 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1709 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1710
1711 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1712 case DP_TRAINING_PATTERN_DISABLE:
1713 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1714 break;
1715 case DP_TRAINING_PATTERN_1:
1716 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1717 break;
1718 case DP_TRAINING_PATTERN_2:
1719 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1720 break;
1721 case DP_TRAINING_PATTERN_3:
1722 DRM_ERROR("DP training pattern 3 not supported\n");
1723 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1724 break;
1725 }
1726
1727 } else {
1728 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1729
1730 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1731 case DP_TRAINING_PATTERN_DISABLE:
1732 dp_reg_value |= DP_LINK_TRAIN_OFF;
1733 break;
1734 case DP_TRAINING_PATTERN_1:
1735 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1736 break;
1737 case DP_TRAINING_PATTERN_2:
1738 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1739 break;
1740 case DP_TRAINING_PATTERN_3:
1741 DRM_ERROR("DP training pattern 3 not supported\n");
1742 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1743 break;
1744 }
1745 }
1746
ea5b213a
CW		 1747 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1748 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1749
ea5b213a 1750 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1751 DP_TRAINING_PATTERN_SET,
1752 dp_train_pat);
1753
47ea7542
PZ		 1754 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1755 DP_TRAINING_PATTERN_DISABLE) {
1756 ret = intel_dp_aux_native_write(intel_dp,
1757 DP_TRAINING_LANE0_SET,
1758 intel_dp->train_set,
1759 intel_dp->lane_count);
1760 if (ret != intel_dp->lane_count)
1761 return false;
1762 }
a4fc5ed6
KP		 1763
1764 return true;
1765}
1766
33a34e4e 1767/* Enable corresponding port and start training pattern 1 */
c19b0669 1768void
33a34e4e 1769intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1770{
c19b0669
PZ		 1771 struct drm_encoder *encoder = &intel_dp->base.base;
1772 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1773 int i;
1774 uint8_t voltage;
1775 bool clock_recovery = false;
cdb0e95b 1776 int voltage_tries, loop_tries;
ea5b213a 1777 uint32_t DP = intel_dp->DP;
a4fc5ed6 1778
c19b0669
PZ		 1779 if (IS_HASWELL(dev))
1780 intel_ddi_prepare_link_retrain(encoder);
1781
3cf2efb1
CW		 1782 /* Write the link configuration data */
1783 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1784 intel_dp->link_configuration,
1785 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1786
1787 DP |= DP_PORT_EN;
1a2eb460 1788
33a34e4e 1789 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1790 voltage = 0xff;
cdb0e95b
KP		 1791 voltage_tries = 0;
1792 loop_tries = 0;
a4fc5ed6
KP		 1793 clock_recovery = false;
1794 for (;;) {
33a34e4e 1795 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1796 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1797 uint32_t signal_levels;
417e822d 1798
d6c0d722
PZ		 1799 if (IS_HASWELL(dev)) {
1800 signal_levels = intel_dp_signal_levels_hsw(
1801 intel_dp->train_set[0]);
1802 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1803 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1804 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1805 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1806 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1807 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1808 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1809 } else {
93f62dad 1810 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1811 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1812 }
d6c0d722
PZ		 1813 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1814 signal_levels);
a4fc5ed6 1815
a7c9655f 1816 /* Set training pattern 1 */
47ea7542 1817 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1818 DP_TRAINING_PATTERN_1 |
1819 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1820 break;
a4fc5ed6 1821
a7c9655f 1822 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1823 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1824 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1825 break;
93f62dad 1826 }
a4fc5ed6 1827
01916270 1828 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1829 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1830 clock_recovery = true;
1831 break;
1832 }
1833
1834 /* Check to see if we've tried the max voltage */
1835 for (i = 0; i < intel_dp->lane_count; i++)
1836 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1837 break;
0d710688 1838 if (i == intel_dp->lane_count && voltage_tries == 5) {
24773670 1839 if (++loop_tries == 5) {
cdb0e95b
KP		 1840 DRM_DEBUG_KMS("too many full retries, give up\n");
1841 break;
1842 }
1843 memset(intel_dp->train_set, 0, 4);
1844 voltage_tries = 0;
1845 continue;
1846 }
a4fc5ed6 1847
3cf2efb1 1848 /* Check to see if we've tried the same voltage 5 times */
24773670
CW		 1849 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1850 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
cdb0e95b 1851 voltage_tries = 0;
24773670
CW		 1852 } else
1853 ++voltage_tries;
a4fc5ed6 1854
3cf2efb1 1855 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1856 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1857 }
1858
33a34e4e
JB		 1859 intel_dp->DP = DP;
1860}
1861
c19b0669 1862void
33a34e4e
JB		 1863intel_dp_complete_link_train(struct intel_dp *intel_dp)
1864{
4ef69c7a 1865 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1866 bool channel_eq = false;
37f80975 1867 int tries, cr_tries;
33a34e4e
JB		 1868 uint32_t DP = intel_dp->DP;
1869
a4fc5ed6
KP		 1870 /* channel equalization */
1871 tries = 0;
37f80975 1872 cr_tries = 0;
a4fc5ed6
KP		 1873 channel_eq = false;
1874 for (;;) {
33a34e4e 1875 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1876 uint32_t signal_levels;
93f62dad 1877 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1878
37f80975
JB		 1879 if (cr_tries > 5) {
1880 DRM_ERROR("failed to train DP, aborting\n");
1881 intel_dp_link_down(intel_dp);
1882 break;
1883 }
1884
d6c0d722
PZ		 1885 if (IS_HASWELL(dev)) {
1886 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1887 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1888 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1889 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1890 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1891 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1892 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1893 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1894 } else {
93f62dad 1895 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1896 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1897 }
1898
a4fc5ed6 1899 /* channel eq pattern */
47ea7542 1900 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1901 DP_TRAINING_PATTERN_2 |
1902 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1903 break;
1904
a7c9655f 1905 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1906 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1907 break;
a4fc5ed6 1908
37f80975 1909 /* Make sure clock is still ok */
01916270 1910 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1911 intel_dp_start_link_train(intel_dp);
1912 cr_tries++;
1913 continue;
1914 }
1915
1ffdff13 1916 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1917 channel_eq = true;
1918 break;
1919 }
a4fc5ed6 1920
37f80975
JB		 1921 /* Try 5 times, then try clock recovery if that fails */
1922 if (tries > 5) {
1923 intel_dp_link_down(intel_dp);
1924 intel_dp_start_link_train(intel_dp);
1925 tries = 0;
1926 cr_tries++;
1927 continue;
1928 }
a4fc5ed6 1929
3cf2efb1 1930 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1931 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1932 ++tries;
869184a6 1933 }
3cf2efb1 1934
d6c0d722
PZ		 1935 if (channel_eq)
1936 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1937
47ea7542 1938 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1939}
1940
1941static void
ea5b213a 1942intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1943{
4ef69c7a 1944 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1945 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1946 uint32_t DP = intel_dp->DP;
a4fc5ed6 1947
c19b0669
PZ		 1948 /*
1949 * DDI code has a strict mode set sequence and we should try to respect
1950 * it, otherwise we might hang the machine in many different ways. So we
1951 * really should be disabling the port only on a complete crtc_disable
1952 * sequence. This function is just called under two conditions on DDI
1953 * code:
1954 * - Link train failed while doing crtc_enable, and on this case we
1955 * really should respect the mode set sequence and wait for a
1956 * crtc_disable.
1957 * - Someone turned the monitor off and intel_dp_check_link_status
1958 * called us. We don't need to disable the whole port on this case, so
1959 * when someone turns the monitor on again,
1960 * intel_ddi_prepare_link_retrain will take care of redoing the link
1961 * train.
1962 */
1963 if (IS_HASWELL(dev))
1964 return;
1965
0c33d8d7 1966 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1967 return;
1968
28c97730 1969 DRM_DEBUG_KMS("\n");
32f9d658 1970
1a2eb460 1971 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1972 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1973 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1974 } else {
1975 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1976 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1977 }
fe255d00 1978 POSTING_READ(intel_dp->output_reg);
5eb08b69 1979
fe255d00 1980 msleep(17);
5eb08b69 1981
493a7081 1982 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1983 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1984 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1985
5bddd17f
EA		 1986 /* Hardware workaround: leaving our transcoder select
1987 * set to transcoder B while it's off will prevent the
1988 * corresponding HDMI output on transcoder A.
1989 *
1990 * Combine this with another hardware workaround:
1991 * transcoder select bit can only be cleared while the
1992 * port is enabled.
1993 */
1994 DP &= ~DP_PIPEB_SELECT;
1995 I915_WRITE(intel_dp->output_reg, DP);
1996
1997 /* Changes to enable or select take place the vblank
1998 * after being written.
1999 */
31acbcc4
CW		 2000 if (crtc == NULL) {
2001 /* We can arrive here never having been attached
2002 * to a CRTC, for instance, due to inheriting
2003 * random state from the BIOS.
2004 *
2005 * If the pipe is not running, play safe and
2006 * wait for the clocks to stabilise before
2007 * continuing.
2008 */
2009 POSTING_READ(intel_dp->output_reg);
2010 msleep(50);
2011 } else
2012 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2013 }
2014
832afda6 2015 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2016 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2017 POSTING_READ(intel_dp->output_reg);
f01eca2e 2018 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2019}
2020
26d61aad
KP		 2021static bool
2022intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2023{
92fd8fd1 2024 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2025 sizeof(intel_dp->dpcd)) == 0)
2026 return false; /* aux transfer failed */
92fd8fd1 2027
b091cd92
AJ		 2028 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2029 return false; /* DPCD not present */
2030
2031 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2032 DP_DWN_STRM_PORT_PRESENT))
2033 return true; /* native DP sink */
2034
2035 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2036 return true; /* no per-port downstream info */
2037
2038 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2039 intel_dp->downstream_ports,
2040 DP_MAX_DOWNSTREAM_PORTS) == 0)
2041 return false; /* downstream port status fetch failed */
2042
2043 return true;
92fd8fd1
KP		 2044}
2045
0d198328
AJ		 2046static void
2047intel_dp_probe_oui(struct intel_dp *intel_dp)
2048{
2049 u8 buf[3];
2050
2051 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2052 return;
2053
351cfc34
DV		 2054 ironlake_edp_panel_vdd_on(intel_dp);
2055
0d198328
AJ		 2056 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2057 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2058 buf[0], buf[1], buf[2]);
2059
2060 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2061 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2062 buf[0], buf[1], buf[2]);
351cfc34
DV		 2063
2064 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2065}
2066
a60f0e38
JB		 2067static bool
2068intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2069{
2070 int ret;
2071
2072 ret = intel_dp_aux_native_read_retry(intel_dp,
2073 DP_DEVICE_SERVICE_IRQ_VECTOR,
2074 sink_irq_vector, 1);
2075 if (!ret)
2076 return false;
2077
2078 return true;
2079}
2080
2081static void
2082intel_dp_handle_test_request(struct intel_dp *intel_dp)
2083{
2084 /* NAK by default */
9324cf7f 2085 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2086}
2087
a4fc5ed6
KP		 2088/*
2089 * According to DP spec
2090 * 5.1.2:
2091 * 1. Read DPCD
2092 * 2. Configure link according to Receiver Capabilities
2093 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2094 * 4. Check link status on receipt of hot-plug interrupt
2095 */
2096
2097static void
ea5b213a 2098intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2099{
a60f0e38 2100 u8 sink_irq_vector;
93f62dad 2101 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2102
24e804ba 2103 if (!intel_dp->base.connectors_active)
d2b996ac 2104 return;
59cd09e1 2105
24e804ba 2106 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2107 return;
2108
92fd8fd1 2109 /* Try to read receiver status if the link appears to be up */
93f62dad 2110 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2111 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2112 return;
2113 }
2114
92fd8fd1 2115 /* Now read the DPCD to see if it's actually running */
26d61aad 2116 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2117 intel_dp_link_down(intel_dp);
2118 return;
2119 }
2120
a60f0e38
JB		 2121 /* Try to read the source of the interrupt */
2122 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2123 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2124 /* Clear interrupt source */
2125 intel_dp_aux_native_write_1(intel_dp,
2126 DP_DEVICE_SERVICE_IRQ_VECTOR,
2127 sink_irq_vector);
2128
2129 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2130 intel_dp_handle_test_request(intel_dp);
2131 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2132 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2133 }
2134
1ffdff13 2135 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1
KP		 2136 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2137 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2138 intel_dp_start_link_train(intel_dp);
2139 intel_dp_complete_link_train(intel_dp);
2140 }
a4fc5ed6 2141}
a4fc5ed6 2142
07d3dc18 2143/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2144static enum drm_connector_status
26d61aad 2145intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2146{
07d3dc18
AJ		 2147 uint8_t *dpcd = intel_dp->dpcd;
2148 bool hpd;
2149 uint8_t type;
2150
2151 if (!intel_dp_get_dpcd(intel_dp))
2152 return connector_status_disconnected;
2153
2154 /* if there's no downstream port, we're done */
2155 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2156 return connector_status_connected;
2157
2158 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2159 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2160 if (hpd) {
da131a46 2161 uint8_t reg;
07d3dc18 2162 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2163 &reg, 1))
07d3dc18 2164 return connector_status_unknown;
da131a46
AJ		 2165 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2166 : connector_status_disconnected;
07d3dc18
AJ		 2167 }
2168
2169 /* If no HPD, poke DDC gently */
2170 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2171 return connector_status_connected;
07d3dc18
AJ		 2172
2173 /* Well we tried, say unknown for unreliable port types */
2174 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2175 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2176 return connector_status_unknown;
2177
2178 /* Anything else is out of spec, warn and ignore */
2179 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2180 return connector_status_disconnected;
71ba9000
AJ		 2181}
2182
5eb08b69 2183static enum drm_connector_status
a9756bb5 2184ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2185{
5eb08b69
ZW		 2186 enum drm_connector_status status;
2187
fe16d949
CW		 2188 /* Can't disconnect eDP, but you can close the lid... */
2189 if (is_edp(intel_dp)) {
2190 status = intel_panel_detect(intel_dp->base.base.dev);
2191 if (status == connector_status_unknown)
2192 status = connector_status_connected;
2193 return status;
2194 }
01cb9ea6 2195
26d61aad 2196 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2197}
2198
a4fc5ed6 2199static enum drm_connector_status
a9756bb5 2200g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2201{
4ef69c7a 2202 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2203 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2204 uint32_t bit;
5eb08b69 2205
ea5b213a 2206 switch (intel_dp->output_reg) {
a4fc5ed6 2207 case DP_B:
10f76a38 2208 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2209 break;
2210 case DP_C:
10f76a38 2211 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2212 break;
2213 case DP_D:
10f76a38 2214 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2215 break;
2216 default:
2217 return connector_status_unknown;
2218 }
2219
10f76a38 2220 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2221 return connector_status_disconnected;
2222
26d61aad 2223 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2224}
2225
8c241fef
KP		 2226static struct edid *
2227intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2228{
9cd300e0 2229 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2230
9cd300e0
JN		 2231 /* use cached edid if we have one */
2232 if (intel_connector->edid) {
2233 struct edid *edid;
2234 int size;
2235
2236 /* invalid edid */
2237 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2238 return NULL;
2239
9cd300e0 2240 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2241 edid = kmalloc(size, GFP_KERNEL);
2242 if (!edid)
2243 return NULL;
2244
9cd300e0 2245 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2246 return edid;
2247 }
8c241fef 2248
9cd300e0 2249 return drm_get_edid(connector, adapter);
8c241fef
KP		 2250}
2251
2252static int
2253intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2254{
9cd300e0 2255 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2256
9cd300e0
JN		 2257 /* use cached edid if we have one */
2258 if (intel_connector->edid) {
2259 /* invalid edid */
2260 if (IS_ERR(intel_connector->edid))
2261 return 0;
2262
2263 return intel_connector_update_modes(connector,
2264 intel_connector->edid);
d6f24d0f
JB		 2265 }
2266
9cd300e0 2267 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2268}
2269
2270
a9756bb5
ZW		 2271/**
2272 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2273 *
2274 * \return true if DP port is connected.
2275 * \return false if DP port is disconnected.
2276 */
2277static enum drm_connector_status
2278intel_dp_detect(struct drm_connector *connector, bool force)
2279{
2280 struct intel_dp *intel_dp = intel_attached_dp(connector);
2281 struct drm_device *dev = intel_dp->base.base.dev;
2282 enum drm_connector_status status;
2283 struct edid *edid = NULL;
898076ed 2284 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
a9756bb5
ZW		 2285
2286 intel_dp->has_audio = false;
2287
2288 if (HAS_PCH_SPLIT(dev))
2289 status = ironlake_dp_detect(intel_dp);
2290 else
2291 status = g4x_dp_detect(intel_dp);
1b9be9d0 2292
898076ed
JN		 2293 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2294 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2295 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
1b9be9d0 2296
a9756bb5
ZW		 2297 if (status != connector_status_connected)
2298 return status;
2299
0d198328
AJ		 2300 intel_dp_probe_oui(intel_dp);
2301
c3e5f67b
DV		 2302 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2303 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2304 } else {
8c241fef 2305 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2306 if (edid) {
2307 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2308 kfree(edid);
2309 }
a9756bb5
ZW		 2310 }
2311
2312 return connector_status_connected;
a4fc5ed6
KP		 2313}
2314
2315static int intel_dp_get_modes(struct drm_connector *connector)
2316{
df0e9248 2317 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2318 struct intel_connector *intel_connector = to_intel_connector(connector);
4ef69c7a 2319 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 2320 int ret;
a4fc5ed6
KP		 2321
2322 /* We should parse the EDID data and find out if it has an audio sink
2323 */
2324
8c241fef 2325 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2326 if (ret)
32f9d658
ZW		 2327 return ret;
2328
f8779fda 2329 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2330 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2331 struct drm_display_mode *mode;
dd06f90e
JN		 2332 mode = drm_mode_duplicate(dev,
2333 intel_connector->panel.fixed_mode);
f8779fda 2334 if (mode) {
32f9d658
ZW		 2335 drm_mode_probed_add(connector, mode);
2336 return 1;
2337 }
2338 }
2339 return 0;
a4fc5ed6
KP		 2340}
2341
1aad7ac0
CW		 2342static bool
2343intel_dp_detect_audio(struct drm_connector *connector)
2344{
2345 struct intel_dp *intel_dp = intel_attached_dp(connector);
2346 struct edid *edid;
2347 bool has_audio = false;
2348
8c241fef 2349 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2350 if (edid) {
2351 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2352 kfree(edid);
2353 }
2354
2355 return has_audio;
2356}
2357
f684960e
CW		 2358static int
2359intel_dp_set_property(struct drm_connector *connector,
2360 struct drm_property *property,
2361 uint64_t val)
2362{
e953fd7b 2363 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2364 struct intel_connector *intel_connector = to_intel_connector(connector);
f684960e
CW		 2365 struct intel_dp *intel_dp = intel_attached_dp(connector);
2366 int ret;
2367
2368 ret = drm_connector_property_set_value(connector, property, val);
2369 if (ret)
2370 return ret;
2371
3f43c48d 2372 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2373 int i = val;
2374 bool has_audio;
2375
2376 if (i == intel_dp->force_audio)
f684960e
CW		 2377 return 0;
2378
1aad7ac0 2379 intel_dp->force_audio = i;
f684960e 2380
c3e5f67b 2381 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2382 has_audio = intel_dp_detect_audio(connector);
2383 else
c3e5f67b 2384 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2385
2386 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2387 return 0;
2388
1aad7ac0 2389 intel_dp->has_audio = has_audio;
f684960e
CW		 2390 goto done;
2391 }
2392
e953fd7b
CW		 2393 if (property == dev_priv->broadcast_rgb_property) {
2394 if (val == !!intel_dp->color_range)
2395 return 0;
2396
2397 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2398 goto done;
2399 }
2400
53b41837
YN		 2401 if (is_edp(intel_dp) &&
2402 property == connector->dev->mode_config.scaling_mode_property) {
2403 if (val == DRM_MODE_SCALE_NONE) {
2404 DRM_DEBUG_KMS("no scaling not supported\n");
2405 return -EINVAL;
2406 }
2407
2408 if (intel_connector->panel.fitting_mode == val) {
2409 /* the eDP scaling property is not changed */
2410 return 0;
2411 }
2412 intel_connector->panel.fitting_mode = val;
2413
2414 goto done;
2415 }
2416
f684960e
CW		 2417 return -EINVAL;
2418
2419done:
2420 if (intel_dp->base.base.crtc) {
2421 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2422 intel_set_mode(crtc, &crtc->mode,
2423 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2424 }
2425
2426 return 0;
2427}
2428
a4fc5ed6 2429static void
0206e353 2430intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2431{
aaa6fd2a 2432 struct drm_device *dev = connector->dev;
be3cd5e3 2433 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2434 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2435
9cd300e0
JN		 2436 if (!IS_ERR_OR_NULL(intel_connector->edid))
2437 kfree(intel_connector->edid);
2438
1d508706 2439 if (is_edp(intel_dp)) {
aaa6fd2a 2440 intel_panel_destroy_backlight(dev);
1d508706
JN		 2441 intel_panel_fini(&intel_connector->panel);
2442 }
aaa6fd2a 2443
a4fc5ed6
KP		 2444 drm_sysfs_connector_remove(connector);
2445 drm_connector_cleanup(connector);
55f78c43 2446 kfree(connector);
a4fc5ed6
KP		 2447}
2448
24d05927
DV		 2449static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2450{
2451 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2452
2453 i2c_del_adapter(&intel_dp->adapter);
2454 drm_encoder_cleanup(encoder);
bd943159
KP		 2455 if (is_edp(intel_dp)) {
2456 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2457 ironlake_panel_vdd_off_sync(intel_dp);
2458 }
24d05927
DV		 2459 kfree(intel_dp);
2460}
2461
a4fc5ed6 2462static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2463 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2464 .mode_set = intel_dp_mode_set,
1f703855 2465 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2466};
2467
a7902ac5
PZ		 2468static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2469 .mode_fixup = intel_dp_mode_fixup,
2470 .mode_set = intel_ddi_mode_set,
2471 .disable = intel_encoder_noop,
2472};
2473
a4fc5ed6 2474static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2475 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2476 .detect = intel_dp_detect,
2477 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2478 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2479 .destroy = intel_dp_destroy,
2480};
2481
2482static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2483 .get_modes = intel_dp_get_modes,
2484 .mode_valid = intel_dp_mode_valid,
df0e9248 2485 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2486};
2487
a4fc5ed6 2488static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2489 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2490};
2491
995b6762 2492static void
21d40d37 2493intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2494{
ea5b213a 2495 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2496
885a5014 2497 intel_dp_check_link_status(intel_dp);
c8110e52 2498}
6207937d 2499
e3421a18
ZW		 2500/* Return which DP Port should be selected for Transcoder DP control */
2501int
0206e353 2502intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2503{
2504 struct drm_device *dev = crtc->dev;
6c2b7c12 2505 struct intel_encoder *encoder;
e3421a18 2506
6c2b7c12
DV		 2507 for_each_encoder_on_crtc(dev, crtc, encoder) {
2508 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2509
417e822d
KP		 2510 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2511 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2512 return intel_dp->output_reg;
e3421a18 2513 }
ea5b213a 2514
e3421a18
ZW		 2515 return -1;
2516}
2517
36e83a18 2518/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2519bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2520{
2521 struct drm_i915_private *dev_priv = dev->dev_private;
2522 struct child_device_config *p_child;
2523 int i;
2524
2525 if (!dev_priv->child_dev_num)
2526 return false;
2527
2528 for (i = 0; i < dev_priv->child_dev_num; i++) {
2529 p_child = dev_priv->child_dev + i;
2530
2531 if (p_child->dvo_port == PORT_IDPD &&
2532 p_child->device_type == DEVICE_TYPE_eDP)
2533 return true;
2534 }
2535 return false;
2536}
2537
f684960e
CW		 2538static void
2539intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2540{
53b41837
YN		 2541 struct intel_connector *intel_connector = to_intel_connector(connector);
2542
3f43c48d 2543 intel_attach_force_audio_property(connector);
e953fd7b 2544 intel_attach_broadcast_rgb_property(connector);
53b41837
YN		 2545
2546 if (is_edp(intel_dp)) {
2547 drm_mode_create_scaling_mode_property(connector->dev);
2548 drm_connector_attach_property(
2549 connector,
2550 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2551 DRM_MODE_SCALE_ASPECT);
2552 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2553 }
f684960e
CW		 2554}
2555
67a54566
DV		 2556static void
2557intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2558 struct intel_dp *intel_dp)
2559{
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct edp_power_seq cur, vbt, spec, final;
2562 u32 pp_on, pp_off, pp_div, pp;
2563
2564 /* Workaround: Need to write PP_CONTROL with the unlock key as
2565 * the very first thing. */
2566 pp = ironlake_get_pp_control(dev_priv);
2567 I915_WRITE(PCH_PP_CONTROL, pp);
2568
2569 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2570 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2571 pp_div = I915_READ(PCH_PP_DIVISOR);
2572
2573 /* Pull timing values out of registers */
2574 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2575 PANEL_POWER_UP_DELAY_SHIFT;
2576
2577 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2578 PANEL_LIGHT_ON_DELAY_SHIFT;
2579
2580 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2581 PANEL_LIGHT_OFF_DELAY_SHIFT;
2582
2583 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2584 PANEL_POWER_DOWN_DELAY_SHIFT;
2585
2586 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2587 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2588
2589 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2590 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2591
2592 vbt = dev_priv->edp.pps;
2593
2594 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2595 * our hw here, which are all in 100usec. */
2596 spec.t1_t3 = 210 * 10;
2597 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2598 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2599 spec.t10 = 500 * 10;
2600 /* This one is special and actually in units of 100ms, but zero
2601 * based in the hw (so we need to add 100 ms). But the sw vbt
2602 * table multiplies it with 1000 to make it in units of 100usec,
2603 * too. */
2604 spec.t11_t12 = (510 + 100) * 10;
2605
2606 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2607 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2608
2609 /* Use the max of the register settings and vbt. If both are
2610 * unset, fall back to the spec limits. */
2611#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2612 spec.field : \
2613 max(cur.field, vbt.field))
2614 assign_final(t1_t3);
2615 assign_final(t8);
2616 assign_final(t9);
2617 assign_final(t10);
2618 assign_final(t11_t12);
2619#undef assign_final
2620
2621#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2622 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2623 intel_dp->backlight_on_delay = get_delay(t8);
2624 intel_dp->backlight_off_delay = get_delay(t9);
2625 intel_dp->panel_power_down_delay = get_delay(t10);
2626 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2627#undef get_delay
2628
2629 /* And finally store the new values in the power sequencer. */
2630 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2631 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2632 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2633 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2634 /* Compute the divisor for the pp clock, simply match the Bspec
2635 * formula. */
2636 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2637 << PP_REFERENCE_DIVIDER_SHIFT;
2638 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2639 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2640
2641 /* Haswell doesn't have any port selection bits for the panel
2642 * power sequencer any more. */
2643 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2644 if (is_cpu_edp(intel_dp))
2645 pp_on |= PANEL_POWER_PORT_DP_A;
2646 else
2647 pp_on |= PANEL_POWER_PORT_DP_D;
2648 }
2649
2650 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2651 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2652 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2653
2654
2655 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2656 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2657 intel_dp->panel_power_cycle_delay);
2658
2659 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2660 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2661
2662 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2663 I915_READ(PCH_PP_ON_DELAYS),
2664 I915_READ(PCH_PP_OFF_DELAYS),
2665 I915_READ(PCH_PP_DIVISOR));
2666}
2667
a4fc5ed6 2668void
ab9d7c30 2669intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2670{
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct drm_connector *connector;
ea5b213a 2673 struct intel_dp *intel_dp;
21d40d37 2674 struct intel_encoder *intel_encoder;
55f78c43 2675 struct intel_connector *intel_connector;
f8779fda 2676 struct drm_display_mode *fixed_mode = NULL;
5eb08b69 2677 const char *name = NULL;
b329530c 2678 int type;
a4fc5ed6 2679
ea5b213a
CW		 2680 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2681 if (!intel_dp)
a4fc5ed6
KP		 2682 return;
2683
3d3dc149 2684 intel_dp->output_reg = output_reg;
ab9d7c30 2685 intel_dp->port = port;
0767935e
DV		 2686 /* Preserve the current hw state. */
2687 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2688
55f78c43
ZW		 2689 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2690 if (!intel_connector) {
ea5b213a 2691 kfree(intel_dp);
55f78c43
ZW		 2692 return;
2693 }
ea5b213a 2694 intel_encoder = &intel_dp->base;
dd06f90e 2695 intel_dp->attached_connector = intel_connector;
55f78c43 2696
ea5b213a 2697 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2698 if (intel_dpd_is_edp(dev))
ea5b213a 2699 intel_dp->is_pch_edp = true;
b329530c 2700
19c03924
GB		 2701 /*
2702 * FIXME : We need to initialize built-in panels before external panels.
2703 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2704 */
2705 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2706 type = DRM_MODE_CONNECTOR_eDP;
2707 intel_encoder->type = INTEL_OUTPUT_EDP;
2708 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2709 type = DRM_MODE_CONNECTOR_eDP;
2710 intel_encoder->type = INTEL_OUTPUT_EDP;
2711 } else {
2712 type = DRM_MODE_CONNECTOR_DisplayPort;
2713 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2714 }
2715
55f78c43 2716 connector = &intel_connector->base;
b329530c 2717 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2718 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2719
eb1f8e4f
DA		 2720 connector->polled = DRM_CONNECTOR_POLL_HPD;
2721
66a9278e 2722 intel_encoder->cloneable = false;
f8aed700 2723
66a9278e
DV		 2724 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2725 ironlake_panel_vdd_work);
6251ec0a 2726
27f8227b 2727 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2728
a4fc5ed6
KP		 2729 connector->interlace_allowed = true;
2730 connector->doublescan_allowed = 0;
2731
4ef69c7a 2732 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2733 DRM_MODE_ENCODER_TMDS);
a7902ac5
PZ		 2734
2735 if (IS_HASWELL(dev))
2736 drm_encoder_helper_add(&intel_encoder->base,
2737 &intel_dp_helper_funcs_hsw);
2738 else
2739 drm_encoder_helper_add(&intel_encoder->base,
2740 &intel_dp_helper_funcs);
a4fc5ed6 2741
df0e9248 2742 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2743 drm_sysfs_connector_add(connector);
2744
a7902ac5
PZ		 2745 if (IS_HASWELL(dev)) {
2746 intel_encoder->enable = intel_enable_ddi;
2747 intel_encoder->pre_enable = intel_ddi_pre_enable;
2748 intel_encoder->disable = intel_disable_ddi;
2749 intel_encoder->post_disable = intel_ddi_post_disable;
2750 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2751 } else {
2752 intel_encoder->enable = intel_enable_dp;
2753 intel_encoder->pre_enable = intel_pre_enable_dp;
2754 intel_encoder->disable = intel_disable_dp;
2755 intel_encoder->post_disable = intel_post_disable_dp;
2756 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2757 }
19d8fe15 2758 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2759
a4fc5ed6 2760 /* Set up the DDC bus. */
ab9d7c30
PZ		 2761 switch (port) {
2762 case PORT_A:
2763 name = "DPDDC-A";
2764 break;
2765 case PORT_B:
2766 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2767 name = "DPDDC-B";
2768 break;
2769 case PORT_C:
2770 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2771 name = "DPDDC-C";
2772 break;
2773 case PORT_D:
2774 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2775 name = "DPDDC-D";
2776 break;
2777 default:
2778 WARN(1, "Invalid port %c\n", port_name(port));
2779 break;
5eb08b69
ZW		 2780 }
2781
67a54566
DV		 2782 if (is_edp(intel_dp))
2783 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2784
2785 intel_dp_i2c_init(intel_dp, intel_connector, name);
2786
67a54566 2787 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2788 if (is_edp(intel_dp)) {
2789 bool ret;
f8779fda 2790 struct drm_display_mode *scan;
c1f05264 2791 struct edid *edid;
5d613501
JB		 2792
2793 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2794 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2795 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2796
59f3e272 2797 if (ret) {
7183dc29
JB		 2798 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2799 dev_priv->no_aux_handshake =
2800 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2801 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2802 } else {
3d3dc149 2803 /* if this fails, presume the device is a ghost */
48898b03 2804 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2805 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2806 intel_dp_destroy(&intel_connector->base);
3d3dc149 2807 return;
89667383 2808 }
89667383 2809
d6f24d0f
JB		 2810 ironlake_edp_panel_vdd_on(intel_dp);
2811 edid = drm_get_edid(connector, &intel_dp->adapter);
2812 if (edid) {
9cd300e0
JN		 2813 if (drm_add_edid_modes(connector, edid)) {
2814 drm_mode_connector_update_edid_property(connector, edid);
2815 drm_edid_to_eld(connector, edid);
2816 } else {
2817 kfree(edid);
2818 edid = ERR_PTR(-EINVAL);
2819 }
2820 } else {
2821 edid = ERR_PTR(-ENOENT);
d6f24d0f 2822 }
9cd300e0 2823 intel_connector->edid = edid;
f8779fda
JN		 2824
2825 /* prefer fixed mode from EDID if available */
2826 list_for_each_entry(scan, &connector->probed_modes, head) {
2827 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2828 fixed_mode = drm_mode_duplicate(dev, scan);
2829 break;
2830 }
2831 }
2832
2833 /* fallback to VBT if available for eDP */
2834 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2835 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2836 if (fixed_mode)
2837 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2838 }
f8779fda 2839
d6f24d0f
JB		 2840 ironlake_edp_panel_vdd_off(intel_dp, false);
2841 }
552fb0b7 2842
21d40d37 2843 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2844
1d508706 2845 if (is_edp(intel_dp)) {
dd06f90e 2846 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2847 intel_panel_setup_backlight(connector);
1d508706 2848 }
32f9d658 2849
f684960e
CW		 2850 intel_dp_add_properties(intel_dp, connector);
2851
a4fc5ed6
KP		 2852 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2853 * 0xd. Failure to do so will result in spurious interrupts being
2854 * generated on the port when a cable is not attached.
2855 */
2856 if (IS_G4X(dev) && !IS_GM45(dev)) {
2857 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2858 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2859 }
2860}
Linux kernel - Deliverables
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