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drm/i915: factor out GMCH panel fitting code and use for eDP v3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
a4fc5ed6 112static int
ea5b213a 113intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 114{
7183dc29 115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 116
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
119 case DP_LINK_BW_2_7:
120 break;
121 default:
122 max_link_bw = DP_LINK_BW_1_62;
123 break;
124 }
125 return max_link_bw;
126}
127
cd9dde44
AJ		 128/*
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
131 *
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
133 *
134 * 270000 * 1 * 8 / 10 == 216000
135 *
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
140 *
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
143 */
144
a4fc5ed6 145static int
c898261c 146intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 147{
cd9dde44 148 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 149}
150
fe27d53e
DA		 151static int
152intel_dp_max_data_rate(int max_link_clock, int max_lanes)
153{
154 return (max_link_clock * max_lanes * 8) / 10;
155}
156
a4fc5ed6
KP		 157static int
158intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
160{
df0e9248 161 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 166
dd06f90e
JN		 167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 169 return MODE_PANEL;
170
dd06f90e 171 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 172 return MODE_PANEL;
03afc4a2
DV		 173
174 target_clock = fixed_mode->clock;
7de56f43
ZY		 175 }
176
36008365
DV		 177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
c4867936 184 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 185
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
188
0af78a2b
DV		 189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
191
a4fc5ed6
KP		 192 return MODE_OK;
193}
194
195static uint32_t
196pack_aux(uint8_t *src, int src_bytes)
197{
198 int i;
199 uint32_t v = 0;
200
201 if (src_bytes > 4)
202 src_bytes = 4;
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 return v;
206}
207
208static void
209unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210{
211 int i;
212 if (dst_bytes > 4)
213 dst_bytes = 4;
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
216}
217
fb0f8fbf
KP		 218/* hrawclock is 1/4 the FSB frequency */
219static int
220intel_hrawclk(struct drm_device *dev)
221{
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 uint32_t clkcfg;
224
9473c8f4
VP		 225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
227 return 200;
228
fb0f8fbf
KP		 229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
231 case CLKCFG_FSB_400:
232 return 100;
233 case CLKCFG_FSB_533:
234 return 133;
235 case CLKCFG_FSB_667:
236 return 166;
237 case CLKCFG_FSB_800:
238 return 200;
239 case CLKCFG_FSB_1067:
240 return 266;
241 case CLKCFG_FSB_1333:
242 return 333;
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
246 return 400;
247 default:
248 return 133;
249 }
250}
251
ebf33b18
KP		 252static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
253{
30add22d 254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 255 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 256 u32 pp_stat_reg;
ebf33b18 257
453c5420
JB		 258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 260}
261
262static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
263{
30add22d 264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 265 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 266 u32 pp_ctrl_reg;
ebf33b18 267
453c5420
JB		 268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 270}
271
9b984dae
KP		 272static void
273intel_dp_check_edp(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 276 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 277 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 278
9b984dae
KP		 279 if (!is_edp(intel_dp))
280 return;
453c5420
JB		 281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
ebf33b18 285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
9b984dae
KP		 290 }
291}
292
9ee32fea
DV		 293static uint32_t
294intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 300 uint32_t status;
301 bool done;
302
ef04f00d 303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 304 if (has_aux_irq)
b90f5176
PZ		 305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
9ee32fea
DV		 307 else
308 done = wait_for_atomic(C, 10) == 0;
309 if (!done)
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
311 has_aux_irq);
312#undef C
313
314 return status;
315}
316
a4fc5ed6 317static int
ea5b213a 318intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
321{
174edf1f
PZ		 322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 324 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 326 uint32_t ch_data = ch_ctl + 4;
9ee32fea 327 int i, ret, recv_bytes;
a4fc5ed6 328 uint32_t status;
fb0f8fbf 329 uint32_t aux_clock_divider;
6b4e0a93 330 int try, precharge;
9ee32fea
DV		 331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
332
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
335 * deep sleep states.
336 */
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 338
9b984dae 339 intel_dp_check_edp(intel_dp);
a4fc5ed6 340 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 343 *
344 * Note that PCH attached eDP panels should use a 125MHz input
345 * clock divider.
a4fc5ed6 346 */
1c95822a 347 if (is_cpu_edp(intel_dp)) {
affa9354 348 if (HAS_DDI(dev))
b8fc2f6a
PZ		 349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 354 else
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 356 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider = 74;
359 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 360 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 361 } else {
5eb08b69 362 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 363 }
5eb08b69 364
6b4e0a93
DV		 365 if (IS_GEN6(dev))
366 precharge = 3;
367 else
368 precharge = 5;
369
11bee43e
JB		 370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
ef04f00d 372 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 373 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
374 break;
375 msleep(1);
376 }
377
378 if (try == 3) {
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
380 I915_READ(ch_ctl));
9ee32fea
DV		 381 ret = -EBUSY;
382 goto out;
4f7f7b7e
CW		 383 }
384
fb0f8fbf
KP		 385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 388 for (i = 0; i < send_bytes; i += 4)
389 I915_WRITE(ch_data + i,
390 pack_aux(send + i, send_bytes - i));
0206e353 391
fb0f8fbf 392 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 393 I915_WRITE(ch_ctl,
394 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 395 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 396 DP_AUX_CH_CTL_TIME_OUT_400us |
397 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
398 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
399 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
400 DP_AUX_CH_CTL_DONE |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR |
402 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 403
404 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 405
fb0f8fbf 406 /* Clear done status and any errors */
4f7f7b7e
CW		 407 I915_WRITE(ch_ctl,
408 status |
409 DP_AUX_CH_CTL_DONE |
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 412
413 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR))
415 continue;
4f7f7b7e 416 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 417 break;
418 }
419
a4fc5ed6 420 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 422 ret = -EBUSY;
423 goto out;
a4fc5ed6
KP		 424 }
425
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
428 */
a5b3da54 429 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 431 ret = -EIO;
432 goto out;
a5b3da54 433 }
1ae8c0a5
KP		 434
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
a5b3da54 437 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 439 ret = -ETIMEDOUT;
440 goto out;
a4fc5ed6
KP		 441 }
442
443 /* Unload any bytes sent back from the other side */
444 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 446 if (recv_bytes > recv_size)
447 recv_bytes = recv_size;
0206e353 448
4f7f7b7e
CW		 449 for (i = 0; i < recv_bytes; i += 4)
450 unpack_aux(I915_READ(ch_data + i),
451 recv + i, recv_bytes - i);
a4fc5ed6 452
9ee32fea
DV		 453 ret = recv_bytes;
454out:
455 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
456
457 return ret;
a4fc5ed6
KP		 458}
459
460/* Write data to the aux channel in native mode */
461static int
ea5b213a 462intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 463 uint16_t address, uint8_t *send, int send_bytes)
464{
465 int ret;
466 uint8_t msg[20];
467 int msg_bytes;
468 uint8_t ack;
469
9b984dae 470 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 471 if (send_bytes > 16)
472 return -1;
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
eebc863e 475 msg[2] = address & 0xff;
a4fc5ed6
KP		 476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
479 for (;;) {
ea5b213a 480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 481 if (ret < 0)
482 return ret;
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
484 break;
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
486 udelay(100);
487 else
a5b3da54 488 return -EIO;
a4fc5ed6
KP		 489 }
490 return send_bytes;
491}
492
493/* Write a single byte to the aux channel in native mode */
494static int
ea5b213a 495intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 496 uint16_t address, uint8_t byte)
497{
ea5b213a 498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 499}
500
501/* read bytes from a native aux channel */
502static int
ea5b213a 503intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 504 uint16_t address, uint8_t *recv, int recv_bytes)
505{
506 uint8_t msg[4];
507 int msg_bytes;
508 uint8_t reply[20];
509 int reply_bytes;
510 uint8_t ack;
511 int ret;
512
9b984dae 513 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
518
519 msg_bytes = 4;
520 reply_bytes = recv_bytes + 1;
521
522 for (;;) {
ea5b213a 523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 524 reply, reply_bytes);
a5b3da54
KP		 525 if (ret == 0)
526 return -EPROTO;
527 if (ret < 0)
a4fc5ed6
KP		 528 return ret;
529 ack = reply[0];
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
532 return ret - 1;
533 }
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
535 udelay(100);
536 else
a5b3da54 537 return -EIO;
a4fc5ed6
KP		 538 }
539}
540
541static int
ab2c0672
DA		 542intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 544{
ab2c0672 545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 546 struct intel_dp *intel_dp = container_of(adapter,
547 struct intel_dp,
548 adapter);
ab2c0672
DA		 549 uint16_t address = algo_data->address;
550 uint8_t msg[5];
551 uint8_t reply[2];
8316f337 552 unsigned retry;
ab2c0672
DA		 553 int msg_bytes;
554 int reply_bytes;
555 int ret;
556
9b984dae 557 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
561 else
562 msg[0] = AUX_I2C_WRITE << 4;
563
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 566
ab2c0672
DA		 567 msg[1] = address >> 8;
568 msg[2] = address;
569
570 switch (mode) {
571 case MODE_I2C_WRITE:
572 msg[3] = 0;
573 msg[4] = write_byte;
574 msg_bytes = 5;
575 reply_bytes = 1;
576 break;
577 case MODE_I2C_READ:
578 msg[3] = 0;
579 msg_bytes = 4;
580 reply_bytes = 2;
581 break;
582 default:
583 msg_bytes = 3;
584 reply_bytes = 1;
585 break;
586 }
587
8316f337
DF		 588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
590 msg, msg_bytes,
591 reply, reply_bytes);
ab2c0672 592 if (ret < 0) {
3ff99164 593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 594 return ret;
595 }
8316f337
DF		 596
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
601 */
602 break;
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
605 return -EREMOTEIO;
606 case AUX_NATIVE_REPLY_DEFER:
607 udelay(100);
608 continue;
609 default:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
611 reply[0]);
612 return -EREMOTEIO;
613 }
614
ab2c0672
DA		 615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
619 }
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
8316f337 622 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 623 return -EREMOTEIO;
624 case AUX_I2C_REPLY_DEFER:
8316f337 625 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 626 udelay(100);
627 break;
628 default:
8316f337 629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 630 return -EREMOTEIO;
631 }
632 }
8316f337
DF		 633
634 DRM_ERROR("too many retries, giving up\n");
635 return -EREMOTEIO;
a4fc5ed6
KP		 636}
637
638static int
ea5b213a 639intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 640 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 641{
0b5c541b
KP		 642 int ret;
643
d54e9d28 644 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 645 intel_dp->algo.running = false;
646 intel_dp->algo.address = 0;
647 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
648
0206e353 649 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 650 intel_dp->adapter.owner = THIS_MODULE;
651 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 652 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 653 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
654 intel_dp->adapter.algo_data = &intel_dp->algo;
655 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
656
0b5c541b
KP		 657 ironlake_edp_panel_vdd_on(intel_dp);
658 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 659 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 660 return ret;
a4fc5ed6
KP		 661}
662
c6bb3538
DV		 663static void
664intel_dp_set_clock(struct intel_encoder *encoder,
665 struct intel_crtc_config *pipe_config, int link_bw)
666{
667 struct drm_device *dev = encoder->base.dev;
668
669 if (IS_G4X(dev)) {
670 if (link_bw == DP_LINK_BW_1_62) {
671 pipe_config->dpll.p1 = 2;
672 pipe_config->dpll.p2 = 10;
673 pipe_config->dpll.n = 2;
674 pipe_config->dpll.m1 = 23;
675 pipe_config->dpll.m2 = 8;
676 } else {
677 pipe_config->dpll.p1 = 1;
678 pipe_config->dpll.p2 = 10;
679 pipe_config->dpll.n = 1;
680 pipe_config->dpll.m1 = 14;
681 pipe_config->dpll.m2 = 2;
682 }
683 pipe_config->clock_set = true;
684 } else if (IS_HASWELL(dev)) {
685 /* Haswell has special-purpose DP DDI clocks. */
686 } else if (HAS_PCH_SPLIT(dev)) {
687 if (link_bw == DP_LINK_BW_1_62) {
688 pipe_config->dpll.n = 1;
689 pipe_config->dpll.p1 = 2;
690 pipe_config->dpll.p2 = 10;
691 pipe_config->dpll.m1 = 12;
692 pipe_config->dpll.m2 = 9;
693 } else {
694 pipe_config->dpll.n = 2;
695 pipe_config->dpll.p1 = 1;
696 pipe_config->dpll.p2 = 10;
697 pipe_config->dpll.m1 = 14;
698 pipe_config->dpll.m2 = 8;
699 }
700 pipe_config->clock_set = true;
701 } else if (IS_VALLEYVIEW(dev)) {
702 /* FIXME: Need to figure out optimized DP clocks for vlv. */
703 }
704}
705
00c09d70 706bool
5bfe2ac0
DV		 707intel_dp_compute_config(struct intel_encoder *encoder,
708 struct intel_crtc_config *pipe_config)
a4fc5ed6 709{
5bfe2ac0 710 struct drm_device *dev = encoder->base.dev;
36008365 711 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV		 712 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
713 struct drm_display_mode *mode = &pipe_config->requested_mode;
714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2dd24552 715 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 716 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 717 int lane_count, clock;
397fe157 718 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 719 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 720 int bpp, mode_rate;
a4fc5ed6 721 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 722 int target_clock, link_avail, link_clock;
a4fc5ed6 723
5bfe2ac0
DV		 724 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
725 pipe_config->has_pch_encoder = true;
726
03afc4a2
DV		 727 pipe_config->has_dp_encoder = true;
728
dd06f90e
JN		 729 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
730 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
731 adjusted_mode);
2dd24552
JB		 732 if (!HAS_PCH_SPLIT(dev))
733 intel_gmch_panel_fitting(intel_crtc, pipe_config,
734 intel_connector->panel.fitting_mode);
735 else
736 intel_pch_panel_fitting(dev,
737 intel_connector->panel.fitting_mode,
738 mode, adjusted_mode);
0d3a1bee 739 }
36008365
DV		 740 /* We need to take the panel's fixed mode into account. */
741 target_clock = adjusted_mode->clock;
0d3a1bee 742
cb1793ce 743 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 744 return false;
745
083f9560
DV		 746 DRM_DEBUG_KMS("DP link computation with max lane count %i "
747 "max bw %02x pixel clock %iKHz\n",
71244653 748 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 749
36008365
DV		 750 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
751 * bpc in between. */
03afc4a2 752 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
36008365
DV		 753 for (; bpp >= 6*3; bpp -= 2*3) {
754 mode_rate = intel_dp_link_required(target_clock, bpp);
755
756 for (clock = 0; clock <= max_clock; clock++) {
757 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
758 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
759 link_avail = intel_dp_max_data_rate(link_clock,
760 lane_count);
761
762 if (mode_rate <= link_avail) {
763 goto found;
764 }
765 }
766 }
767 }
c4867936 768
36008365 769 return false;
3685a8f3 770
36008365 771found:
55bc60db
VS		 772 if (intel_dp->color_range_auto) {
773 /*
774 * See:
775 * CEA-861-E - 5.1 Default Encoding Parameters
776 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
777 */
18316c8c 778 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 779 intel_dp->color_range = DP_COLOR_RANGE_16_235;
780 else
781 intel_dp->color_range = 0;
782 }
783
3685a8f3 784 if (intel_dp->color_range)
50f3b016 785 pipe_config->limited_color_range = true;
3685a8f3 786
36008365
DV		 787 intel_dp->link_bw = bws[clock];
788 intel_dp->lane_count = lane_count;
789 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
df92b1e6 790 pipe_config->pixel_target_clock = target_clock;
fe27d53e 791
36008365
DV		 792 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
793 intel_dp->link_bw, intel_dp->lane_count,
794 adjusted_mode->clock, bpp);
795 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
796 mode_rate, link_avail);
797
03afc4a2
DV		 798 intel_link_compute_m_n(bpp, lane_count,
799 target_clock, adjusted_mode->clock,
800 &pipe_config->dp_m_n);
a4fc5ed6 801
57c21963
DV		 802 /*
803 * XXX: We have a strange regression where using the vbt edp bpp value
804 * for the link bw computation results in black screens, the panel only
805 * works when we do the computation at the usual 24bpp (but still
806 * requires us to use 18bpp). Until that's fully debugged, stay
807 * bug-for-bug compatible with the old code.
808 */
809 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
810 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
811 bpp, dev_priv->edp.bpp);
812 bpp = min_t(int, bpp, dev_priv->edp.bpp);
813 }
814 pipe_config->pipe_bpp = bpp;
815
c6bb3538
DV		 816 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
817
03afc4a2 818 return true;
a4fc5ed6
KP		 819}
820
247d89f6
PZ		 821void intel_dp_init_link_config(struct intel_dp *intel_dp)
822{
823 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
824 intel_dp->link_configuration[0] = intel_dp->link_bw;
825 intel_dp->link_configuration[1] = intel_dp->lane_count;
826 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
827 /*
828 * Check for DPCD version > 1.1 and enhanced framing support
829 */
830 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
831 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
832 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
833 }
834}
835
ea9b6006
DV		 836static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
837{
838 struct drm_device *dev = crtc->dev;
839 struct drm_i915_private *dev_priv = dev->dev_private;
840 u32 dpa_ctl;
841
842 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
843 dpa_ctl = I915_READ(DP_A);
844 dpa_ctl &= ~DP_PLL_FREQ_MASK;
845
846 if (clock < 200000) {
1ce17038
DV		 847 /* For a long time we've carried around a ILK-DevA w/a for the
848 * 160MHz clock. If we're really unlucky, it's still required.
849 */
850 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 851 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 852 } else {
853 dpa_ctl |= DP_PLL_FREQ_270MHZ;
854 }
1ce17038 855
ea9b6006
DV		 856 I915_WRITE(DP_A, dpa_ctl);
857
858 POSTING_READ(DP_A);
859 udelay(500);
860}
861
a4fc5ed6
KP		 862static void
863intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
864 struct drm_display_mode *adjusted_mode)
865{
e3421a18 866 struct drm_device *dev = encoder->dev;
417e822d 867 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 868 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 869 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
871
417e822d 872 /*
1a2eb460 873 * There are four kinds of DP registers:
417e822d
KP		 874 *
875 * IBX PCH
1a2eb460
KP		 876 * SNB CPU
877 * IVB CPU
417e822d
KP		 878 * CPT PCH
879 *
880 * IBX PCH and CPU are the same for almost everything,
881 * except that the CPU DP PLL is configured in this
882 * register
883 *
884 * CPT PCH is quite different, having many bits moved
885 * to the TRANS_DP_CTL register instead. That
886 * configuration happens (oddly) in ironlake_pch_enable
887 */
9c9e7927 888
417e822d
KP		 889 /* Preserve the BIOS-computed detected bit. This is
890 * supposed to be read-only.
891 */
892 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 893
417e822d 894 /* Handle DP bits in common between all three register formats */
417e822d 895 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 896
ea5b213a 897 switch (intel_dp->lane_count) {
a4fc5ed6 898 case 1:
ea5b213a 899 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 900 break;
901 case 2:
ea5b213a 902 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 903 break;
904 case 4:
ea5b213a 905 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 906 break;
907 }
e0dac65e
WF		 908 if (intel_dp->has_audio) {
909 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
910 pipe_name(intel_crtc->pipe));
ea5b213a 911 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 912 intel_write_eld(encoder, adjusted_mode);
913 }
247d89f6
PZ		 914
915 intel_dp_init_link_config(intel_dp);
a4fc5ed6 916
417e822d 917 /* Split out the IBX/CPU vs CPT settings */
32f9d658 918
19c03924 919 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 920 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
921 intel_dp->DP |= DP_SYNC_HS_HIGH;
922 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
923 intel_dp->DP |= DP_SYNC_VS_HIGH;
924 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
925
926 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
927 intel_dp->DP |= DP_ENHANCED_FRAMING;
928
929 intel_dp->DP |= intel_crtc->pipe << 29;
930
931 /* don't miss out required setting for eDP */
1a2eb460
KP		 932 if (adjusted_mode->clock < 200000)
933 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
934 else
935 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
936 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 937 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 938 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 939
940 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
941 intel_dp->DP |= DP_SYNC_HS_HIGH;
942 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
943 intel_dp->DP |= DP_SYNC_VS_HIGH;
944 intel_dp->DP |= DP_LINK_TRAIN_OFF;
945
946 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
947 intel_dp->DP |= DP_ENHANCED_FRAMING;
948
949 if (intel_crtc->pipe == 1)
950 intel_dp->DP |= DP_PIPEB_SELECT;
951
b2634017 952 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 953 /* don't miss out required setting for eDP */
417e822d
KP		 954 if (adjusted_mode->clock < 200000)
955 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
956 else
957 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
958 }
959 } else {
960 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 961 }
ea9b6006 962
5d66d5b6 963 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 964 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 965}
966
99ea7127
KP		 967#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
968#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
969
970#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
971#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
972
973#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
974#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
975
976static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
977 u32 mask,
978 u32 value)
bd943159 979{
30add22d 980 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 981 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 982 u32 pp_stat_reg, pp_ctrl_reg;
983
984 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
985 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 986
99ea7127 987 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 988 mask, value,
989 I915_READ(pp_stat_reg),
990 I915_READ(pp_ctrl_reg));
32ce697c 991
453c5420 992 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 993 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 994 I915_READ(pp_stat_reg),
995 I915_READ(pp_ctrl_reg));
32ce697c 996 }
99ea7127 997}
32ce697c 998
99ea7127
KP		 999static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1000{
1001 DRM_DEBUG_KMS("Wait for panel power on\n");
1002 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1003}
1004
99ea7127
KP		 1005static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1006{
1007 DRM_DEBUG_KMS("Wait for panel power off time\n");
1008 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1009}
1010
1011static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1012{
1013 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1014 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1015}
1016
1017
832dd3c1
KP		 1018/* Read the current pp_control value, unlocking the register if it
1019 * is locked
1020 */
1021
453c5420 1022static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1023{
453c5420
JB		 1024 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1025 struct drm_i915_private *dev_priv = dev->dev_private;
1026 u32 control;
1027 u32 pp_ctrl_reg;
1028
1029 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1030 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 1031
1032 control &= ~PANEL_UNLOCK_MASK;
1033 control |= PANEL_UNLOCK_REGS;
1034 return control;
bd943159
KP		 1035}
1036
82a4d9c0 1037void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1038{
30add22d 1039 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1040 struct drm_i915_private *dev_priv = dev->dev_private;
1041 u32 pp;
453c5420 1042 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1043
97af61f5
KP		 1044 if (!is_edp(intel_dp))
1045 return;
f01eca2e 1046 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1047
bd943159
KP		 1048 WARN(intel_dp->want_panel_vdd,
1049 "eDP VDD already requested on\n");
1050
1051 intel_dp->want_panel_vdd = true;
99ea7127 1052
bd943159
KP		 1053 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1054 DRM_DEBUG_KMS("eDP VDD already on\n");
1055 return;
1056 }
1057
99ea7127
KP		 1058 if (!ironlake_edp_have_panel_power(intel_dp))
1059 ironlake_wait_panel_power_cycle(intel_dp);
1060
453c5420 1061 pp = ironlake_get_pp_control(intel_dp);
5d613501 1062 pp |= EDP_FORCE_VDD;
ebf33b18 1063
453c5420
JB		 1064 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1065 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1066
1067 I915_WRITE(pp_ctrl_reg, pp);
1068 POSTING_READ(pp_ctrl_reg);
1069 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1070 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1071 /*
1072 * If the panel wasn't on, delay before accessing aux channel
1073 */
1074 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1075 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1076 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1077 }
5d613501
JB		 1078}
1079
bd943159 1080static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1081{
30add22d 1082 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 u32 pp;
453c5420 1085 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1086
a0e99e68
DV		 1087 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1088
bd943159 1089 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1090 pp = ironlake_get_pp_control(intel_dp);
bd943159 1091 pp &= ~EDP_FORCE_VDD;
bd943159 1092
453c5420
JB		 1093 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1094 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1095
1096 I915_WRITE(pp_ctrl_reg, pp);
1097 POSTING_READ(pp_ctrl_reg);
99ea7127 1098
453c5420
JB		 1099 /* Make sure sequencer is idle before allowing subsequent activity */
1100 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1101 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1102 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1103 }
1104}
5d613501 1105
bd943159
KP		 1106static void ironlake_panel_vdd_work(struct work_struct *__work)
1107{
1108 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1109 struct intel_dp, panel_vdd_work);
30add22d 1110 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1111
627f7675 1112 mutex_lock(&dev->mode_config.mutex);
bd943159 1113 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1114 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1115}
1116
82a4d9c0 1117void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1118{
97af61f5
KP		 1119 if (!is_edp(intel_dp))
1120 return;
5d613501 1121
bd943159
KP		 1122 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1123 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1124
bd943159
KP		 1125 intel_dp->want_panel_vdd = false;
1126
1127 if (sync) {
1128 ironlake_panel_vdd_off_sync(intel_dp);
1129 } else {
1130 /*
1131 * Queue the timer to fire a long
1132 * time from now (relative to the power down delay)
1133 * to keep the panel power up across a sequence of operations
1134 */
1135 schedule_delayed_work(&intel_dp->panel_vdd_work,
1136 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1137 }
5d613501
JB		 1138}
1139
82a4d9c0 1140void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1141{
30add22d 1142 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1143 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1144 u32 pp;
453c5420 1145 u32 pp_ctrl_reg;
9934c132 1146
97af61f5 1147 if (!is_edp(intel_dp))
bd943159 1148 return;
99ea7127
KP		 1149
1150 DRM_DEBUG_KMS("Turn eDP power on\n");
1151
1152 if (ironlake_edp_have_panel_power(intel_dp)) {
1153 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1154 return;
99ea7127 1155 }
9934c132 1156
99ea7127 1157 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1158
453c5420 1159 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1160 if (IS_GEN5(dev)) {
1161 /* ILK workaround: disable reset around power sequence */
1162 pp &= ~PANEL_POWER_RESET;
1163 I915_WRITE(PCH_PP_CONTROL, pp);
1164 POSTING_READ(PCH_PP_CONTROL);
1165 }
37c6c9b0 1166
1c0ae80a 1167 pp |= POWER_TARGET_ON;
99ea7127
KP		 1168 if (!IS_GEN5(dev))
1169 pp |= PANEL_POWER_RESET;
1170
453c5420
JB		 1171 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1172
1173 I915_WRITE(pp_ctrl_reg, pp);
1174 POSTING_READ(pp_ctrl_reg);
9934c132 1175
99ea7127 1176 ironlake_wait_panel_on(intel_dp);
9934c132 1177
05ce1a49
KP		 1178 if (IS_GEN5(dev)) {
1179 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1180 I915_WRITE(PCH_PP_CONTROL, pp);
1181 POSTING_READ(PCH_PP_CONTROL);
1182 }
9934c132
JB		 1183}
1184
82a4d9c0 1185void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1186{
30add22d 1187 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1188 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1189 u32 pp;
453c5420 1190 u32 pp_ctrl_reg;
9934c132 1191
97af61f5
KP		 1192 if (!is_edp(intel_dp))
1193 return;
37c6c9b0 1194
99ea7127 1195 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1196
6cb49835 1197 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1198
453c5420 1199 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1200 /* We need to switch off panel power _and_ force vdd, for otherwise some
1201 * panels get very unhappy and cease to work. */
1202 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1203
1204 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1205
1206 I915_WRITE(pp_ctrl_reg, pp);
1207 POSTING_READ(pp_ctrl_reg);
9934c132 1208
35a38556
DV		 1209 intel_dp->want_panel_vdd = false;
1210
99ea7127 1211 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1212}
1213
d6c50ff8 1214void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1215{
da63a9f2
PZ		 1216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1217 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1218 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1219 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1220 u32 pp;
453c5420 1221 u32 pp_ctrl_reg;
32f9d658 1222
f01eca2e
KP		 1223 if (!is_edp(intel_dp))
1224 return;
1225
28c97730 1226 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1227 /*
1228 * If we enable the backlight right away following a panel power
1229 * on, we may see slight flicker as the panel syncs with the eDP
1230 * link. So delay a bit to make sure the image is solid before
1231 * allowing it to appear.
1232 */
f01eca2e 1233 msleep(intel_dp->backlight_on_delay);
453c5420 1234 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1235 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1236
1237 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1238
1239 I915_WRITE(pp_ctrl_reg, pp);
1240 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1241
1242 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1243}
1244
d6c50ff8 1245void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1246{
30add22d 1247 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 u32 pp;
453c5420 1250 u32 pp_ctrl_reg;
32f9d658 1251
f01eca2e
KP		 1252 if (!is_edp(intel_dp))
1253 return;
1254
035aa3de
DV		 1255 intel_panel_disable_backlight(dev);
1256
28c97730 1257 DRM_DEBUG_KMS("\n");
453c5420 1258 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1259 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1260
1261 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1262
1263 I915_WRITE(pp_ctrl_reg, pp);
1264 POSTING_READ(pp_ctrl_reg);
f01eca2e 1265 msleep(intel_dp->backlight_off_delay);
32f9d658 1266}
a4fc5ed6 1267
2bd2ad64 1268static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1269{
da63a9f2
PZ		 1270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1271 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1272 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274 u32 dpa_ctl;
1275
2bd2ad64
DV		 1276 assert_pipe_disabled(dev_priv,
1277 to_intel_crtc(crtc)->pipe);
1278
d240f20f
JB		 1279 DRM_DEBUG_KMS("\n");
1280 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1281 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1282 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1283
1284 /* We don't adjust intel_dp->DP while tearing down the link, to
1285 * facilitate link retraining (e.g. after hotplug). Hence clear all
1286 * enable bits here to ensure that we don't enable too much. */
1287 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1288 intel_dp->DP |= DP_PLL_ENABLE;
1289 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1290 POSTING_READ(DP_A);
1291 udelay(200);
d240f20f
JB		 1292}
1293
2bd2ad64 1294static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1295{
da63a9f2
PZ		 1296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1298 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 u32 dpa_ctl;
1301
2bd2ad64
DV		 1302 assert_pipe_disabled(dev_priv,
1303 to_intel_crtc(crtc)->pipe);
1304
d240f20f 1305 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1306 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1307 "dp pll off, should be on\n");
1308 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1309
1310 /* We can't rely on the value tracked for the DP register in
1311 * intel_dp->DP because link_down must not change that (otherwise link
1312 * re-training will fail. */
298b0b39 1313 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1314 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1315 POSTING_READ(DP_A);
d240f20f
JB		 1316 udelay(200);
1317}
1318
c7ad3810 1319/* If the sink supports it, try to set the power state appropriately */
c19b0669 1320void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1321{
1322 int ret, i;
1323
1324 /* Should have a valid DPCD by this point */
1325 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1326 return;
1327
1328 if (mode != DRM_MODE_DPMS_ON) {
1329 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1330 DP_SET_POWER_D3);
1331 if (ret != 1)
1332 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1333 } else {
1334 /*
1335 * When turning on, we need to retry for 1ms to give the sink
1336 * time to wake up.
1337 */
1338 for (i = 0; i < 3; i++) {
1339 ret = intel_dp_aux_native_write_1(intel_dp,
1340 DP_SET_POWER,
1341 DP_SET_POWER_D0);
1342 if (ret == 1)
1343 break;
1344 msleep(1);
1345 }
1346 }
1347}
1348
19d8fe15
DV		 1349static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1350 enum pipe *pipe)
d240f20f 1351{
19d8fe15
DV		 1352 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1353 struct drm_device *dev = encoder->base.dev;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 u32 tmp = I915_READ(intel_dp->output_reg);
1356
1357 if (!(tmp & DP_PORT_EN))
1358 return false;
1359
5d66d5b6 1360 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1361 *pipe = PORT_TO_PIPE_CPT(tmp);
1362 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1363 *pipe = PORT_TO_PIPE(tmp);
1364 } else {
1365 u32 trans_sel;
1366 u32 trans_dp;
1367 int i;
1368
1369 switch (intel_dp->output_reg) {
1370 case PCH_DP_B:
1371 trans_sel = TRANS_DP_PORT_SEL_B;
1372 break;
1373 case PCH_DP_C:
1374 trans_sel = TRANS_DP_PORT_SEL_C;
1375 break;
1376 case PCH_DP_D:
1377 trans_sel = TRANS_DP_PORT_SEL_D;
1378 break;
1379 default:
1380 return true;
1381 }
1382
1383 for_each_pipe(i) {
1384 trans_dp = I915_READ(TRANS_DP_CTL(i));
1385 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1386 *pipe = i;
1387 return true;
1388 }
1389 }
19d8fe15 1390
4a0833ec
DV		 1391 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1392 intel_dp->output_reg);
1393 }
d240f20f 1394
2af8898b 1395 return true;
19d8fe15 1396}
d240f20f 1397
e8cb4558 1398static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1399{
e8cb4558 1400 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1401
1402 /* Make sure the panel is off before trying to change the mode. But also
1403 * ensure that we have vdd while we switch off the panel. */
1404 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1405 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1406 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1407 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1408
1409 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1410 if (!is_cpu_edp(intel_dp))
1411 intel_dp_link_down(intel_dp);
d240f20f
JB		 1412}
1413
2bd2ad64 1414static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1415{
2bd2ad64 1416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1417 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1418
3739850b
DV		 1419 if (is_cpu_edp(intel_dp)) {
1420 intel_dp_link_down(intel_dp);
b2634017
JB		 1421 if (!IS_VALLEYVIEW(dev))
1422 ironlake_edp_pll_off(intel_dp);
3739850b 1423 }
2bd2ad64
DV		 1424}
1425
e8cb4558 1426static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1427{
e8cb4558
DV		 1428 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1429 struct drm_device *dev = encoder->base.dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1432
0c33d8d7
DV		 1433 if (WARN_ON(dp_reg & DP_PORT_EN))
1434 return;
5d613501 1435
97af61f5 1436 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1437 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1438 intel_dp_start_link_train(intel_dp);
97af61f5 1439 ironlake_edp_panel_on(intel_dp);
bd943159 1440 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1441 intel_dp_complete_link_train(intel_dp);
f01eca2e 1442 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1443
1444 if (IS_VALLEYVIEW(dev)) {
1445 struct intel_digital_port *dport =
1446 enc_to_dig_port(&encoder->base);
1447 int channel = vlv_dport_to_channel(dport);
1448
1449 vlv_wait_port_ready(dev_priv, channel);
1450 }
d240f20f
JB		 1451}
1452
2bd2ad64 1453static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1454{
2bd2ad64 1455 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1456 struct drm_device *dev = encoder->base.dev;
89b667f8 1457 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1458
b2634017 1459 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1460 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1461
1462 if (IS_VALLEYVIEW(dev)) {
1463 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1464 struct intel_crtc *intel_crtc =
1465 to_intel_crtc(encoder->base.crtc);
1466 int port = vlv_dport_to_channel(dport);
1467 int pipe = intel_crtc->pipe;
1468 u32 val;
1469
1470 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1471
1472 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1473 val = 0;
1474 if (pipe)
1475 val |= (1<<21);
1476 else
1477 val &= ~(1<<21);
1478 val |= 0x001000c4;
1479 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1480
1481 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1482 0x00760018);
1483 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1484 0x00400888);
1485 }
1486}
1487
1488static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1489{
1490 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1491 struct drm_device *dev = encoder->base.dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 int port = vlv_dport_to_channel(dport);
1494
1495 if (!IS_VALLEYVIEW(dev))
1496 return;
1497
1498 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1499
1500 /* Program Tx lane resets to default */
1501 intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1502 DPIO_PCS_TX_LANE2_RESET |
1503 DPIO_PCS_TX_LANE1_RESET);
1504 intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1505 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1506 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1507 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1508 DPIO_PCS_CLK_SOFT_RESET);
1509
1510 /* Fix up inter-pair skew failure */
1511 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1512 intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1513 intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1514}
1515
1516/*
df0c237d
JB		 1517 * Native read with retry for link status and receiver capability reads for
1518 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1519 */
1520static bool
df0c237d
JB		 1521intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1522 uint8_t *recv, int recv_bytes)
a4fc5ed6 1523{
61da5fab
JB		 1524 int ret, i;
1525
df0c237d
JB		 1526 /*
1527 * Sinks are *supposed* to come up within 1ms from an off state,
1528 * but we're also supposed to retry 3 times per the spec.
1529 */
61da5fab 1530 for (i = 0; i < 3; i++) {
df0c237d
JB		 1531 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1532 recv_bytes);
1533 if (ret == recv_bytes)
61da5fab
JB		 1534 return true;
1535 msleep(1);
1536 }
a4fc5ed6 1537
61da5fab 1538 return false;
a4fc5ed6
KP		 1539}
1540
1541/*
1542 * Fetch AUX CH registers 0x202 - 0x207 which contain
1543 * link status information
1544 */
1545static bool
93f62dad 1546intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1547{
df0c237d
JB		 1548 return intel_dp_aux_native_read_retry(intel_dp,
1549 DP_LANE0_1_STATUS,
93f62dad 1550 link_status,
df0c237d 1551 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1552}
1553
a4fc5ed6
KP		 1554#if 0
1555static char *voltage_names[] = {
1556 "0.4V", "0.6V", "0.8V", "1.2V"
1557};
1558static char *pre_emph_names[] = {
1559 "0dB", "3.5dB", "6dB", "9.5dB"
1560};
1561static char *link_train_names[] = {
1562 "pattern 1", "pattern 2", "idle", "off"
1563};
1564#endif
1565
1566/*
1567 * These are source-specific values; current Intel hardware supports
1568 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1569 */
a4fc5ed6
KP		 1570
1571static uint8_t
1a2eb460 1572intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1573{
30add22d 1574 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1575
e2fa6fba
P		 1576 if (IS_VALLEYVIEW(dev))
1577 return DP_TRAIN_VOLTAGE_SWING_1200;
1578 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1a2eb460
KP		 1579 return DP_TRAIN_VOLTAGE_SWING_800;
1580 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1581 return DP_TRAIN_VOLTAGE_SWING_1200;
1582 else
1583 return DP_TRAIN_VOLTAGE_SWING_800;
1584}
1585
1586static uint8_t
1587intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1588{
30add22d 1589 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1590
22b8bf17 1591 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1592 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1593 case DP_TRAIN_VOLTAGE_SWING_400:
1594 return DP_TRAIN_PRE_EMPHASIS_9_5;
1595 case DP_TRAIN_VOLTAGE_SWING_600:
1596 return DP_TRAIN_PRE_EMPHASIS_6;
1597 case DP_TRAIN_VOLTAGE_SWING_800:
1598 return DP_TRAIN_PRE_EMPHASIS_3_5;
1599 case DP_TRAIN_VOLTAGE_SWING_1200:
1600 default:
1601 return DP_TRAIN_PRE_EMPHASIS_0;
1602 }
e2fa6fba
P		 1603 } else if (IS_VALLEYVIEW(dev)) {
1604 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1605 case DP_TRAIN_VOLTAGE_SWING_400:
1606 return DP_TRAIN_PRE_EMPHASIS_9_5;
1607 case DP_TRAIN_VOLTAGE_SWING_600:
1608 return DP_TRAIN_PRE_EMPHASIS_6;
1609 case DP_TRAIN_VOLTAGE_SWING_800:
1610 return DP_TRAIN_PRE_EMPHASIS_3_5;
1611 case DP_TRAIN_VOLTAGE_SWING_1200:
1612 default:
1613 return DP_TRAIN_PRE_EMPHASIS_0;
1614 }
1615 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1a2eb460
KP		 1616 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1617 case DP_TRAIN_VOLTAGE_SWING_400:
1618 return DP_TRAIN_PRE_EMPHASIS_6;
1619 case DP_TRAIN_VOLTAGE_SWING_600:
1620 case DP_TRAIN_VOLTAGE_SWING_800:
1621 return DP_TRAIN_PRE_EMPHASIS_3_5;
1622 default:
1623 return DP_TRAIN_PRE_EMPHASIS_0;
1624 }
1625 } else {
1626 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1627 case DP_TRAIN_VOLTAGE_SWING_400:
1628 return DP_TRAIN_PRE_EMPHASIS_6;
1629 case DP_TRAIN_VOLTAGE_SWING_600:
1630 return DP_TRAIN_PRE_EMPHASIS_6;
1631 case DP_TRAIN_VOLTAGE_SWING_800:
1632 return DP_TRAIN_PRE_EMPHASIS_3_5;
1633 case DP_TRAIN_VOLTAGE_SWING_1200:
1634 default:
1635 return DP_TRAIN_PRE_EMPHASIS_0;
1636 }
a4fc5ed6
KP		 1637 }
1638}
1639
e2fa6fba
P		 1640static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1641{
1642 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1645 unsigned long demph_reg_value, preemph_reg_value,
1646 uniqtranscale_reg_value;
1647 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1648 int port = vlv_dport_to_channel(dport);
e2fa6fba 1649
89b667f8
JB		 1650 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1651
e2fa6fba
P		 1652 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1653 case DP_TRAIN_PRE_EMPHASIS_0:
1654 preemph_reg_value = 0x0004000;
1655 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1656 case DP_TRAIN_VOLTAGE_SWING_400:
1657 demph_reg_value = 0x2B405555;
1658 uniqtranscale_reg_value = 0x552AB83A;
1659 break;
1660 case DP_TRAIN_VOLTAGE_SWING_600:
1661 demph_reg_value = 0x2B404040;
1662 uniqtranscale_reg_value = 0x5548B83A;
1663 break;
1664 case DP_TRAIN_VOLTAGE_SWING_800:
1665 demph_reg_value = 0x2B245555;
1666 uniqtranscale_reg_value = 0x5560B83A;
1667 break;
1668 case DP_TRAIN_VOLTAGE_SWING_1200:
1669 demph_reg_value = 0x2B405555;
1670 uniqtranscale_reg_value = 0x5598DA3A;
1671 break;
1672 default:
1673 return 0;
1674 }
1675 break;
1676 case DP_TRAIN_PRE_EMPHASIS_3_5:
1677 preemph_reg_value = 0x0002000;
1678 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1679 case DP_TRAIN_VOLTAGE_SWING_400:
1680 demph_reg_value = 0x2B404040;
1681 uniqtranscale_reg_value = 0x5552B83A;
1682 break;
1683 case DP_TRAIN_VOLTAGE_SWING_600:
1684 demph_reg_value = 0x2B404848;
1685 uniqtranscale_reg_value = 0x5580B83A;
1686 break;
1687 case DP_TRAIN_VOLTAGE_SWING_800:
1688 demph_reg_value = 0x2B404040;
1689 uniqtranscale_reg_value = 0x55ADDA3A;
1690 break;
1691 default:
1692 return 0;
1693 }
1694 break;
1695 case DP_TRAIN_PRE_EMPHASIS_6:
1696 preemph_reg_value = 0x0000000;
1697 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1698 case DP_TRAIN_VOLTAGE_SWING_400:
1699 demph_reg_value = 0x2B305555;
1700 uniqtranscale_reg_value = 0x5570B83A;
1701 break;
1702 case DP_TRAIN_VOLTAGE_SWING_600:
1703 demph_reg_value = 0x2B2B4040;
1704 uniqtranscale_reg_value = 0x55ADDA3A;
1705 break;
1706 default:
1707 return 0;
1708 }
1709 break;
1710 case DP_TRAIN_PRE_EMPHASIS_9_5:
1711 preemph_reg_value = 0x0006000;
1712 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1713 case DP_TRAIN_VOLTAGE_SWING_400:
1714 demph_reg_value = 0x1B405555;
1715 uniqtranscale_reg_value = 0x55ADDA3A;
1716 break;
1717 default:
1718 return 0;
1719 }
1720 break;
1721 default:
1722 return 0;
1723 }
1724
e2fa6fba
P		 1725 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1726 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1727 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1728 uniqtranscale_reg_value);
1729 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1730 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1731 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1732 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1733
1734 return 0;
1735}
1736
a4fc5ed6 1737static void
93f62dad 1738intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1739{
1740 uint8_t v = 0;
1741 uint8_t p = 0;
1742 int lane;
1a2eb460
KP		 1743 uint8_t voltage_max;
1744 uint8_t preemph_max;
a4fc5ed6 1745
33a34e4e 1746 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1747 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1748 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1749
1750 if (this_v > v)
1751 v = this_v;
1752 if (this_p > p)
1753 p = this_p;
1754 }
1755
1a2eb460 1756 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1757 if (v >= voltage_max)
1758 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1759
1a2eb460
KP		 1760 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1761 if (p >= preemph_max)
1762 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1763
1764 for (lane = 0; lane < 4; lane++)
33a34e4e 1765 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1766}
1767
1768static uint32_t
f0a3424e 1769intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1770{
3cf2efb1 1771 uint32_t signal_levels = 0;
a4fc5ed6 1772
3cf2efb1 1773 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1774 case DP_TRAIN_VOLTAGE_SWING_400:
1775 default:
1776 signal_levels |= DP_VOLTAGE_0_4;
1777 break;
1778 case DP_TRAIN_VOLTAGE_SWING_600:
1779 signal_levels |= DP_VOLTAGE_0_6;
1780 break;
1781 case DP_TRAIN_VOLTAGE_SWING_800:
1782 signal_levels |= DP_VOLTAGE_0_8;
1783 break;
1784 case DP_TRAIN_VOLTAGE_SWING_1200:
1785 signal_levels |= DP_VOLTAGE_1_2;
1786 break;
1787 }
3cf2efb1 1788 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1789 case DP_TRAIN_PRE_EMPHASIS_0:
1790 default:
1791 signal_levels |= DP_PRE_EMPHASIS_0;
1792 break;
1793 case DP_TRAIN_PRE_EMPHASIS_3_5:
1794 signal_levels |= DP_PRE_EMPHASIS_3_5;
1795 break;
1796 case DP_TRAIN_PRE_EMPHASIS_6:
1797 signal_levels |= DP_PRE_EMPHASIS_6;
1798 break;
1799 case DP_TRAIN_PRE_EMPHASIS_9_5:
1800 signal_levels |= DP_PRE_EMPHASIS_9_5;
1801 break;
1802 }
1803 return signal_levels;
1804}
1805
e3421a18
ZW		 1806/* Gen6's DP voltage swing and pre-emphasis control */
1807static uint32_t
1808intel_gen6_edp_signal_levels(uint8_t train_set)
1809{
3c5a62b5
YL		 1810 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1811 DP_TRAIN_PRE_EMPHASIS_MASK);
1812 switch (signal_levels) {
e3421a18 1813 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1814 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1815 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1816 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1817 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1818 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1819 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1820 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1821 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1822 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1823 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1824 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1825 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1826 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1827 default:
3c5a62b5
YL		 1828 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1829 "0x%x\n", signal_levels);
1830 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1831 }
1832}
1833
1a2eb460
KP		 1834/* Gen7's DP voltage swing and pre-emphasis control */
1835static uint32_t
1836intel_gen7_edp_signal_levels(uint8_t train_set)
1837{
1838 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1839 DP_TRAIN_PRE_EMPHASIS_MASK);
1840 switch (signal_levels) {
1841 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1842 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1843 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1844 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1845 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1846 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1847
1848 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1849 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1850 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1851 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1852
1853 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1854 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1855 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1856 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1857
1858 default:
1859 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1860 "0x%x\n", signal_levels);
1861 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1862 }
1863}
1864
d6c0d722
PZ		 1865/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1866static uint32_t
f0a3424e 1867intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1868{
d6c0d722
PZ		 1869 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1870 DP_TRAIN_PRE_EMPHASIS_MASK);
1871 switch (signal_levels) {
1872 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1873 return DDI_BUF_EMP_400MV_0DB_HSW;
1874 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1875 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1876 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1877 return DDI_BUF_EMP_400MV_6DB_HSW;
1878 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1879 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1880
d6c0d722
PZ		 1881 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1882 return DDI_BUF_EMP_600MV_0DB_HSW;
1883 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1884 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1885 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1886 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1887
d6c0d722
PZ		 1888 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1889 return DDI_BUF_EMP_800MV_0DB_HSW;
1890 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1891 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1892 default:
1893 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1894 "0x%x\n", signal_levels);
1895 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1896 }
a4fc5ed6
KP		 1897}
1898
f0a3424e
PZ		 1899/* Properly updates "DP" with the correct signal levels. */
1900static void
1901intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1902{
1903 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1904 struct drm_device *dev = intel_dig_port->base.base.dev;
1905 uint32_t signal_levels, mask;
1906 uint8_t train_set = intel_dp->train_set[0];
1907
22b8bf17 1908 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1909 signal_levels = intel_hsw_signal_levels(train_set);
1910 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 1911 } else if (IS_VALLEYVIEW(dev)) {
1912 signal_levels = intel_vlv_signal_levels(intel_dp);
1913 mask = 0;
1914 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
f0a3424e
PZ		 1915 signal_levels = intel_gen7_edp_signal_levels(train_set);
1916 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1917 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1918 signal_levels = intel_gen6_edp_signal_levels(train_set);
1919 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1920 } else {
1921 signal_levels = intel_gen4_signal_levels(train_set);
1922 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1923 }
1924
1925 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1926
1927 *DP = (*DP & ~mask) | signal_levels;
1928}
1929
a4fc5ed6 1930static bool
ea5b213a 1931intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1932 uint32_t dp_reg_value,
58e10eb9 1933 uint8_t dp_train_pat)
a4fc5ed6 1934{
174edf1f
PZ		 1935 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1936 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1937 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1938 enum port port = intel_dig_port->port;
a4fc5ed6 1939 int ret;
d6c0d722 1940 uint32_t temp;
a4fc5ed6 1941
22b8bf17 1942 if (HAS_DDI(dev)) {
174edf1f 1943 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1944
1945 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1946 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1947 else
1948 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1949
1950 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1951 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1952 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1953
10aa17c8
PZ		 1954 if (port != PORT_A) {
1955 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1956 I915_WRITE(DP_TP_CTL(port), temp);
1957
1958 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1959 DP_TP_STATUS_IDLE_DONE), 1))
1960 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1961
1962 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1963 }
d6c0d722 1964
d6c0d722
PZ		 1965 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1966
1967 break;
1968 case DP_TRAINING_PATTERN_1:
1969 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1970 break;
1971 case DP_TRAINING_PATTERN_2:
1972 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1973 break;
1974 case DP_TRAINING_PATTERN_3:
1975 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1976 break;
1977 }
174edf1f 1978 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1979
1980 } else if (HAS_PCH_CPT(dev) &&
1981 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1982 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1983
1984 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1985 case DP_TRAINING_PATTERN_DISABLE:
1986 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1987 break;
1988 case DP_TRAINING_PATTERN_1:
1989 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1990 break;
1991 case DP_TRAINING_PATTERN_2:
1992 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1993 break;
1994 case DP_TRAINING_PATTERN_3:
1995 DRM_ERROR("DP training pattern 3 not supported\n");
1996 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1997 break;
1998 }
1999
2000 } else {
2001 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2002
2003 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2004 case DP_TRAINING_PATTERN_DISABLE:
2005 dp_reg_value |= DP_LINK_TRAIN_OFF;
2006 break;
2007 case DP_TRAINING_PATTERN_1:
2008 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2009 break;
2010 case DP_TRAINING_PATTERN_2:
2011 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2012 break;
2013 case DP_TRAINING_PATTERN_3:
2014 DRM_ERROR("DP training pattern 3 not supported\n");
2015 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2016 break;
2017 }
2018 }
2019
ea5b213a
CW		 2020 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2021 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2022
ea5b213a 2023 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2024 DP_TRAINING_PATTERN_SET,
2025 dp_train_pat);
2026
47ea7542
PZ		 2027 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2028 DP_TRAINING_PATTERN_DISABLE) {
2029 ret = intel_dp_aux_native_write(intel_dp,
2030 DP_TRAINING_LANE0_SET,
2031 intel_dp->train_set,
2032 intel_dp->lane_count);
2033 if (ret != intel_dp->lane_count)
2034 return false;
2035 }
a4fc5ed6
KP		 2036
2037 return true;
2038}
2039
33a34e4e 2040/* Enable corresponding port and start training pattern 1 */
c19b0669 2041void
33a34e4e 2042intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2043{
da63a9f2 2044 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2045 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2046 int i;
2047 uint8_t voltage;
2048 bool clock_recovery = false;
cdb0e95b 2049 int voltage_tries, loop_tries;
ea5b213a 2050 uint32_t DP = intel_dp->DP;
a4fc5ed6 2051
affa9354 2052 if (HAS_DDI(dev))
c19b0669
PZ		 2053 intel_ddi_prepare_link_retrain(encoder);
2054
3cf2efb1
CW		 2055 /* Write the link configuration data */
2056 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2057 intel_dp->link_configuration,
2058 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2059
2060 DP |= DP_PORT_EN;
1a2eb460 2061
33a34e4e 2062 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2063 voltage = 0xff;
cdb0e95b
KP		 2064 voltage_tries = 0;
2065 loop_tries = 0;
a4fc5ed6
KP		 2066 clock_recovery = false;
2067 for (;;) {
33a34e4e 2068 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2069 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2070
2071 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2072
a7c9655f 2073 /* Set training pattern 1 */
47ea7542 2074 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2075 DP_TRAINING_PATTERN_1 |
2076 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2077 break;
a4fc5ed6 2078
a7c9655f 2079 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2080 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2081 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2082 break;
93f62dad 2083 }
a4fc5ed6 2084
01916270 2085 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2086 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2087 clock_recovery = true;
2088 break;
2089 }
2090
2091 /* Check to see if we've tried the max voltage */
2092 for (i = 0; i < intel_dp->lane_count; i++)
2093 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2094 break;
3b4f819d 2095 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2096 ++loop_tries;
2097 if (loop_tries == 5) {
cdb0e95b
KP		 2098 DRM_DEBUG_KMS("too many full retries, give up\n");
2099 break;
2100 }
2101 memset(intel_dp->train_set, 0, 4);
2102 voltage_tries = 0;
2103 continue;
2104 }
a4fc5ed6 2105
3cf2efb1 2106 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2107 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2108 ++voltage_tries;
b06fbda3
DV		 2109 if (voltage_tries == 5) {
2110 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2111 break;
2112 }
2113 } else
2114 voltage_tries = 0;
2115 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2116
3cf2efb1 2117 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2118 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2119 }
2120
33a34e4e
JB		 2121 intel_dp->DP = DP;
2122}
2123
c19b0669 2124void
33a34e4e
JB		 2125intel_dp_complete_link_train(struct intel_dp *intel_dp)
2126{
33a34e4e 2127 bool channel_eq = false;
37f80975 2128 int tries, cr_tries;
33a34e4e
JB		 2129 uint32_t DP = intel_dp->DP;
2130
a4fc5ed6
KP		 2131 /* channel equalization */
2132 tries = 0;
37f80975 2133 cr_tries = 0;
a4fc5ed6
KP		 2134 channel_eq = false;
2135 for (;;) {
93f62dad 2136 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2137
37f80975
JB		 2138 if (cr_tries > 5) {
2139 DRM_ERROR("failed to train DP, aborting\n");
2140 intel_dp_link_down(intel_dp);
2141 break;
2142 }
2143
f0a3424e 2144 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2145
a4fc5ed6 2146 /* channel eq pattern */
47ea7542 2147 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2148 DP_TRAINING_PATTERN_2 |
2149 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2150 break;
2151
a7c9655f 2152 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2153 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2154 break;
a4fc5ed6 2155
37f80975 2156 /* Make sure clock is still ok */
01916270 2157 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2158 intel_dp_start_link_train(intel_dp);
2159 cr_tries++;
2160 continue;
2161 }
2162
1ffdff13 2163 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2164 channel_eq = true;
2165 break;
2166 }
a4fc5ed6 2167
37f80975
JB		 2168 /* Try 5 times, then try clock recovery if that fails */
2169 if (tries > 5) {
2170 intel_dp_link_down(intel_dp);
2171 intel_dp_start_link_train(intel_dp);
2172 tries = 0;
2173 cr_tries++;
2174 continue;
2175 }
a4fc5ed6 2176
3cf2efb1 2177 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2178 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2179 ++tries;
869184a6 2180 }
3cf2efb1 2181
d6c0d722
PZ		 2182 if (channel_eq)
2183 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2184
47ea7542 2185 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2186}
2187
2188static void
ea5b213a 2189intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2190{
da63a9f2
PZ		 2191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2192 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2193 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2194 struct intel_crtc *intel_crtc =
2195 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2196 uint32_t DP = intel_dp->DP;
a4fc5ed6 2197
c19b0669
PZ		 2198 /*
2199 * DDI code has a strict mode set sequence and we should try to respect
2200 * it, otherwise we might hang the machine in many different ways. So we
2201 * really should be disabling the port only on a complete crtc_disable
2202 * sequence. This function is just called under two conditions on DDI
2203 * code:
2204 * - Link train failed while doing crtc_enable, and on this case we
2205 * really should respect the mode set sequence and wait for a
2206 * crtc_disable.
2207 * - Someone turned the monitor off and intel_dp_check_link_status
2208 * called us. We don't need to disable the whole port on this case, so
2209 * when someone turns the monitor on again,
2210 * intel_ddi_prepare_link_retrain will take care of redoing the link
2211 * train.
2212 */
affa9354 2213 if (HAS_DDI(dev))
c19b0669
PZ		 2214 return;
2215
0c33d8d7 2216 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2217 return;
2218
28c97730 2219 DRM_DEBUG_KMS("\n");
32f9d658 2220
1a2eb460 2221 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2222 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2223 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2224 } else {
2225 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2226 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2227 }
fe255d00 2228 POSTING_READ(intel_dp->output_reg);
5eb08b69 2229
ab527efc
DV		 2230 /* We don't really know why we're doing this */
2231 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2232
493a7081 2233 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2234 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2235 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2236
5bddd17f
EA		 2237 /* Hardware workaround: leaving our transcoder select
2238 * set to transcoder B while it's off will prevent the
2239 * corresponding HDMI output on transcoder A.
2240 *
2241 * Combine this with another hardware workaround:
2242 * transcoder select bit can only be cleared while the
2243 * port is enabled.
2244 */
2245 DP &= ~DP_PIPEB_SELECT;
2246 I915_WRITE(intel_dp->output_reg, DP);
2247
2248 /* Changes to enable or select take place the vblank
2249 * after being written.
2250 */
ff50afe9
DV		 2251 if (WARN_ON(crtc == NULL)) {
2252 /* We should never try to disable a port without a crtc
2253 * attached. For paranoia keep the code around for a
2254 * bit. */
31acbcc4
CW		 2255 POSTING_READ(intel_dp->output_reg);
2256 msleep(50);
2257 } else
ab527efc 2258 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2259 }
2260
832afda6 2261 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2262 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2263 POSTING_READ(intel_dp->output_reg);
f01eca2e 2264 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2265}
2266
26d61aad
KP		 2267static bool
2268intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2269{
577c7a50
DL		 2270 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2271
92fd8fd1 2272 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2273 sizeof(intel_dp->dpcd)) == 0)
2274 return false; /* aux transfer failed */
92fd8fd1 2275
577c7a50
DL		 2276 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2277 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2278 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2279
edb39244
AJ		 2280 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2281 return false; /* DPCD not present */
2282
2283 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2284 DP_DWN_STRM_PORT_PRESENT))
2285 return true; /* native DP sink */
2286
2287 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2288 return true; /* no per-port downstream info */
2289
2290 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2291 intel_dp->downstream_ports,
2292 DP_MAX_DOWNSTREAM_PORTS) == 0)
2293 return false; /* downstream port status fetch failed */
2294
2295 return true;
92fd8fd1
KP		 2296}
2297
0d198328
AJ		 2298static void
2299intel_dp_probe_oui(struct intel_dp *intel_dp)
2300{
2301 u8 buf[3];
2302
2303 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2304 return;
2305
351cfc34
DV		 2306 ironlake_edp_panel_vdd_on(intel_dp);
2307
0d198328
AJ		 2308 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2309 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2310 buf[0], buf[1], buf[2]);
2311
2312 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2313 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2314 buf[0], buf[1], buf[2]);
351cfc34
DV		 2315
2316 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2317}
2318
a60f0e38
JB		 2319static bool
2320intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2321{
2322 int ret;
2323
2324 ret = intel_dp_aux_native_read_retry(intel_dp,
2325 DP_DEVICE_SERVICE_IRQ_VECTOR,
2326 sink_irq_vector, 1);
2327 if (!ret)
2328 return false;
2329
2330 return true;
2331}
2332
2333static void
2334intel_dp_handle_test_request(struct intel_dp *intel_dp)
2335{
2336 /* NAK by default */
9324cf7f 2337 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2338}
2339
a4fc5ed6
KP		 2340/*
2341 * According to DP spec
2342 * 5.1.2:
2343 * 1. Read DPCD
2344 * 2. Configure link according to Receiver Capabilities
2345 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2346 * 4. Check link status on receipt of hot-plug interrupt
2347 */
2348
00c09d70 2349void
ea5b213a 2350intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2351{
da63a9f2 2352 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2353 u8 sink_irq_vector;
93f62dad 2354 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2355
da63a9f2 2356 if (!intel_encoder->connectors_active)
d2b996ac 2357 return;
59cd09e1 2358
da63a9f2 2359 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2360 return;
2361
92fd8fd1 2362 /* Try to read receiver status if the link appears to be up */
93f62dad 2363 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2364 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2365 return;
2366 }
2367
92fd8fd1 2368 /* Now read the DPCD to see if it's actually running */
26d61aad 2369 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2370 intel_dp_link_down(intel_dp);
2371 return;
2372 }
2373
a60f0e38
JB		 2374 /* Try to read the source of the interrupt */
2375 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2376 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2377 /* Clear interrupt source */
2378 intel_dp_aux_native_write_1(intel_dp,
2379 DP_DEVICE_SERVICE_IRQ_VECTOR,
2380 sink_irq_vector);
2381
2382 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2383 intel_dp_handle_test_request(intel_dp);
2384 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2385 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2386 }
2387
1ffdff13 2388 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2389 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2390 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2391 intel_dp_start_link_train(intel_dp);
2392 intel_dp_complete_link_train(intel_dp);
2393 }
a4fc5ed6 2394}
a4fc5ed6 2395
caf9ab24 2396/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2397static enum drm_connector_status
26d61aad 2398intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2399{
caf9ab24
AJ		 2400 uint8_t *dpcd = intel_dp->dpcd;
2401 bool hpd;
2402 uint8_t type;
2403
2404 if (!intel_dp_get_dpcd(intel_dp))
2405 return connector_status_disconnected;
2406
2407 /* if there's no downstream port, we're done */
2408 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2409 return connector_status_connected;
caf9ab24
AJ		 2410
2411 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2412 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2413 if (hpd) {
23235177 2414 uint8_t reg;
caf9ab24 2415 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2416 &reg, 1))
caf9ab24 2417 return connector_status_unknown;
23235177
AJ		 2418 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2419 : connector_status_disconnected;
caf9ab24
AJ		 2420 }
2421
2422 /* If no HPD, poke DDC gently */
2423 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2424 return connector_status_connected;
caf9ab24
AJ		 2425
2426 /* Well we tried, say unknown for unreliable port types */
2427 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2428 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2429 return connector_status_unknown;
2430
2431 /* Anything else is out of spec, warn and ignore */
2432 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2433 return connector_status_disconnected;
71ba9000
AJ		 2434}
2435
5eb08b69 2436static enum drm_connector_status
a9756bb5 2437ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2438{
30add22d 2439 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2440 struct drm_i915_private *dev_priv = dev->dev_private;
2441 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2442 enum drm_connector_status status;
2443
fe16d949
CW		 2444 /* Can't disconnect eDP, but you can close the lid... */
2445 if (is_edp(intel_dp)) {
30add22d 2446 status = intel_panel_detect(dev);
fe16d949
CW		 2447 if (status == connector_status_unknown)
2448 status = connector_status_connected;
2449 return status;
2450 }
01cb9ea6 2451
1b469639
DL		 2452 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2453 return connector_status_disconnected;
2454
26d61aad 2455 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2456}
2457
a4fc5ed6 2458static enum drm_connector_status
a9756bb5 2459g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2460{
30add22d 2461 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2462 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2464 uint32_t bit;
5eb08b69 2465
35aad75f
JB		 2466 /* Can't disconnect eDP, but you can close the lid... */
2467 if (is_edp(intel_dp)) {
2468 enum drm_connector_status status;
2469
2470 status = intel_panel_detect(dev);
2471 if (status == connector_status_unknown)
2472 status = connector_status_connected;
2473 return status;
2474 }
2475
34f2be46
VS		 2476 switch (intel_dig_port->port) {
2477 case PORT_B:
26739f12 2478 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2479 break;
34f2be46 2480 case PORT_C:
26739f12 2481 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2482 break;
34f2be46 2483 case PORT_D:
26739f12 2484 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2485 break;
2486 default:
2487 return connector_status_unknown;
2488 }
2489
10f76a38 2490 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2491 return connector_status_disconnected;
2492
26d61aad 2493 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2494}
2495
8c241fef
KP		 2496static struct edid *
2497intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2498{
9cd300e0 2499 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2500
9cd300e0
JN		 2501 /* use cached edid if we have one */
2502 if (intel_connector->edid) {
2503 struct edid *edid;
2504 int size;
2505
2506 /* invalid edid */
2507 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2508 return NULL;
2509
9cd300e0 2510 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2511 edid = kmalloc(size, GFP_KERNEL);
2512 if (!edid)
2513 return NULL;
2514
9cd300e0 2515 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2516 return edid;
2517 }
8c241fef 2518
9cd300e0 2519 return drm_get_edid(connector, adapter);
8c241fef
KP		 2520}
2521
2522static int
2523intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2524{
9cd300e0 2525 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2526
9cd300e0
JN		 2527 /* use cached edid if we have one */
2528 if (intel_connector->edid) {
2529 /* invalid edid */
2530 if (IS_ERR(intel_connector->edid))
2531 return 0;
2532
2533 return intel_connector_update_modes(connector,
2534 intel_connector->edid);
d6f24d0f
JB		 2535 }
2536
9cd300e0 2537 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2538}
2539
a9756bb5
ZW		 2540static enum drm_connector_status
2541intel_dp_detect(struct drm_connector *connector, bool force)
2542{
2543 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2544 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2545 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2546 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2547 enum drm_connector_status status;
2548 struct edid *edid = NULL;
2549
2550 intel_dp->has_audio = false;
2551
2552 if (HAS_PCH_SPLIT(dev))
2553 status = ironlake_dp_detect(intel_dp);
2554 else
2555 status = g4x_dp_detect(intel_dp);
1b9be9d0 2556
a9756bb5
ZW		 2557 if (status != connector_status_connected)
2558 return status;
2559
0d198328
AJ		 2560 intel_dp_probe_oui(intel_dp);
2561
c3e5f67b
DV		 2562 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2563 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2564 } else {
8c241fef 2565 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2566 if (edid) {
2567 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2568 kfree(edid);
2569 }
a9756bb5
ZW		 2570 }
2571
d63885da
PZ		 2572 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2573 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2574 return connector_status_connected;
a4fc5ed6
KP		 2575}
2576
2577static int intel_dp_get_modes(struct drm_connector *connector)
2578{
df0e9248 2579 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2580 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2581 struct drm_device *dev = connector->dev;
32f9d658 2582 int ret;
a4fc5ed6
KP		 2583
2584 /* We should parse the EDID data and find out if it has an audio sink
2585 */
2586
8c241fef 2587 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2588 if (ret)
32f9d658
ZW		 2589 return ret;
2590
f8779fda 2591 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2592 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2593 struct drm_display_mode *mode;
dd06f90e
JN		 2594 mode = drm_mode_duplicate(dev,
2595 intel_connector->panel.fixed_mode);
f8779fda 2596 if (mode) {
32f9d658
ZW		 2597 drm_mode_probed_add(connector, mode);
2598 return 1;
2599 }
2600 }
2601 return 0;
a4fc5ed6
KP		 2602}
2603
1aad7ac0
CW		 2604static bool
2605intel_dp_detect_audio(struct drm_connector *connector)
2606{
2607 struct intel_dp *intel_dp = intel_attached_dp(connector);
2608 struct edid *edid;
2609 bool has_audio = false;
2610
8c241fef 2611 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2612 if (edid) {
2613 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2614 kfree(edid);
2615 }
2616
2617 return has_audio;
2618}
2619
f684960e
CW		 2620static int
2621intel_dp_set_property(struct drm_connector *connector,
2622 struct drm_property *property,
2623 uint64_t val)
2624{
e953fd7b 2625 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2626 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2627 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2628 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2629 int ret;
2630
662595df 2631 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2632 if (ret)
2633 return ret;
2634
3f43c48d 2635 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2636 int i = val;
2637 bool has_audio;
2638
2639 if (i == intel_dp->force_audio)
f684960e
CW		 2640 return 0;
2641
1aad7ac0 2642 intel_dp->force_audio = i;
f684960e 2643
c3e5f67b 2644 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2645 has_audio = intel_dp_detect_audio(connector);
2646 else
c3e5f67b 2647 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2648
2649 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2650 return 0;
2651
1aad7ac0 2652 intel_dp->has_audio = has_audio;
f684960e
CW		 2653 goto done;
2654 }
2655
e953fd7b 2656 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2657 switch (val) {
2658 case INTEL_BROADCAST_RGB_AUTO:
2659 intel_dp->color_range_auto = true;
2660 break;
2661 case INTEL_BROADCAST_RGB_FULL:
2662 intel_dp->color_range_auto = false;
2663 intel_dp->color_range = 0;
2664 break;
2665 case INTEL_BROADCAST_RGB_LIMITED:
2666 intel_dp->color_range_auto = false;
2667 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
e953fd7b
CW		 2672 goto done;
2673 }
2674
53b41837
YN		 2675 if (is_edp(intel_dp) &&
2676 property == connector->dev->mode_config.scaling_mode_property) {
2677 if (val == DRM_MODE_SCALE_NONE) {
2678 DRM_DEBUG_KMS("no scaling not supported\n");
2679 return -EINVAL;
2680 }
2681
2682 if (intel_connector->panel.fitting_mode == val) {
2683 /* the eDP scaling property is not changed */
2684 return 0;
2685 }
2686 intel_connector->panel.fitting_mode = val;
2687
2688 goto done;
2689 }
2690
f684960e
CW		 2691 return -EINVAL;
2692
2693done:
c0c36b94
CW		 2694 if (intel_encoder->base.crtc)
2695 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2696
2697 return 0;
2698}
2699
a4fc5ed6 2700static void
0206e353 2701intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2702{
be3cd5e3 2703 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2704 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2705
9cd300e0
JN		 2706 if (!IS_ERR_OR_NULL(intel_connector->edid))
2707 kfree(intel_connector->edid);
2708
dc652f90 2709 if (is_edp(intel_dp))
1d508706 2710 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2711
a4fc5ed6
KP		 2712 drm_sysfs_connector_remove(connector);
2713 drm_connector_cleanup(connector);
55f78c43 2714 kfree(connector);
a4fc5ed6
KP		 2715}
2716
00c09d70 2717void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2718{
da63a9f2
PZ		 2719 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2720 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2721
2722 i2c_del_adapter(&intel_dp->adapter);
2723 drm_encoder_cleanup(encoder);
bd943159
KP		 2724 if (is_edp(intel_dp)) {
2725 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2726 ironlake_panel_vdd_off_sync(intel_dp);
2727 }
da63a9f2 2728 kfree(intel_dig_port);
24d05927
DV		 2729}
2730
a4fc5ed6 2731static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2732 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2733};
2734
2735static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2736 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2737 .detect = intel_dp_detect,
2738 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2739 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2740 .destroy = intel_dp_destroy,
2741};
2742
2743static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2744 .get_modes = intel_dp_get_modes,
2745 .mode_valid = intel_dp_mode_valid,
df0e9248 2746 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2747};
2748
a4fc5ed6 2749static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2750 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2751};
2752
995b6762 2753static void
21d40d37 2754intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2755{
fa90ecef 2756 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2757
885a5014 2758 intel_dp_check_link_status(intel_dp);
c8110e52 2759}
6207937d 2760
e3421a18
ZW		 2761/* Return which DP Port should be selected for Transcoder DP control */
2762int
0206e353 2763intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2764{
2765 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2766 struct intel_encoder *intel_encoder;
2767 struct intel_dp *intel_dp;
e3421a18 2768
fa90ecef
PZ		 2769 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2770 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2771
fa90ecef
PZ		 2772 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2773 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2774 return intel_dp->output_reg;
e3421a18 2775 }
ea5b213a 2776
e3421a18
ZW		 2777 return -1;
2778}
2779
36e83a18 2780/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2781bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2782{
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct child_device_config *p_child;
2785 int i;
2786
2787 if (!dev_priv->child_dev_num)
2788 return false;
2789
2790 for (i = 0; i < dev_priv->child_dev_num; i++) {
2791 p_child = dev_priv->child_dev + i;
2792
2793 if (p_child->dvo_port == PORT_IDPD &&
2794 p_child->device_type == DEVICE_TYPE_eDP)
2795 return true;
2796 }
2797 return false;
2798}
2799
f684960e
CW		 2800static void
2801intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2802{
53b41837
YN		 2803 struct intel_connector *intel_connector = to_intel_connector(connector);
2804
3f43c48d 2805 intel_attach_force_audio_property(connector);
e953fd7b 2806 intel_attach_broadcast_rgb_property(connector);
55bc60db 2807 intel_dp->color_range_auto = true;
53b41837
YN		 2808
2809 if (is_edp(intel_dp)) {
2810 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2811 drm_object_attach_property(
2812 &connector->base,
53b41837 2813 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2814 DRM_MODE_SCALE_ASPECT);
2815 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2816 }
f684960e
CW		 2817}
2818
67a54566
DV		 2819static void
2820intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2821 struct intel_dp *intel_dp,
2822 struct edp_power_seq *out)
67a54566
DV		 2823{
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 struct edp_power_seq cur, vbt, spec, final;
2826 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2827 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2828
2829 if (HAS_PCH_SPLIT(dev)) {
2830 pp_control_reg = PCH_PP_CONTROL;
2831 pp_on_reg = PCH_PP_ON_DELAYS;
2832 pp_off_reg = PCH_PP_OFF_DELAYS;
2833 pp_div_reg = PCH_PP_DIVISOR;
2834 } else {
2835 pp_control_reg = PIPEA_PP_CONTROL;
2836 pp_on_reg = PIPEA_PP_ON_DELAYS;
2837 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2838 pp_div_reg = PIPEA_PP_DIVISOR;
2839 }
67a54566
DV		 2840
2841 /* Workaround: Need to write PP_CONTROL with the unlock key as
2842 * the very first thing. */
453c5420
JB		 2843 pp = ironlake_get_pp_control(intel_dp);
2844 I915_WRITE(pp_control_reg, pp);
67a54566 2845
453c5420
JB		 2846 pp_on = I915_READ(pp_on_reg);
2847 pp_off = I915_READ(pp_off_reg);
2848 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2849
2850 /* Pull timing values out of registers */
2851 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2852 PANEL_POWER_UP_DELAY_SHIFT;
2853
2854 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2855 PANEL_LIGHT_ON_DELAY_SHIFT;
2856
2857 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2858 PANEL_LIGHT_OFF_DELAY_SHIFT;
2859
2860 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2861 PANEL_POWER_DOWN_DELAY_SHIFT;
2862
2863 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2864 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2865
2866 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2867 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2868
2869 vbt = dev_priv->edp.pps;
2870
2871 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2872 * our hw here, which are all in 100usec. */
2873 spec.t1_t3 = 210 * 10;
2874 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2875 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2876 spec.t10 = 500 * 10;
2877 /* This one is special and actually in units of 100ms, but zero
2878 * based in the hw (so we need to add 100 ms). But the sw vbt
2879 * table multiplies it with 1000 to make it in units of 100usec,
2880 * too. */
2881 spec.t11_t12 = (510 + 100) * 10;
2882
2883 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2884 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2885
2886 /* Use the max of the register settings and vbt. If both are
2887 * unset, fall back to the spec limits. */
2888#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2889 spec.field : \
2890 max(cur.field, vbt.field))
2891 assign_final(t1_t3);
2892 assign_final(t8);
2893 assign_final(t9);
2894 assign_final(t10);
2895 assign_final(t11_t12);
2896#undef assign_final
2897
2898#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2899 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2900 intel_dp->backlight_on_delay = get_delay(t8);
2901 intel_dp->backlight_off_delay = get_delay(t9);
2902 intel_dp->panel_power_down_delay = get_delay(t10);
2903 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2904#undef get_delay
2905
f30d26e4
JN		 2906 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2907 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2908 intel_dp->panel_power_cycle_delay);
2909
2910 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2911 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2912
2913 if (out)
2914 *out = final;
2915}
2916
2917static void
2918intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2919 struct intel_dp *intel_dp,
2920 struct edp_power_seq *seq)
2921{
2922 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2923 u32 pp_on, pp_off, pp_div, port_sel = 0;
2924 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2925 int pp_on_reg, pp_off_reg, pp_div_reg;
2926
2927 if (HAS_PCH_SPLIT(dev)) {
2928 pp_on_reg = PCH_PP_ON_DELAYS;
2929 pp_off_reg = PCH_PP_OFF_DELAYS;
2930 pp_div_reg = PCH_PP_DIVISOR;
2931 } else {
2932 pp_on_reg = PIPEA_PP_ON_DELAYS;
2933 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2934 pp_div_reg = PIPEA_PP_DIVISOR;
2935 }
2936
2937 if (IS_VALLEYVIEW(dev))
2938 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
f30d26e4 2939
67a54566 2940 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2941 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2942 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2943 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2944 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2945 /* Compute the divisor for the pp clock, simply match the Bspec
2946 * formula. */
453c5420 2947 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2948 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2949 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2950
2951 /* Haswell doesn't have any port selection bits for the panel
2952 * power sequencer any more. */
2953 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2954 if (is_cpu_edp(intel_dp))
453c5420 2955 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2956 else
453c5420 2957 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2958 }
2959
453c5420
JB		 2960 pp_on |= port_sel;
2961
2962 I915_WRITE(pp_on_reg, pp_on);
2963 I915_WRITE(pp_off_reg, pp_off);
2964 I915_WRITE(pp_div_reg, pp_div);
67a54566 2965
67a54566 2966 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2967 I915_READ(pp_on_reg),
2968 I915_READ(pp_off_reg),
2969 I915_READ(pp_div_reg));
f684960e
CW		 2970}
2971
a4fc5ed6 2972void
f0fec3f2
PZ		 2973intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2974 struct intel_connector *intel_connector)
a4fc5ed6 2975{
f0fec3f2
PZ		 2976 struct drm_connector *connector = &intel_connector->base;
2977 struct intel_dp *intel_dp = &intel_dig_port->dp;
2978 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2979 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2980 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2981 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2982 struct edp_power_seq power_seq = { 0 };
174edf1f 2983 enum port port = intel_dig_port->port;
5eb08b69 2984 const char *name = NULL;
b329530c 2985 int type;
a4fc5ed6 2986
0767935e
DV		 2987 /* Preserve the current hw state. */
2988 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2989 intel_dp->attached_connector = intel_connector;
3d3dc149 2990
f0fec3f2 2991 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2992 if (intel_dpd_is_edp(dev))
ea5b213a 2993 intel_dp->is_pch_edp = true;
b329530c 2994
19c03924
GB		 2995 /*
2996 * FIXME : We need to initialize built-in panels before external panels.
2997 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2998 */
f0fec3f2 2999 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 3000 type = DRM_MODE_CONNECTOR_eDP;
3001 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 3002 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 3003 type = DRM_MODE_CONNECTOR_eDP;
3004 intel_encoder->type = INTEL_OUTPUT_EDP;
3005 } else {
00c09d70
PZ		 3006 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
3007 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
3008 * rewrite it.
3009 */
b329530c 3010 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 3011 }
3012
b329530c 3013 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3014 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3015
a4fc5ed6
KP		 3016 connector->interlace_allowed = true;
3017 connector->doublescan_allowed = 0;
3018
f0fec3f2
PZ		 3019 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3020 ironlake_panel_vdd_work);
a4fc5ed6 3021
df0e9248 3022 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3023 drm_sysfs_connector_add(connector);
3024
affa9354 3025 if (HAS_DDI(dev))
bcbc889b
PZ		 3026 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3027 else
3028 intel_connector->get_hw_state = intel_connector_get_hw_state;
3029
9ed35ab1
PZ		 3030 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3031 if (HAS_DDI(dev)) {
3032 switch (intel_dig_port->port) {
3033 case PORT_A:
3034 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3035 break;
3036 case PORT_B:
3037 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3038 break;
3039 case PORT_C:
3040 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3041 break;
3042 case PORT_D:
3043 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3044 break;
3045 default:
3046 BUG();
3047 }
3048 }
e8cb4558 3049
a4fc5ed6 3050 /* Set up the DDC bus. */
ab9d7c30
PZ		 3051 switch (port) {
3052 case PORT_A:
1d843f9d 3053 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3054 name = "DPDDC-A";
3055 break;
3056 case PORT_B:
1d843f9d 3057 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3058 name = "DPDDC-B";
3059 break;
3060 case PORT_C:
1d843f9d 3061 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3062 name = "DPDDC-C";
3063 break;
3064 case PORT_D:
1d843f9d 3065 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3066 name = "DPDDC-D";
3067 break;
3068 default:
ad1c0b19 3069 BUG();
5eb08b69
ZW		 3070 }
3071
67a54566 3072 if (is_edp(intel_dp))
f30d26e4 3073 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 3074
3075 intel_dp_i2c_init(intel_dp, intel_connector, name);
3076
67a54566 3077 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 3078 if (is_edp(intel_dp)) {
3079 bool ret;
f8779fda 3080 struct drm_display_mode *scan;
c1f05264 3081 struct edid *edid;
5d613501
JB		 3082
3083 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 3084 ret = intel_dp_get_dpcd(intel_dp);
bd943159 3085 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 3086
59f3e272 3087 if (ret) {
7183dc29
JB		 3088 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3089 dev_priv->no_aux_handshake =
3090 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 3091 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3092 } else {
3d3dc149 3093 /* if this fails, presume the device is a ghost */
48898b03 3094 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 3095 intel_dp_encoder_destroy(&intel_encoder->base);
3096 intel_dp_destroy(connector);
3d3dc149 3097 return;
89667383 3098 }
89667383 3099
f30d26e4
JN		 3100 /* We now know it's not a ghost, init power sequence regs. */
3101 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3102 &power_seq);
3103
d6f24d0f
JB		 3104 ironlake_edp_panel_vdd_on(intel_dp);
3105 edid = drm_get_edid(connector, &intel_dp->adapter);
3106 if (edid) {
9cd300e0
JN		 3107 if (drm_add_edid_modes(connector, edid)) {
3108 drm_mode_connector_update_edid_property(connector, edid);
3109 drm_edid_to_eld(connector, edid);
3110 } else {
3111 kfree(edid);
3112 edid = ERR_PTR(-EINVAL);
3113 }
3114 } else {
3115 edid = ERR_PTR(-ENOENT);
d6f24d0f 3116 }
9cd300e0 3117 intel_connector->edid = edid;
f8779fda
JN		 3118
3119 /* prefer fixed mode from EDID if available */
3120 list_for_each_entry(scan, &connector->probed_modes, head) {
3121 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3122 fixed_mode = drm_mode_duplicate(dev, scan);
3123 break;
3124 }
d6f24d0f 3125 }
f8779fda
JN		 3126
3127 /* fallback to VBT if available for eDP */
3128 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3129 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3130 if (fixed_mode)
3131 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3132 }
f8779fda 3133
d6f24d0f
JB		 3134 ironlake_edp_panel_vdd_off(intel_dp, false);
3135 }
552fb0b7 3136
4d926461 3137 if (is_edp(intel_dp)) {
dd06f90e 3138 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 3139 intel_panel_setup_backlight(connector);
32f9d658
ZW		 3140 }
3141
f684960e
CW		 3142 intel_dp_add_properties(intel_dp, connector);
3143
a4fc5ed6
KP		 3144 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3145 * 0xd. Failure to do so will result in spurious interrupts being
3146 * generated on the port when a cable is not attached.
3147 */
3148 if (IS_G4X(dev) && !IS_GM45(dev)) {
3149 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3150 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3151 }
3152}
f0fec3f2
PZ		 3153
3154void
3155intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3156{
3157 struct intel_digital_port *intel_dig_port;
3158 struct intel_encoder *intel_encoder;
3159 struct drm_encoder *encoder;
3160 struct intel_connector *intel_connector;
3161
3162 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3163 if (!intel_dig_port)
3164 return;
3165
3166 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3167 if (!intel_connector) {
3168 kfree(intel_dig_port);
3169 return;
3170 }
3171
3172 intel_encoder = &intel_dig_port->base;
3173 encoder = &intel_encoder->base;
3174
3175 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3176 DRM_MODE_ENCODER_TMDS);
00c09d70 3177 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3178
5bfe2ac0 3179 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3180 intel_encoder->enable = intel_enable_dp;
3181 intel_encoder->pre_enable = intel_pre_enable_dp;
3182 intel_encoder->disable = intel_disable_dp;
3183 intel_encoder->post_disable = intel_post_disable_dp;
3184 intel_encoder->get_hw_state = intel_dp_get_hw_state;
89b667f8
JB		 3185 if (IS_VALLEYVIEW(dev))
3186 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3187
174edf1f 3188 intel_dig_port->port = port;
f0fec3f2
PZ		 3189 intel_dig_port->dp.output_reg = output_reg;
3190
00c09d70 3191 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3192 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3193 intel_encoder->cloneable = false;
3194 intel_encoder->hot_plug = intel_dp_hot_plug;
3195
3196 intel_dp_init_connector(intel_dig_port, intel_connector);
3197}
Linux kernel - Deliverables
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