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drm/i915/sdvo: Markup a few constant strings.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
ea5b213a
CW		 45#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46#define IS_PCH_eDP(i) ((i)->is_pch_edp)
32f9d658 47
ea5b213a
CW		 48struct intel_dp {
49 struct intel_encoder base;
a4fc5ed6
KP		 50 uint32_t output_reg;
51 uint32_t DP;
52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 53 bool has_audio;
c8110e52 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[4];
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
a4fc5ed6
KP		 61};
62
ea5b213a
CW		 63static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
64{
65 return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base);
66}
a4fc5ed6 67
ea5b213a
CW		 68static void intel_dp_link_train(struct intel_dp *intel_dp);
69static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 70
32f9d658 71void
21d40d37 72intel_edp_link_config (struct intel_encoder *intel_encoder,
ea5b213a 73 int *lane_num, int *link_bw)
32f9d658 74{
ea5b213a 75 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 76
ea5b213a
CW		 77 *lane_num = intel_dp->lane_count;
78 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 79 *link_bw = 162000;
ea5b213a 80 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 81 *link_bw = 270000;
82}
83
a4fc5ed6 84static int
ea5b213a 85intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 86{
a4fc5ed6
KP		 87 int max_lane_count = 4;
88
ea5b213a
CW		 89 if (intel_dp->dpcd[0] >= 0x11) {
90 max_lane_count = intel_dp->dpcd[2] & 0x1f;
a4fc5ed6
KP		 91 switch (max_lane_count) {
92 case 1: case 2: case 4:
93 break;
94 default:
95 max_lane_count = 4;
96 }
97 }
98 return max_lane_count;
99}
100
101static int
ea5b213a 102intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 103{
ea5b213a 104 int max_link_bw = intel_dp->dpcd[1];
a4fc5ed6
KP		 105
106 switch (max_link_bw) {
107 case DP_LINK_BW_1_62:
108 case DP_LINK_BW_2_7:
109 break;
110 default:
111 max_link_bw = DP_LINK_BW_1_62;
112 break;
113 }
114 return max_link_bw;
115}
116
117static int
118intel_dp_link_clock(uint8_t link_bw)
119{
120 if (link_bw == DP_LINK_BW_2_7)
121 return 270000;
122 else
123 return 162000;
124}
125
126/* I think this is a fiction */
127static int
ea5b213a 128intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
a4fc5ed6 129{
885a5fb5
ZW		 130 struct drm_i915_private *dev_priv = dev->dev_private;
131
ea5b213a 132 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
885a5fb5
ZW		 133 return (pixel_clock * dev_priv->edp_bpp) / 8;
134 else
135 return pixel_clock * 3;
a4fc5ed6
KP		 136}
137
fe27d53e
DA		 138static int
139intel_dp_max_data_rate(int max_link_clock, int max_lanes)
140{
141 return (max_link_clock * max_lanes * 8) / 10;
142}
143
a4fc5ed6
KP		 144static int
145intel_dp_mode_valid(struct drm_connector *connector,
146 struct drm_display_mode *mode)
147{
55f78c43 148 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
7de56f43
ZY		 150 struct drm_device *dev = connector->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a
CW		 152 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
153 int max_lanes = intel_dp_max_lane_count(intel_dp);
a4fc5ed6 154
ea5b213a 155 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
7de56f43
ZY		 156 dev_priv->panel_fixed_mode) {
157 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
158 return MODE_PANEL;
159
160 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
161 return MODE_PANEL;
162 }
163
fe27d53e
DA		 164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
165 which are outside spec tolerances but somehow work by magic */
ea5b213a
CW		 166 if (!IS_eDP(intel_dp) &&
167 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
fe27d53e 168 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
a4fc5ed6
KP		 169 return MODE_CLOCK_HIGH;
170
171 if (mode->clock < 10000)
172 return MODE_CLOCK_LOW;
173
174 return MODE_OK;
175}
176
177static uint32_t
178pack_aux(uint8_t *src, int src_bytes)
179{
180 int i;
181 uint32_t v = 0;
182
183 if (src_bytes > 4)
184 src_bytes = 4;
185 for (i = 0; i < src_bytes; i++)
186 v |= ((uint32_t) src[i]) << ((3-i) * 8);
187 return v;
188}
189
190static void
191unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
192{
193 int i;
194 if (dst_bytes > 4)
195 dst_bytes = 4;
196 for (i = 0; i < dst_bytes; i++)
197 dst[i] = src >> ((3-i) * 8);
198}
199
fb0f8fbf
KP		 200/* hrawclock is 1/4 the FSB frequency */
201static int
202intel_hrawclk(struct drm_device *dev)
203{
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 uint32_t clkcfg;
206
207 clkcfg = I915_READ(CLKCFG);
208 switch (clkcfg & CLKCFG_FSB_MASK) {
209 case CLKCFG_FSB_400:
210 return 100;
211 case CLKCFG_FSB_533:
212 return 133;
213 case CLKCFG_FSB_667:
214 return 166;
215 case CLKCFG_FSB_800:
216 return 200;
217 case CLKCFG_FSB_1067:
218 return 266;
219 case CLKCFG_FSB_1333:
220 return 333;
221 /* these two are just a guess; one of them might be right */
222 case CLKCFG_FSB_1600:
223 case CLKCFG_FSB_1600_ALT:
224 return 400;
225 default:
226 return 133;
227 }
228}
229
a4fc5ed6 230static int
ea5b213a 231intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 232 uint8_t *send, int send_bytes,
233 uint8_t *recv, int recv_size)
234{
ea5b213a
CW		 235 uint32_t output_reg = intel_dp->output_reg;
236 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6
KP		 237 struct drm_i915_private *dev_priv = dev->dev_private;
238 uint32_t ch_ctl = output_reg + 0x10;
239 uint32_t ch_data = ch_ctl + 4;
240 int i;
241 int recv_bytes;
242 uint32_t ctl;
243 uint32_t status;
fb0f8fbf 244 uint32_t aux_clock_divider;
e3421a18 245 int try, precharge;
a4fc5ed6
KP		 246
247 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 248 * and would like to run at 2MHz. So, take the
249 * hrawclk value and divide by 2 and use that
a4fc5ed6 250 */
ea5b213a 251 if (IS_eDP(intel_dp)) {
e3421a18
ZW		 252 if (IS_GEN6(dev))
253 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
254 else
255 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
256 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 257 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 258 else
259 aux_clock_divider = intel_hrawclk(dev) / 2;
260
e3421a18
ZW		 261 if (IS_GEN6(dev))
262 precharge = 3;
263 else
264 precharge = 5;
265
fb0f8fbf
KP		 266 /* Must try at least 3 times according to DP spec */
267 for (try = 0; try < 5; try++) {
268 /* Load the send data into the aux channel data registers */
269 for (i = 0; i < send_bytes; i += 4) {
a419aef8 270 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 271
272 I915_WRITE(ch_data + i, d);
273 }
274
275 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
276 DP_AUX_CH_CTL_TIME_OUT_400us |
277 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
e3421a18 278 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
fb0f8fbf
KP		 279 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
280 DP_AUX_CH_CTL_DONE |
281 DP_AUX_CH_CTL_TIME_OUT_ERROR |
282 DP_AUX_CH_CTL_RECEIVE_ERROR);
283
284 /* Send the command and wait for it to complete */
285 I915_WRITE(ch_ctl, ctl);
286 (void) I915_READ(ch_ctl);
287 for (;;) {
288 udelay(100);
289 status = I915_READ(ch_ctl);
290 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
291 break;
292 }
293
294 /* Clear done status and any errors */
eebc863e 295 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 296 DP_AUX_CH_CTL_DONE |
297 DP_AUX_CH_CTL_TIME_OUT_ERROR |
298 DP_AUX_CH_CTL_RECEIVE_ERROR));
299 (void) I915_READ(ch_ctl);
300 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 301 break;
302 }
303
a4fc5ed6 304 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 305 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 306 return -EBUSY;
a4fc5ed6
KP		 307 }
308
309 /* Check for timeout or receive error.
310 * Timeouts occur when the sink is not connected
311 */
a5b3da54 312 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 313 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 314 return -EIO;
315 }
1ae8c0a5
KP		 316
317 /* Timeouts occur when the device isn't connected, so they're
318 * "normal" -- don't fill the kernel log with these */
a5b3da54 319 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 320 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 321 return -ETIMEDOUT;
a4fc5ed6
KP		 322 }
323
324 /* Unload any bytes sent back from the other side */
325 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
326 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
327
328 if (recv_bytes > recv_size)
329 recv_bytes = recv_size;
330
331 for (i = 0; i < recv_bytes; i += 4) {
332 uint32_t d = I915_READ(ch_data + i);
333
334 unpack_aux(d, recv + i, recv_bytes - i);
335 }
336
337 return recv_bytes;
338}
339
340/* Write data to the aux channel in native mode */
341static int
ea5b213a 342intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 343 uint16_t address, uint8_t *send, int send_bytes)
344{
345 int ret;
346 uint8_t msg[20];
347 int msg_bytes;
348 uint8_t ack;
349
350 if (send_bytes > 16)
351 return -1;
352 msg[0] = AUX_NATIVE_WRITE << 4;
353 msg[1] = address >> 8;
eebc863e 354 msg[2] = address & 0xff;
a4fc5ed6
KP		 355 msg[3] = send_bytes - 1;
356 memcpy(&msg[4], send, send_bytes);
357 msg_bytes = send_bytes + 4;
358 for (;;) {
ea5b213a 359 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 360 if (ret < 0)
361 return ret;
362 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
363 break;
364 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
365 udelay(100);
366 else
a5b3da54 367 return -EIO;
a4fc5ed6
KP		 368 }
369 return send_bytes;
370}
371
372/* Write a single byte to the aux channel in native mode */
373static int
ea5b213a 374intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 375 uint16_t address, uint8_t byte)
376{
ea5b213a 377 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 378}
379
380/* read bytes from a native aux channel */
381static int
ea5b213a 382intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 383 uint16_t address, uint8_t *recv, int recv_bytes)
384{
385 uint8_t msg[4];
386 int msg_bytes;
387 uint8_t reply[20];
388 int reply_bytes;
389 uint8_t ack;
390 int ret;
391
392 msg[0] = AUX_NATIVE_READ << 4;
393 msg[1] = address >> 8;
394 msg[2] = address & 0xff;
395 msg[3] = recv_bytes - 1;
396
397 msg_bytes = 4;
398 reply_bytes = recv_bytes + 1;
399
400 for (;;) {
ea5b213a 401 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 402 reply, reply_bytes);
a5b3da54
KP		 403 if (ret == 0)
404 return -EPROTO;
405 if (ret < 0)
a4fc5ed6
KP		 406 return ret;
407 ack = reply[0];
408 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
409 memcpy(recv, reply + 1, ret - 1);
410 return ret - 1;
411 }
412 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
413 udelay(100);
414 else
a5b3da54 415 return -EIO;
a4fc5ed6
KP		 416 }
417}
418
419static int
ab2c0672
DA		 420intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
421 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 422{
ab2c0672 423 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 424 struct intel_dp *intel_dp = container_of(adapter,
425 struct intel_dp,
426 adapter);
ab2c0672
DA		 427 uint16_t address = algo_data->address;
428 uint8_t msg[5];
429 uint8_t reply[2];
430 int msg_bytes;
431 int reply_bytes;
432 int ret;
433
434 /* Set up the command byte */
435 if (mode & MODE_I2C_READ)
436 msg[0] = AUX_I2C_READ << 4;
437 else
438 msg[0] = AUX_I2C_WRITE << 4;
439
440 if (!(mode & MODE_I2C_STOP))
441 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 442
ab2c0672
DA		 443 msg[1] = address >> 8;
444 msg[2] = address;
445
446 switch (mode) {
447 case MODE_I2C_WRITE:
448 msg[3] = 0;
449 msg[4] = write_byte;
450 msg_bytes = 5;
451 reply_bytes = 1;
452 break;
453 case MODE_I2C_READ:
454 msg[3] = 0;
455 msg_bytes = 4;
456 reply_bytes = 2;
457 break;
458 default:
459 msg_bytes = 3;
460 reply_bytes = 1;
461 break;
462 }
463
464 for (;;) {
ea5b213a 465 ret = intel_dp_aux_ch(intel_dp,
ab2c0672
DA		 466 msg, msg_bytes,
467 reply, reply_bytes);
468 if (ret < 0) {
3ff99164 469 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 470 return ret;
471 }
472 switch (reply[0] & AUX_I2C_REPLY_MASK) {
473 case AUX_I2C_REPLY_ACK:
474 if (mode == MODE_I2C_READ) {
475 *read_byte = reply[1];
476 }
477 return reply_bytes - 1;
478 case AUX_I2C_REPLY_NACK:
3ff99164 479 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 480 return -EREMOTEIO;
481 case AUX_I2C_REPLY_DEFER:
3ff99164 482 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 483 udelay(100);
484 break;
485 default:
486 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
487 return -EREMOTEIO;
488 }
489 }
a4fc5ed6
KP		 490}
491
492static int
ea5b213a 493intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 494 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 495{
d54e9d28 496 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 497 intel_dp->algo.running = false;
498 intel_dp->algo.address = 0;
499 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
500
501 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
502 intel_dp->adapter.owner = THIS_MODULE;
503 intel_dp->adapter.class = I2C_CLASS_DDC;
504 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
505 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
506 intel_dp->adapter.algo_data = &intel_dp->algo;
507 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
508
509 return i2c_dp_aux_add_bus(&intel_dp->adapter);
a4fc5ed6
KP		 510}
511
512static bool
513intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
514 struct drm_display_mode *adjusted_mode)
515{
0d3a1bee
ZY		 516 struct drm_device *dev = encoder->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 518 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 519 int lane_count, clock;
ea5b213a
CW		 520 int max_lane_count = intel_dp_max_lane_count(intel_dp);
521 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 522 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
523
ea5b213a 524 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
0d3a1bee
ZY		 525 dev_priv->panel_fixed_mode) {
526 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
527
528 adjusted_mode->hdisplay = fixed_mode->hdisplay;
529 adjusted_mode->hsync_start = fixed_mode->hsync_start;
530 adjusted_mode->hsync_end = fixed_mode->hsync_end;
531 adjusted_mode->htotal = fixed_mode->htotal;
532
533 adjusted_mode->vdisplay = fixed_mode->vdisplay;
534 adjusted_mode->vsync_start = fixed_mode->vsync_start;
535 adjusted_mode->vsync_end = fixed_mode->vsync_end;
536 adjusted_mode->vtotal = fixed_mode->vtotal;
537
538 adjusted_mode->clock = fixed_mode->clock;
539 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
540
541 /*
542 * the mode->clock is used to calculate the Data&Link M/N
543 * of the pipe. For the eDP the fixed clock should be used.
544 */
545 mode->clock = dev_priv->panel_fixed_mode->clock;
546 }
547
a4fc5ed6
KP		 548 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
549 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 550 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 551
ea5b213a 552 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
885a5fb5 553 <= link_avail) {
ea5b213a
CW		 554 intel_dp->link_bw = bws[clock];
555 intel_dp->lane_count = lane_count;
556 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
28c97730
ZY		 557 DRM_DEBUG_KMS("Display port link bw %02x lane "
558 "count %d clock %d\n",
ea5b213a 559 intel_dp->link_bw, intel_dp->lane_count,
a4fc5ed6
KP		 560 adjusted_mode->clock);
561 return true;
562 }
563 }
564 }
fe27d53e 565
ea5b213a 566 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
fe27d53e 567 /* okay we failed just pick the highest */
ea5b213a
CW		 568 intel_dp->lane_count = max_lane_count;
569 intel_dp->link_bw = bws[max_clock];
570 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
fe27d53e
DA		 571 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
572 "count %d clock %d\n",
ea5b213a 573 intel_dp->link_bw, intel_dp->lane_count,
fe27d53e
DA		 574 adjusted_mode->clock);
575 return true;
576 }
a4fc5ed6
KP		 577 return false;
578}
579
580struct intel_dp_m_n {
581 uint32_t tu;
582 uint32_t gmch_m;
583 uint32_t gmch_n;
584 uint32_t link_m;
585 uint32_t link_n;
586};
587
588static void
589intel_reduce_ratio(uint32_t *num, uint32_t *den)
590{
591 while (*num > 0xffffff || *den > 0xffffff) {
592 *num >>= 1;
593 *den >>= 1;
594 }
595}
596
597static void
36e83a18 598intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 599 int nlanes,
600 int pixel_clock,
601 int link_clock,
602 struct intel_dp_m_n *m_n)
603{
604 m_n->tu = 64;
36e83a18 605 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 606 m_n->gmch_n = link_clock * nlanes;
607 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
608 m_n->link_m = pixel_clock;
609 m_n->link_n = link_clock;
610 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
611}
612
36e83a18
ZY		 613bool intel_pch_has_edp(struct drm_crtc *crtc)
614{
615 struct drm_device *dev = crtc->dev;
616 struct drm_mode_config *mode_config = &dev->mode_config;
617 struct drm_encoder *encoder;
618
619 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 620 struct intel_dp *intel_dp;
36e83a18 621
ea5b213a 622 if (encoder->crtc != crtc)
36e83a18
ZY		 623 continue;
624
ea5b213a
CW		 625 intel_dp = enc_to_intel_dp(encoder);
626 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
627 return intel_dp->is_pch_edp;
36e83a18
ZY		 628 }
629 return false;
630}
631
a4fc5ed6
KP		 632void
633intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
634 struct drm_display_mode *adjusted_mode)
635{
636 struct drm_device *dev = crtc->dev;
637 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 638 struct drm_encoder *encoder;
a4fc5ed6
KP		 639 struct drm_i915_private *dev_priv = dev->dev_private;
640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
36e83a18 641 int lane_count = 4, bpp = 24;
a4fc5ed6
KP		 642 struct intel_dp_m_n m_n;
643
644 /*
21d40d37 645 * Find the lane count in the intel_encoder private
a4fc5ed6 646 */
55f78c43 647 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 648 struct intel_dp *intel_dp;
a4fc5ed6 649
d8201ab6 650 if (encoder->crtc != crtc)
a4fc5ed6
KP		 651 continue;
652
ea5b213a
CW		 653 intel_dp = enc_to_intel_dp(encoder);
654 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
655 lane_count = intel_dp->lane_count;
656 if (IS_PCH_eDP(intel_dp))
36e83a18 657 bpp = dev_priv->edp_bpp;
a4fc5ed6
KP		 658 break;
659 }
660 }
661
662 /*
663 * Compute the GMCH and Link ratios. The '3' here is
664 * the number of bytes_per_pixel post-LUT, which we always
665 * set up for 8-bits of R/G/B, or 3 bytes total.
666 */
36e83a18 667 intel_dp_compute_m_n(bpp, lane_count,
a4fc5ed6
KP		 668 mode->clock, adjusted_mode->clock, &m_n);
669
c619eed4 670 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 671 if (intel_crtc->pipe == 0) {
672 I915_WRITE(TRANSA_DATA_M1,
673 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
674 m_n.gmch_m);
675 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
676 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
677 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
678 } else {
679 I915_WRITE(TRANSB_DATA_M1,
680 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
681 m_n.gmch_m);
682 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
683 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
684 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
685 }
a4fc5ed6 686 } else {
5eb08b69
ZW		 687 if (intel_crtc->pipe == 0) {
688 I915_WRITE(PIPEA_GMCH_DATA_M,
689 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
690 m_n.gmch_m);
691 I915_WRITE(PIPEA_GMCH_DATA_N,
692 m_n.gmch_n);
693 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
694 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
695 } else {
696 I915_WRITE(PIPEB_GMCH_DATA_M,
697 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
698 m_n.gmch_m);
699 I915_WRITE(PIPEB_GMCH_DATA_N,
700 m_n.gmch_n);
701 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
702 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
703 }
a4fc5ed6
KP		 704 }
705}
706
707static void
708intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
709 struct drm_display_mode *adjusted_mode)
710{
e3421a18 711 struct drm_device *dev = encoder->dev;
ea5b213a
CW		 712 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
713 struct drm_crtc *crtc = intel_dp->base.enc.crtc;
a4fc5ed6
KP		 714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
715
ea5b213a 716 intel_dp->DP = (DP_VOLTAGE_0_4 |
9c9e7927
AJ		 717 DP_PRE_EMPHASIS_0);
718
719 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
ea5b213a 720 intel_dp->DP |= DP_SYNC_HS_HIGH;
9c9e7927 721 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
ea5b213a 722 intel_dp->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 723
ea5b213a
CW		 724 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
725 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3421a18 726 else
ea5b213a 727 intel_dp->DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6 728
ea5b213a 729 switch (intel_dp->lane_count) {
a4fc5ed6 730 case 1:
ea5b213a 731 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 732 break;
733 case 2:
ea5b213a 734 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 735 break;
736 case 4:
ea5b213a 737 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 738 break;
739 }
ea5b213a
CW		 740 if (intel_dp->has_audio)
741 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
a4fc5ed6 742
ea5b213a
CW		 743 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
744 intel_dp->link_configuration[0] = intel_dp->link_bw;
745 intel_dp->link_configuration[1] = intel_dp->lane_count;
a4fc5ed6
KP		 746
747 /*
9962c925 748 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 749 */
ea5b213a
CW		 750 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
751 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
752 intel_dp->DP |= DP_ENHANCED_FRAMING;
a4fc5ed6
KP		 753 }
754
e3421a18
ZW		 755 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
756 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
ea5b213a 757 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 758
ea5b213a 759 if (IS_eDP(intel_dp)) {
32f9d658 760 /* don't miss out required setting for eDP */
ea5b213a 761 intel_dp->DP |= DP_PLL_ENABLE;
32f9d658 762 if (adjusted_mode->clock < 200000)
ea5b213a 763 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
32f9d658 764 else
ea5b213a 765 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
32f9d658 766 }
a4fc5ed6
KP		 767}
768
9934c132
JB		 769static void ironlake_edp_panel_on (struct drm_device *dev)
770{
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
773 u32 pp, pp_status;
774
775 pp_status = I915_READ(PCH_PP_STATUS);
776 if (pp_status & PP_ON)
777 return;
778
779 pp = I915_READ(PCH_PP_CONTROL);
780 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
781 I915_WRITE(PCH_PP_CONTROL, pp);
782 do {
783 pp_status = I915_READ(PCH_PP_STATUS);
784 } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
785
786 if (time_after(jiffies, timeout))
787 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
788
789 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
790 I915_WRITE(PCH_PP_CONTROL, pp);
791}
792
793static void ironlake_edp_panel_off (struct drm_device *dev)
794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
796 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
797 u32 pp, pp_status;
798
799 pp = I915_READ(PCH_PP_CONTROL);
800 pp &= ~POWER_TARGET_ON;
801 I915_WRITE(PCH_PP_CONTROL, pp);
802 do {
803 pp_status = I915_READ(PCH_PP_STATUS);
804 } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
805
806 if (time_after(jiffies, timeout))
807 DRM_DEBUG_KMS("panel off wait timed out\n");
808
809 /* Make sure VDD is enabled so DP AUX will work */
810 pp |= EDP_FORCE_VDD;
811 I915_WRITE(PCH_PP_CONTROL, pp);
812}
813
f2b115e6 814static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
817 u32 pp;
818
28c97730 819 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 820 pp = I915_READ(PCH_PP_CONTROL);
821 pp |= EDP_BLC_ENABLE;
822 I915_WRITE(PCH_PP_CONTROL, pp);
823}
824
f2b115e6 825static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 u32 pp;
829
28c97730 830 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 831 pp = I915_READ(PCH_PP_CONTROL);
832 pp &= ~EDP_BLC_ENABLE;
833 I915_WRITE(PCH_PP_CONTROL, pp);
834}
a4fc5ed6
KP		 835
836static void
837intel_dp_dpms(struct drm_encoder *encoder, int mode)
838{
ea5b213a 839 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 840 struct drm_device *dev = encoder->dev;
a4fc5ed6 841 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 842 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 843
844 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 845 if (dp_reg & DP_PORT_EN) {
ea5b213a
CW		 846 intel_dp_link_down(intel_dp);
847 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
f2b115e6 848 ironlake_edp_backlight_off(dev);
5620ae29 849 ironlake_edp_panel_off(dev);
9934c132 850 }
32f9d658 851 }
a4fc5ed6 852 } else {
32f9d658 853 if (!(dp_reg & DP_PORT_EN)) {
ea5b213a
CW		 854 intel_dp_link_train(intel_dp);
855 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
9934c132 856 ironlake_edp_panel_on(dev);
f2b115e6 857 ironlake_edp_backlight_on(dev);
9934c132 858 }
32f9d658 859 }
a4fc5ed6 860 }
ea5b213a 861 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 862}
863
864/*
865 * Fetch AUX CH registers 0x202 - 0x207 which contain
866 * link status information
867 */
868static bool
ea5b213a 869intel_dp_get_link_status(struct intel_dp *intel_dp,
a4fc5ed6
KP		 870 uint8_t link_status[DP_LINK_STATUS_SIZE])
871{
872 int ret;
873
ea5b213a 874 ret = intel_dp_aux_native_read(intel_dp,
a4fc5ed6
KP		 875 DP_LANE0_1_STATUS,
876 link_status, DP_LINK_STATUS_SIZE);
877 if (ret != DP_LINK_STATUS_SIZE)
878 return false;
879 return true;
880}
881
882static uint8_t
883intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
884 int r)
885{
886 return link_status[r - DP_LANE0_1_STATUS];
887}
888
a4fc5ed6
KP		 889static uint8_t
890intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
891 int lane)
892{
893 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
894 int s = ((lane & 1) ?
895 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
896 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
897 uint8_t l = intel_dp_link_status(link_status, i);
898
899 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
900}
901
902static uint8_t
903intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
904 int lane)
905{
906 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
907 int s = ((lane & 1) ?
908 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
909 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
910 uint8_t l = intel_dp_link_status(link_status, i);
911
912 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
913}
914
915
916#if 0
917static char *voltage_names[] = {
918 "0.4V", "0.6V", "0.8V", "1.2V"
919};
920static char *pre_emph_names[] = {
921 "0dB", "3.5dB", "6dB", "9.5dB"
922};
923static char *link_train_names[] = {
924 "pattern 1", "pattern 2", "idle", "off"
925};
926#endif
927
928/*
929 * These are source-specific values; current Intel hardware supports
930 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
931 */
932#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
933
934static uint8_t
935intel_dp_pre_emphasis_max(uint8_t voltage_swing)
936{
937 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
938 case DP_TRAIN_VOLTAGE_SWING_400:
939 return DP_TRAIN_PRE_EMPHASIS_6;
940 case DP_TRAIN_VOLTAGE_SWING_600:
941 return DP_TRAIN_PRE_EMPHASIS_6;
942 case DP_TRAIN_VOLTAGE_SWING_800:
943 return DP_TRAIN_PRE_EMPHASIS_3_5;
944 case DP_TRAIN_VOLTAGE_SWING_1200:
945 default:
946 return DP_TRAIN_PRE_EMPHASIS_0;
947 }
948}
949
950static void
ea5b213a 951intel_get_adjust_train(struct intel_dp *intel_dp,
a4fc5ed6
KP		 952 uint8_t link_status[DP_LINK_STATUS_SIZE],
953 int lane_count,
954 uint8_t train_set[4])
955{
956 uint8_t v = 0;
957 uint8_t p = 0;
958 int lane;
959
960 for (lane = 0; lane < lane_count; lane++) {
961 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
962 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
963
964 if (this_v > v)
965 v = this_v;
966 if (this_p > p)
967 p = this_p;
968 }
969
970 if (v >= I830_DP_VOLTAGE_MAX)
971 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
972
973 if (p >= intel_dp_pre_emphasis_max(v))
974 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
975
976 for (lane = 0; lane < 4; lane++)
977 train_set[lane] = v | p;
978}
979
980static uint32_t
981intel_dp_signal_levels(uint8_t train_set, int lane_count)
982{
983 uint32_t signal_levels = 0;
984
985 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
986 case DP_TRAIN_VOLTAGE_SWING_400:
987 default:
988 signal_levels |= DP_VOLTAGE_0_4;
989 break;
990 case DP_TRAIN_VOLTAGE_SWING_600:
991 signal_levels |= DP_VOLTAGE_0_6;
992 break;
993 case DP_TRAIN_VOLTAGE_SWING_800:
994 signal_levels |= DP_VOLTAGE_0_8;
995 break;
996 case DP_TRAIN_VOLTAGE_SWING_1200:
997 signal_levels |= DP_VOLTAGE_1_2;
998 break;
999 }
1000 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1001 case DP_TRAIN_PRE_EMPHASIS_0:
1002 default:
1003 signal_levels |= DP_PRE_EMPHASIS_0;
1004 break;
1005 case DP_TRAIN_PRE_EMPHASIS_3_5:
1006 signal_levels |= DP_PRE_EMPHASIS_3_5;
1007 break;
1008 case DP_TRAIN_PRE_EMPHASIS_6:
1009 signal_levels |= DP_PRE_EMPHASIS_6;
1010 break;
1011 case DP_TRAIN_PRE_EMPHASIS_9_5:
1012 signal_levels |= DP_PRE_EMPHASIS_9_5;
1013 break;
1014 }
1015 return signal_levels;
1016}
1017
e3421a18
ZW		 1018/* Gen6's DP voltage swing and pre-emphasis control */
1019static uint32_t
1020intel_gen6_edp_signal_levels(uint8_t train_set)
1021{
1022 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1023 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1024 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1025 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1026 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1027 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1028 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1029 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1030 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1031 default:
1032 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1033 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1034 }
1035}
1036
a4fc5ed6
KP		 1037static uint8_t
1038intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1039 int lane)
1040{
1041 int i = DP_LANE0_1_STATUS + (lane >> 1);
1042 int s = (lane & 1) * 4;
1043 uint8_t l = intel_dp_link_status(link_status, i);
1044
1045 return (l >> s) & 0xf;
1046}
1047
1048/* Check for clock recovery is done on all channels */
1049static bool
1050intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1051{
1052 int lane;
1053 uint8_t lane_status;
1054
1055 for (lane = 0; lane < lane_count; lane++) {
1056 lane_status = intel_get_lane_status(link_status, lane);
1057 if ((lane_status & DP_LANE_CR_DONE) == 0)
1058 return false;
1059 }
1060 return true;
1061}
1062
1063/* Check to see if channel eq is done on all channels */
1064#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1065 DP_LANE_CHANNEL_EQ_DONE|\
1066 DP_LANE_SYMBOL_LOCKED)
1067static bool
1068intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1069{
1070 uint8_t lane_align;
1071 uint8_t lane_status;
1072 int lane;
1073
1074 lane_align = intel_dp_link_status(link_status,
1075 DP_LANE_ALIGN_STATUS_UPDATED);
1076 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1077 return false;
1078 for (lane = 0; lane < lane_count; lane++) {
1079 lane_status = intel_get_lane_status(link_status, lane);
1080 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1081 return false;
1082 }
1083 return true;
1084}
1085
1086static bool
ea5b213a 1087intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6
KP		 1088 uint32_t dp_reg_value,
1089 uint8_t dp_train_pat,
1090 uint8_t train_set[4],
1091 bool first)
1092{
ea5b213a 1093 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1094 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1095 int ret;
1096
ea5b213a
CW		 1097 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1098 POSTING_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1099 if (first)
1100 intel_wait_for_vblank(dev);
1101
ea5b213a 1102 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1103 DP_TRAINING_PATTERN_SET,
1104 dp_train_pat);
1105
ea5b213a 1106 ret = intel_dp_aux_native_write(intel_dp,
a4fc5ed6
KP		 1107 DP_TRAINING_LANE0_SET, train_set, 4);
1108 if (ret != 4)
1109 return false;
1110
1111 return true;
1112}
1113
1114static void
ea5b213a 1115intel_dp_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1116{
ea5b213a 1117 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1118 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1119 uint8_t train_set[4];
1120 uint8_t link_status[DP_LINK_STATUS_SIZE];
1121 int i;
1122 uint8_t voltage;
1123 bool clock_recovery = false;
1124 bool channel_eq = false;
1125 bool first = true;
1126 int tries;
e3421a18 1127 u32 reg;
ea5b213a 1128 uint32_t DP = intel_dp->DP;
a4fc5ed6
KP		 1129
1130 /* Write the link configuration data */
ea5b213a
CW		 1131 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1132 intel_dp->link_configuration,
1133 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1134
1135 DP |= DP_PORT_EN;
ea5b213a 1136 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1137 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1138 else
1139 DP &= ~DP_LINK_TRAIN_MASK;
a4fc5ed6
KP		 1140 memset(train_set, 0, 4);
1141 voltage = 0xff;
1142 tries = 0;
1143 clock_recovery = false;
1144 for (;;) {
1145 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18 1146 uint32_t signal_levels;
ea5b213a 1147 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
e3421a18
ZW		 1148 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1149 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1150 } else {
ea5b213a 1151 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1152 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1153 }
a4fc5ed6 1154
ea5b213a 1155 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1156 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1157 else
1158 reg = DP | DP_LINK_TRAIN_PAT_1;
1159
ea5b213a 1160 if (!intel_dp_set_link_train(intel_dp, reg,
a4fc5ed6
KP		 1161 DP_TRAINING_PATTERN_1, train_set, first))
1162 break;
1163 first = false;
1164 /* Set training pattern 1 */
1165
1166 udelay(100);
ea5b213a 1167 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6
KP		 1168 break;
1169
ea5b213a 1170 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
a4fc5ed6
KP		 1171 clock_recovery = true;
1172 break;
1173 }
1174
1175 /* Check to see if we've tried the max voltage */
ea5b213a 1176 for (i = 0; i < intel_dp->lane_count; i++)
a4fc5ed6
KP		 1177 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1178 break;
ea5b213a 1179 if (i == intel_dp->lane_count)
a4fc5ed6
KP		 1180 break;
1181
1182 /* Check to see if we've tried the same voltage 5 times */
1183 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1184 ++tries;
1185 if (tries == 5)
1186 break;
1187 } else
1188 tries = 0;
1189 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1190
1191 /* Compute new train_set as requested by target */
ea5b213a 1192 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
a4fc5ed6
KP		 1193 }
1194
1195 /* channel equalization */
1196 tries = 0;
1197 channel_eq = false;
1198 for (;;) {
1199 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1200 uint32_t signal_levels;
1201
ea5b213a 1202 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
e3421a18
ZW		 1203 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1204 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1205 } else {
ea5b213a 1206 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1207 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1208 }
1209
ea5b213a 1210 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1211 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1212 else
1213 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1214
1215 /* channel eq pattern */
ea5b213a 1216 if (!intel_dp_set_link_train(intel_dp, reg,
a4fc5ed6
KP		 1217 DP_TRAINING_PATTERN_2, train_set,
1218 false))
1219 break;
1220
1221 udelay(400);
ea5b213a 1222 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6
KP		 1223 break;
1224
ea5b213a 1225 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) {
a4fc5ed6
KP		 1226 channel_eq = true;
1227 break;
1228 }
1229
1230 /* Try 5 times */
1231 if (tries > 5)
1232 break;
1233
1234 /* Compute new train_set as requested by target */
ea5b213a 1235 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
a4fc5ed6
KP		 1236 ++tries;
1237 }
1238
ea5b213a 1239 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1240 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1241 else
1242 reg = DP | DP_LINK_TRAIN_OFF;
1243
ea5b213a
CW		 1244 I915_WRITE(intel_dp->output_reg, reg);
1245 POSTING_READ(intel_dp->output_reg);
1246 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1247 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1248}
1249
1250static void
ea5b213a 1251intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1252{
ea5b213a 1253 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1254 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1255 uint32_t DP = intel_dp->DP;
a4fc5ed6 1256
28c97730 1257 DRM_DEBUG_KMS("\n");
32f9d658 1258
ea5b213a 1259 if (IS_eDP(intel_dp)) {
32f9d658 1260 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1261 I915_WRITE(intel_dp->output_reg, DP);
1262 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1263 udelay(100);
1264 }
1265
ea5b213a 1266 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
e3421a18 1267 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a
CW		 1268 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1269 POSTING_READ(intel_dp->output_reg);
e3421a18
ZW		 1270 } else {
1271 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a
CW		 1272 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1273 POSTING_READ(intel_dp->output_reg);
e3421a18 1274 }
5eb08b69
ZW		 1275
1276 udelay(17000);
1277
ea5b213a 1278 if (IS_eDP(intel_dp))
32f9d658 1279 DP |= DP_LINK_TRAIN_OFF;
ea5b213a
CW		 1280 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1281 POSTING_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1282}
1283
a4fc5ed6
KP		 1284/*
1285 * According to DP spec
1286 * 5.1.2:
1287 * 1. Read DPCD
1288 * 2. Configure link according to Receiver Capabilities
1289 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1290 * 4. Check link status on receipt of hot-plug interrupt
1291 */
1292
1293static void
ea5b213a 1294intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 1295{
a4fc5ed6
KP		 1296 uint8_t link_status[DP_LINK_STATUS_SIZE];
1297
ea5b213a 1298 if (!intel_dp->base.enc.crtc)
a4fc5ed6
KP		 1299 return;
1300
ea5b213a
CW		 1301 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1302 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 1303 return;
1304 }
1305
ea5b213a
CW		 1306 if (!intel_channel_eq_ok(link_status, intel_dp->lane_count))
1307 intel_dp_link_train(intel_dp);
a4fc5ed6 1308}
a4fc5ed6 1309
5eb08b69 1310static enum drm_connector_status
f2b115e6 1311ironlake_dp_detect(struct drm_connector *connector)
5eb08b69 1312{
55f78c43 1313 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1314 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5eb08b69
ZW		 1315 enum drm_connector_status status;
1316
1317 status = connector_status_disconnected;
ea5b213a
CW		 1318 if (intel_dp_aux_native_read(intel_dp,
1319 0x000, intel_dp->dpcd,
1320 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
5eb08b69 1321 {
ea5b213a 1322 if (intel_dp->dpcd[0] != 0)
5eb08b69
ZW		 1323 status = connector_status_connected;
1324 }
ea5b213a
CW		 1325 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1326 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
5eb08b69
ZW		 1327 return status;
1328}
1329
a4fc5ed6
KP		 1330/**
1331 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1332 *
1333 * \return true if DP port is connected.
1334 * \return false if DP port is disconnected.
1335 */
1336static enum drm_connector_status
1337intel_dp_detect(struct drm_connector *connector)
1338{
55f78c43 1339 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a
CW		 1340 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1341 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1342 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1343 uint32_t temp, bit;
1344 enum drm_connector_status status;
1345
ea5b213a 1346 intel_dp->has_audio = false;
a4fc5ed6 1347
c619eed4 1348 if (HAS_PCH_SPLIT(dev))
f2b115e6 1349 return ironlake_dp_detect(connector);
5eb08b69 1350
ea5b213a 1351 switch (intel_dp->output_reg) {
a4fc5ed6
KP		 1352 case DP_B:
1353 bit = DPB_HOTPLUG_INT_STATUS;
1354 break;
1355 case DP_C:
1356 bit = DPC_HOTPLUG_INT_STATUS;
1357 break;
1358 case DP_D:
1359 bit = DPD_HOTPLUG_INT_STATUS;
1360 break;
1361 default:
1362 return connector_status_unknown;
1363 }
1364
1365 temp = I915_READ(PORT_HOTPLUG_STAT);
1366
1367 if ((temp & bit) == 0)
1368 return connector_status_disconnected;
1369
1370 status = connector_status_disconnected;
ea5b213a
CW		 1371 if (intel_dp_aux_native_read(intel_dp,
1372 0x000, intel_dp->dpcd,
1373 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
a4fc5ed6 1374 {
ea5b213a 1375 if (intel_dp->dpcd[0] != 0)
a4fc5ed6
KP		 1376 status = connector_status_connected;
1377 }
1378 return status;
1379}
1380
1381static int intel_dp_get_modes(struct drm_connector *connector)
1382{
55f78c43 1383 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a
CW		 1384 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1385 struct drm_device *dev = intel_dp->base.enc.dev;
32f9d658
ZW		 1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 int ret;
a4fc5ed6
KP		 1388
1389 /* We should parse the EDID data and find out if it has an audio sink
1390 */
1391
ea5b213a 1392 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
b9efc480 1393 if (ret) {
ea5b213a 1394 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
b9efc480
ZY		 1395 !dev_priv->panel_fixed_mode) {
1396 struct drm_display_mode *newmode;
1397 list_for_each_entry(newmode, &connector->probed_modes,
1398 head) {
1399 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1400 dev_priv->panel_fixed_mode =
1401 drm_mode_duplicate(dev, newmode);
1402 break;
1403 }
1404 }
1405 }
1406
32f9d658 1407 return ret;
b9efc480 1408 }
32f9d658
ZW		 1409
1410 /* if eDP has no EDID, try to use fixed panel mode from VBT */
ea5b213a 1411 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
32f9d658
ZW		 1412 if (dev_priv->panel_fixed_mode != NULL) {
1413 struct drm_display_mode *mode;
1414 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1415 drm_mode_probed_add(connector, mode);
1416 return 1;
1417 }
1418 }
1419 return 0;
a4fc5ed6
KP		 1420}
1421
1422static void
1423intel_dp_destroy (struct drm_connector *connector)
1424{
a4fc5ed6
KP		 1425 drm_sysfs_connector_remove(connector);
1426 drm_connector_cleanup(connector);
55f78c43 1427 kfree(connector);
a4fc5ed6
KP		 1428}
1429
1430static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1431 .dpms = intel_dp_dpms,
1432 .mode_fixup = intel_dp_mode_fixup,
1433 .prepare = intel_encoder_prepare,
1434 .mode_set = intel_dp_mode_set,
1435 .commit = intel_encoder_commit,
1436};
1437
1438static const struct drm_connector_funcs intel_dp_connector_funcs = {
1439 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1440 .detect = intel_dp_detect,
1441 .fill_modes = drm_helper_probe_single_connector_modes,
1442 .destroy = intel_dp_destroy,
1443};
1444
1445static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1446 .get_modes = intel_dp_get_modes,
1447 .mode_valid = intel_dp_mode_valid,
55f78c43 1448 .best_encoder = intel_attached_encoder,
a4fc5ed6
KP		 1449};
1450
a4fc5ed6 1451static const struct drm_encoder_funcs intel_dp_enc_funcs = {
ea5b213a 1452 .destroy = intel_encoder_destroy,
a4fc5ed6
KP		 1453};
1454
c8110e52 1455void
21d40d37 1456intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 1457{
ea5b213a 1458 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 1459
ea5b213a
CW		 1460 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1461 intel_dp_check_link_status(intel_dp);
c8110e52 1462}
6207937d 1463
e3421a18
ZW		 1464/* Return which DP Port should be selected for Transcoder DP control */
1465int
1466intel_trans_dp_port_sel (struct drm_crtc *crtc)
1467{
1468 struct drm_device *dev = crtc->dev;
1469 struct drm_mode_config *mode_config = &dev->mode_config;
1470 struct drm_encoder *encoder;
e3421a18
ZW		 1471
1472 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 1473 struct intel_dp *intel_dp;
1474
d8201ab6 1475 if (encoder->crtc != crtc)
e3421a18
ZW		 1476 continue;
1477
ea5b213a
CW		 1478 intel_dp = enc_to_intel_dp(encoder);
1479 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1480 return intel_dp->output_reg;
e3421a18 1481 }
ea5b213a 1482
e3421a18
ZW		 1483 return -1;
1484}
1485
36e83a18 1486/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 1487bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 1488{
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 struct child_device_config *p_child;
1491 int i;
1492
1493 if (!dev_priv->child_dev_num)
1494 return false;
1495
1496 for (i = 0; i < dev_priv->child_dev_num; i++) {
1497 p_child = dev_priv->child_dev + i;
1498
1499 if (p_child->dvo_port == PORT_IDPD &&
1500 p_child->device_type == DEVICE_TYPE_eDP)
1501 return true;
1502 }
1503 return false;
1504}
1505
a4fc5ed6
KP		 1506void
1507intel_dp_init(struct drm_device *dev, int output_reg)
1508{
1509 struct drm_i915_private *dev_priv = dev->dev_private;
1510 struct drm_connector *connector;
ea5b213a 1511 struct intel_dp *intel_dp;
21d40d37 1512 struct intel_encoder *intel_encoder;
55f78c43 1513 struct intel_connector *intel_connector;
5eb08b69 1514 const char *name = NULL;
b329530c 1515 int type;
a4fc5ed6 1516
ea5b213a
CW		 1517 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1518 if (!intel_dp)
a4fc5ed6
KP		 1519 return;
1520
55f78c43
ZW		 1521 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1522 if (!intel_connector) {
ea5b213a 1523 kfree(intel_dp);
55f78c43
ZW		 1524 return;
1525 }
ea5b213a 1526 intel_encoder = &intel_dp->base;
55f78c43 1527
ea5b213a 1528 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 1529 if (intel_dpd_is_edp(dev))
ea5b213a 1530 intel_dp->is_pch_edp = true;
b329530c 1531
ea5b213a 1532 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
b329530c
AJ		 1533 type = DRM_MODE_CONNECTOR_eDP;
1534 intel_encoder->type = INTEL_OUTPUT_EDP;
1535 } else {
1536 type = DRM_MODE_CONNECTOR_DisplayPort;
1537 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1538 }
1539
55f78c43 1540 connector = &intel_connector->base;
b329530c 1541 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 1542 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1543
eb1f8e4f
DA		 1544 connector->polled = DRM_CONNECTOR_POLL_HPD;
1545
652af9d7 1546 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 1547 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1548 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 1549 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1550 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 1551 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 1552
ea5b213a 1553 if (IS_eDP(intel_dp))
21d40d37 1554 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 1555
21d40d37 1556 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1557 connector->interlace_allowed = true;
1558 connector->doublescan_allowed = 0;
1559
ea5b213a
CW		 1560 intel_dp->output_reg = output_reg;
1561 intel_dp->has_audio = false;
1562 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6 1563
21d40d37 1564 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
a4fc5ed6 1565 DRM_MODE_ENCODER_TMDS);
21d40d37 1566 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
a4fc5ed6 1567
55f78c43 1568 drm_mode_connector_attach_encoder(&intel_connector->base,
21d40d37 1569 &intel_encoder->enc);
a4fc5ed6
KP		 1570 drm_sysfs_connector_add(connector);
1571
1572 /* Set up the DDC bus. */
5eb08b69 1573 switch (output_reg) {
32f9d658
ZW		 1574 case DP_A:
1575 name = "DPDDC-A";
1576 break;
5eb08b69
ZW		 1577 case DP_B:
1578 case PCH_DP_B:
b01f2c3a
JB		 1579 dev_priv->hotplug_supported_mask |=
1580 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1581 name = "DPDDC-B";
1582 break;
1583 case DP_C:
1584 case PCH_DP_C:
b01f2c3a
JB		 1585 dev_priv->hotplug_supported_mask |=
1586 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1587 name = "DPDDC-C";
1588 break;
1589 case DP_D:
1590 case PCH_DP_D:
b01f2c3a
JB		 1591 dev_priv->hotplug_supported_mask |=
1592 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1593 name = "DPDDC-D";
1594 break;
1595 }
1596
ea5b213a 1597 intel_dp_i2c_init(intel_dp, intel_connector, name);
32f9d658 1598
ea5b213a 1599 intel_encoder->ddc_bus = &intel_dp->adapter;
21d40d37 1600 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1601
ea5b213a 1602 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
32f9d658
ZW		 1603 /* initialize panel mode from VBT if available for eDP */
1604 if (dev_priv->lfp_lvds_vbt_mode) {
1605 dev_priv->panel_fixed_mode =
1606 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1607 if (dev_priv->panel_fixed_mode) {
1608 dev_priv->panel_fixed_mode->type |=
1609 DRM_MODE_TYPE_PREFERRED;
1610 }
1611 }
1612 }
1613
a4fc5ed6
KP		 1614 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1615 * 0xd. Failure to do so will result in spurious interrupts being
1616 * generated on the port when a cable is not attached.
1617 */
1618 if (IS_G4X(dev) && !IS_GM45(dev)) {
1619 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1620 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1621 }
1622}
Linux kernel - Deliverables
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