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drm/i915: bounds check execbuffer relocation count
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
c4867936
DV		 180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
cb1793ce 183 bool adjust_mode)
c4867936 184{
9fa5f652
PZ		 185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
30add22d 295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
30add22d 303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
30add22d 312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
9ee32fea
DV		 325static uint32_t
326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
ef04f00d 354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 355 if (has_aux_irq)
b18ac466
PZ		 356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
357 msecs_to_jiffies(10));
9ee32fea
DV		 358 else
359 done = wait_for_atomic(C, 10) == 0;
360 if (!done)
361 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
362 has_aux_irq);
363#undef C
364
365 return status;
366}
367
a4fc5ed6 368static int
ea5b213a 369intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 370 uint8_t *send, int send_bytes,
371 uint8_t *recv, int recv_size)
372{
ea5b213a 373 uint32_t output_reg = intel_dp->output_reg;
174edf1f
PZ		 374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
375 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6
KP		 376 struct drm_i915_private *dev_priv = dev->dev_private;
377 uint32_t ch_ctl = output_reg + 0x10;
378 uint32_t ch_data = ch_ctl + 4;
9ee32fea 379 int i, ret, recv_bytes;
a4fc5ed6 380 uint32_t status;
fb0f8fbf 381 uint32_t aux_clock_divider;
6b4e0a93 382 int try, precharge;
9ee32fea
DV		 383 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
384
385 /* dp aux is extremely sensitive to irq latency, hence request the
386 * lowest possible wakeup latency and so prevent the cpu from going into
387 * deep sleep states.
388 */
389 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 390
750eb99e 391 if (IS_HASWELL(dev)) {
174edf1f 392 switch (intel_dig_port->port) {
750eb99e
PZ		 393 case PORT_A:
394 ch_ctl = DPA_AUX_CH_CTL;
395 ch_data = DPA_AUX_CH_DATA1;
396 break;
397 case PORT_B:
398 ch_ctl = PCH_DPB_AUX_CH_CTL;
399 ch_data = PCH_DPB_AUX_CH_DATA1;
400 break;
401 case PORT_C:
402 ch_ctl = PCH_DPC_AUX_CH_CTL;
403 ch_data = PCH_DPC_AUX_CH_DATA1;
404 break;
405 case PORT_D:
406 ch_ctl = PCH_DPD_AUX_CH_CTL;
407 ch_data = PCH_DPD_AUX_CH_DATA1;
408 break;
409 default:
410 BUG();
411 }
412 }
413
9b984dae 414 intel_dp_check_edp(intel_dp);
a4fc5ed6 415 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 416 * and would like to run at 2MHz. So, take the
417 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 418 *
419 * Note that PCH attached eDP panels should use a 125MHz input
420 * clock divider.
a4fc5ed6 421 */
1c95822a 422 if (is_cpu_edp(intel_dp)) {
affa9354 423 if (HAS_DDI(dev))
b8fc2f6a
PZ		 424 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
425 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 426 aux_clock_divider = 100;
427 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 428 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 429 else
430 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
431 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 432 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 433 else
434 aux_clock_divider = intel_hrawclk(dev) / 2;
435
6b4e0a93
DV		 436 if (IS_GEN6(dev))
437 precharge = 3;
438 else
439 precharge = 5;
440
11bee43e
JB		 441 /* Try to wait for any previous AUX channel activity */
442 for (try = 0; try < 3; try++) {
ef04f00d 443 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 444 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
445 break;
446 msleep(1);
447 }
448
449 if (try == 3) {
450 WARN(1, "dp_aux_ch not started status 0x%08x\n",
451 I915_READ(ch_ctl));
9ee32fea
DV		 452 ret = -EBUSY;
453 goto out;
4f7f7b7e
CW		 454 }
455
fb0f8fbf
KP		 456 /* Must try at least 3 times according to DP spec */
457 for (try = 0; try < 5; try++) {
458 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 459 for (i = 0; i < send_bytes; i += 4)
460 I915_WRITE(ch_data + i,
461 pack_aux(send + i, send_bytes - i));
0206e353 462
fb0f8fbf 463 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 464 I915_WRITE(ch_ctl,
465 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 466 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 467 DP_AUX_CH_CTL_TIME_OUT_400us |
468 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
469 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
470 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
471 DP_AUX_CH_CTL_DONE |
472 DP_AUX_CH_CTL_TIME_OUT_ERROR |
473 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 474
475 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 476
fb0f8fbf 477 /* Clear done status and any errors */
4f7f7b7e
CW		 478 I915_WRITE(ch_ctl,
479 status |
480 DP_AUX_CH_CTL_DONE |
481 DP_AUX_CH_CTL_TIME_OUT_ERROR |
482 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 483
484 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
485 DP_AUX_CH_CTL_RECEIVE_ERROR))
486 continue;
4f7f7b7e 487 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 488 break;
489 }
490
a4fc5ed6 491 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 492 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 493 ret = -EBUSY;
494 goto out;
a4fc5ed6
KP		 495 }
496
497 /* Check for timeout or receive error.
498 * Timeouts occur when the sink is not connected
499 */
a5b3da54 500 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 501 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 502 ret = -EIO;
503 goto out;
a5b3da54 504 }
1ae8c0a5
KP		 505
506 /* Timeouts occur when the device isn't connected, so they're
507 * "normal" -- don't fill the kernel log with these */
a5b3da54 508 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 509 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 510 ret = -ETIMEDOUT;
511 goto out;
a4fc5ed6
KP		 512 }
513
514 /* Unload any bytes sent back from the other side */
515 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
516 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 517 if (recv_bytes > recv_size)
518 recv_bytes = recv_size;
0206e353 519
4f7f7b7e
CW		 520 for (i = 0; i < recv_bytes; i += 4)
521 unpack_aux(I915_READ(ch_data + i),
522 recv + i, recv_bytes - i);
a4fc5ed6 523
9ee32fea
DV		 524 ret = recv_bytes;
525out:
526 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
527
528 return ret;
a4fc5ed6
KP		 529}
530
531/* Write data to the aux channel in native mode */
532static int
ea5b213a 533intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 534 uint16_t address, uint8_t *send, int send_bytes)
535{
536 int ret;
537 uint8_t msg[20];
538 int msg_bytes;
539 uint8_t ack;
540
9b984dae 541 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 542 if (send_bytes > 16)
543 return -1;
544 msg[0] = AUX_NATIVE_WRITE << 4;
545 msg[1] = address >> 8;
eebc863e 546 msg[2] = address & 0xff;
a4fc5ed6
KP		 547 msg[3] = send_bytes - 1;
548 memcpy(&msg[4], send, send_bytes);
549 msg_bytes = send_bytes + 4;
550 for (;;) {
ea5b213a 551 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 552 if (ret < 0)
553 return ret;
554 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
555 break;
556 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
557 udelay(100);
558 else
a5b3da54 559 return -EIO;
a4fc5ed6
KP		 560 }
561 return send_bytes;
562}
563
564/* Write a single byte to the aux channel in native mode */
565static int
ea5b213a 566intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 567 uint16_t address, uint8_t byte)
568{
ea5b213a 569 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 570}
571
572/* read bytes from a native aux channel */
573static int
ea5b213a 574intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 575 uint16_t address, uint8_t *recv, int recv_bytes)
576{
577 uint8_t msg[4];
578 int msg_bytes;
579 uint8_t reply[20];
580 int reply_bytes;
581 uint8_t ack;
582 int ret;
583
9b984dae 584 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 585 msg[0] = AUX_NATIVE_READ << 4;
586 msg[1] = address >> 8;
587 msg[2] = address & 0xff;
588 msg[3] = recv_bytes - 1;
589
590 msg_bytes = 4;
591 reply_bytes = recv_bytes + 1;
592
593 for (;;) {
ea5b213a 594 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 595 reply, reply_bytes);
a5b3da54
KP		 596 if (ret == 0)
597 return -EPROTO;
598 if (ret < 0)
a4fc5ed6
KP		 599 return ret;
600 ack = reply[0];
601 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
602 memcpy(recv, reply + 1, ret - 1);
603 return ret - 1;
604 }
605 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
606 udelay(100);
607 else
a5b3da54 608 return -EIO;
a4fc5ed6
KP		 609 }
610}
611
612static int
ab2c0672
DA		 613intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
614 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 615{
ab2c0672 616 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 617 struct intel_dp *intel_dp = container_of(adapter,
618 struct intel_dp,
619 adapter);
ab2c0672
DA		 620 uint16_t address = algo_data->address;
621 uint8_t msg[5];
622 uint8_t reply[2];
8316f337 623 unsigned retry;
ab2c0672
DA		 624 int msg_bytes;
625 int reply_bytes;
626 int ret;
627
9b984dae 628 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 629 /* Set up the command byte */
630 if (mode & MODE_I2C_READ)
631 msg[0] = AUX_I2C_READ << 4;
632 else
633 msg[0] = AUX_I2C_WRITE << 4;
634
635 if (!(mode & MODE_I2C_STOP))
636 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 637
ab2c0672
DA		 638 msg[1] = address >> 8;
639 msg[2] = address;
640
641 switch (mode) {
642 case MODE_I2C_WRITE:
643 msg[3] = 0;
644 msg[4] = write_byte;
645 msg_bytes = 5;
646 reply_bytes = 1;
647 break;
648 case MODE_I2C_READ:
649 msg[3] = 0;
650 msg_bytes = 4;
651 reply_bytes = 2;
652 break;
653 default:
654 msg_bytes = 3;
655 reply_bytes = 1;
656 break;
657 }
658
8316f337
DF		 659 for (retry = 0; retry < 5; retry++) {
660 ret = intel_dp_aux_ch(intel_dp,
661 msg, msg_bytes,
662 reply, reply_bytes);
ab2c0672 663 if (ret < 0) {
3ff99164 664 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 665 return ret;
666 }
8316f337
DF		 667
668 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
669 case AUX_NATIVE_REPLY_ACK:
670 /* I2C-over-AUX Reply field is only valid
671 * when paired with AUX ACK.
672 */
673 break;
674 case AUX_NATIVE_REPLY_NACK:
675 DRM_DEBUG_KMS("aux_ch native nack\n");
676 return -EREMOTEIO;
677 case AUX_NATIVE_REPLY_DEFER:
678 udelay(100);
679 continue;
680 default:
681 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
682 reply[0]);
683 return -EREMOTEIO;
684 }
685
ab2c0672
DA		 686 switch (reply[0] & AUX_I2C_REPLY_MASK) {
687 case AUX_I2C_REPLY_ACK:
688 if (mode == MODE_I2C_READ) {
689 *read_byte = reply[1];
690 }
691 return reply_bytes - 1;
692 case AUX_I2C_REPLY_NACK:
8316f337 693 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 694 return -EREMOTEIO;
695 case AUX_I2C_REPLY_DEFER:
8316f337 696 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 697 udelay(100);
698 break;
699 default:
8316f337 700 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 701 return -EREMOTEIO;
702 }
703 }
8316f337
DF		 704
705 DRM_ERROR("too many retries, giving up\n");
706 return -EREMOTEIO;
a4fc5ed6
KP		 707}
708
709static int
ea5b213a 710intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 711 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 712{
0b5c541b
KP		 713 int ret;
714
d54e9d28 715 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 716 intel_dp->algo.running = false;
717 intel_dp->algo.address = 0;
718 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
719
0206e353 720 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 721 intel_dp->adapter.owner = THIS_MODULE;
722 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 723 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 724 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
725 intel_dp->adapter.algo_data = &intel_dp->algo;
726 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
727
0b5c541b
KP		 728 ironlake_edp_panel_vdd_on(intel_dp);
729 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 730 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 731 return ret;
a4fc5ed6
KP		 732}
733
00c09d70 734bool
e811f5ae
LP		 735intel_dp_mode_fixup(struct drm_encoder *encoder,
736 const struct drm_display_mode *mode,
a4fc5ed6
KP		 737 struct drm_display_mode *adjusted_mode)
738{
0d3a1bee 739 struct drm_device *dev = encoder->dev;
ea5b213a 740 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 741 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 742 int lane_count, clock;
397fe157 743 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 744 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 745 int bpp, mode_rate;
a4fc5ed6
KP		 746 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
747
dd06f90e
JN		 748 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
749 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
750 adjusted_mode);
53b41837
YN		 751 intel_pch_panel_fitting(dev,
752 intel_connector->panel.fitting_mode,
1d8e1c75 753 mode, adjusted_mode);
0d3a1bee
ZY		 754 }
755
cb1793ce 756 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 757 return false;
758
083f9560
DV		 759 DRM_DEBUG_KMS("DP link computation with max lane count %i "
760 "max bw %02x pixel clock %iKHz\n",
71244653 761 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 762
cb1793ce 763 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 764 return false;
765
766 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
3685a8f3 767
55bc60db
VS		 768 if (intel_dp->color_range_auto) {
769 /*
770 * See:
771 * CEA-861-E - 5.1 Default Encoding Parameters
772 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
773 */
18316c8c 774 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 775 intel_dp->color_range = DP_COLOR_RANGE_16_235;
776 else
777 intel_dp->color_range = 0;
778 }
779
3685a8f3
VS		 780 if (intel_dp->color_range)
781 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
782
71244653 783 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 784
2514bc51
JB		 785 for (clock = 0; clock <= max_clock; clock++) {
786 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
9fa5f652
PZ		 787 int link_bw_clock =
788 drm_dp_bw_code_to_link_rate(bws[clock]);
789 int link_avail = intel_dp_max_data_rate(link_bw_clock,
790 lane_count);
a4fc5ed6 791
083f9560 792 if (mode_rate <= link_avail) {
ea5b213a
CW		 793 intel_dp->link_bw = bws[clock];
794 intel_dp->lane_count = lane_count;
9fa5f652 795 adjusted_mode->clock = link_bw_clock;
083f9560
DV		 796 DRM_DEBUG_KMS("DP link bw %02x lane "
797 "count %d clock %d bpp %d\n",
ea5b213a 798 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 799 adjusted_mode->clock, bpp);
800 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
801 mode_rate, link_avail);
a4fc5ed6
KP		 802 return true;
803 }
804 }
805 }
fe27d53e 806
a4fc5ed6
KP		 807 return false;
808}
809
a4fc5ed6
KP		 810void
811intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode)
813{
814 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 815 struct intel_encoder *intel_encoder;
816 struct intel_dp *intel_dp;
a4fc5ed6
KP		 817 struct drm_i915_private *dev_priv = dev->dev_private;
818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 819 int lane_count = 4;
e69d0bc1 820 struct intel_link_m_n m_n;
9db4a9c7 821 int pipe = intel_crtc->pipe;
afe2fcf5 822 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 823
824 /*
21d40d37 825 * Find the lane count in the intel_encoder private
a4fc5ed6 826 */
fa90ecef
PZ		 827 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
828 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 829
fa90ecef
PZ		 830 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
831 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 832 {
ea5b213a 833 lane_count = intel_dp->lane_count;
51190667 834 break;
a4fc5ed6
KP		 835 }
836 }
837
838 /*
839 * Compute the GMCH and Link ratios. The '3' here is
840 * the number of bytes_per_pixel post-LUT, which we always
841 * set up for 8-bits of R/G/B, or 3 bytes total.
842 */
e69d0bc1
DV		 843 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
844 mode->clock, adjusted_mode->clock, &m_n);
a4fc5ed6 845
1eb8dfec 846 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 847 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
848 TU_SIZE(m_n.tu) | m_n.gmch_m);
849 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
850 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
851 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 852 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 853 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 854 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
855 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
856 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 857 } else if (IS_VALLEYVIEW(dev)) {
858 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
859 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
860 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
861 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 862 } else {
9db4a9c7 863 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 864 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 865 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
866 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
867 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 868 }
869}
870
247d89f6
PZ		 871void intel_dp_init_link_config(struct intel_dp *intel_dp)
872{
873 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
874 intel_dp->link_configuration[0] = intel_dp->link_bw;
875 intel_dp->link_configuration[1] = intel_dp->lane_count;
876 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
877 /*
878 * Check for DPCD version > 1.1 and enhanced framing support
879 */
880 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
881 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
882 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
883 }
884}
885
ea9b6006
DV		 886static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
887{
888 struct drm_device *dev = crtc->dev;
889 struct drm_i915_private *dev_priv = dev->dev_private;
890 u32 dpa_ctl;
891
892 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
893 dpa_ctl = I915_READ(DP_A);
894 dpa_ctl &= ~DP_PLL_FREQ_MASK;
895
896 if (clock < 200000) {
1ce17038
DV		 897 /* For a long time we've carried around a ILK-DevA w/a for the
898 * 160MHz clock. If we're really unlucky, it's still required.
899 */
900 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 901 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 902 } else {
903 dpa_ctl |= DP_PLL_FREQ_270MHZ;
904 }
1ce17038 905
ea9b6006
DV		 906 I915_WRITE(DP_A, dpa_ctl);
907
908 POSTING_READ(DP_A);
909 udelay(500);
910}
911
a4fc5ed6
KP		 912static void
913intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
914 struct drm_display_mode *adjusted_mode)
915{
e3421a18 916 struct drm_device *dev = encoder->dev;
417e822d 917 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 918 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 919 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
921
417e822d 922 /*
1a2eb460 923 * There are four kinds of DP registers:
417e822d
KP		 924 *
925 * IBX PCH
1a2eb460
KP		 926 * SNB CPU
927 * IVB CPU
417e822d
KP		 928 * CPT PCH
929 *
930 * IBX PCH and CPU are the same for almost everything,
931 * except that the CPU DP PLL is configured in this
932 * register
933 *
934 * CPT PCH is quite different, having many bits moved
935 * to the TRANS_DP_CTL register instead. That
936 * configuration happens (oddly) in ironlake_pch_enable
937 */
9c9e7927 938
417e822d
KP		 939 /* Preserve the BIOS-computed detected bit. This is
940 * supposed to be read-only.
941 */
942 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 943
417e822d 944 /* Handle DP bits in common between all three register formats */
417e822d 945 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 946
ea5b213a 947 switch (intel_dp->lane_count) {
a4fc5ed6 948 case 1:
ea5b213a 949 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 950 break;
951 case 2:
ea5b213a 952 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 953 break;
954 case 4:
ea5b213a 955 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 956 break;
957 }
e0dac65e
WF		 958 if (intel_dp->has_audio) {
959 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
960 pipe_name(intel_crtc->pipe));
ea5b213a 961 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 962 intel_write_eld(encoder, adjusted_mode);
963 }
247d89f6
PZ		 964
965 intel_dp_init_link_config(intel_dp);
a4fc5ed6 966
417e822d 967 /* Split out the IBX/CPU vs CPT settings */
32f9d658 968
19c03924 969 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 970 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
971 intel_dp->DP |= DP_SYNC_HS_HIGH;
972 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
973 intel_dp->DP |= DP_SYNC_VS_HIGH;
974 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
975
976 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
977 intel_dp->DP |= DP_ENHANCED_FRAMING;
978
979 intel_dp->DP |= intel_crtc->pipe << 29;
980
981 /* don't miss out required setting for eDP */
1a2eb460
KP		 982 if (adjusted_mode->clock < 200000)
983 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
984 else
985 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
986 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
3685a8f3
VS		 987 if (!HAS_PCH_SPLIT(dev))
988 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 989
990 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
991 intel_dp->DP |= DP_SYNC_HS_HIGH;
992 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
993 intel_dp->DP |= DP_SYNC_VS_HIGH;
994 intel_dp->DP |= DP_LINK_TRAIN_OFF;
995
996 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
997 intel_dp->DP |= DP_ENHANCED_FRAMING;
998
999 if (intel_crtc->pipe == 1)
1000 intel_dp->DP |= DP_PIPEB_SELECT;
1001
1002 if (is_cpu_edp(intel_dp)) {
1003 /* don't miss out required setting for eDP */
417e822d
KP		 1004 if (adjusted_mode->clock < 200000)
1005 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1006 else
1007 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1008 }
1009 } else {
1010 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1011 }
ea9b6006
DV		 1012
1013 if (is_cpu_edp(intel_dp))
1014 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 1015}
1016
99ea7127
KP		 1017#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1018#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1019
1020#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1021#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1022
1023#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1024#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1025
1026static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1027 u32 mask,
1028 u32 value)
bd943159 1029{
30add22d 1030 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1031 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 1032
99ea7127
KP		 1033 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1034 mask, value,
1035 I915_READ(PCH_PP_STATUS),
1036 I915_READ(PCH_PP_CONTROL));
32ce697c 1037
99ea7127
KP		 1038 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1039 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1040 I915_READ(PCH_PP_STATUS),
1041 I915_READ(PCH_PP_CONTROL));
32ce697c 1042 }
99ea7127 1043}
32ce697c 1044
99ea7127
KP		 1045static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1046{
1047 DRM_DEBUG_KMS("Wait for panel power on\n");
1048 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1049}
1050
99ea7127
KP		 1051static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1052{
1053 DRM_DEBUG_KMS("Wait for panel power off time\n");
1054 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1055}
1056
1057static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1058{
1059 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1060 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061}
1062
1063
832dd3c1
KP		 1064/* Read the current pp_control value, unlocking the register if it
1065 * is locked
1066 */
1067
1068static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1069{
1070 u32 control = I915_READ(PCH_PP_CONTROL);
1071
1072 control &= ~PANEL_UNLOCK_MASK;
1073 control |= PANEL_UNLOCK_REGS;
1074 return control;
bd943159
KP		 1075}
1076
82a4d9c0 1077void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1078{
30add22d 1079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 u32 pp;
1082
97af61f5
KP		 1083 if (!is_edp(intel_dp))
1084 return;
f01eca2e 1085 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1086
bd943159
KP		 1087 WARN(intel_dp->want_panel_vdd,
1088 "eDP VDD already requested on\n");
1089
1090 intel_dp->want_panel_vdd = true;
99ea7127 1091
bd943159
KP		 1092 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1093 DRM_DEBUG_KMS("eDP VDD already on\n");
1094 return;
1095 }
1096
99ea7127
KP		 1097 if (!ironlake_edp_have_panel_power(intel_dp))
1098 ironlake_wait_panel_power_cycle(intel_dp);
1099
832dd3c1 1100 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1101 pp |= EDP_FORCE_VDD;
1102 I915_WRITE(PCH_PP_CONTROL, pp);
1103 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1104 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1105 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1106
1107 /*
1108 * If the panel wasn't on, delay before accessing aux channel
1109 */
1110 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1111 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1112 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1113 }
5d613501
JB		 1114}
1115
bd943159 1116static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1117{
30add22d 1118 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 u32 pp;
1121
a0e99e68
DV		 1122 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1123
bd943159 1124 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1125 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1126 pp &= ~EDP_FORCE_VDD;
1127 I915_WRITE(PCH_PP_CONTROL, pp);
1128 POSTING_READ(PCH_PP_CONTROL);
1129
1130 /* Make sure sequencer is idle before allowing subsequent activity */
1131 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1132 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1133
1134 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1135 }
1136}
5d613501 1137
bd943159
KP		 1138static void ironlake_panel_vdd_work(struct work_struct *__work)
1139{
1140 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1141 struct intel_dp, panel_vdd_work);
30add22d 1142 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1143
627f7675 1144 mutex_lock(&dev->mode_config.mutex);
bd943159 1145 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1146 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1147}
1148
82a4d9c0 1149void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1150{
97af61f5
KP		 1151 if (!is_edp(intel_dp))
1152 return;
5d613501 1153
bd943159
KP		 1154 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1155 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1156
bd943159
KP		 1157 intel_dp->want_panel_vdd = false;
1158
1159 if (sync) {
1160 ironlake_panel_vdd_off_sync(intel_dp);
1161 } else {
1162 /*
1163 * Queue the timer to fire a long
1164 * time from now (relative to the power down delay)
1165 * to keep the panel power up across a sequence of operations
1166 */
1167 schedule_delayed_work(&intel_dp->panel_vdd_work,
1168 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1169 }
5d613501
JB		 1170}
1171
82a4d9c0 1172void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1173{
30add22d 1174 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1175 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1176 u32 pp;
9934c132 1177
97af61f5 1178 if (!is_edp(intel_dp))
bd943159 1179 return;
99ea7127
KP		 1180
1181 DRM_DEBUG_KMS("Turn eDP power on\n");
1182
1183 if (ironlake_edp_have_panel_power(intel_dp)) {
1184 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1185 return;
99ea7127 1186 }
9934c132 1187
99ea7127 1188 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1189
99ea7127 1190 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1191 if (IS_GEN5(dev)) {
1192 /* ILK workaround: disable reset around power sequence */
1193 pp &= ~PANEL_POWER_RESET;
1194 I915_WRITE(PCH_PP_CONTROL, pp);
1195 POSTING_READ(PCH_PP_CONTROL);
1196 }
37c6c9b0 1197
1c0ae80a 1198 pp |= POWER_TARGET_ON;
99ea7127
KP		 1199 if (!IS_GEN5(dev))
1200 pp |= PANEL_POWER_RESET;
1201
9934c132 1202 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1203 POSTING_READ(PCH_PP_CONTROL);
9934c132 1204
99ea7127 1205 ironlake_wait_panel_on(intel_dp);
9934c132 1206
05ce1a49
KP		 1207 if (IS_GEN5(dev)) {
1208 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1209 I915_WRITE(PCH_PP_CONTROL, pp);
1210 POSTING_READ(PCH_PP_CONTROL);
1211 }
9934c132
JB		 1212}
1213
82a4d9c0 1214void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1215{
30add22d 1216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1217 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1218 u32 pp;
9934c132 1219
97af61f5
KP		 1220 if (!is_edp(intel_dp))
1221 return;
37c6c9b0 1222
99ea7127 1223 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1224
6cb49835 1225 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1226
99ea7127 1227 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1228 /* We need to switch off panel power _and_ force vdd, for otherwise some
1229 * panels get very unhappy and cease to work. */
1230 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1231 I915_WRITE(PCH_PP_CONTROL, pp);
1232 POSTING_READ(PCH_PP_CONTROL);
9934c132 1233
35a38556
DV		 1234 intel_dp->want_panel_vdd = false;
1235
99ea7127 1236 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1237}
1238
d6c50ff8 1239void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1240{
da63a9f2
PZ		 1241 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1242 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1243 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1244 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1245 u32 pp;
1246
f01eca2e
KP		 1247 if (!is_edp(intel_dp))
1248 return;
1249
28c97730 1250 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1251 /*
1252 * If we enable the backlight right away following a panel power
1253 * on, we may see slight flicker as the panel syncs with the eDP
1254 * link. So delay a bit to make sure the image is solid before
1255 * allowing it to appear.
1256 */
f01eca2e 1257 msleep(intel_dp->backlight_on_delay);
832dd3c1 1258 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1259 pp |= EDP_BLC_ENABLE;
1260 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1261 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1262
1263 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1264}
1265
d6c50ff8 1266void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1267{
30add22d 1268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 u32 pp;
1271
f01eca2e
KP		 1272 if (!is_edp(intel_dp))
1273 return;
1274
035aa3de
DV		 1275 intel_panel_disable_backlight(dev);
1276
28c97730 1277 DRM_DEBUG_KMS("\n");
832dd3c1 1278 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1279 pp &= ~EDP_BLC_ENABLE;
1280 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1281 POSTING_READ(PCH_PP_CONTROL);
1282 msleep(intel_dp->backlight_off_delay);
32f9d658 1283}
a4fc5ed6 1284
2bd2ad64 1285static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1286{
da63a9f2
PZ		 1287 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1288 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1289 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 u32 dpa_ctl;
1292
2bd2ad64
DV		 1293 assert_pipe_disabled(dev_priv,
1294 to_intel_crtc(crtc)->pipe);
1295
d240f20f
JB		 1296 DRM_DEBUG_KMS("\n");
1297 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1298 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1299 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1300
1301 /* We don't adjust intel_dp->DP while tearing down the link, to
1302 * facilitate link retraining (e.g. after hotplug). Hence clear all
1303 * enable bits here to ensure that we don't enable too much. */
1304 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1305 intel_dp->DP |= DP_PLL_ENABLE;
1306 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1307 POSTING_READ(DP_A);
1308 udelay(200);
d240f20f
JB		 1309}
1310
2bd2ad64 1311static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1312{
da63a9f2
PZ		 1313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1314 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1315 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 u32 dpa_ctl;
1318
2bd2ad64
DV		 1319 assert_pipe_disabled(dev_priv,
1320 to_intel_crtc(crtc)->pipe);
1321
d240f20f 1322 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1323 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1324 "dp pll off, should be on\n");
1325 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1326
1327 /* We can't rely on the value tracked for the DP register in
1328 * intel_dp->DP because link_down must not change that (otherwise link
1329 * re-training will fail. */
298b0b39 1330 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1331 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1332 POSTING_READ(DP_A);
d240f20f
JB		 1333 udelay(200);
1334}
1335
c7ad3810 1336/* If the sink supports it, try to set the power state appropriately */
c19b0669 1337void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1338{
1339 int ret, i;
1340
1341 /* Should have a valid DPCD by this point */
1342 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1343 return;
1344
1345 if (mode != DRM_MODE_DPMS_ON) {
1346 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1347 DP_SET_POWER_D3);
1348 if (ret != 1)
1349 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1350 } else {
1351 /*
1352 * When turning on, we need to retry for 1ms to give the sink
1353 * time to wake up.
1354 */
1355 for (i = 0; i < 3; i++) {
1356 ret = intel_dp_aux_native_write_1(intel_dp,
1357 DP_SET_POWER,
1358 DP_SET_POWER_D0);
1359 if (ret == 1)
1360 break;
1361 msleep(1);
1362 }
1363 }
1364}
1365
19d8fe15
DV		 1366static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1367 enum pipe *pipe)
d240f20f 1368{
19d8fe15
DV		 1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1370 struct drm_device *dev = encoder->base.dev;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 u32 tmp = I915_READ(intel_dp->output_reg);
1373
1374 if (!(tmp & DP_PORT_EN))
1375 return false;
1376
1377 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1378 *pipe = PORT_TO_PIPE_CPT(tmp);
1379 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1380 *pipe = PORT_TO_PIPE(tmp);
1381 } else {
1382 u32 trans_sel;
1383 u32 trans_dp;
1384 int i;
1385
1386 switch (intel_dp->output_reg) {
1387 case PCH_DP_B:
1388 trans_sel = TRANS_DP_PORT_SEL_B;
1389 break;
1390 case PCH_DP_C:
1391 trans_sel = TRANS_DP_PORT_SEL_C;
1392 break;
1393 case PCH_DP_D:
1394 trans_sel = TRANS_DP_PORT_SEL_D;
1395 break;
1396 default:
1397 return true;
1398 }
1399
1400 for_each_pipe(i) {
1401 trans_dp = I915_READ(TRANS_DP_CTL(i));
1402 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1403 *pipe = i;
1404 return true;
1405 }
1406 }
19d8fe15 1407
4a0833ec
DV		 1408 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1409 intel_dp->output_reg);
1410 }
d240f20f 1411
19d8fe15
DV		 1412 return true;
1413}
d240f20f 1414
e8cb4558 1415static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1416{
e8cb4558 1417 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1418
1419 /* Make sure the panel is off before trying to change the mode. But also
1420 * ensure that we have vdd while we switch off the panel. */
1421 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1422 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1423 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1424 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1425
1426 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1427 if (!is_cpu_edp(intel_dp))
1428 intel_dp_link_down(intel_dp);
d240f20f
JB		 1429}
1430
2bd2ad64 1431static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1432{
2bd2ad64
DV		 1433 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1434
3739850b
DV		 1435 if (is_cpu_edp(intel_dp)) {
1436 intel_dp_link_down(intel_dp);
2bd2ad64 1437 ironlake_edp_pll_off(intel_dp);
3739850b 1438 }
2bd2ad64
DV		 1439}
1440
e8cb4558 1441static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1442{
e8cb4558
DV		 1443 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1447
0c33d8d7
DV		 1448 if (WARN_ON(dp_reg & DP_PORT_EN))
1449 return;
5d613501 1450
97af61f5 1451 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1452 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1453 intel_dp_start_link_train(intel_dp);
97af61f5 1454 ironlake_edp_panel_on(intel_dp);
bd943159 1455 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1456 intel_dp_complete_link_train(intel_dp);
f01eca2e 1457 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1458}
1459
2bd2ad64 1460static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1461{
2bd2ad64 1462 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 1463
2bd2ad64
DV		 1464 if (is_cpu_edp(intel_dp))
1465 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1466}
1467
1468/*
df0c237d
JB		 1469 * Native read with retry for link status and receiver capability reads for
1470 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1471 */
1472static bool
df0c237d
JB		 1473intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1474 uint8_t *recv, int recv_bytes)
a4fc5ed6 1475{
61da5fab
JB		 1476 int ret, i;
1477
df0c237d
JB		 1478 /*
1479 * Sinks are *supposed* to come up within 1ms from an off state,
1480 * but we're also supposed to retry 3 times per the spec.
1481 */
61da5fab 1482 for (i = 0; i < 3; i++) {
df0c237d
JB		 1483 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1484 recv_bytes);
1485 if (ret == recv_bytes)
61da5fab
JB		 1486 return true;
1487 msleep(1);
1488 }
a4fc5ed6 1489
61da5fab 1490 return false;
a4fc5ed6
KP		 1491}
1492
1493/*
1494 * Fetch AUX CH registers 0x202 - 0x207 which contain
1495 * link status information
1496 */
1497static bool
93f62dad 1498intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1499{
df0c237d
JB		 1500 return intel_dp_aux_native_read_retry(intel_dp,
1501 DP_LANE0_1_STATUS,
93f62dad 1502 link_status,
df0c237d 1503 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1504}
1505
a4fc5ed6
KP		 1506#if 0
1507static char *voltage_names[] = {
1508 "0.4V", "0.6V", "0.8V", "1.2V"
1509};
1510static char *pre_emph_names[] = {
1511 "0dB", "3.5dB", "6dB", "9.5dB"
1512};
1513static char *link_train_names[] = {
1514 "pattern 1", "pattern 2", "idle", "off"
1515};
1516#endif
1517
1518/*
1519 * These are source-specific values; current Intel hardware supports
1520 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1521 */
a4fc5ed6
KP		 1522
1523static uint8_t
1a2eb460 1524intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1525{
30add22d 1526 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1527
1528 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1529 return DP_TRAIN_VOLTAGE_SWING_800;
1530 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1531 return DP_TRAIN_VOLTAGE_SWING_1200;
1532 else
1533 return DP_TRAIN_VOLTAGE_SWING_800;
1534}
1535
1536static uint8_t
1537intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1538{
30add22d 1539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1540
d6c0d722
PZ		 1541 if (IS_HASWELL(dev)) {
1542 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1543 case DP_TRAIN_VOLTAGE_SWING_400:
1544 return DP_TRAIN_PRE_EMPHASIS_9_5;
1545 case DP_TRAIN_VOLTAGE_SWING_600:
1546 return DP_TRAIN_PRE_EMPHASIS_6;
1547 case DP_TRAIN_VOLTAGE_SWING_800:
1548 return DP_TRAIN_PRE_EMPHASIS_3_5;
1549 case DP_TRAIN_VOLTAGE_SWING_1200:
1550 default:
1551 return DP_TRAIN_PRE_EMPHASIS_0;
1552 }
1553 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1554 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1555 case DP_TRAIN_VOLTAGE_SWING_400:
1556 return DP_TRAIN_PRE_EMPHASIS_6;
1557 case DP_TRAIN_VOLTAGE_SWING_600:
1558 case DP_TRAIN_VOLTAGE_SWING_800:
1559 return DP_TRAIN_PRE_EMPHASIS_3_5;
1560 default:
1561 return DP_TRAIN_PRE_EMPHASIS_0;
1562 }
1563 } else {
1564 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1565 case DP_TRAIN_VOLTAGE_SWING_400:
1566 return DP_TRAIN_PRE_EMPHASIS_6;
1567 case DP_TRAIN_VOLTAGE_SWING_600:
1568 return DP_TRAIN_PRE_EMPHASIS_6;
1569 case DP_TRAIN_VOLTAGE_SWING_800:
1570 return DP_TRAIN_PRE_EMPHASIS_3_5;
1571 case DP_TRAIN_VOLTAGE_SWING_1200:
1572 default:
1573 return DP_TRAIN_PRE_EMPHASIS_0;
1574 }
a4fc5ed6
KP		 1575 }
1576}
1577
1578static void
93f62dad 1579intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1580{
1581 uint8_t v = 0;
1582 uint8_t p = 0;
1583 int lane;
1a2eb460
KP		 1584 uint8_t voltage_max;
1585 uint8_t preemph_max;
a4fc5ed6 1586
33a34e4e 1587 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1588 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1589 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1590
1591 if (this_v > v)
1592 v = this_v;
1593 if (this_p > p)
1594 p = this_p;
1595 }
1596
1a2eb460 1597 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1598 if (v >= voltage_max)
1599 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1600
1a2eb460
KP		 1601 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1602 if (p >= preemph_max)
1603 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1604
1605 for (lane = 0; lane < 4; lane++)
33a34e4e 1606 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1607}
1608
1609static uint32_t
f0a3424e 1610intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1611{
3cf2efb1 1612 uint32_t signal_levels = 0;
a4fc5ed6 1613
3cf2efb1 1614 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1615 case DP_TRAIN_VOLTAGE_SWING_400:
1616 default:
1617 signal_levels |= DP_VOLTAGE_0_4;
1618 break;
1619 case DP_TRAIN_VOLTAGE_SWING_600:
1620 signal_levels |= DP_VOLTAGE_0_6;
1621 break;
1622 case DP_TRAIN_VOLTAGE_SWING_800:
1623 signal_levels |= DP_VOLTAGE_0_8;
1624 break;
1625 case DP_TRAIN_VOLTAGE_SWING_1200:
1626 signal_levels |= DP_VOLTAGE_1_2;
1627 break;
1628 }
3cf2efb1 1629 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1630 case DP_TRAIN_PRE_EMPHASIS_0:
1631 default:
1632 signal_levels |= DP_PRE_EMPHASIS_0;
1633 break;
1634 case DP_TRAIN_PRE_EMPHASIS_3_5:
1635 signal_levels |= DP_PRE_EMPHASIS_3_5;
1636 break;
1637 case DP_TRAIN_PRE_EMPHASIS_6:
1638 signal_levels |= DP_PRE_EMPHASIS_6;
1639 break;
1640 case DP_TRAIN_PRE_EMPHASIS_9_5:
1641 signal_levels |= DP_PRE_EMPHASIS_9_5;
1642 break;
1643 }
1644 return signal_levels;
1645}
1646
e3421a18
ZW		 1647/* Gen6's DP voltage swing and pre-emphasis control */
1648static uint32_t
1649intel_gen6_edp_signal_levels(uint8_t train_set)
1650{
3c5a62b5
YL		 1651 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1652 DP_TRAIN_PRE_EMPHASIS_MASK);
1653 switch (signal_levels) {
e3421a18 1654 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1655 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1656 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1657 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1658 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1659 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1660 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1661 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1662 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1663 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1664 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1665 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1666 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1667 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1668 default:
3c5a62b5
YL		 1669 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1670 "0x%x\n", signal_levels);
1671 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1672 }
1673}
1674
1a2eb460
KP		 1675/* Gen7's DP voltage swing and pre-emphasis control */
1676static uint32_t
1677intel_gen7_edp_signal_levels(uint8_t train_set)
1678{
1679 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1680 DP_TRAIN_PRE_EMPHASIS_MASK);
1681 switch (signal_levels) {
1682 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1683 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1684 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1685 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1686 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1687 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1688
1689 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1690 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1691 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1692 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1693
1694 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1695 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1696 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1697 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1698
1699 default:
1700 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1701 "0x%x\n", signal_levels);
1702 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1703 }
1704}
1705
d6c0d722
PZ		 1706/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1707static uint32_t
f0a3424e 1708intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1709{
d6c0d722
PZ		 1710 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1711 DP_TRAIN_PRE_EMPHASIS_MASK);
1712 switch (signal_levels) {
1713 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1714 return DDI_BUF_EMP_400MV_0DB_HSW;
1715 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1716 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1717 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1718 return DDI_BUF_EMP_400MV_6DB_HSW;
1719 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1720 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1721
d6c0d722
PZ		 1722 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1723 return DDI_BUF_EMP_600MV_0DB_HSW;
1724 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1725 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1726 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1727 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1728
d6c0d722
PZ		 1729 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1730 return DDI_BUF_EMP_800MV_0DB_HSW;
1731 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1732 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1733 default:
1734 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1735 "0x%x\n", signal_levels);
1736 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1737 }
a4fc5ed6
KP		 1738}
1739
f0a3424e
PZ		 1740/* Properly updates "DP" with the correct signal levels. */
1741static void
1742intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1743{
1744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1745 struct drm_device *dev = intel_dig_port->base.base.dev;
1746 uint32_t signal_levels, mask;
1747 uint8_t train_set = intel_dp->train_set[0];
1748
1749 if (IS_HASWELL(dev)) {
1750 signal_levels = intel_hsw_signal_levels(train_set);
1751 mask = DDI_BUF_EMP_MASK;
1752 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1753 signal_levels = intel_gen7_edp_signal_levels(train_set);
1754 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1755 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1756 signal_levels = intel_gen6_edp_signal_levels(train_set);
1757 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1758 } else {
1759 signal_levels = intel_gen4_signal_levels(train_set);
1760 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1761 }
1762
1763 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1764
1765 *DP = (*DP & ~mask) | signal_levels;
1766}
1767
a4fc5ed6 1768static bool
ea5b213a 1769intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1770 uint32_t dp_reg_value,
58e10eb9 1771 uint8_t dp_train_pat)
a4fc5ed6 1772{
174edf1f
PZ		 1773 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1774 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1775 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1776 enum port port = intel_dig_port->port;
a4fc5ed6 1777 int ret;
d6c0d722 1778 uint32_t temp;
a4fc5ed6 1779
d6c0d722 1780 if (IS_HASWELL(dev)) {
174edf1f 1781 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1782
1783 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1784 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1785 else
1786 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1787
1788 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1789 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1790 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1791
10aa17c8
PZ		 1792 if (port != PORT_A) {
1793 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1794 I915_WRITE(DP_TP_CTL(port), temp);
1795
1796 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1797 DP_TP_STATUS_IDLE_DONE), 1))
1798 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1799
1800 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1801 }
d6c0d722 1802
d6c0d722
PZ		 1803 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1804
1805 break;
1806 case DP_TRAINING_PATTERN_1:
1807 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1808 break;
1809 case DP_TRAINING_PATTERN_2:
1810 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1811 break;
1812 case DP_TRAINING_PATTERN_3:
1813 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1814 break;
1815 }
174edf1f 1816 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1817
1818 } else if (HAS_PCH_CPT(dev) &&
1819 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1820 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1821
1822 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1823 case DP_TRAINING_PATTERN_DISABLE:
1824 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1825 break;
1826 case DP_TRAINING_PATTERN_1:
1827 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1828 break;
1829 case DP_TRAINING_PATTERN_2:
1830 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1831 break;
1832 case DP_TRAINING_PATTERN_3:
1833 DRM_ERROR("DP training pattern 3 not supported\n");
1834 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1835 break;
1836 }
1837
1838 } else {
1839 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1840
1841 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1842 case DP_TRAINING_PATTERN_DISABLE:
1843 dp_reg_value |= DP_LINK_TRAIN_OFF;
1844 break;
1845 case DP_TRAINING_PATTERN_1:
1846 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1847 break;
1848 case DP_TRAINING_PATTERN_2:
1849 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1850 break;
1851 case DP_TRAINING_PATTERN_3:
1852 DRM_ERROR("DP training pattern 3 not supported\n");
1853 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1854 break;
1855 }
1856 }
1857
ea5b213a
CW		 1858 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1859 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1860
ea5b213a 1861 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1862 DP_TRAINING_PATTERN_SET,
1863 dp_train_pat);
1864
47ea7542
PZ		 1865 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1866 DP_TRAINING_PATTERN_DISABLE) {
1867 ret = intel_dp_aux_native_write(intel_dp,
1868 DP_TRAINING_LANE0_SET,
1869 intel_dp->train_set,
1870 intel_dp->lane_count);
1871 if (ret != intel_dp->lane_count)
1872 return false;
1873 }
a4fc5ed6
KP		 1874
1875 return true;
1876}
1877
33a34e4e 1878/* Enable corresponding port and start training pattern 1 */
c19b0669 1879void
33a34e4e 1880intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1881{
da63a9f2 1882 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1883 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1884 int i;
1885 uint8_t voltage;
1886 bool clock_recovery = false;
cdb0e95b 1887 int voltage_tries, loop_tries;
ea5b213a 1888 uint32_t DP = intel_dp->DP;
a4fc5ed6 1889
affa9354 1890 if (HAS_DDI(dev))
c19b0669
PZ		 1891 intel_ddi_prepare_link_retrain(encoder);
1892
3cf2efb1
CW		 1893 /* Write the link configuration data */
1894 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1895 intel_dp->link_configuration,
1896 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1897
1898 DP |= DP_PORT_EN;
1a2eb460 1899
33a34e4e 1900 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1901 voltage = 0xff;
cdb0e95b
KP		 1902 voltage_tries = 0;
1903 loop_tries = 0;
a4fc5ed6
KP		 1904 clock_recovery = false;
1905 for (;;) {
33a34e4e 1906 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1907 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1908
1909 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1910
a7c9655f 1911 /* Set training pattern 1 */
47ea7542 1912 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1913 DP_TRAINING_PATTERN_1 |
1914 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1915 break;
a4fc5ed6 1916
a7c9655f 1917 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1918 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1919 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1920 break;
93f62dad 1921 }
a4fc5ed6 1922
01916270 1923 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1924 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1925 clock_recovery = true;
1926 break;
1927 }
1928
1929 /* Check to see if we've tried the max voltage */
1930 for (i = 0; i < intel_dp->lane_count; i++)
1931 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1932 break;
0d710688 1933 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1934 ++loop_tries;
1935 if (loop_tries == 5) {
cdb0e95b
KP		 1936 DRM_DEBUG_KMS("too many full retries, give up\n");
1937 break;
1938 }
1939 memset(intel_dp->train_set, 0, 4);
1940 voltage_tries = 0;
1941 continue;
1942 }
a4fc5ed6 1943
3cf2efb1 1944 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1945 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1946 ++voltage_tries;
b06fbda3
DV		 1947 if (voltage_tries == 5) {
1948 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1949 break;
1950 }
1951 } else
1952 voltage_tries = 0;
1953 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1954
3cf2efb1 1955 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1956 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1957 }
1958
33a34e4e
JB		 1959 intel_dp->DP = DP;
1960}
1961
c19b0669 1962void
33a34e4e
JB		 1963intel_dp_complete_link_train(struct intel_dp *intel_dp)
1964{
33a34e4e 1965 bool channel_eq = false;
37f80975 1966 int tries, cr_tries;
33a34e4e
JB		 1967 uint32_t DP = intel_dp->DP;
1968
a4fc5ed6
KP		 1969 /* channel equalization */
1970 tries = 0;
37f80975 1971 cr_tries = 0;
a4fc5ed6
KP		 1972 channel_eq = false;
1973 for (;;) {
93f62dad 1974 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1975
37f80975
JB		 1976 if (cr_tries > 5) {
1977 DRM_ERROR("failed to train DP, aborting\n");
1978 intel_dp_link_down(intel_dp);
1979 break;
1980 }
1981
f0a3424e 1982 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 1983
a4fc5ed6 1984 /* channel eq pattern */
47ea7542 1985 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1986 DP_TRAINING_PATTERN_2 |
1987 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1988 break;
1989
a7c9655f 1990 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1991 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1992 break;
a4fc5ed6 1993
37f80975 1994 /* Make sure clock is still ok */
01916270 1995 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1996 intel_dp_start_link_train(intel_dp);
1997 cr_tries++;
1998 continue;
1999 }
2000
1ffdff13 2001 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2002 channel_eq = true;
2003 break;
2004 }
a4fc5ed6 2005
37f80975
JB		 2006 /* Try 5 times, then try clock recovery if that fails */
2007 if (tries > 5) {
2008 intel_dp_link_down(intel_dp);
2009 intel_dp_start_link_train(intel_dp);
2010 tries = 0;
2011 cr_tries++;
2012 continue;
2013 }
a4fc5ed6 2014
3cf2efb1 2015 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2016 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2017 ++tries;
869184a6 2018 }
3cf2efb1 2019
d6c0d722
PZ		 2020 if (channel_eq)
2021 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2022
47ea7542 2023 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2024}
2025
2026static void
ea5b213a 2027intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2028{
da63a9f2
PZ		 2029 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2030 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2031 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2032 struct intel_crtc *intel_crtc =
2033 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2034 uint32_t DP = intel_dp->DP;
a4fc5ed6 2035
c19b0669
PZ		 2036 /*
2037 * DDI code has a strict mode set sequence and we should try to respect
2038 * it, otherwise we might hang the machine in many different ways. So we
2039 * really should be disabling the port only on a complete crtc_disable
2040 * sequence. This function is just called under two conditions on DDI
2041 * code:
2042 * - Link train failed while doing crtc_enable, and on this case we
2043 * really should respect the mode set sequence and wait for a
2044 * crtc_disable.
2045 * - Someone turned the monitor off and intel_dp_check_link_status
2046 * called us. We don't need to disable the whole port on this case, so
2047 * when someone turns the monitor on again,
2048 * intel_ddi_prepare_link_retrain will take care of redoing the link
2049 * train.
2050 */
affa9354 2051 if (HAS_DDI(dev))
c19b0669
PZ		 2052 return;
2053
0c33d8d7 2054 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2055 return;
2056
28c97730 2057 DRM_DEBUG_KMS("\n");
32f9d658 2058
1a2eb460 2059 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2060 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2061 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2062 } else {
2063 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2064 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2065 }
fe255d00 2066 POSTING_READ(intel_dp->output_reg);
5eb08b69 2067
ab527efc
DV		 2068 /* We don't really know why we're doing this */
2069 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2070
493a7081 2071 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2072 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2073 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2074
5bddd17f
EA		 2075 /* Hardware workaround: leaving our transcoder select
2076 * set to transcoder B while it's off will prevent the
2077 * corresponding HDMI output on transcoder A.
2078 *
2079 * Combine this with another hardware workaround:
2080 * transcoder select bit can only be cleared while the
2081 * port is enabled.
2082 */
2083 DP &= ~DP_PIPEB_SELECT;
2084 I915_WRITE(intel_dp->output_reg, DP);
2085
2086 /* Changes to enable or select take place the vblank
2087 * after being written.
2088 */
ff50afe9
DV		 2089 if (WARN_ON(crtc == NULL)) {
2090 /* We should never try to disable a port without a crtc
2091 * attached. For paranoia keep the code around for a
2092 * bit. */
31acbcc4
CW		 2093 POSTING_READ(intel_dp->output_reg);
2094 msleep(50);
2095 } else
ab527efc 2096 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2097 }
2098
832afda6 2099 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2100 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2101 POSTING_READ(intel_dp->output_reg);
f01eca2e 2102 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2103}
2104
26d61aad
KP		 2105static bool
2106intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2107{
577c7a50
DL		 2108 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2109
92fd8fd1 2110 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2111 sizeof(intel_dp->dpcd)) == 0)
2112 return false; /* aux transfer failed */
92fd8fd1 2113
577c7a50
DL		 2114 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2115 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2116 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2117
edb39244
AJ		 2118 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2119 return false; /* DPCD not present */
2120
2121 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2122 DP_DWN_STRM_PORT_PRESENT))
2123 return true; /* native DP sink */
2124
2125 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2126 return true; /* no per-port downstream info */
2127
2128 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2129 intel_dp->downstream_ports,
2130 DP_MAX_DOWNSTREAM_PORTS) == 0)
2131 return false; /* downstream port status fetch failed */
2132
2133 return true;
92fd8fd1
KP		 2134}
2135
0d198328
AJ		 2136static void
2137intel_dp_probe_oui(struct intel_dp *intel_dp)
2138{
2139 u8 buf[3];
2140
2141 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2142 return;
2143
351cfc34
DV		 2144 ironlake_edp_panel_vdd_on(intel_dp);
2145
0d198328
AJ		 2146 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2147 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2148 buf[0], buf[1], buf[2]);
2149
2150 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2151 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2152 buf[0], buf[1], buf[2]);
351cfc34
DV		 2153
2154 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2155}
2156
a60f0e38
JB		 2157static bool
2158intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2159{
2160 int ret;
2161
2162 ret = intel_dp_aux_native_read_retry(intel_dp,
2163 DP_DEVICE_SERVICE_IRQ_VECTOR,
2164 sink_irq_vector, 1);
2165 if (!ret)
2166 return false;
2167
2168 return true;
2169}
2170
2171static void
2172intel_dp_handle_test_request(struct intel_dp *intel_dp)
2173{
2174 /* NAK by default */
9324cf7f 2175 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2176}
2177
a4fc5ed6
KP		 2178/*
2179 * According to DP spec
2180 * 5.1.2:
2181 * 1. Read DPCD
2182 * 2. Configure link according to Receiver Capabilities
2183 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2184 * 4. Check link status on receipt of hot-plug interrupt
2185 */
2186
00c09d70 2187void
ea5b213a 2188intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2189{
da63a9f2 2190 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2191 u8 sink_irq_vector;
93f62dad 2192 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2193
da63a9f2 2194 if (!intel_encoder->connectors_active)
d2b996ac 2195 return;
59cd09e1 2196
da63a9f2 2197 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2198 return;
2199
92fd8fd1 2200 /* Try to read receiver status if the link appears to be up */
93f62dad 2201 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2202 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2203 return;
2204 }
2205
92fd8fd1 2206 /* Now read the DPCD to see if it's actually running */
26d61aad 2207 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2208 intel_dp_link_down(intel_dp);
2209 return;
2210 }
2211
a60f0e38
JB		 2212 /* Try to read the source of the interrupt */
2213 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2214 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2215 /* Clear interrupt source */
2216 intel_dp_aux_native_write_1(intel_dp,
2217 DP_DEVICE_SERVICE_IRQ_VECTOR,
2218 sink_irq_vector);
2219
2220 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2221 intel_dp_handle_test_request(intel_dp);
2222 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2223 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2224 }
2225
1ffdff13 2226 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2227 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2228 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2229 intel_dp_start_link_train(intel_dp);
2230 intel_dp_complete_link_train(intel_dp);
2231 }
a4fc5ed6 2232}
a4fc5ed6 2233
caf9ab24 2234/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2235static enum drm_connector_status
26d61aad 2236intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2237{
caf9ab24
AJ		 2238 uint8_t *dpcd = intel_dp->dpcd;
2239 bool hpd;
2240 uint8_t type;
2241
2242 if (!intel_dp_get_dpcd(intel_dp))
2243 return connector_status_disconnected;
2244
2245 /* if there's no downstream port, we're done */
2246 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2247 return connector_status_connected;
caf9ab24
AJ		 2248
2249 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2250 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2251 if (hpd) {
23235177 2252 uint8_t reg;
caf9ab24 2253 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2254 &reg, 1))
caf9ab24 2255 return connector_status_unknown;
23235177
AJ		 2256 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2257 : connector_status_disconnected;
caf9ab24
AJ		 2258 }
2259
2260 /* If no HPD, poke DDC gently */
2261 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2262 return connector_status_connected;
caf9ab24
AJ		 2263
2264 /* Well we tried, say unknown for unreliable port types */
2265 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2266 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2267 return connector_status_unknown;
2268
2269 /* Anything else is out of spec, warn and ignore */
2270 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2271 return connector_status_disconnected;
71ba9000
AJ		 2272}
2273
5eb08b69 2274static enum drm_connector_status
a9756bb5 2275ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2276{
30add22d 2277 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2280 enum drm_connector_status status;
2281
fe16d949
CW		 2282 /* Can't disconnect eDP, but you can close the lid... */
2283 if (is_edp(intel_dp)) {
30add22d 2284 status = intel_panel_detect(dev);
fe16d949
CW		 2285 if (status == connector_status_unknown)
2286 status = connector_status_connected;
2287 return status;
2288 }
01cb9ea6 2289
1b469639
DL		 2290 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2291 return connector_status_disconnected;
2292
26d61aad 2293 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2294}
2295
a4fc5ed6 2296static enum drm_connector_status
a9756bb5 2297g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2298{
30add22d 2299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2300 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2301 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2302 uint32_t bit;
5eb08b69 2303
34f2be46
VS		 2304 switch (intel_dig_port->port) {
2305 case PORT_B:
26739f12 2306 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2307 break;
34f2be46 2308 case PORT_C:
26739f12 2309 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2310 break;
34f2be46 2311 case PORT_D:
26739f12 2312 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2313 break;
2314 default:
2315 return connector_status_unknown;
2316 }
2317
10f76a38 2318 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2319 return connector_status_disconnected;
2320
26d61aad 2321 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2322}
2323
8c241fef
KP		 2324static struct edid *
2325intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2326{
9cd300e0 2327 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2328
9cd300e0
JN		 2329 /* use cached edid if we have one */
2330 if (intel_connector->edid) {
2331 struct edid *edid;
2332 int size;
2333
2334 /* invalid edid */
2335 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2336 return NULL;
2337
9cd300e0 2338 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2339 edid = kmalloc(size, GFP_KERNEL);
2340 if (!edid)
2341 return NULL;
2342
9cd300e0 2343 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2344 return edid;
2345 }
8c241fef 2346
9cd300e0 2347 return drm_get_edid(connector, adapter);
8c241fef
KP		 2348}
2349
2350static int
2351intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2352{
9cd300e0 2353 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2354
9cd300e0
JN		 2355 /* use cached edid if we have one */
2356 if (intel_connector->edid) {
2357 /* invalid edid */
2358 if (IS_ERR(intel_connector->edid))
2359 return 0;
2360
2361 return intel_connector_update_modes(connector,
2362 intel_connector->edid);
d6f24d0f
JB		 2363 }
2364
9cd300e0 2365 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2366}
2367
a9756bb5
ZW		 2368static enum drm_connector_status
2369intel_dp_detect(struct drm_connector *connector, bool force)
2370{
2371 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2372 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2373 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2374 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2375 enum drm_connector_status status;
2376 struct edid *edid = NULL;
2377
2378 intel_dp->has_audio = false;
2379
2380 if (HAS_PCH_SPLIT(dev))
2381 status = ironlake_dp_detect(intel_dp);
2382 else
2383 status = g4x_dp_detect(intel_dp);
1b9be9d0 2384
a9756bb5
ZW		 2385 if (status != connector_status_connected)
2386 return status;
2387
0d198328
AJ		 2388 intel_dp_probe_oui(intel_dp);
2389
c3e5f67b
DV		 2390 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2391 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2392 } else {
8c241fef 2393 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2394 if (edid) {
2395 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2396 kfree(edid);
2397 }
a9756bb5
ZW		 2398 }
2399
d63885da
PZ		 2400 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2401 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2402 return connector_status_connected;
a4fc5ed6
KP		 2403}
2404
2405static int intel_dp_get_modes(struct drm_connector *connector)
2406{
df0e9248 2407 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2408 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2409 struct drm_device *dev = connector->dev;
32f9d658 2410 int ret;
a4fc5ed6
KP		 2411
2412 /* We should parse the EDID data and find out if it has an audio sink
2413 */
2414
8c241fef 2415 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2416 if (ret)
32f9d658
ZW		 2417 return ret;
2418
f8779fda 2419 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2420 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2421 struct drm_display_mode *mode;
dd06f90e
JN		 2422 mode = drm_mode_duplicate(dev,
2423 intel_connector->panel.fixed_mode);
f8779fda 2424 if (mode) {
32f9d658
ZW		 2425 drm_mode_probed_add(connector, mode);
2426 return 1;
2427 }
2428 }
2429 return 0;
a4fc5ed6
KP		 2430}
2431
1aad7ac0
CW		 2432static bool
2433intel_dp_detect_audio(struct drm_connector *connector)
2434{
2435 struct intel_dp *intel_dp = intel_attached_dp(connector);
2436 struct edid *edid;
2437 bool has_audio = false;
2438
8c241fef 2439 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2440 if (edid) {
2441 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2442 kfree(edid);
2443 }
2444
2445 return has_audio;
2446}
2447
f684960e
CW		 2448static int
2449intel_dp_set_property(struct drm_connector *connector,
2450 struct drm_property *property,
2451 uint64_t val)
2452{
e953fd7b 2453 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2454 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2455 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2456 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2457 int ret;
2458
662595df 2459 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2460 if (ret)
2461 return ret;
2462
3f43c48d 2463 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2464 int i = val;
2465 bool has_audio;
2466
2467 if (i == intel_dp->force_audio)
f684960e
CW		 2468 return 0;
2469
1aad7ac0 2470 intel_dp->force_audio = i;
f684960e 2471
c3e5f67b 2472 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2473 has_audio = intel_dp_detect_audio(connector);
2474 else
c3e5f67b 2475 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2476
2477 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2478 return 0;
2479
1aad7ac0 2480 intel_dp->has_audio = has_audio;
f684960e
CW		 2481 goto done;
2482 }
2483
e953fd7b 2484 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2485 switch (val) {
2486 case INTEL_BROADCAST_RGB_AUTO:
2487 intel_dp->color_range_auto = true;
2488 break;
2489 case INTEL_BROADCAST_RGB_FULL:
2490 intel_dp->color_range_auto = false;
2491 intel_dp->color_range = 0;
2492 break;
2493 case INTEL_BROADCAST_RGB_LIMITED:
2494 intel_dp->color_range_auto = false;
2495 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2496 break;
2497 default:
2498 return -EINVAL;
2499 }
e953fd7b
CW		 2500 goto done;
2501 }
2502
53b41837
YN		 2503 if (is_edp(intel_dp) &&
2504 property == connector->dev->mode_config.scaling_mode_property) {
2505 if (val == DRM_MODE_SCALE_NONE) {
2506 DRM_DEBUG_KMS("no scaling not supported\n");
2507 return -EINVAL;
2508 }
2509
2510 if (intel_connector->panel.fitting_mode == val) {
2511 /* the eDP scaling property is not changed */
2512 return 0;
2513 }
2514 intel_connector->panel.fitting_mode = val;
2515
2516 goto done;
2517 }
2518
f684960e
CW		 2519 return -EINVAL;
2520
2521done:
c0c36b94
CW		 2522 if (intel_encoder->base.crtc)
2523 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2524
2525 return 0;
2526}
2527
a4fc5ed6 2528static void
0206e353 2529intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2530{
aaa6fd2a 2531 struct drm_device *dev = connector->dev;
be3cd5e3 2532 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2533 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2534
9cd300e0
JN		 2535 if (!IS_ERR_OR_NULL(intel_connector->edid))
2536 kfree(intel_connector->edid);
2537
1d508706 2538 if (is_edp(intel_dp)) {
aaa6fd2a 2539 intel_panel_destroy_backlight(dev);
1d508706
JN		 2540 intel_panel_fini(&intel_connector->panel);
2541 }
aaa6fd2a 2542
a4fc5ed6
KP		 2543 drm_sysfs_connector_remove(connector);
2544 drm_connector_cleanup(connector);
55f78c43 2545 kfree(connector);
a4fc5ed6
KP		 2546}
2547
00c09d70 2548void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2549{
da63a9f2
PZ		 2550 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2551 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2552
2553 i2c_del_adapter(&intel_dp->adapter);
2554 drm_encoder_cleanup(encoder);
bd943159
KP		 2555 if (is_edp(intel_dp)) {
2556 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2557 ironlake_panel_vdd_off_sync(intel_dp);
2558 }
da63a9f2 2559 kfree(intel_dig_port);
24d05927
DV		 2560}
2561
a4fc5ed6 2562static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2563 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2564 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2565};
2566
2567static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2568 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2569 .detect = intel_dp_detect,
2570 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2571 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2572 .destroy = intel_dp_destroy,
2573};
2574
2575static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2576 .get_modes = intel_dp_get_modes,
2577 .mode_valid = intel_dp_mode_valid,
df0e9248 2578 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2579};
2580
a4fc5ed6 2581static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2582 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2583};
2584
995b6762 2585static void
21d40d37 2586intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2587{
fa90ecef 2588 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2589
885a5014 2590 intel_dp_check_link_status(intel_dp);
c8110e52 2591}
6207937d 2592
e3421a18
ZW		 2593/* Return which DP Port should be selected for Transcoder DP control */
2594int
0206e353 2595intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2596{
2597 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2598 struct intel_encoder *intel_encoder;
2599 struct intel_dp *intel_dp;
e3421a18 2600
fa90ecef
PZ		 2601 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2602 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2603
fa90ecef
PZ		 2604 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2605 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2606 return intel_dp->output_reg;
e3421a18 2607 }
ea5b213a 2608
e3421a18
ZW		 2609 return -1;
2610}
2611
36e83a18 2612/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2613bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2614{
2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 struct child_device_config *p_child;
2617 int i;
2618
2619 if (!dev_priv->child_dev_num)
2620 return false;
2621
2622 for (i = 0; i < dev_priv->child_dev_num; i++) {
2623 p_child = dev_priv->child_dev + i;
2624
2625 if (p_child->dvo_port == PORT_IDPD &&
2626 p_child->device_type == DEVICE_TYPE_eDP)
2627 return true;
2628 }
2629 return false;
2630}
2631
f684960e
CW		 2632static void
2633intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2634{
53b41837
YN		 2635 struct intel_connector *intel_connector = to_intel_connector(connector);
2636
3f43c48d 2637 intel_attach_force_audio_property(connector);
e953fd7b 2638 intel_attach_broadcast_rgb_property(connector);
55bc60db 2639 intel_dp->color_range_auto = true;
53b41837
YN		 2640
2641 if (is_edp(intel_dp)) {
2642 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2643 drm_object_attach_property(
2644 &connector->base,
53b41837 2645 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2646 DRM_MODE_SCALE_ASPECT);
2647 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2648 }
f684960e
CW		 2649}
2650
67a54566
DV		 2651static void
2652intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2653 struct intel_dp *intel_dp,
2654 struct edp_power_seq *out)
67a54566
DV		 2655{
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 struct edp_power_seq cur, vbt, spec, final;
2658 u32 pp_on, pp_off, pp_div, pp;
2659
2660 /* Workaround: Need to write PP_CONTROL with the unlock key as
2661 * the very first thing. */
2662 pp = ironlake_get_pp_control(dev_priv);
2663 I915_WRITE(PCH_PP_CONTROL, pp);
2664
2665 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2666 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2667 pp_div = I915_READ(PCH_PP_DIVISOR);
2668
2669 /* Pull timing values out of registers */
2670 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2671 PANEL_POWER_UP_DELAY_SHIFT;
2672
2673 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2674 PANEL_LIGHT_ON_DELAY_SHIFT;
2675
2676 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2677 PANEL_LIGHT_OFF_DELAY_SHIFT;
2678
2679 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2680 PANEL_POWER_DOWN_DELAY_SHIFT;
2681
2682 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2683 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2684
2685 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2686 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2687
2688 vbt = dev_priv->edp.pps;
2689
2690 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2691 * our hw here, which are all in 100usec. */
2692 spec.t1_t3 = 210 * 10;
2693 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2694 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2695 spec.t10 = 500 * 10;
2696 /* This one is special and actually in units of 100ms, but zero
2697 * based in the hw (so we need to add 100 ms). But the sw vbt
2698 * table multiplies it with 1000 to make it in units of 100usec,
2699 * too. */
2700 spec.t11_t12 = (510 + 100) * 10;
2701
2702 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2703 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2704
2705 /* Use the max of the register settings and vbt. If both are
2706 * unset, fall back to the spec limits. */
2707#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2708 spec.field : \
2709 max(cur.field, vbt.field))
2710 assign_final(t1_t3);
2711 assign_final(t8);
2712 assign_final(t9);
2713 assign_final(t10);
2714 assign_final(t11_t12);
2715#undef assign_final
2716
2717#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2718 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2719 intel_dp->backlight_on_delay = get_delay(t8);
2720 intel_dp->backlight_off_delay = get_delay(t9);
2721 intel_dp->panel_power_down_delay = get_delay(t10);
2722 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2723#undef get_delay
2724
f30d26e4
JN		 2725 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2726 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2727 intel_dp->panel_power_cycle_delay);
2728
2729 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2730 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2731
2732 if (out)
2733 *out = final;
2734}
2735
2736static void
2737intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2738 struct intel_dp *intel_dp,
2739 struct edp_power_seq *seq)
2740{
2741 struct drm_i915_private *dev_priv = dev->dev_private;
2742 u32 pp_on, pp_off, pp_div;
2743
67a54566 2744 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2745 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2746 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2747 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2748 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2749 /* Compute the divisor for the pp clock, simply match the Bspec
2750 * formula. */
2751 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2752 << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2753 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2754 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2755
2756 /* Haswell doesn't have any port selection bits for the panel
2757 * power sequencer any more. */
2758 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2759 if (is_cpu_edp(intel_dp))
2760 pp_on |= PANEL_POWER_PORT_DP_A;
2761 else
2762 pp_on |= PANEL_POWER_PORT_DP_D;
2763 }
2764
2765 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2766 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2767 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2768
67a54566
DV		 2769 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2770 I915_READ(PCH_PP_ON_DELAYS),
2771 I915_READ(PCH_PP_OFF_DELAYS),
2772 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2773}
2774
a4fc5ed6 2775void
f0fec3f2
PZ		 2776intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2777 struct intel_connector *intel_connector)
a4fc5ed6 2778{
f0fec3f2
PZ		 2779 struct drm_connector *connector = &intel_connector->base;
2780 struct intel_dp *intel_dp = &intel_dig_port->dp;
2781 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2782 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2783 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2784 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2785 struct edp_power_seq power_seq = { 0 };
174edf1f 2786 enum port port = intel_dig_port->port;
5eb08b69 2787 const char *name = NULL;
b329530c 2788 int type;
a4fc5ed6 2789
0767935e
DV		 2790 /* Preserve the current hw state. */
2791 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2792 intel_dp->attached_connector = intel_connector;
3d3dc149 2793
f0fec3f2 2794 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2795 if (intel_dpd_is_edp(dev))
ea5b213a 2796 intel_dp->is_pch_edp = true;
b329530c 2797
19c03924
GB		 2798 /*
2799 * FIXME : We need to initialize built-in panels before external panels.
2800 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2801 */
f0fec3f2 2802 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2803 type = DRM_MODE_CONNECTOR_eDP;
2804 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2805 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2806 type = DRM_MODE_CONNECTOR_eDP;
2807 intel_encoder->type = INTEL_OUTPUT_EDP;
2808 } else {
00c09d70
PZ		 2809 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2810 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2811 * rewrite it.
2812 */
b329530c 2813 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2814 }
2815
b329530c 2816 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2817 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2818
eb1f8e4f 2819 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2820 connector->interlace_allowed = true;
2821 connector->doublescan_allowed = 0;
2822
f0fec3f2
PZ		 2823 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2824 ironlake_panel_vdd_work);
a4fc5ed6 2825
df0e9248 2826 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2827 drm_sysfs_connector_add(connector);
2828
affa9354 2829 if (HAS_DDI(dev))
bcbc889b
PZ		 2830 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2831 else
2832 intel_connector->get_hw_state = intel_connector_get_hw_state;
2833
e8cb4558 2834
a4fc5ed6 2835 /* Set up the DDC bus. */
ab9d7c30
PZ		 2836 switch (port) {
2837 case PORT_A:
2838 name = "DPDDC-A";
2839 break;
2840 case PORT_B:
26739f12 2841 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
ab9d7c30
PZ		 2842 name = "DPDDC-B";
2843 break;
2844 case PORT_C:
26739f12 2845 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
ab9d7c30
PZ		 2846 name = "DPDDC-C";
2847 break;
2848 case PORT_D:
26739f12 2849 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
ab9d7c30
PZ		 2850 name = "DPDDC-D";
2851 break;
2852 default:
2853 WARN(1, "Invalid port %c\n", port_name(port));
2854 break;
5eb08b69
ZW		 2855 }
2856
67a54566 2857 if (is_edp(intel_dp))
f30d26e4 2858 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 2859
2860 intel_dp_i2c_init(intel_dp, intel_connector, name);
2861
67a54566 2862 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2863 if (is_edp(intel_dp)) {
2864 bool ret;
f8779fda 2865 struct drm_display_mode *scan;
c1f05264 2866 struct edid *edid;
5d613501
JB		 2867
2868 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2869 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2870 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2871
59f3e272 2872 if (ret) {
7183dc29
JB		 2873 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2874 dev_priv->no_aux_handshake =
2875 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2876 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2877 } else {
3d3dc149 2878 /* if this fails, presume the device is a ghost */
48898b03 2879 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2880 intel_dp_encoder_destroy(&intel_encoder->base);
2881 intel_dp_destroy(connector);
3d3dc149 2882 return;
89667383 2883 }
89667383 2884
f30d26e4
JN		 2885 /* We now know it's not a ghost, init power sequence regs. */
2886 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2887 &power_seq);
2888
d6f24d0f
JB		 2889 ironlake_edp_panel_vdd_on(intel_dp);
2890 edid = drm_get_edid(connector, &intel_dp->adapter);
2891 if (edid) {
9cd300e0
JN		 2892 if (drm_add_edid_modes(connector, edid)) {
2893 drm_mode_connector_update_edid_property(connector, edid);
2894 drm_edid_to_eld(connector, edid);
2895 } else {
2896 kfree(edid);
2897 edid = ERR_PTR(-EINVAL);
2898 }
2899 } else {
2900 edid = ERR_PTR(-ENOENT);
d6f24d0f 2901 }
9cd300e0 2902 intel_connector->edid = edid;
f8779fda
JN		 2903
2904 /* prefer fixed mode from EDID if available */
2905 list_for_each_entry(scan, &connector->probed_modes, head) {
2906 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2907 fixed_mode = drm_mode_duplicate(dev, scan);
2908 break;
2909 }
d6f24d0f 2910 }
f8779fda
JN		 2911
2912 /* fallback to VBT if available for eDP */
2913 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2914 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2915 if (fixed_mode)
2916 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2917 }
f8779fda 2918
d6f24d0f
JB		 2919 ironlake_edp_panel_vdd_off(intel_dp, false);
2920 }
552fb0b7 2921
4d926461 2922 if (is_edp(intel_dp)) {
dd06f90e 2923 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2924 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2925 }
2926
f684960e
CW		 2927 intel_dp_add_properties(intel_dp, connector);
2928
a4fc5ed6
KP		 2929 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2930 * 0xd. Failure to do so will result in spurious interrupts being
2931 * generated on the port when a cable is not attached.
2932 */
2933 if (IS_G4X(dev) && !IS_GM45(dev)) {
2934 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2935 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2936 }
2937}
f0fec3f2
PZ		 2938
2939void
2940intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2941{
2942 struct intel_digital_port *intel_dig_port;
2943 struct intel_encoder *intel_encoder;
2944 struct drm_encoder *encoder;
2945 struct intel_connector *intel_connector;
2946
2947 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2948 if (!intel_dig_port)
2949 return;
2950
2951 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2952 if (!intel_connector) {
2953 kfree(intel_dig_port);
2954 return;
2955 }
2956
2957 intel_encoder = &intel_dig_port->base;
2958 encoder = &intel_encoder->base;
2959
2960 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2961 DRM_MODE_ENCODER_TMDS);
00c09d70 2962 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2963
00c09d70
PZ		 2964 intel_encoder->enable = intel_enable_dp;
2965 intel_encoder->pre_enable = intel_pre_enable_dp;
2966 intel_encoder->disable = intel_disable_dp;
2967 intel_encoder->post_disable = intel_post_disable_dp;
2968 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2969
174edf1f 2970 intel_dig_port->port = port;
f0fec3f2
PZ		 2971 intel_dig_port->dp.output_reg = output_reg;
2972
00c09d70 2973 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2974 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2975 intel_encoder->cloneable = false;
2976 intel_encoder->hot_plug = intel_dp_hot_plug;
2977
2978 intel_dp_init_connector(intel_dig_port, intel_connector);
2979}
Linux kernel - Deliverables
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