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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
a2006cf5 | 39 | #define DP_RECEIVER_CAP_SIZE 0xf |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
d2b996ac | 53 | int dpms_mode; |
a4fc5ed6 KP |
54 | uint8_t link_bw; |
55 | uint8_t lane_count; | |
a2006cf5 | 56 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
a4fc5ed6 KP |
57 | struct i2c_adapter adapter; |
58 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 59 | bool is_pch_edp; |
33a34e4e | 60 | uint8_t train_set[4]; |
f01eca2e KP |
61 | int panel_power_up_delay; |
62 | int panel_power_down_delay; | |
63 | int panel_power_cycle_delay; | |
64 | int backlight_on_delay; | |
65 | int backlight_off_delay; | |
d15456de | 66 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
bd943159 KP |
67 | struct delayed_work panel_vdd_work; |
68 | bool want_panel_vdd; | |
69 | unsigned long panel_off_jiffies; | |
a4fc5ed6 KP |
70 | }; |
71 | ||
cfcb0fc9 JB |
72 | /** |
73 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
74 | * @intel_dp: DP struct | |
75 | * | |
76 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
77 | * will return true, and false otherwise. | |
78 | */ | |
79 | static bool is_edp(struct intel_dp *intel_dp) | |
80 | { | |
81 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
82 | } | |
83 | ||
84 | /** | |
85 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
86 | * @intel_dp: DP struct | |
87 | * | |
88 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
89 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
90 | * may need FDI resources for a given DP output or not. | |
91 | */ | |
92 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
93 | { | |
94 | return intel_dp->is_pch_edp; | |
95 | } | |
96 | ||
1c95822a AJ |
97 | /** |
98 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? | |
99 | * @intel_dp: DP struct | |
100 | * | |
101 | * Returns true if the given DP struct corresponds to a CPU eDP port. | |
102 | */ | |
103 | static bool is_cpu_edp(struct intel_dp *intel_dp) | |
104 | { | |
105 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); | |
106 | } | |
107 | ||
ea5b213a CW |
108 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
109 | { | |
4ef69c7a | 110 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 111 | } |
a4fc5ed6 | 112 | |
df0e9248 CW |
113 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
114 | { | |
115 | return container_of(intel_attached_encoder(connector), | |
116 | struct intel_dp, base); | |
117 | } | |
118 | ||
814948ad JB |
119 | /** |
120 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
121 | * @encoder: DRM encoder | |
122 | * | |
123 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
124 | * by intel_display.c. | |
125 | */ | |
126 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
127 | { | |
128 | struct intel_dp *intel_dp; | |
129 | ||
130 | if (!encoder) | |
131 | return false; | |
132 | ||
133 | intel_dp = enc_to_intel_dp(encoder); | |
134 | ||
135 | return is_pch_edp(intel_dp); | |
136 | } | |
137 | ||
33a34e4e JB |
138 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
139 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 140 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 141 | |
32f9d658 | 142 | void |
0206e353 | 143 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
ea5b213a | 144 | int *lane_num, int *link_bw) |
32f9d658 | 145 | { |
ea5b213a | 146 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 147 | |
ea5b213a CW |
148 | *lane_num = intel_dp->lane_count; |
149 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 150 | *link_bw = 162000; |
ea5b213a | 151 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
152 | *link_bw = 270000; |
153 | } | |
154 | ||
a4fc5ed6 | 155 | static int |
ea5b213a | 156 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 157 | { |
a4fc5ed6 KP |
158 | int max_lane_count = 4; |
159 | ||
7183dc29 JB |
160 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
161 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
162 | switch (max_lane_count) { |
163 | case 1: case 2: case 4: | |
164 | break; | |
165 | default: | |
166 | max_lane_count = 4; | |
167 | } | |
168 | } | |
169 | return max_lane_count; | |
170 | } | |
171 | ||
172 | static int | |
ea5b213a | 173 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 174 | { |
7183dc29 | 175 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
176 | |
177 | switch (max_link_bw) { | |
178 | case DP_LINK_BW_1_62: | |
179 | case DP_LINK_BW_2_7: | |
180 | break; | |
181 | default: | |
182 | max_link_bw = DP_LINK_BW_1_62; | |
183 | break; | |
184 | } | |
185 | return max_link_bw; | |
186 | } | |
187 | ||
188 | static int | |
189 | intel_dp_link_clock(uint8_t link_bw) | |
190 | { | |
191 | if (link_bw == DP_LINK_BW_2_7) | |
192 | return 270000; | |
193 | else | |
194 | return 162000; | |
195 | } | |
196 | ||
cd9dde44 AJ |
197 | /* |
198 | * The units on the numbers in the next two are... bizarre. Examples will | |
199 | * make it clearer; this one parallels an example in the eDP spec. | |
200 | * | |
201 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
202 | * | |
203 | * 270000 * 1 * 8 / 10 == 216000 | |
204 | * | |
205 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
206 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
207 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
208 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
209 | * | |
210 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
211 | * get the result in decakilobits instead of kilobits. | |
212 | */ | |
213 | ||
a4fc5ed6 | 214 | static int |
cd9dde44 | 215 | intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 216 | { |
89c61432 JB |
217 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
218 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
219 | int bpp = 24; | |
885a5fb5 | 220 | |
89c61432 JB |
221 | if (intel_crtc) |
222 | bpp = intel_crtc->bpp; | |
223 | ||
cd9dde44 | 224 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
225 | } |
226 | ||
fe27d53e DA |
227 | static int |
228 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
229 | { | |
230 | return (max_link_clock * max_lanes * 8) / 10; | |
231 | } | |
232 | ||
a4fc5ed6 KP |
233 | static int |
234 | intel_dp_mode_valid(struct drm_connector *connector, | |
235 | struct drm_display_mode *mode) | |
236 | { | |
df0e9248 | 237 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
ea5b213a CW |
238 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
239 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 240 | |
d15456de KP |
241 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
242 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) | |
7de56f43 ZY |
243 | return MODE_PANEL; |
244 | ||
d15456de | 245 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
7de56f43 ZY |
246 | return MODE_PANEL; |
247 | } | |
248 | ||
dc22ee6f AJ |
249 | if (intel_dp_link_required(intel_dp, mode->clock) |
250 | > intel_dp_max_data_rate(max_link_clock, max_lanes)) | |
a4fc5ed6 KP |
251 | return MODE_CLOCK_HIGH; |
252 | ||
253 | if (mode->clock < 10000) | |
254 | return MODE_CLOCK_LOW; | |
255 | ||
256 | return MODE_OK; | |
257 | } | |
258 | ||
259 | static uint32_t | |
260 | pack_aux(uint8_t *src, int src_bytes) | |
261 | { | |
262 | int i; | |
263 | uint32_t v = 0; | |
264 | ||
265 | if (src_bytes > 4) | |
266 | src_bytes = 4; | |
267 | for (i = 0; i < src_bytes; i++) | |
268 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
269 | return v; | |
270 | } | |
271 | ||
272 | static void | |
273 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
274 | { | |
275 | int i; | |
276 | if (dst_bytes > 4) | |
277 | dst_bytes = 4; | |
278 | for (i = 0; i < dst_bytes; i++) | |
279 | dst[i] = src >> ((3-i) * 8); | |
280 | } | |
281 | ||
fb0f8fbf KP |
282 | /* hrawclock is 1/4 the FSB frequency */ |
283 | static int | |
284 | intel_hrawclk(struct drm_device *dev) | |
285 | { | |
286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
287 | uint32_t clkcfg; | |
288 | ||
289 | clkcfg = I915_READ(CLKCFG); | |
290 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
291 | case CLKCFG_FSB_400: | |
292 | return 100; | |
293 | case CLKCFG_FSB_533: | |
294 | return 133; | |
295 | case CLKCFG_FSB_667: | |
296 | return 166; | |
297 | case CLKCFG_FSB_800: | |
298 | return 200; | |
299 | case CLKCFG_FSB_1067: | |
300 | return 266; | |
301 | case CLKCFG_FSB_1333: | |
302 | return 333; | |
303 | /* these two are just a guess; one of them might be right */ | |
304 | case CLKCFG_FSB_1600: | |
305 | case CLKCFG_FSB_1600_ALT: | |
306 | return 400; | |
307 | default: | |
308 | return 133; | |
309 | } | |
310 | } | |
311 | ||
ebf33b18 KP |
312 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
313 | { | |
314 | struct drm_device *dev = intel_dp->base.base.dev; | |
315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
316 | ||
317 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; | |
318 | } | |
319 | ||
320 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
321 | { | |
322 | struct drm_device *dev = intel_dp->base.base.dev; | |
323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
324 | ||
325 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; | |
326 | } | |
327 | ||
9b984dae KP |
328 | static void |
329 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
330 | { | |
331 | struct drm_device *dev = intel_dp->base.base.dev; | |
332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 333 | |
9b984dae KP |
334 | if (!is_edp(intel_dp)) |
335 | return; | |
ebf33b18 | 336 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
337 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
338 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
ebf33b18 | 339 | I915_READ(PCH_PP_STATUS), |
9b984dae KP |
340 | I915_READ(PCH_PP_CONTROL)); |
341 | } | |
342 | } | |
343 | ||
a4fc5ed6 | 344 | static int |
ea5b213a | 345 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
346 | uint8_t *send, int send_bytes, |
347 | uint8_t *recv, int recv_size) | |
348 | { | |
ea5b213a | 349 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 350 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
351 | struct drm_i915_private *dev_priv = dev->dev_private; |
352 | uint32_t ch_ctl = output_reg + 0x10; | |
353 | uint32_t ch_data = ch_ctl + 4; | |
354 | int i; | |
355 | int recv_bytes; | |
a4fc5ed6 | 356 | uint32_t status; |
fb0f8fbf | 357 | uint32_t aux_clock_divider; |
e3421a18 | 358 | int try, precharge; |
a4fc5ed6 | 359 | |
9b984dae | 360 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 361 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
362 | * and would like to run at 2MHz. So, take the |
363 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
364 | * |
365 | * Note that PCH attached eDP panels should use a 125MHz input | |
366 | * clock divider. | |
a4fc5ed6 | 367 | */ |
1c95822a | 368 | if (is_cpu_edp(intel_dp)) { |
e3421a18 ZW |
369 | if (IS_GEN6(dev)) |
370 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
371 | else | |
372 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
373 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 374 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
375 | else |
376 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
377 | ||
e3421a18 ZW |
378 | if (IS_GEN6(dev)) |
379 | precharge = 3; | |
380 | else | |
381 | precharge = 5; | |
382 | ||
11bee43e JB |
383 | /* Try to wait for any previous AUX channel activity */ |
384 | for (try = 0; try < 3; try++) { | |
385 | status = I915_READ(ch_ctl); | |
386 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
387 | break; | |
388 | msleep(1); | |
389 | } | |
390 | ||
391 | if (try == 3) { | |
392 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
393 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
394 | return -EBUSY; |
395 | } | |
396 | ||
fb0f8fbf KP |
397 | /* Must try at least 3 times according to DP spec */ |
398 | for (try = 0; try < 5; try++) { | |
399 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
400 | for (i = 0; i < send_bytes; i += 4) |
401 | I915_WRITE(ch_data + i, | |
402 | pack_aux(send + i, send_bytes - i)); | |
0206e353 | 403 | |
fb0f8fbf | 404 | /* Send the command and wait for it to complete */ |
4f7f7b7e CW |
405 | I915_WRITE(ch_ctl, |
406 | DP_AUX_CH_CTL_SEND_BUSY | | |
407 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
408 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
409 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
410 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
411 | DP_AUX_CH_CTL_DONE | | |
412 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
413 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 414 | for (;;) { |
fb0f8fbf KP |
415 | status = I915_READ(ch_ctl); |
416 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
417 | break; | |
4f7f7b7e | 418 | udelay(100); |
fb0f8fbf | 419 | } |
0206e353 | 420 | |
fb0f8fbf | 421 | /* Clear done status and any errors */ |
4f7f7b7e CW |
422 | I915_WRITE(ch_ctl, |
423 | status | | |
424 | DP_AUX_CH_CTL_DONE | | |
425 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
426 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
427 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
428 | break; |
429 | } | |
430 | ||
a4fc5ed6 | 431 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 432 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 433 | return -EBUSY; |
a4fc5ed6 KP |
434 | } |
435 | ||
436 | /* Check for timeout or receive error. | |
437 | * Timeouts occur when the sink is not connected | |
438 | */ | |
a5b3da54 | 439 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 440 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
441 | return -EIO; |
442 | } | |
1ae8c0a5 KP |
443 | |
444 | /* Timeouts occur when the device isn't connected, so they're | |
445 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 446 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 447 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 448 | return -ETIMEDOUT; |
a4fc5ed6 KP |
449 | } |
450 | ||
451 | /* Unload any bytes sent back from the other side */ | |
452 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
453 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
454 | if (recv_bytes > recv_size) |
455 | recv_bytes = recv_size; | |
0206e353 | 456 | |
4f7f7b7e CW |
457 | for (i = 0; i < recv_bytes; i += 4) |
458 | unpack_aux(I915_READ(ch_data + i), | |
459 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
460 | |
461 | return recv_bytes; | |
462 | } | |
463 | ||
464 | /* Write data to the aux channel in native mode */ | |
465 | static int | |
ea5b213a | 466 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
467 | uint16_t address, uint8_t *send, int send_bytes) |
468 | { | |
469 | int ret; | |
470 | uint8_t msg[20]; | |
471 | int msg_bytes; | |
472 | uint8_t ack; | |
473 | ||
9b984dae | 474 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
475 | if (send_bytes > 16) |
476 | return -1; | |
477 | msg[0] = AUX_NATIVE_WRITE << 4; | |
478 | msg[1] = address >> 8; | |
eebc863e | 479 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
480 | msg[3] = send_bytes - 1; |
481 | memcpy(&msg[4], send, send_bytes); | |
482 | msg_bytes = send_bytes + 4; | |
483 | for (;;) { | |
ea5b213a | 484 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
485 | if (ret < 0) |
486 | return ret; | |
487 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
488 | break; | |
489 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
490 | udelay(100); | |
491 | else | |
a5b3da54 | 492 | return -EIO; |
a4fc5ed6 KP |
493 | } |
494 | return send_bytes; | |
495 | } | |
496 | ||
497 | /* Write a single byte to the aux channel in native mode */ | |
498 | static int | |
ea5b213a | 499 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
500 | uint16_t address, uint8_t byte) |
501 | { | |
ea5b213a | 502 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
503 | } |
504 | ||
505 | /* read bytes from a native aux channel */ | |
506 | static int | |
ea5b213a | 507 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
508 | uint16_t address, uint8_t *recv, int recv_bytes) |
509 | { | |
510 | uint8_t msg[4]; | |
511 | int msg_bytes; | |
512 | uint8_t reply[20]; | |
513 | int reply_bytes; | |
514 | uint8_t ack; | |
515 | int ret; | |
516 | ||
9b984dae | 517 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
518 | msg[0] = AUX_NATIVE_READ << 4; |
519 | msg[1] = address >> 8; | |
520 | msg[2] = address & 0xff; | |
521 | msg[3] = recv_bytes - 1; | |
522 | ||
523 | msg_bytes = 4; | |
524 | reply_bytes = recv_bytes + 1; | |
525 | ||
526 | for (;;) { | |
ea5b213a | 527 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 528 | reply, reply_bytes); |
a5b3da54 KP |
529 | if (ret == 0) |
530 | return -EPROTO; | |
531 | if (ret < 0) | |
a4fc5ed6 KP |
532 | return ret; |
533 | ack = reply[0]; | |
534 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
535 | memcpy(recv, reply + 1, ret - 1); | |
536 | return ret - 1; | |
537 | } | |
538 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
539 | udelay(100); | |
540 | else | |
a5b3da54 | 541 | return -EIO; |
a4fc5ed6 KP |
542 | } |
543 | } | |
544 | ||
545 | static int | |
ab2c0672 DA |
546 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
547 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 548 | { |
ab2c0672 | 549 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
550 | struct intel_dp *intel_dp = container_of(adapter, |
551 | struct intel_dp, | |
552 | adapter); | |
ab2c0672 DA |
553 | uint16_t address = algo_data->address; |
554 | uint8_t msg[5]; | |
555 | uint8_t reply[2]; | |
8316f337 | 556 | unsigned retry; |
ab2c0672 DA |
557 | int msg_bytes; |
558 | int reply_bytes; | |
559 | int ret; | |
560 | ||
9b984dae | 561 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
562 | /* Set up the command byte */ |
563 | if (mode & MODE_I2C_READ) | |
564 | msg[0] = AUX_I2C_READ << 4; | |
565 | else | |
566 | msg[0] = AUX_I2C_WRITE << 4; | |
567 | ||
568 | if (!(mode & MODE_I2C_STOP)) | |
569 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 570 | |
ab2c0672 DA |
571 | msg[1] = address >> 8; |
572 | msg[2] = address; | |
573 | ||
574 | switch (mode) { | |
575 | case MODE_I2C_WRITE: | |
576 | msg[3] = 0; | |
577 | msg[4] = write_byte; | |
578 | msg_bytes = 5; | |
579 | reply_bytes = 1; | |
580 | break; | |
581 | case MODE_I2C_READ: | |
582 | msg[3] = 0; | |
583 | msg_bytes = 4; | |
584 | reply_bytes = 2; | |
585 | break; | |
586 | default: | |
587 | msg_bytes = 3; | |
588 | reply_bytes = 1; | |
589 | break; | |
590 | } | |
591 | ||
8316f337 DF |
592 | for (retry = 0; retry < 5; retry++) { |
593 | ret = intel_dp_aux_ch(intel_dp, | |
594 | msg, msg_bytes, | |
595 | reply, reply_bytes); | |
ab2c0672 | 596 | if (ret < 0) { |
3ff99164 | 597 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
598 | return ret; |
599 | } | |
8316f337 DF |
600 | |
601 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
602 | case AUX_NATIVE_REPLY_ACK: | |
603 | /* I2C-over-AUX Reply field is only valid | |
604 | * when paired with AUX ACK. | |
605 | */ | |
606 | break; | |
607 | case AUX_NATIVE_REPLY_NACK: | |
608 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
609 | return -EREMOTEIO; | |
610 | case AUX_NATIVE_REPLY_DEFER: | |
611 | udelay(100); | |
612 | continue; | |
613 | default: | |
614 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
615 | reply[0]); | |
616 | return -EREMOTEIO; | |
617 | } | |
618 | ||
ab2c0672 DA |
619 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
620 | case AUX_I2C_REPLY_ACK: | |
621 | if (mode == MODE_I2C_READ) { | |
622 | *read_byte = reply[1]; | |
623 | } | |
624 | return reply_bytes - 1; | |
625 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 626 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
627 | return -EREMOTEIO; |
628 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 629 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
630 | udelay(100); |
631 | break; | |
632 | default: | |
8316f337 | 633 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
634 | return -EREMOTEIO; |
635 | } | |
636 | } | |
8316f337 DF |
637 | |
638 | DRM_ERROR("too many retries, giving up\n"); | |
639 | return -EREMOTEIO; | |
a4fc5ed6 KP |
640 | } |
641 | ||
0b5c541b | 642 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
bd943159 | 643 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
0b5c541b | 644 | |
a4fc5ed6 | 645 | static int |
ea5b213a | 646 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 647 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 648 | { |
0b5c541b KP |
649 | int ret; |
650 | ||
d54e9d28 | 651 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
652 | intel_dp->algo.running = false; |
653 | intel_dp->algo.address = 0; | |
654 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
655 | ||
0206e353 | 656 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
657 | intel_dp->adapter.owner = THIS_MODULE; |
658 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 659 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
660 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
661 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
662 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
663 | ||
0b5c541b KP |
664 | ironlake_edp_panel_vdd_on(intel_dp); |
665 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 666 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 667 | return ret; |
a4fc5ed6 KP |
668 | } |
669 | ||
670 | static bool | |
671 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
672 | struct drm_display_mode *adjusted_mode) | |
673 | { | |
0d3a1bee | 674 | struct drm_device *dev = encoder->dev; |
ea5b213a | 675 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 676 | int lane_count, clock; |
ea5b213a CW |
677 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
678 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
679 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
680 | ||
d15456de KP |
681 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
682 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); | |
1d8e1c75 CW |
683 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
684 | mode, adjusted_mode); | |
0d3a1bee ZY |
685 | /* |
686 | * the mode->clock is used to calculate the Data&Link M/N | |
687 | * of the pipe. For the eDP the fixed clock should be used. | |
688 | */ | |
d15456de | 689 | mode->clock = intel_dp->panel_fixed_mode->clock; |
0d3a1bee ZY |
690 | } |
691 | ||
a4fc5ed6 KP |
692 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
693 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 694 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 695 | |
cd9dde44 | 696 | if (intel_dp_link_required(intel_dp, mode->clock) |
885a5fb5 | 697 | <= link_avail) { |
ea5b213a CW |
698 | intel_dp->link_bw = bws[clock]; |
699 | intel_dp->lane_count = lane_count; | |
700 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
701 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
702 | "count %d clock %d\n", | |
ea5b213a | 703 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
704 | adjusted_mode->clock); |
705 | return true; | |
706 | } | |
707 | } | |
708 | } | |
fe27d53e | 709 | |
a4fc5ed6 KP |
710 | return false; |
711 | } | |
712 | ||
713 | struct intel_dp_m_n { | |
714 | uint32_t tu; | |
715 | uint32_t gmch_m; | |
716 | uint32_t gmch_n; | |
717 | uint32_t link_m; | |
718 | uint32_t link_n; | |
719 | }; | |
720 | ||
721 | static void | |
722 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
723 | { | |
724 | while (*num > 0xffffff || *den > 0xffffff) { | |
725 | *num >>= 1; | |
726 | *den >>= 1; | |
727 | } | |
728 | } | |
729 | ||
730 | static void | |
36e83a18 | 731 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
732 | int nlanes, |
733 | int pixel_clock, | |
734 | int link_clock, | |
735 | struct intel_dp_m_n *m_n) | |
736 | { | |
737 | m_n->tu = 64; | |
36e83a18 | 738 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
739 | m_n->gmch_n = link_clock * nlanes; |
740 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
741 | m_n->link_m = pixel_clock; | |
742 | m_n->link_n = link_clock; | |
743 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
744 | } | |
745 | ||
746 | void | |
747 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
748 | struct drm_display_mode *adjusted_mode) | |
749 | { | |
750 | struct drm_device *dev = crtc->dev; | |
751 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 752 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
753 | struct drm_i915_private *dev_priv = dev->dev_private; |
754 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 755 | int lane_count = 4; |
a4fc5ed6 | 756 | struct intel_dp_m_n m_n; |
9db4a9c7 | 757 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
758 | |
759 | /* | |
21d40d37 | 760 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 761 | */ |
55f78c43 | 762 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 763 | struct intel_dp *intel_dp; |
a4fc5ed6 | 764 | |
d8201ab6 | 765 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
766 | continue; |
767 | ||
ea5b213a | 768 | intel_dp = enc_to_intel_dp(encoder); |
417e822d | 769 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || is_pch_edp(intel_dp)) { |
ea5b213a | 770 | lane_count = intel_dp->lane_count; |
51190667 | 771 | break; |
417e822d | 772 | } else if (is_cpu_edp(intel_dp)) { |
51190667 | 773 | lane_count = dev_priv->edp.lanes; |
a4fc5ed6 KP |
774 | break; |
775 | } | |
776 | } | |
777 | ||
778 | /* | |
779 | * Compute the GMCH and Link ratios. The '3' here is | |
780 | * the number of bytes_per_pixel post-LUT, which we always | |
781 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
782 | */ | |
858fa035 | 783 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
784 | mode->clock, adjusted_mode->clock, &m_n); |
785 | ||
c619eed4 | 786 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
787 | I915_WRITE(TRANSDATA_M1(pipe), |
788 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
789 | m_n.gmch_m); | |
790 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
791 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
792 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 793 | } else { |
9db4a9c7 JB |
794 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
795 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
796 | m_n.gmch_m); | |
797 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
798 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
799 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
800 | } |
801 | } | |
802 | ||
f01eca2e KP |
803 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
804 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
805 | ||
a4fc5ed6 KP |
806 | static void |
807 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
808 | struct drm_display_mode *adjusted_mode) | |
809 | { | |
e3421a18 | 810 | struct drm_device *dev = encoder->dev; |
417e822d | 811 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 812 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 813 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
815 | ||
f01eca2e KP |
816 | /* Turn on the eDP PLL if needed */ |
817 | if (is_edp(intel_dp)) { | |
818 | if (!is_pch_edp(intel_dp)) | |
819 | ironlake_edp_pll_on(encoder); | |
820 | else | |
821 | ironlake_edp_pll_off(encoder); | |
822 | } | |
823 | ||
417e822d KP |
824 | /* |
825 | * There are three kinds of DP registers: | |
826 | * | |
827 | * IBX PCH | |
828 | * CPU | |
829 | * CPT PCH | |
830 | * | |
831 | * IBX PCH and CPU are the same for almost everything, | |
832 | * except that the CPU DP PLL is configured in this | |
833 | * register | |
834 | * | |
835 | * CPT PCH is quite different, having many bits moved | |
836 | * to the TRANS_DP_CTL register instead. That | |
837 | * configuration happens (oddly) in ironlake_pch_enable | |
838 | */ | |
9c9e7927 | 839 | |
417e822d KP |
840 | /* Preserve the BIOS-computed detected bit. This is |
841 | * supposed to be read-only. | |
842 | */ | |
843 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
844 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 845 | |
417e822d KP |
846 | /* Handle DP bits in common between all three register formats */ |
847 | ||
848 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 849 | |
ea5b213a | 850 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 851 | case 1: |
ea5b213a | 852 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
853 | break; |
854 | case 2: | |
ea5b213a | 855 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
856 | break; |
857 | case 4: | |
ea5b213a | 858 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
859 | break; |
860 | } | |
e0dac65e WF |
861 | if (intel_dp->has_audio) { |
862 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
863 | pipe_name(intel_crtc->pipe)); | |
ea5b213a | 864 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
e0dac65e WF |
865 | intel_write_eld(encoder, adjusted_mode); |
866 | } | |
ea5b213a CW |
867 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
868 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
869 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 870 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 | 871 | /* |
9962c925 | 872 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 873 | */ |
7183dc29 JB |
874 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
875 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a | 876 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
a4fc5ed6 KP |
877 | } |
878 | ||
417e822d | 879 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 880 | |
417e822d KP |
881 | if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
882 | intel_dp->DP |= intel_dp->color_range; | |
883 | ||
884 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
885 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
886 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
887 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
888 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
889 | ||
890 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
891 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
892 | ||
893 | if (intel_crtc->pipe == 1) | |
894 | intel_dp->DP |= DP_PIPEB_SELECT; | |
895 | ||
896 | if (is_cpu_edp(intel_dp)) { | |
897 | /* don't miss out required setting for eDP */ | |
898 | intel_dp->DP |= DP_PLL_ENABLE; | |
899 | if (adjusted_mode->clock < 200000) | |
900 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | |
901 | else | |
902 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
903 | } | |
904 | } else { | |
905 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 906 | } |
a4fc5ed6 KP |
907 | } |
908 | ||
bd943159 KP |
909 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
910 | { | |
911 | unsigned long off_time; | |
912 | unsigned long delay; | |
32ce697c | 913 | |
bd943159 | 914 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
32ce697c KP |
915 | |
916 | if (ironlake_edp_have_panel_power(intel_dp) || | |
917 | ironlake_edp_have_panel_vdd(intel_dp)) | |
918 | { | |
919 | DRM_DEBUG_KMS("Panel still on, no delay needed\n"); | |
920 | return; | |
921 | } | |
922 | ||
bd943159 KP |
923 | off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay); |
924 | if (time_after(jiffies, off_time)) { | |
925 | DRM_DEBUG_KMS("Time already passed"); | |
926 | return; | |
927 | } | |
928 | delay = jiffies_to_msecs(off_time - jiffies); | |
929 | if (delay > intel_dp->panel_power_down_delay) | |
930 | delay = intel_dp->panel_power_down_delay; | |
931 | DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay); | |
932 | msleep(delay); | |
933 | } | |
934 | ||
832dd3c1 KP |
935 | /* Read the current pp_control value, unlocking the register if it |
936 | * is locked | |
937 | */ | |
938 | ||
939 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) | |
940 | { | |
941 | u32 control = I915_READ(PCH_PP_CONTROL); | |
942 | ||
943 | control &= ~PANEL_UNLOCK_MASK; | |
944 | control |= PANEL_UNLOCK_REGS; | |
945 | return control; | |
946 | } | |
947 | ||
5d613501 JB |
948 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
949 | { | |
950 | struct drm_device *dev = intel_dp->base.base.dev; | |
951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
952 | u32 pp; | |
953 | ||
97af61f5 KP |
954 | if (!is_edp(intel_dp)) |
955 | return; | |
f01eca2e | 956 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 957 | |
bd943159 KP |
958 | WARN(intel_dp->want_panel_vdd, |
959 | "eDP VDD already requested on\n"); | |
960 | ||
961 | intel_dp->want_panel_vdd = true; | |
962 | if (ironlake_edp_have_panel_vdd(intel_dp)) { | |
963 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
964 | return; | |
965 | } | |
966 | ||
967 | ironlake_wait_panel_off(intel_dp); | |
832dd3c1 | 968 | pp = ironlake_get_pp_control(dev_priv); |
5d613501 JB |
969 | pp |= EDP_FORCE_VDD; |
970 | I915_WRITE(PCH_PP_CONTROL, pp); | |
971 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
972 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
973 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
ebf33b18 KP |
974 | |
975 | /* | |
976 | * If the panel wasn't on, delay before accessing aux channel | |
977 | */ | |
978 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 979 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 980 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 981 | } |
5d613501 JB |
982 | } |
983 | ||
bd943159 | 984 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 JB |
985 | { |
986 | struct drm_device *dev = intel_dp->base.base.dev; | |
987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
988 | u32 pp; | |
989 | ||
bd943159 | 990 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
832dd3c1 | 991 | pp = ironlake_get_pp_control(dev_priv); |
bd943159 KP |
992 | pp &= ~EDP_FORCE_VDD; |
993 | I915_WRITE(PCH_PP_CONTROL, pp); | |
994 | POSTING_READ(PCH_PP_CONTROL); | |
995 | ||
996 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
997 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", | |
998 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
999 | intel_dp->panel_off_jiffies = jiffies; | |
1000 | } | |
1001 | } | |
5d613501 | 1002 | |
bd943159 KP |
1003 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1004 | { | |
1005 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1006 | struct intel_dp, panel_vdd_work); | |
1007 | struct drm_device *dev = intel_dp->base.base.dev; | |
1008 | ||
627f7675 | 1009 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 1010 | ironlake_panel_vdd_off_sync(intel_dp); |
627f7675 | 1011 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1012 | } |
1013 | ||
1014 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) | |
1015 | { | |
97af61f5 KP |
1016 | if (!is_edp(intel_dp)) |
1017 | return; | |
5d613501 | 1018 | |
bd943159 KP |
1019 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
1020 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
1021 | ||
1022 | intel_dp->want_panel_vdd = false; | |
1023 | ||
1024 | if (sync) { | |
1025 | ironlake_panel_vdd_off_sync(intel_dp); | |
1026 | } else { | |
1027 | /* | |
1028 | * Queue the timer to fire a long | |
1029 | * time from now (relative to the power down delay) | |
1030 | * to keep the panel power up across a sequence of operations | |
1031 | */ | |
1032 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1033 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1034 | } | |
5d613501 JB |
1035 | } |
1036 | ||
7eaf5547 | 1037 | /* Returns true if the panel was already on when called */ |
86a3073e | 1038 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1039 | { |
01cb9ea6 | 1040 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1041 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 1042 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 1043 | |
97af61f5 | 1044 | if (!is_edp(intel_dp)) |
bd943159 | 1045 | return; |
ebf33b18 | 1046 | if (ironlake_edp_have_panel_power(intel_dp)) |
7d639f35 | 1047 | return; |
9934c132 | 1048 | |
bd943159 | 1049 | ironlake_wait_panel_off(intel_dp); |
832dd3c1 | 1050 | pp = ironlake_get_pp_control(dev_priv); |
37c6c9b0 | 1051 | |
05ce1a49 KP |
1052 | if (IS_GEN5(dev)) { |
1053 | /* ILK workaround: disable reset around power sequence */ | |
1054 | pp &= ~PANEL_POWER_RESET; | |
1055 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1056 | POSTING_READ(PCH_PP_CONTROL); | |
1057 | } | |
37c6c9b0 | 1058 | |
1c0ae80a | 1059 | pp |= POWER_TARGET_ON; |
9934c132 | 1060 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 1061 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 1062 | |
01cb9ea6 JB |
1063 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
1064 | 5000)) | |
913d8d11 CW |
1065 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
1066 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 1067 | |
05ce1a49 KP |
1068 | if (IS_GEN5(dev)) { |
1069 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1070 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1071 | POSTING_READ(PCH_PP_CONTROL); | |
1072 | } | |
9934c132 JB |
1073 | } |
1074 | ||
f01eca2e | 1075 | static void ironlake_edp_panel_off(struct drm_encoder *encoder) |
9934c132 | 1076 | { |
f01eca2e KP |
1077 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1078 | struct drm_device *dev = encoder->dev; | |
9934c132 | 1079 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 JB |
1080 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
1081 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 | 1082 | |
97af61f5 KP |
1083 | if (!is_edp(intel_dp)) |
1084 | return; | |
832dd3c1 | 1085 | pp = ironlake_get_pp_control(dev_priv); |
37c6c9b0 | 1086 | |
05ce1a49 KP |
1087 | if (IS_GEN5(dev)) { |
1088 | /* ILK workaround: disable reset around power sequence */ | |
1089 | pp &= ~PANEL_POWER_RESET; | |
1090 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1091 | POSTING_READ(PCH_PP_CONTROL); | |
1092 | } | |
37c6c9b0 | 1093 | |
05ce1a49 | 1094 | intel_dp->panel_off_jiffies = jiffies; |
37c6c9b0 | 1095 | |
05ce1a49 KP |
1096 | if (IS_GEN5(dev)) { |
1097 | pp &= ~POWER_TARGET_ON; | |
1098 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1099 | POSTING_READ(PCH_PP_CONTROL); | |
1100 | pp &= ~POWER_TARGET_ON; | |
1101 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1102 | POSTING_READ(PCH_PP_CONTROL); | |
1103 | msleep(intel_dp->panel_power_cycle_delay); | |
9934c132 | 1104 | |
05ce1a49 KP |
1105 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
1106 | DRM_ERROR("panel off wait timed out: 0x%08x\n", | |
1107 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 1108 | |
05ce1a49 KP |
1109 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1110 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1111 | POSTING_READ(PCH_PP_CONTROL); | |
1112 | } | |
9934c132 JB |
1113 | } |
1114 | ||
86a3073e | 1115 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1116 | { |
f01eca2e | 1117 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1118 | struct drm_i915_private *dev_priv = dev->dev_private; |
1119 | u32 pp; | |
1120 | ||
f01eca2e KP |
1121 | if (!is_edp(intel_dp)) |
1122 | return; | |
1123 | ||
28c97730 | 1124 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1125 | /* |
1126 | * If we enable the backlight right away following a panel power | |
1127 | * on, we may see slight flicker as the panel syncs with the eDP | |
1128 | * link. So delay a bit to make sure the image is solid before | |
1129 | * allowing it to appear. | |
1130 | */ | |
f01eca2e | 1131 | msleep(intel_dp->backlight_on_delay); |
832dd3c1 | 1132 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1133 | pp |= EDP_BLC_ENABLE; |
1134 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 1135 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
1136 | } |
1137 | ||
86a3073e | 1138 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1139 | { |
f01eca2e | 1140 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
1142 | u32 pp; | |
1143 | ||
f01eca2e KP |
1144 | if (!is_edp(intel_dp)) |
1145 | return; | |
1146 | ||
28c97730 | 1147 | DRM_DEBUG_KMS("\n"); |
832dd3c1 | 1148 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1149 | pp &= ~EDP_BLC_ENABLE; |
1150 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1151 | POSTING_READ(PCH_PP_CONTROL); |
1152 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1153 | } |
a4fc5ed6 | 1154 | |
d240f20f JB |
1155 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1156 | { | |
1157 | struct drm_device *dev = encoder->dev; | |
1158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1159 | u32 dpa_ctl; | |
1160 | ||
1161 | DRM_DEBUG_KMS("\n"); | |
1162 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1163 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1164 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1165 | POSTING_READ(DP_A); |
1166 | udelay(200); | |
d240f20f JB |
1167 | } |
1168 | ||
1169 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1170 | { | |
1171 | struct drm_device *dev = encoder->dev; | |
1172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1173 | u32 dpa_ctl; | |
1174 | ||
1175 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1176 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1177 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1178 | POSTING_READ(DP_A); |
d240f20f JB |
1179 | udelay(200); |
1180 | } | |
1181 | ||
c7ad3810 JB |
1182 | /* If the sink supports it, try to set the power state appropriately */ |
1183 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1184 | { | |
1185 | int ret, i; | |
1186 | ||
1187 | /* Should have a valid DPCD by this point */ | |
1188 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1189 | return; | |
1190 | ||
1191 | if (mode != DRM_MODE_DPMS_ON) { | |
1192 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1193 | DP_SET_POWER_D3); | |
1194 | if (ret != 1) | |
1195 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1196 | } else { | |
1197 | /* | |
1198 | * When turning on, we need to retry for 1ms to give the sink | |
1199 | * time to wake up. | |
1200 | */ | |
1201 | for (i = 0; i < 3; i++) { | |
1202 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1203 | DP_SET_POWER, | |
1204 | DP_SET_POWER_D0); | |
1205 | if (ret == 1) | |
1206 | break; | |
1207 | msleep(1); | |
1208 | } | |
1209 | } | |
1210 | } | |
1211 | ||
d240f20f JB |
1212 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1213 | { | |
1214 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1215 | |
c7ad3810 | 1216 | /* Wake up the sink first */ |
f58ff854 | 1217 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1218 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
bd943159 | 1219 | ironlake_edp_panel_vdd_off(intel_dp, false); |
c7ad3810 | 1220 | |
f01eca2e KP |
1221 | /* Make sure the panel is off before trying to |
1222 | * change the mode | |
1223 | */ | |
1224 | ironlake_edp_backlight_off(intel_dp); | |
736085bc | 1225 | intel_dp_link_down(intel_dp); |
f01eca2e | 1226 | ironlake_edp_panel_off(encoder); |
d240f20f JB |
1227 | } |
1228 | ||
1229 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1230 | { | |
1231 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d4270e57 JB |
1232 | struct drm_device *dev = encoder->dev; |
1233 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); | |
5d613501 | 1234 | |
97af61f5 | 1235 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1236 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1237 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1238 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1239 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e JB |
1240 | |
1241 | intel_dp_complete_link_train(intel_dp); | |
f01eca2e | 1242 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1243 | |
1244 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d4270e57 JB |
1245 | |
1246 | if (HAS_PCH_CPT(dev)) | |
1247 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
d240f20f JB |
1248 | } |
1249 | ||
a4fc5ed6 KP |
1250 | static void |
1251 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1252 | { | |
ea5b213a | 1253 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1254 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1255 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1256 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1257 | |
1258 | if (mode != DRM_MODE_DPMS_ON) { | |
245e2708 | 1259 | ironlake_edp_panel_vdd_on(intel_dp); |
01cb9ea6 | 1260 | if (is_edp(intel_dp)) |
f01eca2e | 1261 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1262 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1263 | intel_dp_link_down(intel_dp); |
f01eca2e | 1264 | ironlake_edp_panel_off(encoder); |
01cb9ea6 | 1265 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
d240f20f | 1266 | ironlake_edp_pll_off(encoder); |
bd943159 | 1267 | ironlake_edp_panel_vdd_off(intel_dp, false); |
a4fc5ed6 | 1268 | } else { |
97af61f5 | 1269 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1270 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1271 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1272 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1273 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1274 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1275 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1276 | ironlake_edp_backlight_on(intel_dp); |
bee7eb2d | 1277 | } else |
bd943159 KP |
1278 | ironlake_edp_panel_vdd_off(intel_dp, false); |
1279 | ironlake_edp_backlight_on(intel_dp); | |
a4fc5ed6 | 1280 | } |
d2b996ac | 1281 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1282 | } |
1283 | ||
1284 | /* | |
df0c237d JB |
1285 | * Native read with retry for link status and receiver capability reads for |
1286 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1287 | */ |
1288 | static bool | |
df0c237d JB |
1289 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1290 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1291 | { |
61da5fab JB |
1292 | int ret, i; |
1293 | ||
df0c237d JB |
1294 | /* |
1295 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1296 | * but we're also supposed to retry 3 times per the spec. | |
1297 | */ | |
61da5fab | 1298 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1299 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1300 | recv_bytes); | |
1301 | if (ret == recv_bytes) | |
61da5fab JB |
1302 | return true; |
1303 | msleep(1); | |
1304 | } | |
a4fc5ed6 | 1305 | |
61da5fab | 1306 | return false; |
a4fc5ed6 KP |
1307 | } |
1308 | ||
1309 | /* | |
1310 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1311 | * link status information | |
1312 | */ | |
1313 | static bool | |
93f62dad | 1314 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1315 | { |
df0c237d JB |
1316 | return intel_dp_aux_native_read_retry(intel_dp, |
1317 | DP_LANE0_1_STATUS, | |
93f62dad | 1318 | link_status, |
df0c237d | 1319 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
1320 | } |
1321 | ||
1322 | static uint8_t | |
1323 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1324 | int r) | |
1325 | { | |
1326 | return link_status[r - DP_LANE0_1_STATUS]; | |
1327 | } | |
1328 | ||
a4fc5ed6 | 1329 | static uint8_t |
93f62dad | 1330 | intel_get_adjust_request_voltage(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1331 | int lane) |
1332 | { | |
a4fc5ed6 KP |
1333 | int s = ((lane & 1) ? |
1334 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1335 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
93f62dad | 1336 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1337 | |
1338 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1339 | } | |
1340 | ||
1341 | static uint8_t | |
93f62dad | 1342 | intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1343 | int lane) |
1344 | { | |
a4fc5ed6 KP |
1345 | int s = ((lane & 1) ? |
1346 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1347 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
93f62dad | 1348 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1349 | |
1350 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1351 | } | |
1352 | ||
1353 | ||
1354 | #if 0 | |
1355 | static char *voltage_names[] = { | |
1356 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1357 | }; | |
1358 | static char *pre_emph_names[] = { | |
1359 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1360 | }; | |
1361 | static char *link_train_names[] = { | |
1362 | "pattern 1", "pattern 2", "idle", "off" | |
1363 | }; | |
1364 | #endif | |
1365 | ||
1366 | /* | |
1367 | * These are source-specific values; current Intel hardware supports | |
1368 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1369 | */ | |
1370 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
417e822d | 1371 | #define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200 |
a4fc5ed6 KP |
1372 | |
1373 | static uint8_t | |
1374 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1375 | { | |
1376 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1377 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1378 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1379 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1380 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1381 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1382 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1383 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1384 | default: | |
1385 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1386 | } | |
1387 | } | |
1388 | ||
1389 | static void | |
93f62dad | 1390 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1391 | { |
93f62dad | 1392 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
1393 | uint8_t v = 0; |
1394 | uint8_t p = 0; | |
1395 | int lane; | |
93f62dad KP |
1396 | uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); |
1397 | int voltage_max; | |
a4fc5ed6 | 1398 | |
33a34e4e | 1399 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad KP |
1400 | uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); |
1401 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); | |
a4fc5ed6 KP |
1402 | |
1403 | if (this_v > v) | |
1404 | v = this_v; | |
1405 | if (this_p > p) | |
1406 | p = this_p; | |
1407 | } | |
1408 | ||
417e822d KP |
1409 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
1410 | voltage_max = I830_DP_VOLTAGE_MAX_CPT; | |
1411 | else | |
1412 | voltage_max = I830_DP_VOLTAGE_MAX; | |
1413 | if (v >= voltage_max) | |
1414 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 KP |
1415 | |
1416 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1417 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1418 | ||
1419 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1420 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1421 | } |
1422 | ||
1423 | static uint32_t | |
93f62dad | 1424 | intel_dp_signal_levels(uint8_t train_set) |
a4fc5ed6 | 1425 | { |
3cf2efb1 | 1426 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1427 | |
3cf2efb1 | 1428 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1429 | case DP_TRAIN_VOLTAGE_SWING_400: |
1430 | default: | |
1431 | signal_levels |= DP_VOLTAGE_0_4; | |
1432 | break; | |
1433 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1434 | signal_levels |= DP_VOLTAGE_0_6; | |
1435 | break; | |
1436 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1437 | signal_levels |= DP_VOLTAGE_0_8; | |
1438 | break; | |
1439 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1440 | signal_levels |= DP_VOLTAGE_1_2; | |
1441 | break; | |
1442 | } | |
3cf2efb1 | 1443 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1444 | case DP_TRAIN_PRE_EMPHASIS_0: |
1445 | default: | |
1446 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1447 | break; | |
1448 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1449 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1450 | break; | |
1451 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1452 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1453 | break; | |
1454 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1455 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1456 | break; | |
1457 | } | |
1458 | return signal_levels; | |
1459 | } | |
1460 | ||
e3421a18 ZW |
1461 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1462 | static uint32_t | |
1463 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1464 | { | |
3c5a62b5 YL |
1465 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1466 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1467 | switch (signal_levels) { | |
e3421a18 | 1468 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1469 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1470 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1471 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1472 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1473 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1474 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1475 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1476 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1477 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1478 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1479 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1480 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1481 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1482 | default: |
3c5a62b5 YL |
1483 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1484 | "0x%x\n", signal_levels); | |
1485 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1486 | } |
1487 | } | |
1488 | ||
a4fc5ed6 KP |
1489 | static uint8_t |
1490 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1491 | int lane) | |
1492 | { | |
a4fc5ed6 | 1493 | int s = (lane & 1) * 4; |
93f62dad | 1494 | uint8_t l = link_status[lane>>1]; |
a4fc5ed6 KP |
1495 | |
1496 | return (l >> s) & 0xf; | |
1497 | } | |
1498 | ||
1499 | /* Check for clock recovery is done on all channels */ | |
1500 | static bool | |
1501 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1502 | { | |
1503 | int lane; | |
1504 | uint8_t lane_status; | |
1505 | ||
1506 | for (lane = 0; lane < lane_count; lane++) { | |
1507 | lane_status = intel_get_lane_status(link_status, lane); | |
1508 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1509 | return false; | |
1510 | } | |
1511 | return true; | |
1512 | } | |
1513 | ||
1514 | /* Check to see if channel eq is done on all channels */ | |
1515 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1516 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1517 | DP_LANE_SYMBOL_LOCKED) | |
1518 | static bool | |
93f62dad | 1519 | intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 KP |
1520 | { |
1521 | uint8_t lane_align; | |
1522 | uint8_t lane_status; | |
1523 | int lane; | |
1524 | ||
93f62dad | 1525 | lane_align = intel_dp_link_status(link_status, |
a4fc5ed6 KP |
1526 | DP_LANE_ALIGN_STATUS_UPDATED); |
1527 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1528 | return false; | |
33a34e4e | 1529 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad | 1530 | lane_status = intel_get_lane_status(link_status, lane); |
a4fc5ed6 KP |
1531 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1532 | return false; | |
1533 | } | |
1534 | return true; | |
1535 | } | |
1536 | ||
1537 | static bool | |
ea5b213a | 1538 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1539 | uint32_t dp_reg_value, |
58e10eb9 | 1540 | uint8_t dp_train_pat) |
a4fc5ed6 | 1541 | { |
4ef69c7a | 1542 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1543 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1544 | int ret; |
1545 | ||
ea5b213a CW |
1546 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1547 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1548 | |
ea5b213a | 1549 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1550 | DP_TRAINING_PATTERN_SET, |
1551 | dp_train_pat); | |
1552 | ||
ea5b213a | 1553 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1554 | DP_TRAINING_LANE0_SET, |
1555 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1556 | if (ret != 4) |
1557 | return false; | |
1558 | ||
1559 | return true; | |
1560 | } | |
1561 | ||
33a34e4e | 1562 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1563 | static void |
33a34e4e | 1564 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1565 | { |
4ef69c7a | 1566 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1567 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1568 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1569 | int i; |
1570 | uint8_t voltage; | |
1571 | bool clock_recovery = false; | |
a4fc5ed6 | 1572 | int tries; |
e3421a18 | 1573 | u32 reg; |
ea5b213a | 1574 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1575 | |
e8519464 AJ |
1576 | /* |
1577 | * On CPT we have to enable the port in training pattern 1, which | |
1578 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1579 | * the port and wait for it to become active. | |
1580 | */ | |
1581 | if (!HAS_PCH_CPT(dev)) { | |
1582 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1583 | POSTING_READ(intel_dp->output_reg); | |
1584 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1585 | } | |
a4fc5ed6 | 1586 | |
3cf2efb1 CW |
1587 | /* Write the link configuration data */ |
1588 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1589 | intel_dp->link_configuration, | |
1590 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1591 | |
1592 | DP |= DP_PORT_EN; | |
82d16555 | 1593 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1594 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1595 | else | |
1596 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1597 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1598 | voltage = 0xff; |
1599 | tries = 0; | |
1600 | clock_recovery = false; | |
1601 | for (;;) { | |
33a34e4e | 1602 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
93f62dad | 1603 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1604 | uint32_t signal_levels; |
417e822d KP |
1605 | |
1606 | if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { | |
33a34e4e | 1607 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1608 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1609 | } else { | |
93f62dad KP |
1610 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
1611 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); | |
e3421a18 ZW |
1612 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1613 | } | |
a4fc5ed6 | 1614 | |
82d16555 | 1615 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1616 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1617 | else | |
1618 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1619 | ||
ea5b213a | 1620 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1621 | DP_TRAINING_PATTERN_1 | |
1622 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1623 | break; |
a4fc5ed6 KP |
1624 | /* Set training pattern 1 */ |
1625 | ||
3cf2efb1 | 1626 | udelay(100); |
93f62dad KP |
1627 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1628 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 1629 | break; |
93f62dad | 1630 | } |
a4fc5ed6 | 1631 | |
93f62dad KP |
1632 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1633 | DRM_DEBUG_KMS("clock recovery OK\n"); | |
3cf2efb1 CW |
1634 | clock_recovery = true; |
1635 | break; | |
1636 | } | |
1637 | ||
1638 | /* Check to see if we've tried the max voltage */ | |
1639 | for (i = 0; i < intel_dp->lane_count; i++) | |
1640 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1641 | break; |
3cf2efb1 CW |
1642 | if (i == intel_dp->lane_count) |
1643 | break; | |
a4fc5ed6 | 1644 | |
3cf2efb1 CW |
1645 | /* Check to see if we've tried the same voltage 5 times */ |
1646 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1647 | ++tries; | |
1648 | if (tries == 5) | |
a4fc5ed6 | 1649 | break; |
3cf2efb1 CW |
1650 | } else |
1651 | tries = 0; | |
1652 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1653 | |
3cf2efb1 | 1654 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1655 | intel_get_adjust_train(intel_dp, link_status); |
a4fc5ed6 KP |
1656 | } |
1657 | ||
33a34e4e JB |
1658 | intel_dp->DP = DP; |
1659 | } | |
1660 | ||
1661 | static void | |
1662 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1663 | { | |
4ef69c7a | 1664 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1665 | struct drm_i915_private *dev_priv = dev->dev_private; |
1666 | bool channel_eq = false; | |
37f80975 | 1667 | int tries, cr_tries; |
33a34e4e JB |
1668 | u32 reg; |
1669 | uint32_t DP = intel_dp->DP; | |
1670 | ||
a4fc5ed6 KP |
1671 | /* channel equalization */ |
1672 | tries = 0; | |
37f80975 | 1673 | cr_tries = 0; |
a4fc5ed6 KP |
1674 | channel_eq = false; |
1675 | for (;;) { | |
33a34e4e | 1676 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1677 | uint32_t signal_levels; |
93f62dad | 1678 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1679 | |
37f80975 JB |
1680 | if (cr_tries > 5) { |
1681 | DRM_ERROR("failed to train DP, aborting\n"); | |
1682 | intel_dp_link_down(intel_dp); | |
1683 | break; | |
1684 | } | |
1685 | ||
417e822d | 1686 | if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
33a34e4e | 1687 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1688 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1689 | } else { | |
93f62dad | 1690 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1691 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1692 | } | |
1693 | ||
82d16555 | 1694 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1695 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1696 | else | |
1697 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1698 | |
1699 | /* channel eq pattern */ | |
ea5b213a | 1700 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1701 | DP_TRAINING_PATTERN_2 | |
1702 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1703 | break; |
1704 | ||
3cf2efb1 | 1705 | udelay(400); |
93f62dad | 1706 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 | 1707 | break; |
a4fc5ed6 | 1708 | |
37f80975 | 1709 | /* Make sure clock is still ok */ |
93f62dad | 1710 | if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 JB |
1711 | intel_dp_start_link_train(intel_dp); |
1712 | cr_tries++; | |
1713 | continue; | |
1714 | } | |
1715 | ||
93f62dad | 1716 | if (intel_channel_eq_ok(intel_dp, link_status)) { |
3cf2efb1 CW |
1717 | channel_eq = true; |
1718 | break; | |
1719 | } | |
a4fc5ed6 | 1720 | |
37f80975 JB |
1721 | /* Try 5 times, then try clock recovery if that fails */ |
1722 | if (tries > 5) { | |
1723 | intel_dp_link_down(intel_dp); | |
1724 | intel_dp_start_link_train(intel_dp); | |
1725 | tries = 0; | |
1726 | cr_tries++; | |
1727 | continue; | |
1728 | } | |
a4fc5ed6 | 1729 | |
3cf2efb1 | 1730 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1731 | intel_get_adjust_train(intel_dp, link_status); |
3cf2efb1 | 1732 | ++tries; |
869184a6 | 1733 | } |
3cf2efb1 | 1734 | |
82d16555 | 1735 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1736 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1737 | else | |
1738 | reg = DP | DP_LINK_TRAIN_OFF; | |
1739 | ||
ea5b213a CW |
1740 | I915_WRITE(intel_dp->output_reg, reg); |
1741 | POSTING_READ(intel_dp->output_reg); | |
1742 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1743 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1744 | } | |
1745 | ||
1746 | static void | |
ea5b213a | 1747 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1748 | { |
4ef69c7a | 1749 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1750 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1751 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1752 | |
1b39d6f3 CW |
1753 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1754 | return; | |
1755 | ||
28c97730 | 1756 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1757 | |
cfcb0fc9 | 1758 | if (is_edp(intel_dp)) { |
32f9d658 | 1759 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1760 | I915_WRITE(intel_dp->output_reg, DP); |
1761 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1762 | udelay(100); |
1763 | } | |
1764 | ||
82d16555 | 1765 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) { |
e3421a18 | 1766 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1767 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1768 | } else { |
1769 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1770 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1771 | } |
fe255d00 | 1772 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1773 | |
fe255d00 | 1774 | msleep(17); |
5eb08b69 | 1775 | |
417e822d KP |
1776 | if (is_edp(intel_dp)) { |
1777 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) | |
1778 | DP |= DP_LINK_TRAIN_OFF_CPT; | |
1779 | else | |
1780 | DP |= DP_LINK_TRAIN_OFF; | |
1781 | } | |
5bddd17f | 1782 | |
1b39d6f3 CW |
1783 | if (!HAS_PCH_CPT(dev) && |
1784 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1785 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1786 | ||
5bddd17f EA |
1787 | /* Hardware workaround: leaving our transcoder select |
1788 | * set to transcoder B while it's off will prevent the | |
1789 | * corresponding HDMI output on transcoder A. | |
1790 | * | |
1791 | * Combine this with another hardware workaround: | |
1792 | * transcoder select bit can only be cleared while the | |
1793 | * port is enabled. | |
1794 | */ | |
1795 | DP &= ~DP_PIPEB_SELECT; | |
1796 | I915_WRITE(intel_dp->output_reg, DP); | |
1797 | ||
1798 | /* Changes to enable or select take place the vblank | |
1799 | * after being written. | |
1800 | */ | |
31acbcc4 CW |
1801 | if (crtc == NULL) { |
1802 | /* We can arrive here never having been attached | |
1803 | * to a CRTC, for instance, due to inheriting | |
1804 | * random state from the BIOS. | |
1805 | * | |
1806 | * If the pipe is not running, play safe and | |
1807 | * wait for the clocks to stabilise before | |
1808 | * continuing. | |
1809 | */ | |
1810 | POSTING_READ(intel_dp->output_reg); | |
1811 | msleep(50); | |
1812 | } else | |
1813 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1814 | } |
1815 | ||
ea5b213a CW |
1816 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1817 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1818 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1819 | } |
1820 | ||
26d61aad KP |
1821 | static bool |
1822 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1823 | { |
92fd8fd1 | 1824 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
0206e353 | 1825 | sizeof(intel_dp->dpcd)) && |
92fd8fd1 | 1826 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { |
26d61aad | 1827 | return true; |
92fd8fd1 KP |
1828 | } |
1829 | ||
26d61aad | 1830 | return false; |
92fd8fd1 KP |
1831 | } |
1832 | ||
a60f0e38 JB |
1833 | static bool |
1834 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
1835 | { | |
1836 | int ret; | |
1837 | ||
1838 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
1839 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1840 | sink_irq_vector, 1); | |
1841 | if (!ret) | |
1842 | return false; | |
1843 | ||
1844 | return true; | |
1845 | } | |
1846 | ||
1847 | static void | |
1848 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
1849 | { | |
1850 | /* NAK by default */ | |
1851 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); | |
1852 | } | |
1853 | ||
a4fc5ed6 KP |
1854 | /* |
1855 | * According to DP spec | |
1856 | * 5.1.2: | |
1857 | * 1. Read DPCD | |
1858 | * 2. Configure link according to Receiver Capabilities | |
1859 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1860 | * 4. Check link status on receipt of hot-plug interrupt | |
1861 | */ | |
1862 | ||
1863 | static void | |
ea5b213a | 1864 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1865 | { |
a60f0e38 | 1866 | u8 sink_irq_vector; |
93f62dad | 1867 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 1868 | |
d2b996ac KP |
1869 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1870 | return; | |
59cd09e1 | 1871 | |
4ef69c7a | 1872 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1873 | return; |
1874 | ||
92fd8fd1 | 1875 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 1876 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
ea5b213a | 1877 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1878 | return; |
1879 | } | |
1880 | ||
92fd8fd1 | 1881 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1882 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1883 | intel_dp_link_down(intel_dp); |
1884 | return; | |
1885 | } | |
1886 | ||
a60f0e38 JB |
1887 | /* Try to read the source of the interrupt */ |
1888 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
1889 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
1890 | /* Clear interrupt source */ | |
1891 | intel_dp_aux_native_write_1(intel_dp, | |
1892 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1893 | sink_irq_vector); | |
1894 | ||
1895 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
1896 | intel_dp_handle_test_request(intel_dp); | |
1897 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
1898 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
1899 | } | |
1900 | ||
93f62dad | 1901 | if (!intel_channel_eq_ok(intel_dp, link_status)) { |
92fd8fd1 KP |
1902 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1903 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1904 | intel_dp_start_link_train(intel_dp); |
1905 | intel_dp_complete_link_train(intel_dp); | |
1906 | } | |
a4fc5ed6 | 1907 | } |
a4fc5ed6 | 1908 | |
71ba9000 | 1909 | static enum drm_connector_status |
26d61aad | 1910 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1911 | { |
26d61aad KP |
1912 | if (intel_dp_get_dpcd(intel_dp)) |
1913 | return connector_status_connected; | |
1914 | return connector_status_disconnected; | |
71ba9000 AJ |
1915 | } |
1916 | ||
5eb08b69 | 1917 | static enum drm_connector_status |
a9756bb5 | 1918 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1919 | { |
5eb08b69 ZW |
1920 | enum drm_connector_status status; |
1921 | ||
fe16d949 CW |
1922 | /* Can't disconnect eDP, but you can close the lid... */ |
1923 | if (is_edp(intel_dp)) { | |
1924 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1925 | if (status == connector_status_unknown) | |
1926 | status = connector_status_connected; | |
1927 | return status; | |
1928 | } | |
01cb9ea6 | 1929 | |
26d61aad | 1930 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1931 | } |
1932 | ||
a4fc5ed6 | 1933 | static enum drm_connector_status |
a9756bb5 | 1934 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1935 | { |
4ef69c7a | 1936 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1937 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1938 | uint32_t temp, bit; |
5eb08b69 | 1939 | |
ea5b213a | 1940 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1941 | case DP_B: |
1942 | bit = DPB_HOTPLUG_INT_STATUS; | |
1943 | break; | |
1944 | case DP_C: | |
1945 | bit = DPC_HOTPLUG_INT_STATUS; | |
1946 | break; | |
1947 | case DP_D: | |
1948 | bit = DPD_HOTPLUG_INT_STATUS; | |
1949 | break; | |
1950 | default: | |
1951 | return connector_status_unknown; | |
1952 | } | |
1953 | ||
1954 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1955 | ||
1956 | if ((temp & bit) == 0) | |
1957 | return connector_status_disconnected; | |
1958 | ||
26d61aad | 1959 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1960 | } |
1961 | ||
8c241fef KP |
1962 | static struct edid * |
1963 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1964 | { | |
1965 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1966 | struct edid *edid; | |
1967 | ||
1968 | ironlake_edp_panel_vdd_on(intel_dp); | |
1969 | edid = drm_get_edid(connector, adapter); | |
bd943159 | 1970 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1971 | return edid; |
1972 | } | |
1973 | ||
1974 | static int | |
1975 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1976 | { | |
1977 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1978 | int ret; | |
1979 | ||
1980 | ironlake_edp_panel_vdd_on(intel_dp); | |
1981 | ret = intel_ddc_get_modes(connector, adapter); | |
bd943159 | 1982 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1983 | return ret; |
1984 | } | |
1985 | ||
1986 | ||
a9756bb5 ZW |
1987 | /** |
1988 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1989 | * | |
1990 | * \return true if DP port is connected. | |
1991 | * \return false if DP port is disconnected. | |
1992 | */ | |
1993 | static enum drm_connector_status | |
1994 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1995 | { | |
1996 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1997 | struct drm_device *dev = intel_dp->base.base.dev; | |
1998 | enum drm_connector_status status; | |
1999 | struct edid *edid = NULL; | |
2000 | ||
2001 | intel_dp->has_audio = false; | |
2002 | ||
2003 | if (HAS_PCH_SPLIT(dev)) | |
2004 | status = ironlake_dp_detect(intel_dp); | |
2005 | else | |
2006 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 2007 | |
ac66ae83 AJ |
2008 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
2009 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
2010 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
2011 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 2012 | |
a9756bb5 ZW |
2013 | if (status != connector_status_connected) |
2014 | return status; | |
2015 | ||
f684960e CW |
2016 | if (intel_dp->force_audio) { |
2017 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
2018 | } else { | |
8c241fef | 2019 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
2020 | if (edid) { |
2021 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
2022 | connector->display_info.raw_edid = NULL; | |
2023 | kfree(edid); | |
2024 | } | |
a9756bb5 ZW |
2025 | } |
2026 | ||
2027 | return connector_status_connected; | |
a4fc5ed6 KP |
2028 | } |
2029 | ||
2030 | static int intel_dp_get_modes(struct drm_connector *connector) | |
2031 | { | |
df0e9248 | 2032 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 2033 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
2034 | struct drm_i915_private *dev_priv = dev->dev_private; |
2035 | int ret; | |
a4fc5ed6 KP |
2036 | |
2037 | /* We should parse the EDID data and find out if it has an audio sink | |
2038 | */ | |
2039 | ||
8c241fef | 2040 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 2041 | if (ret) { |
d15456de | 2042 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
b9efc480 ZY |
2043 | struct drm_display_mode *newmode; |
2044 | list_for_each_entry(newmode, &connector->probed_modes, | |
2045 | head) { | |
d15456de KP |
2046 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
2047 | intel_dp->panel_fixed_mode = | |
b9efc480 ZY |
2048 | drm_mode_duplicate(dev, newmode); |
2049 | break; | |
2050 | } | |
2051 | } | |
2052 | } | |
32f9d658 | 2053 | return ret; |
b9efc480 | 2054 | } |
32f9d658 ZW |
2055 | |
2056 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 2057 | if (is_edp(intel_dp)) { |
47f0eb22 | 2058 | /* initialize panel mode from VBT if available for eDP */ |
d15456de KP |
2059 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
2060 | intel_dp->panel_fixed_mode = | |
47f0eb22 | 2061 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
d15456de KP |
2062 | if (intel_dp->panel_fixed_mode) { |
2063 | intel_dp->panel_fixed_mode->type |= | |
47f0eb22 KP |
2064 | DRM_MODE_TYPE_PREFERRED; |
2065 | } | |
2066 | } | |
d15456de | 2067 | if (intel_dp->panel_fixed_mode) { |
32f9d658 | 2068 | struct drm_display_mode *mode; |
d15456de | 2069 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
32f9d658 ZW |
2070 | drm_mode_probed_add(connector, mode); |
2071 | return 1; | |
2072 | } | |
2073 | } | |
2074 | return 0; | |
a4fc5ed6 KP |
2075 | } |
2076 | ||
1aad7ac0 CW |
2077 | static bool |
2078 | intel_dp_detect_audio(struct drm_connector *connector) | |
2079 | { | |
2080 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2081 | struct edid *edid; | |
2082 | bool has_audio = false; | |
2083 | ||
8c241fef | 2084 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
2085 | if (edid) { |
2086 | has_audio = drm_detect_monitor_audio(edid); | |
2087 | ||
2088 | connector->display_info.raw_edid = NULL; | |
2089 | kfree(edid); | |
2090 | } | |
2091 | ||
2092 | return has_audio; | |
2093 | } | |
2094 | ||
f684960e CW |
2095 | static int |
2096 | intel_dp_set_property(struct drm_connector *connector, | |
2097 | struct drm_property *property, | |
2098 | uint64_t val) | |
2099 | { | |
e953fd7b | 2100 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
2101 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2102 | int ret; | |
2103 | ||
2104 | ret = drm_connector_property_set_value(connector, property, val); | |
2105 | if (ret) | |
2106 | return ret; | |
2107 | ||
3f43c48d | 2108 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2109 | int i = val; |
2110 | bool has_audio; | |
2111 | ||
2112 | if (i == intel_dp->force_audio) | |
f684960e CW |
2113 | return 0; |
2114 | ||
1aad7ac0 | 2115 | intel_dp->force_audio = i; |
f684960e | 2116 | |
1aad7ac0 CW |
2117 | if (i == 0) |
2118 | has_audio = intel_dp_detect_audio(connector); | |
2119 | else | |
2120 | has_audio = i > 0; | |
2121 | ||
2122 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2123 | return 0; |
2124 | ||
1aad7ac0 | 2125 | intel_dp->has_audio = has_audio; |
f684960e CW |
2126 | goto done; |
2127 | } | |
2128 | ||
e953fd7b CW |
2129 | if (property == dev_priv->broadcast_rgb_property) { |
2130 | if (val == !!intel_dp->color_range) | |
2131 | return 0; | |
2132 | ||
2133 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
2134 | goto done; | |
2135 | } | |
2136 | ||
f684960e CW |
2137 | return -EINVAL; |
2138 | ||
2139 | done: | |
2140 | if (intel_dp->base.base.crtc) { | |
2141 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
2142 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
2143 | crtc->x, crtc->y, | |
2144 | crtc->fb); | |
2145 | } | |
2146 | ||
2147 | return 0; | |
2148 | } | |
2149 | ||
a4fc5ed6 | 2150 | static void |
0206e353 | 2151 | intel_dp_destroy(struct drm_connector *connector) |
a4fc5ed6 | 2152 | { |
aaa6fd2a MG |
2153 | struct drm_device *dev = connector->dev; |
2154 | ||
2155 | if (intel_dpd_is_edp(dev)) | |
2156 | intel_panel_destroy_backlight(dev); | |
2157 | ||
a4fc5ed6 KP |
2158 | drm_sysfs_connector_remove(connector); |
2159 | drm_connector_cleanup(connector); | |
55f78c43 | 2160 | kfree(connector); |
a4fc5ed6 KP |
2161 | } |
2162 | ||
24d05927 DV |
2163 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2164 | { | |
2165 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2166 | ||
2167 | i2c_del_adapter(&intel_dp->adapter); | |
2168 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
2169 | if (is_edp(intel_dp)) { |
2170 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
2171 | ironlake_panel_vdd_off_sync(intel_dp); | |
2172 | } | |
24d05927 DV |
2173 | kfree(intel_dp); |
2174 | } | |
2175 | ||
a4fc5ed6 KP |
2176 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
2177 | .dpms = intel_dp_dpms, | |
2178 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 2179 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 2180 | .mode_set = intel_dp_mode_set, |
d240f20f | 2181 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
2182 | }; |
2183 | ||
2184 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2185 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
2186 | .detect = intel_dp_detect, |
2187 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2188 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2189 | .destroy = intel_dp_destroy, |
2190 | }; | |
2191 | ||
2192 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2193 | .get_modes = intel_dp_get_modes, | |
2194 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2195 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2196 | }; |
2197 | ||
a4fc5ed6 | 2198 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2199 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2200 | }; |
2201 | ||
995b6762 | 2202 | static void |
21d40d37 | 2203 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2204 | { |
ea5b213a | 2205 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2206 | |
885a5014 | 2207 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2208 | } |
6207937d | 2209 | |
e3421a18 ZW |
2210 | /* Return which DP Port should be selected for Transcoder DP control */ |
2211 | int | |
0206e353 | 2212 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
2213 | { |
2214 | struct drm_device *dev = crtc->dev; | |
2215 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2216 | struct drm_encoder *encoder; | |
e3421a18 ZW |
2217 | |
2218 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
2219 | struct intel_dp *intel_dp; |
2220 | ||
d8201ab6 | 2221 | if (encoder->crtc != crtc) |
e3421a18 ZW |
2222 | continue; |
2223 | ||
ea5b213a | 2224 | intel_dp = enc_to_intel_dp(encoder); |
417e822d KP |
2225 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
2226 | intel_dp->base.type == INTEL_OUTPUT_EDP) | |
ea5b213a | 2227 | return intel_dp->output_reg; |
e3421a18 | 2228 | } |
ea5b213a | 2229 | |
e3421a18 ZW |
2230 | return -1; |
2231 | } | |
2232 | ||
36e83a18 | 2233 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2234 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2235 | { |
2236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2237 | struct child_device_config *p_child; | |
2238 | int i; | |
2239 | ||
2240 | if (!dev_priv->child_dev_num) | |
2241 | return false; | |
2242 | ||
2243 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2244 | p_child = dev_priv->child_dev + i; | |
2245 | ||
2246 | if (p_child->dvo_port == PORT_IDPD && | |
2247 | p_child->device_type == DEVICE_TYPE_eDP) | |
2248 | return true; | |
2249 | } | |
2250 | return false; | |
2251 | } | |
2252 | ||
f684960e CW |
2253 | static void |
2254 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2255 | { | |
3f43c48d | 2256 | intel_attach_force_audio_property(connector); |
e953fd7b | 2257 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2258 | } |
2259 | ||
a4fc5ed6 KP |
2260 | void |
2261 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2262 | { | |
2263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2264 | struct drm_connector *connector; | |
ea5b213a | 2265 | struct intel_dp *intel_dp; |
21d40d37 | 2266 | struct intel_encoder *intel_encoder; |
55f78c43 | 2267 | struct intel_connector *intel_connector; |
5eb08b69 | 2268 | const char *name = NULL; |
b329530c | 2269 | int type; |
a4fc5ed6 | 2270 | |
ea5b213a CW |
2271 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2272 | if (!intel_dp) | |
a4fc5ed6 KP |
2273 | return; |
2274 | ||
3d3dc149 | 2275 | intel_dp->output_reg = output_reg; |
d2b996ac | 2276 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2277 | |
55f78c43 ZW |
2278 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2279 | if (!intel_connector) { | |
ea5b213a | 2280 | kfree(intel_dp); |
55f78c43 ZW |
2281 | return; |
2282 | } | |
ea5b213a | 2283 | intel_encoder = &intel_dp->base; |
55f78c43 | 2284 | |
ea5b213a | 2285 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2286 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2287 | intel_dp->is_pch_edp = true; |
b329530c | 2288 | |
cfcb0fc9 | 2289 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2290 | type = DRM_MODE_CONNECTOR_eDP; |
2291 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2292 | } else { | |
2293 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2294 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2295 | } | |
2296 | ||
55f78c43 | 2297 | connector = &intel_connector->base; |
b329530c | 2298 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2299 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2300 | ||
eb1f8e4f DA |
2301 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2302 | ||
652af9d7 | 2303 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2304 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2305 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2306 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2307 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2308 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2309 | |
bd943159 | 2310 | if (is_edp(intel_dp)) { |
21d40d37 | 2311 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
bd943159 KP |
2312 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2313 | ironlake_panel_vdd_work); | |
2314 | } | |
6251ec0a | 2315 | |
27f8227b | 2316 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
a4fc5ed6 KP |
2317 | connector->interlace_allowed = true; |
2318 | connector->doublescan_allowed = 0; | |
2319 | ||
4ef69c7a | 2320 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2321 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2322 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2323 | |
df0e9248 | 2324 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2325 | drm_sysfs_connector_add(connector); |
2326 | ||
2327 | /* Set up the DDC bus. */ | |
5eb08b69 | 2328 | switch (output_reg) { |
32f9d658 ZW |
2329 | case DP_A: |
2330 | name = "DPDDC-A"; | |
2331 | break; | |
5eb08b69 ZW |
2332 | case DP_B: |
2333 | case PCH_DP_B: | |
b01f2c3a JB |
2334 | dev_priv->hotplug_supported_mask |= |
2335 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2336 | name = "DPDDC-B"; |
2337 | break; | |
2338 | case DP_C: | |
2339 | case PCH_DP_C: | |
b01f2c3a JB |
2340 | dev_priv->hotplug_supported_mask |= |
2341 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2342 | name = "DPDDC-C"; |
2343 | break; | |
2344 | case DP_D: | |
2345 | case PCH_DP_D: | |
b01f2c3a JB |
2346 | dev_priv->hotplug_supported_mask |= |
2347 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2348 | name = "DPDDC-D"; |
2349 | break; | |
2350 | } | |
2351 | ||
89667383 JB |
2352 | /* Cache some DPCD data in the eDP case */ |
2353 | if (is_edp(intel_dp)) { | |
59f3e272 | 2354 | bool ret; |
f01eca2e KP |
2355 | struct edp_power_seq cur, vbt; |
2356 | u32 pp_on, pp_off, pp_div; | |
5d613501 JB |
2357 | |
2358 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2359 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2360 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2361 | |
f01eca2e KP |
2362 | /* Pull timing values out of registers */ |
2363 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2364 | PANEL_POWER_UP_DELAY_SHIFT; | |
2365 | ||
2366 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2367 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
2368 | ||
2369 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
2370 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2371 | ||
2372 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2373 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2374 | ||
2375 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2376 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2377 | ||
2378 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2379 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2380 | ||
2381 | vbt = dev_priv->edp.pps; | |
2382 | ||
2383 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2384 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2385 | ||
2386 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2387 | ||
2388 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2389 | intel_dp->backlight_on_delay = get_delay(t8); | |
2390 | intel_dp->backlight_off_delay = get_delay(t9); | |
2391 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2392 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2393 | ||
2394 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2395 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2396 | intel_dp->panel_power_cycle_delay); | |
2397 | ||
2398 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2399 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 | 2400 | |
bd943159 | 2401 | intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay; |
5d613501 JB |
2402 | |
2403 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2404 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 2405 | ironlake_edp_panel_vdd_off(intel_dp, false); |
59f3e272 | 2406 | if (ret) { |
7183dc29 JB |
2407 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2408 | dev_priv->no_aux_handshake = | |
2409 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2410 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2411 | } else { | |
3d3dc149 | 2412 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2413 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2414 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2415 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2416 | return; |
89667383 | 2417 | } |
89667383 JB |
2418 | } |
2419 | ||
552fb0b7 KP |
2420 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2421 | ||
21d40d37 | 2422 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2423 | |
4d926461 | 2424 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2425 | dev_priv->int_edp_connector = connector; |
2426 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2427 | } |
2428 | ||
f684960e CW |
2429 | intel_dp_add_properties(intel_dp, connector); |
2430 | ||
a4fc5ed6 KP |
2431 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2432 | * 0xd. Failure to do so will result in spurious interrupts being | |
2433 | * generated on the port when a cable is not attached. | |
2434 | */ | |
2435 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2436 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2437 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2438 | } | |
2439 | } |