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drm/i915: make backlight functions take a connector
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
a4fc5ed6
KP		 145static int
146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
b84a1cf8
RV		 407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
408
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
411 * deep sleep states.
412 */
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
414
415 intel_dp_check_edp(intel_dp);
5eb08b69 416
6b4e0a93
DV		 417 if (IS_GEN6(dev))
418 precharge = 3;
419 else
420 precharge = 5;
421
c67a470b
PZ		 422 intel_aux_display_runtime_get(dev_priv);
423
11bee43e
JB		 424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
ef04f00d 426 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
428 break;
429 msleep(1);
430 }
431
432 if (try == 3) {
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
434 I915_READ(ch_ctl));
9ee32fea
DV		 435 ret = -EBUSY;
436 goto out;
4f7f7b7e
CW		 437 }
438
46a5ae9f
PZ		 439 /* Only 5 data registers! */
440 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
441 ret = -E2BIG;
442 goto out;
443 }
444
bc86625a
CW		 445 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
446 /* Must try at least 3 times according to DP spec */
447 for (try = 0; try < 5; try++) {
448 /* Load the send data into the aux channel data registers */
449 for (i = 0; i < send_bytes; i += 4)
450 I915_WRITE(ch_data + i,
451 pack_aux(send + i, send_bytes - i));
452
453 /* Send the command and wait for it to complete */
454 I915_WRITE(ch_ctl,
455 DP_AUX_CH_CTL_SEND_BUSY |
456 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
457 DP_AUX_CH_CTL_TIME_OUT_400us |
458 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
459 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
460 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
461 DP_AUX_CH_CTL_DONE |
462 DP_AUX_CH_CTL_TIME_OUT_ERROR |
463 DP_AUX_CH_CTL_RECEIVE_ERROR);
464
465 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
466
467 /* Clear done status and any errors */
468 I915_WRITE(ch_ctl,
469 status |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
473
474 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
475 DP_AUX_CH_CTL_RECEIVE_ERROR))
476 continue;
477 if (status & DP_AUX_CH_CTL_DONE)
478 break;
479 }
4f7f7b7e 480 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 481 break;
482 }
483
a4fc5ed6 484 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 485 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 486 ret = -EBUSY;
487 goto out;
a4fc5ed6
KP		 488 }
489
490 /* Check for timeout or receive error.
491 * Timeouts occur when the sink is not connected
492 */
a5b3da54 493 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 494 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 495 ret = -EIO;
496 goto out;
a5b3da54 497 }
1ae8c0a5
KP		 498
499 /* Timeouts occur when the device isn't connected, so they're
500 * "normal" -- don't fill the kernel log with these */
a5b3da54 501 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 502 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 503 ret = -ETIMEDOUT;
504 goto out;
a4fc5ed6
KP		 505 }
506
507 /* Unload any bytes sent back from the other side */
508 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
509 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 510 if (recv_bytes > recv_size)
511 recv_bytes = recv_size;
0206e353 512
4f7f7b7e
CW		 513 for (i = 0; i < recv_bytes; i += 4)
514 unpack_aux(I915_READ(ch_data + i),
515 recv + i, recv_bytes - i);
a4fc5ed6 516
9ee32fea
DV		 517 ret = recv_bytes;
518out:
519 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 520 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 521
522 return ret;
a4fc5ed6
KP		 523}
524
525/* Write data to the aux channel in native mode */
526static int
ea5b213a 527intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 528 uint16_t address, uint8_t *send, int send_bytes)
529{
530 int ret;
531 uint8_t msg[20];
532 int msg_bytes;
533 uint8_t ack;
534
46a5ae9f
PZ		 535 if (WARN_ON(send_bytes > 16))
536 return -E2BIG;
537
9b984dae 538 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 539 msg[0] = AUX_NATIVE_WRITE << 4;
540 msg[1] = address >> 8;
eebc863e 541 msg[2] = address & 0xff;
a4fc5ed6
KP		 542 msg[3] = send_bytes - 1;
543 memcpy(&msg[4], send, send_bytes);
544 msg_bytes = send_bytes + 4;
545 for (;;) {
ea5b213a 546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 547 if (ret < 0)
548 return ret;
549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
550 break;
551 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
552 udelay(100);
553 else
a5b3da54 554 return -EIO;
a4fc5ed6
KP		 555 }
556 return send_bytes;
557}
558
559/* Write a single byte to the aux channel in native mode */
560static int
ea5b213a 561intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 562 uint16_t address, uint8_t byte)
563{
ea5b213a 564 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 565}
566
567/* read bytes from a native aux channel */
568static int
ea5b213a 569intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 570 uint16_t address, uint8_t *recv, int recv_bytes)
571{
572 uint8_t msg[4];
573 int msg_bytes;
574 uint8_t reply[20];
575 int reply_bytes;
576 uint8_t ack;
577 int ret;
578
46a5ae9f
PZ		 579 if (WARN_ON(recv_bytes > 19))
580 return -E2BIG;
581
9b984dae 582 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 583 msg[0] = AUX_NATIVE_READ << 4;
584 msg[1] = address >> 8;
585 msg[2] = address & 0xff;
586 msg[3] = recv_bytes - 1;
587
588 msg_bytes = 4;
589 reply_bytes = recv_bytes + 1;
590
591 for (;;) {
ea5b213a 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 593 reply, reply_bytes);
a5b3da54
KP		 594 if (ret == 0)
595 return -EPROTO;
596 if (ret < 0)
a4fc5ed6
KP		 597 return ret;
598 ack = reply[0];
599 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
600 memcpy(recv, reply + 1, ret - 1);
601 return ret - 1;
602 }
603 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
604 udelay(100);
605 else
a5b3da54 606 return -EIO;
a4fc5ed6
KP		 607 }
608}
609
610static int
ab2c0672
DA		 611intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
612 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 613{
ab2c0672 614 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 615 struct intel_dp *intel_dp = container_of(adapter,
616 struct intel_dp,
617 adapter);
ab2c0672
DA		 618 uint16_t address = algo_data->address;
619 uint8_t msg[5];
620 uint8_t reply[2];
8316f337 621 unsigned retry;
ab2c0672
DA		 622 int msg_bytes;
623 int reply_bytes;
624 int ret;
625
8a5e6aeb 626 ironlake_edp_panel_vdd_on(intel_dp);
9b984dae 627 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
631 else
632 msg[0] = AUX_I2C_WRITE << 4;
633
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 636
ab2c0672
DA		 637 msg[1] = address >> 8;
638 msg[2] = address;
639
640 switch (mode) {
641 case MODE_I2C_WRITE:
642 msg[3] = 0;
643 msg[4] = write_byte;
644 msg_bytes = 5;
645 reply_bytes = 1;
646 break;
647 case MODE_I2C_READ:
648 msg[3] = 0;
649 msg_bytes = 4;
650 reply_bytes = 2;
651 break;
652 default:
653 msg_bytes = 3;
654 reply_bytes = 1;
655 break;
656 }
657
58c67ce9
JN		 658 /*
659 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
660 * required to retry at least seven times upon receiving AUX_DEFER
661 * before giving up the AUX transaction.
662 */
663 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 664 ret = intel_dp_aux_ch(intel_dp,
665 msg, msg_bytes,
666 reply, reply_bytes);
ab2c0672 667 if (ret < 0) {
3ff99164 668 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 669 goto out;
ab2c0672 670 }
8316f337
DF		 671
672 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
673 case AUX_NATIVE_REPLY_ACK:
674 /* I2C-over-AUX Reply field is only valid
675 * when paired with AUX ACK.
676 */
677 break;
678 case AUX_NATIVE_REPLY_NACK:
679 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 680 ret = -EREMOTEIO;
681 goto out;
8316f337 682 case AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 683 /*
684 * For now, just give more slack to branch devices. We
685 * could check the DPCD for I2C bit rate capabilities,
686 * and if available, adjust the interval. We could also
687 * be more careful with DP-to-Legacy adapters where a
688 * long legacy cable may force very low I2C bit rates.
689 */
690 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
691 DP_DWN_STRM_PORT_PRESENT)
692 usleep_range(500, 600);
693 else
694 usleep_range(300, 400);
8316f337
DF		 695 continue;
696 default:
697 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
698 reply[0]);
8a5e6aeb
PZ		 699 ret = -EREMOTEIO;
700 goto out;
8316f337
DF		 701 }
702
ab2c0672
DA		 703 switch (reply[0] & AUX_I2C_REPLY_MASK) {
704 case AUX_I2C_REPLY_ACK:
705 if (mode == MODE_I2C_READ) {
706 *read_byte = reply[1];
707 }
8a5e6aeb
PZ		 708 ret = reply_bytes - 1;
709 goto out;
ab2c0672 710 case AUX_I2C_REPLY_NACK:
8316f337 711 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 712 ret = -EREMOTEIO;
713 goto out;
ab2c0672 714 case AUX_I2C_REPLY_DEFER:
8316f337 715 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 716 udelay(100);
717 break;
718 default:
8316f337 719 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 720 ret = -EREMOTEIO;
721 goto out;
ab2c0672
DA		 722 }
723 }
8316f337
DF		 724
725 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 726 ret = -EREMOTEIO;
727
728out:
729 ironlake_edp_panel_vdd_off(intel_dp, false);
730 return ret;
a4fc5ed6
KP		 731}
732
733static int
ea5b213a 734intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 735 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 736{
0b5c541b
KP		 737 int ret;
738
d54e9d28 739 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 740 intel_dp->algo.running = false;
741 intel_dp->algo.address = 0;
742 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
743
0206e353 744 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 745 intel_dp->adapter.owner = THIS_MODULE;
746 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 747 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 748 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
749 intel_dp->adapter.algo_data = &intel_dp->algo;
750 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
751
0b5c541b 752 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
0b5c541b 753 return ret;
a4fc5ed6
KP		 754}
755
c6bb3538
DV		 756static void
757intel_dp_set_clock(struct intel_encoder *encoder,
758 struct intel_crtc_config *pipe_config, int link_bw)
759{
760 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 761 const struct dp_link_dpll *divisor = NULL;
762 int i, count = 0;
c6bb3538
DV		 763
764 if (IS_G4X(dev)) {
9dd4ffdf
CML		 765 divisor = gen4_dpll;
766 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 767 } else if (IS_HASWELL(dev)) {
768 /* Haswell has special-purpose DP DDI clocks. */
769 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 770 divisor = pch_dpll;
771 count = ARRAY_SIZE(pch_dpll);
c6bb3538 772 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 773 divisor = vlv_dpll;
774 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 775 }
9dd4ffdf
CML		 776
777 if (divisor && count) {
778 for (i = 0; i < count; i++) {
779 if (link_bw == divisor[i].link_bw) {
780 pipe_config->dpll = divisor[i].dpll;
781 pipe_config->clock_set = true;
782 break;
783 }
784 }
c6bb3538
DV		 785 }
786}
787
00c09d70 788bool
5bfe2ac0
DV		 789intel_dp_compute_config(struct intel_encoder *encoder,
790 struct intel_crtc_config *pipe_config)
a4fc5ed6 791{
5bfe2ac0 792 struct drm_device *dev = encoder->base.dev;
36008365 793 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 794 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 795 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 796 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 797 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 798 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 799 int lane_count, clock;
397fe157 800 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 801 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 802 int bpp, mode_rate;
a4fc5ed6 803 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 804 int link_avail, link_clock;
a4fc5ed6 805
bc7d38a4 806 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 807 pipe_config->has_pch_encoder = true;
808
03afc4a2 809 pipe_config->has_dp_encoder = true;
a4fc5ed6 810
dd06f90e
JN		 811 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
812 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
813 adjusted_mode);
2dd24552
JB		 814 if (!HAS_PCH_SPLIT(dev))
815 intel_gmch_panel_fitting(intel_crtc, pipe_config,
816 intel_connector->panel.fitting_mode);
817 else
b074cec8
JB		 818 intel_pch_panel_fitting(intel_crtc, pipe_config,
819 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 820 }
821
cb1793ce 822 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 823 return false;
824
083f9560
DV		 825 DRM_DEBUG_KMS("DP link computation with max lane count %i "
826 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 827 max_lane_count, bws[max_clock],
828 adjusted_mode->crtc_clock);
083f9560 829
36008365
DV		 830 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
831 * bpc in between. */
3e7ca985 832 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 833 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
834 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 835 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
836 dev_priv->vbt.edp_bpp);
6da7f10d 837 bpp = dev_priv->vbt.edp_bpp;
7984211e 838 }
657445fe 839
36008365 840 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 841 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
842 bpp);
36008365
DV		 843
844 for (clock = 0; clock <= max_clock; clock++) {
845 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
846 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
847 link_avail = intel_dp_max_data_rate(link_clock,
848 lane_count);
849
850 if (mode_rate <= link_avail) {
851 goto found;
852 }
853 }
854 }
855 }
c4867936 856
36008365 857 return false;
3685a8f3 858
36008365 859found:
55bc60db
VS		 860 if (intel_dp->color_range_auto) {
861 /*
862 * See:
863 * CEA-861-E - 5.1 Default Encoding Parameters
864 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
865 */
18316c8c 866 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 867 intel_dp->color_range = DP_COLOR_RANGE_16_235;
868 else
869 intel_dp->color_range = 0;
870 }
871
3685a8f3 872 if (intel_dp->color_range)
50f3b016 873 pipe_config->limited_color_range = true;
a4fc5ed6 874
36008365
DV		 875 intel_dp->link_bw = bws[clock];
876 intel_dp->lane_count = lane_count;
657445fe 877 pipe_config->pipe_bpp = bpp;
ff9a6750 878 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 879
36008365
DV		 880 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
881 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 882 pipe_config->port_clock, bpp);
36008365
DV		 883 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
884 mode_rate, link_avail);
a4fc5ed6 885
03afc4a2 886 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 887 adjusted_mode->crtc_clock,
888 pipe_config->port_clock,
03afc4a2 889 &pipe_config->dp_m_n);
9d1a455b 890
c6bb3538
DV		 891 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
892
03afc4a2 893 return true;
a4fc5ed6
KP		 894}
895
7c62a164 896static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 897{
7c62a164
DV		 898 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
899 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
900 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 901 struct drm_i915_private *dev_priv = dev->dev_private;
902 u32 dpa_ctl;
903
ff9a6750 904 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 905 dpa_ctl = I915_READ(DP_A);
906 dpa_ctl &= ~DP_PLL_FREQ_MASK;
907
ff9a6750 908 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 909 /* For a long time we've carried around a ILK-DevA w/a for the
910 * 160MHz clock. If we're really unlucky, it's still required.
911 */
912 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 913 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 914 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 915 } else {
916 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 917 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 918 }
1ce17038 919
ea9b6006
DV		 920 I915_WRITE(DP_A, dpa_ctl);
921
922 POSTING_READ(DP_A);
923 udelay(500);
924}
925
b934223d 926static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 927{
b934223d 928 struct drm_device *dev = encoder->base.dev;
417e822d 929 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 930 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 931 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 932 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
933 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 934
417e822d 935 /*
1a2eb460 936 * There are four kinds of DP registers:
417e822d
KP		 937 *
938 * IBX PCH
1a2eb460
KP		 939 * SNB CPU
940 * IVB CPU
417e822d
KP		 941 * CPT PCH
942 *
943 * IBX PCH and CPU are the same for almost everything,
944 * except that the CPU DP PLL is configured in this
945 * register
946 *
947 * CPT PCH is quite different, having many bits moved
948 * to the TRANS_DP_CTL register instead. That
949 * configuration happens (oddly) in ironlake_pch_enable
950 */
9c9e7927 951
417e822d
KP		 952 /* Preserve the BIOS-computed detected bit. This is
953 * supposed to be read-only.
954 */
955 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 956
417e822d 957 /* Handle DP bits in common between all three register formats */
417e822d 958 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 959 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 960
e0dac65e
WF		 961 if (intel_dp->has_audio) {
962 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 963 pipe_name(crtc->pipe));
ea5b213a 964 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 965 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 966 }
247d89f6 967
417e822d 968 /* Split out the IBX/CPU vs CPT settings */
32f9d658 969
bc7d38a4 970 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 971 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
972 intel_dp->DP |= DP_SYNC_HS_HIGH;
973 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
974 intel_dp->DP |= DP_SYNC_VS_HIGH;
975 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
976
6aba5b6c 977 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 978 intel_dp->DP |= DP_ENHANCED_FRAMING;
979
7c62a164 980 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 981 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 982 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 983 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 984
985 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
986 intel_dp->DP |= DP_SYNC_HS_HIGH;
987 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
988 intel_dp->DP |= DP_SYNC_VS_HIGH;
989 intel_dp->DP |= DP_LINK_TRAIN_OFF;
990
6aba5b6c 991 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 992 intel_dp->DP |= DP_ENHANCED_FRAMING;
993
7c62a164 994 if (crtc->pipe == 1)
417e822d 995 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 996 } else {
997 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 998 }
ea9b6006 999
bc7d38a4 1000 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1001 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1002}
1003
99ea7127
KP		 1004#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1005#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1006
1007#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1009
1010#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1011#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1012
1013static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1014 u32 mask,
1015 u32 value)
bd943159 1016{
30add22d 1017 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1018 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1019 u32 pp_stat_reg, pp_ctrl_reg;
1020
bf13e81b
JN		 1021 pp_stat_reg = _pp_stat_reg(intel_dp);
1022 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1023
99ea7127 1024 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1025 mask, value,
1026 I915_READ(pp_stat_reg),
1027 I915_READ(pp_ctrl_reg));
32ce697c 1028
453c5420 1029 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1030 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1031 I915_READ(pp_stat_reg),
1032 I915_READ(pp_ctrl_reg));
32ce697c 1033 }
99ea7127 1034}
32ce697c 1035
99ea7127
KP		 1036static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1037{
1038 DRM_DEBUG_KMS("Wait for panel power on\n");
1039 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1040}
1041
99ea7127
KP		 1042static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1043{
1044 DRM_DEBUG_KMS("Wait for panel power off time\n");
1045 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1046}
1047
1048static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1049{
1050 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1051 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1052}
1053
1054
832dd3c1
KP		 1055/* Read the current pp_control value, unlocking the register if it
1056 * is locked
1057 */
1058
453c5420 1059static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1060{
453c5420
JB		 1061 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063 u32 control;
832dd3c1 1064
bf13e81b 1065 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1066 control &= ~PANEL_UNLOCK_MASK;
1067 control |= PANEL_UNLOCK_REGS;
1068 return control;
bd943159
KP		 1069}
1070
82a4d9c0 1071void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1072{
30add22d 1073 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1074 struct drm_i915_private *dev_priv = dev->dev_private;
1075 u32 pp;
453c5420 1076 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1077
97af61f5
KP		 1078 if (!is_edp(intel_dp))
1079 return;
5d613501 1080
bd943159
KP		 1081 WARN(intel_dp->want_panel_vdd,
1082 "eDP VDD already requested on\n");
1083
1084 intel_dp->want_panel_vdd = true;
99ea7127 1085
b0665d57 1086 if (ironlake_edp_have_panel_vdd(intel_dp))
bd943159 1087 return;
b0665d57
PZ		 1088
1089 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1090
99ea7127
KP		 1091 if (!ironlake_edp_have_panel_power(intel_dp))
1092 ironlake_wait_panel_power_cycle(intel_dp);
1093
453c5420 1094 pp = ironlake_get_pp_control(intel_dp);
5d613501 1095 pp |= EDP_FORCE_VDD;
ebf33b18 1096
bf13e81b
JN		 1097 pp_stat_reg = _pp_stat_reg(intel_dp);
1098 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1099
1100 I915_WRITE(pp_ctrl_reg, pp);
1101 POSTING_READ(pp_ctrl_reg);
1102 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1103 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1104 /*
1105 * If the panel wasn't on, delay before accessing aux channel
1106 */
1107 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1108 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1109 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1110 }
5d613501
JB		 1111}
1112
bd943159 1113static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1114{
30add22d 1115 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1116 struct drm_i915_private *dev_priv = dev->dev_private;
1117 u32 pp;
453c5420 1118 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1119
a0e99e68
DV		 1120 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1121
bd943159 1122 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1123 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1124
453c5420 1125 pp = ironlake_get_pp_control(intel_dp);
bd943159 1126 pp &= ~EDP_FORCE_VDD;
bd943159 1127
9f08ef59
PZ		 1128 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1129 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1130
1131 I915_WRITE(pp_ctrl_reg, pp);
1132 POSTING_READ(pp_ctrl_reg);
99ea7127 1133
453c5420
JB		 1134 /* Make sure sequencer is idle before allowing subsequent activity */
1135 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1136 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1137 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1138 }
1139}
5d613501 1140
bd943159
KP		 1141static void ironlake_panel_vdd_work(struct work_struct *__work)
1142{
1143 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1144 struct intel_dp, panel_vdd_work);
30add22d 1145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1146
627f7675 1147 mutex_lock(&dev->mode_config.mutex);
bd943159 1148 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1149 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1150}
1151
82a4d9c0 1152void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1153{
97af61f5
KP		 1154 if (!is_edp(intel_dp))
1155 return;
5d613501 1156
bd943159 1157 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1158
bd943159
KP		 1159 intel_dp->want_panel_vdd = false;
1160
1161 if (sync) {
1162 ironlake_panel_vdd_off_sync(intel_dp);
1163 } else {
1164 /*
1165 * Queue the timer to fire a long
1166 * time from now (relative to the power down delay)
1167 * to keep the panel power up across a sequence of operations
1168 */
1169 schedule_delayed_work(&intel_dp->panel_vdd_work,
1170 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1171 }
5d613501
JB		 1172}
1173
82a4d9c0 1174void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1175{
30add22d 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1177 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1178 u32 pp;
453c5420 1179 u32 pp_ctrl_reg;
9934c132 1180
97af61f5 1181 if (!is_edp(intel_dp))
bd943159 1182 return;
99ea7127
KP		 1183
1184 DRM_DEBUG_KMS("Turn eDP power on\n");
1185
1186 if (ironlake_edp_have_panel_power(intel_dp)) {
1187 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1188 return;
99ea7127 1189 }
9934c132 1190
99ea7127 1191 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1192
bf13e81b 1193 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1194 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1195 if (IS_GEN5(dev)) {
1196 /* ILK workaround: disable reset around power sequence */
1197 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1198 I915_WRITE(pp_ctrl_reg, pp);
1199 POSTING_READ(pp_ctrl_reg);
05ce1a49 1200 }
37c6c9b0 1201
1c0ae80a 1202 pp |= POWER_TARGET_ON;
99ea7127
KP		 1203 if (!IS_GEN5(dev))
1204 pp |= PANEL_POWER_RESET;
1205
453c5420
JB		 1206 I915_WRITE(pp_ctrl_reg, pp);
1207 POSTING_READ(pp_ctrl_reg);
9934c132 1208
99ea7127 1209 ironlake_wait_panel_on(intel_dp);
9934c132 1210
05ce1a49
KP		 1211 if (IS_GEN5(dev)) {
1212 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1213 I915_WRITE(pp_ctrl_reg, pp);
1214 POSTING_READ(pp_ctrl_reg);
05ce1a49 1215 }
9934c132
JB		 1216}
1217
82a4d9c0 1218void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1219{
30add22d 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1221 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1222 u32 pp;
453c5420 1223 u32 pp_ctrl_reg;
9934c132 1224
97af61f5
KP		 1225 if (!is_edp(intel_dp))
1226 return;
37c6c9b0 1227
99ea7127 1228 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1229
6cb49835 1230 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1231
453c5420 1232 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1233 /* We need to switch off panel power _and_ force vdd, for otherwise some
1234 * panels get very unhappy and cease to work. */
1235 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1236
bf13e81b 1237 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1238
1239 I915_WRITE(pp_ctrl_reg, pp);
1240 POSTING_READ(pp_ctrl_reg);
9934c132 1241
35a38556
DV		 1242 intel_dp->want_panel_vdd = false;
1243
99ea7127 1244 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1245}
1246
d6c50ff8 1247void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1248{
da63a9f2
PZ		 1249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1250 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1251 struct drm_i915_private *dev_priv = dev->dev_private;
1252 u32 pp;
453c5420 1253 u32 pp_ctrl_reg;
32f9d658 1254
f01eca2e
KP		 1255 if (!is_edp(intel_dp))
1256 return;
1257
28c97730 1258 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1259 /*
1260 * If we enable the backlight right away following a panel power
1261 * on, we may see slight flicker as the panel syncs with the eDP
1262 * link. So delay a bit to make sure the image is solid before
1263 * allowing it to appear.
1264 */
f01eca2e 1265 msleep(intel_dp->backlight_on_delay);
453c5420 1266 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1267 pp |= EDP_BLC_ENABLE;
453c5420 1268
bf13e81b 1269 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1270
1271 I915_WRITE(pp_ctrl_reg, pp);
1272 POSTING_READ(pp_ctrl_reg);
035aa3de 1273
752aa88a 1274 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1275}
1276
d6c50ff8 1277void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1278{
30add22d 1279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281 u32 pp;
453c5420 1282 u32 pp_ctrl_reg;
32f9d658 1283
f01eca2e
KP		 1284 if (!is_edp(intel_dp))
1285 return;
1286
752aa88a 1287 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1288
28c97730 1289 DRM_DEBUG_KMS("\n");
453c5420 1290 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1291 pp &= ~EDP_BLC_ENABLE;
453c5420 1292
bf13e81b 1293 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1294
1295 I915_WRITE(pp_ctrl_reg, pp);
1296 POSTING_READ(pp_ctrl_reg);
f01eca2e 1297 msleep(intel_dp->backlight_off_delay);
32f9d658 1298}
a4fc5ed6 1299
2bd2ad64 1300static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1301{
da63a9f2
PZ		 1302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1303 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1304 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1305 struct drm_i915_private *dev_priv = dev->dev_private;
1306 u32 dpa_ctl;
1307
2bd2ad64
DV		 1308 assert_pipe_disabled(dev_priv,
1309 to_intel_crtc(crtc)->pipe);
1310
d240f20f
JB		 1311 DRM_DEBUG_KMS("\n");
1312 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1313 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1314 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1315
1316 /* We don't adjust intel_dp->DP while tearing down the link, to
1317 * facilitate link retraining (e.g. after hotplug). Hence clear all
1318 * enable bits here to ensure that we don't enable too much. */
1319 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1320 intel_dp->DP |= DP_PLL_ENABLE;
1321 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1322 POSTING_READ(DP_A);
1323 udelay(200);
d240f20f
JB		 1324}
1325
2bd2ad64 1326static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1327{
da63a9f2
PZ		 1328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1329 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1330 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1331 struct drm_i915_private *dev_priv = dev->dev_private;
1332 u32 dpa_ctl;
1333
2bd2ad64
DV		 1334 assert_pipe_disabled(dev_priv,
1335 to_intel_crtc(crtc)->pipe);
1336
d240f20f 1337 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1338 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1339 "dp pll off, should be on\n");
1340 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1341
1342 /* We can't rely on the value tracked for the DP register in
1343 * intel_dp->DP because link_down must not change that (otherwise link
1344 * re-training will fail. */
298b0b39 1345 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1346 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1347 POSTING_READ(DP_A);
d240f20f
JB		 1348 udelay(200);
1349}
1350
c7ad3810 1351/* If the sink supports it, try to set the power state appropriately */
c19b0669 1352void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1353{
1354 int ret, i;
1355
1356 /* Should have a valid DPCD by this point */
1357 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1358 return;
1359
1360 if (mode != DRM_MODE_DPMS_ON) {
1361 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1362 DP_SET_POWER_D3);
1363 if (ret != 1)
1364 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1365 } else {
1366 /*
1367 * When turning on, we need to retry for 1ms to give the sink
1368 * time to wake up.
1369 */
1370 for (i = 0; i < 3; i++) {
1371 ret = intel_dp_aux_native_write_1(intel_dp,
1372 DP_SET_POWER,
1373 DP_SET_POWER_D0);
1374 if (ret == 1)
1375 break;
1376 msleep(1);
1377 }
1378 }
1379}
1380
19d8fe15
DV		 1381static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1382 enum pipe *pipe)
d240f20f 1383{
19d8fe15 1384 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1385 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1386 struct drm_device *dev = encoder->base.dev;
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 u32 tmp = I915_READ(intel_dp->output_reg);
1389
1390 if (!(tmp & DP_PORT_EN))
1391 return false;
1392
bc7d38a4 1393 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1394 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1395 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1396 *pipe = PORT_TO_PIPE(tmp);
1397 } else {
1398 u32 trans_sel;
1399 u32 trans_dp;
1400 int i;
1401
1402 switch (intel_dp->output_reg) {
1403 case PCH_DP_B:
1404 trans_sel = TRANS_DP_PORT_SEL_B;
1405 break;
1406 case PCH_DP_C:
1407 trans_sel = TRANS_DP_PORT_SEL_C;
1408 break;
1409 case PCH_DP_D:
1410 trans_sel = TRANS_DP_PORT_SEL_D;
1411 break;
1412 default:
1413 return true;
1414 }
1415
1416 for_each_pipe(i) {
1417 trans_dp = I915_READ(TRANS_DP_CTL(i));
1418 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1419 *pipe = i;
1420 return true;
1421 }
1422 }
19d8fe15 1423
4a0833ec
DV		 1424 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1425 intel_dp->output_reg);
1426 }
d240f20f 1427
19d8fe15
DV		 1428 return true;
1429}
d240f20f 1430
045ac3b5
JB		 1431static void intel_dp_get_config(struct intel_encoder *encoder,
1432 struct intel_crtc_config *pipe_config)
1433{
1434 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1435 u32 tmp, flags = 0;
63000ef6
XZ		 1436 struct drm_device *dev = encoder->base.dev;
1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438 enum port port = dp_to_dig_port(intel_dp)->port;
1439 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1440 int dotclock;
045ac3b5 1441
63000ef6
XZ		 1442 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1443 tmp = I915_READ(intel_dp->output_reg);
1444 if (tmp & DP_SYNC_HS_HIGH)
1445 flags |= DRM_MODE_FLAG_PHSYNC;
1446 else
1447 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1448
63000ef6
XZ		 1449 if (tmp & DP_SYNC_VS_HIGH)
1450 flags |= DRM_MODE_FLAG_PVSYNC;
1451 else
1452 flags |= DRM_MODE_FLAG_NVSYNC;
1453 } else {
1454 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1455 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1456 flags |= DRM_MODE_FLAG_PHSYNC;
1457 else
1458 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1459
63000ef6
XZ		 1460 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1461 flags |= DRM_MODE_FLAG_PVSYNC;
1462 else
1463 flags |= DRM_MODE_FLAG_NVSYNC;
1464 }
045ac3b5
JB		 1465
1466 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1467
eb14cb74
VS		 1468 pipe_config->has_dp_encoder = true;
1469
1470 intel_dp_get_m_n(crtc, pipe_config);
1471
18442d08 1472 if (port == PORT_A) {
f1f644dc
JB		 1473 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1474 pipe_config->port_clock = 162000;
1475 else
1476 pipe_config->port_clock = 270000;
1477 }
18442d08
VS		 1478
1479 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1480 &pipe_config->dp_m_n);
1481
1482 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1483 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1484
241bfc38 1485 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1486
c6cd2ee2
JN		 1487 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1488 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1489 /*
1490 * This is a big fat ugly hack.
1491 *
1492 * Some machines in UEFI boot mode provide us a VBT that has 18
1493 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1494 * unknown we fail to light up. Yet the same BIOS boots up with
1495 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1496 * max, not what it tells us to use.
1497 *
1498 * Note: This will still be broken if the eDP panel is not lit
1499 * up by the BIOS, and thus we can't get the mode at module
1500 * load.
1501 */
1502 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1503 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1504 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1505 }
045ac3b5
JB		 1506}
1507
a031d709 1508static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1509{
a031d709
RV		 1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
1512 return dev_priv->psr.sink_support;
2293bb5c
SK		 1513}
1514
2b28bb1b
RV		 1515static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1516{
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518
18b5992c 1519 if (!HAS_PSR(dev))
2b28bb1b
RV		 1520 return false;
1521
18b5992c 1522 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1523}
1524
1525static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1526 struct edp_vsc_psr *vsc_psr)
1527{
1528 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1529 struct drm_device *dev = dig_port->base.base.dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1532 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1533 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1534 uint32_t *data = (uint32_t *) vsc_psr;
1535 unsigned int i;
1536
1537 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1538 the video DIP being updated before program video DIP data buffer
1539 registers for DIP being updated. */
1540 I915_WRITE(ctl_reg, 0);
1541 POSTING_READ(ctl_reg);
1542
1543 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1544 if (i < sizeof(struct edp_vsc_psr))
1545 I915_WRITE(data_reg + i, *data++);
1546 else
1547 I915_WRITE(data_reg + i, 0);
1548 }
1549
1550 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1551 POSTING_READ(ctl_reg);
1552}
1553
1554static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1555{
1556 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 struct edp_vsc_psr psr_vsc;
1559
1560 if (intel_dp->psr_setup_done)
1561 return;
1562
1563 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1564 memset(&psr_vsc, 0, sizeof(psr_vsc));
1565 psr_vsc.sdp_header.HB0 = 0;
1566 psr_vsc.sdp_header.HB1 = 0x7;
1567 psr_vsc.sdp_header.HB2 = 0x2;
1568 psr_vsc.sdp_header.HB3 = 0x8;
1569 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1570
1571 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1572 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1573 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1574
1575 intel_dp->psr_setup_done = true;
1576}
1577
1578static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1579{
1580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1581 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1582 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1583 int precharge = 0x3;
1584 int msg_size = 5; /* Header(4) + Message(1) */
1585
1586 /* Enable PSR in sink */
1587 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1588 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1589 DP_PSR_ENABLE &
1590 ~DP_PSR_MAIN_LINK_ACTIVE);
1591 else
1592 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1593 DP_PSR_ENABLE |
1594 DP_PSR_MAIN_LINK_ACTIVE);
1595
1596 /* Setup AUX registers */
18b5992c
BW		 1597 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1598 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1599 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1600 DP_AUX_CH_CTL_TIME_OUT_400us |
1601 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1602 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1603 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1604}
1605
1606static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1607{
1608 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 uint32_t max_sleep_time = 0x1f;
1611 uint32_t idle_frames = 1;
1612 uint32_t val = 0x0;
1613
1614 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1615 val |= EDP_PSR_LINK_STANDBY;
1616 val |= EDP_PSR_TP2_TP3_TIME_0us;
1617 val |= EDP_PSR_TP1_TIME_0us;
1618 val |= EDP_PSR_SKIP_AUX_EXIT;
1619 } else
1620 val |= EDP_PSR_LINK_DISABLE;
1621
18b5992c 1622 I915_WRITE(EDP_PSR_CTL(dev), val |
2b28bb1b
RV		 1623 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1624 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1625 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1626 EDP_PSR_ENABLE);
1627}
1628
3f51e471
RV		 1629static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1630{
1631 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1632 struct drm_device *dev = dig_port->base.base.dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 struct drm_crtc *crtc = dig_port->base.base.crtc;
1635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1636 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1637 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1638
a031d709
RV		 1639 dev_priv->psr.source_ok = false;
1640
18b5992c 1641 if (!HAS_PSR(dev)) {
3f51e471 1642 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1643 return false;
1644 }
1645
1646 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1647 (dig_port->port != PORT_A)) {
1648 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1649 return false;
1650 }
1651
105b7c11
RV		 1652 if (!i915_enable_psr) {
1653 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1654 return false;
1655 }
1656
cd234b0b
CW		 1657 crtc = dig_port->base.base.crtc;
1658 if (crtc == NULL) {
1659 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1660 return false;
1661 }
1662
1663 intel_crtc = to_intel_crtc(crtc);
20ddf665 1664 if (!intel_crtc_active(crtc)) {
3f51e471 1665 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1666 return false;
1667 }
1668
cd234b0b 1669 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1670 if (obj->tiling_mode != I915_TILING_X ||
1671 obj->fence_reg == I915_FENCE_REG_NONE) {
1672 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1673 return false;
1674 }
1675
1676 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1677 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1678 return false;
1679 }
1680
1681 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1682 S3D_ENABLE) {
1683 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1684 return false;
1685 }
1686
ca73b4f0 1687 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1688 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1689 return false;
1690 }
1691
a031d709 1692 dev_priv->psr.source_ok = true;
3f51e471
RV		 1693 return true;
1694}
1695
3d739d92 1696static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1697{
1698 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1699
3f51e471
RV		 1700 if (!intel_edp_psr_match_conditions(intel_dp) ||
1701 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1702 return;
1703
1704 /* Setup PSR once */
1705 intel_edp_psr_setup(intel_dp);
1706
1707 /* Enable PSR on the panel */
1708 intel_edp_psr_enable_sink(intel_dp);
1709
1710 /* Enable PSR on the host */
1711 intel_edp_psr_enable_source(intel_dp);
1712}
1713
3d739d92
RV		 1714void intel_edp_psr_enable(struct intel_dp *intel_dp)
1715{
1716 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1717
1718 if (intel_edp_psr_match_conditions(intel_dp) &&
1719 !intel_edp_is_psr_enabled(dev))
1720 intel_edp_psr_do_enable(intel_dp);
1721}
1722
2b28bb1b
RV		 1723void intel_edp_psr_disable(struct intel_dp *intel_dp)
1724{
1725 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727
1728 if (!intel_edp_is_psr_enabled(dev))
1729 return;
1730
18b5992c
BW		 1731 I915_WRITE(EDP_PSR_CTL(dev),
1732 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1733
1734 /* Wait till PSR is idle */
18b5992c 1735 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1736 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1737 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1738}
1739
3d739d92
RV		 1740void intel_edp_psr_update(struct drm_device *dev)
1741{
1742 struct intel_encoder *encoder;
1743 struct intel_dp *intel_dp = NULL;
1744
1745 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1746 if (encoder->type == INTEL_OUTPUT_EDP) {
1747 intel_dp = enc_to_intel_dp(&encoder->base);
1748
a031d709 1749 if (!is_edp_psr(dev))
3d739d92
RV		 1750 return;
1751
1752 if (!intel_edp_psr_match_conditions(intel_dp))
1753 intel_edp_psr_disable(intel_dp);
1754 else
1755 if (!intel_edp_is_psr_enabled(dev))
1756 intel_edp_psr_do_enable(intel_dp);
1757 }
1758}
1759
e8cb4558 1760static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1761{
e8cb4558 1762 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1763 enum port port = dp_to_dig_port(intel_dp)->port;
1764 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1765
1766 /* Make sure the panel is off before trying to change the mode. But also
1767 * ensure that we have vdd while we switch off the panel. */
1768 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1769 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1770 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1771 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1772
1773 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1774 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1775 intel_dp_link_down(intel_dp);
d240f20f
JB		 1776}
1777
2bd2ad64 1778static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1779{
2bd2ad64 1780 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1781 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1782 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1783
982a3866 1784 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1785 intel_dp_link_down(intel_dp);
b2634017
JB		 1786 if (!IS_VALLEYVIEW(dev))
1787 ironlake_edp_pll_off(intel_dp);
3739850b 1788 }
2bd2ad64
DV		 1789}
1790
e8cb4558 1791static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1792{
e8cb4558
DV		 1793 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1794 struct drm_device *dev = encoder->base.dev;
1795 struct drm_i915_private *dev_priv = dev->dev_private;
1796 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1797
0c33d8d7
DV		 1798 if (WARN_ON(dp_reg & DP_PORT_EN))
1799 return;
5d613501 1800
97af61f5 1801 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1802 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1803 intel_dp_start_link_train(intel_dp);
97af61f5 1804 ironlake_edp_panel_on(intel_dp);
bd943159 1805 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1806 intel_dp_complete_link_train(intel_dp);
3ab9c637 1807 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1808}
89b667f8 1809
ecff4f3b
JN		 1810static void g4x_enable_dp(struct intel_encoder *encoder)
1811{
828f5c6e
JN		 1812 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1813
ecff4f3b 1814 intel_enable_dp(encoder);
f01eca2e 1815 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1816}
89b667f8 1817
ab1f90f9
JN		 1818static void vlv_enable_dp(struct intel_encoder *encoder)
1819{
828f5c6e
JN		 1820 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1821
1822 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1823}
1824
ecff4f3b 1825static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1826{
1827 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1828 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1829
1830 if (dport->port == PORT_A)
1831 ironlake_edp_pll_on(intel_dp);
1832}
1833
1834static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1835{
2bd2ad64 1836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1837 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1838 struct drm_device *dev = encoder->base.dev;
89b667f8 1839 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1840 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1841 int port = vlv_dport_to_channel(dport);
1842 int pipe = intel_crtc->pipe;
bf13e81b 1843 struct edp_power_seq power_seq;
ab1f90f9 1844 u32 val;
a4fc5ed6 1845
ab1f90f9 1846 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1847
5e69f97f 1848 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
ab1f90f9
JN		 1849 val = 0;
1850 if (pipe)
1851 val |= (1<<21);
1852 else
1853 val &= ~(1<<21);
1854 val |= 0x001000c4;
5e69f97f
CML		 1855 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1856 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1857 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1858
ab1f90f9
JN		 1859 mutex_unlock(&dev_priv->dpio_lock);
1860
bf13e81b
JN		 1861 /* init power sequencer on this pipe and port */
1862 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1863 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1864 &power_seq);
1865
ab1f90f9
JN		 1866 intel_enable_dp(encoder);
1867
1868 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1869}
1870
ecff4f3b 1871static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1872{
1873 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1874 struct drm_device *dev = encoder->base.dev;
1875 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1876 struct intel_crtc *intel_crtc =
1877 to_intel_crtc(encoder->base.crtc);
89b667f8 1878 int port = vlv_dport_to_channel(dport);
5e69f97f 1879 int pipe = intel_crtc->pipe;
89b667f8 1880
89b667f8 1881 /* Program Tx lane resets to default */
0980a60f 1882 mutex_lock(&dev_priv->dpio_lock);
5e69f97f 1883 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
89b667f8
JB		 1884 DPIO_PCS_TX_LANE2_RESET |
1885 DPIO_PCS_TX_LANE1_RESET);
5e69f97f 1886 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
89b667f8
JB		 1887 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1888 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1889 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1890 DPIO_PCS_CLK_SOFT_RESET);
1891
1892 /* Fix up inter-pair skew failure */
5e69f97f
CML		 1893 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1894 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1895 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1896 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1897}
1898
1899/*
df0c237d
JB		 1900 * Native read with retry for link status and receiver capability reads for
1901 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1902 */
1903static bool
df0c237d
JB		 1904intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1905 uint8_t *recv, int recv_bytes)
a4fc5ed6 1906{
61da5fab
JB		 1907 int ret, i;
1908
df0c237d
JB		 1909 /*
1910 * Sinks are *supposed* to come up within 1ms from an off state,
1911 * but we're also supposed to retry 3 times per the spec.
1912 */
61da5fab 1913 for (i = 0; i < 3; i++) {
df0c237d
JB		 1914 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1915 recv_bytes);
1916 if (ret == recv_bytes)
61da5fab
JB		 1917 return true;
1918 msleep(1);
1919 }
a4fc5ed6 1920
61da5fab 1921 return false;
a4fc5ed6
KP		 1922}
1923
1924/*
1925 * Fetch AUX CH registers 0x202 - 0x207 which contain
1926 * link status information
1927 */
1928static bool
93f62dad 1929intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1930{
df0c237d
JB		 1931 return intel_dp_aux_native_read_retry(intel_dp,
1932 DP_LANE0_1_STATUS,
93f62dad 1933 link_status,
df0c237d 1934 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1935}
1936
a4fc5ed6
KP		 1937#if 0
1938static char *voltage_names[] = {
1939 "0.4V", "0.6V", "0.8V", "1.2V"
1940};
1941static char *pre_emph_names[] = {
1942 "0dB", "3.5dB", "6dB", "9.5dB"
1943};
1944static char *link_train_names[] = {
1945 "pattern 1", "pattern 2", "idle", "off"
1946};
1947#endif
1948
1949/*
1950 * These are source-specific values; current Intel hardware supports
1951 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1952 */
a4fc5ed6
KP		 1953
1954static uint8_t
1a2eb460 1955intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1956{
30add22d 1957 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1958 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1959
e2fa6fba
P		 1960 if (IS_VALLEYVIEW(dev))
1961 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1962 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1963 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1964 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1965 return DP_TRAIN_VOLTAGE_SWING_1200;
1966 else
1967 return DP_TRAIN_VOLTAGE_SWING_800;
1968}
1969
1970static uint8_t
1971intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1972{
30add22d 1973 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1974 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1975
22b8bf17 1976 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1977 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1978 case DP_TRAIN_VOLTAGE_SWING_400:
1979 return DP_TRAIN_PRE_EMPHASIS_9_5;
1980 case DP_TRAIN_VOLTAGE_SWING_600:
1981 return DP_TRAIN_PRE_EMPHASIS_6;
1982 case DP_TRAIN_VOLTAGE_SWING_800:
1983 return DP_TRAIN_PRE_EMPHASIS_3_5;
1984 case DP_TRAIN_VOLTAGE_SWING_1200:
1985 default:
1986 return DP_TRAIN_PRE_EMPHASIS_0;
1987 }
e2fa6fba
P		 1988 } else if (IS_VALLEYVIEW(dev)) {
1989 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1990 case DP_TRAIN_VOLTAGE_SWING_400:
1991 return DP_TRAIN_PRE_EMPHASIS_9_5;
1992 case DP_TRAIN_VOLTAGE_SWING_600:
1993 return DP_TRAIN_PRE_EMPHASIS_6;
1994 case DP_TRAIN_VOLTAGE_SWING_800:
1995 return DP_TRAIN_PRE_EMPHASIS_3_5;
1996 case DP_TRAIN_VOLTAGE_SWING_1200:
1997 default:
1998 return DP_TRAIN_PRE_EMPHASIS_0;
1999 }
bc7d38a4 2000 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2001 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2002 case DP_TRAIN_VOLTAGE_SWING_400:
2003 return DP_TRAIN_PRE_EMPHASIS_6;
2004 case DP_TRAIN_VOLTAGE_SWING_600:
2005 case DP_TRAIN_VOLTAGE_SWING_800:
2006 return DP_TRAIN_PRE_EMPHASIS_3_5;
2007 default:
2008 return DP_TRAIN_PRE_EMPHASIS_0;
2009 }
2010 } else {
2011 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2012 case DP_TRAIN_VOLTAGE_SWING_400:
2013 return DP_TRAIN_PRE_EMPHASIS_6;
2014 case DP_TRAIN_VOLTAGE_SWING_600:
2015 return DP_TRAIN_PRE_EMPHASIS_6;
2016 case DP_TRAIN_VOLTAGE_SWING_800:
2017 return DP_TRAIN_PRE_EMPHASIS_3_5;
2018 case DP_TRAIN_VOLTAGE_SWING_1200:
2019 default:
2020 return DP_TRAIN_PRE_EMPHASIS_0;
2021 }
a4fc5ed6
KP		 2022 }
2023}
2024
e2fa6fba
P		 2025static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2026{
2027 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2030 struct intel_crtc *intel_crtc =
2031 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2032 unsigned long demph_reg_value, preemph_reg_value,
2033 uniqtranscale_reg_value;
2034 uint8_t train_set = intel_dp->train_set[0];
cece5d58 2035 int port = vlv_dport_to_channel(dport);
5e69f97f 2036 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2037
2038 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2039 case DP_TRAIN_PRE_EMPHASIS_0:
2040 preemph_reg_value = 0x0004000;
2041 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2042 case DP_TRAIN_VOLTAGE_SWING_400:
2043 demph_reg_value = 0x2B405555;
2044 uniqtranscale_reg_value = 0x552AB83A;
2045 break;
2046 case DP_TRAIN_VOLTAGE_SWING_600:
2047 demph_reg_value = 0x2B404040;
2048 uniqtranscale_reg_value = 0x5548B83A;
2049 break;
2050 case DP_TRAIN_VOLTAGE_SWING_800:
2051 demph_reg_value = 0x2B245555;
2052 uniqtranscale_reg_value = 0x5560B83A;
2053 break;
2054 case DP_TRAIN_VOLTAGE_SWING_1200:
2055 demph_reg_value = 0x2B405555;
2056 uniqtranscale_reg_value = 0x5598DA3A;
2057 break;
2058 default:
2059 return 0;
2060 }
2061 break;
2062 case DP_TRAIN_PRE_EMPHASIS_3_5:
2063 preemph_reg_value = 0x0002000;
2064 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2065 case DP_TRAIN_VOLTAGE_SWING_400:
2066 demph_reg_value = 0x2B404040;
2067 uniqtranscale_reg_value = 0x5552B83A;
2068 break;
2069 case DP_TRAIN_VOLTAGE_SWING_600:
2070 demph_reg_value = 0x2B404848;
2071 uniqtranscale_reg_value = 0x5580B83A;
2072 break;
2073 case DP_TRAIN_VOLTAGE_SWING_800:
2074 demph_reg_value = 0x2B404040;
2075 uniqtranscale_reg_value = 0x55ADDA3A;
2076 break;
2077 default:
2078 return 0;
2079 }
2080 break;
2081 case DP_TRAIN_PRE_EMPHASIS_6:
2082 preemph_reg_value = 0x0000000;
2083 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2084 case DP_TRAIN_VOLTAGE_SWING_400:
2085 demph_reg_value = 0x2B305555;
2086 uniqtranscale_reg_value = 0x5570B83A;
2087 break;
2088 case DP_TRAIN_VOLTAGE_SWING_600:
2089 demph_reg_value = 0x2B2B4040;
2090 uniqtranscale_reg_value = 0x55ADDA3A;
2091 break;
2092 default:
2093 return 0;
2094 }
2095 break;
2096 case DP_TRAIN_PRE_EMPHASIS_9_5:
2097 preemph_reg_value = 0x0006000;
2098 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2099 case DP_TRAIN_VOLTAGE_SWING_400:
2100 demph_reg_value = 0x1B405555;
2101 uniqtranscale_reg_value = 0x55ADDA3A;
2102 break;
2103 default:
2104 return 0;
2105 }
2106 break;
2107 default:
2108 return 0;
2109 }
2110
0980a60f 2111 mutex_lock(&dev_priv->dpio_lock);
5e69f97f
CML		 2112 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2113 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2114 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2115 uniqtranscale_reg_value);
5e69f97f
CML		 2116 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2117 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2118 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2119 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2120 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2121
2122 return 0;
2123}
2124
a4fc5ed6 2125static void
0301b3ac
JN		 2126intel_get_adjust_train(struct intel_dp *intel_dp,
2127 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2128{
2129 uint8_t v = 0;
2130 uint8_t p = 0;
2131 int lane;
1a2eb460
KP		 2132 uint8_t voltage_max;
2133 uint8_t preemph_max;
a4fc5ed6 2134
33a34e4e 2135 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2136 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2137 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2138
2139 if (this_v > v)
2140 v = this_v;
2141 if (this_p > p)
2142 p = this_p;
2143 }
2144
1a2eb460 2145 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2146 if (v >= voltage_max)
2147 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2148
1a2eb460
KP		 2149 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2150 if (p >= preemph_max)
2151 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2152
2153 for (lane = 0; lane < 4; lane++)
33a34e4e 2154 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2155}
2156
2157static uint32_t
f0a3424e 2158intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2159{
3cf2efb1 2160 uint32_t signal_levels = 0;
a4fc5ed6 2161
3cf2efb1 2162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2163 case DP_TRAIN_VOLTAGE_SWING_400:
2164 default:
2165 signal_levels |= DP_VOLTAGE_0_4;
2166 break;
2167 case DP_TRAIN_VOLTAGE_SWING_600:
2168 signal_levels |= DP_VOLTAGE_0_6;
2169 break;
2170 case DP_TRAIN_VOLTAGE_SWING_800:
2171 signal_levels |= DP_VOLTAGE_0_8;
2172 break;
2173 case DP_TRAIN_VOLTAGE_SWING_1200:
2174 signal_levels |= DP_VOLTAGE_1_2;
2175 break;
2176 }
3cf2efb1 2177 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2178 case DP_TRAIN_PRE_EMPHASIS_0:
2179 default:
2180 signal_levels |= DP_PRE_EMPHASIS_0;
2181 break;
2182 case DP_TRAIN_PRE_EMPHASIS_3_5:
2183 signal_levels |= DP_PRE_EMPHASIS_3_5;
2184 break;
2185 case DP_TRAIN_PRE_EMPHASIS_6:
2186 signal_levels |= DP_PRE_EMPHASIS_6;
2187 break;
2188 case DP_TRAIN_PRE_EMPHASIS_9_5:
2189 signal_levels |= DP_PRE_EMPHASIS_9_5;
2190 break;
2191 }
2192 return signal_levels;
2193}
2194
e3421a18
ZW		 2195/* Gen6's DP voltage swing and pre-emphasis control */
2196static uint32_t
2197intel_gen6_edp_signal_levels(uint8_t train_set)
2198{
3c5a62b5
YL		 2199 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2200 DP_TRAIN_PRE_EMPHASIS_MASK);
2201 switch (signal_levels) {
e3421a18 2202 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2203 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2204 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2205 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2206 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2207 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2208 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2209 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2210 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2211 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2212 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2213 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2214 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2215 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2216 default:
3c5a62b5
YL		 2217 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2218 "0x%x\n", signal_levels);
2219 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2220 }
2221}
2222
1a2eb460
KP		 2223/* Gen7's DP voltage swing and pre-emphasis control */
2224static uint32_t
2225intel_gen7_edp_signal_levels(uint8_t train_set)
2226{
2227 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2228 DP_TRAIN_PRE_EMPHASIS_MASK);
2229 switch (signal_levels) {
2230 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2231 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2232 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2233 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2234 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2235 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2236
2237 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2238 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2239 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2240 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2241
2242 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2243 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2244 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2245 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2246
2247 default:
2248 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2249 "0x%x\n", signal_levels);
2250 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2251 }
2252}
2253
d6c0d722
PZ		 2254/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2255static uint32_t
f0a3424e 2256intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2257{
d6c0d722
PZ		 2258 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2259 DP_TRAIN_PRE_EMPHASIS_MASK);
2260 switch (signal_levels) {
2261 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2262 return DDI_BUF_EMP_400MV_0DB_HSW;
2263 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2264 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2265 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2266 return DDI_BUF_EMP_400MV_6DB_HSW;
2267 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2268 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2269
d6c0d722
PZ		 2270 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2271 return DDI_BUF_EMP_600MV_0DB_HSW;
2272 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2273 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2274 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2275 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2276
d6c0d722
PZ		 2277 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2278 return DDI_BUF_EMP_800MV_0DB_HSW;
2279 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2280 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2281 default:
2282 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2283 "0x%x\n", signal_levels);
2284 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2285 }
a4fc5ed6
KP		 2286}
2287
f0a3424e
PZ		 2288/* Properly updates "DP" with the correct signal levels. */
2289static void
2290intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2291{
2292 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2293 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2294 struct drm_device *dev = intel_dig_port->base.base.dev;
2295 uint32_t signal_levels, mask;
2296 uint8_t train_set = intel_dp->train_set[0];
2297
22b8bf17 2298 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2299 signal_levels = intel_hsw_signal_levels(train_set);
2300 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2301 } else if (IS_VALLEYVIEW(dev)) {
2302 signal_levels = intel_vlv_signal_levels(intel_dp);
2303 mask = 0;
bc7d38a4 2304 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2305 signal_levels = intel_gen7_edp_signal_levels(train_set);
2306 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2307 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2308 signal_levels = intel_gen6_edp_signal_levels(train_set);
2309 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2310 } else {
2311 signal_levels = intel_gen4_signal_levels(train_set);
2312 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2313 }
2314
2315 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2316
2317 *DP = (*DP & ~mask) | signal_levels;
2318}
2319
a4fc5ed6 2320static bool
ea5b213a 2321intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2322 uint32_t *DP,
58e10eb9 2323 uint8_t dp_train_pat)
a4fc5ed6 2324{
174edf1f
PZ		 2325 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2326 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2327 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2328 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2329 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2330 int ret, len;
a4fc5ed6 2331
22b8bf17 2332 if (HAS_DDI(dev)) {
3ab9c637 2333 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2334
2335 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2336 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2337 else
2338 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2339
2340 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2341 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2342 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2343 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2344
2345 break;
2346 case DP_TRAINING_PATTERN_1:
2347 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2348 break;
2349 case DP_TRAINING_PATTERN_2:
2350 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2351 break;
2352 case DP_TRAINING_PATTERN_3:
2353 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2354 break;
2355 }
174edf1f 2356 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2357
bc7d38a4 2358 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2359 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2360
2361 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2362 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2363 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2364 break;
2365 case DP_TRAINING_PATTERN_1:
70aff66c 2366 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2367 break;
2368 case DP_TRAINING_PATTERN_2:
70aff66c 2369 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2370 break;
2371 case DP_TRAINING_PATTERN_3:
2372 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2373 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2374 break;
2375 }
2376
2377 } else {
70aff66c 2378 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2379
2380 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2381 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2382 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2383 break;
2384 case DP_TRAINING_PATTERN_1:
70aff66c 2385 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2386 break;
2387 case DP_TRAINING_PATTERN_2:
70aff66c 2388 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2389 break;
2390 case DP_TRAINING_PATTERN_3:
2391 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2392 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2393 break;
2394 }
2395 }
2396
70aff66c 2397 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2398 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2399
2cdfe6c8
JN		 2400 buf[0] = dp_train_pat;
2401 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2402 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2403 /* don't write DP_TRAINING_LANEx_SET on disable */
2404 len = 1;
2405 } else {
2406 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2407 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2408 len = intel_dp->lane_count + 1;
47ea7542 2409 }
a4fc5ed6 2410
2cdfe6c8
JN		 2411 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2412 buf, len);
2413
2414 return ret == len;
a4fc5ed6
KP		 2415}
2416
70aff66c
JN		 2417static bool
2418intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2419 uint8_t dp_train_pat)
2420{
953d22e8 2421 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2422 intel_dp_set_signal_levels(intel_dp, DP);
2423 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2424}
2425
2426static bool
2427intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2428 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2429{
2430 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2431 struct drm_device *dev = intel_dig_port->base.base.dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 int ret;
2434
2435 intel_get_adjust_train(intel_dp, link_status);
2436 intel_dp_set_signal_levels(intel_dp, DP);
2437
2438 I915_WRITE(intel_dp->output_reg, *DP);
2439 POSTING_READ(intel_dp->output_reg);
2440
2441 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2442 intel_dp->train_set,
2443 intel_dp->lane_count);
2444
2445 return ret == intel_dp->lane_count;
2446}
2447
3ab9c637
ID		 2448static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2449{
2450 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2451 struct drm_device *dev = intel_dig_port->base.base.dev;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 enum port port = intel_dig_port->port;
2454 uint32_t val;
2455
2456 if (!HAS_DDI(dev))
2457 return;
2458
2459 val = I915_READ(DP_TP_CTL(port));
2460 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2461 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2462 I915_WRITE(DP_TP_CTL(port), val);
2463
2464 /*
2465 * On PORT_A we can have only eDP in SST mode. There the only reason
2466 * we need to set idle transmission mode is to work around a HW issue
2467 * where we enable the pipe while not in idle link-training mode.
2468 * In this case there is requirement to wait for a minimum number of
2469 * idle patterns to be sent.
2470 */
2471 if (port == PORT_A)
2472 return;
2473
2474 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2475 1))
2476 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2477}
2478
33a34e4e 2479/* Enable corresponding port and start training pattern 1 */
c19b0669 2480void
33a34e4e 2481intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2482{
da63a9f2 2483 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2484 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2485 int i;
2486 uint8_t voltage;
cdb0e95b 2487 int voltage_tries, loop_tries;
ea5b213a 2488 uint32_t DP = intel_dp->DP;
6aba5b6c 2489 uint8_t link_config[2];
a4fc5ed6 2490
affa9354 2491 if (HAS_DDI(dev))
c19b0669
PZ		 2492 intel_ddi_prepare_link_retrain(encoder);
2493
3cf2efb1 2494 /* Write the link configuration data */
6aba5b6c
JN		 2495 link_config[0] = intel_dp->link_bw;
2496 link_config[1] = intel_dp->lane_count;
2497 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2498 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2499 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2500
2501 link_config[0] = 0;
2502 link_config[1] = DP_SET_ANSI_8B10B;
2503 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2504
2505 DP |= DP_PORT_EN;
1a2eb460 2506
70aff66c
JN		 2507 /* clock recovery */
2508 if (!intel_dp_reset_link_train(intel_dp, &DP,
2509 DP_TRAINING_PATTERN_1 |
2510 DP_LINK_SCRAMBLING_DISABLE)) {
2511 DRM_ERROR("failed to enable link training\n");
2512 return;
2513 }
2514
a4fc5ed6 2515 voltage = 0xff;
cdb0e95b
KP		 2516 voltage_tries = 0;
2517 loop_tries = 0;
a4fc5ed6 2518 for (;;) {
70aff66c 2519 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2520
a7c9655f 2521 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2522 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2523 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2524 break;
93f62dad 2525 }
a4fc5ed6 2526
01916270 2527 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2528 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2529 break;
2530 }
2531
2532 /* Check to see if we've tried the max voltage */
2533 for (i = 0; i < intel_dp->lane_count; i++)
2534 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2535 break;
3b4f819d 2536 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2537 ++loop_tries;
2538 if (loop_tries == 5) {
3def84b3 2539 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2540 break;
2541 }
70aff66c
JN		 2542 intel_dp_reset_link_train(intel_dp, &DP,
2543 DP_TRAINING_PATTERN_1 |
2544 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2545 voltage_tries = 0;
2546 continue;
2547 }
a4fc5ed6 2548
3cf2efb1 2549 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2550 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2551 ++voltage_tries;
b06fbda3 2552 if (voltage_tries == 5) {
3def84b3 2553 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2554 break;
2555 }
2556 } else
2557 voltage_tries = 0;
2558 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2559
70aff66c
JN		 2560 /* Update training set as requested by target */
2561 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2562 DRM_ERROR("failed to update link training\n");
2563 break;
2564 }
a4fc5ed6
KP		 2565 }
2566
33a34e4e
JB		 2567 intel_dp->DP = DP;
2568}
2569
c19b0669 2570void
33a34e4e
JB		 2571intel_dp_complete_link_train(struct intel_dp *intel_dp)
2572{
33a34e4e 2573 bool channel_eq = false;
37f80975 2574 int tries, cr_tries;
33a34e4e
JB		 2575 uint32_t DP = intel_dp->DP;
2576
a4fc5ed6 2577 /* channel equalization */
70aff66c
JN		 2578 if (!intel_dp_set_link_train(intel_dp, &DP,
2579 DP_TRAINING_PATTERN_2 |
2580 DP_LINK_SCRAMBLING_DISABLE)) {
2581 DRM_ERROR("failed to start channel equalization\n");
2582 return;
2583 }
2584
a4fc5ed6 2585 tries = 0;
37f80975 2586 cr_tries = 0;
a4fc5ed6
KP		 2587 channel_eq = false;
2588 for (;;) {
70aff66c 2589 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2590
37f80975
JB		 2591 if (cr_tries > 5) {
2592 DRM_ERROR("failed to train DP, aborting\n");
2593 intel_dp_link_down(intel_dp);
2594 break;
2595 }
2596
a7c9655f 2597 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2598 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2599 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2600 break;
70aff66c 2601 }
a4fc5ed6 2602
37f80975 2603 /* Make sure clock is still ok */
01916270 2604 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2605 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2606 intel_dp_set_link_train(intel_dp, &DP,
2607 DP_TRAINING_PATTERN_2 |
2608 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2609 cr_tries++;
2610 continue;
2611 }
2612
1ffdff13 2613 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2614 channel_eq = true;
2615 break;
2616 }
a4fc5ed6 2617
37f80975
JB		 2618 /* Try 5 times, then try clock recovery if that fails */
2619 if (tries > 5) {
2620 intel_dp_link_down(intel_dp);
2621 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2622 intel_dp_set_link_train(intel_dp, &DP,
2623 DP_TRAINING_PATTERN_2 |
2624 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2625 tries = 0;
2626 cr_tries++;
2627 continue;
2628 }
a4fc5ed6 2629
70aff66c
JN		 2630 /* Update training set as requested by target */
2631 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2632 DRM_ERROR("failed to update link training\n");
2633 break;
2634 }
3cf2efb1 2635 ++tries;
869184a6 2636 }
3cf2efb1 2637
3ab9c637
ID		 2638 intel_dp_set_idle_link_train(intel_dp);
2639
2640 intel_dp->DP = DP;
2641
d6c0d722 2642 if (channel_eq)
07f42258 2643 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2644
3ab9c637
ID		 2645}
2646
2647void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2648{
70aff66c 2649 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2650 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2651}
2652
2653static void
ea5b213a 2654intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2655{
da63a9f2 2656 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2657 enum port port = intel_dig_port->port;
da63a9f2 2658 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2659 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2660 struct intel_crtc *intel_crtc =
2661 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2662 uint32_t DP = intel_dp->DP;
a4fc5ed6 2663
c19b0669
PZ		 2664 /*
2665 * DDI code has a strict mode set sequence and we should try to respect
2666 * it, otherwise we might hang the machine in many different ways. So we
2667 * really should be disabling the port only on a complete crtc_disable
2668 * sequence. This function is just called under two conditions on DDI
2669 * code:
2670 * - Link train failed while doing crtc_enable, and on this case we
2671 * really should respect the mode set sequence and wait for a
2672 * crtc_disable.
2673 * - Someone turned the monitor off and intel_dp_check_link_status
2674 * called us. We don't need to disable the whole port on this case, so
2675 * when someone turns the monitor on again,
2676 * intel_ddi_prepare_link_retrain will take care of redoing the link
2677 * train.
2678 */
affa9354 2679 if (HAS_DDI(dev))
c19b0669
PZ		 2680 return;
2681
0c33d8d7 2682 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2683 return;
2684
28c97730 2685 DRM_DEBUG_KMS("\n");
32f9d658 2686
bc7d38a4 2687 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2688 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2689 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2690 } else {
2691 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2692 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2693 }
fe255d00 2694 POSTING_READ(intel_dp->output_reg);
5eb08b69 2695
ab527efc
DV		 2696 /* We don't really know why we're doing this */
2697 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2698
493a7081 2699 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2700 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2701 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2702
5bddd17f
EA		 2703 /* Hardware workaround: leaving our transcoder select
2704 * set to transcoder B while it's off will prevent the
2705 * corresponding HDMI output on transcoder A.
2706 *
2707 * Combine this with another hardware workaround:
2708 * transcoder select bit can only be cleared while the
2709 * port is enabled.
2710 */
2711 DP &= ~DP_PIPEB_SELECT;
2712 I915_WRITE(intel_dp->output_reg, DP);
2713
2714 /* Changes to enable or select take place the vblank
2715 * after being written.
2716 */
ff50afe9
DV		 2717 if (WARN_ON(crtc == NULL)) {
2718 /* We should never try to disable a port without a crtc
2719 * attached. For paranoia keep the code around for a
2720 * bit. */
31acbcc4
CW		 2721 POSTING_READ(intel_dp->output_reg);
2722 msleep(50);
2723 } else
ab527efc 2724 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2725 }
2726
832afda6 2727 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2728 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2729 POSTING_READ(intel_dp->output_reg);
f01eca2e 2730 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2731}
2732
26d61aad
KP		 2733static bool
2734intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2735{
a031d709
RV		 2736 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2737 struct drm_device *dev = dig_port->base.base.dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739
577c7a50
DL		 2740 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2741
92fd8fd1 2742 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2743 sizeof(intel_dp->dpcd)) == 0)
2744 return false; /* aux transfer failed */
92fd8fd1 2745
577c7a50
DL		 2746 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2747 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2748 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2749
edb39244
AJ		 2750 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2751 return false; /* DPCD not present */
2752
2293bb5c
SK		 2753 /* Check if the panel supports PSR */
2754 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2755 if (is_edp(intel_dp)) {
2756 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2757 intel_dp->psr_dpcd,
2758 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2759 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2760 dev_priv->psr.sink_support = true;
50003939 2761 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2762 }
50003939
JN		 2763 }
2764
edb39244
AJ		 2765 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2766 DP_DWN_STRM_PORT_PRESENT))
2767 return true; /* native DP sink */
2768
2769 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2770 return true; /* no per-port downstream info */
2771
2772 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2773 intel_dp->downstream_ports,
2774 DP_MAX_DOWNSTREAM_PORTS) == 0)
2775 return false; /* downstream port status fetch failed */
2776
2777 return true;
92fd8fd1
KP		 2778}
2779
0d198328
AJ		 2780static void
2781intel_dp_probe_oui(struct intel_dp *intel_dp)
2782{
2783 u8 buf[3];
2784
2785 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2786 return;
2787
351cfc34
DV		 2788 ironlake_edp_panel_vdd_on(intel_dp);
2789
0d198328
AJ		 2790 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2791 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2792 buf[0], buf[1], buf[2]);
2793
2794 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2795 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2796 buf[0], buf[1], buf[2]);
351cfc34
DV		 2797
2798 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2799}
2800
a60f0e38
JB		 2801static bool
2802intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2803{
2804 int ret;
2805
2806 ret = intel_dp_aux_native_read_retry(intel_dp,
2807 DP_DEVICE_SERVICE_IRQ_VECTOR,
2808 sink_irq_vector, 1);
2809 if (!ret)
2810 return false;
2811
2812 return true;
2813}
2814
2815static void
2816intel_dp_handle_test_request(struct intel_dp *intel_dp)
2817{
2818 /* NAK by default */
9324cf7f 2819 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2820}
2821
a4fc5ed6
KP		 2822/*
2823 * According to DP spec
2824 * 5.1.2:
2825 * 1. Read DPCD
2826 * 2. Configure link according to Receiver Capabilities
2827 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2828 * 4. Check link status on receipt of hot-plug interrupt
2829 */
2830
00c09d70 2831void
ea5b213a 2832intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2833{
da63a9f2 2834 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2835 u8 sink_irq_vector;
93f62dad 2836 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2837
da63a9f2 2838 if (!intel_encoder->connectors_active)
d2b996ac 2839 return;
59cd09e1 2840
da63a9f2 2841 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2842 return;
2843
92fd8fd1 2844 /* Try to read receiver status if the link appears to be up */
93f62dad 2845 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2846 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2847 return;
2848 }
2849
92fd8fd1 2850 /* Now read the DPCD to see if it's actually running */
26d61aad 2851 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2852 intel_dp_link_down(intel_dp);
2853 return;
2854 }
2855
a60f0e38
JB		 2856 /* Try to read the source of the interrupt */
2857 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2858 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2859 /* Clear interrupt source */
2860 intel_dp_aux_native_write_1(intel_dp,
2861 DP_DEVICE_SERVICE_IRQ_VECTOR,
2862 sink_irq_vector);
2863
2864 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2865 intel_dp_handle_test_request(intel_dp);
2866 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2867 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2868 }
2869
1ffdff13 2870 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2871 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2872 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2873 intel_dp_start_link_train(intel_dp);
2874 intel_dp_complete_link_train(intel_dp);
3ab9c637 2875 intel_dp_stop_link_train(intel_dp);
33a34e4e 2876 }
a4fc5ed6 2877}
a4fc5ed6 2878
caf9ab24 2879/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2880static enum drm_connector_status
26d61aad 2881intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2882{
caf9ab24 2883 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2884 uint8_t type;
2885
2886 if (!intel_dp_get_dpcd(intel_dp))
2887 return connector_status_disconnected;
2888
2889 /* if there's no downstream port, we're done */
2890 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2891 return connector_status_connected;
caf9ab24
AJ		 2892
2893 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2894 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2895 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2896 uint8_t reg;
caf9ab24 2897 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2898 &reg, 1))
caf9ab24 2899 return connector_status_unknown;
23235177
AJ		 2900 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2901 : connector_status_disconnected;
caf9ab24
AJ		 2902 }
2903
2904 /* If no HPD, poke DDC gently */
2905 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2906 return connector_status_connected;
caf9ab24
AJ		 2907
2908 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2909 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2910 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2911 if (type == DP_DS_PORT_TYPE_VGA ||
2912 type == DP_DS_PORT_TYPE_NON_EDID)
2913 return connector_status_unknown;
2914 } else {
2915 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2916 DP_DWN_STRM_PORT_TYPE_MASK;
2917 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2918 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2919 return connector_status_unknown;
2920 }
caf9ab24
AJ		 2921
2922 /* Anything else is out of spec, warn and ignore */
2923 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2924 return connector_status_disconnected;
71ba9000
AJ		 2925}
2926
5eb08b69 2927static enum drm_connector_status
a9756bb5 2928ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2929{
30add22d 2930 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2933 enum drm_connector_status status;
2934
fe16d949
CW		 2935 /* Can't disconnect eDP, but you can close the lid... */
2936 if (is_edp(intel_dp)) {
30add22d 2937 status = intel_panel_detect(dev);
fe16d949
CW		 2938 if (status == connector_status_unknown)
2939 status = connector_status_connected;
2940 return status;
2941 }
01cb9ea6 2942
1b469639
DL		 2943 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2944 return connector_status_disconnected;
2945
26d61aad 2946 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2947}
2948
a4fc5ed6 2949static enum drm_connector_status
a9756bb5 2950g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2951{
30add22d 2952 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2953 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2955 uint32_t bit;
5eb08b69 2956
35aad75f
JB		 2957 /* Can't disconnect eDP, but you can close the lid... */
2958 if (is_edp(intel_dp)) {
2959 enum drm_connector_status status;
2960
2961 status = intel_panel_detect(dev);
2962 if (status == connector_status_unknown)
2963 status = connector_status_connected;
2964 return status;
2965 }
2966
34f2be46
VS		 2967 switch (intel_dig_port->port) {
2968 case PORT_B:
26739f12 2969 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2970 break;
34f2be46 2971 case PORT_C:
26739f12 2972 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2973 break;
34f2be46 2974 case PORT_D:
26739f12 2975 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2976 break;
2977 default:
2978 return connector_status_unknown;
2979 }
2980
10f76a38 2981 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2982 return connector_status_disconnected;
2983
26d61aad 2984 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2985}
2986
8c241fef
KP		 2987static struct edid *
2988intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2989{
9cd300e0 2990 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2991
9cd300e0
JN		 2992 /* use cached edid if we have one */
2993 if (intel_connector->edid) {
9cd300e0
JN		 2994 /* invalid edid */
2995 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2996 return NULL;
2997
55e9edeb 2998 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 2999 }
8c241fef 3000
9cd300e0 3001 return drm_get_edid(connector, adapter);
8c241fef
KP		 3002}
3003
3004static int
3005intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3006{
9cd300e0 3007 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3008
9cd300e0
JN		 3009 /* use cached edid if we have one */
3010 if (intel_connector->edid) {
3011 /* invalid edid */
3012 if (IS_ERR(intel_connector->edid))
3013 return 0;
3014
3015 return intel_connector_update_modes(connector,
3016 intel_connector->edid);
d6f24d0f
JB		 3017 }
3018
9cd300e0 3019 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3020}
3021
a9756bb5
ZW		 3022static enum drm_connector_status
3023intel_dp_detect(struct drm_connector *connector, bool force)
3024{
3025 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3026 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3027 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3028 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 3029 enum drm_connector_status status;
3030 struct edid *edid = NULL;
3031
164c8598
CW		 3032 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3033 connector->base.id, drm_get_connector_name(connector));
3034
a9756bb5
ZW		 3035 intel_dp->has_audio = false;
3036
3037 if (HAS_PCH_SPLIT(dev))
3038 status = ironlake_dp_detect(intel_dp);
3039 else
3040 status = g4x_dp_detect(intel_dp);
1b9be9d0 3041
a9756bb5
ZW		 3042 if (status != connector_status_connected)
3043 return status;
3044
0d198328
AJ		 3045 intel_dp_probe_oui(intel_dp);
3046
c3e5f67b
DV		 3047 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3048 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3049 } else {
8c241fef 3050 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3051 if (edid) {
3052 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3053 kfree(edid);
3054 }
a9756bb5
ZW		 3055 }
3056
d63885da
PZ		 3057 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3058 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 3059 return connector_status_connected;
a4fc5ed6
KP		 3060}
3061
3062static int intel_dp_get_modes(struct drm_connector *connector)
3063{
df0e9248 3064 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 3065 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3066 struct drm_device *dev = connector->dev;
32f9d658 3067 int ret;
a4fc5ed6
KP		 3068
3069 /* We should parse the EDID data and find out if it has an audio sink
3070 */
3071
8c241fef 3072 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3073 if (ret)
32f9d658
ZW		 3074 return ret;
3075
f8779fda 3076 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3077 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3078 struct drm_display_mode *mode;
dd06f90e
JN		 3079 mode = drm_mode_duplicate(dev,
3080 intel_connector->panel.fixed_mode);
f8779fda 3081 if (mode) {
32f9d658
ZW		 3082 drm_mode_probed_add(connector, mode);
3083 return 1;
3084 }
3085 }
3086 return 0;
a4fc5ed6
KP		 3087}
3088
1aad7ac0
CW		 3089static bool
3090intel_dp_detect_audio(struct drm_connector *connector)
3091{
3092 struct intel_dp *intel_dp = intel_attached_dp(connector);
3093 struct edid *edid;
3094 bool has_audio = false;
3095
8c241fef 3096 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3097 if (edid) {
3098 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3099 kfree(edid);
3100 }
3101
3102 return has_audio;
3103}
3104
f684960e
CW		 3105static int
3106intel_dp_set_property(struct drm_connector *connector,
3107 struct drm_property *property,
3108 uint64_t val)
3109{
e953fd7b 3110 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3111 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3112 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3113 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3114 int ret;
3115
662595df 3116 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3117 if (ret)
3118 return ret;
3119
3f43c48d 3120 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3121 int i = val;
3122 bool has_audio;
3123
3124 if (i == intel_dp->force_audio)
f684960e
CW		 3125 return 0;
3126
1aad7ac0 3127 intel_dp->force_audio = i;
f684960e 3128
c3e5f67b 3129 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3130 has_audio = intel_dp_detect_audio(connector);
3131 else
c3e5f67b 3132 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3133
3134 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3135 return 0;
3136
1aad7ac0 3137 intel_dp->has_audio = has_audio;
f684960e
CW		 3138 goto done;
3139 }
3140
e953fd7b 3141 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3142 bool old_auto = intel_dp->color_range_auto;
3143 uint32_t old_range = intel_dp->color_range;
3144
55bc60db
VS		 3145 switch (val) {
3146 case INTEL_BROADCAST_RGB_AUTO:
3147 intel_dp->color_range_auto = true;
3148 break;
3149 case INTEL_BROADCAST_RGB_FULL:
3150 intel_dp->color_range_auto = false;
3151 intel_dp->color_range = 0;
3152 break;
3153 case INTEL_BROADCAST_RGB_LIMITED:
3154 intel_dp->color_range_auto = false;
3155 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3156 break;
3157 default:
3158 return -EINVAL;
3159 }
ae4edb80
DV		 3160
3161 if (old_auto == intel_dp->color_range_auto &&
3162 old_range == intel_dp->color_range)
3163 return 0;
3164
e953fd7b
CW		 3165 goto done;
3166 }
3167
53b41837
YN		 3168 if (is_edp(intel_dp) &&
3169 property == connector->dev->mode_config.scaling_mode_property) {
3170 if (val == DRM_MODE_SCALE_NONE) {
3171 DRM_DEBUG_KMS("no scaling not supported\n");
3172 return -EINVAL;
3173 }
3174
3175 if (intel_connector->panel.fitting_mode == val) {
3176 /* the eDP scaling property is not changed */
3177 return 0;
3178 }
3179 intel_connector->panel.fitting_mode = val;
3180
3181 goto done;
3182 }
3183
f684960e
CW		 3184 return -EINVAL;
3185
3186done:
c0c36b94
CW		 3187 if (intel_encoder->base.crtc)
3188 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3189
3190 return 0;
3191}
3192
a4fc5ed6 3193static void
73845adf 3194intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3195{
1d508706 3196 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3197
9cd300e0
JN		 3198 if (!IS_ERR_OR_NULL(intel_connector->edid))
3199 kfree(intel_connector->edid);
3200
acd8db10
PZ		 3201 /* Can't call is_edp() since the encoder may have been destroyed
3202 * already. */
3203 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3204 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3205
a4fc5ed6 3206 drm_connector_cleanup(connector);
55f78c43 3207 kfree(connector);
a4fc5ed6
KP		 3208}
3209
00c09d70 3210void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3211{
da63a9f2
PZ		 3212 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3213 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3214 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3215
3216 i2c_del_adapter(&intel_dp->adapter);
3217 drm_encoder_cleanup(encoder);
bd943159
KP		 3218 if (is_edp(intel_dp)) {
3219 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3220 mutex_lock(&dev->mode_config.mutex);
bd943159 3221 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3222 mutex_unlock(&dev->mode_config.mutex);
bd943159 3223 }
da63a9f2 3224 kfree(intel_dig_port);
24d05927
DV		 3225}
3226
a4fc5ed6 3227static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3228 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3229 .detect = intel_dp_detect,
3230 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3231 .set_property = intel_dp_set_property,
73845adf 3232 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3233};
3234
3235static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3236 .get_modes = intel_dp_get_modes,
3237 .mode_valid = intel_dp_mode_valid,
df0e9248 3238 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3239};
3240
a4fc5ed6 3241static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3242 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3243};
3244
995b6762 3245static void
21d40d37 3246intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3247{
fa90ecef 3248 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3249
885a5014 3250 intel_dp_check_link_status(intel_dp);
c8110e52 3251}
6207937d 3252
e3421a18
ZW		 3253/* Return which DP Port should be selected for Transcoder DP control */
3254int
0206e353 3255intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3256{
3257 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3258 struct intel_encoder *intel_encoder;
3259 struct intel_dp *intel_dp;
e3421a18 3260
fa90ecef
PZ		 3261 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3262 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3263
fa90ecef
PZ		 3264 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3265 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3266 return intel_dp->output_reg;
e3421a18 3267 }
ea5b213a 3268
e3421a18
ZW		 3269 return -1;
3270}
3271
36e83a18 3272/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3273bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3274{
3275 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3276 union child_device_config *p_child;
36e83a18
ZY		 3277 int i;
3278
41aa3448 3279 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3280 return false;
3281
41aa3448
RV		 3282 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3283 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3284
768f69c9 3285 if (p_child->common.dvo_port == PORT_IDPD &&
f02586df
VS		 3286 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3287 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3288 return true;
3289 }
3290 return false;
3291}
3292
f684960e
CW		 3293static void
3294intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3295{
53b41837
YN		 3296 struct intel_connector *intel_connector = to_intel_connector(connector);
3297
3f43c48d 3298 intel_attach_force_audio_property(connector);
e953fd7b 3299 intel_attach_broadcast_rgb_property(connector);
55bc60db 3300 intel_dp->color_range_auto = true;
53b41837
YN		 3301
3302 if (is_edp(intel_dp)) {
3303 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3304 drm_object_attach_property(
3305 &connector->base,
53b41837 3306 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3307 DRM_MODE_SCALE_ASPECT);
3308 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3309 }
f684960e
CW		 3310}
3311
67a54566
DV		 3312static void
3313intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3314 struct intel_dp *intel_dp,
3315 struct edp_power_seq *out)
67a54566
DV		 3316{
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 struct edp_power_seq cur, vbt, spec, final;
3319 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3320 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3321
3322 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3323 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3324 pp_on_reg = PCH_PP_ON_DELAYS;
3325 pp_off_reg = PCH_PP_OFF_DELAYS;
3326 pp_div_reg = PCH_PP_DIVISOR;
3327 } else {
bf13e81b
JN		 3328 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3329
3330 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3331 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3332 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3333 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3334 }
67a54566
DV		 3335
3336 /* Workaround: Need to write PP_CONTROL with the unlock key as
3337 * the very first thing. */
453c5420 3338 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3339 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3340
453c5420
JB		 3341 pp_on = I915_READ(pp_on_reg);
3342 pp_off = I915_READ(pp_off_reg);
3343 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3344
3345 /* Pull timing values out of registers */
3346 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3347 PANEL_POWER_UP_DELAY_SHIFT;
3348
3349 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3350 PANEL_LIGHT_ON_DELAY_SHIFT;
3351
3352 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3353 PANEL_LIGHT_OFF_DELAY_SHIFT;
3354
3355 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3356 PANEL_POWER_DOWN_DELAY_SHIFT;
3357
3358 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3359 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3360
3361 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3362 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3363
41aa3448 3364 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3365
3366 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3367 * our hw here, which are all in 100usec. */
3368 spec.t1_t3 = 210 * 10;
3369 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3370 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3371 spec.t10 = 500 * 10;
3372 /* This one is special and actually in units of 100ms, but zero
3373 * based in the hw (so we need to add 100 ms). But the sw vbt
3374 * table multiplies it with 1000 to make it in units of 100usec,
3375 * too. */
3376 spec.t11_t12 = (510 + 100) * 10;
3377
3378 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3379 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3380
3381 /* Use the max of the register settings and vbt. If both are
3382 * unset, fall back to the spec limits. */
3383#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3384 spec.field : \
3385 max(cur.field, vbt.field))
3386 assign_final(t1_t3);
3387 assign_final(t8);
3388 assign_final(t9);
3389 assign_final(t10);
3390 assign_final(t11_t12);
3391#undef assign_final
3392
3393#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3394 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3395 intel_dp->backlight_on_delay = get_delay(t8);
3396 intel_dp->backlight_off_delay = get_delay(t9);
3397 intel_dp->panel_power_down_delay = get_delay(t10);
3398 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3399#undef get_delay
3400
f30d26e4
JN		 3401 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3402 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3403 intel_dp->panel_power_cycle_delay);
3404
3405 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3406 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3407
3408 if (out)
3409 *out = final;
3410}
3411
3412static void
3413intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3414 struct intel_dp *intel_dp,
3415 struct edp_power_seq *seq)
3416{
3417 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3418 u32 pp_on, pp_off, pp_div, port_sel = 0;
3419 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3420 int pp_on_reg, pp_off_reg, pp_div_reg;
3421
3422 if (HAS_PCH_SPLIT(dev)) {
3423 pp_on_reg = PCH_PP_ON_DELAYS;
3424 pp_off_reg = PCH_PP_OFF_DELAYS;
3425 pp_div_reg = PCH_PP_DIVISOR;
3426 } else {
bf13e81b
JN		 3427 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3428
3429 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3430 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3431 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3432 }
3433
67a54566 3434 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3435 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3436 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3437 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3438 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3439 /* Compute the divisor for the pp clock, simply match the Bspec
3440 * formula. */
453c5420 3441 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3442 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3443 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3444
3445 /* Haswell doesn't have any port selection bits for the panel
3446 * power sequencer any more. */
bc7d38a4 3447 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3448 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3449 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3450 else
3451 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3452 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3453 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3454 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3455 else
a24c144c 3456 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3457 }
3458
453c5420
JB		 3459 pp_on |= port_sel;
3460
3461 I915_WRITE(pp_on_reg, pp_on);
3462 I915_WRITE(pp_off_reg, pp_off);
3463 I915_WRITE(pp_div_reg, pp_div);
67a54566 3464
67a54566 3465 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3466 I915_READ(pp_on_reg),
3467 I915_READ(pp_off_reg),
3468 I915_READ(pp_div_reg));
f684960e
CW		 3469}
3470
ed92f0b2
PZ		 3471static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3472 struct intel_connector *intel_connector)
3473{
3474 struct drm_connector *connector = &intel_connector->base;
3475 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3476 struct drm_device *dev = intel_dig_port->base.base.dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct drm_display_mode *fixed_mode = NULL;
3479 struct edp_power_seq power_seq = { 0 };
3480 bool has_dpcd;
3481 struct drm_display_mode *scan;
3482 struct edid *edid;
3483
3484 if (!is_edp(intel_dp))
3485 return true;
3486
3487 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3488
3489 /* Cache DPCD and EDID for edp. */
3490 ironlake_edp_panel_vdd_on(intel_dp);
3491 has_dpcd = intel_dp_get_dpcd(intel_dp);
3492 ironlake_edp_panel_vdd_off(intel_dp, false);
3493
3494 if (has_dpcd) {
3495 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3496 dev_priv->no_aux_handshake =
3497 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3498 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3499 } else {
3500 /* if this fails, presume the device is a ghost */
3501 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3502 return false;
3503 }
3504
3505 /* We now know it's not a ghost, init power sequence regs. */
3506 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3507 &power_seq);
3508
ed92f0b2
PZ		 3509 edid = drm_get_edid(connector, &intel_dp->adapter);
3510 if (edid) {
3511 if (drm_add_edid_modes(connector, edid)) {
3512 drm_mode_connector_update_edid_property(connector,
3513 edid);
3514 drm_edid_to_eld(connector, edid);
3515 } else {
3516 kfree(edid);
3517 edid = ERR_PTR(-EINVAL);
3518 }
3519 } else {
3520 edid = ERR_PTR(-ENOENT);
3521 }
3522 intel_connector->edid = edid;
3523
3524 /* prefer fixed mode from EDID if available */
3525 list_for_each_entry(scan, &connector->probed_modes, head) {
3526 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3527 fixed_mode = drm_mode_duplicate(dev, scan);
3528 break;
3529 }
3530 }
3531
3532 /* fallback to VBT if available for eDP */
3533 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3534 fixed_mode = drm_mode_duplicate(dev,
3535 dev_priv->vbt.lfp_lvds_vbt_mode);
3536 if (fixed_mode)
3537 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3538 }
3539
ed92f0b2
PZ		 3540 intel_panel_init(&intel_connector->panel, fixed_mode);
3541 intel_panel_setup_backlight(connector);
3542
3543 return true;
3544}
3545
16c25533 3546bool
f0fec3f2
PZ		 3547intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3548 struct intel_connector *intel_connector)
a4fc5ed6 3549{
f0fec3f2
PZ		 3550 struct drm_connector *connector = &intel_connector->base;
3551 struct intel_dp *intel_dp = &intel_dig_port->dp;
3552 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3553 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3554 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3555 enum port port = intel_dig_port->port;
5eb08b69 3556 const char *name = NULL;
b2a14755 3557 int type, error;
a4fc5ed6 3558
0767935e
DV		 3559 /* Preserve the current hw state. */
3560 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3561 intel_dp->attached_connector = intel_connector;
3d3dc149 3562
f7d24902 3563 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3564 /*
3565 * FIXME : We need to initialize built-in panels before external panels.
3566 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3567 */
f7d24902
ID		 3568 switch (port) {
3569 case PORT_A:
b329530c 3570 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3571 break;
3572 case PORT_C:
3573 if (IS_VALLEYVIEW(dev))
3574 type = DRM_MODE_CONNECTOR_eDP;
3575 break;
3576 case PORT_D:
3577 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3578 type = DRM_MODE_CONNECTOR_eDP;
3579 break;
3580 default: /* silence GCC warning */
3581 break;
b329530c
AJ		 3582 }
3583
f7d24902
ID		 3584 /*
3585 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3586 * for DP the encoder type can be set by the caller to
3587 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3588 */
3589 if (type == DRM_MODE_CONNECTOR_eDP)
3590 intel_encoder->type = INTEL_OUTPUT_EDP;
3591
e7281eab
ID		 3592 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3593 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3594 port_name(port));
3595
b329530c 3596 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3597 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3598
a4fc5ed6
KP		 3599 connector->interlace_allowed = true;
3600 connector->doublescan_allowed = 0;
3601
f0fec3f2
PZ		 3602 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3603 ironlake_panel_vdd_work);
a4fc5ed6 3604
df0e9248 3605 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3606 drm_sysfs_connector_add(connector);
3607
affa9354 3608 if (HAS_DDI(dev))
bcbc889b
PZ		 3609 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3610 else
3611 intel_connector->get_hw_state = intel_connector_get_hw_state;
3612
9ed35ab1
PZ		 3613 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3614 if (HAS_DDI(dev)) {
3615 switch (intel_dig_port->port) {
3616 case PORT_A:
3617 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3618 break;
3619 case PORT_B:
3620 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3621 break;
3622 case PORT_C:
3623 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3624 break;
3625 case PORT_D:
3626 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3627 break;
3628 default:
3629 BUG();
3630 }
3631 }
e8cb4558 3632
a4fc5ed6 3633 /* Set up the DDC bus. */
ab9d7c30
PZ		 3634 switch (port) {
3635 case PORT_A:
1d843f9d 3636 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3637 name = "DPDDC-A";
3638 break;
3639 case PORT_B:
1d843f9d 3640 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3641 name = "DPDDC-B";
3642 break;
3643 case PORT_C:
1d843f9d 3644 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3645 name = "DPDDC-C";
3646 break;
3647 case PORT_D:
1d843f9d 3648 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3649 name = "DPDDC-D";
3650 break;
3651 default:
ad1c0b19 3652 BUG();
5eb08b69
ZW		 3653 }
3654
b2a14755
PZ		 3655 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3656 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3657 error, port_name(port));
c1f05264 3658
2b28bb1b
RV		 3659 intel_dp->psr_setup_done = false;
3660
b2f246a8 3661 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3662 i2c_del_adapter(&intel_dp->adapter);
3663 if (is_edp(intel_dp)) {
3664 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3665 mutex_lock(&dev->mode_config.mutex);
3666 ironlake_panel_vdd_off_sync(intel_dp);
3667 mutex_unlock(&dev->mode_config.mutex);
3668 }
b2f246a8
PZ		 3669 drm_sysfs_connector_remove(connector);
3670 drm_connector_cleanup(connector);
16c25533 3671 return false;
b2f246a8 3672 }
32f9d658 3673
f684960e
CW		 3674 intel_dp_add_properties(intel_dp, connector);
3675
a4fc5ed6
KP		 3676 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3677 * 0xd. Failure to do so will result in spurious interrupts being
3678 * generated on the port when a cable is not attached.
3679 */
3680 if (IS_G4X(dev) && !IS_GM45(dev)) {
3681 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3682 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3683 }
16c25533
PZ		 3684
3685 return true;
a4fc5ed6 3686}
f0fec3f2
PZ		 3687
3688void
3689intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3690{
3691 struct intel_digital_port *intel_dig_port;
3692 struct intel_encoder *intel_encoder;
3693 struct drm_encoder *encoder;
3694 struct intel_connector *intel_connector;
3695
b14c5679 3696 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3697 if (!intel_dig_port)
3698 return;
3699
b14c5679 3700 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3701 if (!intel_connector) {
3702 kfree(intel_dig_port);
3703 return;
3704 }
3705
3706 intel_encoder = &intel_dig_port->base;
3707 encoder = &intel_encoder->base;
3708
3709 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3710 DRM_MODE_ENCODER_TMDS);
3711
5bfe2ac0 3712 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3713 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3714 intel_encoder->disable = intel_disable_dp;
3715 intel_encoder->post_disable = intel_post_disable_dp;
3716 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3717 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3718 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3719 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3720 intel_encoder->pre_enable = vlv_pre_enable_dp;
3721 intel_encoder->enable = vlv_enable_dp;
3722 } else {
ecff4f3b
JN		 3723 intel_encoder->pre_enable = g4x_pre_enable_dp;
3724 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3725 }
f0fec3f2 3726
174edf1f 3727 intel_dig_port->port = port;
f0fec3f2
PZ		 3728 intel_dig_port->dp.output_reg = output_reg;
3729
00c09d70 3730 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3731 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3732 intel_encoder->cloneable = false;
3733 intel_encoder->hot_plug = intel_dp_hot_plug;
3734
15b1d171
PZ		 3735 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3736 drm_encoder_cleanup(encoder);
3737 kfree(intel_dig_port);
b2f246a8 3738 kfree(intel_connector);
15b1d171 3739 }
f0fec3f2 3740}
Linux kernel - Deliverables
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