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drm/i915: drop init_dpio, shouldn't be needed
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
a4fc5ed6 112static int
ea5b213a 113intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 114{
7183dc29 115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 116
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
119 case DP_LINK_BW_2_7:
120 break;
121 default:
122 max_link_bw = DP_LINK_BW_1_62;
123 break;
124 }
125 return max_link_bw;
126}
127
cd9dde44
AJ		 128/*
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
131 *
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
133 *
134 * 270000 * 1 * 8 / 10 == 216000
135 *
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
140 *
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
143 */
144
a4fc5ed6 145static int
c898261c 146intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 147{
cd9dde44 148 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 149}
150
fe27d53e
DA		 151static int
152intel_dp_max_data_rate(int max_link_clock, int max_lanes)
153{
154 return (max_link_clock * max_lanes * 8) / 10;
155}
156
a4fc5ed6
KP		 157static int
158intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
160{
df0e9248 161 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 166
dd06f90e
JN		 167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 169 return MODE_PANEL;
170
dd06f90e 171 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 172 return MODE_PANEL;
03afc4a2
DV		 173
174 target_clock = fixed_mode->clock;
7de56f43
ZY		 175 }
176
36008365
DV		 177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
c4867936 184 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 185
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
188
0af78a2b
DV		 189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
191
a4fc5ed6
KP		 192 return MODE_OK;
193}
194
195static uint32_t
196pack_aux(uint8_t *src, int src_bytes)
197{
198 int i;
199 uint32_t v = 0;
200
201 if (src_bytes > 4)
202 src_bytes = 4;
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 return v;
206}
207
208static void
209unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210{
211 int i;
212 if (dst_bytes > 4)
213 dst_bytes = 4;
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
216}
217
fb0f8fbf
KP		 218/* hrawclock is 1/4 the FSB frequency */
219static int
220intel_hrawclk(struct drm_device *dev)
221{
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 uint32_t clkcfg;
224
9473c8f4
VP		 225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
227 return 200;
228
fb0f8fbf
KP		 229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
231 case CLKCFG_FSB_400:
232 return 100;
233 case CLKCFG_FSB_533:
234 return 133;
235 case CLKCFG_FSB_667:
236 return 166;
237 case CLKCFG_FSB_800:
238 return 200;
239 case CLKCFG_FSB_1067:
240 return 266;
241 case CLKCFG_FSB_1333:
242 return 333;
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
246 return 400;
247 default:
248 return 133;
249 }
250}
251
ebf33b18
KP		 252static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
253{
30add22d 254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 255 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 256 u32 pp_stat_reg;
ebf33b18 257
453c5420
JB		 258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 260}
261
262static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
263{
30add22d 264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 265 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 266 u32 pp_ctrl_reg;
ebf33b18 267
453c5420
JB		 268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 270}
271
9b984dae
KP		 272static void
273intel_dp_check_edp(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 276 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 277 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 278
9b984dae
KP		 279 if (!is_edp(intel_dp))
280 return;
453c5420
JB		 281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
ebf33b18 285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
9b984dae
KP		 290 }
291}
292
9ee32fea
DV		 293static uint32_t
294intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 300 uint32_t status;
301 bool done;
302
ef04f00d 303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 304 if (has_aux_irq)
b90f5176
PZ		 305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
9ee32fea
DV		 307 else
308 done = wait_for_atomic(C, 10) == 0;
309 if (!done)
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
311 has_aux_irq);
312#undef C
313
314 return status;
315}
316
a4fc5ed6 317static int
ea5b213a 318intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
321{
174edf1f
PZ		 322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 324 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 326 uint32_t ch_data = ch_ctl + 4;
9ee32fea 327 int i, ret, recv_bytes;
a4fc5ed6 328 uint32_t status;
fb0f8fbf 329 uint32_t aux_clock_divider;
6b4e0a93 330 int try, precharge;
9ee32fea
DV		 331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
332
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
335 * deep sleep states.
336 */
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 338
9b984dae 339 intel_dp_check_edp(intel_dp);
a4fc5ed6 340 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 343 *
344 * Note that PCH attached eDP panels should use a 125MHz input
345 * clock divider.
a4fc5ed6 346 */
1c95822a 347 if (is_cpu_edp(intel_dp)) {
affa9354 348 if (HAS_DDI(dev))
b8fc2f6a
PZ		 349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 354 else
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 356 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider = 74;
359 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 360 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 361 } else {
5eb08b69 362 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 363 }
5eb08b69 364
6b4e0a93
DV		 365 if (IS_GEN6(dev))
366 precharge = 3;
367 else
368 precharge = 5;
369
11bee43e
JB		 370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
ef04f00d 372 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 373 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
374 break;
375 msleep(1);
376 }
377
378 if (try == 3) {
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
380 I915_READ(ch_ctl));
9ee32fea
DV		 381 ret = -EBUSY;
382 goto out;
4f7f7b7e
CW		 383 }
384
fb0f8fbf
KP		 385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 388 for (i = 0; i < send_bytes; i += 4)
389 I915_WRITE(ch_data + i,
390 pack_aux(send + i, send_bytes - i));
0206e353 391
fb0f8fbf 392 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 393 I915_WRITE(ch_ctl,
394 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 395 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 396 DP_AUX_CH_CTL_TIME_OUT_400us |
397 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
398 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
399 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
400 DP_AUX_CH_CTL_DONE |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR |
402 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 403
404 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 405
fb0f8fbf 406 /* Clear done status and any errors */
4f7f7b7e
CW		 407 I915_WRITE(ch_ctl,
408 status |
409 DP_AUX_CH_CTL_DONE |
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 412
413 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR))
415 continue;
4f7f7b7e 416 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 417 break;
418 }
419
a4fc5ed6 420 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 422 ret = -EBUSY;
423 goto out;
a4fc5ed6
KP		 424 }
425
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
428 */
a5b3da54 429 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 431 ret = -EIO;
432 goto out;
a5b3da54 433 }
1ae8c0a5
KP		 434
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
a5b3da54 437 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 439 ret = -ETIMEDOUT;
440 goto out;
a4fc5ed6
KP		 441 }
442
443 /* Unload any bytes sent back from the other side */
444 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 446 if (recv_bytes > recv_size)
447 recv_bytes = recv_size;
0206e353 448
4f7f7b7e
CW		 449 for (i = 0; i < recv_bytes; i += 4)
450 unpack_aux(I915_READ(ch_data + i),
451 recv + i, recv_bytes - i);
a4fc5ed6 452
9ee32fea
DV		 453 ret = recv_bytes;
454out:
455 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
456
457 return ret;
a4fc5ed6
KP		 458}
459
460/* Write data to the aux channel in native mode */
461static int
ea5b213a 462intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 463 uint16_t address, uint8_t *send, int send_bytes)
464{
465 int ret;
466 uint8_t msg[20];
467 int msg_bytes;
468 uint8_t ack;
469
9b984dae 470 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 471 if (send_bytes > 16)
472 return -1;
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
eebc863e 475 msg[2] = address & 0xff;
a4fc5ed6
KP		 476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
479 for (;;) {
ea5b213a 480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 481 if (ret < 0)
482 return ret;
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
484 break;
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
486 udelay(100);
487 else
a5b3da54 488 return -EIO;
a4fc5ed6
KP		 489 }
490 return send_bytes;
491}
492
493/* Write a single byte to the aux channel in native mode */
494static int
ea5b213a 495intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 496 uint16_t address, uint8_t byte)
497{
ea5b213a 498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 499}
500
501/* read bytes from a native aux channel */
502static int
ea5b213a 503intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 504 uint16_t address, uint8_t *recv, int recv_bytes)
505{
506 uint8_t msg[4];
507 int msg_bytes;
508 uint8_t reply[20];
509 int reply_bytes;
510 uint8_t ack;
511 int ret;
512
9b984dae 513 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
518
519 msg_bytes = 4;
520 reply_bytes = recv_bytes + 1;
521
522 for (;;) {
ea5b213a 523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 524 reply, reply_bytes);
a5b3da54
KP		 525 if (ret == 0)
526 return -EPROTO;
527 if (ret < 0)
a4fc5ed6
KP		 528 return ret;
529 ack = reply[0];
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
532 return ret - 1;
533 }
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
535 udelay(100);
536 else
a5b3da54 537 return -EIO;
a4fc5ed6
KP		 538 }
539}
540
541static int
ab2c0672
DA		 542intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 544{
ab2c0672 545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 546 struct intel_dp *intel_dp = container_of(adapter,
547 struct intel_dp,
548 adapter);
ab2c0672
DA		 549 uint16_t address = algo_data->address;
550 uint8_t msg[5];
551 uint8_t reply[2];
8316f337 552 unsigned retry;
ab2c0672
DA		 553 int msg_bytes;
554 int reply_bytes;
555 int ret;
556
9b984dae 557 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
561 else
562 msg[0] = AUX_I2C_WRITE << 4;
563
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 566
ab2c0672
DA		 567 msg[1] = address >> 8;
568 msg[2] = address;
569
570 switch (mode) {
571 case MODE_I2C_WRITE:
572 msg[3] = 0;
573 msg[4] = write_byte;
574 msg_bytes = 5;
575 reply_bytes = 1;
576 break;
577 case MODE_I2C_READ:
578 msg[3] = 0;
579 msg_bytes = 4;
580 reply_bytes = 2;
581 break;
582 default:
583 msg_bytes = 3;
584 reply_bytes = 1;
585 break;
586 }
587
8316f337
DF		 588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
590 msg, msg_bytes,
591 reply, reply_bytes);
ab2c0672 592 if (ret < 0) {
3ff99164 593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 594 return ret;
595 }
8316f337
DF		 596
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
601 */
602 break;
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
605 return -EREMOTEIO;
606 case AUX_NATIVE_REPLY_DEFER:
607 udelay(100);
608 continue;
609 default:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
611 reply[0]);
612 return -EREMOTEIO;
613 }
614
ab2c0672
DA		 615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
619 }
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
8316f337 622 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 623 return -EREMOTEIO;
624 case AUX_I2C_REPLY_DEFER:
8316f337 625 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 626 udelay(100);
627 break;
628 default:
8316f337 629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 630 return -EREMOTEIO;
631 }
632 }
8316f337
DF		 633
634 DRM_ERROR("too many retries, giving up\n");
635 return -EREMOTEIO;
a4fc5ed6
KP		 636}
637
638static int
ea5b213a 639intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 640 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 641{
0b5c541b
KP		 642 int ret;
643
d54e9d28 644 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 645 intel_dp->algo.running = false;
646 intel_dp->algo.address = 0;
647 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
648
0206e353 649 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 650 intel_dp->adapter.owner = THIS_MODULE;
651 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 652 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 653 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
654 intel_dp->adapter.algo_data = &intel_dp->algo;
655 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
656
0b5c541b
KP		 657 ironlake_edp_panel_vdd_on(intel_dp);
658 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 659 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 660 return ret;
a4fc5ed6
KP		 661}
662
00c09d70 663bool
5bfe2ac0
DV		 664intel_dp_compute_config(struct intel_encoder *encoder,
665 struct intel_crtc_config *pipe_config)
a4fc5ed6 666{
5bfe2ac0 667 struct drm_device *dev = encoder->base.dev;
36008365 668 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV		 669 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
670 struct drm_display_mode *mode = &pipe_config->requested_mode;
671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
dd06f90e 672 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 673 int lane_count, clock;
397fe157 674 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 675 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 676 int bpp, mode_rate;
a4fc5ed6 677 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 678 int target_clock, link_avail, link_clock;
a4fc5ed6 679
5bfe2ac0
DV		 680 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
681 pipe_config->has_pch_encoder = true;
682
03afc4a2
DV		 683 pipe_config->has_dp_encoder = true;
684
dd06f90e
JN		 685 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
686 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
687 adjusted_mode);
53b41837
YN		 688 intel_pch_panel_fitting(dev,
689 intel_connector->panel.fitting_mode,
1d8e1c75 690 mode, adjusted_mode);
0d3a1bee 691 }
36008365
DV		 692 /* We need to take the panel's fixed mode into account. */
693 target_clock = adjusted_mode->clock;
0d3a1bee 694
cb1793ce 695 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 696 return false;
697
083f9560
DV		 698 DRM_DEBUG_KMS("DP link computation with max lane count %i "
699 "max bw %02x pixel clock %iKHz\n",
71244653 700 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 701
36008365
DV		 702 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
703 * bpc in between. */
03afc4a2 704 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
36008365
DV		 705 for (; bpp >= 6*3; bpp -= 2*3) {
706 mode_rate = intel_dp_link_required(target_clock, bpp);
707
708 for (clock = 0; clock <= max_clock; clock++) {
709 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
710 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
711 link_avail = intel_dp_max_data_rate(link_clock,
712 lane_count);
713
714 if (mode_rate <= link_avail) {
715 goto found;
716 }
717 }
718 }
719 }
c4867936 720
36008365 721 return false;
3685a8f3 722
36008365 723found:
55bc60db
VS		 724 if (intel_dp->color_range_auto) {
725 /*
726 * See:
727 * CEA-861-E - 5.1 Default Encoding Parameters
728 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
729 */
18316c8c 730 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 731 intel_dp->color_range = DP_COLOR_RANGE_16_235;
732 else
733 intel_dp->color_range = 0;
734 }
735
3685a8f3 736 if (intel_dp->color_range)
50f3b016 737 pipe_config->limited_color_range = true;
3685a8f3 738
36008365
DV		 739 intel_dp->link_bw = bws[clock];
740 intel_dp->lane_count = lane_count;
741 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
df92b1e6 742 pipe_config->pixel_target_clock = target_clock;
fe27d53e 743
36008365
DV		 744 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
745 intel_dp->link_bw, intel_dp->lane_count,
746 adjusted_mode->clock, bpp);
747 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
748 mode_rate, link_avail);
749
03afc4a2
DV		 750 intel_link_compute_m_n(bpp, lane_count,
751 target_clock, adjusted_mode->clock,
752 &pipe_config->dp_m_n);
a4fc5ed6 753
57c21963
DV		 754 /*
755 * XXX: We have a strange regression where using the vbt edp bpp value
756 * for the link bw computation results in black screens, the panel only
757 * works when we do the computation at the usual 24bpp (but still
758 * requires us to use 18bpp). Until that's fully debugged, stay
759 * bug-for-bug compatible with the old code.
760 */
761 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
762 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
763 bpp, dev_priv->edp.bpp);
764 bpp = min_t(int, bpp, dev_priv->edp.bpp);
765 }
766 pipe_config->pipe_bpp = bpp;
767
03afc4a2 768 return true;
a4fc5ed6
KP		 769}
770
247d89f6
PZ		 771void intel_dp_init_link_config(struct intel_dp *intel_dp)
772{
773 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
774 intel_dp->link_configuration[0] = intel_dp->link_bw;
775 intel_dp->link_configuration[1] = intel_dp->lane_count;
776 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
777 /*
778 * Check for DPCD version > 1.1 and enhanced framing support
779 */
780 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
781 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
782 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
783 }
784}
785
ea9b6006
DV		 786static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
787{
788 struct drm_device *dev = crtc->dev;
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 dpa_ctl;
791
792 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
793 dpa_ctl = I915_READ(DP_A);
794 dpa_ctl &= ~DP_PLL_FREQ_MASK;
795
796 if (clock < 200000) {
1ce17038
DV		 797 /* For a long time we've carried around a ILK-DevA w/a for the
798 * 160MHz clock. If we're really unlucky, it's still required.
799 */
800 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 801 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 802 } else {
803 dpa_ctl |= DP_PLL_FREQ_270MHZ;
804 }
1ce17038 805
ea9b6006
DV		 806 I915_WRITE(DP_A, dpa_ctl);
807
808 POSTING_READ(DP_A);
809 udelay(500);
810}
811
a4fc5ed6
KP		 812static void
813intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
814 struct drm_display_mode *adjusted_mode)
815{
e3421a18 816 struct drm_device *dev = encoder->dev;
417e822d 817 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 818 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 819 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
821
417e822d 822 /*
1a2eb460 823 * There are four kinds of DP registers:
417e822d
KP		 824 *
825 * IBX PCH
1a2eb460
KP		 826 * SNB CPU
827 * IVB CPU
417e822d
KP		 828 * CPT PCH
829 *
830 * IBX PCH and CPU are the same for almost everything,
831 * except that the CPU DP PLL is configured in this
832 * register
833 *
834 * CPT PCH is quite different, having many bits moved
835 * to the TRANS_DP_CTL register instead. That
836 * configuration happens (oddly) in ironlake_pch_enable
837 */
9c9e7927 838
417e822d
KP		 839 /* Preserve the BIOS-computed detected bit. This is
840 * supposed to be read-only.
841 */
842 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 843
417e822d 844 /* Handle DP bits in common between all three register formats */
417e822d 845 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 846
ea5b213a 847 switch (intel_dp->lane_count) {
a4fc5ed6 848 case 1:
ea5b213a 849 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 850 break;
851 case 2:
ea5b213a 852 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 853 break;
854 case 4:
ea5b213a 855 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 856 break;
857 }
e0dac65e
WF		 858 if (intel_dp->has_audio) {
859 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
860 pipe_name(intel_crtc->pipe));
ea5b213a 861 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 862 intel_write_eld(encoder, adjusted_mode);
863 }
247d89f6
PZ		 864
865 intel_dp_init_link_config(intel_dp);
a4fc5ed6 866
417e822d 867 /* Split out the IBX/CPU vs CPT settings */
32f9d658 868
19c03924 869 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 870 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
871 intel_dp->DP |= DP_SYNC_HS_HIGH;
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
873 intel_dp->DP |= DP_SYNC_VS_HIGH;
874 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
875
876 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
877 intel_dp->DP |= DP_ENHANCED_FRAMING;
878
879 intel_dp->DP |= intel_crtc->pipe << 29;
880
881 /* don't miss out required setting for eDP */
1a2eb460
KP		 882 if (adjusted_mode->clock < 200000)
883 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
884 else
885 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
886 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 887 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 888 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 889
890 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
891 intel_dp->DP |= DP_SYNC_HS_HIGH;
892 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
893 intel_dp->DP |= DP_SYNC_VS_HIGH;
894 intel_dp->DP |= DP_LINK_TRAIN_OFF;
895
896 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
897 intel_dp->DP |= DP_ENHANCED_FRAMING;
898
899 if (intel_crtc->pipe == 1)
900 intel_dp->DP |= DP_PIPEB_SELECT;
901
b2634017 902 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 903 /* don't miss out required setting for eDP */
417e822d
KP		 904 if (adjusted_mode->clock < 200000)
905 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
906 else
907 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
908 }
909 } else {
910 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 911 }
ea9b6006 912
5d66d5b6 913 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 914 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 915}
916
99ea7127
KP		 917#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
918#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
919
920#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
921#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
922
923#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
924#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
925
926static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
927 u32 mask,
928 u32 value)
bd943159 929{
30add22d 930 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 931 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 932 u32 pp_stat_reg, pp_ctrl_reg;
933
934 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
935 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 936
99ea7127 937 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 938 mask, value,
939 I915_READ(pp_stat_reg),
940 I915_READ(pp_ctrl_reg));
32ce697c 941
453c5420 942 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 943 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 944 I915_READ(pp_stat_reg),
945 I915_READ(pp_ctrl_reg));
32ce697c 946 }
99ea7127 947}
32ce697c 948
99ea7127
KP		 949static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
950{
951 DRM_DEBUG_KMS("Wait for panel power on\n");
952 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 953}
954
99ea7127
KP		 955static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
956{
957 DRM_DEBUG_KMS("Wait for panel power off time\n");
958 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
959}
960
961static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
962{
963 DRM_DEBUG_KMS("Wait for panel power cycle\n");
964 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
965}
966
967
832dd3c1
KP		 968/* Read the current pp_control value, unlocking the register if it
969 * is locked
970 */
971
453c5420 972static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 973{
453c5420
JB		 974 struct drm_device *dev = intel_dp_to_dev(intel_dp);
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u32 control;
977 u32 pp_ctrl_reg;
978
979 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
980 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 981
982 control &= ~PANEL_UNLOCK_MASK;
983 control |= PANEL_UNLOCK_REGS;
984 return control;
bd943159
KP		 985}
986
82a4d9c0 987void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 988{
30add22d 989 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u32 pp;
453c5420 992 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 993
97af61f5
KP		 994 if (!is_edp(intel_dp))
995 return;
f01eca2e 996 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 997
bd943159
KP		 998 WARN(intel_dp->want_panel_vdd,
999 "eDP VDD already requested on\n");
1000
1001 intel_dp->want_panel_vdd = true;
99ea7127 1002
bd943159
KP		 1003 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1004 DRM_DEBUG_KMS("eDP VDD already on\n");
1005 return;
1006 }
1007
99ea7127
KP		 1008 if (!ironlake_edp_have_panel_power(intel_dp))
1009 ironlake_wait_panel_power_cycle(intel_dp);
1010
453c5420 1011 pp = ironlake_get_pp_control(intel_dp);
5d613501 1012 pp |= EDP_FORCE_VDD;
ebf33b18 1013
453c5420
JB		 1014 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1015 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1016
1017 I915_WRITE(pp_ctrl_reg, pp);
1018 POSTING_READ(pp_ctrl_reg);
1019 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1020 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1021 /*
1022 * If the panel wasn't on, delay before accessing aux channel
1023 */
1024 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1025 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1026 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1027 }
5d613501
JB		 1028}
1029
bd943159 1030static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1031{
30add22d 1032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u32 pp;
453c5420 1035 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1036
a0e99e68
DV		 1037 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1038
bd943159 1039 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1040 pp = ironlake_get_pp_control(intel_dp);
bd943159 1041 pp &= ~EDP_FORCE_VDD;
bd943159 1042
453c5420
JB		 1043 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1044 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1045
1046 I915_WRITE(pp_ctrl_reg, pp);
1047 POSTING_READ(pp_ctrl_reg);
99ea7127 1048
453c5420
JB		 1049 /* Make sure sequencer is idle before allowing subsequent activity */
1050 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1051 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1052 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1053 }
1054}
5d613501 1055
bd943159
KP		 1056static void ironlake_panel_vdd_work(struct work_struct *__work)
1057{
1058 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1059 struct intel_dp, panel_vdd_work);
30add22d 1060 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1061
627f7675 1062 mutex_lock(&dev->mode_config.mutex);
bd943159 1063 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1064 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1065}
1066
82a4d9c0 1067void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1068{
97af61f5
KP		 1069 if (!is_edp(intel_dp))
1070 return;
5d613501 1071
bd943159
KP		 1072 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1073 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1074
bd943159
KP		 1075 intel_dp->want_panel_vdd = false;
1076
1077 if (sync) {
1078 ironlake_panel_vdd_off_sync(intel_dp);
1079 } else {
1080 /*
1081 * Queue the timer to fire a long
1082 * time from now (relative to the power down delay)
1083 * to keep the panel power up across a sequence of operations
1084 */
1085 schedule_delayed_work(&intel_dp->panel_vdd_work,
1086 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1087 }
5d613501
JB		 1088}
1089
82a4d9c0 1090void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1091{
30add22d 1092 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1093 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1094 u32 pp;
453c5420 1095 u32 pp_ctrl_reg;
9934c132 1096
97af61f5 1097 if (!is_edp(intel_dp))
bd943159 1098 return;
99ea7127
KP		 1099
1100 DRM_DEBUG_KMS("Turn eDP power on\n");
1101
1102 if (ironlake_edp_have_panel_power(intel_dp)) {
1103 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1104 return;
99ea7127 1105 }
9934c132 1106
99ea7127 1107 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1108
453c5420 1109 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1110 if (IS_GEN5(dev)) {
1111 /* ILK workaround: disable reset around power sequence */
1112 pp &= ~PANEL_POWER_RESET;
1113 I915_WRITE(PCH_PP_CONTROL, pp);
1114 POSTING_READ(PCH_PP_CONTROL);
1115 }
37c6c9b0 1116
1c0ae80a 1117 pp |= POWER_TARGET_ON;
99ea7127
KP		 1118 if (!IS_GEN5(dev))
1119 pp |= PANEL_POWER_RESET;
1120
453c5420
JB		 1121 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1122
1123 I915_WRITE(pp_ctrl_reg, pp);
1124 POSTING_READ(pp_ctrl_reg);
9934c132 1125
99ea7127 1126 ironlake_wait_panel_on(intel_dp);
9934c132 1127
05ce1a49
KP		 1128 if (IS_GEN5(dev)) {
1129 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1130 I915_WRITE(PCH_PP_CONTROL, pp);
1131 POSTING_READ(PCH_PP_CONTROL);
1132 }
9934c132
JB		 1133}
1134
82a4d9c0 1135void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1136{
30add22d 1137 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1138 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1139 u32 pp;
453c5420 1140 u32 pp_ctrl_reg;
9934c132 1141
97af61f5
KP		 1142 if (!is_edp(intel_dp))
1143 return;
37c6c9b0 1144
99ea7127 1145 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1146
6cb49835 1147 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1148
453c5420 1149 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1150 /* We need to switch off panel power _and_ force vdd, for otherwise some
1151 * panels get very unhappy and cease to work. */
1152 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1153
1154 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1155
1156 I915_WRITE(pp_ctrl_reg, pp);
1157 POSTING_READ(pp_ctrl_reg);
9934c132 1158
35a38556
DV		 1159 intel_dp->want_panel_vdd = false;
1160
99ea7127 1161 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1162}
1163
d6c50ff8 1164void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1165{
da63a9f2
PZ		 1166 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1167 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1168 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1169 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1170 u32 pp;
453c5420 1171 u32 pp_ctrl_reg;
32f9d658 1172
f01eca2e
KP		 1173 if (!is_edp(intel_dp))
1174 return;
1175
28c97730 1176 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1177 /*
1178 * If we enable the backlight right away following a panel power
1179 * on, we may see slight flicker as the panel syncs with the eDP
1180 * link. So delay a bit to make sure the image is solid before
1181 * allowing it to appear.
1182 */
f01eca2e 1183 msleep(intel_dp->backlight_on_delay);
453c5420 1184 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1185 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1186
1187 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1188
1189 I915_WRITE(pp_ctrl_reg, pp);
1190 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1191
1192 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1193}
1194
d6c50ff8 1195void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1196{
30add22d 1197 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 u32 pp;
453c5420 1200 u32 pp_ctrl_reg;
32f9d658 1201
f01eca2e
KP		 1202 if (!is_edp(intel_dp))
1203 return;
1204
035aa3de
DV		 1205 intel_panel_disable_backlight(dev);
1206
28c97730 1207 DRM_DEBUG_KMS("\n");
453c5420 1208 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1209 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1210
1211 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1212
1213 I915_WRITE(pp_ctrl_reg, pp);
1214 POSTING_READ(pp_ctrl_reg);
f01eca2e 1215 msleep(intel_dp->backlight_off_delay);
32f9d658 1216}
a4fc5ed6 1217
2bd2ad64 1218static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1219{
da63a9f2
PZ		 1220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
2bd2ad64
DV		 1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1228
d240f20f
JB		 1229 DRM_DEBUG_KMS("\n");
1230 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1231 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234 /* We don't adjust intel_dp->DP while tearing down the link, to
1235 * facilitate link retraining (e.g. after hotplug). Hence clear all
1236 * enable bits here to ensure that we don't enable too much. */
1237 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1238 intel_dp->DP |= DP_PLL_ENABLE;
1239 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1240 POSTING_READ(DP_A);
1241 udelay(200);
d240f20f
JB		 1242}
1243
2bd2ad64 1244static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1245{
da63a9f2
PZ		 1246 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1247 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1248 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 u32 dpa_ctl;
1251
2bd2ad64
DV		 1252 assert_pipe_disabled(dev_priv,
1253 to_intel_crtc(crtc)->pipe);
1254
d240f20f 1255 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1256 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1257 "dp pll off, should be on\n");
1258 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1259
1260 /* We can't rely on the value tracked for the DP register in
1261 * intel_dp->DP because link_down must not change that (otherwise link
1262 * re-training will fail. */
298b0b39 1263 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1264 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1265 POSTING_READ(DP_A);
d240f20f
JB		 1266 udelay(200);
1267}
1268
c7ad3810 1269/* If the sink supports it, try to set the power state appropriately */
c19b0669 1270void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1271{
1272 int ret, i;
1273
1274 /* Should have a valid DPCD by this point */
1275 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1276 return;
1277
1278 if (mode != DRM_MODE_DPMS_ON) {
1279 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1280 DP_SET_POWER_D3);
1281 if (ret != 1)
1282 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1283 } else {
1284 /*
1285 * When turning on, we need to retry for 1ms to give the sink
1286 * time to wake up.
1287 */
1288 for (i = 0; i < 3; i++) {
1289 ret = intel_dp_aux_native_write_1(intel_dp,
1290 DP_SET_POWER,
1291 DP_SET_POWER_D0);
1292 if (ret == 1)
1293 break;
1294 msleep(1);
1295 }
1296 }
1297}
1298
19d8fe15
DV		 1299static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1300 enum pipe *pipe)
d240f20f 1301{
19d8fe15
DV		 1302 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1303 struct drm_device *dev = encoder->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 u32 tmp = I915_READ(intel_dp->output_reg);
1306
1307 if (!(tmp & DP_PORT_EN))
1308 return false;
1309
5d66d5b6 1310 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1311 *pipe = PORT_TO_PIPE_CPT(tmp);
1312 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1313 *pipe = PORT_TO_PIPE(tmp);
1314 } else {
1315 u32 trans_sel;
1316 u32 trans_dp;
1317 int i;
1318
1319 switch (intel_dp->output_reg) {
1320 case PCH_DP_B:
1321 trans_sel = TRANS_DP_PORT_SEL_B;
1322 break;
1323 case PCH_DP_C:
1324 trans_sel = TRANS_DP_PORT_SEL_C;
1325 break;
1326 case PCH_DP_D:
1327 trans_sel = TRANS_DP_PORT_SEL_D;
1328 break;
1329 default:
1330 return true;
1331 }
1332
1333 for_each_pipe(i) {
1334 trans_dp = I915_READ(TRANS_DP_CTL(i));
1335 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1336 *pipe = i;
1337 return true;
1338 }
1339 }
19d8fe15 1340
4a0833ec
DV		 1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342 intel_dp->output_reg);
1343 }
d240f20f 1344
2af8898b 1345 return true;
19d8fe15 1346}
d240f20f 1347
e8cb4558 1348static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1349{
e8cb4558 1350 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1351
1352 /* Make sure the panel is off before trying to change the mode. But also
1353 * ensure that we have vdd while we switch off the panel. */
1354 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1355 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1356 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1357 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1358
1359 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1360 if (!is_cpu_edp(intel_dp))
1361 intel_dp_link_down(intel_dp);
d240f20f
JB		 1362}
1363
2bd2ad64 1364static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1365{
2bd2ad64 1366 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1367 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1368
3739850b
DV		 1369 if (is_cpu_edp(intel_dp)) {
1370 intel_dp_link_down(intel_dp);
b2634017
JB		 1371 if (!IS_VALLEYVIEW(dev))
1372 ironlake_edp_pll_off(intel_dp);
3739850b 1373 }
2bd2ad64
DV		 1374}
1375
e8cb4558 1376static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1377{
e8cb4558
DV		 1378 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1382
0c33d8d7
DV		 1383 if (WARN_ON(dp_reg & DP_PORT_EN))
1384 return;
5d613501 1385
97af61f5 1386 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1387 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1388 intel_dp_start_link_train(intel_dp);
97af61f5 1389 ironlake_edp_panel_on(intel_dp);
bd943159 1390 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1391 intel_dp_complete_link_train(intel_dp);
f01eca2e 1392 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1393}
1394
2bd2ad64 1395static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1396{
2bd2ad64 1397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1398 struct drm_device *dev = encoder->base.dev;
a4fc5ed6 1399
b2634017 1400 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1401 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1402}
1403
1404/*
df0c237d
JB		 1405 * Native read with retry for link status and receiver capability reads for
1406 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1407 */
1408static bool
df0c237d
JB		 1409intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1410 uint8_t *recv, int recv_bytes)
a4fc5ed6 1411{
61da5fab
JB		 1412 int ret, i;
1413
df0c237d
JB		 1414 /*
1415 * Sinks are *supposed* to come up within 1ms from an off state,
1416 * but we're also supposed to retry 3 times per the spec.
1417 */
61da5fab 1418 for (i = 0; i < 3; i++) {
df0c237d
JB		 1419 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1420 recv_bytes);
1421 if (ret == recv_bytes)
61da5fab
JB		 1422 return true;
1423 msleep(1);
1424 }
a4fc5ed6 1425
61da5fab 1426 return false;
a4fc5ed6
KP		 1427}
1428
1429/*
1430 * Fetch AUX CH registers 0x202 - 0x207 which contain
1431 * link status information
1432 */
1433static bool
93f62dad 1434intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1435{
df0c237d
JB		 1436 return intel_dp_aux_native_read_retry(intel_dp,
1437 DP_LANE0_1_STATUS,
93f62dad 1438 link_status,
df0c237d 1439 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1440}
1441
a4fc5ed6
KP		 1442#if 0
1443static char *voltage_names[] = {
1444 "0.4V", "0.6V", "0.8V", "1.2V"
1445};
1446static char *pre_emph_names[] = {
1447 "0dB", "3.5dB", "6dB", "9.5dB"
1448};
1449static char *link_train_names[] = {
1450 "pattern 1", "pattern 2", "idle", "off"
1451};
1452#endif
1453
1454/*
1455 * These are source-specific values; current Intel hardware supports
1456 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1457 */
a4fc5ed6
KP		 1458
1459static uint8_t
1a2eb460 1460intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1461{
30add22d 1462 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1463
e2fa6fba
P		 1464 if (IS_VALLEYVIEW(dev))
1465 return DP_TRAIN_VOLTAGE_SWING_1200;
1466 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1a2eb460
KP		 1467 return DP_TRAIN_VOLTAGE_SWING_800;
1468 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1469 return DP_TRAIN_VOLTAGE_SWING_1200;
1470 else
1471 return DP_TRAIN_VOLTAGE_SWING_800;
1472}
1473
1474static uint8_t
1475intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1476{
30add22d 1477 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1478
22b8bf17 1479 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1480 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1481 case DP_TRAIN_VOLTAGE_SWING_400:
1482 return DP_TRAIN_PRE_EMPHASIS_9_5;
1483 case DP_TRAIN_VOLTAGE_SWING_600:
1484 return DP_TRAIN_PRE_EMPHASIS_6;
1485 case DP_TRAIN_VOLTAGE_SWING_800:
1486 return DP_TRAIN_PRE_EMPHASIS_3_5;
1487 case DP_TRAIN_VOLTAGE_SWING_1200:
1488 default:
1489 return DP_TRAIN_PRE_EMPHASIS_0;
1490 }
e2fa6fba
P		 1491 } else if (IS_VALLEYVIEW(dev)) {
1492 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1493 case DP_TRAIN_VOLTAGE_SWING_400:
1494 return DP_TRAIN_PRE_EMPHASIS_9_5;
1495 case DP_TRAIN_VOLTAGE_SWING_600:
1496 return DP_TRAIN_PRE_EMPHASIS_6;
1497 case DP_TRAIN_VOLTAGE_SWING_800:
1498 return DP_TRAIN_PRE_EMPHASIS_3_5;
1499 case DP_TRAIN_VOLTAGE_SWING_1200:
1500 default:
1501 return DP_TRAIN_PRE_EMPHASIS_0;
1502 }
1503 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1a2eb460
KP		 1504 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1505 case DP_TRAIN_VOLTAGE_SWING_400:
1506 return DP_TRAIN_PRE_EMPHASIS_6;
1507 case DP_TRAIN_VOLTAGE_SWING_600:
1508 case DP_TRAIN_VOLTAGE_SWING_800:
1509 return DP_TRAIN_PRE_EMPHASIS_3_5;
1510 default:
1511 return DP_TRAIN_PRE_EMPHASIS_0;
1512 }
1513 } else {
1514 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1515 case DP_TRAIN_VOLTAGE_SWING_400:
1516 return DP_TRAIN_PRE_EMPHASIS_6;
1517 case DP_TRAIN_VOLTAGE_SWING_600:
1518 return DP_TRAIN_PRE_EMPHASIS_6;
1519 case DP_TRAIN_VOLTAGE_SWING_800:
1520 return DP_TRAIN_PRE_EMPHASIS_3_5;
1521 case DP_TRAIN_VOLTAGE_SWING_1200:
1522 default:
1523 return DP_TRAIN_PRE_EMPHASIS_0;
1524 }
a4fc5ed6
KP		 1525 }
1526}
1527
e2fa6fba
P		 1528static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1529{
1530 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1533 unsigned long demph_reg_value, preemph_reg_value,
1534 uniqtranscale_reg_value;
1535 uint8_t train_set = intel_dp->train_set[0];
1536 int port;
1537
1538 if (dport->port == PORT_B)
1539 port = 0;
1540 else if (dport->port == PORT_C)
1541 port = 1;
1542 else
1543 BUG();
1544
1545 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1546 case DP_TRAIN_PRE_EMPHASIS_0:
1547 preemph_reg_value = 0x0004000;
1548 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1549 case DP_TRAIN_VOLTAGE_SWING_400:
1550 demph_reg_value = 0x2B405555;
1551 uniqtranscale_reg_value = 0x552AB83A;
1552 break;
1553 case DP_TRAIN_VOLTAGE_SWING_600:
1554 demph_reg_value = 0x2B404040;
1555 uniqtranscale_reg_value = 0x5548B83A;
1556 break;
1557 case DP_TRAIN_VOLTAGE_SWING_800:
1558 demph_reg_value = 0x2B245555;
1559 uniqtranscale_reg_value = 0x5560B83A;
1560 break;
1561 case DP_TRAIN_VOLTAGE_SWING_1200:
1562 demph_reg_value = 0x2B405555;
1563 uniqtranscale_reg_value = 0x5598DA3A;
1564 break;
1565 default:
1566 return 0;
1567 }
1568 break;
1569 case DP_TRAIN_PRE_EMPHASIS_3_5:
1570 preemph_reg_value = 0x0002000;
1571 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1572 case DP_TRAIN_VOLTAGE_SWING_400:
1573 demph_reg_value = 0x2B404040;
1574 uniqtranscale_reg_value = 0x5552B83A;
1575 break;
1576 case DP_TRAIN_VOLTAGE_SWING_600:
1577 demph_reg_value = 0x2B404848;
1578 uniqtranscale_reg_value = 0x5580B83A;
1579 break;
1580 case DP_TRAIN_VOLTAGE_SWING_800:
1581 demph_reg_value = 0x2B404040;
1582 uniqtranscale_reg_value = 0x55ADDA3A;
1583 break;
1584 default:
1585 return 0;
1586 }
1587 break;
1588 case DP_TRAIN_PRE_EMPHASIS_6:
1589 preemph_reg_value = 0x0000000;
1590 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1591 case DP_TRAIN_VOLTAGE_SWING_400:
1592 demph_reg_value = 0x2B305555;
1593 uniqtranscale_reg_value = 0x5570B83A;
1594 break;
1595 case DP_TRAIN_VOLTAGE_SWING_600:
1596 demph_reg_value = 0x2B2B4040;
1597 uniqtranscale_reg_value = 0x55ADDA3A;
1598 break;
1599 default:
1600 return 0;
1601 }
1602 break;
1603 case DP_TRAIN_PRE_EMPHASIS_9_5:
1604 preemph_reg_value = 0x0006000;
1605 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1606 case DP_TRAIN_VOLTAGE_SWING_400:
1607 demph_reg_value = 0x1B405555;
1608 uniqtranscale_reg_value = 0x55ADDA3A;
1609 break;
1610 default:
1611 return 0;
1612 }
1613 break;
1614 default:
1615 return 0;
1616 }
1617
1618 /* eDP is only on port C */
1619 mutex_lock(&dev_priv->dpio_lock);
1620 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1621 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1622 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1623 uniqtranscale_reg_value);
1624 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1625 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1626 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1627 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1628 mutex_unlock(&dev_priv->dpio_lock);
1629
1630 return 0;
1631}
1632
a4fc5ed6 1633static void
93f62dad 1634intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1635{
1636 uint8_t v = 0;
1637 uint8_t p = 0;
1638 int lane;
1a2eb460
KP		 1639 uint8_t voltage_max;
1640 uint8_t preemph_max;
a4fc5ed6 1641
33a34e4e 1642 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1643 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1644 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1645
1646 if (this_v > v)
1647 v = this_v;
1648 if (this_p > p)
1649 p = this_p;
1650 }
1651
1a2eb460 1652 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1653 if (v >= voltage_max)
1654 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1655
1a2eb460
KP		 1656 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1657 if (p >= preemph_max)
1658 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1659
1660 for (lane = 0; lane < 4; lane++)
33a34e4e 1661 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1662}
1663
1664static uint32_t
f0a3424e 1665intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1666{
3cf2efb1 1667 uint32_t signal_levels = 0;
a4fc5ed6 1668
3cf2efb1 1669 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1670 case DP_TRAIN_VOLTAGE_SWING_400:
1671 default:
1672 signal_levels |= DP_VOLTAGE_0_4;
1673 break;
1674 case DP_TRAIN_VOLTAGE_SWING_600:
1675 signal_levels |= DP_VOLTAGE_0_6;
1676 break;
1677 case DP_TRAIN_VOLTAGE_SWING_800:
1678 signal_levels |= DP_VOLTAGE_0_8;
1679 break;
1680 case DP_TRAIN_VOLTAGE_SWING_1200:
1681 signal_levels |= DP_VOLTAGE_1_2;
1682 break;
1683 }
3cf2efb1 1684 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1685 case DP_TRAIN_PRE_EMPHASIS_0:
1686 default:
1687 signal_levels |= DP_PRE_EMPHASIS_0;
1688 break;
1689 case DP_TRAIN_PRE_EMPHASIS_3_5:
1690 signal_levels |= DP_PRE_EMPHASIS_3_5;
1691 break;
1692 case DP_TRAIN_PRE_EMPHASIS_6:
1693 signal_levels |= DP_PRE_EMPHASIS_6;
1694 break;
1695 case DP_TRAIN_PRE_EMPHASIS_9_5:
1696 signal_levels |= DP_PRE_EMPHASIS_9_5;
1697 break;
1698 }
1699 return signal_levels;
1700}
1701
e3421a18
ZW		 1702/* Gen6's DP voltage swing and pre-emphasis control */
1703static uint32_t
1704intel_gen6_edp_signal_levels(uint8_t train_set)
1705{
3c5a62b5
YL		 1706 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1707 DP_TRAIN_PRE_EMPHASIS_MASK);
1708 switch (signal_levels) {
e3421a18 1709 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1710 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1711 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1712 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1713 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1714 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1715 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1716 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1717 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1718 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1719 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1720 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1721 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1722 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1723 default:
3c5a62b5
YL		 1724 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1725 "0x%x\n", signal_levels);
1726 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1727 }
1728}
1729
1a2eb460
KP		 1730/* Gen7's DP voltage swing and pre-emphasis control */
1731static uint32_t
1732intel_gen7_edp_signal_levels(uint8_t train_set)
1733{
1734 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1735 DP_TRAIN_PRE_EMPHASIS_MASK);
1736 switch (signal_levels) {
1737 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1738 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1739 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1740 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1741 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1742 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1743
1744 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1745 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1746 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1747 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1748
1749 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1750 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1751 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1752 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1753
1754 default:
1755 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1756 "0x%x\n", signal_levels);
1757 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1758 }
1759}
1760
d6c0d722
PZ		 1761/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1762static uint32_t
f0a3424e 1763intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1764{
d6c0d722
PZ		 1765 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1766 DP_TRAIN_PRE_EMPHASIS_MASK);
1767 switch (signal_levels) {
1768 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1769 return DDI_BUF_EMP_400MV_0DB_HSW;
1770 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1771 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1772 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1773 return DDI_BUF_EMP_400MV_6DB_HSW;
1774 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1775 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1776
d6c0d722
PZ		 1777 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1778 return DDI_BUF_EMP_600MV_0DB_HSW;
1779 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1780 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1781 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1782 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1783
d6c0d722
PZ		 1784 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1785 return DDI_BUF_EMP_800MV_0DB_HSW;
1786 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1787 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1788 default:
1789 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1790 "0x%x\n", signal_levels);
1791 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1792 }
a4fc5ed6
KP		 1793}
1794
f0a3424e
PZ		 1795/* Properly updates "DP" with the correct signal levels. */
1796static void
1797intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1798{
1799 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1800 struct drm_device *dev = intel_dig_port->base.base.dev;
1801 uint32_t signal_levels, mask;
1802 uint8_t train_set = intel_dp->train_set[0];
1803
22b8bf17 1804 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1805 signal_levels = intel_hsw_signal_levels(train_set);
1806 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 1807 } else if (IS_VALLEYVIEW(dev)) {
1808 signal_levels = intel_vlv_signal_levels(intel_dp);
1809 mask = 0;
1810 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
f0a3424e
PZ		 1811 signal_levels = intel_gen7_edp_signal_levels(train_set);
1812 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1813 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1814 signal_levels = intel_gen6_edp_signal_levels(train_set);
1815 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1816 } else {
1817 signal_levels = intel_gen4_signal_levels(train_set);
1818 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1819 }
1820
1821 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1822
1823 *DP = (*DP & ~mask) | signal_levels;
1824}
1825
a4fc5ed6 1826static bool
ea5b213a 1827intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1828 uint32_t dp_reg_value,
58e10eb9 1829 uint8_t dp_train_pat)
a4fc5ed6 1830{
174edf1f
PZ		 1831 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1832 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1833 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1834 enum port port = intel_dig_port->port;
a4fc5ed6 1835 int ret;
d6c0d722 1836 uint32_t temp;
a4fc5ed6 1837
22b8bf17 1838 if (HAS_DDI(dev)) {
174edf1f 1839 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1840
1841 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1842 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1843 else
1844 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1845
1846 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1847 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1848 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1849
10aa17c8
PZ		 1850 if (port != PORT_A) {
1851 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1852 I915_WRITE(DP_TP_CTL(port), temp);
1853
1854 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1855 DP_TP_STATUS_IDLE_DONE), 1))
1856 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1857
1858 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1859 }
d6c0d722 1860
d6c0d722
PZ		 1861 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1862
1863 break;
1864 case DP_TRAINING_PATTERN_1:
1865 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1866 break;
1867 case DP_TRAINING_PATTERN_2:
1868 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1869 break;
1870 case DP_TRAINING_PATTERN_3:
1871 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1872 break;
1873 }
174edf1f 1874 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1875
1876 } else if (HAS_PCH_CPT(dev) &&
1877 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1878 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1879
1880 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1881 case DP_TRAINING_PATTERN_DISABLE:
1882 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1883 break;
1884 case DP_TRAINING_PATTERN_1:
1885 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1886 break;
1887 case DP_TRAINING_PATTERN_2:
1888 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1889 break;
1890 case DP_TRAINING_PATTERN_3:
1891 DRM_ERROR("DP training pattern 3 not supported\n");
1892 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1893 break;
1894 }
1895
1896 } else {
1897 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1898
1899 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1900 case DP_TRAINING_PATTERN_DISABLE:
1901 dp_reg_value |= DP_LINK_TRAIN_OFF;
1902 break;
1903 case DP_TRAINING_PATTERN_1:
1904 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1905 break;
1906 case DP_TRAINING_PATTERN_2:
1907 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1908 break;
1909 case DP_TRAINING_PATTERN_3:
1910 DRM_ERROR("DP training pattern 3 not supported\n");
1911 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1912 break;
1913 }
1914 }
1915
ea5b213a
CW		 1916 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1917 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1918
ea5b213a 1919 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1920 DP_TRAINING_PATTERN_SET,
1921 dp_train_pat);
1922
47ea7542
PZ		 1923 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1924 DP_TRAINING_PATTERN_DISABLE) {
1925 ret = intel_dp_aux_native_write(intel_dp,
1926 DP_TRAINING_LANE0_SET,
1927 intel_dp->train_set,
1928 intel_dp->lane_count);
1929 if (ret != intel_dp->lane_count)
1930 return false;
1931 }
a4fc5ed6
KP		 1932
1933 return true;
1934}
1935
33a34e4e 1936/* Enable corresponding port and start training pattern 1 */
c19b0669 1937void
33a34e4e 1938intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1939{
da63a9f2 1940 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1941 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1942 int i;
1943 uint8_t voltage;
1944 bool clock_recovery = false;
cdb0e95b 1945 int voltage_tries, loop_tries;
ea5b213a 1946 uint32_t DP = intel_dp->DP;
a4fc5ed6 1947
affa9354 1948 if (HAS_DDI(dev))
c19b0669
PZ		 1949 intel_ddi_prepare_link_retrain(encoder);
1950
3cf2efb1
CW		 1951 /* Write the link configuration data */
1952 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1953 intel_dp->link_configuration,
1954 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1955
1956 DP |= DP_PORT_EN;
1a2eb460 1957
33a34e4e 1958 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1959 voltage = 0xff;
cdb0e95b
KP		 1960 voltage_tries = 0;
1961 loop_tries = 0;
a4fc5ed6
KP		 1962 clock_recovery = false;
1963 for (;;) {
33a34e4e 1964 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1965 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1966
1967 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1968
a7c9655f 1969 /* Set training pattern 1 */
47ea7542 1970 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1971 DP_TRAINING_PATTERN_1 |
1972 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1973 break;
a4fc5ed6 1974
a7c9655f 1975 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1976 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1977 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1978 break;
93f62dad 1979 }
a4fc5ed6 1980
01916270 1981 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1982 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1983 clock_recovery = true;
1984 break;
1985 }
1986
1987 /* Check to see if we've tried the max voltage */
1988 for (i = 0; i < intel_dp->lane_count; i++)
1989 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1990 break;
3b4f819d 1991 if (i == intel_dp->lane_count) {
b06fbda3
DV		 1992 ++loop_tries;
1993 if (loop_tries == 5) {
cdb0e95b
KP		 1994 DRM_DEBUG_KMS("too many full retries, give up\n");
1995 break;
1996 }
1997 memset(intel_dp->train_set, 0, 4);
1998 voltage_tries = 0;
1999 continue;
2000 }
a4fc5ed6 2001
3cf2efb1 2002 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2003 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2004 ++voltage_tries;
b06fbda3
DV		 2005 if (voltage_tries == 5) {
2006 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2007 break;
2008 }
2009 } else
2010 voltage_tries = 0;
2011 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2012
3cf2efb1 2013 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2014 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2015 }
2016
33a34e4e
JB		 2017 intel_dp->DP = DP;
2018}
2019
c19b0669 2020void
33a34e4e
JB		 2021intel_dp_complete_link_train(struct intel_dp *intel_dp)
2022{
33a34e4e 2023 bool channel_eq = false;
37f80975 2024 int tries, cr_tries;
33a34e4e
JB		 2025 uint32_t DP = intel_dp->DP;
2026
a4fc5ed6
KP		 2027 /* channel equalization */
2028 tries = 0;
37f80975 2029 cr_tries = 0;
a4fc5ed6
KP		 2030 channel_eq = false;
2031 for (;;) {
93f62dad 2032 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2033
37f80975
JB		 2034 if (cr_tries > 5) {
2035 DRM_ERROR("failed to train DP, aborting\n");
2036 intel_dp_link_down(intel_dp);
2037 break;
2038 }
2039
f0a3424e 2040 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2041
a4fc5ed6 2042 /* channel eq pattern */
47ea7542 2043 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2044 DP_TRAINING_PATTERN_2 |
2045 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2046 break;
2047
a7c9655f 2048 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2049 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2050 break;
a4fc5ed6 2051
37f80975 2052 /* Make sure clock is still ok */
01916270 2053 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2054 intel_dp_start_link_train(intel_dp);
2055 cr_tries++;
2056 continue;
2057 }
2058
1ffdff13 2059 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2060 channel_eq = true;
2061 break;
2062 }
a4fc5ed6 2063
37f80975
JB		 2064 /* Try 5 times, then try clock recovery if that fails */
2065 if (tries > 5) {
2066 intel_dp_link_down(intel_dp);
2067 intel_dp_start_link_train(intel_dp);
2068 tries = 0;
2069 cr_tries++;
2070 continue;
2071 }
a4fc5ed6 2072
3cf2efb1 2073 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2074 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2075 ++tries;
869184a6 2076 }
3cf2efb1 2077
d6c0d722
PZ		 2078 if (channel_eq)
2079 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2080
47ea7542 2081 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2082}
2083
2084static void
ea5b213a 2085intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2086{
da63a9f2
PZ		 2087 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2088 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2089 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2090 struct intel_crtc *intel_crtc =
2091 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2092 uint32_t DP = intel_dp->DP;
a4fc5ed6 2093
c19b0669
PZ		 2094 /*
2095 * DDI code has a strict mode set sequence and we should try to respect
2096 * it, otherwise we might hang the machine in many different ways. So we
2097 * really should be disabling the port only on a complete crtc_disable
2098 * sequence. This function is just called under two conditions on DDI
2099 * code:
2100 * - Link train failed while doing crtc_enable, and on this case we
2101 * really should respect the mode set sequence and wait for a
2102 * crtc_disable.
2103 * - Someone turned the monitor off and intel_dp_check_link_status
2104 * called us. We don't need to disable the whole port on this case, so
2105 * when someone turns the monitor on again,
2106 * intel_ddi_prepare_link_retrain will take care of redoing the link
2107 * train.
2108 */
affa9354 2109 if (HAS_DDI(dev))
c19b0669
PZ		 2110 return;
2111
0c33d8d7 2112 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2113 return;
2114
28c97730 2115 DRM_DEBUG_KMS("\n");
32f9d658 2116
1a2eb460 2117 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2118 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2119 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2120 } else {
2121 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2122 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2123 }
fe255d00 2124 POSTING_READ(intel_dp->output_reg);
5eb08b69 2125
ab527efc
DV		 2126 /* We don't really know why we're doing this */
2127 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2128
493a7081 2129 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2130 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2131 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2132
5bddd17f
EA		 2133 /* Hardware workaround: leaving our transcoder select
2134 * set to transcoder B while it's off will prevent the
2135 * corresponding HDMI output on transcoder A.
2136 *
2137 * Combine this with another hardware workaround:
2138 * transcoder select bit can only be cleared while the
2139 * port is enabled.
2140 */
2141 DP &= ~DP_PIPEB_SELECT;
2142 I915_WRITE(intel_dp->output_reg, DP);
2143
2144 /* Changes to enable or select take place the vblank
2145 * after being written.
2146 */
ff50afe9
DV		 2147 if (WARN_ON(crtc == NULL)) {
2148 /* We should never try to disable a port without a crtc
2149 * attached. For paranoia keep the code around for a
2150 * bit. */
31acbcc4
CW		 2151 POSTING_READ(intel_dp->output_reg);
2152 msleep(50);
2153 } else
ab527efc 2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2155 }
2156
832afda6 2157 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2158 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2159 POSTING_READ(intel_dp->output_reg);
f01eca2e 2160 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2161}
2162
26d61aad
KP		 2163static bool
2164intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2165{
577c7a50
DL		 2166 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2167
92fd8fd1 2168 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2169 sizeof(intel_dp->dpcd)) == 0)
2170 return false; /* aux transfer failed */
92fd8fd1 2171
577c7a50
DL		 2172 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2173 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2174 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2175
edb39244
AJ		 2176 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2177 return false; /* DPCD not present */
2178
2179 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2180 DP_DWN_STRM_PORT_PRESENT))
2181 return true; /* native DP sink */
2182
2183 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2184 return true; /* no per-port downstream info */
2185
2186 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2187 intel_dp->downstream_ports,
2188 DP_MAX_DOWNSTREAM_PORTS) == 0)
2189 return false; /* downstream port status fetch failed */
2190
2191 return true;
92fd8fd1
KP		 2192}
2193
0d198328
AJ		 2194static void
2195intel_dp_probe_oui(struct intel_dp *intel_dp)
2196{
2197 u8 buf[3];
2198
2199 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2200 return;
2201
351cfc34
DV		 2202 ironlake_edp_panel_vdd_on(intel_dp);
2203
0d198328
AJ		 2204 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2205 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2206 buf[0], buf[1], buf[2]);
2207
2208 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2209 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2210 buf[0], buf[1], buf[2]);
351cfc34
DV		 2211
2212 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2213}
2214
a60f0e38
JB		 2215static bool
2216intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2217{
2218 int ret;
2219
2220 ret = intel_dp_aux_native_read_retry(intel_dp,
2221 DP_DEVICE_SERVICE_IRQ_VECTOR,
2222 sink_irq_vector, 1);
2223 if (!ret)
2224 return false;
2225
2226 return true;
2227}
2228
2229static void
2230intel_dp_handle_test_request(struct intel_dp *intel_dp)
2231{
2232 /* NAK by default */
9324cf7f 2233 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2234}
2235
a4fc5ed6
KP		 2236/*
2237 * According to DP spec
2238 * 5.1.2:
2239 * 1. Read DPCD
2240 * 2. Configure link according to Receiver Capabilities
2241 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2242 * 4. Check link status on receipt of hot-plug interrupt
2243 */
2244
00c09d70 2245void
ea5b213a 2246intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2247{
da63a9f2 2248 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2249 u8 sink_irq_vector;
93f62dad 2250 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2251
da63a9f2 2252 if (!intel_encoder->connectors_active)
d2b996ac 2253 return;
59cd09e1 2254
da63a9f2 2255 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2256 return;
2257
92fd8fd1 2258 /* Try to read receiver status if the link appears to be up */
93f62dad 2259 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2260 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2261 return;
2262 }
2263
92fd8fd1 2264 /* Now read the DPCD to see if it's actually running */
26d61aad 2265 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2266 intel_dp_link_down(intel_dp);
2267 return;
2268 }
2269
a60f0e38
JB		 2270 /* Try to read the source of the interrupt */
2271 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2272 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2273 /* Clear interrupt source */
2274 intel_dp_aux_native_write_1(intel_dp,
2275 DP_DEVICE_SERVICE_IRQ_VECTOR,
2276 sink_irq_vector);
2277
2278 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2279 intel_dp_handle_test_request(intel_dp);
2280 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2281 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2282 }
2283
1ffdff13 2284 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2285 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2286 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2287 intel_dp_start_link_train(intel_dp);
2288 intel_dp_complete_link_train(intel_dp);
2289 }
a4fc5ed6 2290}
a4fc5ed6 2291
caf9ab24 2292/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2293static enum drm_connector_status
26d61aad 2294intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2295{
caf9ab24
AJ		 2296 uint8_t *dpcd = intel_dp->dpcd;
2297 bool hpd;
2298 uint8_t type;
2299
2300 if (!intel_dp_get_dpcd(intel_dp))
2301 return connector_status_disconnected;
2302
2303 /* if there's no downstream port, we're done */
2304 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2305 return connector_status_connected;
caf9ab24
AJ		 2306
2307 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2308 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2309 if (hpd) {
23235177 2310 uint8_t reg;
caf9ab24 2311 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2312 &reg, 1))
caf9ab24 2313 return connector_status_unknown;
23235177
AJ		 2314 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2315 : connector_status_disconnected;
caf9ab24
AJ		 2316 }
2317
2318 /* If no HPD, poke DDC gently */
2319 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2320 return connector_status_connected;
caf9ab24
AJ		 2321
2322 /* Well we tried, say unknown for unreliable port types */
2323 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2324 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2325 return connector_status_unknown;
2326
2327 /* Anything else is out of spec, warn and ignore */
2328 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2329 return connector_status_disconnected;
71ba9000
AJ		 2330}
2331
5eb08b69 2332static enum drm_connector_status
a9756bb5 2333ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2334{
30add22d 2335 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2338 enum drm_connector_status status;
2339
fe16d949
CW		 2340 /* Can't disconnect eDP, but you can close the lid... */
2341 if (is_edp(intel_dp)) {
30add22d 2342 status = intel_panel_detect(dev);
fe16d949
CW		 2343 if (status == connector_status_unknown)
2344 status = connector_status_connected;
2345 return status;
2346 }
01cb9ea6 2347
1b469639
DL		 2348 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2349 return connector_status_disconnected;
2350
26d61aad 2351 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2352}
2353
a4fc5ed6 2354static enum drm_connector_status
a9756bb5 2355g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2356{
30add22d 2357 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2358 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2359 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2360 uint32_t bit;
5eb08b69 2361
35aad75f
JB		 2362 /* Can't disconnect eDP, but you can close the lid... */
2363 if (is_edp(intel_dp)) {
2364 enum drm_connector_status status;
2365
2366 status = intel_panel_detect(dev);
2367 if (status == connector_status_unknown)
2368 status = connector_status_connected;
2369 return status;
2370 }
2371
34f2be46
VS		 2372 switch (intel_dig_port->port) {
2373 case PORT_B:
26739f12 2374 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2375 break;
34f2be46 2376 case PORT_C:
26739f12 2377 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2378 break;
34f2be46 2379 case PORT_D:
26739f12 2380 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2381 break;
2382 default:
2383 return connector_status_unknown;
2384 }
2385
10f76a38 2386 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2387 return connector_status_disconnected;
2388
26d61aad 2389 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2390}
2391
8c241fef
KP		 2392static struct edid *
2393intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2394{
9cd300e0 2395 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2396
9cd300e0
JN		 2397 /* use cached edid if we have one */
2398 if (intel_connector->edid) {
2399 struct edid *edid;
2400 int size;
2401
2402 /* invalid edid */
2403 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2404 return NULL;
2405
9cd300e0 2406 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2407 edid = kmalloc(size, GFP_KERNEL);
2408 if (!edid)
2409 return NULL;
2410
9cd300e0 2411 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2412 return edid;
2413 }
8c241fef 2414
9cd300e0 2415 return drm_get_edid(connector, adapter);
8c241fef
KP		 2416}
2417
2418static int
2419intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2420{
9cd300e0 2421 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2422
9cd300e0
JN		 2423 /* use cached edid if we have one */
2424 if (intel_connector->edid) {
2425 /* invalid edid */
2426 if (IS_ERR(intel_connector->edid))
2427 return 0;
2428
2429 return intel_connector_update_modes(connector,
2430 intel_connector->edid);
d6f24d0f
JB		 2431 }
2432
9cd300e0 2433 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2434}
2435
a9756bb5
ZW		 2436static enum drm_connector_status
2437intel_dp_detect(struct drm_connector *connector, bool force)
2438{
2439 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2440 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2441 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2442 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2443 enum drm_connector_status status;
2444 struct edid *edid = NULL;
2445
2446 intel_dp->has_audio = false;
2447
2448 if (HAS_PCH_SPLIT(dev))
2449 status = ironlake_dp_detect(intel_dp);
2450 else
2451 status = g4x_dp_detect(intel_dp);
1b9be9d0 2452
a9756bb5
ZW		 2453 if (status != connector_status_connected)
2454 return status;
2455
0d198328
AJ		 2456 intel_dp_probe_oui(intel_dp);
2457
c3e5f67b
DV		 2458 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2459 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2460 } else {
8c241fef 2461 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2462 if (edid) {
2463 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2464 kfree(edid);
2465 }
a9756bb5
ZW		 2466 }
2467
d63885da
PZ		 2468 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2469 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2470 return connector_status_connected;
a4fc5ed6
KP		 2471}
2472
2473static int intel_dp_get_modes(struct drm_connector *connector)
2474{
df0e9248 2475 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2476 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2477 struct drm_device *dev = connector->dev;
32f9d658 2478 int ret;
a4fc5ed6
KP		 2479
2480 /* We should parse the EDID data and find out if it has an audio sink
2481 */
2482
8c241fef 2483 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2484 if (ret)
32f9d658
ZW		 2485 return ret;
2486
f8779fda 2487 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2488 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2489 struct drm_display_mode *mode;
dd06f90e
JN		 2490 mode = drm_mode_duplicate(dev,
2491 intel_connector->panel.fixed_mode);
f8779fda 2492 if (mode) {
32f9d658
ZW		 2493 drm_mode_probed_add(connector, mode);
2494 return 1;
2495 }
2496 }
2497 return 0;
a4fc5ed6
KP		 2498}
2499
1aad7ac0
CW		 2500static bool
2501intel_dp_detect_audio(struct drm_connector *connector)
2502{
2503 struct intel_dp *intel_dp = intel_attached_dp(connector);
2504 struct edid *edid;
2505 bool has_audio = false;
2506
8c241fef 2507 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2508 if (edid) {
2509 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2510 kfree(edid);
2511 }
2512
2513 return has_audio;
2514}
2515
f684960e
CW		 2516static int
2517intel_dp_set_property(struct drm_connector *connector,
2518 struct drm_property *property,
2519 uint64_t val)
2520{
e953fd7b 2521 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2522 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2523 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2524 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2525 int ret;
2526
662595df 2527 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2528 if (ret)
2529 return ret;
2530
3f43c48d 2531 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2532 int i = val;
2533 bool has_audio;
2534
2535 if (i == intel_dp->force_audio)
f684960e
CW		 2536 return 0;
2537
1aad7ac0 2538 intel_dp->force_audio = i;
f684960e 2539
c3e5f67b 2540 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2541 has_audio = intel_dp_detect_audio(connector);
2542 else
c3e5f67b 2543 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2544
2545 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2546 return 0;
2547
1aad7ac0 2548 intel_dp->has_audio = has_audio;
f684960e
CW		 2549 goto done;
2550 }
2551
e953fd7b 2552 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2553 switch (val) {
2554 case INTEL_BROADCAST_RGB_AUTO:
2555 intel_dp->color_range_auto = true;
2556 break;
2557 case INTEL_BROADCAST_RGB_FULL:
2558 intel_dp->color_range_auto = false;
2559 intel_dp->color_range = 0;
2560 break;
2561 case INTEL_BROADCAST_RGB_LIMITED:
2562 intel_dp->color_range_auto = false;
2563 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2564 break;
2565 default:
2566 return -EINVAL;
2567 }
e953fd7b
CW		 2568 goto done;
2569 }
2570
53b41837
YN		 2571 if (is_edp(intel_dp) &&
2572 property == connector->dev->mode_config.scaling_mode_property) {
2573 if (val == DRM_MODE_SCALE_NONE) {
2574 DRM_DEBUG_KMS("no scaling not supported\n");
2575 return -EINVAL;
2576 }
2577
2578 if (intel_connector->panel.fitting_mode == val) {
2579 /* the eDP scaling property is not changed */
2580 return 0;
2581 }
2582 intel_connector->panel.fitting_mode = val;
2583
2584 goto done;
2585 }
2586
f684960e
CW		 2587 return -EINVAL;
2588
2589done:
c0c36b94
CW		 2590 if (intel_encoder->base.crtc)
2591 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2592
2593 return 0;
2594}
2595
a4fc5ed6 2596static void
0206e353 2597intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2598{
be3cd5e3 2599 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2600 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2601
9cd300e0
JN		 2602 if (!IS_ERR_OR_NULL(intel_connector->edid))
2603 kfree(intel_connector->edid);
2604
dc652f90 2605 if (is_edp(intel_dp))
1d508706 2606 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2607
a4fc5ed6
KP		 2608 drm_sysfs_connector_remove(connector);
2609 drm_connector_cleanup(connector);
55f78c43 2610 kfree(connector);
a4fc5ed6
KP		 2611}
2612
00c09d70 2613void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2614{
da63a9f2
PZ		 2615 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2616 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2617
2618 i2c_del_adapter(&intel_dp->adapter);
2619 drm_encoder_cleanup(encoder);
bd943159
KP		 2620 if (is_edp(intel_dp)) {
2621 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2622 ironlake_panel_vdd_off_sync(intel_dp);
2623 }
da63a9f2 2624 kfree(intel_dig_port);
24d05927
DV		 2625}
2626
a4fc5ed6 2627static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2628 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2629};
2630
2631static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2632 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2633 .detect = intel_dp_detect,
2634 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2635 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2636 .destroy = intel_dp_destroy,
2637};
2638
2639static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2640 .get_modes = intel_dp_get_modes,
2641 .mode_valid = intel_dp_mode_valid,
df0e9248 2642 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2643};
2644
a4fc5ed6 2645static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2646 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2647};
2648
995b6762 2649static void
21d40d37 2650intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2651{
fa90ecef 2652 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2653
885a5014 2654 intel_dp_check_link_status(intel_dp);
c8110e52 2655}
6207937d 2656
e3421a18
ZW		 2657/* Return which DP Port should be selected for Transcoder DP control */
2658int
0206e353 2659intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2660{
2661 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2662 struct intel_encoder *intel_encoder;
2663 struct intel_dp *intel_dp;
e3421a18 2664
fa90ecef
PZ		 2665 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2666 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2667
fa90ecef
PZ		 2668 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2669 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2670 return intel_dp->output_reg;
e3421a18 2671 }
ea5b213a 2672
e3421a18
ZW		 2673 return -1;
2674}
2675
36e83a18 2676/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2677bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2678{
2679 struct drm_i915_private *dev_priv = dev->dev_private;
2680 struct child_device_config *p_child;
2681 int i;
2682
2683 if (!dev_priv->child_dev_num)
2684 return false;
2685
2686 for (i = 0; i < dev_priv->child_dev_num; i++) {
2687 p_child = dev_priv->child_dev + i;
2688
2689 if (p_child->dvo_port == PORT_IDPD &&
2690 p_child->device_type == DEVICE_TYPE_eDP)
2691 return true;
2692 }
2693 return false;
2694}
2695
f684960e
CW		 2696static void
2697intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2698{
53b41837
YN		 2699 struct intel_connector *intel_connector = to_intel_connector(connector);
2700
3f43c48d 2701 intel_attach_force_audio_property(connector);
e953fd7b 2702 intel_attach_broadcast_rgb_property(connector);
55bc60db 2703 intel_dp->color_range_auto = true;
53b41837
YN		 2704
2705 if (is_edp(intel_dp)) {
2706 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2707 drm_object_attach_property(
2708 &connector->base,
53b41837 2709 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2710 DRM_MODE_SCALE_ASPECT);
2711 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2712 }
f684960e
CW		 2713}
2714
67a54566
DV		 2715static void
2716intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2717 struct intel_dp *intel_dp,
2718 struct edp_power_seq *out)
67a54566
DV		 2719{
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct edp_power_seq cur, vbt, spec, final;
2722 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2723 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2724
2725 if (HAS_PCH_SPLIT(dev)) {
2726 pp_control_reg = PCH_PP_CONTROL;
2727 pp_on_reg = PCH_PP_ON_DELAYS;
2728 pp_off_reg = PCH_PP_OFF_DELAYS;
2729 pp_div_reg = PCH_PP_DIVISOR;
2730 } else {
2731 pp_control_reg = PIPEA_PP_CONTROL;
2732 pp_on_reg = PIPEA_PP_ON_DELAYS;
2733 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2734 pp_div_reg = PIPEA_PP_DIVISOR;
2735 }
67a54566
DV		 2736
2737 /* Workaround: Need to write PP_CONTROL with the unlock key as
2738 * the very first thing. */
453c5420
JB		 2739 pp = ironlake_get_pp_control(intel_dp);
2740 I915_WRITE(pp_control_reg, pp);
67a54566 2741
453c5420
JB		 2742 pp_on = I915_READ(pp_on_reg);
2743 pp_off = I915_READ(pp_off_reg);
2744 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2745
2746 /* Pull timing values out of registers */
2747 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2748 PANEL_POWER_UP_DELAY_SHIFT;
2749
2750 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2751 PANEL_LIGHT_ON_DELAY_SHIFT;
2752
2753 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2754 PANEL_LIGHT_OFF_DELAY_SHIFT;
2755
2756 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2757 PANEL_POWER_DOWN_DELAY_SHIFT;
2758
2759 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2760 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2761
2762 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2763 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2764
2765 vbt = dev_priv->edp.pps;
2766
2767 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2768 * our hw here, which are all in 100usec. */
2769 spec.t1_t3 = 210 * 10;
2770 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2771 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2772 spec.t10 = 500 * 10;
2773 /* This one is special and actually in units of 100ms, but zero
2774 * based in the hw (so we need to add 100 ms). But the sw vbt
2775 * table multiplies it with 1000 to make it in units of 100usec,
2776 * too. */
2777 spec.t11_t12 = (510 + 100) * 10;
2778
2779 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2780 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2781
2782 /* Use the max of the register settings and vbt. If both are
2783 * unset, fall back to the spec limits. */
2784#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2785 spec.field : \
2786 max(cur.field, vbt.field))
2787 assign_final(t1_t3);
2788 assign_final(t8);
2789 assign_final(t9);
2790 assign_final(t10);
2791 assign_final(t11_t12);
2792#undef assign_final
2793
2794#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2795 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2796 intel_dp->backlight_on_delay = get_delay(t8);
2797 intel_dp->backlight_off_delay = get_delay(t9);
2798 intel_dp->panel_power_down_delay = get_delay(t10);
2799 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2800#undef get_delay
2801
f30d26e4
JN		 2802 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2803 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2804 intel_dp->panel_power_cycle_delay);
2805
2806 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2807 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2808
2809 if (out)
2810 *out = final;
2811}
2812
2813static void
2814intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2815 struct intel_dp *intel_dp,
2816 struct edp_power_seq *seq)
2817{
2818 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2819 u32 pp_on, pp_off, pp_div, port_sel = 0;
2820 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2821 int pp_on_reg, pp_off_reg, pp_div_reg;
2822
2823 if (HAS_PCH_SPLIT(dev)) {
2824 pp_on_reg = PCH_PP_ON_DELAYS;
2825 pp_off_reg = PCH_PP_OFF_DELAYS;
2826 pp_div_reg = PCH_PP_DIVISOR;
2827 } else {
2828 pp_on_reg = PIPEA_PP_ON_DELAYS;
2829 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2830 pp_div_reg = PIPEA_PP_DIVISOR;
2831 }
2832
2833 if (IS_VALLEYVIEW(dev))
2834 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
f30d26e4 2835
67a54566 2836 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2837 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2838 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2839 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2840 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2841 /* Compute the divisor for the pp clock, simply match the Bspec
2842 * formula. */
453c5420 2843 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2844 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2845 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2846
2847 /* Haswell doesn't have any port selection bits for the panel
2848 * power sequencer any more. */
2849 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2850 if (is_cpu_edp(intel_dp))
453c5420 2851 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2852 else
453c5420 2853 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2854 }
2855
453c5420
JB		 2856 pp_on |= port_sel;
2857
2858 I915_WRITE(pp_on_reg, pp_on);
2859 I915_WRITE(pp_off_reg, pp_off);
2860 I915_WRITE(pp_div_reg, pp_div);
67a54566 2861
67a54566 2862 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2863 I915_READ(pp_on_reg),
2864 I915_READ(pp_off_reg),
2865 I915_READ(pp_div_reg));
f684960e
CW		 2866}
2867
a4fc5ed6 2868void
f0fec3f2
PZ		 2869intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2870 struct intel_connector *intel_connector)
a4fc5ed6 2871{
f0fec3f2
PZ		 2872 struct drm_connector *connector = &intel_connector->base;
2873 struct intel_dp *intel_dp = &intel_dig_port->dp;
2874 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2875 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2876 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2877 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2878 struct edp_power_seq power_seq = { 0 };
174edf1f 2879 enum port port = intel_dig_port->port;
5eb08b69 2880 const char *name = NULL;
b329530c 2881 int type;
a4fc5ed6 2882
0767935e
DV		 2883 /* Preserve the current hw state. */
2884 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2885 intel_dp->attached_connector = intel_connector;
3d3dc149 2886
f0fec3f2 2887 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2888 if (intel_dpd_is_edp(dev))
ea5b213a 2889 intel_dp->is_pch_edp = true;
b329530c 2890
19c03924
GB		 2891 /*
2892 * FIXME : We need to initialize built-in panels before external panels.
2893 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2894 */
f0fec3f2 2895 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2896 type = DRM_MODE_CONNECTOR_eDP;
2897 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2898 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2899 type = DRM_MODE_CONNECTOR_eDP;
2900 intel_encoder->type = INTEL_OUTPUT_EDP;
2901 } else {
00c09d70
PZ		 2902 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2903 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2904 * rewrite it.
2905 */
b329530c 2906 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2907 }
2908
b329530c 2909 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2910 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2911
a4fc5ed6
KP		 2912 connector->interlace_allowed = true;
2913 connector->doublescan_allowed = 0;
2914
f0fec3f2
PZ		 2915 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2916 ironlake_panel_vdd_work);
a4fc5ed6 2917
df0e9248 2918 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2919 drm_sysfs_connector_add(connector);
2920
affa9354 2921 if (HAS_DDI(dev))
bcbc889b
PZ		 2922 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2923 else
2924 intel_connector->get_hw_state = intel_connector_get_hw_state;
2925
9ed35ab1
PZ		 2926 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2927 if (HAS_DDI(dev)) {
2928 switch (intel_dig_port->port) {
2929 case PORT_A:
2930 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2931 break;
2932 case PORT_B:
2933 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2934 break;
2935 case PORT_C:
2936 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2937 break;
2938 case PORT_D:
2939 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2940 break;
2941 default:
2942 BUG();
2943 }
2944 }
e8cb4558 2945
a4fc5ed6 2946 /* Set up the DDC bus. */
ab9d7c30
PZ		 2947 switch (port) {
2948 case PORT_A:
1d843f9d 2949 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 2950 name = "DPDDC-A";
2951 break;
2952 case PORT_B:
1d843f9d 2953 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 2954 name = "DPDDC-B";
2955 break;
2956 case PORT_C:
1d843f9d 2957 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 2958 name = "DPDDC-C";
2959 break;
2960 case PORT_D:
1d843f9d 2961 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 2962 name = "DPDDC-D";
2963 break;
2964 default:
ad1c0b19 2965 BUG();
5eb08b69
ZW		 2966 }
2967
67a54566 2968 if (is_edp(intel_dp))
f30d26e4 2969 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 2970
2971 intel_dp_i2c_init(intel_dp, intel_connector, name);
2972
67a54566 2973 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2974 if (is_edp(intel_dp)) {
2975 bool ret;
f8779fda 2976 struct drm_display_mode *scan;
c1f05264 2977 struct edid *edid;
5d613501
JB		 2978
2979 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2980 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2981 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2982
59f3e272 2983 if (ret) {
7183dc29
JB		 2984 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2985 dev_priv->no_aux_handshake =
2986 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2987 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2988 } else {
3d3dc149 2989 /* if this fails, presume the device is a ghost */
48898b03 2990 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2991 intel_dp_encoder_destroy(&intel_encoder->base);
2992 intel_dp_destroy(connector);
3d3dc149 2993 return;
89667383 2994 }
89667383 2995
f30d26e4
JN		 2996 /* We now know it's not a ghost, init power sequence regs. */
2997 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2998 &power_seq);
2999
d6f24d0f
JB		 3000 ironlake_edp_panel_vdd_on(intel_dp);
3001 edid = drm_get_edid(connector, &intel_dp->adapter);
3002 if (edid) {
9cd300e0
JN		 3003 if (drm_add_edid_modes(connector, edid)) {
3004 drm_mode_connector_update_edid_property(connector, edid);
3005 drm_edid_to_eld(connector, edid);
3006 } else {
3007 kfree(edid);
3008 edid = ERR_PTR(-EINVAL);
3009 }
3010 } else {
3011 edid = ERR_PTR(-ENOENT);
d6f24d0f 3012 }
9cd300e0 3013 intel_connector->edid = edid;
f8779fda
JN		 3014
3015 /* prefer fixed mode from EDID if available */
3016 list_for_each_entry(scan, &connector->probed_modes, head) {
3017 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3018 fixed_mode = drm_mode_duplicate(dev, scan);
3019 break;
3020 }
d6f24d0f 3021 }
f8779fda
JN		 3022
3023 /* fallback to VBT if available for eDP */
3024 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3025 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3026 if (fixed_mode)
3027 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3028 }
f8779fda 3029
d6f24d0f
JB		 3030 ironlake_edp_panel_vdd_off(intel_dp, false);
3031 }
552fb0b7 3032
4d926461 3033 if (is_edp(intel_dp)) {
dd06f90e 3034 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 3035 intel_panel_setup_backlight(connector);
32f9d658
ZW		 3036 }
3037
f684960e
CW		 3038 intel_dp_add_properties(intel_dp, connector);
3039
a4fc5ed6
KP		 3040 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3041 * 0xd. Failure to do so will result in spurious interrupts being
3042 * generated on the port when a cable is not attached.
3043 */
3044 if (IS_G4X(dev) && !IS_GM45(dev)) {
3045 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3046 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3047 }
3048}
f0fec3f2
PZ		 3049
3050void
3051intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3052{
3053 struct intel_digital_port *intel_dig_port;
3054 struct intel_encoder *intel_encoder;
3055 struct drm_encoder *encoder;
3056 struct intel_connector *intel_connector;
3057
3058 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3059 if (!intel_dig_port)
3060 return;
3061
3062 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3063 if (!intel_connector) {
3064 kfree(intel_dig_port);
3065 return;
3066 }
3067
3068 intel_encoder = &intel_dig_port->base;
3069 encoder = &intel_encoder->base;
3070
3071 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3072 DRM_MODE_ENCODER_TMDS);
00c09d70 3073 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3074
5bfe2ac0 3075 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3076 intel_encoder->enable = intel_enable_dp;
3077 intel_encoder->pre_enable = intel_pre_enable_dp;
3078 intel_encoder->disable = intel_disable_dp;
3079 intel_encoder->post_disable = intel_post_disable_dp;
3080 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 3081
174edf1f 3082 intel_dig_port->port = port;
f0fec3f2
PZ		 3083 intel_dig_port->dp.output_reg = output_reg;
3084
00c09d70 3085 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3086 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3087 intel_encoder->cloneable = false;
3088 intel_encoder->hot_plug = intel_dp_hot_plug;
3089
3090 intel_dp_init_connector(intel_dig_port, intel_connector);
3091}
Linux kernel - Deliverables
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