projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: fix eDP detection
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
ea5b213a
CW		 45#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46#define IS_PCH_eDP(i) ((i)->is_pch_edp)
32f9d658 47
ea5b213a
CW		 48struct intel_dp {
49 struct intel_encoder base;
a4fc5ed6
KP		 50 uint32_t output_reg;
51 uint32_t DP;
52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 53 bool has_audio;
c8110e52 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[4];
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
a4fc5ed6
KP		 61};
62
ea5b213a
CW		 63static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
64{
65 return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base);
66}
a4fc5ed6 67
ea5b213a
CW		 68static void intel_dp_link_train(struct intel_dp *intel_dp);
69static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 70
32f9d658 71void
21d40d37 72intel_edp_link_config (struct intel_encoder *intel_encoder,
ea5b213a 73 int *lane_num, int *link_bw)
32f9d658 74{
ea5b213a 75 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 76
ea5b213a
CW		 77 *lane_num = intel_dp->lane_count;
78 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 79 *link_bw = 162000;
ea5b213a 80 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 81 *link_bw = 270000;
82}
83
a4fc5ed6 84static int
ea5b213a 85intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 86{
a4fc5ed6
KP		 87 int max_lane_count = 4;
88
ea5b213a
CW		 89 if (intel_dp->dpcd[0] >= 0x11) {
90 max_lane_count = intel_dp->dpcd[2] & 0x1f;
a4fc5ed6
KP		 91 switch (max_lane_count) {
92 case 1: case 2: case 4:
93 break;
94 default:
95 max_lane_count = 4;
96 }
97 }
98 return max_lane_count;
99}
100
101static int
ea5b213a 102intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 103{
ea5b213a 104 int max_link_bw = intel_dp->dpcd[1];
a4fc5ed6
KP		 105
106 switch (max_link_bw) {
107 case DP_LINK_BW_1_62:
108 case DP_LINK_BW_2_7:
109 break;
110 default:
111 max_link_bw = DP_LINK_BW_1_62;
112 break;
113 }
114 return max_link_bw;
115}
116
117static int
118intel_dp_link_clock(uint8_t link_bw)
119{
120 if (link_bw == DP_LINK_BW_2_7)
121 return 270000;
122 else
123 return 162000;
124}
125
126/* I think this is a fiction */
127static int
ea5b213a 128intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
a4fc5ed6 129{
885a5fb5
ZW		 130 struct drm_i915_private *dev_priv = dev->dev_private;
131
ea5b213a 132 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
885a5fb5
ZW		 133 return (pixel_clock * dev_priv->edp_bpp) / 8;
134 else
135 return pixel_clock * 3;
a4fc5ed6
KP		 136}
137
fe27d53e
DA		 138static int
139intel_dp_max_data_rate(int max_link_clock, int max_lanes)
140{
141 return (max_link_clock * max_lanes * 8) / 10;
142}
143
a4fc5ed6
KP		 144static int
145intel_dp_mode_valid(struct drm_connector *connector,
146 struct drm_display_mode *mode)
147{
55f78c43 148 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
7de56f43
ZY		 150 struct drm_device *dev = connector->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a
CW		 152 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
153 int max_lanes = intel_dp_max_lane_count(intel_dp);
a4fc5ed6 154
ea5b213a 155 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
7de56f43
ZY		 156 dev_priv->panel_fixed_mode) {
157 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
158 return MODE_PANEL;
159
160 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
161 return MODE_PANEL;
162 }
163
fe27d53e
DA		 164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
165 which are outside spec tolerances but somehow work by magic */
ea5b213a
CW		 166 if (!IS_eDP(intel_dp) &&
167 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
fe27d53e 168 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
a4fc5ed6
KP		 169 return MODE_CLOCK_HIGH;
170
171 if (mode->clock < 10000)
172 return MODE_CLOCK_LOW;
173
174 return MODE_OK;
175}
176
177static uint32_t
178pack_aux(uint8_t *src, int src_bytes)
179{
180 int i;
181 uint32_t v = 0;
182
183 if (src_bytes > 4)
184 src_bytes = 4;
185 for (i = 0; i < src_bytes; i++)
186 v |= ((uint32_t) src[i]) << ((3-i) * 8);
187 return v;
188}
189
190static void
191unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
192{
193 int i;
194 if (dst_bytes > 4)
195 dst_bytes = 4;
196 for (i = 0; i < dst_bytes; i++)
197 dst[i] = src >> ((3-i) * 8);
198}
199
fb0f8fbf
KP		 200/* hrawclock is 1/4 the FSB frequency */
201static int
202intel_hrawclk(struct drm_device *dev)
203{
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 uint32_t clkcfg;
206
207 clkcfg = I915_READ(CLKCFG);
208 switch (clkcfg & CLKCFG_FSB_MASK) {
209 case CLKCFG_FSB_400:
210 return 100;
211 case CLKCFG_FSB_533:
212 return 133;
213 case CLKCFG_FSB_667:
214 return 166;
215 case CLKCFG_FSB_800:
216 return 200;
217 case CLKCFG_FSB_1067:
218 return 266;
219 case CLKCFG_FSB_1333:
220 return 333;
221 /* these two are just a guess; one of them might be right */
222 case CLKCFG_FSB_1600:
223 case CLKCFG_FSB_1600_ALT:
224 return 400;
225 default:
226 return 133;
227 }
228}
229
a4fc5ed6 230static int
ea5b213a 231intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 232 uint8_t *send, int send_bytes,
233 uint8_t *recv, int recv_size)
234{
ea5b213a
CW		 235 uint32_t output_reg = intel_dp->output_reg;
236 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6
KP		 237 struct drm_i915_private *dev_priv = dev->dev_private;
238 uint32_t ch_ctl = output_reg + 0x10;
239 uint32_t ch_data = ch_ctl + 4;
240 int i;
241 int recv_bytes;
a4fc5ed6 242 uint32_t status;
fb0f8fbf 243 uint32_t aux_clock_divider;
e3421a18 244 int try, precharge;
a4fc5ed6
KP		 245
246 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 247 * and would like to run at 2MHz. So, take the
248 * hrawclk value and divide by 2 and use that
a4fc5ed6 249 */
ea5b213a 250 if (IS_eDP(intel_dp)) {
e3421a18
ZW		 251 if (IS_GEN6(dev))
252 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
253 else
254 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
255 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 256 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 257 else
258 aux_clock_divider = intel_hrawclk(dev) / 2;
259
e3421a18
ZW		 260 if (IS_GEN6(dev))
261 precharge = 3;
262 else
263 precharge = 5;
264
4f7f7b7e
CW		 265 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
266 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
267 I915_READ(ch_ctl));
268 return -EBUSY;
269 }
270
fb0f8fbf
KP		 271 /* Must try at least 3 times according to DP spec */
272 for (try = 0; try < 5; try++) {
273 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 274 for (i = 0; i < send_bytes; i += 4)
275 I915_WRITE(ch_data + i,
276 pack_aux(send + i, send_bytes - i));
fb0f8fbf
KP		 277
278 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 279 I915_WRITE(ch_ctl,
280 DP_AUX_CH_CTL_SEND_BUSY |
281 DP_AUX_CH_CTL_TIME_OUT_400us |
282 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
283 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
284 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
285 DP_AUX_CH_CTL_DONE |
286 DP_AUX_CH_CTL_TIME_OUT_ERROR |
287 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 288 for (;;) {
fb0f8fbf
KP		 289 status = I915_READ(ch_ctl);
290 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
291 break;
4f7f7b7e 292 udelay(100);
fb0f8fbf
KP		 293 }
294
295 /* Clear done status and any errors */
4f7f7b7e
CW		 296 I915_WRITE(ch_ctl,
297 status |
298 DP_AUX_CH_CTL_DONE |
299 DP_AUX_CH_CTL_TIME_OUT_ERROR |
300 DP_AUX_CH_CTL_RECEIVE_ERROR);
301 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 302 break;
303 }
304
a4fc5ed6 305 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 306 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 307 return -EBUSY;
a4fc5ed6
KP		 308 }
309
310 /* Check for timeout or receive error.
311 * Timeouts occur when the sink is not connected
312 */
a5b3da54 313 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 314 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 315 return -EIO;
316 }
1ae8c0a5
KP		 317
318 /* Timeouts occur when the device isn't connected, so they're
319 * "normal" -- don't fill the kernel log with these */
a5b3da54 320 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 321 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 322 return -ETIMEDOUT;
a4fc5ed6
KP		 323 }
324
325 /* Unload any bytes sent back from the other side */
326 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
327 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 328 if (recv_bytes > recv_size)
329 recv_bytes = recv_size;
330
4f7f7b7e
CW		 331 for (i = 0; i < recv_bytes; i += 4)
332 unpack_aux(I915_READ(ch_data + i),
333 recv + i, recv_bytes - i);
a4fc5ed6
KP		 334
335 return recv_bytes;
336}
337
338/* Write data to the aux channel in native mode */
339static int
ea5b213a 340intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 341 uint16_t address, uint8_t *send, int send_bytes)
342{
343 int ret;
344 uint8_t msg[20];
345 int msg_bytes;
346 uint8_t ack;
347
348 if (send_bytes > 16)
349 return -1;
350 msg[0] = AUX_NATIVE_WRITE << 4;
351 msg[1] = address >> 8;
eebc863e 352 msg[2] = address & 0xff;
a4fc5ed6
KP		 353 msg[3] = send_bytes - 1;
354 memcpy(&msg[4], send, send_bytes);
355 msg_bytes = send_bytes + 4;
356 for (;;) {
ea5b213a 357 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 358 if (ret < 0)
359 return ret;
360 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
361 break;
362 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
363 udelay(100);
364 else
a5b3da54 365 return -EIO;
a4fc5ed6
KP		 366 }
367 return send_bytes;
368}
369
370/* Write a single byte to the aux channel in native mode */
371static int
ea5b213a 372intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 373 uint16_t address, uint8_t byte)
374{
ea5b213a 375 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 376}
377
378/* read bytes from a native aux channel */
379static int
ea5b213a 380intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 381 uint16_t address, uint8_t *recv, int recv_bytes)
382{
383 uint8_t msg[4];
384 int msg_bytes;
385 uint8_t reply[20];
386 int reply_bytes;
387 uint8_t ack;
388 int ret;
389
390 msg[0] = AUX_NATIVE_READ << 4;
391 msg[1] = address >> 8;
392 msg[2] = address & 0xff;
393 msg[3] = recv_bytes - 1;
394
395 msg_bytes = 4;
396 reply_bytes = recv_bytes + 1;
397
398 for (;;) {
ea5b213a 399 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 400 reply, reply_bytes);
a5b3da54
KP		 401 if (ret == 0)
402 return -EPROTO;
403 if (ret < 0)
a4fc5ed6
KP		 404 return ret;
405 ack = reply[0];
406 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
407 memcpy(recv, reply + 1, ret - 1);
408 return ret - 1;
409 }
410 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
411 udelay(100);
412 else
a5b3da54 413 return -EIO;
a4fc5ed6
KP		 414 }
415}
416
417static int
ab2c0672
DA		 418intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
419 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 420{
ab2c0672 421 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 422 struct intel_dp *intel_dp = container_of(adapter,
423 struct intel_dp,
424 adapter);
ab2c0672
DA		 425 uint16_t address = algo_data->address;
426 uint8_t msg[5];
427 uint8_t reply[2];
428 int msg_bytes;
429 int reply_bytes;
430 int ret;
431
432 /* Set up the command byte */
433 if (mode & MODE_I2C_READ)
434 msg[0] = AUX_I2C_READ << 4;
435 else
436 msg[0] = AUX_I2C_WRITE << 4;
437
438 if (!(mode & MODE_I2C_STOP))
439 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 440
ab2c0672
DA		 441 msg[1] = address >> 8;
442 msg[2] = address;
443
444 switch (mode) {
445 case MODE_I2C_WRITE:
446 msg[3] = 0;
447 msg[4] = write_byte;
448 msg_bytes = 5;
449 reply_bytes = 1;
450 break;
451 case MODE_I2C_READ:
452 msg[3] = 0;
453 msg_bytes = 4;
454 reply_bytes = 2;
455 break;
456 default:
457 msg_bytes = 3;
458 reply_bytes = 1;
459 break;
460 }
461
462 for (;;) {
ea5b213a 463 ret = intel_dp_aux_ch(intel_dp,
ab2c0672
DA		 464 msg, msg_bytes,
465 reply, reply_bytes);
466 if (ret < 0) {
3ff99164 467 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 468 return ret;
469 }
470 switch (reply[0] & AUX_I2C_REPLY_MASK) {
471 case AUX_I2C_REPLY_ACK:
472 if (mode == MODE_I2C_READ) {
473 *read_byte = reply[1];
474 }
475 return reply_bytes - 1;
476 case AUX_I2C_REPLY_NACK:
3ff99164 477 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 478 return -EREMOTEIO;
479 case AUX_I2C_REPLY_DEFER:
3ff99164 480 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 481 udelay(100);
482 break;
483 default:
484 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
485 return -EREMOTEIO;
486 }
487 }
a4fc5ed6
KP		 488}
489
490static int
ea5b213a 491intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 492 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 493{
d54e9d28 494 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 495 intel_dp->algo.running = false;
496 intel_dp->algo.address = 0;
497 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
498
499 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
500 intel_dp->adapter.owner = THIS_MODULE;
501 intel_dp->adapter.class = I2C_CLASS_DDC;
502 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
503 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
504 intel_dp->adapter.algo_data = &intel_dp->algo;
505 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
506
507 return i2c_dp_aux_add_bus(&intel_dp->adapter);
a4fc5ed6
KP		 508}
509
510static bool
511intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
512 struct drm_display_mode *adjusted_mode)
513{
0d3a1bee
ZY		 514 struct drm_device *dev = encoder->dev;
515 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 516 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 517 int lane_count, clock;
ea5b213a
CW		 518 int max_lane_count = intel_dp_max_lane_count(intel_dp);
519 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 520 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
521
ea5b213a 522 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
0d3a1bee 523 dev_priv->panel_fixed_mode) {
1d8e1c75
CW		 524 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
525 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
526 mode, adjusted_mode);
0d3a1bee
ZY		 527 /*
528 * the mode->clock is used to calculate the Data&Link M/N
529 * of the pipe. For the eDP the fixed clock should be used.
530 */
531 mode->clock = dev_priv->panel_fixed_mode->clock;
532 }
533
a4fc5ed6
KP		 534 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
535 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 536 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 537
ea5b213a 538 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
885a5fb5 539 <= link_avail) {
ea5b213a
CW		 540 intel_dp->link_bw = bws[clock];
541 intel_dp->lane_count = lane_count;
542 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
28c97730
ZY		 543 DRM_DEBUG_KMS("Display port link bw %02x lane "
544 "count %d clock %d\n",
ea5b213a 545 intel_dp->link_bw, intel_dp->lane_count,
a4fc5ed6
KP		 546 adjusted_mode->clock);
547 return true;
548 }
549 }
550 }
fe27d53e 551
ea5b213a 552 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
fe27d53e 553 /* okay we failed just pick the highest */
ea5b213a
CW		 554 intel_dp->lane_count = max_lane_count;
555 intel_dp->link_bw = bws[max_clock];
556 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
fe27d53e
DA		 557 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
558 "count %d clock %d\n",
ea5b213a 559 intel_dp->link_bw, intel_dp->lane_count,
fe27d53e 560 adjusted_mode->clock);
1d8e1c75 561
fe27d53e
DA		 562 return true;
563 }
1d8e1c75 564
a4fc5ed6
KP		 565 return false;
566}
567
568struct intel_dp_m_n {
569 uint32_t tu;
570 uint32_t gmch_m;
571 uint32_t gmch_n;
572 uint32_t link_m;
573 uint32_t link_n;
574};
575
576static void
577intel_reduce_ratio(uint32_t *num, uint32_t *den)
578{
579 while (*num > 0xffffff || *den > 0xffffff) {
580 *num >>= 1;
581 *den >>= 1;
582 }
583}
584
585static void
36e83a18 586intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 587 int nlanes,
588 int pixel_clock,
589 int link_clock,
590 struct intel_dp_m_n *m_n)
591{
592 m_n->tu = 64;
36e83a18 593 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 594 m_n->gmch_n = link_clock * nlanes;
595 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
596 m_n->link_m = pixel_clock;
597 m_n->link_n = link_clock;
598 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
599}
600
36e83a18
ZY		 601bool intel_pch_has_edp(struct drm_crtc *crtc)
602{
603 struct drm_device *dev = crtc->dev;
604 struct drm_mode_config *mode_config = &dev->mode_config;
605 struct drm_encoder *encoder;
606
607 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 608 struct intel_dp *intel_dp;
36e83a18 609
ea5b213a 610 if (encoder->crtc != crtc)
36e83a18
ZY		 611 continue;
612
ea5b213a
CW		 613 intel_dp = enc_to_intel_dp(encoder);
614 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
615 return intel_dp->is_pch_edp;
36e83a18
ZY		 616 }
617 return false;
618}
619
a4fc5ed6
KP		 620void
621intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
622 struct drm_display_mode *adjusted_mode)
623{
624 struct drm_device *dev = crtc->dev;
625 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 626 struct drm_encoder *encoder;
a4fc5ed6
KP		 627 struct drm_i915_private *dev_priv = dev->dev_private;
628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
36e83a18 629 int lane_count = 4, bpp = 24;
a4fc5ed6
KP		 630 struct intel_dp_m_n m_n;
631
632 /*
21d40d37 633 * Find the lane count in the intel_encoder private
a4fc5ed6 634 */
55f78c43 635 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 636 struct intel_dp *intel_dp;
a4fc5ed6 637
d8201ab6 638 if (encoder->crtc != crtc)
a4fc5ed6
KP		 639 continue;
640
ea5b213a
CW		 641 intel_dp = enc_to_intel_dp(encoder);
642 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
643 lane_count = intel_dp->lane_count;
644 if (IS_PCH_eDP(intel_dp))
36e83a18 645 bpp = dev_priv->edp_bpp;
a4fc5ed6
KP		 646 break;
647 }
648 }
649
650 /*
651 * Compute the GMCH and Link ratios. The '3' here is
652 * the number of bytes_per_pixel post-LUT, which we always
653 * set up for 8-bits of R/G/B, or 3 bytes total.
654 */
36e83a18 655 intel_dp_compute_m_n(bpp, lane_count,
a4fc5ed6
KP		 656 mode->clock, adjusted_mode->clock, &m_n);
657
c619eed4 658 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 659 if (intel_crtc->pipe == 0) {
660 I915_WRITE(TRANSA_DATA_M1,
661 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
662 m_n.gmch_m);
663 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
664 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
665 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
666 } else {
667 I915_WRITE(TRANSB_DATA_M1,
668 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
669 m_n.gmch_m);
670 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
671 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
672 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
673 }
a4fc5ed6 674 } else {
5eb08b69
ZW		 675 if (intel_crtc->pipe == 0) {
676 I915_WRITE(PIPEA_GMCH_DATA_M,
677 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
678 m_n.gmch_m);
679 I915_WRITE(PIPEA_GMCH_DATA_N,
680 m_n.gmch_n);
681 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
682 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
683 } else {
684 I915_WRITE(PIPEB_GMCH_DATA_M,
685 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
686 m_n.gmch_m);
687 I915_WRITE(PIPEB_GMCH_DATA_N,
688 m_n.gmch_n);
689 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
690 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
691 }
a4fc5ed6
KP		 692 }
693}
694
695static void
696intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
697 struct drm_display_mode *adjusted_mode)
698{
e3421a18 699 struct drm_device *dev = encoder->dev;
ea5b213a
CW		 700 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
701 struct drm_crtc *crtc = intel_dp->base.enc.crtc;
a4fc5ed6
KP		 702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
703
ea5b213a 704 intel_dp->DP = (DP_VOLTAGE_0_4 |
9c9e7927
AJ		 705 DP_PRE_EMPHASIS_0);
706
707 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
ea5b213a 708 intel_dp->DP |= DP_SYNC_HS_HIGH;
9c9e7927 709 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
ea5b213a 710 intel_dp->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 711
ea5b213a
CW		 712 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
713 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3421a18 714 else
ea5b213a 715 intel_dp->DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6 716
ea5b213a 717 switch (intel_dp->lane_count) {
a4fc5ed6 718 case 1:
ea5b213a 719 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 720 break;
721 case 2:
ea5b213a 722 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 723 break;
724 case 4:
ea5b213a 725 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 726 break;
727 }
ea5b213a
CW		 728 if (intel_dp->has_audio)
729 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
a4fc5ed6 730
ea5b213a
CW		 731 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
732 intel_dp->link_configuration[0] = intel_dp->link_bw;
733 intel_dp->link_configuration[1] = intel_dp->lane_count;
a4fc5ed6
KP		 734
735 /*
9962c925 736 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 737 */
ea5b213a
CW		 738 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
739 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
740 intel_dp->DP |= DP_ENHANCED_FRAMING;
a4fc5ed6
KP		 741 }
742
e3421a18
ZW		 743 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
744 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
ea5b213a 745 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 746
ea5b213a 747 if (IS_eDP(intel_dp)) {
32f9d658 748 /* don't miss out required setting for eDP */
ea5b213a 749 intel_dp->DP |= DP_PLL_ENABLE;
32f9d658 750 if (adjusted_mode->clock < 200000)
ea5b213a 751 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
32f9d658 752 else
ea5b213a 753 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
32f9d658 754 }
a4fc5ed6
KP		 755}
756
7eaf5547
JB		 757/* Returns true if the panel was already on when called */
758static bool ironlake_edp_panel_on (struct drm_device *dev)
9934c132
JB		 759{
760 struct drm_i915_private *dev_priv = dev->dev_private;
913d8d11 761 u32 pp;
9934c132 762
913d8d11 763 if (I915_READ(PCH_PP_STATUS) & PP_ON)
7eaf5547 764 return true;
9934c132
JB		 765
766 pp = I915_READ(PCH_PP_CONTROL);
37c6c9b0
JB		 767
768 /* ILK workaround: disable reset around power sequence */
769 pp &= ~PANEL_POWER_RESET;
770 I915_WRITE(PCH_PP_CONTROL, pp);
771 POSTING_READ(PCH_PP_CONTROL);
772
9934c132
JB		 773 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
774 I915_WRITE(PCH_PP_CONTROL, pp);
9934c132 775
481b6af3 776 if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000))
913d8d11
CW		 777 DRM_ERROR("panel on wait timed out: 0x%08x\n",
778 I915_READ(PCH_PP_STATUS));
9934c132
JB		 779
780 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
37c6c9b0 781 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
9934c132 782 I915_WRITE(PCH_PP_CONTROL, pp);
37c6c9b0 783 POSTING_READ(PCH_PP_CONTROL);
7eaf5547
JB		 784
785 return false;
9934c132
JB		 786}
787
788static void ironlake_edp_panel_off (struct drm_device *dev)
789{
790 struct drm_i915_private *dev_priv = dev->dev_private;
913d8d11 791 u32 pp;
9934c132
JB		 792
793 pp = I915_READ(PCH_PP_CONTROL);
37c6c9b0
JB		 794
795 /* ILK workaround: disable reset around power sequence */
796 pp &= ~PANEL_POWER_RESET;
797 I915_WRITE(PCH_PP_CONTROL, pp);
798 POSTING_READ(PCH_PP_CONTROL);
799
9934c132
JB		 800 pp &= ~POWER_TARGET_ON;
801 I915_WRITE(PCH_PP_CONTROL, pp);
9934c132 802
481b6af3 803 if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000))
913d8d11
CW		 804 DRM_ERROR("panel off wait timed out: 0x%08x\n",
805 I915_READ(PCH_PP_STATUS));
9934c132
JB		 806
807 /* Make sure VDD is enabled so DP AUX will work */
37c6c9b0 808 pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */
9934c132 809 I915_WRITE(PCH_PP_CONTROL, pp);
37c6c9b0 810 POSTING_READ(PCH_PP_CONTROL);
9934c132
JB		 811}
812
f2b115e6 813static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 814{
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 u32 pp;
817
28c97730 818 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 819 pp = I915_READ(PCH_PP_CONTROL);
820 pp |= EDP_BLC_ENABLE;
821 I915_WRITE(PCH_PP_CONTROL, pp);
822}
823
f2b115e6 824static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 825{
826 struct drm_i915_private *dev_priv = dev->dev_private;
827 u32 pp;
828
28c97730 829 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 830 pp = I915_READ(PCH_PP_CONTROL);
831 pp &= ~EDP_BLC_ENABLE;
832 I915_WRITE(PCH_PP_CONTROL, pp);
833}
a4fc5ed6 834
d240f20f
JB		 835static void ironlake_edp_pll_on(struct drm_encoder *encoder)
836{
837 struct drm_device *dev = encoder->dev;
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 u32 dpa_ctl;
840
841 DRM_DEBUG_KMS("\n");
842 dpa_ctl = I915_READ(DP_A);
843 dpa_ctl &= ~DP_PLL_ENABLE;
844 I915_WRITE(DP_A, dpa_ctl);
845}
846
847static void ironlake_edp_pll_off(struct drm_encoder *encoder)
848{
849 struct drm_device *dev = encoder->dev;
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 u32 dpa_ctl;
852
853 dpa_ctl = I915_READ(DP_A);
854 dpa_ctl |= DP_PLL_ENABLE;
855 I915_WRITE(DP_A, dpa_ctl);
856 udelay(200);
857}
858
859static void intel_dp_prepare(struct drm_encoder *encoder)
860{
861 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
862 struct drm_device *dev = encoder->dev;
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
865
7eaf5547 866 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
d240f20f
JB		 867 ironlake_edp_backlight_off(dev);
868 ironlake_edp_panel_on(dev);
869 ironlake_edp_pll_on(encoder);
870 }
871 if (dp_reg & DP_PORT_EN)
872 intel_dp_link_down(intel_dp);
873}
874
875static void intel_dp_commit(struct drm_encoder *encoder)
876{
877 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
878 struct drm_device *dev = encoder->dev;
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
881
882 if (!(dp_reg & DP_PORT_EN)) {
883 intel_dp_link_train(intel_dp);
884 }
885 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
886 ironlake_edp_backlight_on(dev);
887}
888
a4fc5ed6
KP		 889static void
890intel_dp_dpms(struct drm_encoder *encoder, int mode)
891{
ea5b213a 892 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 893 struct drm_device *dev = encoder->dev;
a4fc5ed6 894 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 895 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 896
897 if (mode != DRM_MODE_DPMS_ON) {
7643a7fa
JB		 898 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
899 ironlake_edp_backlight_off(dev);
900 ironlake_edp_panel_off(dev);
32f9d658 901 }
7643a7fa
JB		 902 if (dp_reg & DP_PORT_EN)
903 intel_dp_link_down(intel_dp);
d240f20f
JB		 904 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
905 ironlake_edp_pll_off(encoder);
a4fc5ed6 906 } else {
32f9d658 907 if (!(dp_reg & DP_PORT_EN)) {
7643a7fa 908 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
9934c132 909 ironlake_edp_panel_on(dev);
7643a7fa
JB		 910 intel_dp_link_train(intel_dp);
911 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
f2b115e6 912 ironlake_edp_backlight_on(dev);
32f9d658 913 }
a4fc5ed6 914 }
ea5b213a 915 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 916}
917
918/*
919 * Fetch AUX CH registers 0x202 - 0x207 which contain
920 * link status information
921 */
922static bool
ea5b213a 923intel_dp_get_link_status(struct intel_dp *intel_dp,
a4fc5ed6
KP		 924 uint8_t link_status[DP_LINK_STATUS_SIZE])
925{
926 int ret;
927
ea5b213a 928 ret = intel_dp_aux_native_read(intel_dp,
a4fc5ed6
KP		 929 DP_LANE0_1_STATUS,
930 link_status, DP_LINK_STATUS_SIZE);
931 if (ret != DP_LINK_STATUS_SIZE)
932 return false;
933 return true;
934}
935
936static uint8_t
937intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
938 int r)
939{
940 return link_status[r - DP_LANE0_1_STATUS];
941}
942
a4fc5ed6
KP		 943static uint8_t
944intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
945 int lane)
946{
947 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
948 int s = ((lane & 1) ?
949 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
950 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
951 uint8_t l = intel_dp_link_status(link_status, i);
952
953 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
954}
955
956static uint8_t
957intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
958 int lane)
959{
960 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
961 int s = ((lane & 1) ?
962 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
963 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
964 uint8_t l = intel_dp_link_status(link_status, i);
965
966 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
967}
968
969
970#if 0
971static char *voltage_names[] = {
972 "0.4V", "0.6V", "0.8V", "1.2V"
973};
974static char *pre_emph_names[] = {
975 "0dB", "3.5dB", "6dB", "9.5dB"
976};
977static char *link_train_names[] = {
978 "pattern 1", "pattern 2", "idle", "off"
979};
980#endif
981
982/*
983 * These are source-specific values; current Intel hardware supports
984 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
985 */
986#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
987
988static uint8_t
989intel_dp_pre_emphasis_max(uint8_t voltage_swing)
990{
991 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
992 case DP_TRAIN_VOLTAGE_SWING_400:
993 return DP_TRAIN_PRE_EMPHASIS_6;
994 case DP_TRAIN_VOLTAGE_SWING_600:
995 return DP_TRAIN_PRE_EMPHASIS_6;
996 case DP_TRAIN_VOLTAGE_SWING_800:
997 return DP_TRAIN_PRE_EMPHASIS_3_5;
998 case DP_TRAIN_VOLTAGE_SWING_1200:
999 default:
1000 return DP_TRAIN_PRE_EMPHASIS_0;
1001 }
1002}
1003
1004static void
ea5b213a 1005intel_get_adjust_train(struct intel_dp *intel_dp,
a4fc5ed6
KP		 1006 uint8_t link_status[DP_LINK_STATUS_SIZE],
1007 int lane_count,
1008 uint8_t train_set[4])
1009{
1010 uint8_t v = 0;
1011 uint8_t p = 0;
1012 int lane;
1013
1014 for (lane = 0; lane < lane_count; lane++) {
1015 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
1016 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
1017
1018 if (this_v > v)
1019 v = this_v;
1020 if (this_p > p)
1021 p = this_p;
1022 }
1023
1024 if (v >= I830_DP_VOLTAGE_MAX)
1025 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1026
1027 if (p >= intel_dp_pre_emphasis_max(v))
1028 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1029
1030 for (lane = 0; lane < 4; lane++)
1031 train_set[lane] = v | p;
1032}
1033
1034static uint32_t
1035intel_dp_signal_levels(uint8_t train_set, int lane_count)
1036{
1037 uint32_t signal_levels = 0;
1038
1039 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1040 case DP_TRAIN_VOLTAGE_SWING_400:
1041 default:
1042 signal_levels |= DP_VOLTAGE_0_4;
1043 break;
1044 case DP_TRAIN_VOLTAGE_SWING_600:
1045 signal_levels |= DP_VOLTAGE_0_6;
1046 break;
1047 case DP_TRAIN_VOLTAGE_SWING_800:
1048 signal_levels |= DP_VOLTAGE_0_8;
1049 break;
1050 case DP_TRAIN_VOLTAGE_SWING_1200:
1051 signal_levels |= DP_VOLTAGE_1_2;
1052 break;
1053 }
1054 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1055 case DP_TRAIN_PRE_EMPHASIS_0:
1056 default:
1057 signal_levels |= DP_PRE_EMPHASIS_0;
1058 break;
1059 case DP_TRAIN_PRE_EMPHASIS_3_5:
1060 signal_levels |= DP_PRE_EMPHASIS_3_5;
1061 break;
1062 case DP_TRAIN_PRE_EMPHASIS_6:
1063 signal_levels |= DP_PRE_EMPHASIS_6;
1064 break;
1065 case DP_TRAIN_PRE_EMPHASIS_9_5:
1066 signal_levels |= DP_PRE_EMPHASIS_9_5;
1067 break;
1068 }
1069 return signal_levels;
1070}
1071
e3421a18
ZW		 1072/* Gen6's DP voltage swing and pre-emphasis control */
1073static uint32_t
1074intel_gen6_edp_signal_levels(uint8_t train_set)
1075{
1076 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1077 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1078 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1079 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1080 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1081 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1082 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1083 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1084 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1085 default:
1086 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1087 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1088 }
1089}
1090
a4fc5ed6
KP		 1091static uint8_t
1092intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1093 int lane)
1094{
1095 int i = DP_LANE0_1_STATUS + (lane >> 1);
1096 int s = (lane & 1) * 4;
1097 uint8_t l = intel_dp_link_status(link_status, i);
1098
1099 return (l >> s) & 0xf;
1100}
1101
1102/* Check for clock recovery is done on all channels */
1103static bool
1104intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1105{
1106 int lane;
1107 uint8_t lane_status;
1108
1109 for (lane = 0; lane < lane_count; lane++) {
1110 lane_status = intel_get_lane_status(link_status, lane);
1111 if ((lane_status & DP_LANE_CR_DONE) == 0)
1112 return false;
1113 }
1114 return true;
1115}
1116
1117/* Check to see if channel eq is done on all channels */
1118#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1119 DP_LANE_CHANNEL_EQ_DONE|\
1120 DP_LANE_SYMBOL_LOCKED)
1121static bool
1122intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1123{
1124 uint8_t lane_align;
1125 uint8_t lane_status;
1126 int lane;
1127
1128 lane_align = intel_dp_link_status(link_status,
1129 DP_LANE_ALIGN_STATUS_UPDATED);
1130 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1131 return false;
1132 for (lane = 0; lane < lane_count; lane++) {
1133 lane_status = intel_get_lane_status(link_status, lane);
1134 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1135 return false;
1136 }
1137 return true;
1138}
1139
1140static bool
ea5b213a 1141intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6
KP		 1142 uint32_t dp_reg_value,
1143 uint8_t dp_train_pat,
1144 uint8_t train_set[4],
1145 bool first)
1146{
ea5b213a 1147 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1148 struct drm_i915_private *dev_priv = dev->dev_private;
9d0498a2 1149 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
a4fc5ed6
KP		 1150 int ret;
1151
ea5b213a
CW		 1152 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1153 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1154 if (first)
9d0498a2 1155 intel_wait_for_vblank(dev, intel_crtc->pipe);
a4fc5ed6 1156
ea5b213a 1157 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1158 DP_TRAINING_PATTERN_SET,
1159 dp_train_pat);
1160
ea5b213a 1161 ret = intel_dp_aux_native_write(intel_dp,
a4fc5ed6
KP		 1162 DP_TRAINING_LANE0_SET, train_set, 4);
1163 if (ret != 4)
1164 return false;
1165
1166 return true;
1167}
1168
1169static void
ea5b213a 1170intel_dp_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1171{
ea5b213a 1172 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1173 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1174 uint8_t train_set[4];
1175 uint8_t link_status[DP_LINK_STATUS_SIZE];
1176 int i;
1177 uint8_t voltage;
1178 bool clock_recovery = false;
1179 bool channel_eq = false;
1180 bool first = true;
1181 int tries;
e3421a18 1182 u32 reg;
ea5b213a 1183 uint32_t DP = intel_dp->DP;
a4fc5ed6
KP		 1184
1185 /* Write the link configuration data */
ea5b213a
CW		 1186 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1187 intel_dp->link_configuration,
1188 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1189
1190 DP |= DP_PORT_EN;
ea5b213a 1191 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1192 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1193 else
1194 DP &= ~DP_LINK_TRAIN_MASK;
a4fc5ed6
KP		 1195 memset(train_set, 0, 4);
1196 voltage = 0xff;
1197 tries = 0;
1198 clock_recovery = false;
1199 for (;;) {
1200 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18 1201 uint32_t signal_levels;
ea5b213a 1202 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
e3421a18
ZW		 1203 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1204 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1205 } else {
ea5b213a 1206 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1207 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1208 }
a4fc5ed6 1209
ea5b213a 1210 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1211 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1212 else
1213 reg = DP | DP_LINK_TRAIN_PAT_1;
1214
ea5b213a 1215 if (!intel_dp_set_link_train(intel_dp, reg,
a4fc5ed6
KP		 1216 DP_TRAINING_PATTERN_1, train_set, first))
1217 break;
1218 first = false;
1219 /* Set training pattern 1 */
1220
1221 udelay(100);
ea5b213a 1222 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6
KP		 1223 break;
1224
ea5b213a 1225 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
a4fc5ed6
KP		 1226 clock_recovery = true;
1227 break;
1228 }
1229
1230 /* Check to see if we've tried the max voltage */
ea5b213a 1231 for (i = 0; i < intel_dp->lane_count; i++)
a4fc5ed6
KP		 1232 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1233 break;
ea5b213a 1234 if (i == intel_dp->lane_count)
a4fc5ed6
KP		 1235 break;
1236
1237 /* Check to see if we've tried the same voltage 5 times */
1238 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1239 ++tries;
1240 if (tries == 5)
1241 break;
1242 } else
1243 tries = 0;
1244 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1245
1246 /* Compute new train_set as requested by target */
ea5b213a 1247 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
a4fc5ed6
KP		 1248 }
1249
1250 /* channel equalization */
1251 tries = 0;
1252 channel_eq = false;
1253 for (;;) {
1254 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1255 uint32_t signal_levels;
1256
ea5b213a 1257 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
e3421a18
ZW		 1258 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1259 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1260 } else {
ea5b213a 1261 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1262 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1263 }
1264
ea5b213a 1265 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1266 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1267 else
1268 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1269
1270 /* channel eq pattern */
ea5b213a 1271 if (!intel_dp_set_link_train(intel_dp, reg,
a4fc5ed6
KP		 1272 DP_TRAINING_PATTERN_2, train_set,
1273 false))
1274 break;
1275
1276 udelay(400);
ea5b213a 1277 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6
KP		 1278 break;
1279
ea5b213a 1280 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) {
a4fc5ed6
KP		 1281 channel_eq = true;
1282 break;
1283 }
1284
1285 /* Try 5 times */
1286 if (tries > 5)
1287 break;
1288
1289 /* Compute new train_set as requested by target */
ea5b213a 1290 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
a4fc5ed6
KP		 1291 ++tries;
1292 }
1293
ea5b213a 1294 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1295 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1296 else
1297 reg = DP | DP_LINK_TRAIN_OFF;
1298
ea5b213a
CW		 1299 I915_WRITE(intel_dp->output_reg, reg);
1300 POSTING_READ(intel_dp->output_reg);
1301 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1302 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1303}
1304
1305static void
ea5b213a 1306intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1307{
ea5b213a 1308 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1309 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1310 uint32_t DP = intel_dp->DP;
a4fc5ed6 1311
28c97730 1312 DRM_DEBUG_KMS("\n");
32f9d658 1313
ea5b213a 1314 if (IS_eDP(intel_dp)) {
32f9d658 1315 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1316 I915_WRITE(intel_dp->output_reg, DP);
1317 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1318 udelay(100);
1319 }
1320
ea5b213a 1321 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
e3421a18 1322 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a
CW		 1323 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1324 POSTING_READ(intel_dp->output_reg);
e3421a18
ZW		 1325 } else {
1326 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a
CW		 1327 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1328 POSTING_READ(intel_dp->output_reg);
e3421a18 1329 }
5eb08b69
ZW		 1330
1331 udelay(17000);
1332
ea5b213a 1333 if (IS_eDP(intel_dp))
32f9d658 1334 DP |= DP_LINK_TRAIN_OFF;
ea5b213a
CW		 1335 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1336 POSTING_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1337}
1338
a4fc5ed6
KP		 1339/*
1340 * According to DP spec
1341 * 5.1.2:
1342 * 1. Read DPCD
1343 * 2. Configure link according to Receiver Capabilities
1344 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1345 * 4. Check link status on receipt of hot-plug interrupt
1346 */
1347
1348static void
ea5b213a 1349intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 1350{
a4fc5ed6
KP		 1351 uint8_t link_status[DP_LINK_STATUS_SIZE];
1352
ea5b213a 1353 if (!intel_dp->base.enc.crtc)
a4fc5ed6
KP		 1354 return;
1355
ea5b213a
CW		 1356 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1357 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 1358 return;
1359 }
1360
ea5b213a
CW		 1361 if (!intel_channel_eq_ok(link_status, intel_dp->lane_count))
1362 intel_dp_link_train(intel_dp);
a4fc5ed6 1363}
a4fc5ed6 1364
5eb08b69 1365static enum drm_connector_status
f2b115e6 1366ironlake_dp_detect(struct drm_connector *connector)
5eb08b69 1367{
55f78c43 1368 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1369 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5eb08b69 1370 enum drm_connector_status status;
7eaf5547 1371 bool was_on = false;
5eb08b69 1372
7eaf5547
JB		 1373 /* Panel needs power for AUX to work */
1374 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
1375 was_on = ironlake_edp_panel_on(connector->dev);
5eb08b69 1376 status = connector_status_disconnected;
ea5b213a
CW		 1377 if (intel_dp_aux_native_read(intel_dp,
1378 0x000, intel_dp->dpcd,
1379 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
5eb08b69 1380 {
ea5b213a 1381 if (intel_dp->dpcd[0] != 0)
5eb08b69
ZW		 1382 status = connector_status_connected;
1383 }
ea5b213a
CW		 1384 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1385 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
7eaf5547
JB		 1386 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && !was_on)
1387 ironlake_edp_panel_off(connector->dev);
5eb08b69
ZW		 1388 return status;
1389}
1390
a4fc5ed6
KP		 1391/**
1392 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1393 *
1394 * \return true if DP port is connected.
1395 * \return false if DP port is disconnected.
1396 */
1397static enum drm_connector_status
1398intel_dp_detect(struct drm_connector *connector)
1399{
55f78c43 1400 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a
CW		 1401 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1402 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1403 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1404 uint32_t temp, bit;
1405 enum drm_connector_status status;
1406
ea5b213a 1407 intel_dp->has_audio = false;
a4fc5ed6 1408
c619eed4 1409 if (HAS_PCH_SPLIT(dev))
f2b115e6 1410 return ironlake_dp_detect(connector);
5eb08b69 1411
ea5b213a 1412 switch (intel_dp->output_reg) {
a4fc5ed6
KP		 1413 case DP_B:
1414 bit = DPB_HOTPLUG_INT_STATUS;
1415 break;
1416 case DP_C:
1417 bit = DPC_HOTPLUG_INT_STATUS;
1418 break;
1419 case DP_D:
1420 bit = DPD_HOTPLUG_INT_STATUS;
1421 break;
1422 default:
1423 return connector_status_unknown;
1424 }
1425
1426 temp = I915_READ(PORT_HOTPLUG_STAT);
1427
1428 if ((temp & bit) == 0)
1429 return connector_status_disconnected;
1430
1431 status = connector_status_disconnected;
ea5b213a
CW		 1432 if (intel_dp_aux_native_read(intel_dp,
1433 0x000, intel_dp->dpcd,
1434 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
a4fc5ed6 1435 {
ea5b213a 1436 if (intel_dp->dpcd[0] != 0)
a4fc5ed6
KP		 1437 status = connector_status_connected;
1438 }
1439 return status;
1440}
1441
1442static int intel_dp_get_modes(struct drm_connector *connector)
1443{
55f78c43 1444 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a
CW		 1445 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1446 struct drm_device *dev = intel_dp->base.enc.dev;
32f9d658
ZW		 1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448 int ret;
a4fc5ed6
KP		 1449
1450 /* We should parse the EDID data and find out if it has an audio sink
1451 */
1452
ea5b213a 1453 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
b9efc480 1454 if (ret) {
ea5b213a 1455 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
b9efc480
ZY		 1456 !dev_priv->panel_fixed_mode) {
1457 struct drm_display_mode *newmode;
1458 list_for_each_entry(newmode, &connector->probed_modes,
1459 head) {
1460 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1461 dev_priv->panel_fixed_mode =
1462 drm_mode_duplicate(dev, newmode);
1463 break;
1464 }
1465 }
1466 }
1467
32f9d658 1468 return ret;
b9efc480 1469 }
32f9d658
ZW		 1470
1471 /* if eDP has no EDID, try to use fixed panel mode from VBT */
ea5b213a 1472 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
32f9d658
ZW		 1473 if (dev_priv->panel_fixed_mode != NULL) {
1474 struct drm_display_mode *mode;
1475 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1476 drm_mode_probed_add(connector, mode);
1477 return 1;
1478 }
1479 }
1480 return 0;
a4fc5ed6
KP		 1481}
1482
1483static void
1484intel_dp_destroy (struct drm_connector *connector)
1485{
a4fc5ed6
KP		 1486 drm_sysfs_connector_remove(connector);
1487 drm_connector_cleanup(connector);
55f78c43 1488 kfree(connector);
a4fc5ed6
KP		 1489}
1490
24d05927
DV		 1491static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1492{
1493 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1494
1495 i2c_del_adapter(&intel_dp->adapter);
1496 drm_encoder_cleanup(encoder);
1497 kfree(intel_dp);
1498}
1499
a4fc5ed6
KP		 1500static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1501 .dpms = intel_dp_dpms,
1502 .mode_fixup = intel_dp_mode_fixup,
d240f20f 1503 .prepare = intel_dp_prepare,
a4fc5ed6 1504 .mode_set = intel_dp_mode_set,
d240f20f 1505 .commit = intel_dp_commit,
a4fc5ed6
KP		 1506};
1507
1508static const struct drm_connector_funcs intel_dp_connector_funcs = {
1509 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1510 .detect = intel_dp_detect,
1511 .fill_modes = drm_helper_probe_single_connector_modes,
1512 .destroy = intel_dp_destroy,
1513};
1514
1515static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1516 .get_modes = intel_dp_get_modes,
1517 .mode_valid = intel_dp_mode_valid,
55f78c43 1518 .best_encoder = intel_attached_encoder,
a4fc5ed6
KP		 1519};
1520
a4fc5ed6 1521static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 1522 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 1523};
1524
995b6762 1525static void
21d40d37 1526intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 1527{
ea5b213a 1528 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 1529
ea5b213a
CW		 1530 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1531 intel_dp_check_link_status(intel_dp);
c8110e52 1532}
6207937d 1533
e3421a18
ZW		 1534/* Return which DP Port should be selected for Transcoder DP control */
1535int
1536intel_trans_dp_port_sel (struct drm_crtc *crtc)
1537{
1538 struct drm_device *dev = crtc->dev;
1539 struct drm_mode_config *mode_config = &dev->mode_config;
1540 struct drm_encoder *encoder;
e3421a18
ZW		 1541
1542 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 1543 struct intel_dp *intel_dp;
1544
d8201ab6 1545 if (encoder->crtc != crtc)
e3421a18
ZW		 1546 continue;
1547
ea5b213a
CW		 1548 intel_dp = enc_to_intel_dp(encoder);
1549 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1550 return intel_dp->output_reg;
e3421a18 1551 }
ea5b213a 1552
e3421a18
ZW		 1553 return -1;
1554}
1555
36e83a18 1556/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 1557bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 1558{
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 struct child_device_config *p_child;
1561 int i;
1562
1563 if (!dev_priv->child_dev_num)
1564 return false;
1565
1566 for (i = 0; i < dev_priv->child_dev_num; i++) {
1567 p_child = dev_priv->child_dev + i;
1568
1569 if (p_child->dvo_port == PORT_IDPD &&
1570 p_child->device_type == DEVICE_TYPE_eDP)
1571 return true;
1572 }
1573 return false;
1574}
1575
a4fc5ed6
KP		 1576void
1577intel_dp_init(struct drm_device *dev, int output_reg)
1578{
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580 struct drm_connector *connector;
ea5b213a 1581 struct intel_dp *intel_dp;
21d40d37 1582 struct intel_encoder *intel_encoder;
55f78c43 1583 struct intel_connector *intel_connector;
5eb08b69 1584 const char *name = NULL;
b329530c 1585 int type;
a4fc5ed6 1586
ea5b213a
CW		 1587 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1588 if (!intel_dp)
a4fc5ed6
KP		 1589 return;
1590
55f78c43
ZW		 1591 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1592 if (!intel_connector) {
ea5b213a 1593 kfree(intel_dp);
55f78c43
ZW		 1594 return;
1595 }
ea5b213a 1596 intel_encoder = &intel_dp->base;
55f78c43 1597
ea5b213a 1598 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 1599 if (intel_dpd_is_edp(dev))
ea5b213a 1600 intel_dp->is_pch_edp = true;
b329530c 1601
ea5b213a 1602 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
b329530c
AJ		 1603 type = DRM_MODE_CONNECTOR_eDP;
1604 intel_encoder->type = INTEL_OUTPUT_EDP;
1605 } else {
1606 type = DRM_MODE_CONNECTOR_DisplayPort;
1607 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1608 }
1609
55f78c43 1610 connector = &intel_connector->base;
b329530c 1611 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 1612 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1613
eb1f8e4f
DA		 1614 connector->polled = DRM_CONNECTOR_POLL_HPD;
1615
652af9d7 1616 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 1617 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1618 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 1619 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1620 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 1621 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 1622
ea5b213a 1623 if (IS_eDP(intel_dp))
21d40d37 1624 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 1625
21d40d37 1626 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1627 connector->interlace_allowed = true;
1628 connector->doublescan_allowed = 0;
1629
ea5b213a
CW		 1630 intel_dp->output_reg = output_reg;
1631 intel_dp->has_audio = false;
1632 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6 1633
21d40d37 1634 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
a4fc5ed6 1635 DRM_MODE_ENCODER_TMDS);
21d40d37 1636 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
a4fc5ed6 1637
55f78c43 1638 drm_mode_connector_attach_encoder(&intel_connector->base,
21d40d37 1639 &intel_encoder->enc);
a4fc5ed6
KP		 1640 drm_sysfs_connector_add(connector);
1641
1642 /* Set up the DDC bus. */
5eb08b69 1643 switch (output_reg) {
32f9d658
ZW		 1644 case DP_A:
1645 name = "DPDDC-A";
1646 break;
5eb08b69
ZW		 1647 case DP_B:
1648 case PCH_DP_B:
b01f2c3a
JB		 1649 dev_priv->hotplug_supported_mask |=
1650 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1651 name = "DPDDC-B";
1652 break;
1653 case DP_C:
1654 case PCH_DP_C:
b01f2c3a
JB		 1655 dev_priv->hotplug_supported_mask |=
1656 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1657 name = "DPDDC-C";
1658 break;
1659 case DP_D:
1660 case PCH_DP_D:
b01f2c3a
JB		 1661 dev_priv->hotplug_supported_mask |=
1662 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1663 name = "DPDDC-D";
1664 break;
1665 }
1666
ea5b213a 1667 intel_dp_i2c_init(intel_dp, intel_connector, name);
32f9d658 1668
ea5b213a 1669 intel_encoder->ddc_bus = &intel_dp->adapter;
21d40d37 1670 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1671
ea5b213a 1672 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
32f9d658
ZW		 1673 /* initialize panel mode from VBT if available for eDP */
1674 if (dev_priv->lfp_lvds_vbt_mode) {
1675 dev_priv->panel_fixed_mode =
1676 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1677 if (dev_priv->panel_fixed_mode) {
1678 dev_priv->panel_fixed_mode->type |=
1679 DRM_MODE_TYPE_PREFERRED;
1680 }
1681 }
1682 }
1683
a4fc5ed6
KP		 1684 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1685 * 0xd. Failure to do so will result in spurious interrupts being
1686 * generated on the port when a cable is not attached.
1687 */
1688 if (IS_G4X(dev) && !IS_GM45(dev)) {
1689 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1690 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1691 }
1692}
Linux kernel - Deliverables
This page took 0.179196 seconds and 5 git commands to generate.