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drm/i915: BDW PSR: Add single frame update support.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
130 else
131 max_link_bw = DP_LINK_BW_2_7;
d4eead50 132 break;
a4fc5ed6 133 default:
d4eead50
ID		 134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw);
a4fc5ed6
KP		 136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140}
141
eeb6324d
PZ		 142static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143{
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
147
148 source_max = 4;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
151 source_max = 2;
152
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154
155 return min(source_max, sink_max);
156}
157
cd9dde44
AJ		 158/*
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
161 *
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 *
164 * 270000 * 1 * 8 / 10 == 216000
165 *
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
170 *
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
173 */
174
a4fc5ed6 175static int
c898261c 176intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 177{
cd9dde44 178 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 179}
180
fe27d53e
DA		 181static int
182intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183{
184 return (max_link_clock * max_lanes * 8) / 10;
185}
186
c19de8eb 187static enum drm_mode_status
a4fc5ed6
KP		 188intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190{
df0e9248 191 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 196
dd06f90e
JN		 197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 199 return MODE_PANEL;
200
dd06f90e 201 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 202 return MODE_PANEL;
03afc4a2
DV		 203
204 target_clock = fixed_mode->clock;
7de56f43
ZY		 205 }
206
36008365 207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 208 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 209
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
212
213 if (mode_rate > max_rate)
c4867936 214 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 215
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
218
0af78a2b
DV		 219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
221
a4fc5ed6
KP		 222 return MODE_OK;
223}
224
225static uint32_t
226pack_aux(uint8_t *src, int src_bytes)
227{
228 int i;
229 uint32_t v = 0;
230
231 if (src_bytes > 4)
232 src_bytes = 4;
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
235 return v;
236}
237
238static void
239unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
240{
241 int i;
242 if (dst_bytes > 4)
243 dst_bytes = 4;
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
246}
247
fb0f8fbf
KP		 248/* hrawclock is 1/4 the FSB frequency */
249static int
250intel_hrawclk(struct drm_device *dev)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 uint32_t clkcfg;
254
9473c8f4
VP		 255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
257 return 200;
258
fb0f8fbf
KP		 259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280}
281
bf13e81b
JN		 282static void
283intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
286static void
287intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
290
291static enum pipe
292vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum port port = intel_dig_port->port;
299 enum pipe pipe;
300
301 /* modeset should have pipe */
302 if (crtc)
303 return to_intel_crtc(crtc)->pipe;
304
305 /* init time, try to find a pipe with this port selected */
306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
308 PANEL_PORT_SELECT_MASK;
309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 return pipe;
311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
4be73780 339static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 342 struct drm_i915_private *dev_priv = dev->dev_private;
343
bf13e81b 344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 345}
346
4be73780 347static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 348{
30add22d 349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 350 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
353 enum intel_display_power_domain power_domain;
ebf33b18 354
bb4932c4
ID		 355 power_domain = intel_display_port_power_domain(intel_encoder);
356 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 358}
359
9b984dae
KP		 360static void
361intel_dp_check_edp(struct intel_dp *intel_dp)
362{
30add22d 363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 364 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 365
9b984dae
KP		 366 if (!is_edp(intel_dp))
367 return;
453c5420 368
4be73780 369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 370 WARN(1, "eDP powered off while attempting aux channel communication.\n");
371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 372 I915_READ(_pp_stat_reg(intel_dp)),
373 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 374 }
375}
376
9ee32fea
DV		 377static uint32_t
378intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
379{
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 384 uint32_t status;
385 bool done;
386
ef04f00d 387#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 388 if (has_aux_irq)
b18ac466 389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 390 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 391 else
392 done = wait_for_atomic(C, 10) == 0;
393 if (!done)
394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
395 has_aux_irq);
396#undef C
397
398 return status;
399}
400
ec5b01dd 401static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 402{
174edf1f
PZ		 403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
404 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 405
ec5b01dd
DL		 406 /*
407 * The clock divider is based off the hrawclk, and would like to run at
408 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 409 */
ec5b01dd
DL		 410 return index ? 0 : intel_hrawclk(dev) / 2;
411}
412
413static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
416 struct drm_device *dev = intel_dig_port->base.base.dev;
417
418 if (index)
419 return 0;
420
421 if (intel_dig_port->port == PORT_A) {
422 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 423 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 424 else
b84a1cf8 425 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 426 } else {
427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
428 }
429}
430
431static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct drm_device *dev = intel_dig_port->base.base.dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436
437 if (intel_dig_port->port == PORT_A) {
438 if (index)
439 return 0;
440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
442 /* Workaround for non-ULT HSW */
bc86625a
CW		 443 switch (index) {
444 case 0: return 63;
445 case 1: return 72;
446 default: return 0;
447 }
ec5b01dd 448 } else {
bc86625a 449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 450 }
b84a1cf8
RV		 451}
452
ec5b01dd
DL		 453static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
454{
455 return index ? 0 : 100;
456}
457
5ed12a19
DL		 458static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
459 bool has_aux_irq,
460 int send_bytes,
461 uint32_t aux_clock_divider)
462{
463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
464 struct drm_device *dev = intel_dig_port->base.base.dev;
465 uint32_t precharge, timeout;
466
467 if (IS_GEN6(dev))
468 precharge = 3;
469 else
470 precharge = 5;
471
472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
474 else
475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
476
477 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 478 DP_AUX_CH_CTL_DONE |
5ed12a19 479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 481 timeout |
788d4433 482 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 486}
487
b84a1cf8
RV		 488static int
489intel_dp_aux_ch(struct intel_dp *intel_dp,
490 uint8_t *send, int send_bytes,
491 uint8_t *recv, int recv_size)
492{
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
497 uint32_t ch_data = ch_ctl + 4;
bc86625a 498 uint32_t aux_clock_divider;
b84a1cf8
RV		 499 int i, ret, recv_bytes;
500 uint32_t status;
5ed12a19 501 int try, clock = 0;
4e6b788c 502 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 503 bool vdd;
504
505 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 506
507 /* dp aux is extremely sensitive to irq latency, hence request the
508 * lowest possible wakeup latency and so prevent the cpu from going into
509 * deep sleep states.
510 */
511 pm_qos_update_request(&dev_priv->pm_qos, 0);
512
513 intel_dp_check_edp(intel_dp);
5eb08b69 514
c67a470b
PZ		 515 intel_aux_display_runtime_get(dev_priv);
516
11bee43e
JB		 517 /* Try to wait for any previous AUX channel activity */
518 for (try = 0; try < 3; try++) {
ef04f00d 519 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
521 break;
522 msleep(1);
523 }
524
525 if (try == 3) {
526 WARN(1, "dp_aux_ch not started status 0x%08x\n",
527 I915_READ(ch_ctl));
9ee32fea
DV		 528 ret = -EBUSY;
529 goto out;
4f7f7b7e
CW		 530 }
531
46a5ae9f
PZ		 532 /* Only 5 data registers! */
533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
534 ret = -E2BIG;
535 goto out;
536 }
537
ec5b01dd 538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
540 has_aux_irq,
541 send_bytes,
542 aux_clock_divider);
5ed12a19 543
bc86625a
CW		 544 /* Must try at least 3 times according to DP spec */
545 for (try = 0; try < 5; try++) {
546 /* Load the send data into the aux channel data registers */
547 for (i = 0; i < send_bytes; i += 4)
548 I915_WRITE(ch_data + i,
549 pack_aux(send + i, send_bytes - i));
550
551 /* Send the command and wait for it to complete */
5ed12a19 552 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 553
554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
555
556 /* Clear done status and any errors */
557 I915_WRITE(ch_ctl,
558 status |
559 DP_AUX_CH_CTL_DONE |
560 DP_AUX_CH_CTL_TIME_OUT_ERROR |
561 DP_AUX_CH_CTL_RECEIVE_ERROR);
562
563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
564 DP_AUX_CH_CTL_RECEIVE_ERROR))
565 continue;
566 if (status & DP_AUX_CH_CTL_DONE)
567 break;
568 }
4f7f7b7e 569 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 570 break;
571 }
572
a4fc5ed6 573 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -EBUSY;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Check for timeout or receive error.
580 * Timeouts occur when the sink is not connected
581 */
a5b3da54 582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 584 ret = -EIO;
585 goto out;
a5b3da54 586 }
1ae8c0a5
KP		 587
588 /* Timeouts occur when the device isn't connected, so they're
589 * "normal" -- don't fill the kernel log with these */
a5b3da54 590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 592 ret = -ETIMEDOUT;
593 goto out;
a4fc5ed6
KP		 594 }
595
596 /* Unload any bytes sent back from the other side */
597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 599 if (recv_bytes > recv_size)
600 recv_bytes = recv_size;
0206e353 601
4f7f7b7e
CW		 602 for (i = 0; i < recv_bytes; i += 4)
603 unpack_aux(I915_READ(ch_data + i),
604 recv + i, recv_bytes - i);
a4fc5ed6 605
9ee32fea
DV		 606 ret = recv_bytes;
607out:
608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 609 intel_aux_display_runtime_put(dev_priv);
9ee32fea 610
884f19e9
JN		 611 if (vdd)
612 edp_panel_vdd_off(intel_dp, false);
613
9ee32fea 614 return ret;
a4fc5ed6
KP		 615}
616
a6c8aff0
JN		 617#define BARE_ADDRESS_SIZE 3
618#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 619static ssize_t
620intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 621{
9d1a1031
JN		 622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
623 uint8_t txbuf[20], rxbuf[20];
624 size_t txsize, rxsize;
a4fc5ed6 625 int ret;
a4fc5ed6 626
9d1a1031
JN		 627 txbuf[0] = msg->request << 4;
628 txbuf[1] = msg->address >> 8;
629 txbuf[2] = msg->address & 0xff;
630 txbuf[3] = msg->size - 1;
46a5ae9f 631
9d1a1031
JN		 632 switch (msg->request & ~DP_AUX_I2C_MOT) {
633 case DP_AUX_NATIVE_WRITE:
634 case DP_AUX_I2C_WRITE:
a6c8aff0 635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 636 rxsize = 1;
f51a44b9 637
9d1a1031
JN		 638 if (WARN_ON(txsize > 20))
639 return -E2BIG;
a4fc5ed6 640
9d1a1031 641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 646
9d1a1031
JN		 647 /* Return payload size. */
648 ret = msg->size;
649 }
650 break;
46a5ae9f 651
9d1a1031
JN		 652 case DP_AUX_NATIVE_READ:
653 case DP_AUX_I2C_READ:
a6c8aff0 654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 655 rxsize = msg->size + 1;
a4fc5ed6 656
9d1a1031
JN		 657 if (WARN_ON(rxsize > 20))
658 return -E2BIG;
a4fc5ed6 659
9d1a1031
JN		 660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
661 if (ret > 0) {
662 msg->reply = rxbuf[0] >> 4;
663 /*
664 * Assume happy day, and copy the data. The caller is
665 * expected to check msg->reply before touching it.
666 *
667 * Return payload size.
668 */
669 ret--;
670 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 671 }
9d1a1031
JN		 672 break;
673
674 default:
675 ret = -EINVAL;
676 break;
a4fc5ed6 677 }
f51a44b9 678
9d1a1031 679 return ret;
a4fc5ed6
KP		 680}
681
9d1a1031
JN		 682static void
683intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
684{
685 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 enum port port = intel_dig_port->port;
0b99836f 688 const char *name = NULL;
ab2c0672
DA		 689 int ret;
690
33ad6626
JN		 691 switch (port) {
692 case PORT_A:
693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 694 name = "DPDDC-A";
ab2c0672 695 break;
33ad6626
JN		 696 case PORT_B:
697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 698 name = "DPDDC-B";
ab2c0672 699 break;
33ad6626
JN		 700 case PORT_C:
701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 702 name = "DPDDC-C";
ab2c0672 703 break;
33ad6626
JN		 704 case PORT_D:
705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 706 name = "DPDDC-D";
33ad6626
JN		 707 break;
708 default:
709 BUG();
ab2c0672
DA		 710 }
711
33ad6626
JN		 712 if (!HAS_DDI(dev))
713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 714
0b99836f 715 intel_dp->aux.name = name;
9d1a1031
JN		 716 intel_dp->aux.dev = dev->dev;
717 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 718
0b99836f
JN		 719 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
720 connector->base.kdev->kobj.name);
8316f337 721
4f71d0cb 722 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 723 if (ret < 0) {
4f71d0cb 724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 725 name, ret);
726 return;
ab2c0672 727 }
8a5e6aeb 728
0b99836f
JN		 729 ret = sysfs_create_link(&connector->base.kdev->kobj,
730 &intel_dp->aux.ddc.dev.kobj,
731 intel_dp->aux.ddc.dev.kobj.name);
732 if (ret < 0) {
733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 734 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 735 }
a4fc5ed6
KP		 736}
737
80f65de3
ID		 738static void
739intel_dp_connector_unregister(struct intel_connector *intel_connector)
740{
741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
742
743 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 744 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 745 intel_connector_unregister(intel_connector);
746}
747
c6bb3538
DV		 748static void
749intel_dp_set_clock(struct intel_encoder *encoder,
750 struct intel_crtc_config *pipe_config, int link_bw)
751{
752 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 753 const struct dp_link_dpll *divisor = NULL;
754 int i, count = 0;
c6bb3538
DV		 755
756 if (IS_G4X(dev)) {
9dd4ffdf
CML		 757 divisor = gen4_dpll;
758 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 759 } else if (IS_HASWELL(dev)) {
760 /* Haswell has special-purpose DP DDI clocks. */
761 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 762 divisor = pch_dpll;
763 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 764 } else if (IS_CHERRYVIEW(dev)) {
765 divisor = chv_dpll;
766 count = ARRAY_SIZE(chv_dpll);
c6bb3538 767 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 768 divisor = vlv_dpll;
769 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 770 }
9dd4ffdf
CML		 771
772 if (divisor && count) {
773 for (i = 0; i < count; i++) {
774 if (link_bw == divisor[i].link_bw) {
775 pipe_config->dpll = divisor[i].dpll;
776 pipe_config->clock_set = true;
777 break;
778 }
779 }
c6bb3538
DV		 780 }
781}
782
439d7ac0
PB		 783static void
784intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
785{
786 struct drm_device *dev = crtc->base.dev;
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 enum transcoder transcoder = crtc->config.cpu_transcoder;
789
790 I915_WRITE(PIPE_DATA_M2(transcoder),
791 TU_SIZE(m_n->tu) | m_n->gmch_m);
792 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
793 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
794 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
795}
796
00c09d70 797bool
5bfe2ac0
DV		 798intel_dp_compute_config(struct intel_encoder *encoder,
799 struct intel_crtc_config *pipe_config)
a4fc5ed6 800{
5bfe2ac0 801 struct drm_device *dev = encoder->base.dev;
36008365 802 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 803 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 805 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 806 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 807 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 808 int lane_count, clock;
56071a20 809 int min_lane_count = 1;
eeb6324d 810 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 811 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 812 int min_clock = 0;
06ea66b6 813 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 814 int bpp, mode_rate;
06ea66b6 815 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 816 int link_avail, link_clock;
a4fc5ed6 817
bc7d38a4 818 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 819 pipe_config->has_pch_encoder = true;
820
03afc4a2 821 pipe_config->has_dp_encoder = true;
9ed109a7 822 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 823
dd06f90e
JN		 824 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
825 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
826 adjusted_mode);
2dd24552
JB		 827 if (!HAS_PCH_SPLIT(dev))
828 intel_gmch_panel_fitting(intel_crtc, pipe_config,
829 intel_connector->panel.fitting_mode);
830 else
b074cec8
JB		 831 intel_pch_panel_fitting(intel_crtc, pipe_config,
832 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 833 }
834
cb1793ce 835 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 836 return false;
837
083f9560
DV		 838 DRM_DEBUG_KMS("DP link computation with max lane count %i "
839 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 840 max_lane_count, bws[max_clock],
841 adjusted_mode->crtc_clock);
083f9560 842
36008365
DV		 843 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
844 * bpc in between. */
3e7ca985 845 bpp = pipe_config->pipe_bpp;
56071a20
JN		 846 if (is_edp(intel_dp)) {
847 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
848 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
849 dev_priv->vbt.edp_bpp);
850 bpp = dev_priv->vbt.edp_bpp;
851 }
852
f4cdbc21
JN		 853 if (IS_BROADWELL(dev)) {
854 /* Yes, it's an ugly hack. */
855 min_lane_count = max_lane_count;
856 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
857 min_lane_count);
858 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 859 min_lane_count = min(dev_priv->vbt.edp_lanes,
860 max_lane_count);
861 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
862 min_lane_count);
863 }
864
865 if (dev_priv->vbt.edp_rate) {
866 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
867 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
868 bws[min_clock]);
869 }
7984211e 870 }
657445fe 871
36008365 872 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 873 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
874 bpp);
36008365 875
56071a20
JN		 876 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
877 for (clock = min_clock; clock <= max_clock; clock++) {
36008365
DV		 878 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
879 link_avail = intel_dp_max_data_rate(link_clock,
880 lane_count);
881
882 if (mode_rate <= link_avail) {
883 goto found;
884 }
885 }
886 }
887 }
c4867936 888
36008365 889 return false;
3685a8f3 890
36008365 891found:
55bc60db
VS		 892 if (intel_dp->color_range_auto) {
893 /*
894 * See:
895 * CEA-861-E - 5.1 Default Encoding Parameters
896 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
897 */
18316c8c 898 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 899 intel_dp->color_range = DP_COLOR_RANGE_16_235;
900 else
901 intel_dp->color_range = 0;
902 }
903
3685a8f3 904 if (intel_dp->color_range)
50f3b016 905 pipe_config->limited_color_range = true;
a4fc5ed6 906
36008365
DV		 907 intel_dp->link_bw = bws[clock];
908 intel_dp->lane_count = lane_count;
657445fe 909 pipe_config->pipe_bpp = bpp;
ff9a6750 910 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 911
36008365
DV		 912 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
913 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 914 pipe_config->port_clock, bpp);
36008365
DV		 915 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
916 mode_rate, link_avail);
a4fc5ed6 917
03afc4a2 918 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 919 adjusted_mode->crtc_clock,
920 pipe_config->port_clock,
03afc4a2 921 &pipe_config->dp_m_n);
9d1a455b 922
439d7ac0
PB		 923 if (intel_connector->panel.downclock_mode != NULL &&
924 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
925 intel_link_compute_m_n(bpp, lane_count,
926 intel_connector->panel.downclock_mode->clock,
927 pipe_config->port_clock,
928 &pipe_config->dp_m2_n2);
929 }
930
c6bb3538
DV		 931 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
932
03afc4a2 933 return true;
a4fc5ed6
KP		 934}
935
7c62a164 936static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 937{
7c62a164
DV		 938 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
939 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
940 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 941 struct drm_i915_private *dev_priv = dev->dev_private;
942 u32 dpa_ctl;
943
ff9a6750 944 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 945 dpa_ctl = I915_READ(DP_A);
946 dpa_ctl &= ~DP_PLL_FREQ_MASK;
947
ff9a6750 948 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 949 /* For a long time we've carried around a ILK-DevA w/a for the
950 * 160MHz clock. If we're really unlucky, it's still required.
951 */
952 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 953 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 954 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 955 } else {
956 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 957 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 958 }
1ce17038 959
ea9b6006
DV		 960 I915_WRITE(DP_A, dpa_ctl);
961
962 POSTING_READ(DP_A);
963 udelay(500);
964}
965
8ac33ed3 966static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 967{
b934223d 968 struct drm_device *dev = encoder->base.dev;
417e822d 969 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 970 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 971 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 972 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
973 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 974
417e822d 975 /*
1a2eb460 976 * There are four kinds of DP registers:
417e822d
KP		 977 *
978 * IBX PCH
1a2eb460
KP		 979 * SNB CPU
980 * IVB CPU
417e822d
KP		 981 * CPT PCH
982 *
983 * IBX PCH and CPU are the same for almost everything,
984 * except that the CPU DP PLL is configured in this
985 * register
986 *
987 * CPT PCH is quite different, having many bits moved
988 * to the TRANS_DP_CTL register instead. That
989 * configuration happens (oddly) in ironlake_pch_enable
990 */
9c9e7927 991
417e822d
KP		 992 /* Preserve the BIOS-computed detected bit. This is
993 * supposed to be read-only.
994 */
995 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 996
417e822d 997 /* Handle DP bits in common between all three register formats */
417e822d 998 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 999 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1000
9ed109a7 1001 if (crtc->config.has_audio) {
e0dac65e 1002 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1003 pipe_name(crtc->pipe));
ea5b213a 1004 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1005 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1006 }
247d89f6 1007
417e822d 1008 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1009
bc7d38a4 1010 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1011 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1012 intel_dp->DP |= DP_SYNC_HS_HIGH;
1013 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1014 intel_dp->DP |= DP_SYNC_VS_HIGH;
1015 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1016
6aba5b6c 1017 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1018 intel_dp->DP |= DP_ENHANCED_FRAMING;
1019
7c62a164 1020 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1021 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1022 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1023 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1024
1025 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1026 intel_dp->DP |= DP_SYNC_HS_HIGH;
1027 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1028 intel_dp->DP |= DP_SYNC_VS_HIGH;
1029 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1030
6aba5b6c 1031 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1032 intel_dp->DP |= DP_ENHANCED_FRAMING;
1033
44f37d1f
CML		 1034 if (!IS_CHERRYVIEW(dev)) {
1035 if (crtc->pipe == 1)
1036 intel_dp->DP |= DP_PIPEB_SELECT;
1037 } else {
1038 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1039 }
417e822d
KP		 1040 } else {
1041 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1042 }
a4fc5ed6
KP		 1043}
1044
ffd6749d
PZ		 1045#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1046#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1047
1a5ef5b7
PZ		 1048#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1049#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1050
ffd6749d
PZ		 1051#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1052#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1053
4be73780 1054static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1055 u32 mask,
1056 u32 value)
bd943159 1057{
30add22d 1058 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1059 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1060 u32 pp_stat_reg, pp_ctrl_reg;
1061
bf13e81b
JN		 1062 pp_stat_reg = _pp_stat_reg(intel_dp);
1063 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1064
99ea7127 1065 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1066 mask, value,
1067 I915_READ(pp_stat_reg),
1068 I915_READ(pp_ctrl_reg));
32ce697c 1069
453c5420 1070 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1071 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1072 I915_READ(pp_stat_reg),
1073 I915_READ(pp_ctrl_reg));
32ce697c 1074 }
54c136d4
CW		 1075
1076 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1077}
32ce697c 1078
4be73780 1079static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1080{
1081 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1082 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1083}
1084
4be73780 1085static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1086{
1087 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1088 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1089}
1090
4be73780 1091static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1092{
1093 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1094
1095 /* When we disable the VDD override bit last we have to do the manual
1096 * wait. */
1097 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1098 intel_dp->panel_power_cycle_delay);
1099
4be73780 1100 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1101}
1102
4be73780 1103static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1104{
1105 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1106 intel_dp->backlight_on_delay);
1107}
1108
4be73780 1109static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1110{
1111 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1112 intel_dp->backlight_off_delay);
1113}
99ea7127 1114
832dd3c1
KP		 1115/* Read the current pp_control value, unlocking the register if it
1116 * is locked
1117 */
1118
453c5420 1119static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1120{
453c5420
JB		 1121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1123 u32 control;
832dd3c1 1124
bf13e81b 1125 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1126 control &= ~PANEL_UNLOCK_MASK;
1127 control |= PANEL_UNLOCK_REGS;
1128 return control;
bd943159
KP		 1129}
1130
adddaaf4 1131static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1132{
30add22d 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1134 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1135 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1136 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1137 enum intel_display_power_domain power_domain;
5d613501 1138 u32 pp;
453c5420 1139 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1140 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1141
97af61f5 1142 if (!is_edp(intel_dp))
adddaaf4 1143 return false;
bd943159
KP		 1144
1145 intel_dp->want_panel_vdd = true;
99ea7127 1146
4be73780 1147 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1148 return need_to_disable;
b0665d57 1149
4e6e1a54
ID		 1150 power_domain = intel_display_port_power_domain(intel_encoder);
1151 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1152
b0665d57 1153 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1154
4be73780
DV		 1155 if (!edp_have_panel_power(intel_dp))
1156 wait_panel_power_cycle(intel_dp);
99ea7127 1157
453c5420 1158 pp = ironlake_get_pp_control(intel_dp);
5d613501 1159 pp |= EDP_FORCE_VDD;
ebf33b18 1160
bf13e81b
JN		 1161 pp_stat_reg = _pp_stat_reg(intel_dp);
1162 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1163
1164 I915_WRITE(pp_ctrl_reg, pp);
1165 POSTING_READ(pp_ctrl_reg);
1166 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1167 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1168 /*
1169 * If the panel wasn't on, delay before accessing aux channel
1170 */
4be73780 1171 if (!edp_have_panel_power(intel_dp)) {
bd943159 1172 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1173 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1174 }
adddaaf4
JN		 1175
1176 return need_to_disable;
1177}
1178
b80d6c78 1179void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1180{
1181 if (is_edp(intel_dp)) {
1182 bool vdd = _edp_panel_vdd_on(intel_dp);
1183
1184 WARN(!vdd, "eDP VDD already requested on\n");
1185 }
5d613501
JB		 1186}
1187
4be73780 1188static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1189{
30add22d 1190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 u32 pp;
453c5420 1193 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1194
51fd371b 1195 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1196
4be73780 1197 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1198 struct intel_digital_port *intel_dig_port =
1199 dp_to_dig_port(intel_dp);
1200 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1201 enum intel_display_power_domain power_domain;
1202
b0665d57
PZ		 1203 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1204
453c5420 1205 pp = ironlake_get_pp_control(intel_dp);
bd943159 1206 pp &= ~EDP_FORCE_VDD;
bd943159 1207
9f08ef59
PZ		 1208 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1209 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1210
1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
99ea7127 1213
453c5420
JB		 1214 /* Make sure sequencer is idle before allowing subsequent activity */
1215 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1216 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1217
1218 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1219 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1220
4e6e1a54
ID		 1221 power_domain = intel_display_port_power_domain(intel_encoder);
1222 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1223 }
1224}
5d613501 1225
4be73780 1226static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1227{
1228 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1229 struct intel_dp, panel_vdd_work);
30add22d 1230 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1231
51fd371b 1232 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1233 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1234 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1235}
1236
4be73780 1237static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1238{
97af61f5
KP		 1239 if (!is_edp(intel_dp))
1240 return;
5d613501 1241
bd943159 1242 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1243
bd943159
KP		 1244 intel_dp->want_panel_vdd = false;
1245
1246 if (sync) {
4be73780 1247 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1248 } else {
1249 /*
1250 * Queue the timer to fire a long
1251 * time from now (relative to the power down delay)
1252 * to keep the panel power up across a sequence of operations
1253 */
1254 schedule_delayed_work(&intel_dp->panel_vdd_work,
1255 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1256 }
5d613501
JB		 1257}
1258
4be73780 1259void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1260{
30add22d 1261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1262 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1263 u32 pp;
453c5420 1264 u32 pp_ctrl_reg;
9934c132 1265
97af61f5 1266 if (!is_edp(intel_dp))
bd943159 1267 return;
99ea7127
KP		 1268
1269 DRM_DEBUG_KMS("Turn eDP power on\n");
1270
4be73780 1271 if (edp_have_panel_power(intel_dp)) {
99ea7127 1272 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1273 return;
99ea7127 1274 }
9934c132 1275
4be73780 1276 wait_panel_power_cycle(intel_dp);
37c6c9b0 1277
bf13e81b 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1279 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1280 if (IS_GEN5(dev)) {
1281 /* ILK workaround: disable reset around power sequence */
1282 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1283 I915_WRITE(pp_ctrl_reg, pp);
1284 POSTING_READ(pp_ctrl_reg);
05ce1a49 1285 }
37c6c9b0 1286
1c0ae80a 1287 pp |= POWER_TARGET_ON;
99ea7127
KP		 1288 if (!IS_GEN5(dev))
1289 pp |= PANEL_POWER_RESET;
1290
453c5420
JB		 1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
9934c132 1293
4be73780 1294 wait_panel_on(intel_dp);
dce56b3c 1295 intel_dp->last_power_on = jiffies;
9934c132 1296
05ce1a49
KP		 1297 if (IS_GEN5(dev)) {
1298 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
05ce1a49 1301 }
9934c132
JB		 1302}
1303
4be73780 1304void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1305{
4e6e1a54
ID		 1306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1308 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1309 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1310 enum intel_display_power_domain power_domain;
99ea7127 1311 u32 pp;
453c5420 1312 u32 pp_ctrl_reg;
9934c132 1313
97af61f5
KP		 1314 if (!is_edp(intel_dp))
1315 return;
37c6c9b0 1316
99ea7127 1317 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1318
4be73780 1319 edp_wait_backlight_off(intel_dp);
dce56b3c 1320
24f3e092
JN		 1321 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1322
453c5420 1323 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1324 /* We need to switch off panel power _and_ force vdd, for otherwise some
1325 * panels get very unhappy and cease to work. */
b3064154
PJ		 1326 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1327 EDP_BLC_ENABLE);
453c5420 1328
bf13e81b 1329 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1330
849e39f5
PZ		 1331 intel_dp->want_panel_vdd = false;
1332
453c5420
JB		 1333 I915_WRITE(pp_ctrl_reg, pp);
1334 POSTING_READ(pp_ctrl_reg);
9934c132 1335
dce56b3c 1336 intel_dp->last_power_cycle = jiffies;
4be73780 1337 wait_panel_off(intel_dp);
849e39f5
PZ		 1338
1339 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1340 power_domain = intel_display_port_power_domain(intel_encoder);
1341 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1342}
1343
4be73780 1344void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1345{
da63a9f2
PZ		 1346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1347 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 u32 pp;
453c5420 1350 u32 pp_ctrl_reg;
32f9d658 1351
f01eca2e
KP		 1352 if (!is_edp(intel_dp))
1353 return;
1354
28c97730 1355 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1356 /*
1357 * If we enable the backlight right away following a panel power
1358 * on, we may see slight flicker as the panel syncs with the eDP
1359 * link. So delay a bit to make sure the image is solid before
1360 * allowing it to appear.
1361 */
4be73780 1362 wait_backlight_on(intel_dp);
453c5420 1363 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1364 pp |= EDP_BLC_ENABLE;
453c5420 1365
bf13e81b 1366 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1367
1368 I915_WRITE(pp_ctrl_reg, pp);
1369 POSTING_READ(pp_ctrl_reg);
035aa3de 1370
752aa88a 1371 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1372}
1373
4be73780 1374void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1375{
30add22d 1376 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378 u32 pp;
453c5420 1379 u32 pp_ctrl_reg;
32f9d658 1380
f01eca2e
KP		 1381 if (!is_edp(intel_dp))
1382 return;
1383
752aa88a 1384 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1385
28c97730 1386 DRM_DEBUG_KMS("\n");
453c5420 1387 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1388 pp &= ~EDP_BLC_ENABLE;
453c5420 1389
bf13e81b 1390 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1391
1392 I915_WRITE(pp_ctrl_reg, pp);
1393 POSTING_READ(pp_ctrl_reg);
dce56b3c 1394 intel_dp->last_backlight_off = jiffies;
32f9d658 1395}
a4fc5ed6 1396
2bd2ad64 1397static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1398{
da63a9f2
PZ		 1399 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1400 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1401 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 u32 dpa_ctl;
1404
2bd2ad64
DV		 1405 assert_pipe_disabled(dev_priv,
1406 to_intel_crtc(crtc)->pipe);
1407
d240f20f
JB		 1408 DRM_DEBUG_KMS("\n");
1409 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1410 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1411 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1412
1413 /* We don't adjust intel_dp->DP while tearing down the link, to
1414 * facilitate link retraining (e.g. after hotplug). Hence clear all
1415 * enable bits here to ensure that we don't enable too much. */
1416 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1417 intel_dp->DP |= DP_PLL_ENABLE;
1418 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1419 POSTING_READ(DP_A);
1420 udelay(200);
d240f20f
JB		 1421}
1422
2bd2ad64 1423static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1424{
da63a9f2
PZ		 1425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1426 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1427 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 u32 dpa_ctl;
1430
2bd2ad64
DV		 1431 assert_pipe_disabled(dev_priv,
1432 to_intel_crtc(crtc)->pipe);
1433
d240f20f 1434 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1435 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1436 "dp pll off, should be on\n");
1437 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1438
1439 /* We can't rely on the value tracked for the DP register in
1440 * intel_dp->DP because link_down must not change that (otherwise link
1441 * re-training will fail. */
298b0b39 1442 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1443 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1444 POSTING_READ(DP_A);
d240f20f
JB		 1445 udelay(200);
1446}
1447
c7ad3810 1448/* If the sink supports it, try to set the power state appropriately */
c19b0669 1449void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1450{
1451 int ret, i;
1452
1453 /* Should have a valid DPCD by this point */
1454 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1455 return;
1456
1457 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1458 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1459 DP_SET_POWER_D3);
c7ad3810
JB		 1460 if (ret != 1)
1461 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1462 } else {
1463 /*
1464 * When turning on, we need to retry for 1ms to give the sink
1465 * time to wake up.
1466 */
1467 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1468 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1469 DP_SET_POWER_D0);
c7ad3810
JB		 1470 if (ret == 1)
1471 break;
1472 msleep(1);
1473 }
1474 }
1475}
1476
19d8fe15
DV		 1477static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1478 enum pipe *pipe)
d240f20f 1479{
19d8fe15 1480 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1481 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1482 struct drm_device *dev = encoder->base.dev;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1484 enum intel_display_power_domain power_domain;
1485 u32 tmp;
1486
1487 power_domain = intel_display_port_power_domain(encoder);
1488 if (!intel_display_power_enabled(dev_priv, power_domain))
1489 return false;
1490
1491 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1492
1493 if (!(tmp & DP_PORT_EN))
1494 return false;
1495
bc7d38a4 1496 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1497 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1498 } else if (IS_CHERRYVIEW(dev)) {
1499 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1500 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1501 *pipe = PORT_TO_PIPE(tmp);
1502 } else {
1503 u32 trans_sel;
1504 u32 trans_dp;
1505 int i;
1506
1507 switch (intel_dp->output_reg) {
1508 case PCH_DP_B:
1509 trans_sel = TRANS_DP_PORT_SEL_B;
1510 break;
1511 case PCH_DP_C:
1512 trans_sel = TRANS_DP_PORT_SEL_C;
1513 break;
1514 case PCH_DP_D:
1515 trans_sel = TRANS_DP_PORT_SEL_D;
1516 break;
1517 default:
1518 return true;
1519 }
1520
1521 for_each_pipe(i) {
1522 trans_dp = I915_READ(TRANS_DP_CTL(i));
1523 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1524 *pipe = i;
1525 return true;
1526 }
1527 }
19d8fe15 1528
4a0833ec
DV		 1529 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1530 intel_dp->output_reg);
1531 }
d240f20f 1532
19d8fe15
DV		 1533 return true;
1534}
d240f20f 1535
045ac3b5
JB		 1536static void intel_dp_get_config(struct intel_encoder *encoder,
1537 struct intel_crtc_config *pipe_config)
1538{
1539 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1540 u32 tmp, flags = 0;
63000ef6
XZ		 1541 struct drm_device *dev = encoder->base.dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 enum port port = dp_to_dig_port(intel_dp)->port;
1544 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1545 int dotclock;
045ac3b5 1546
9ed109a7
DV		 1547 tmp = I915_READ(intel_dp->output_reg);
1548 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1549 pipe_config->has_audio = true;
1550
63000ef6 1551 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1552 if (tmp & DP_SYNC_HS_HIGH)
1553 flags |= DRM_MODE_FLAG_PHSYNC;
1554 else
1555 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1556
63000ef6
XZ		 1557 if (tmp & DP_SYNC_VS_HIGH)
1558 flags |= DRM_MODE_FLAG_PVSYNC;
1559 else
1560 flags |= DRM_MODE_FLAG_NVSYNC;
1561 } else {
1562 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1563 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1564 flags |= DRM_MODE_FLAG_PHSYNC;
1565 else
1566 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1567
63000ef6
XZ		 1568 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1569 flags |= DRM_MODE_FLAG_PVSYNC;
1570 else
1571 flags |= DRM_MODE_FLAG_NVSYNC;
1572 }
045ac3b5
JB		 1573
1574 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1575
eb14cb74
VS		 1576 pipe_config->has_dp_encoder = true;
1577
1578 intel_dp_get_m_n(crtc, pipe_config);
1579
18442d08 1580 if (port == PORT_A) {
f1f644dc
JB		 1581 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1582 pipe_config->port_clock = 162000;
1583 else
1584 pipe_config->port_clock = 270000;
1585 }
18442d08
VS		 1586
1587 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1588 &pipe_config->dp_m_n);
1589
1590 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1591 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1592
241bfc38 1593 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1594
c6cd2ee2
JN		 1595 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1596 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1597 /*
1598 * This is a big fat ugly hack.
1599 *
1600 * Some machines in UEFI boot mode provide us a VBT that has 18
1601 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1602 * unknown we fail to light up. Yet the same BIOS boots up with
1603 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1604 * max, not what it tells us to use.
1605 *
1606 * Note: This will still be broken if the eDP panel is not lit
1607 * up by the BIOS, and thus we can't get the mode at module
1608 * load.
1609 */
1610 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1611 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1612 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1613 }
045ac3b5
JB		 1614}
1615
34eb7579 1616static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1617{
34eb7579 1618 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1619}
1620
2b28bb1b
RV		 1621static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1622{
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624
18b5992c 1625 if (!HAS_PSR(dev))
2b28bb1b
RV		 1626 return false;
1627
18b5992c 1628 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1629}
1630
1631static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1632 struct edp_vsc_psr *vsc_psr)
1633{
1634 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1635 struct drm_device *dev = dig_port->base.base.dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1638 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1639 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1640 uint32_t *data = (uint32_t *) vsc_psr;
1641 unsigned int i;
1642
1643 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1644 the video DIP being updated before program video DIP data buffer
1645 registers for DIP being updated. */
1646 I915_WRITE(ctl_reg, 0);
1647 POSTING_READ(ctl_reg);
1648
1649 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1650 if (i < sizeof(struct edp_vsc_psr))
1651 I915_WRITE(data_reg + i, *data++);
1652 else
1653 I915_WRITE(data_reg + i, 0);
1654 }
1655
1656 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1657 POSTING_READ(ctl_reg);
1658}
1659
1660static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1661{
1662 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct edp_vsc_psr psr_vsc;
1665
6118efe5 1666 if (dev_priv->psr.setup_done)
2b28bb1b
RV		 1667 return;
1668
1669 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1670 memset(&psr_vsc, 0, sizeof(psr_vsc));
1671 psr_vsc.sdp_header.HB0 = 0;
1672 psr_vsc.sdp_header.HB1 = 0x7;
1673 psr_vsc.sdp_header.HB2 = 0x2;
1674 psr_vsc.sdp_header.HB3 = 0x8;
1675 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1676
1677 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1678 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1679 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b 1680
6118efe5 1681 dev_priv->psr.setup_done = true;
2b28bb1b
RV		 1682}
1683
1684static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1685{
1686 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1687 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1688 uint32_t aux_clock_divider;
2b28bb1b
RV		 1689 int precharge = 0x3;
1690 int msg_size = 5; /* Header(4) + Message(1) */
1691
ec5b01dd
DL		 1692 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1693
2b28bb1b
RV		 1694 /* Enable PSR in sink */
1695 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1696 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1697 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1698 else
9d1a1031
JN		 1699 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1700 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1701
1702 /* Setup AUX registers */
18b5992c
BW		 1703 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1704 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1705 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1706 DP_AUX_CH_CTL_TIME_OUT_400us |
1707 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1708 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1709 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1710}
1711
1712static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1713{
1714 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 uint32_t max_sleep_time = 0x1f;
1717 uint32_t idle_frames = 1;
1718 uint32_t val = 0x0;
ed8546ac 1719 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1720
1721 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1722 val |= EDP_PSR_LINK_STANDBY;
1723 val |= EDP_PSR_TP2_TP3_TIME_0us;
1724 val |= EDP_PSR_TP1_TIME_0us;
1725 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1726 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1727 } else
1728 val |= EDP_PSR_LINK_DISABLE;
1729
18b5992c 1730 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1731 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1732 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1733 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1734 EDP_PSR_ENABLE);
1735}
1736
3f51e471
RV		 1737static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1738{
1739 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1740 struct drm_device *dev = dig_port->base.base.dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 struct drm_crtc *crtc = dig_port->base.base.crtc;
1743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1744 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1745 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1746
a031d709
RV		 1747 dev_priv->psr.source_ok = false;
1748
3f51e471
RV		 1749 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1750 (dig_port->port != PORT_A)) {
1751 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1752 return false;
1753 }
1754
d330a953 1755 if (!i915.enable_psr) {
105b7c11 1756 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1757 return false;
1758 }
1759
cd234b0b
CW		 1760 crtc = dig_port->base.base.crtc;
1761 if (crtc == NULL) {
1762 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1763 return false;
1764 }
1765
1766 intel_crtc = to_intel_crtc(crtc);
20ddf665 1767 if (!intel_crtc_active(crtc)) {
3f51e471 1768 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1769 return false;
1770 }
1771
f4510a27 1772 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1773 if (obj->tiling_mode != I915_TILING_X ||
1774 obj->fence_reg == I915_FENCE_REG_NONE) {
1775 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1776 return false;
1777 }
1778
1779 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1780 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1781 return false;
1782 }
1783
1784 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1785 S3D_ENABLE) {
1786 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1787 return false;
1788 }
1789
ca73b4f0 1790 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1791 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1792 return false;
1793 }
1794
a031d709 1795 dev_priv->psr.source_ok = true;
3f51e471
RV		 1796 return true;
1797}
1798
3d739d92 1799static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1800{
1801 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1802
3f51e471
RV		 1803 if (!intel_edp_psr_match_conditions(intel_dp) ||
1804 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1805 return;
1806
2b28bb1b
RV		 1807 /* Enable PSR on the panel */
1808 intel_edp_psr_enable_sink(intel_dp);
1809
1810 /* Enable PSR on the host */
1811 intel_edp_psr_enable_source(intel_dp);
1812}
1813
3d739d92
RV		 1814void intel_edp_psr_enable(struct intel_dp *intel_dp)
1815{
1816 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1817
4704c573
RV		 1818 if (!HAS_PSR(dev)) {
1819 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1820 return;
1821 }
1822
34eb7579
RV		 1823 if (!is_edp_psr(intel_dp)) {
1824 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1825 return;
1826 }
1827
16487254
RV		 1828 /* Setup PSR once */
1829 intel_edp_psr_setup(intel_dp);
1830
3d739d92
RV		 1831 if (intel_edp_psr_match_conditions(intel_dp) &&
1832 !intel_edp_is_psr_enabled(dev))
1833 intel_edp_psr_do_enable(intel_dp);
1834}
1835
2b28bb1b
RV		 1836void intel_edp_psr_disable(struct intel_dp *intel_dp)
1837{
1838 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840
1841 if (!intel_edp_is_psr_enabled(dev))
1842 return;
1843
18b5992c
BW		 1844 I915_WRITE(EDP_PSR_CTL(dev),
1845 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1846
1847 /* Wait till PSR is idle */
18b5992c 1848 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1849 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1850 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1851}
1852
3d739d92
RV		 1853void intel_edp_psr_update(struct drm_device *dev)
1854{
16487254 1855 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92
RV		 1856 struct intel_encoder *encoder;
1857 struct intel_dp *intel_dp = NULL;
1858
4704c573
RV		 1859 if (!HAS_PSR(dev))
1860 return;
1861
16487254
RV		 1862 if (!dev_priv->psr.setup_done)
1863 return;
1864
3d739d92
RV		 1865 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1866 if (encoder->type == INTEL_OUTPUT_EDP) {
1867 intel_dp = enc_to_intel_dp(&encoder->base);
1868
3d739d92
RV		 1869 if (!intel_edp_psr_match_conditions(intel_dp))
1870 intel_edp_psr_disable(intel_dp);
1871 else
1872 if (!intel_edp_is_psr_enabled(dev))
1873 intel_edp_psr_do_enable(intel_dp);
1874 }
1875}
1876
e8cb4558 1877static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1878{
e8cb4558 1879 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1880 enum port port = dp_to_dig_port(intel_dp)->port;
1881 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1882
1883 /* Make sure the panel is off before trying to change the mode. But also
1884 * ensure that we have vdd while we switch off the panel. */
24f3e092 1885 intel_edp_panel_vdd_on(intel_dp);
4be73780 1886 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1887 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1888 intel_edp_panel_off(intel_dp);
3739850b
DV		 1889
1890 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1891 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1892 intel_dp_link_down(intel_dp);
d240f20f
JB		 1893}
1894
49277c31 1895static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1896{
2bd2ad64 1897 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1898 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1899
49277c31
VS		 1900 if (port != PORT_A)
1901 return;
1902
1903 intel_dp_link_down(intel_dp);
1904 ironlake_edp_pll_off(intel_dp);
1905}
1906
1907static void vlv_post_disable_dp(struct intel_encoder *encoder)
1908{
1909 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1910
1911 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1912}
1913
580d3811
VS		 1914static void chv_post_disable_dp(struct intel_encoder *encoder)
1915{
1916 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1917 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1918 struct drm_device *dev = encoder->base.dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920 struct intel_crtc *intel_crtc =
1921 to_intel_crtc(encoder->base.crtc);
1922 enum dpio_channel ch = vlv_dport_to_channel(dport);
1923 enum pipe pipe = intel_crtc->pipe;
1924 u32 val;
1925
1926 intel_dp_link_down(intel_dp);
1927
1928 mutex_lock(&dev_priv->dpio_lock);
1929
1930 /* Propagate soft reset to data lane reset */
97fd4d5c 1931 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 1932 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 1933 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 1934
97fd4d5c
VS		 1935 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1936 val |= CHV_PCS_REQ_SOFTRESET_EN;
1937 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1938
1939 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1940 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1941 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1942
1943 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 1944 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 1945 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 1946
1947 mutex_unlock(&dev_priv->dpio_lock);
1948}
1949
e8cb4558 1950static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1951{
e8cb4558
DV		 1952 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1953 struct drm_device *dev = encoder->base.dev;
1954 struct drm_i915_private *dev_priv = dev->dev_private;
1955 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1956
0c33d8d7
DV		 1957 if (WARN_ON(dp_reg & DP_PORT_EN))
1958 return;
5d613501 1959
24f3e092 1960 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1961 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1962 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1963 intel_edp_panel_on(intel_dp);
1964 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1965 intel_dp_complete_link_train(intel_dp);
3ab9c637 1966 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1967}
89b667f8 1968
ecff4f3b
JN		 1969static void g4x_enable_dp(struct intel_encoder *encoder)
1970{
828f5c6e
JN		 1971 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1972
ecff4f3b 1973 intel_enable_dp(encoder);
4be73780 1974 intel_edp_backlight_on(intel_dp);
ab1f90f9 1975}
89b667f8 1976
ab1f90f9
JN		 1977static void vlv_enable_dp(struct intel_encoder *encoder)
1978{
828f5c6e
JN		 1979 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1980
4be73780 1981 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1982}
1983
ecff4f3b 1984static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1985{
1986 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1987 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1988
8ac33ed3
DV		 1989 intel_dp_prepare(encoder);
1990
d41f1efb
DV		 1991 /* Only ilk+ has port A */
1992 if (dport->port == PORT_A) {
1993 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 1994 ironlake_edp_pll_on(intel_dp);
d41f1efb 1995 }
ab1f90f9
JN		 1996}
1997
1998static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1999{
2bd2ad64 2000 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2001 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2002 struct drm_device *dev = encoder->base.dev;
89b667f8 2003 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2004 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2005 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2006 int pipe = intel_crtc->pipe;
bf13e81b 2007 struct edp_power_seq power_seq;
ab1f90f9 2008 u32 val;
a4fc5ed6 2009
ab1f90f9 2010 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2011
ab3c759a 2012 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2013 val = 0;
2014 if (pipe)
2015 val |= (1<<21);
2016 else
2017 val &= ~(1<<21);
2018 val |= 0x001000c4;
ab3c759a
CML		 2019 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2020 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2021 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2022
ab1f90f9
JN		 2023 mutex_unlock(&dev_priv->dpio_lock);
2024
2cac613b
ID		 2025 if (is_edp(intel_dp)) {
2026 /* init power sequencer on this pipe and port */
2027 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2028 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2029 &power_seq);
2030 }
bf13e81b 2031
ab1f90f9
JN		 2032 intel_enable_dp(encoder);
2033
e4607fcf 2034 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2035}
2036
ecff4f3b 2037static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2038{
2039 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2040 struct drm_device *dev = encoder->base.dev;
2041 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2042 struct intel_crtc *intel_crtc =
2043 to_intel_crtc(encoder->base.crtc);
e4607fcf 2044 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2045 int pipe = intel_crtc->pipe;
89b667f8 2046
8ac33ed3
DV		 2047 intel_dp_prepare(encoder);
2048
89b667f8 2049 /* Program Tx lane resets to default */
0980a60f 2050 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2051 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2052 DPIO_PCS_TX_LANE2_RESET |
2053 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2054 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2055 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2056 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2057 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2058 DPIO_PCS_CLK_SOFT_RESET);
2059
2060 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2061 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2063 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2064 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2065}
2066
e4a1d846
CML		 2067static void chv_pre_enable_dp(struct intel_encoder *encoder)
2068{
2069 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2070 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2071 struct drm_device *dev = encoder->base.dev;
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2073 struct edp_power_seq power_seq;
2074 struct intel_crtc *intel_crtc =
2075 to_intel_crtc(encoder->base.crtc);
2076 enum dpio_channel ch = vlv_dport_to_channel(dport);
2077 int pipe = intel_crtc->pipe;
2078 int data, i;
949c1d43 2079 u32 val;
e4a1d846 2080
e4a1d846 2081 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2082
2083 /* Deassert soft data lane reset*/
97fd4d5c 2084 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2085 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2086 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2087
2088 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2089 val |= CHV_PCS_REQ_SOFTRESET_EN;
2090 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2091
2092 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2093 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2094 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2095
97fd4d5c 2096 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2097 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2098 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2099
2100 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2101 for (i = 0; i < 4; i++) {
2102 /* Set the latency optimal bit */
2103 data = (i == 1) ? 0x0 : 0x6;
2104 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2105 data << DPIO_FRC_LATENCY_SHFIT);
2106
2107 /* Set the upar bit */
2108 data = (i == 1) ? 0x0 : 0x1;
2109 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2110 data << DPIO_UPAR_SHIFT);
2111 }
2112
2113 /* Data lane stagger programming */
2114 /* FIXME: Fix up value only after power analysis */
2115
2116 mutex_unlock(&dev_priv->dpio_lock);
2117
2118 if (is_edp(intel_dp)) {
2119 /* init power sequencer on this pipe and port */
2120 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2121 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2122 &power_seq);
2123 }
2124
2125 intel_enable_dp(encoder);
2126
2127 vlv_wait_port_ready(dev_priv, dport);
2128}
2129
9197c88b
VS		 2130static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2131{
2132 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2133 struct drm_device *dev = encoder->base.dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc =
2136 to_intel_crtc(encoder->base.crtc);
2137 enum dpio_channel ch = vlv_dport_to_channel(dport);
2138 enum pipe pipe = intel_crtc->pipe;
2139 u32 val;
2140
2141 mutex_lock(&dev_priv->dpio_lock);
2142
b9e5ac3c
VS		 2143 /* program left/right clock distribution */
2144 if (pipe != PIPE_B) {
2145 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2146 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2147 if (ch == DPIO_CH0)
2148 val |= CHV_BUFLEFTENA1_FORCE;
2149 if (ch == DPIO_CH1)
2150 val |= CHV_BUFRIGHTENA1_FORCE;
2151 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2152 } else {
2153 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2154 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2155 if (ch == DPIO_CH0)
2156 val |= CHV_BUFLEFTENA2_FORCE;
2157 if (ch == DPIO_CH1)
2158 val |= CHV_BUFRIGHTENA2_FORCE;
2159 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2160 }
2161
9197c88b
VS		 2162 /* program clock channel usage */
2163 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2164 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2165 if (pipe != PIPE_B)
2166 val &= ~CHV_PCS_USEDCLKCHANNEL;
2167 else
2168 val |= CHV_PCS_USEDCLKCHANNEL;
2169 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2170
2171 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2172 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2173 if (pipe != PIPE_B)
2174 val &= ~CHV_PCS_USEDCLKCHANNEL;
2175 else
2176 val |= CHV_PCS_USEDCLKCHANNEL;
2177 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2178
2179 /*
2180 * This a a bit weird since generally CL
2181 * matches the pipe, but here we need to
2182 * pick the CL based on the port.
2183 */
2184 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2185 if (pipe != PIPE_B)
2186 val &= ~CHV_CMN_USEDCLKCHANNEL;
2187 else
2188 val |= CHV_CMN_USEDCLKCHANNEL;
2189 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2190
2191 mutex_unlock(&dev_priv->dpio_lock);
2192}
2193
a4fc5ed6 2194/*
df0c237d
JB		 2195 * Native read with retry for link status and receiver capability reads for
2196 * cases where the sink may still be asleep.
9d1a1031
JN		 2197 *
2198 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2199 * supposed to retry 3 times per the spec.
a4fc5ed6 2200 */
9d1a1031
JN		 2201static ssize_t
2202intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2203 void *buffer, size_t size)
a4fc5ed6 2204{
9d1a1031
JN		 2205 ssize_t ret;
2206 int i;
61da5fab 2207
61da5fab 2208 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2209 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2210 if (ret == size)
2211 return ret;
61da5fab
JB		 2212 msleep(1);
2213 }
a4fc5ed6 2214
9d1a1031 2215 return ret;
a4fc5ed6
KP		 2216}
2217
2218/*
2219 * Fetch AUX CH registers 0x202 - 0x207 which contain
2220 * link status information
2221 */
2222static bool
93f62dad 2223intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2224{
9d1a1031
JN		 2225 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2226 DP_LANE0_1_STATUS,
2227 link_status,
2228 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2229}
2230
a4fc5ed6
KP		 2231/*
2232 * These are source-specific values; current Intel hardware supports
2233 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2234 */
a4fc5ed6
KP		 2235
2236static uint8_t
1a2eb460 2237intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2238{
30add22d 2239 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2240 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2241
8f93f4f1 2242 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2243 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2244 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2245 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2246 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2247 return DP_TRAIN_VOLTAGE_SWING_1200;
2248 else
2249 return DP_TRAIN_VOLTAGE_SWING_800;
2250}
2251
2252static uint8_t
2253intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2254{
30add22d 2255 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2256 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2257
8f93f4f1
PZ		 2258 if (IS_BROADWELL(dev)) {
2259 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2260 case DP_TRAIN_VOLTAGE_SWING_400:
2261 case DP_TRAIN_VOLTAGE_SWING_600:
2262 return DP_TRAIN_PRE_EMPHASIS_6;
2263 case DP_TRAIN_VOLTAGE_SWING_800:
2264 return DP_TRAIN_PRE_EMPHASIS_3_5;
2265 case DP_TRAIN_VOLTAGE_SWING_1200:
2266 default:
2267 return DP_TRAIN_PRE_EMPHASIS_0;
2268 }
2269 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2270 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2271 case DP_TRAIN_VOLTAGE_SWING_400:
2272 return DP_TRAIN_PRE_EMPHASIS_9_5;
2273 case DP_TRAIN_VOLTAGE_SWING_600:
2274 return DP_TRAIN_PRE_EMPHASIS_6;
2275 case DP_TRAIN_VOLTAGE_SWING_800:
2276 return DP_TRAIN_PRE_EMPHASIS_3_5;
2277 case DP_TRAIN_VOLTAGE_SWING_1200:
2278 default:
2279 return DP_TRAIN_PRE_EMPHASIS_0;
2280 }
e2fa6fba
P		 2281 } else if (IS_VALLEYVIEW(dev)) {
2282 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2283 case DP_TRAIN_VOLTAGE_SWING_400:
2284 return DP_TRAIN_PRE_EMPHASIS_9_5;
2285 case DP_TRAIN_VOLTAGE_SWING_600:
2286 return DP_TRAIN_PRE_EMPHASIS_6;
2287 case DP_TRAIN_VOLTAGE_SWING_800:
2288 return DP_TRAIN_PRE_EMPHASIS_3_5;
2289 case DP_TRAIN_VOLTAGE_SWING_1200:
2290 default:
2291 return DP_TRAIN_PRE_EMPHASIS_0;
2292 }
bc7d38a4 2293 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2294 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2295 case DP_TRAIN_VOLTAGE_SWING_400:
2296 return DP_TRAIN_PRE_EMPHASIS_6;
2297 case DP_TRAIN_VOLTAGE_SWING_600:
2298 case DP_TRAIN_VOLTAGE_SWING_800:
2299 return DP_TRAIN_PRE_EMPHASIS_3_5;
2300 default:
2301 return DP_TRAIN_PRE_EMPHASIS_0;
2302 }
2303 } else {
2304 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2305 case DP_TRAIN_VOLTAGE_SWING_400:
2306 return DP_TRAIN_PRE_EMPHASIS_6;
2307 case DP_TRAIN_VOLTAGE_SWING_600:
2308 return DP_TRAIN_PRE_EMPHASIS_6;
2309 case DP_TRAIN_VOLTAGE_SWING_800:
2310 return DP_TRAIN_PRE_EMPHASIS_3_5;
2311 case DP_TRAIN_VOLTAGE_SWING_1200:
2312 default:
2313 return DP_TRAIN_PRE_EMPHASIS_0;
2314 }
a4fc5ed6
KP		 2315 }
2316}
2317
e2fa6fba
P		 2318static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2319{
2320 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2323 struct intel_crtc *intel_crtc =
2324 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2325 unsigned long demph_reg_value, preemph_reg_value,
2326 uniqtranscale_reg_value;
2327 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2328 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2329 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2330
2331 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2332 case DP_TRAIN_PRE_EMPHASIS_0:
2333 preemph_reg_value = 0x0004000;
2334 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2335 case DP_TRAIN_VOLTAGE_SWING_400:
2336 demph_reg_value = 0x2B405555;
2337 uniqtranscale_reg_value = 0x552AB83A;
2338 break;
2339 case DP_TRAIN_VOLTAGE_SWING_600:
2340 demph_reg_value = 0x2B404040;
2341 uniqtranscale_reg_value = 0x5548B83A;
2342 break;
2343 case DP_TRAIN_VOLTAGE_SWING_800:
2344 demph_reg_value = 0x2B245555;
2345 uniqtranscale_reg_value = 0x5560B83A;
2346 break;
2347 case DP_TRAIN_VOLTAGE_SWING_1200:
2348 demph_reg_value = 0x2B405555;
2349 uniqtranscale_reg_value = 0x5598DA3A;
2350 break;
2351 default:
2352 return 0;
2353 }
2354 break;
2355 case DP_TRAIN_PRE_EMPHASIS_3_5:
2356 preemph_reg_value = 0x0002000;
2357 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2358 case DP_TRAIN_VOLTAGE_SWING_400:
2359 demph_reg_value = 0x2B404040;
2360 uniqtranscale_reg_value = 0x5552B83A;
2361 break;
2362 case DP_TRAIN_VOLTAGE_SWING_600:
2363 demph_reg_value = 0x2B404848;
2364 uniqtranscale_reg_value = 0x5580B83A;
2365 break;
2366 case DP_TRAIN_VOLTAGE_SWING_800:
2367 demph_reg_value = 0x2B404040;
2368 uniqtranscale_reg_value = 0x55ADDA3A;
2369 break;
2370 default:
2371 return 0;
2372 }
2373 break;
2374 case DP_TRAIN_PRE_EMPHASIS_6:
2375 preemph_reg_value = 0x0000000;
2376 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2377 case DP_TRAIN_VOLTAGE_SWING_400:
2378 demph_reg_value = 0x2B305555;
2379 uniqtranscale_reg_value = 0x5570B83A;
2380 break;
2381 case DP_TRAIN_VOLTAGE_SWING_600:
2382 demph_reg_value = 0x2B2B4040;
2383 uniqtranscale_reg_value = 0x55ADDA3A;
2384 break;
2385 default:
2386 return 0;
2387 }
2388 break;
2389 case DP_TRAIN_PRE_EMPHASIS_9_5:
2390 preemph_reg_value = 0x0006000;
2391 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2392 case DP_TRAIN_VOLTAGE_SWING_400:
2393 demph_reg_value = 0x1B405555;
2394 uniqtranscale_reg_value = 0x55ADDA3A;
2395 break;
2396 default:
2397 return 0;
2398 }
2399 break;
2400 default:
2401 return 0;
2402 }
2403
0980a60f 2404 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2405 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2406 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2407 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2408 uniqtranscale_reg_value);
ab3c759a
CML		 2409 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2410 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2411 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2412 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2413 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2414
2415 return 0;
2416}
2417
e4a1d846
CML		 2418static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2419{
2420 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2423 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2424 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2425 uint8_t train_set = intel_dp->train_set[0];
2426 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2427 enum pipe pipe = intel_crtc->pipe;
2428 int i;
e4a1d846
CML		 2429
2430 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2431 case DP_TRAIN_PRE_EMPHASIS_0:
2432 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2433 case DP_TRAIN_VOLTAGE_SWING_400:
2434 deemph_reg_value = 128;
2435 margin_reg_value = 52;
2436 break;
2437 case DP_TRAIN_VOLTAGE_SWING_600:
2438 deemph_reg_value = 128;
2439 margin_reg_value = 77;
2440 break;
2441 case DP_TRAIN_VOLTAGE_SWING_800:
2442 deemph_reg_value = 128;
2443 margin_reg_value = 102;
2444 break;
2445 case DP_TRAIN_VOLTAGE_SWING_1200:
2446 deemph_reg_value = 128;
2447 margin_reg_value = 154;
2448 /* FIXME extra to set for 1200 */
2449 break;
2450 default:
2451 return 0;
2452 }
2453 break;
2454 case DP_TRAIN_PRE_EMPHASIS_3_5:
2455 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2456 case DP_TRAIN_VOLTAGE_SWING_400:
2457 deemph_reg_value = 85;
2458 margin_reg_value = 78;
2459 break;
2460 case DP_TRAIN_VOLTAGE_SWING_600:
2461 deemph_reg_value = 85;
2462 margin_reg_value = 116;
2463 break;
2464 case DP_TRAIN_VOLTAGE_SWING_800:
2465 deemph_reg_value = 85;
2466 margin_reg_value = 154;
2467 break;
2468 default:
2469 return 0;
2470 }
2471 break;
2472 case DP_TRAIN_PRE_EMPHASIS_6:
2473 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2474 case DP_TRAIN_VOLTAGE_SWING_400:
2475 deemph_reg_value = 64;
2476 margin_reg_value = 104;
2477 break;
2478 case DP_TRAIN_VOLTAGE_SWING_600:
2479 deemph_reg_value = 64;
2480 margin_reg_value = 154;
2481 break;
2482 default:
2483 return 0;
2484 }
2485 break;
2486 case DP_TRAIN_PRE_EMPHASIS_9_5:
2487 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2488 case DP_TRAIN_VOLTAGE_SWING_400:
2489 deemph_reg_value = 43;
2490 margin_reg_value = 154;
2491 break;
2492 default:
2493 return 0;
2494 }
2495 break;
2496 default:
2497 return 0;
2498 }
2499
2500 mutex_lock(&dev_priv->dpio_lock);
2501
2502 /* Clear calc init */
1966e59e
VS		 2503 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2504 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2505 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2506
2507 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2508 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2509 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2510
2511 /* Program swing deemph */
f72df8db
VS		 2512 for (i = 0; i < 4; i++) {
2513 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2514 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2515 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2516 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2517 }
e4a1d846
CML		 2518
2519 /* Program swing margin */
f72df8db
VS		 2520 for (i = 0; i < 4; i++) {
2521 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2522 val &= ~DPIO_SWING_MARGIN_MASK;
2523 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2524 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2525 }
e4a1d846
CML		 2526
2527 /* Disable unique transition scale */
f72df8db
VS		 2528 for (i = 0; i < 4; i++) {
2529 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2530 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2531 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2532 }
e4a1d846
CML		 2533
2534 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2535 == DP_TRAIN_PRE_EMPHASIS_0) &&
2536 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2537 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2538
2539 /*
2540 * The document said it needs to set bit 27 for ch0 and bit 26
2541 * for ch1. Might be a typo in the doc.
2542 * For now, for this unique transition scale selection, set bit
2543 * 27 for ch0 and ch1.
2544 */
f72df8db
VS		 2545 for (i = 0; i < 4; i++) {
2546 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2547 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2548 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2549 }
e4a1d846 2550
f72df8db
VS		 2551 for (i = 0; i < 4; i++) {
2552 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2553 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2554 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2555 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2556 }
e4a1d846
CML		 2557 }
2558
2559 /* Start swing calculation */
1966e59e
VS		 2560 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2561 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2562 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2563
2564 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2565 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2566 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2567
2568 /* LRC Bypass */
2569 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2570 val |= DPIO_LRC_BYPASS;
2571 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2572
2573 mutex_unlock(&dev_priv->dpio_lock);
2574
2575 return 0;
2576}
2577
a4fc5ed6 2578static void
0301b3ac
JN		 2579intel_get_adjust_train(struct intel_dp *intel_dp,
2580 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2581{
2582 uint8_t v = 0;
2583 uint8_t p = 0;
2584 int lane;
1a2eb460
KP		 2585 uint8_t voltage_max;
2586 uint8_t preemph_max;
a4fc5ed6 2587
33a34e4e 2588 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2589 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2590 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2591
2592 if (this_v > v)
2593 v = this_v;
2594 if (this_p > p)
2595 p = this_p;
2596 }
2597
1a2eb460 2598 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2599 if (v >= voltage_max)
2600 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2601
1a2eb460
KP		 2602 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2603 if (p >= preemph_max)
2604 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2605
2606 for (lane = 0; lane < 4; lane++)
33a34e4e 2607 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2608}
2609
2610static uint32_t
f0a3424e 2611intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2612{
3cf2efb1 2613 uint32_t signal_levels = 0;
a4fc5ed6 2614
3cf2efb1 2615 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2616 case DP_TRAIN_VOLTAGE_SWING_400:
2617 default:
2618 signal_levels |= DP_VOLTAGE_0_4;
2619 break;
2620 case DP_TRAIN_VOLTAGE_SWING_600:
2621 signal_levels |= DP_VOLTAGE_0_6;
2622 break;
2623 case DP_TRAIN_VOLTAGE_SWING_800:
2624 signal_levels |= DP_VOLTAGE_0_8;
2625 break;
2626 case DP_TRAIN_VOLTAGE_SWING_1200:
2627 signal_levels |= DP_VOLTAGE_1_2;
2628 break;
2629 }
3cf2efb1 2630 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2631 case DP_TRAIN_PRE_EMPHASIS_0:
2632 default:
2633 signal_levels |= DP_PRE_EMPHASIS_0;
2634 break;
2635 case DP_TRAIN_PRE_EMPHASIS_3_5:
2636 signal_levels |= DP_PRE_EMPHASIS_3_5;
2637 break;
2638 case DP_TRAIN_PRE_EMPHASIS_6:
2639 signal_levels |= DP_PRE_EMPHASIS_6;
2640 break;
2641 case DP_TRAIN_PRE_EMPHASIS_9_5:
2642 signal_levels |= DP_PRE_EMPHASIS_9_5;
2643 break;
2644 }
2645 return signal_levels;
2646}
2647
e3421a18
ZW		 2648/* Gen6's DP voltage swing and pre-emphasis control */
2649static uint32_t
2650intel_gen6_edp_signal_levels(uint8_t train_set)
2651{
3c5a62b5
YL		 2652 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2653 DP_TRAIN_PRE_EMPHASIS_MASK);
2654 switch (signal_levels) {
e3421a18 2655 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2656 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2657 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2658 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2659 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2660 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2661 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2662 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2663 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2664 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2665 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2666 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2667 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2668 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2669 default:
3c5a62b5
YL		 2670 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2671 "0x%x\n", signal_levels);
2672 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2673 }
2674}
2675
1a2eb460
KP		 2676/* Gen7's DP voltage swing and pre-emphasis control */
2677static uint32_t
2678intel_gen7_edp_signal_levels(uint8_t train_set)
2679{
2680 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2681 DP_TRAIN_PRE_EMPHASIS_MASK);
2682 switch (signal_levels) {
2683 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2684 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2685 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2686 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2687 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2688 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2689
2690 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2691 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2692 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2693 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2694
2695 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2696 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2697 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2698 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2699
2700 default:
2701 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2702 "0x%x\n", signal_levels);
2703 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2704 }
2705}
2706
d6c0d722
PZ		 2707/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2708static uint32_t
f0a3424e 2709intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2710{
d6c0d722
PZ		 2711 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2712 DP_TRAIN_PRE_EMPHASIS_MASK);
2713 switch (signal_levels) {
2714 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2715 return DDI_BUF_EMP_400MV_0DB_HSW;
2716 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2717 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2718 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2719 return DDI_BUF_EMP_400MV_6DB_HSW;
2720 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2721 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2722
d6c0d722
PZ		 2723 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2724 return DDI_BUF_EMP_600MV_0DB_HSW;
2725 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2726 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2727 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2728 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2729
d6c0d722
PZ		 2730 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2731 return DDI_BUF_EMP_800MV_0DB_HSW;
2732 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2733 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2734 default:
2735 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2736 "0x%x\n", signal_levels);
2737 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2738 }
a4fc5ed6
KP		 2739}
2740
8f93f4f1
PZ		 2741static uint32_t
2742intel_bdw_signal_levels(uint8_t train_set)
2743{
2744 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2745 DP_TRAIN_PRE_EMPHASIS_MASK);
2746 switch (signal_levels) {
2747 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2748 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2749 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2750 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2751 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2752 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2753
2754 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2755 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2756 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2757 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2758 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2759 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2760
2761 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2762 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2763 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2764 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2765
2766 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2767 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2768
2769 default:
2770 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2771 "0x%x\n", signal_levels);
2772 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2773 }
2774}
2775
f0a3424e
PZ		 2776/* Properly updates "DP" with the correct signal levels. */
2777static void
2778intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2779{
2780 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2781 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2782 struct drm_device *dev = intel_dig_port->base.base.dev;
2783 uint32_t signal_levels, mask;
2784 uint8_t train_set = intel_dp->train_set[0];
2785
8f93f4f1
PZ		 2786 if (IS_BROADWELL(dev)) {
2787 signal_levels = intel_bdw_signal_levels(train_set);
2788 mask = DDI_BUF_EMP_MASK;
2789 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2790 signal_levels = intel_hsw_signal_levels(train_set);
2791 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2792 } else if (IS_CHERRYVIEW(dev)) {
2793 signal_levels = intel_chv_signal_levels(intel_dp);
2794 mask = 0;
e2fa6fba
P		 2795 } else if (IS_VALLEYVIEW(dev)) {
2796 signal_levels = intel_vlv_signal_levels(intel_dp);
2797 mask = 0;
bc7d38a4 2798 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2799 signal_levels = intel_gen7_edp_signal_levels(train_set);
2800 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2801 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2802 signal_levels = intel_gen6_edp_signal_levels(train_set);
2803 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2804 } else {
2805 signal_levels = intel_gen4_signal_levels(train_set);
2806 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2807 }
2808
2809 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2810
2811 *DP = (*DP & ~mask) | signal_levels;
2812}
2813
a4fc5ed6 2814static bool
ea5b213a 2815intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2816 uint32_t *DP,
58e10eb9 2817 uint8_t dp_train_pat)
a4fc5ed6 2818{
174edf1f
PZ		 2819 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2820 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2821 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2822 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2823 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2824 int ret, len;
a4fc5ed6 2825
22b8bf17 2826 if (HAS_DDI(dev)) {
3ab9c637 2827 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2828
2829 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2830 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2831 else
2832 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2833
2834 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2835 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2836 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2837 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2838
2839 break;
2840 case DP_TRAINING_PATTERN_1:
2841 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2842 break;
2843 case DP_TRAINING_PATTERN_2:
2844 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2845 break;
2846 case DP_TRAINING_PATTERN_3:
2847 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2848 break;
2849 }
174edf1f 2850 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2851
bc7d38a4 2852 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2853 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2854
2855 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2856 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2857 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2858 break;
2859 case DP_TRAINING_PATTERN_1:
70aff66c 2860 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2861 break;
2862 case DP_TRAINING_PATTERN_2:
70aff66c 2863 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2864 break;
2865 case DP_TRAINING_PATTERN_3:
2866 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2867 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2868 break;
2869 }
2870
2871 } else {
70aff66c 2872 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2873
2874 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2875 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2876 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2877 break;
2878 case DP_TRAINING_PATTERN_1:
70aff66c 2879 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2880 break;
2881 case DP_TRAINING_PATTERN_2:
70aff66c 2882 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2883 break;
2884 case DP_TRAINING_PATTERN_3:
2885 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2886 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2887 break;
2888 }
2889 }
2890
70aff66c 2891 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2892 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2893
2cdfe6c8
JN		 2894 buf[0] = dp_train_pat;
2895 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2896 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2897 /* don't write DP_TRAINING_LANEx_SET on disable */
2898 len = 1;
2899 } else {
2900 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2901 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2902 len = intel_dp->lane_count + 1;
47ea7542 2903 }
a4fc5ed6 2904
9d1a1031
JN		 2905 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2906 buf, len);
2cdfe6c8
JN		 2907
2908 return ret == len;
a4fc5ed6
KP		 2909}
2910
70aff66c
JN		 2911static bool
2912intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2913 uint8_t dp_train_pat)
2914{
953d22e8 2915 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2916 intel_dp_set_signal_levels(intel_dp, DP);
2917 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2918}
2919
2920static bool
2921intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2922 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2923{
2924 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2925 struct drm_device *dev = intel_dig_port->base.base.dev;
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927 int ret;
2928
2929 intel_get_adjust_train(intel_dp, link_status);
2930 intel_dp_set_signal_levels(intel_dp, DP);
2931
2932 I915_WRITE(intel_dp->output_reg, *DP);
2933 POSTING_READ(intel_dp->output_reg);
2934
9d1a1031
JN		 2935 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2936 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2937
2938 return ret == intel_dp->lane_count;
2939}
2940
3ab9c637
ID		 2941static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2942{
2943 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2944 struct drm_device *dev = intel_dig_port->base.base.dev;
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2946 enum port port = intel_dig_port->port;
2947 uint32_t val;
2948
2949 if (!HAS_DDI(dev))
2950 return;
2951
2952 val = I915_READ(DP_TP_CTL(port));
2953 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2954 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2955 I915_WRITE(DP_TP_CTL(port), val);
2956
2957 /*
2958 * On PORT_A we can have only eDP in SST mode. There the only reason
2959 * we need to set idle transmission mode is to work around a HW issue
2960 * where we enable the pipe while not in idle link-training mode.
2961 * In this case there is requirement to wait for a minimum number of
2962 * idle patterns to be sent.
2963 */
2964 if (port == PORT_A)
2965 return;
2966
2967 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2968 1))
2969 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2970}
2971
33a34e4e 2972/* Enable corresponding port and start training pattern 1 */
c19b0669 2973void
33a34e4e 2974intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2975{
da63a9f2 2976 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2977 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2978 int i;
2979 uint8_t voltage;
cdb0e95b 2980 int voltage_tries, loop_tries;
ea5b213a 2981 uint32_t DP = intel_dp->DP;
6aba5b6c 2982 uint8_t link_config[2];
a4fc5ed6 2983
affa9354 2984 if (HAS_DDI(dev))
c19b0669
PZ		 2985 intel_ddi_prepare_link_retrain(encoder);
2986
3cf2efb1 2987 /* Write the link configuration data */
6aba5b6c
JN		 2988 link_config[0] = intel_dp->link_bw;
2989 link_config[1] = intel_dp->lane_count;
2990 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2991 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2992 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2993
2994 link_config[0] = 0;
2995 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2996 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2997
2998 DP |= DP_PORT_EN;
1a2eb460 2999
70aff66c
JN		 3000 /* clock recovery */
3001 if (!intel_dp_reset_link_train(intel_dp, &DP,
3002 DP_TRAINING_PATTERN_1 |
3003 DP_LINK_SCRAMBLING_DISABLE)) {
3004 DRM_ERROR("failed to enable link training\n");
3005 return;
3006 }
3007
a4fc5ed6 3008 voltage = 0xff;
cdb0e95b
KP		 3009 voltage_tries = 0;
3010 loop_tries = 0;
a4fc5ed6 3011 for (;;) {
70aff66c 3012 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3013
a7c9655f 3014 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3015 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3016 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3017 break;
93f62dad 3018 }
a4fc5ed6 3019
01916270 3020 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3021 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3022 break;
3023 }
3024
3025 /* Check to see if we've tried the max voltage */
3026 for (i = 0; i < intel_dp->lane_count; i++)
3027 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3028 break;
3b4f819d 3029 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3030 ++loop_tries;
3031 if (loop_tries == 5) {
3def84b3 3032 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3033 break;
3034 }
70aff66c
JN		 3035 intel_dp_reset_link_train(intel_dp, &DP,
3036 DP_TRAINING_PATTERN_1 |
3037 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3038 voltage_tries = 0;
3039 continue;
3040 }
a4fc5ed6 3041
3cf2efb1 3042 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3043 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3044 ++voltage_tries;
b06fbda3 3045 if (voltage_tries == 5) {
3def84b3 3046 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3047 break;
3048 }
3049 } else
3050 voltage_tries = 0;
3051 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3052
70aff66c
JN		 3053 /* Update training set as requested by target */
3054 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3055 DRM_ERROR("failed to update link training\n");
3056 break;
3057 }
a4fc5ed6
KP		 3058 }
3059
33a34e4e
JB		 3060 intel_dp->DP = DP;
3061}
3062
c19b0669 3063void
33a34e4e
JB		 3064intel_dp_complete_link_train(struct intel_dp *intel_dp)
3065{
33a34e4e 3066 bool channel_eq = false;
37f80975 3067 int tries, cr_tries;
33a34e4e 3068 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3069 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3070
3071 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3072 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3073 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3074
a4fc5ed6 3075 /* channel equalization */
70aff66c 3076 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3077 training_pattern |
70aff66c
JN		 3078 DP_LINK_SCRAMBLING_DISABLE)) {
3079 DRM_ERROR("failed to start channel equalization\n");
3080 return;
3081 }
3082
a4fc5ed6 3083 tries = 0;
37f80975 3084 cr_tries = 0;
a4fc5ed6
KP		 3085 channel_eq = false;
3086 for (;;) {
70aff66c 3087 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3088
37f80975
JB		 3089 if (cr_tries > 5) {
3090 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3091 break;
3092 }
3093
a7c9655f 3094 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3095 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3096 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3097 break;
70aff66c 3098 }
a4fc5ed6 3099
37f80975 3100 /* Make sure clock is still ok */
01916270 3101 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3102 intel_dp_start_link_train(intel_dp);
70aff66c 3103 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3104 training_pattern |
70aff66c 3105 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3106 cr_tries++;
3107 continue;
3108 }
3109
1ffdff13 3110 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3111 channel_eq = true;
3112 break;
3113 }
a4fc5ed6 3114
37f80975
JB		 3115 /* Try 5 times, then try clock recovery if that fails */
3116 if (tries > 5) {
3117 intel_dp_link_down(intel_dp);
3118 intel_dp_start_link_train(intel_dp);
70aff66c 3119 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3120 training_pattern |
70aff66c 3121 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3122 tries = 0;
3123 cr_tries++;
3124 continue;
3125 }
a4fc5ed6 3126
70aff66c
JN		 3127 /* Update training set as requested by target */
3128 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3129 DRM_ERROR("failed to update link training\n");
3130 break;
3131 }
3cf2efb1 3132 ++tries;
869184a6 3133 }
3cf2efb1 3134
3ab9c637
ID		 3135 intel_dp_set_idle_link_train(intel_dp);
3136
3137 intel_dp->DP = DP;
3138
d6c0d722 3139 if (channel_eq)
07f42258 3140 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3141
3ab9c637
ID		 3142}
3143
3144void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3145{
70aff66c 3146 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3147 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3148}
3149
3150static void
ea5b213a 3151intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3152{
da63a9f2 3153 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3154 enum port port = intel_dig_port->port;
da63a9f2 3155 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3156 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3157 struct intel_crtc *intel_crtc =
3158 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3159 uint32_t DP = intel_dp->DP;
a4fc5ed6 3160
bc76e320 3161 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3162 return;
3163
0c33d8d7 3164 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3165 return;
3166
28c97730 3167 DRM_DEBUG_KMS("\n");
32f9d658 3168
bc7d38a4 3169 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3170 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3171 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3172 } else {
3173 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3174 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3175 }
fe255d00 3176 POSTING_READ(intel_dp->output_reg);
5eb08b69 3177
493a7081 3178 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3179 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3180 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3181
5bddd17f
EA		 3182 /* Hardware workaround: leaving our transcoder select
3183 * set to transcoder B while it's off will prevent the
3184 * corresponding HDMI output on transcoder A.
3185 *
3186 * Combine this with another hardware workaround:
3187 * transcoder select bit can only be cleared while the
3188 * port is enabled.
3189 */
3190 DP &= ~DP_PIPEB_SELECT;
3191 I915_WRITE(intel_dp->output_reg, DP);
3192
3193 /* Changes to enable or select take place the vblank
3194 * after being written.
3195 */
ff50afe9
DV		 3196 if (WARN_ON(crtc == NULL)) {
3197 /* We should never try to disable a port without a crtc
3198 * attached. For paranoia keep the code around for a
3199 * bit. */
31acbcc4
CW		 3200 POSTING_READ(intel_dp->output_reg);
3201 msleep(50);
3202 } else
ab527efc 3203 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3204 }
3205
832afda6 3206 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3207 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3208 POSTING_READ(intel_dp->output_reg);
f01eca2e 3209 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3210}
3211
26d61aad
KP		 3212static bool
3213intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3214{
a031d709
RV		 3215 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3216 struct drm_device *dev = dig_port->base.base.dev;
3217 struct drm_i915_private *dev_priv = dev->dev_private;
3218
577c7a50
DL		 3219 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3220
9d1a1031
JN		 3221 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3222 sizeof(intel_dp->dpcd)) < 0)
edb39244 3223 return false; /* aux transfer failed */
92fd8fd1 3224
577c7a50
DL		 3225 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3226 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3227 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3228
edb39244
AJ		 3229 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3230 return false; /* DPCD not present */
3231
2293bb5c
SK		 3232 /* Check if the panel supports PSR */
3233 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3234 if (is_edp(intel_dp)) {
9d1a1031
JN		 3235 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3236 intel_dp->psr_dpcd,
3237 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3238 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3239 dev_priv->psr.sink_support = true;
50003939 3240 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3241 }
50003939
JN		 3242 }
3243
06ea66b6
TP		 3244 /* Training Pattern 3 support */
3245 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3246 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3247 intel_dp->use_tps3 = true;
3248 DRM_DEBUG_KMS("Displayport TPS3 supported");
3249 } else
3250 intel_dp->use_tps3 = false;
3251
edb39244
AJ		 3252 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3253 DP_DWN_STRM_PORT_PRESENT))
3254 return true; /* native DP sink */
3255
3256 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3257 return true; /* no per-port downstream info */
3258
9d1a1031
JN		 3259 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3260 intel_dp->downstream_ports,
3261 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3262 return false; /* downstream port status fetch failed */
3263
3264 return true;
92fd8fd1
KP		 3265}
3266
0d198328
AJ		 3267static void
3268intel_dp_probe_oui(struct intel_dp *intel_dp)
3269{
3270 u8 buf[3];
3271
3272 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3273 return;
3274
24f3e092 3275 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3276
9d1a1031 3277 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3278 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3279 buf[0], buf[1], buf[2]);
3280
9d1a1031 3281 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3282 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3283 buf[0], buf[1], buf[2]);
351cfc34 3284
4be73780 3285 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3286}
3287
d2e216d0
RV		 3288int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3289{
3290 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3291 struct drm_device *dev = intel_dig_port->base.base.dev;
3292 struct intel_crtc *intel_crtc =
3293 to_intel_crtc(intel_dig_port->base.base.crtc);
3294 u8 buf[1];
3295
9d1a1031 3296 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3297 return -EAGAIN;
3298
3299 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3300 return -ENOTTY;
3301
9d1a1031
JN		 3302 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3303 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3304 return -EAGAIN;
3305
3306 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3307 intel_wait_for_vblank(dev, intel_crtc->pipe);
3308 intel_wait_for_vblank(dev, intel_crtc->pipe);
3309
9d1a1031 3310 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3311 return -EAGAIN;
3312
9d1a1031 3313 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3314 return 0;
3315}
3316
a60f0e38
JB		 3317static bool
3318intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3319{
9d1a1031
JN		 3320 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3321 DP_DEVICE_SERVICE_IRQ_VECTOR,
3322 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3323}
3324
3325static void
3326intel_dp_handle_test_request(struct intel_dp *intel_dp)
3327{
3328 /* NAK by default */
9d1a1031 3329 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3330}
3331
a4fc5ed6
KP		 3332/*
3333 * According to DP spec
3334 * 5.1.2:
3335 * 1. Read DPCD
3336 * 2. Configure link according to Receiver Capabilities
3337 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3338 * 4. Check link status on receipt of hot-plug interrupt
3339 */
3340
00c09d70 3341void
ea5b213a 3342intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3343{
da63a9f2 3344 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3345 u8 sink_irq_vector;
93f62dad 3346 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3347
6e9f798d 3348 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3349 if (!intel_encoder->connectors_active)
d2b996ac 3350 return;
59cd09e1 3351
da63a9f2 3352 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3353 return;
3354
92fd8fd1 3355 /* Try to read receiver status if the link appears to be up */
93f62dad 3356 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3357 return;
3358 }
3359
92fd8fd1 3360 /* Now read the DPCD to see if it's actually running */
26d61aad 3361 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3362 return;
3363 }
3364
a60f0e38
JB		 3365 /* Try to read the source of the interrupt */
3366 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3367 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3368 /* Clear interrupt source */
9d1a1031
JN		 3369 drm_dp_dpcd_writeb(&intel_dp->aux,
3370 DP_DEVICE_SERVICE_IRQ_VECTOR,
3371 sink_irq_vector);
a60f0e38
JB		 3372
3373 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3374 intel_dp_handle_test_request(intel_dp);
3375 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3376 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3377 }
3378
1ffdff13 3379 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3380 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3381 intel_encoder->base.name);
33a34e4e
JB		 3382 intel_dp_start_link_train(intel_dp);
3383 intel_dp_complete_link_train(intel_dp);
3ab9c637 3384 intel_dp_stop_link_train(intel_dp);
33a34e4e 3385 }
a4fc5ed6 3386}
a4fc5ed6 3387
caf9ab24 3388/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3389static enum drm_connector_status
26d61aad 3390intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3391{
caf9ab24 3392 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3393 uint8_t type;
3394
3395 if (!intel_dp_get_dpcd(intel_dp))
3396 return connector_status_disconnected;
3397
3398 /* if there's no downstream port, we're done */
3399 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3400 return connector_status_connected;
caf9ab24
AJ		 3401
3402 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3403 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3404 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3405 uint8_t reg;
9d1a1031
JN		 3406
3407 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3408 &reg, 1) < 0)
caf9ab24 3409 return connector_status_unknown;
9d1a1031 3410
23235177
AJ		 3411 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3412 : connector_status_disconnected;
caf9ab24
AJ		 3413 }
3414
3415 /* If no HPD, poke DDC gently */
0b99836f 3416 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3417 return connector_status_connected;
caf9ab24
AJ		 3418
3419 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3420 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3421 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3422 if (type == DP_DS_PORT_TYPE_VGA ||
3423 type == DP_DS_PORT_TYPE_NON_EDID)
3424 return connector_status_unknown;
3425 } else {
3426 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3427 DP_DWN_STRM_PORT_TYPE_MASK;
3428 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3429 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3430 return connector_status_unknown;
3431 }
caf9ab24
AJ		 3432
3433 /* Anything else is out of spec, warn and ignore */
3434 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3435 return connector_status_disconnected;
71ba9000
AJ		 3436}
3437
5eb08b69 3438static enum drm_connector_status
a9756bb5 3439ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3440{
30add22d 3441 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3442 struct drm_i915_private *dev_priv = dev->dev_private;
3443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3444 enum drm_connector_status status;
3445
fe16d949
CW		 3446 /* Can't disconnect eDP, but you can close the lid... */
3447 if (is_edp(intel_dp)) {
30add22d 3448 status = intel_panel_detect(dev);
fe16d949
CW		 3449 if (status == connector_status_unknown)
3450 status = connector_status_connected;
3451 return status;
3452 }
01cb9ea6 3453
1b469639
DL		 3454 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3455 return connector_status_disconnected;
3456
26d61aad 3457 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3458}
3459
a4fc5ed6 3460static enum drm_connector_status
a9756bb5 3461g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3462{
30add22d 3463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3464 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3466 uint32_t bit;
5eb08b69 3467
35aad75f
JB		 3468 /* Can't disconnect eDP, but you can close the lid... */
3469 if (is_edp(intel_dp)) {
3470 enum drm_connector_status status;
3471
3472 status = intel_panel_detect(dev);
3473 if (status == connector_status_unknown)
3474 status = connector_status_connected;
3475 return status;
3476 }
3477
232a6ee9
TP		 3478 if (IS_VALLEYVIEW(dev)) {
3479 switch (intel_dig_port->port) {
3480 case PORT_B:
3481 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3482 break;
3483 case PORT_C:
3484 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3485 break;
3486 case PORT_D:
3487 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3488 break;
3489 default:
3490 return connector_status_unknown;
3491 }
3492 } else {
3493 switch (intel_dig_port->port) {
3494 case PORT_B:
3495 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3496 break;
3497 case PORT_C:
3498 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3499 break;
3500 case PORT_D:
3501 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3502 break;
3503 default:
3504 return connector_status_unknown;
3505 }
a4fc5ed6
KP		 3506 }
3507
10f76a38 3508 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3509 return connector_status_disconnected;
3510
26d61aad 3511 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3512}
3513
8c241fef
KP		 3514static struct edid *
3515intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3516{
9cd300e0 3517 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3518
9cd300e0
JN		 3519 /* use cached edid if we have one */
3520 if (intel_connector->edid) {
9cd300e0
JN		 3521 /* invalid edid */
3522 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3523 return NULL;
3524
55e9edeb 3525 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3526 }
8c241fef 3527
9cd300e0 3528 return drm_get_edid(connector, adapter);
8c241fef
KP		 3529}
3530
3531static int
3532intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3533{
9cd300e0 3534 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3535
9cd300e0
JN		 3536 /* use cached edid if we have one */
3537 if (intel_connector->edid) {
3538 /* invalid edid */
3539 if (IS_ERR(intel_connector->edid))
3540 return 0;
3541
3542 return intel_connector_update_modes(connector,
3543 intel_connector->edid);
d6f24d0f
JB		 3544 }
3545
9cd300e0 3546 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3547}
3548
a9756bb5
ZW		 3549static enum drm_connector_status
3550intel_dp_detect(struct drm_connector *connector, bool force)
3551{
3552 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3553 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3555 struct drm_device *dev = connector->dev;
c8c8fb33 3556 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3557 enum drm_connector_status status;
671dedd2 3558 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3559 struct edid *edid = NULL;
3560
c8c8fb33
PZ		 3561 intel_runtime_pm_get(dev_priv);
3562
671dedd2
ID		 3563 power_domain = intel_display_port_power_domain(intel_encoder);
3564 intel_display_power_get(dev_priv, power_domain);
3565
164c8598 3566 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3567 connector->base.id, connector->name);
164c8598 3568
a9756bb5
ZW		 3569 intel_dp->has_audio = false;
3570
3571 if (HAS_PCH_SPLIT(dev))
3572 status = ironlake_dp_detect(intel_dp);
3573 else
3574 status = g4x_dp_detect(intel_dp);
1b9be9d0 3575
a9756bb5 3576 if (status != connector_status_connected)
c8c8fb33 3577 goto out;
a9756bb5 3578
0d198328
AJ		 3579 intel_dp_probe_oui(intel_dp);
3580
c3e5f67b
DV		 3581 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3582 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3583 } else {
0b99836f 3584 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3585 if (edid) {
3586 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3587 kfree(edid);
3588 }
a9756bb5
ZW		 3589 }
3590
d63885da
PZ		 3591 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3592 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3593 status = connector_status_connected;
3594
3595out:
671dedd2
ID		 3596 intel_display_power_put(dev_priv, power_domain);
3597
c8c8fb33 3598 intel_runtime_pm_put(dev_priv);
671dedd2 3599
c8c8fb33 3600 return status;
a4fc5ed6
KP		 3601}
3602
3603static int intel_dp_get_modes(struct drm_connector *connector)
3604{
df0e9248 3605 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3606 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3607 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3608 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3609 struct drm_device *dev = connector->dev;
671dedd2
ID		 3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 enum intel_display_power_domain power_domain;
32f9d658 3612 int ret;
a4fc5ed6
KP		 3613
3614 /* We should parse the EDID data and find out if it has an audio sink
3615 */
3616
671dedd2
ID		 3617 power_domain = intel_display_port_power_domain(intel_encoder);
3618 intel_display_power_get(dev_priv, power_domain);
3619
0b99836f 3620 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3621 intel_display_power_put(dev_priv, power_domain);
f8779fda 3622 if (ret)
32f9d658
ZW		 3623 return ret;
3624
f8779fda 3625 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3626 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3627 struct drm_display_mode *mode;
dd06f90e
JN		 3628 mode = drm_mode_duplicate(dev,
3629 intel_connector->panel.fixed_mode);
f8779fda 3630 if (mode) {
32f9d658
ZW		 3631 drm_mode_probed_add(connector, mode);
3632 return 1;
3633 }
3634 }
3635 return 0;
a4fc5ed6
KP		 3636}
3637
1aad7ac0
CW		 3638static bool
3639intel_dp_detect_audio(struct drm_connector *connector)
3640{
3641 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3642 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3643 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3644 struct drm_device *dev = connector->dev;
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3647 struct edid *edid;
3648 bool has_audio = false;
3649
671dedd2
ID		 3650 power_domain = intel_display_port_power_domain(intel_encoder);
3651 intel_display_power_get(dev_priv, power_domain);
3652
0b99836f 3653 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3654 if (edid) {
3655 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3656 kfree(edid);
3657 }
3658
671dedd2
ID		 3659 intel_display_power_put(dev_priv, power_domain);
3660
1aad7ac0
CW		 3661 return has_audio;
3662}
3663
f684960e
CW		 3664static int
3665intel_dp_set_property(struct drm_connector *connector,
3666 struct drm_property *property,
3667 uint64_t val)
3668{
e953fd7b 3669 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3670 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3671 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3672 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3673 int ret;
3674
662595df 3675 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3676 if (ret)
3677 return ret;
3678
3f43c48d 3679 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3680 int i = val;
3681 bool has_audio;
3682
3683 if (i == intel_dp->force_audio)
f684960e
CW		 3684 return 0;
3685
1aad7ac0 3686 intel_dp->force_audio = i;
f684960e 3687
c3e5f67b 3688 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3689 has_audio = intel_dp_detect_audio(connector);
3690 else
c3e5f67b 3691 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3692
3693 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3694 return 0;
3695
1aad7ac0 3696 intel_dp->has_audio = has_audio;
f684960e
CW		 3697 goto done;
3698 }
3699
e953fd7b 3700 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3701 bool old_auto = intel_dp->color_range_auto;
3702 uint32_t old_range = intel_dp->color_range;
3703
55bc60db
VS		 3704 switch (val) {
3705 case INTEL_BROADCAST_RGB_AUTO:
3706 intel_dp->color_range_auto = true;
3707 break;
3708 case INTEL_BROADCAST_RGB_FULL:
3709 intel_dp->color_range_auto = false;
3710 intel_dp->color_range = 0;
3711 break;
3712 case INTEL_BROADCAST_RGB_LIMITED:
3713 intel_dp->color_range_auto = false;
3714 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3715 break;
3716 default:
3717 return -EINVAL;
3718 }
ae4edb80
DV		 3719
3720 if (old_auto == intel_dp->color_range_auto &&
3721 old_range == intel_dp->color_range)
3722 return 0;
3723
e953fd7b
CW		 3724 goto done;
3725 }
3726
53b41837
YN		 3727 if (is_edp(intel_dp) &&
3728 property == connector->dev->mode_config.scaling_mode_property) {
3729 if (val == DRM_MODE_SCALE_NONE) {
3730 DRM_DEBUG_KMS("no scaling not supported\n");
3731 return -EINVAL;
3732 }
3733
3734 if (intel_connector->panel.fitting_mode == val) {
3735 /* the eDP scaling property is not changed */
3736 return 0;
3737 }
3738 intel_connector->panel.fitting_mode = val;
3739
3740 goto done;
3741 }
3742
f684960e
CW		 3743 return -EINVAL;
3744
3745done:
c0c36b94
CW		 3746 if (intel_encoder->base.crtc)
3747 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3748
3749 return 0;
3750}
3751
a4fc5ed6 3752static void
73845adf 3753intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3754{
1d508706 3755 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3756
9cd300e0
JN		 3757 if (!IS_ERR_OR_NULL(intel_connector->edid))
3758 kfree(intel_connector->edid);
3759
acd8db10
PZ		 3760 /* Can't call is_edp() since the encoder may have been destroyed
3761 * already. */
3762 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3763 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3764
a4fc5ed6 3765 drm_connector_cleanup(connector);
55f78c43 3766 kfree(connector);
a4fc5ed6
KP		 3767}
3768
00c09d70 3769void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3770{
da63a9f2
PZ		 3771 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3772 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3773 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3774
4f71d0cb 3775 drm_dp_aux_unregister(&intel_dp->aux);
24d05927 3776 drm_encoder_cleanup(encoder);
bd943159
KP		 3777 if (is_edp(intel_dp)) {
3778 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3779 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3780 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3781 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159 3782 }
da63a9f2 3783 kfree(intel_dig_port);
24d05927
DV		 3784}
3785
a4fc5ed6 3786static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3787 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3788 .detect = intel_dp_detect,
3789 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3790 .set_property = intel_dp_set_property,
73845adf 3791 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3792};
3793
3794static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3795 .get_modes = intel_dp_get_modes,
3796 .mode_valid = intel_dp_mode_valid,
df0e9248 3797 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3798};
3799
a4fc5ed6 3800static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3801 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3802};
3803
995b6762 3804static void
21d40d37 3805intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3806{
fa90ecef 3807 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3808
885a5014 3809 intel_dp_check_link_status(intel_dp);
c8110e52 3810}
6207937d 3811
e3421a18
ZW		 3812/* Return which DP Port should be selected for Transcoder DP control */
3813int
0206e353 3814intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3815{
3816 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3817 struct intel_encoder *intel_encoder;
3818 struct intel_dp *intel_dp;
e3421a18 3819
fa90ecef
PZ		 3820 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3821 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3822
fa90ecef
PZ		 3823 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3824 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3825 return intel_dp->output_reg;
e3421a18 3826 }
ea5b213a 3827
e3421a18
ZW		 3828 return -1;
3829}
3830
36e83a18 3831/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3832bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3833{
3834 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3835 union child_device_config *p_child;
36e83a18 3836 int i;
5d8a7752
VS		 3837 static const short port_mapping[] = {
3838 [PORT_B] = PORT_IDPB,
3839 [PORT_C] = PORT_IDPC,
3840 [PORT_D] = PORT_IDPD,
3841 };
36e83a18 3842
3b32a35b
VS		 3843 if (port == PORT_A)
3844 return true;
3845
41aa3448 3846 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3847 return false;
3848
41aa3448
RV		 3849 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3850 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3851
5d8a7752 3852 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3853 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3854 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3855 return true;
3856 }
3857 return false;
3858}
3859
f684960e
CW		 3860static void
3861intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3862{
53b41837
YN		 3863 struct intel_connector *intel_connector = to_intel_connector(connector);
3864
3f43c48d 3865 intel_attach_force_audio_property(connector);
e953fd7b 3866 intel_attach_broadcast_rgb_property(connector);
55bc60db 3867 intel_dp->color_range_auto = true;
53b41837
YN		 3868
3869 if (is_edp(intel_dp)) {
3870 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3871 drm_object_attach_property(
3872 &connector->base,
53b41837 3873 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3874 DRM_MODE_SCALE_ASPECT);
3875 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3876 }
f684960e
CW		 3877}
3878
dada1a9f
ID		 3879static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3880{
3881 intel_dp->last_power_cycle = jiffies;
3882 intel_dp->last_power_on = jiffies;
3883 intel_dp->last_backlight_off = jiffies;
3884}
3885
67a54566
DV		 3886static void
3887intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3888 struct intel_dp *intel_dp,
3889 struct edp_power_seq *out)
67a54566
DV		 3890{
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct edp_power_seq cur, vbt, spec, final;
3893 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3894 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3895
3896 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3897 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3898 pp_on_reg = PCH_PP_ON_DELAYS;
3899 pp_off_reg = PCH_PP_OFF_DELAYS;
3900 pp_div_reg = PCH_PP_DIVISOR;
3901 } else {
bf13e81b
JN		 3902 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3903
3904 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3905 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3906 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3907 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3908 }
67a54566
DV		 3909
3910 /* Workaround: Need to write PP_CONTROL with the unlock key as
3911 * the very first thing. */
453c5420 3912 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3913 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3914
453c5420
JB		 3915 pp_on = I915_READ(pp_on_reg);
3916 pp_off = I915_READ(pp_off_reg);
3917 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3918
3919 /* Pull timing values out of registers */
3920 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3921 PANEL_POWER_UP_DELAY_SHIFT;
3922
3923 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3924 PANEL_LIGHT_ON_DELAY_SHIFT;
3925
3926 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3927 PANEL_LIGHT_OFF_DELAY_SHIFT;
3928
3929 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3930 PANEL_POWER_DOWN_DELAY_SHIFT;
3931
3932 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3933 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3934
3935 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3936 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3937
41aa3448 3938 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3939
3940 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3941 * our hw here, which are all in 100usec. */
3942 spec.t1_t3 = 210 * 10;
3943 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3944 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3945 spec.t10 = 500 * 10;
3946 /* This one is special and actually in units of 100ms, but zero
3947 * based in the hw (so we need to add 100 ms). But the sw vbt
3948 * table multiplies it with 1000 to make it in units of 100usec,
3949 * too. */
3950 spec.t11_t12 = (510 + 100) * 10;
3951
3952 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3953 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3954
3955 /* Use the max of the register settings and vbt. If both are
3956 * unset, fall back to the spec limits. */
3957#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3958 spec.field : \
3959 max(cur.field, vbt.field))
3960 assign_final(t1_t3);
3961 assign_final(t8);
3962 assign_final(t9);
3963 assign_final(t10);
3964 assign_final(t11_t12);
3965#undef assign_final
3966
3967#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3968 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3969 intel_dp->backlight_on_delay = get_delay(t8);
3970 intel_dp->backlight_off_delay = get_delay(t9);
3971 intel_dp->panel_power_down_delay = get_delay(t10);
3972 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3973#undef get_delay
3974
f30d26e4
JN		 3975 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3976 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3977 intel_dp->panel_power_cycle_delay);
3978
3979 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3980 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3981
3982 if (out)
3983 *out = final;
3984}
3985
3986static void
3987intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3988 struct intel_dp *intel_dp,
3989 struct edp_power_seq *seq)
3990{
3991 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3992 u32 pp_on, pp_off, pp_div, port_sel = 0;
3993 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3994 int pp_on_reg, pp_off_reg, pp_div_reg;
3995
3996 if (HAS_PCH_SPLIT(dev)) {
3997 pp_on_reg = PCH_PP_ON_DELAYS;
3998 pp_off_reg = PCH_PP_OFF_DELAYS;
3999 pp_div_reg = PCH_PP_DIVISOR;
4000 } else {
bf13e81b
JN		 4001 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4002
4003 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4004 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4005 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4006 }
4007
b2f19d1a
PZ		 4008 /*
4009 * And finally store the new values in the power sequencer. The
4010 * backlight delays are set to 1 because we do manual waits on them. For
4011 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4012 * we'll end up waiting for the backlight off delay twice: once when we
4013 * do the manual sleep, and once when we disable the panel and wait for
4014 * the PP_STATUS bit to become zero.
4015 */
f30d26e4 4016 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4017 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4018 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4019 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4020 /* Compute the divisor for the pp clock, simply match the Bspec
4021 * formula. */
453c5420 4022 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4023 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4024 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4025
4026 /* Haswell doesn't have any port selection bits for the panel
4027 * power sequencer any more. */
bc7d38a4 4028 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4029 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4030 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4031 else
4032 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4033 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4034 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4035 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4036 else
a24c144c 4037 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4038 }
4039
453c5420
JB		 4040 pp_on |= port_sel;
4041
4042 I915_WRITE(pp_on_reg, pp_on);
4043 I915_WRITE(pp_off_reg, pp_off);
4044 I915_WRITE(pp_div_reg, pp_div);
67a54566 4045
67a54566 4046 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4047 I915_READ(pp_on_reg),
4048 I915_READ(pp_off_reg),
4049 I915_READ(pp_div_reg));
f684960e
CW		 4050}
4051
439d7ac0
PB		 4052void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4053{
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 struct intel_encoder *encoder;
4056 struct intel_dp *intel_dp = NULL;
4057 struct intel_crtc_config *config = NULL;
4058 struct intel_crtc *intel_crtc = NULL;
4059 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4060 u32 reg, val;
4061 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4062
4063 if (refresh_rate <= 0) {
4064 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4065 return;
4066 }
4067
4068 if (intel_connector == NULL) {
4069 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4070 return;
4071 }
4072
4073 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4074 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4075 return;
4076 }
4077
4078 encoder = intel_attached_encoder(&intel_connector->base);
4079 intel_dp = enc_to_intel_dp(&encoder->base);
4080 intel_crtc = encoder->new_crtc;
4081
4082 if (!intel_crtc) {
4083 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4084 return;
4085 }
4086
4087 config = &intel_crtc->config;
4088
4089 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4090 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4091 return;
4092 }
4093
4094 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4095 index = DRRS_LOW_RR;
4096
4097 if (index == intel_dp->drrs_state.refresh_rate_type) {
4098 DRM_DEBUG_KMS(
4099 "DRRS requested for previously set RR...ignoring\n");
4100 return;
4101 }
4102
4103 if (!intel_crtc->active) {
4104 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4105 return;
4106 }
4107
4108 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4109 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4110 val = I915_READ(reg);
4111 if (index > DRRS_HIGH_RR) {
4112 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4113 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4114 } else {
4115 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4116 }
4117 I915_WRITE(reg, val);
4118 }
4119
4120 /*
4121 * mutex taken to ensure that there is no race between differnt
4122 * drrs calls trying to update refresh rate. This scenario may occur
4123 * in future when idleness detection based DRRS in kernel and
4124 * possible calls from user space to set differnt RR are made.
4125 */
4126
4127 mutex_lock(&intel_dp->drrs_state.mutex);
4128
4129 intel_dp->drrs_state.refresh_rate_type = index;
4130
4131 mutex_unlock(&intel_dp->drrs_state.mutex);
4132
4133 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4134}
4135
4f9db5b5
PB		 4136static struct drm_display_mode *
4137intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4138 struct intel_connector *intel_connector,
4139 struct drm_display_mode *fixed_mode)
4140{
4141 struct drm_connector *connector = &intel_connector->base;
4142 struct intel_dp *intel_dp = &intel_dig_port->dp;
4143 struct drm_device *dev = intel_dig_port->base.base.dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct drm_display_mode *downclock_mode = NULL;
4146
4147 if (INTEL_INFO(dev)->gen <= 6) {
4148 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4149 return NULL;
4150 }
4151
4152 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4153 DRM_INFO("VBT doesn't support DRRS\n");
4154 return NULL;
4155 }
4156
4157 downclock_mode = intel_find_panel_downclock
4158 (dev, fixed_mode, connector);
4159
4160 if (!downclock_mode) {
4161 DRM_INFO("DRRS not supported\n");
4162 return NULL;
4163 }
4164
439d7ac0
PB		 4165 dev_priv->drrs.connector = intel_connector;
4166
4167 mutex_init(&intel_dp->drrs_state.mutex);
4168
4f9db5b5
PB		 4169 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4170
4171 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4172 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4173 return downclock_mode;
4174}
4175
ed92f0b2 4176static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4177 struct intel_connector *intel_connector,
4178 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4179{
4180 struct drm_connector *connector = &intel_connector->base;
4181 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4182 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4183 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4186 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4187 bool has_dpcd;
4188 struct drm_display_mode *scan;
4189 struct edid *edid;
4190
4f9db5b5
PB		 4191 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4192
ed92f0b2
PZ		 4193 if (!is_edp(intel_dp))
4194 return true;
4195
63635217
PZ		 4196 /* The VDD bit needs a power domain reference, so if the bit is already
4197 * enabled when we boot, grab this reference. */
4198 if (edp_have_panel_vdd(intel_dp)) {
4199 enum intel_display_power_domain power_domain;
4200 power_domain = intel_display_port_power_domain(intel_encoder);
4201 intel_display_power_get(dev_priv, power_domain);
4202 }
4203
ed92f0b2 4204 /* Cache DPCD and EDID for edp. */
24f3e092 4205 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4206 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4207 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4208
4209 if (has_dpcd) {
4210 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4211 dev_priv->no_aux_handshake =
4212 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4213 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4214 } else {
4215 /* if this fails, presume the device is a ghost */
4216 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4217 return false;
4218 }
4219
4220 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4221 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4222
060c8778 4223 mutex_lock(&dev->mode_config.mutex);
0b99836f 4224 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4225 if (edid) {
4226 if (drm_add_edid_modes(connector, edid)) {
4227 drm_mode_connector_update_edid_property(connector,
4228 edid);
4229 drm_edid_to_eld(connector, edid);
4230 } else {
4231 kfree(edid);
4232 edid = ERR_PTR(-EINVAL);
4233 }
4234 } else {
4235 edid = ERR_PTR(-ENOENT);
4236 }
4237 intel_connector->edid = edid;
4238
4239 /* prefer fixed mode from EDID if available */
4240 list_for_each_entry(scan, &connector->probed_modes, head) {
4241 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4242 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4243 downclock_mode = intel_dp_drrs_init(
4244 intel_dig_port,
4245 intel_connector, fixed_mode);
ed92f0b2
PZ		 4246 break;
4247 }
4248 }
4249
4250 /* fallback to VBT if available for eDP */
4251 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4252 fixed_mode = drm_mode_duplicate(dev,
4253 dev_priv->vbt.lfp_lvds_vbt_mode);
4254 if (fixed_mode)
4255 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4256 }
060c8778 4257 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4258
4f9db5b5 4259 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4260 intel_panel_setup_backlight(connector);
4261
4262 return true;
4263}
4264
16c25533 4265bool
f0fec3f2
PZ		 4266intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4267 struct intel_connector *intel_connector)
a4fc5ed6 4268{
f0fec3f2
PZ		 4269 struct drm_connector *connector = &intel_connector->base;
4270 struct intel_dp *intel_dp = &intel_dig_port->dp;
4271 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4272 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4273 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4274 enum port port = intel_dig_port->port;
0095e6dc 4275 struct edp_power_seq power_seq = { 0 };
0b99836f 4276 int type;
a4fc5ed6 4277
ec5b01dd
DL		 4278 /* intel_dp vfuncs */
4279 if (IS_VALLEYVIEW(dev))
4280 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4281 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4282 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4283 else if (HAS_PCH_SPLIT(dev))
4284 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4285 else
4286 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4287
153b1100
DL		 4288 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4289
0767935e
DV		 4290 /* Preserve the current hw state. */
4291 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4292 intel_dp->attached_connector = intel_connector;
3d3dc149 4293
3b32a35b 4294 if (intel_dp_is_edp(dev, port))
b329530c 4295 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4296 else
4297 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4298
f7d24902
ID		 4299 /*
4300 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4301 * for DP the encoder type can be set by the caller to
4302 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4303 */
4304 if (type == DRM_MODE_CONNECTOR_eDP)
4305 intel_encoder->type = INTEL_OUTPUT_EDP;
4306
e7281eab
ID		 4307 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4308 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4309 port_name(port));
4310
b329530c 4311 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4312 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4313
a4fc5ed6
KP		 4314 connector->interlace_allowed = true;
4315 connector->doublescan_allowed = 0;
4316
f0fec3f2 4317 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4318 edp_panel_vdd_work);
a4fc5ed6 4319
df0e9248 4320 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4321 drm_sysfs_connector_add(connector);
4322
affa9354 4323 if (HAS_DDI(dev))
bcbc889b
PZ		 4324 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4325 else
4326 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4327 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4328
0b99836f 4329 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4330 switch (port) {
4331 case PORT_A:
1d843f9d 4332 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4333 break;
4334 case PORT_B:
1d843f9d 4335 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4336 break;
4337 case PORT_C:
1d843f9d 4338 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4339 break;
4340 case PORT_D:
1d843f9d 4341 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4342 break;
4343 default:
ad1c0b19 4344 BUG();
5eb08b69
ZW		 4345 }
4346
dada1a9f
ID		 4347 if (is_edp(intel_dp)) {
4348 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4349 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4350 }
0095e6dc 4351
9d1a1031 4352 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4353
0095e6dc 4354 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4355 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4356 if (is_edp(intel_dp)) {
4357 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4358 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4359 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4360 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4361 }
b2f246a8
PZ		 4362 drm_sysfs_connector_remove(connector);
4363 drm_connector_cleanup(connector);
16c25533 4364 return false;
b2f246a8 4365 }
32f9d658 4366
f684960e
CW		 4367 intel_dp_add_properties(intel_dp, connector);
4368
a4fc5ed6
KP		 4369 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4370 * 0xd. Failure to do so will result in spurious interrupts being
4371 * generated on the port when a cable is not attached.
4372 */
4373 if (IS_G4X(dev) && !IS_GM45(dev)) {
4374 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4375 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4376 }
16c25533
PZ		 4377
4378 return true;
a4fc5ed6 4379}
f0fec3f2
PZ		 4380
4381void
4382intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4383{
4384 struct intel_digital_port *intel_dig_port;
4385 struct intel_encoder *intel_encoder;
4386 struct drm_encoder *encoder;
4387 struct intel_connector *intel_connector;
4388
b14c5679 4389 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4390 if (!intel_dig_port)
4391 return;
4392
b14c5679 4393 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4394 if (!intel_connector) {
4395 kfree(intel_dig_port);
4396 return;
4397 }
4398
4399 intel_encoder = &intel_dig_port->base;
4400 encoder = &intel_encoder->base;
4401
4402 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4403 DRM_MODE_ENCODER_TMDS);
4404
5bfe2ac0 4405 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4406 intel_encoder->disable = intel_disable_dp;
00c09d70 4407 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4408 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4409 if (IS_CHERRYVIEW(dev)) {
9197c88b 4410 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4411 intel_encoder->pre_enable = chv_pre_enable_dp;
4412 intel_encoder->enable = vlv_enable_dp;
580d3811 4413 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4414 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4415 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4416 intel_encoder->pre_enable = vlv_pre_enable_dp;
4417 intel_encoder->enable = vlv_enable_dp;
49277c31 4418 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4419 } else {
ecff4f3b
JN		 4420 intel_encoder->pre_enable = g4x_pre_enable_dp;
4421 intel_encoder->enable = g4x_enable_dp;
49277c31 4422 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4423 }
f0fec3f2 4424
174edf1f 4425 intel_dig_port->port = port;
f0fec3f2
PZ		 4426 intel_dig_port->dp.output_reg = output_reg;
4427
00c09d70 4428 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4429 if (IS_CHERRYVIEW(dev)) {
4430 if (port == PORT_D)
4431 intel_encoder->crtc_mask = 1 << 2;
4432 else
4433 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4434 } else {
4435 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4436 }
bc079e8b 4437 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4438 intel_encoder->hot_plug = intel_dp_hot_plug;
4439
15b1d171
PZ		 4440 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4441 drm_encoder_cleanup(encoder);
4442 kfree(intel_dig_port);
b2f246a8 4443 kfree(intel_connector);
15b1d171 4444 }
f0fec3f2 4445}
Linux kernel - Deliverables
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