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drm/i915: Clear PPS port select when giving up the power sequencer
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a4fc5ed6 117
0e32b39c 118int
ea5b213a 119intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 120{
7183dc29 121 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 122 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 123
124 switch (max_link_bw) {
125 case DP_LINK_BW_1_62:
126 case DP_LINK_BW_2_7:
127 break;
d4eead50 128 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 129 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
130 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 131 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
132 max_link_bw = DP_LINK_BW_5_4;
133 else
134 max_link_bw = DP_LINK_BW_2_7;
d4eead50 135 break;
a4fc5ed6 136 default:
d4eead50
ID		 137 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw);
a4fc5ed6
KP		 139 max_link_bw = DP_LINK_BW_1_62;
140 break;
141 }
142 return max_link_bw;
143}
144
eeb6324d
PZ		 145static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
146{
147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
148 struct drm_device *dev = intel_dig_port->base.base.dev;
149 u8 source_max, sink_max;
150
151 source_max = 4;
152 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
153 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
154 source_max = 2;
155
156 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
157
158 return min(source_max, sink_max);
159}
160
cd9dde44
AJ		 161/*
162 * The units on the numbers in the next two are... bizarre. Examples will
163 * make it clearer; this one parallels an example in the eDP spec.
164 *
165 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 *
167 * 270000 * 1 * 8 / 10 == 216000
168 *
169 * The actual data capacity of that configuration is 2.16Gbit/s, so the
170 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
171 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
172 * 119000. At 18bpp that's 2142000 kilobits per second.
173 *
174 * Thus the strange-looking division by 10 in intel_dp_link_required, to
175 * get the result in decakilobits instead of kilobits.
176 */
177
a4fc5ed6 178static int
c898261c 179intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 180{
cd9dde44 181 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 182}
183
fe27d53e
DA		 184static int
185intel_dp_max_data_rate(int max_link_clock, int max_lanes)
186{
187 return (max_link_clock * max_lanes * 8) / 10;
188}
189
c19de8eb 190static enum drm_mode_status
a4fc5ed6
KP		 191intel_dp_mode_valid(struct drm_connector *connector,
192 struct drm_display_mode *mode)
193{
df0e9248 194 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 195 struct intel_connector *intel_connector = to_intel_connector(connector);
196 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 197 int target_clock = mode->clock;
198 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 199
dd06f90e
JN		 200 if (is_edp(intel_dp) && fixed_mode) {
201 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 202 return MODE_PANEL;
203
dd06f90e 204 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 205 return MODE_PANEL;
03afc4a2
DV		 206
207 target_clock = fixed_mode->clock;
7de56f43
ZY		 208 }
209
36008365 210 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 211 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 212
213 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
214 mode_rate = intel_dp_link_required(target_clock, 18);
215
216 if (mode_rate > max_rate)
c4867936 217 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 218
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
221
0af78a2b
DV		 222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 return MODE_H_ILLEGAL;
224
a4fc5ed6
KP		 225 return MODE_OK;
226}
227
228static uint32_t
5ca476f8 229pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 230{
231 int i;
232 uint32_t v = 0;
233
234 if (src_bytes > 4)
235 src_bytes = 4;
236 for (i = 0; i < src_bytes; i++)
237 v |= ((uint32_t) src[i]) << ((3-i) * 8);
238 return v;
239}
240
241static void
242unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
331 uint32_t DP;
332
333 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
334 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
335 pipe_name(pipe), port_name(intel_dig_port->port)))
336 return;
337
338 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
339 pipe_name(pipe), port_name(intel_dig_port->port));
340
341 /* Preserve the BIOS-computed detected bit. This is
342 * supposed to be read-only.
343 */
344 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
345 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
346 DP |= DP_PORT_WIDTH(1);
347 DP |= DP_LINK_TRAIN_PAT_1;
348
349 if (IS_CHERRYVIEW(dev))
350 DP |= DP_PIPE_SELECT_CHV(pipe);
351 else if (pipe == PIPE_B)
352 DP |= DP_PIPEB_SELECT;
353
354 /*
355 * Similar magic as in intel_dp_enable_port().
356 * We _must_ do this port enable + disable trick
357 * to make this power seqeuencer lock onto the port.
358 * Otherwise even VDD force bit won't work.
359 */
360 I915_WRITE(intel_dp->output_reg, DP);
361 POSTING_READ(intel_dp->output_reg);
362
363 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
364 POSTING_READ(intel_dp->output_reg);
365
366 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
367 POSTING_READ(intel_dp->output_reg);
368}
369
bf13e81b
JN		 370static enum pipe
371vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
372{
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 376 struct intel_encoder *encoder;
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
bf13e81b 378
e39b999a 379 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
388 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
389 base.head) {
390 struct intel_dp *tmp;
391
392 if (encoder->type != INTEL_OUTPUT_EDP)
393 continue;
394
395 tmp = enc_to_intel_dp(&encoder->base);
396
397 if (tmp->pps_pipe != INVALID_PIPE)
398 pipes &= ~(1 << tmp->pps_pipe);
399 }
400
401 /*
402 * Didn't find one. This should not happen since there
403 * are two power sequencers and up to two eDP ports.
404 */
405 if (WARN_ON(pipes == 0))
406 return PIPE_A;
407
408 intel_dp->pps_pipe = ffs(pipes) - 1;
409
410 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
411 pipe_name(intel_dp->pps_pipe),
412 port_name(intel_dig_port->port));
413
414 /* init power sequencer on this pipe and port */
36b5f425
VS		 415 intel_dp_init_panel_power_sequencer(dev, intel_dp);
416 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 417
961a0db0
VS		 418 /*
419 * Even vdd force doesn't work until we've made
420 * the power sequencer lock in on the port.
421 */
422 vlv_power_sequencer_kick(intel_dp);
423
a4a5d2f8
VS		 424 return intel_dp->pps_pipe;
425}
426
6491ab27
VS		 427typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
428 enum pipe pipe);
429
430static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
431 enum pipe pipe)
432{
433 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
434}
435
436static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
437 enum pipe pipe)
438{
439 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
440}
441
442static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
443 enum pipe pipe)
444{
445 return true;
446}
bf13e81b 447
a4a5d2f8 448static enum pipe
6491ab27
VS		 449vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
450 enum port port,
451 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 452{
453 enum pipe pipe;
bf13e81b 454
bf13e81b
JN		 455 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
456 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
457 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 458
459 if (port_sel != PANEL_PORT_SELECT_VLV(port))
460 continue;
461
6491ab27
VS		 462 if (!pipe_check(dev_priv, pipe))
463 continue;
464
a4a5d2f8 465 return pipe;
bf13e81b
JN		 466 }
467
a4a5d2f8
VS		 468 return INVALID_PIPE;
469}
470
471static void
472vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
473{
474 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
475 struct drm_device *dev = intel_dig_port->base.base.dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 477 enum port port = intel_dig_port->port;
478
479 lockdep_assert_held(&dev_priv->pps_mutex);
480
481 /* try to find a pipe with this port selected */
6491ab27
VS		 482 /* first pick one where the panel is on */
483 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
484 vlv_pipe_has_pp_on);
485 /* didn't find one? pick one where vdd is on */
486 if (intel_dp->pps_pipe == INVALID_PIPE)
487 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
488 vlv_pipe_has_vdd_on);
489 /* didn't find one? pick one with just the correct port */
490 if (intel_dp->pps_pipe == INVALID_PIPE)
491 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
492 vlv_pipe_any);
a4a5d2f8
VS		 493
494 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
495 if (intel_dp->pps_pipe == INVALID_PIPE) {
496 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
497 port_name(port));
498 return;
bf13e81b
JN		 499 }
500
a4a5d2f8
VS		 501 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
502 port_name(port), pipe_name(intel_dp->pps_pipe));
503
36b5f425
VS		 504 intel_dp_init_panel_power_sequencer(dev, intel_dp);
505 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 506}
507
773538e8
VS		 508void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
509{
510 struct drm_device *dev = dev_priv->dev;
511 struct intel_encoder *encoder;
512
513 if (WARN_ON(!IS_VALLEYVIEW(dev)))
514 return;
515
516 /*
517 * We can't grab pps_mutex here due to deadlock with power_domain
518 * mutex when power_domain functions are called while holding pps_mutex.
519 * That also means that in order to use pps_pipe the code needs to
520 * hold both a power domain reference and pps_mutex, and the power domain
521 * reference get/put must be done while _not_ holding pps_mutex.
522 * pps_{lock,unlock}() do these steps in the correct order, so one
523 * should use them always.
524 */
525
526 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
527 struct intel_dp *intel_dp;
528
529 if (encoder->type != INTEL_OUTPUT_EDP)
530 continue;
531
532 intel_dp = enc_to_intel_dp(&encoder->base);
533 intel_dp->pps_pipe = INVALID_PIPE;
534 }
bf13e81b
JN		 535}
536
537static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
538{
539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
540
541 if (HAS_PCH_SPLIT(dev))
542 return PCH_PP_CONTROL;
543 else
544 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
545}
546
547static u32 _pp_stat_reg(struct intel_dp *intel_dp)
548{
549 struct drm_device *dev = intel_dp_to_dev(intel_dp);
550
551 if (HAS_PCH_SPLIT(dev))
552 return PCH_PP_STATUS;
553 else
554 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
555}
556
01527b31
CT		 557/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
558 This function only applicable when panel PM state is not to be tracked */
559static int edp_notify_handler(struct notifier_block *this, unsigned long code,
560 void *unused)
561{
562 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
563 edp_notifier);
564 struct drm_device *dev = intel_dp_to_dev(intel_dp);
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 u32 pp_div;
567 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 568
569 if (!is_edp(intel_dp) || code != SYS_RESTART)
570 return 0;
571
773538e8 572 pps_lock(intel_dp);
e39b999a 573
01527b31 574 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 575 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
576
01527b31
CT		 577 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
578 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
579 pp_div = I915_READ(pp_div_reg);
580 pp_div &= PP_REFERENCE_DIVIDER_MASK;
581
582 /* 0x1F write to PP_DIV_REG sets max cycle delay */
583 I915_WRITE(pp_div_reg, pp_div | 0x1F);
584 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
585 msleep(intel_dp->panel_power_cycle_delay);
586 }
587
773538e8 588 pps_unlock(intel_dp);
e39b999a 589
01527b31
CT		 590 return 0;
591}
592
4be73780 593static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 594{
30add22d 595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 596 struct drm_i915_private *dev_priv = dev->dev_private;
597
e39b999a
VS		 598 lockdep_assert_held(&dev_priv->pps_mutex);
599
9a42356b
VS		 600 if (IS_VALLEYVIEW(dev) &&
601 intel_dp->pps_pipe == INVALID_PIPE)
602 return false;
603
bf13e81b 604 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 605}
606
4be73780 607static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 608{
30add22d 609 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 610 struct drm_i915_private *dev_priv = dev->dev_private;
611
e39b999a
VS		 612 lockdep_assert_held(&dev_priv->pps_mutex);
613
9a42356b
VS		 614 if (IS_VALLEYVIEW(dev) &&
615 intel_dp->pps_pipe == INVALID_PIPE)
616 return false;
617
773538e8 618 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 619}
620
9b984dae
KP		 621static void
622intel_dp_check_edp(struct intel_dp *intel_dp)
623{
30add22d 624 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 625 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 626
9b984dae
KP		 627 if (!is_edp(intel_dp))
628 return;
453c5420 629
4be73780 630 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 631 WARN(1, "eDP powered off while attempting aux channel communication.\n");
632 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 633 I915_READ(_pp_stat_reg(intel_dp)),
634 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 635 }
636}
637
9ee32fea
DV		 638static uint32_t
639intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
640{
641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
642 struct drm_device *dev = intel_dig_port->base.base.dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 644 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 645 uint32_t status;
646 bool done;
647
ef04f00d 648#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 649 if (has_aux_irq)
b18ac466 650 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 651 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 652 else
653 done = wait_for_atomic(C, 10) == 0;
654 if (!done)
655 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
656 has_aux_irq);
657#undef C
658
659 return status;
660}
661
ec5b01dd 662static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 663{
174edf1f
PZ		 664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
665 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 666
ec5b01dd
DL		 667 /*
668 * The clock divider is based off the hrawclk, and would like to run at
669 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 670 */
ec5b01dd
DL		 671 return index ? 0 : intel_hrawclk(dev) / 2;
672}
673
674static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
675{
676 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
677 struct drm_device *dev = intel_dig_port->base.base.dev;
678
679 if (index)
680 return 0;
681
682 if (intel_dig_port->port == PORT_A) {
683 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 684 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 685 else
b84a1cf8 686 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 687 } else {
688 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
689 }
690}
691
692static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
693{
694 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
695 struct drm_device *dev = intel_dig_port->base.base.dev;
696 struct drm_i915_private *dev_priv = dev->dev_private;
697
698 if (intel_dig_port->port == PORT_A) {
699 if (index)
700 return 0;
701 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 702 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
703 /* Workaround for non-ULT HSW */
bc86625a
CW		 704 switch (index) {
705 case 0: return 63;
706 case 1: return 72;
707 default: return 0;
708 }
ec5b01dd 709 } else {
bc86625a 710 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 711 }
b84a1cf8
RV		 712}
713
ec5b01dd
DL		 714static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
715{
716 return index ? 0 : 100;
717}
718
b6b5e383
DL		 719static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
720{
721 /*
722 * SKL doesn't need us to program the AUX clock divider (Hardware will
723 * derive the clock from CDCLK automatically). We still implement the
724 * get_aux_clock_divider vfunc to plug-in into the existing code.
725 */
726 return index ? 0 : 1;
727}
728
5ed12a19
DL		 729static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
730 bool has_aux_irq,
731 int send_bytes,
732 uint32_t aux_clock_divider)
733{
734 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
735 struct drm_device *dev = intel_dig_port->base.base.dev;
736 uint32_t precharge, timeout;
737
738 if (IS_GEN6(dev))
739 precharge = 3;
740 else
741 precharge = 5;
742
743 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
744 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
745 else
746 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
747
748 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 749 DP_AUX_CH_CTL_DONE |
5ed12a19 750 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 751 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 752 timeout |
788d4433 753 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 754 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
755 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 756 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 757}
758
b9ca5fad
DL		 759static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
760 bool has_aux_irq,
761 int send_bytes,
762 uint32_t unused)
763{
764 return DP_AUX_CH_CTL_SEND_BUSY |
765 DP_AUX_CH_CTL_DONE |
766 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
767 DP_AUX_CH_CTL_TIME_OUT_ERROR |
768 DP_AUX_CH_CTL_TIME_OUT_1600us |
769 DP_AUX_CH_CTL_RECEIVE_ERROR |
770 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
771 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
772}
773
b84a1cf8
RV		 774static int
775intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 776 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 777 uint8_t *recv, int recv_size)
778{
779 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
780 struct drm_device *dev = intel_dig_port->base.base.dev;
781 struct drm_i915_private *dev_priv = dev->dev_private;
782 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
783 uint32_t ch_data = ch_ctl + 4;
bc86625a 784 uint32_t aux_clock_divider;
b84a1cf8
RV		 785 int i, ret, recv_bytes;
786 uint32_t status;
5ed12a19 787 int try, clock = 0;
4e6b788c 788 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 789 bool vdd;
790
773538e8 791 pps_lock(intel_dp);
e39b999a 792
72c3500a
VS		 793 /*
794 * We will be called with VDD already enabled for dpcd/edid/oui reads.
795 * In such cases we want to leave VDD enabled and it's up to upper layers
796 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
797 * ourselves.
798 */
1e0560e0 799 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 800
801 /* dp aux is extremely sensitive to irq latency, hence request the
802 * lowest possible wakeup latency and so prevent the cpu from going into
803 * deep sleep states.
804 */
805 pm_qos_update_request(&dev_priv->pm_qos, 0);
806
807 intel_dp_check_edp(intel_dp);
5eb08b69 808
c67a470b
PZ		 809 intel_aux_display_runtime_get(dev_priv);
810
11bee43e
JB		 811 /* Try to wait for any previous AUX channel activity */
812 for (try = 0; try < 3; try++) {
ef04f00d 813 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 814 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
815 break;
816 msleep(1);
817 }
818
819 if (try == 3) {
820 WARN(1, "dp_aux_ch not started status 0x%08x\n",
821 I915_READ(ch_ctl));
9ee32fea
DV		 822 ret = -EBUSY;
823 goto out;
4f7f7b7e
CW		 824 }
825
46a5ae9f
PZ		 826 /* Only 5 data registers! */
827 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
828 ret = -E2BIG;
829 goto out;
830 }
831
ec5b01dd 832 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 833 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
834 has_aux_irq,
835 send_bytes,
836 aux_clock_divider);
5ed12a19 837
bc86625a
CW		 838 /* Must try at least 3 times according to DP spec */
839 for (try = 0; try < 5; try++) {
840 /* Load the send data into the aux channel data registers */
841 for (i = 0; i < send_bytes; i += 4)
842 I915_WRITE(ch_data + i,
843 pack_aux(send + i, send_bytes - i));
844
845 /* Send the command and wait for it to complete */
5ed12a19 846 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 847
848 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
849
850 /* Clear done status and any errors */
851 I915_WRITE(ch_ctl,
852 status |
853 DP_AUX_CH_CTL_DONE |
854 DP_AUX_CH_CTL_TIME_OUT_ERROR |
855 DP_AUX_CH_CTL_RECEIVE_ERROR);
856
857 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
858 DP_AUX_CH_CTL_RECEIVE_ERROR))
859 continue;
860 if (status & DP_AUX_CH_CTL_DONE)
861 break;
862 }
4f7f7b7e 863 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 864 break;
865 }
866
a4fc5ed6 867 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 868 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 869 ret = -EBUSY;
870 goto out;
a4fc5ed6
KP		 871 }
872
873 /* Check for timeout or receive error.
874 * Timeouts occur when the sink is not connected
875 */
a5b3da54 876 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 877 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 878 ret = -EIO;
879 goto out;
a5b3da54 880 }
1ae8c0a5
KP		 881
882 /* Timeouts occur when the device isn't connected, so they're
883 * "normal" -- don't fill the kernel log with these */
a5b3da54 884 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 885 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 886 ret = -ETIMEDOUT;
887 goto out;
a4fc5ed6
KP		 888 }
889
890 /* Unload any bytes sent back from the other side */
891 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
892 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 893 if (recv_bytes > recv_size)
894 recv_bytes = recv_size;
0206e353 895
4f7f7b7e
CW		 896 for (i = 0; i < recv_bytes; i += 4)
897 unpack_aux(I915_READ(ch_data + i),
898 recv + i, recv_bytes - i);
a4fc5ed6 899
9ee32fea
DV		 900 ret = recv_bytes;
901out:
902 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 903 intel_aux_display_runtime_put(dev_priv);
9ee32fea 904
884f19e9
JN		 905 if (vdd)
906 edp_panel_vdd_off(intel_dp, false);
907
773538e8 908 pps_unlock(intel_dp);
e39b999a 909
9ee32fea 910 return ret;
a4fc5ed6
KP		 911}
912
a6c8aff0
JN		 913#define BARE_ADDRESS_SIZE 3
914#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 915static ssize_t
916intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 917{
9d1a1031
JN		 918 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
919 uint8_t txbuf[20], rxbuf[20];
920 size_t txsize, rxsize;
a4fc5ed6 921 int ret;
a4fc5ed6 922
9d1a1031
JN		 923 txbuf[0] = msg->request << 4;
924 txbuf[1] = msg->address >> 8;
925 txbuf[2] = msg->address & 0xff;
926 txbuf[3] = msg->size - 1;
46a5ae9f 927
9d1a1031
JN		 928 switch (msg->request & ~DP_AUX_I2C_MOT) {
929 case DP_AUX_NATIVE_WRITE:
930 case DP_AUX_I2C_WRITE:
a6c8aff0 931 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 932 rxsize = 1;
f51a44b9 933
9d1a1031
JN		 934 if (WARN_ON(txsize > 20))
935 return -E2BIG;
a4fc5ed6 936
9d1a1031 937 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 938
9d1a1031
JN		 939 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
940 if (ret > 0) {
941 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 942
9d1a1031
JN		 943 /* Return payload size. */
944 ret = msg->size;
945 }
946 break;
46a5ae9f 947
9d1a1031
JN		 948 case DP_AUX_NATIVE_READ:
949 case DP_AUX_I2C_READ:
a6c8aff0 950 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 951 rxsize = msg->size + 1;
a4fc5ed6 952
9d1a1031
JN		 953 if (WARN_ON(rxsize > 20))
954 return -E2BIG;
a4fc5ed6 955
9d1a1031
JN		 956 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
957 if (ret > 0) {
958 msg->reply = rxbuf[0] >> 4;
959 /*
960 * Assume happy day, and copy the data. The caller is
961 * expected to check msg->reply before touching it.
962 *
963 * Return payload size.
964 */
965 ret--;
966 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 967 }
9d1a1031
JN		 968 break;
969
970 default:
971 ret = -EINVAL;
972 break;
a4fc5ed6 973 }
f51a44b9 974
9d1a1031 975 return ret;
a4fc5ed6
KP		 976}
977
9d1a1031
JN		 978static void
979intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
980{
981 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 982 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
983 enum port port = intel_dig_port->port;
0b99836f 984 const char *name = NULL;
ab2c0672
DA		 985 int ret;
986
33ad6626
JN		 987 switch (port) {
988 case PORT_A:
989 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 990 name = "DPDDC-A";
ab2c0672 991 break;
33ad6626
JN		 992 case PORT_B:
993 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 994 name = "DPDDC-B";
ab2c0672 995 break;
33ad6626
JN		 996 case PORT_C:
997 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 998 name = "DPDDC-C";
ab2c0672 999 break;
33ad6626
JN		 1000 case PORT_D:
1001 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1002 name = "DPDDC-D";
33ad6626
JN		 1003 break;
1004 default:
1005 BUG();
ab2c0672
DA		 1006 }
1007
1b1aad75
DL		 1008 /*
1009 * The AUX_CTL register is usually DP_CTL + 0x10.
1010 *
1011 * On Haswell and Broadwell though:
1012 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1013 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1014 *
1015 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1016 */
1017 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1018 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1019
0b99836f 1020 intel_dp->aux.name = name;
9d1a1031
JN		 1021 intel_dp->aux.dev = dev->dev;
1022 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1023
0b99836f
JN		 1024 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1025 connector->base.kdev->kobj.name);
8316f337 1026
4f71d0cb 1027 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1028 if (ret < 0) {
4f71d0cb 1029 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1030 name, ret);
1031 return;
ab2c0672 1032 }
8a5e6aeb 1033
0b99836f
JN		 1034 ret = sysfs_create_link(&connector->base.kdev->kobj,
1035 &intel_dp->aux.ddc.dev.kobj,
1036 intel_dp->aux.ddc.dev.kobj.name);
1037 if (ret < 0) {
1038 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1039 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1040 }
a4fc5ed6
KP		 1041}
1042
80f65de3
ID		 1043static void
1044intel_dp_connector_unregister(struct intel_connector *intel_connector)
1045{
1046 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1047
0e32b39c
DA		 1048 if (!intel_connector->mst_port)
1049 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1050 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1051 intel_connector_unregister(intel_connector);
1052}
1053
0e50338c
DV		 1054static void
1055hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1056{
1057 switch (link_bw) {
1058 case DP_LINK_BW_1_62:
1059 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1060 break;
1061 case DP_LINK_BW_2_7:
1062 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1063 break;
1064 case DP_LINK_BW_5_4:
1065 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1066 break;
1067 }
1068}
1069
c6bb3538
DV		 1070static void
1071intel_dp_set_clock(struct intel_encoder *encoder,
1072 struct intel_crtc_config *pipe_config, int link_bw)
1073{
1074 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1075 const struct dp_link_dpll *divisor = NULL;
1076 int i, count = 0;
c6bb3538
DV		 1077
1078 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1079 divisor = gen4_dpll;
1080 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1081 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1082 divisor = pch_dpll;
1083 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1084 } else if (IS_CHERRYVIEW(dev)) {
1085 divisor = chv_dpll;
1086 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1087 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1088 divisor = vlv_dpll;
1089 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1090 }
9dd4ffdf
CML		 1091
1092 if (divisor && count) {
1093 for (i = 0; i < count; i++) {
1094 if (link_bw == divisor[i].link_bw) {
1095 pipe_config->dpll = divisor[i].dpll;
1096 pipe_config->clock_set = true;
1097 break;
1098 }
1099 }
c6bb3538
DV		 1100 }
1101}
1102
00c09d70 1103bool
5bfe2ac0
DV		 1104intel_dp_compute_config(struct intel_encoder *encoder,
1105 struct intel_crtc_config *pipe_config)
a4fc5ed6 1106{
5bfe2ac0 1107 struct drm_device *dev = encoder->base.dev;
36008365 1108 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1109 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1110 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1111 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1112 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1113 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1114 int lane_count, clock;
56071a20 1115 int min_lane_count = 1;
eeb6324d 1116 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1117 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1118 int min_clock = 0;
06ea66b6 1119 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1120 int bpp, mode_rate;
06ea66b6 1121 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1122 int link_avail, link_clock;
a4fc5ed6 1123
bc7d38a4 1124 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1125 pipe_config->has_pch_encoder = true;
1126
03afc4a2 1127 pipe_config->has_dp_encoder = true;
f769cd24 1128 pipe_config->has_drrs = false;
9ed109a7 1129 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1130
dd06f90e
JN		 1131 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1132 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1133 adjusted_mode);
2dd24552
JB		 1134 if (!HAS_PCH_SPLIT(dev))
1135 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1136 intel_connector->panel.fitting_mode);
1137 else
b074cec8
JB		 1138 intel_pch_panel_fitting(intel_crtc, pipe_config,
1139 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1140 }
1141
cb1793ce 1142 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1143 return false;
1144
083f9560
DV		 1145 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1146 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1147 max_lane_count, bws[max_clock],
1148 adjusted_mode->crtc_clock);
083f9560 1149
36008365
DV		 1150 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1151 * bpc in between. */
3e7ca985 1152 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1153 if (is_edp(intel_dp)) {
1154 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1155 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1156 dev_priv->vbt.edp_bpp);
1157 bpp = dev_priv->vbt.edp_bpp;
1158 }
1159
344c5bbc
JN		 1160 /*
1161 * Use the maximum clock and number of lanes the eDP panel
1162 * advertizes being capable of. The panels are generally
1163 * designed to support only a single clock and lane
1164 * configuration, and typically these values correspond to the
1165 * native resolution of the panel.
1166 */
1167 min_lane_count = max_lane_count;
1168 min_clock = max_clock;
7984211e 1169 }
657445fe 1170
36008365 1171 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1172 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1173 bpp);
36008365 1174
c6930992
DA		 1175 for (clock = min_clock; clock <= max_clock; clock++) {
1176 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1177 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1178 link_avail = intel_dp_max_data_rate(link_clock,
1179 lane_count);
1180
1181 if (mode_rate <= link_avail) {
1182 goto found;
1183 }
1184 }
1185 }
1186 }
c4867936 1187
36008365 1188 return false;
3685a8f3 1189
36008365 1190found:
55bc60db
VS		 1191 if (intel_dp->color_range_auto) {
1192 /*
1193 * See:
1194 * CEA-861-E - 5.1 Default Encoding Parameters
1195 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1196 */
18316c8c 1197 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1198 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1199 else
1200 intel_dp->color_range = 0;
1201 }
1202
3685a8f3 1203 if (intel_dp->color_range)
50f3b016 1204 pipe_config->limited_color_range = true;
a4fc5ed6 1205
36008365
DV		 1206 intel_dp->link_bw = bws[clock];
1207 intel_dp->lane_count = lane_count;
657445fe 1208 pipe_config->pipe_bpp = bpp;
ff9a6750 1209 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1210
36008365
DV		 1211 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1212 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1213 pipe_config->port_clock, bpp);
36008365
DV		 1214 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1215 mode_rate, link_avail);
a4fc5ed6 1216
03afc4a2 1217 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1218 adjusted_mode->crtc_clock,
1219 pipe_config->port_clock,
03afc4a2 1220 &pipe_config->dp_m_n);
9d1a455b 1221
439d7ac0
PB		 1222 if (intel_connector->panel.downclock_mode != NULL &&
1223 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1224 pipe_config->has_drrs = true;
439d7ac0
PB		 1225 intel_link_compute_m_n(bpp, lane_count,
1226 intel_connector->panel.downclock_mode->clock,
1227 pipe_config->port_clock,
1228 &pipe_config->dp_m2_n2);
1229 }
1230
ea155f32 1231 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1232 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1233 else
1234 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1235
03afc4a2 1236 return true;
a4fc5ed6
KP		 1237}
1238
7c62a164 1239static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1240{
7c62a164
DV		 1241 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1242 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1243 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1244 struct drm_i915_private *dev_priv = dev->dev_private;
1245 u32 dpa_ctl;
1246
ff9a6750 1247 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1248 dpa_ctl = I915_READ(DP_A);
1249 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1250
ff9a6750 1251 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1252 /* For a long time we've carried around a ILK-DevA w/a for the
1253 * 160MHz clock. If we're really unlucky, it's still required.
1254 */
1255 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1256 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1257 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1258 } else {
1259 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1260 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1261 }
1ce17038 1262
ea9b6006
DV		 1263 I915_WRITE(DP_A, dpa_ctl);
1264
1265 POSTING_READ(DP_A);
1266 udelay(500);
1267}
1268
8ac33ed3 1269static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1270{
b934223d 1271 struct drm_device *dev = encoder->base.dev;
417e822d 1272 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1273 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1274 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1275 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1276 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1277
417e822d 1278 /*
1a2eb460 1279 * There are four kinds of DP registers:
417e822d
KP		 1280 *
1281 * IBX PCH
1a2eb460
KP		 1282 * SNB CPU
1283 * IVB CPU
417e822d
KP		 1284 * CPT PCH
1285 *
1286 * IBX PCH and CPU are the same for almost everything,
1287 * except that the CPU DP PLL is configured in this
1288 * register
1289 *
1290 * CPT PCH is quite different, having many bits moved
1291 * to the TRANS_DP_CTL register instead. That
1292 * configuration happens (oddly) in ironlake_pch_enable
1293 */
9c9e7927 1294
417e822d
KP		 1295 /* Preserve the BIOS-computed detected bit. This is
1296 * supposed to be read-only.
1297 */
1298 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1299
417e822d 1300 /* Handle DP bits in common between all three register formats */
417e822d 1301 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1302 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1303
9ed109a7 1304 if (crtc->config.has_audio) {
e0dac65e 1305 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1306 pipe_name(crtc->pipe));
ea5b213a 1307 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1308 intel_write_eld(encoder);
e0dac65e 1309 }
247d89f6 1310
417e822d 1311 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1312
bc7d38a4 1313 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1314 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1315 intel_dp->DP |= DP_SYNC_HS_HIGH;
1316 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1317 intel_dp->DP |= DP_SYNC_VS_HIGH;
1318 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1319
6aba5b6c 1320 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1321 intel_dp->DP |= DP_ENHANCED_FRAMING;
1322
7c62a164 1323 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1324 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1325 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1326 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1327
1328 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1329 intel_dp->DP |= DP_SYNC_HS_HIGH;
1330 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1331 intel_dp->DP |= DP_SYNC_VS_HIGH;
1332 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1333
6aba5b6c 1334 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1335 intel_dp->DP |= DP_ENHANCED_FRAMING;
1336
44f37d1f
CML		 1337 if (!IS_CHERRYVIEW(dev)) {
1338 if (crtc->pipe == 1)
1339 intel_dp->DP |= DP_PIPEB_SELECT;
1340 } else {
1341 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1342 }
417e822d
KP		 1343 } else {
1344 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1345 }
a4fc5ed6
KP		 1346}
1347
ffd6749d
PZ		 1348#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1349#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1350
1a5ef5b7
PZ		 1351#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1352#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1353
ffd6749d
PZ		 1354#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1355#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1356
4be73780 1357static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1358 u32 mask,
1359 u32 value)
bd943159 1360{
30add22d 1361 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1362 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1363 u32 pp_stat_reg, pp_ctrl_reg;
1364
e39b999a
VS		 1365 lockdep_assert_held(&dev_priv->pps_mutex);
1366
bf13e81b
JN		 1367 pp_stat_reg = _pp_stat_reg(intel_dp);
1368 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1369
99ea7127 1370 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1371 mask, value,
1372 I915_READ(pp_stat_reg),
1373 I915_READ(pp_ctrl_reg));
32ce697c 1374
453c5420 1375 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1376 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1377 I915_READ(pp_stat_reg),
1378 I915_READ(pp_ctrl_reg));
32ce697c 1379 }
54c136d4
CW		 1380
1381 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1382}
32ce697c 1383
4be73780 1384static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1385{
1386 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1387 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1388}
1389
4be73780 1390static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1391{
1392 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1393 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1394}
1395
4be73780 1396static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1397{
1398 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1399
1400 /* When we disable the VDD override bit last we have to do the manual
1401 * wait. */
1402 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1403 intel_dp->panel_power_cycle_delay);
1404
4be73780 1405 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1406}
1407
4be73780 1408static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1409{
1410 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1411 intel_dp->backlight_on_delay);
1412}
1413
4be73780 1414static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1415{
1416 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1417 intel_dp->backlight_off_delay);
1418}
99ea7127 1419
832dd3c1
KP		 1420/* Read the current pp_control value, unlocking the register if it
1421 * is locked
1422 */
1423
453c5420 1424static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1425{
453c5420
JB		 1426 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 u32 control;
832dd3c1 1429
e39b999a
VS		 1430 lockdep_assert_held(&dev_priv->pps_mutex);
1431
bf13e81b 1432 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1433 control &= ~PANEL_UNLOCK_MASK;
1434 control |= PANEL_UNLOCK_REGS;
1435 return control;
bd943159
KP		 1436}
1437
951468f3
VS		 1438/*
1439 * Must be paired with edp_panel_vdd_off().
1440 * Must hold pps_mutex around the whole on/off sequence.
1441 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1442 */
1e0560e0 1443static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1444{
30add22d 1445 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1447 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1448 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1449 enum intel_display_power_domain power_domain;
5d613501 1450 u32 pp;
453c5420 1451 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1452 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1453
e39b999a
VS		 1454 lockdep_assert_held(&dev_priv->pps_mutex);
1455
97af61f5 1456 if (!is_edp(intel_dp))
adddaaf4 1457 return false;
bd943159
KP		 1458
1459 intel_dp->want_panel_vdd = true;
99ea7127 1460
4be73780 1461 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1462 return need_to_disable;
b0665d57 1463
4e6e1a54
ID		 1464 power_domain = intel_display_port_power_domain(intel_encoder);
1465 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1466
b0665d57 1467 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1468
4be73780
DV		 1469 if (!edp_have_panel_power(intel_dp))
1470 wait_panel_power_cycle(intel_dp);
99ea7127 1471
453c5420 1472 pp = ironlake_get_pp_control(intel_dp);
5d613501 1473 pp |= EDP_FORCE_VDD;
ebf33b18 1474
bf13e81b
JN		 1475 pp_stat_reg = _pp_stat_reg(intel_dp);
1476 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1477
1478 I915_WRITE(pp_ctrl_reg, pp);
1479 POSTING_READ(pp_ctrl_reg);
1480 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1481 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1482 /*
1483 * If the panel wasn't on, delay before accessing aux channel
1484 */
4be73780 1485 if (!edp_have_panel_power(intel_dp)) {
bd943159 1486 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1487 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1488 }
adddaaf4
JN		 1489
1490 return need_to_disable;
1491}
1492
951468f3
VS		 1493/*
1494 * Must be paired with intel_edp_panel_vdd_off() or
1495 * intel_edp_panel_off().
1496 * Nested calls to these functions are not allowed since
1497 * we drop the lock. Caller must use some higher level
1498 * locking to prevent nested calls from other threads.
1499 */
b80d6c78 1500void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1501{
c695b6b6 1502 bool vdd;
adddaaf4 1503
c695b6b6
VS		 1504 if (!is_edp(intel_dp))
1505 return;
1506
773538e8 1507 pps_lock(intel_dp);
c695b6b6 1508 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1509 pps_unlock(intel_dp);
c695b6b6
VS		 1510
1511 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1512}
1513
4be73780 1514static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1515{
30add22d 1516 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1517 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1518 struct intel_digital_port *intel_dig_port =
1519 dp_to_dig_port(intel_dp);
1520 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1521 enum intel_display_power_domain power_domain;
5d613501 1522 u32 pp;
453c5420 1523 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1524
e39b999a 1525 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1526
15e899a0 1527 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1528
15e899a0 1529 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1530 return;
b0665d57 1531
be2c9196 1532 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1533
be2c9196
VS		 1534 pp = ironlake_get_pp_control(intel_dp);
1535 pp &= ~EDP_FORCE_VDD;
453c5420 1536
be2c9196
VS		 1537 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1538 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1539
be2c9196
VS		 1540 I915_WRITE(pp_ctrl_reg, pp);
1541 POSTING_READ(pp_ctrl_reg);
90791a5c 1542
be2c9196
VS		 1543 /* Make sure sequencer is idle before allowing subsequent activity */
1544 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1545 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1546
be2c9196
VS		 1547 if ((pp & POWER_TARGET_ON) == 0)
1548 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1549
be2c9196
VS		 1550 power_domain = intel_display_port_power_domain(intel_encoder);
1551 intel_display_power_put(dev_priv, power_domain);
bd943159 1552}
5d613501 1553
4be73780 1554static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1555{
1556 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1557 struct intel_dp, panel_vdd_work);
bd943159 1558
773538e8 1559 pps_lock(intel_dp);
15e899a0
VS		 1560 if (!intel_dp->want_panel_vdd)
1561 edp_panel_vdd_off_sync(intel_dp);
773538e8 1562 pps_unlock(intel_dp);
bd943159
KP		 1563}
1564
aba86890
ID		 1565static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1566{
1567 unsigned long delay;
1568
1569 /*
1570 * Queue the timer to fire a long time from now (relative to the power
1571 * down delay) to keep the panel power up across a sequence of
1572 * operations.
1573 */
1574 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1575 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1576}
1577
951468f3
VS		 1578/*
1579 * Must be paired with edp_panel_vdd_on().
1580 * Must hold pps_mutex around the whole on/off sequence.
1581 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1582 */
4be73780 1583static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1584{
e39b999a
VS		 1585 struct drm_i915_private *dev_priv =
1586 intel_dp_to_dev(intel_dp)->dev_private;
1587
1588 lockdep_assert_held(&dev_priv->pps_mutex);
1589
97af61f5
KP		 1590 if (!is_edp(intel_dp))
1591 return;
5d613501 1592
bd943159 1593 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1594
bd943159
KP		 1595 intel_dp->want_panel_vdd = false;
1596
aba86890 1597 if (sync)
4be73780 1598 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1599 else
1600 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1601}
1602
9f0fb5be 1603static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1604{
30add22d 1605 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1606 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1607 u32 pp;
453c5420 1608 u32 pp_ctrl_reg;
9934c132 1609
9f0fb5be
VS		 1610 lockdep_assert_held(&dev_priv->pps_mutex);
1611
97af61f5 1612 if (!is_edp(intel_dp))
bd943159 1613 return;
99ea7127
KP		 1614
1615 DRM_DEBUG_KMS("Turn eDP power on\n");
1616
4be73780 1617 if (edp_have_panel_power(intel_dp)) {
99ea7127 1618 DRM_DEBUG_KMS("eDP power already on\n");
9f0fb5be 1619 return;
99ea7127 1620 }
9934c132 1621
4be73780 1622 wait_panel_power_cycle(intel_dp);
37c6c9b0 1623
bf13e81b 1624 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1625 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1626 if (IS_GEN5(dev)) {
1627 /* ILK workaround: disable reset around power sequence */
1628 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1629 I915_WRITE(pp_ctrl_reg, pp);
1630 POSTING_READ(pp_ctrl_reg);
05ce1a49 1631 }
37c6c9b0 1632
1c0ae80a 1633 pp |= POWER_TARGET_ON;
99ea7127
KP		 1634 if (!IS_GEN5(dev))
1635 pp |= PANEL_POWER_RESET;
1636
453c5420
JB		 1637 I915_WRITE(pp_ctrl_reg, pp);
1638 POSTING_READ(pp_ctrl_reg);
9934c132 1639
4be73780 1640 wait_panel_on(intel_dp);
dce56b3c 1641 intel_dp->last_power_on = jiffies;
9934c132 1642
05ce1a49
KP		 1643 if (IS_GEN5(dev)) {
1644 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1645 I915_WRITE(pp_ctrl_reg, pp);
1646 POSTING_READ(pp_ctrl_reg);
05ce1a49 1647 }
9f0fb5be 1648}
e39b999a 1649
9f0fb5be
VS		 1650void intel_edp_panel_on(struct intel_dp *intel_dp)
1651{
1652 if (!is_edp(intel_dp))
1653 return;
1654
1655 pps_lock(intel_dp);
1656 edp_panel_on(intel_dp);
773538e8 1657 pps_unlock(intel_dp);
9934c132
JB		 1658}
1659
9f0fb5be
VS		 1660
1661static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1662{
4e6e1a54
ID		 1663 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1664 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1665 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1666 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1667 enum intel_display_power_domain power_domain;
99ea7127 1668 u32 pp;
453c5420 1669 u32 pp_ctrl_reg;
9934c132 1670
9f0fb5be
VS		 1671 lockdep_assert_held(&dev_priv->pps_mutex);
1672
97af61f5
KP		 1673 if (!is_edp(intel_dp))
1674 return;
37c6c9b0 1675
99ea7127 1676 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1677
24f3e092
JN		 1678 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1679
453c5420 1680 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1681 /* We need to switch off panel power _and_ force vdd, for otherwise some
1682 * panels get very unhappy and cease to work. */
b3064154
PJ		 1683 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1684 EDP_BLC_ENABLE);
453c5420 1685
bf13e81b 1686 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1687
849e39f5
PZ		 1688 intel_dp->want_panel_vdd = false;
1689
453c5420
JB		 1690 I915_WRITE(pp_ctrl_reg, pp);
1691 POSTING_READ(pp_ctrl_reg);
9934c132 1692
dce56b3c 1693 intel_dp->last_power_cycle = jiffies;
4be73780 1694 wait_panel_off(intel_dp);
849e39f5
PZ		 1695
1696 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1697 power_domain = intel_display_port_power_domain(intel_encoder);
1698 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1699}
e39b999a 1700
9f0fb5be
VS		 1701void intel_edp_panel_off(struct intel_dp *intel_dp)
1702{
1703 if (!is_edp(intel_dp))
1704 return;
1705
1706 pps_lock(intel_dp);
1707 edp_panel_off(intel_dp);
773538e8 1708 pps_unlock(intel_dp);
9934c132
JB		 1709}
1710
1250d107
JN		 1711/* Enable backlight in the panel power control. */
1712static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1713{
da63a9f2
PZ		 1714 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1715 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 u32 pp;
453c5420 1718 u32 pp_ctrl_reg;
32f9d658 1719
01cb9ea6
JB		 1720 /*
1721 * If we enable the backlight right away following a panel power
1722 * on, we may see slight flicker as the panel syncs with the eDP
1723 * link. So delay a bit to make sure the image is solid before
1724 * allowing it to appear.
1725 */
4be73780 1726 wait_backlight_on(intel_dp);
e39b999a 1727
773538e8 1728 pps_lock(intel_dp);
e39b999a 1729
453c5420 1730 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1731 pp |= EDP_BLC_ENABLE;
453c5420 1732
bf13e81b 1733 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1734
1735 I915_WRITE(pp_ctrl_reg, pp);
1736 POSTING_READ(pp_ctrl_reg);
e39b999a 1737
773538e8 1738 pps_unlock(intel_dp);
32f9d658
ZW		 1739}
1740
1250d107
JN		 1741/* Enable backlight PWM and backlight PP control. */
1742void intel_edp_backlight_on(struct intel_dp *intel_dp)
1743{
1744 if (!is_edp(intel_dp))
1745 return;
1746
1747 DRM_DEBUG_KMS("\n");
1748
1749 intel_panel_enable_backlight(intel_dp->attached_connector);
1750 _intel_edp_backlight_on(intel_dp);
1751}
1752
1753/* Disable backlight in the panel power control. */
1754static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1755{
30add22d 1756 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 u32 pp;
453c5420 1759 u32 pp_ctrl_reg;
32f9d658 1760
f01eca2e
KP		 1761 if (!is_edp(intel_dp))
1762 return;
1763
773538e8 1764 pps_lock(intel_dp);
e39b999a 1765
453c5420 1766 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1767 pp &= ~EDP_BLC_ENABLE;
453c5420 1768
bf13e81b 1769 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1770
1771 I915_WRITE(pp_ctrl_reg, pp);
1772 POSTING_READ(pp_ctrl_reg);
f7d2323c 1773
773538e8 1774 pps_unlock(intel_dp);
e39b999a
VS		 1775
1776 intel_dp->last_backlight_off = jiffies;
f7d2323c 1777 edp_wait_backlight_off(intel_dp);
1250d107 1778}
f7d2323c 1779
1250d107
JN		 1780/* Disable backlight PP control and backlight PWM. */
1781void intel_edp_backlight_off(struct intel_dp *intel_dp)
1782{
1783 if (!is_edp(intel_dp))
1784 return;
1785
1786 DRM_DEBUG_KMS("\n");
f7d2323c 1787
1250d107 1788 _intel_edp_backlight_off(intel_dp);
f7d2323c 1789 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1790}
a4fc5ed6 1791
73580fb7
JN		 1792/*
1793 * Hook for controlling the panel power control backlight through the bl_power
1794 * sysfs attribute. Take care to handle multiple calls.
1795 */
1796static void intel_edp_backlight_power(struct intel_connector *connector,
1797 bool enable)
1798{
1799 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1800 bool is_enabled;
1801
773538e8 1802 pps_lock(intel_dp);
e39b999a 1803 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1804 pps_unlock(intel_dp);
73580fb7
JN		 1805
1806 if (is_enabled == enable)
1807 return;
1808
23ba9373
JN		 1809 DRM_DEBUG_KMS("panel power control backlight %s\n",
1810 enable ? "enable" : "disable");
73580fb7
JN		 1811
1812 if (enable)
1813 _intel_edp_backlight_on(intel_dp);
1814 else
1815 _intel_edp_backlight_off(intel_dp);
1816}
1817
2bd2ad64 1818static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1819{
da63a9f2
PZ		 1820 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1821 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1822 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 u32 dpa_ctl;
1825
2bd2ad64
DV		 1826 assert_pipe_disabled(dev_priv,
1827 to_intel_crtc(crtc)->pipe);
1828
d240f20f
JB		 1829 DRM_DEBUG_KMS("\n");
1830 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1831 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1832 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1833
1834 /* We don't adjust intel_dp->DP while tearing down the link, to
1835 * facilitate link retraining (e.g. after hotplug). Hence clear all
1836 * enable bits here to ensure that we don't enable too much. */
1837 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1838 intel_dp->DP |= DP_PLL_ENABLE;
1839 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1840 POSTING_READ(DP_A);
1841 udelay(200);
d240f20f
JB		 1842}
1843
2bd2ad64 1844static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1845{
da63a9f2
PZ		 1846 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1847 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1848 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 u32 dpa_ctl;
1851
2bd2ad64
DV		 1852 assert_pipe_disabled(dev_priv,
1853 to_intel_crtc(crtc)->pipe);
1854
d240f20f 1855 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1856 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1857 "dp pll off, should be on\n");
1858 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1859
1860 /* We can't rely on the value tracked for the DP register in
1861 * intel_dp->DP because link_down must not change that (otherwise link
1862 * re-training will fail. */
298b0b39 1863 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1864 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1865 POSTING_READ(DP_A);
d240f20f
JB		 1866 udelay(200);
1867}
1868
c7ad3810 1869/* If the sink supports it, try to set the power state appropriately */
c19b0669 1870void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1871{
1872 int ret, i;
1873
1874 /* Should have a valid DPCD by this point */
1875 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1876 return;
1877
1878 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1879 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1880 DP_SET_POWER_D3);
c7ad3810
JB		 1881 } else {
1882 /*
1883 * When turning on, we need to retry for 1ms to give the sink
1884 * time to wake up.
1885 */
1886 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1887 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1888 DP_SET_POWER_D0);
c7ad3810
JB		 1889 if (ret == 1)
1890 break;
1891 msleep(1);
1892 }
1893 }
f9cac721
JN		 1894
1895 if (ret != 1)
1896 DRM_DEBUG_KMS("failed to %s sink power state\n",
1897 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1898}
1899
19d8fe15
DV		 1900static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1901 enum pipe *pipe)
d240f20f 1902{
19d8fe15 1903 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1904 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1905 struct drm_device *dev = encoder->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1907 enum intel_display_power_domain power_domain;
1908 u32 tmp;
1909
1910 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1911 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1912 return false;
1913
1914 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1915
1916 if (!(tmp & DP_PORT_EN))
1917 return false;
1918
bc7d38a4 1919 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1920 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1921 } else if (IS_CHERRYVIEW(dev)) {
1922 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1923 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1924 *pipe = PORT_TO_PIPE(tmp);
1925 } else {
1926 u32 trans_sel;
1927 u32 trans_dp;
1928 int i;
1929
1930 switch (intel_dp->output_reg) {
1931 case PCH_DP_B:
1932 trans_sel = TRANS_DP_PORT_SEL_B;
1933 break;
1934 case PCH_DP_C:
1935 trans_sel = TRANS_DP_PORT_SEL_C;
1936 break;
1937 case PCH_DP_D:
1938 trans_sel = TRANS_DP_PORT_SEL_D;
1939 break;
1940 default:
1941 return true;
1942 }
1943
055e393f 1944 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1945 trans_dp = I915_READ(TRANS_DP_CTL(i));
1946 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1947 *pipe = i;
1948 return true;
1949 }
1950 }
19d8fe15 1951
4a0833ec
DV		 1952 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1953 intel_dp->output_reg);
1954 }
d240f20f 1955
19d8fe15
DV		 1956 return true;
1957}
d240f20f 1958
045ac3b5
JB		 1959static void intel_dp_get_config(struct intel_encoder *encoder,
1960 struct intel_crtc_config *pipe_config)
1961{
1962 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1963 u32 tmp, flags = 0;
63000ef6
XZ		 1964 struct drm_device *dev = encoder->base.dev;
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 enum port port = dp_to_dig_port(intel_dp)->port;
1967 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1968 int dotclock;
045ac3b5 1969
9ed109a7
DV		 1970 tmp = I915_READ(intel_dp->output_reg);
1971 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1972 pipe_config->has_audio = true;
1973
63000ef6 1974 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1975 if (tmp & DP_SYNC_HS_HIGH)
1976 flags |= DRM_MODE_FLAG_PHSYNC;
1977 else
1978 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1979
63000ef6
XZ		 1980 if (tmp & DP_SYNC_VS_HIGH)
1981 flags |= DRM_MODE_FLAG_PVSYNC;
1982 else
1983 flags |= DRM_MODE_FLAG_NVSYNC;
1984 } else {
1985 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1986 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1987 flags |= DRM_MODE_FLAG_PHSYNC;
1988 else
1989 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1990
63000ef6
XZ		 1991 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1992 flags |= DRM_MODE_FLAG_PVSYNC;
1993 else
1994 flags |= DRM_MODE_FLAG_NVSYNC;
1995 }
045ac3b5
JB		 1996
1997 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1998
8c875fca
VS		 1999 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2000 tmp & DP_COLOR_RANGE_16_235)
2001 pipe_config->limited_color_range = true;
2002
eb14cb74
VS		 2003 pipe_config->has_dp_encoder = true;
2004
2005 intel_dp_get_m_n(crtc, pipe_config);
2006
18442d08 2007 if (port == PORT_A) {
f1f644dc
JB		 2008 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2009 pipe_config->port_clock = 162000;
2010 else
2011 pipe_config->port_clock = 270000;
2012 }
18442d08
VS		 2013
2014 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2015 &pipe_config->dp_m_n);
2016
2017 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2018 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2019
241bfc38 2020 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2021
c6cd2ee2
JN		 2022 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2023 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2024 /*
2025 * This is a big fat ugly hack.
2026 *
2027 * Some machines in UEFI boot mode provide us a VBT that has 18
2028 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2029 * unknown we fail to light up. Yet the same BIOS boots up with
2030 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2031 * max, not what it tells us to use.
2032 *
2033 * Note: This will still be broken if the eDP panel is not lit
2034 * up by the BIOS, and thus we can't get the mode at module
2035 * load.
2036 */
2037 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2038 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2039 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2040 }
045ac3b5
JB		 2041}
2042
34eb7579 2043static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 2044{
34eb7579 2045 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 2046}
2047
2b28bb1b
RV		 2048static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2049{
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051
18b5992c 2052 if (!HAS_PSR(dev))
2b28bb1b
RV		 2053 return false;
2054
18b5992c 2055 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 2056}
2057
2058static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2059 struct edp_vsc_psr *vsc_psr)
2060{
2061 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2062 struct drm_device *dev = dig_port->base.base.dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2065 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2066 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2067 uint32_t *data = (uint32_t *) vsc_psr;
2068 unsigned int i;
2069
2070 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2071 the video DIP being updated before program video DIP data buffer
2072 registers for DIP being updated. */
2073 I915_WRITE(ctl_reg, 0);
2074 POSTING_READ(ctl_reg);
2075
2076 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2077 if (i < sizeof(struct edp_vsc_psr))
2078 I915_WRITE(data_reg + i, *data++);
2079 else
2080 I915_WRITE(data_reg + i, 0);
2081 }
2082
2083 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2084 POSTING_READ(ctl_reg);
2085}
2086
ba80f4d4 2087static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2088{
2b28bb1b
RV		 2089 struct edp_vsc_psr psr_vsc;
2090
2b28bb1b
RV		 2091 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2092 memset(&psr_vsc, 0, sizeof(psr_vsc));
2093 psr_vsc.sdp_header.HB0 = 0;
2094 psr_vsc.sdp_header.HB1 = 0x7;
2095 psr_vsc.sdp_header.HB2 = 0x2;
2096 psr_vsc.sdp_header.HB3 = 0x8;
2097 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2098}
2099
2100static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2101{
0e0ae652
RV		 2102 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2103 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2104 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2105 uint32_t aux_clock_divider;
2b28bb1b 2106 int precharge = 0x3;
0e0ae652 2107 bool only_standby = false;
5ca476f8
VS		 2108 static const uint8_t aux_msg[] = {
2109 [0] = DP_AUX_NATIVE_WRITE << 4,
2110 [1] = DP_SET_POWER >> 8,
2111 [2] = DP_SET_POWER & 0xff,
2112 [3] = 1 - 1,
2113 [4] = DP_SET_POWER_D0,
2114 };
2115 int i;
2116
2117 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2118
ec5b01dd
DL		 2119 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2120
0e0ae652
RV		 2121 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2122 only_standby = true;
2123
2b28bb1b 2124 /* Enable PSR in sink */
0e0ae652 2125 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2126 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2127 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2128 else
9d1a1031
JN		 2129 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2130 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2131
2132 /* Setup AUX registers */
5ca476f8
VS		 2133 for (i = 0; i < sizeof(aux_msg); i += 4)
2134 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2135 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2136
18b5992c 2137 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2138 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2139 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2140 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2141 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2142}
2143
2144static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2145{
0e0ae652
RV		 2146 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2147 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2148 struct drm_i915_private *dev_priv = dev->dev_private;
2149 uint32_t max_sleep_time = 0x1f;
2150 uint32_t idle_frames = 1;
2151 uint32_t val = 0x0;
ed8546ac 2152 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2153 bool only_standby = false;
2154
2155 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2156 only_standby = true;
2b28bb1b 2157
0e0ae652 2158 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2159 val |= EDP_PSR_LINK_STANDBY;
2160 val |= EDP_PSR_TP2_TP3_TIME_0us;
2161 val |= EDP_PSR_TP1_TIME_0us;
2162 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2163 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2164 } else
2165 val |= EDP_PSR_LINK_DISABLE;
2166
18b5992c 2167 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2168 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2169 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2170 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2171 EDP_PSR_ENABLE);
2172}
2173
3f51e471
RV		 2174static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2175{
2176 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2177 struct drm_device *dev = dig_port->base.base.dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct drm_crtc *crtc = dig_port->base.base.crtc;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2181
f0355c4a 2182 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2183 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2184 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2185
a031d709
RV		 2186 dev_priv->psr.source_ok = false;
2187
9ca15301 2188 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2189 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2190 return false;
2191 }
2192
d330a953 2193 if (!i915.enable_psr) {
105b7c11 2194 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2195 return false;
2196 }
2197
4c8c7000
RV		 2198 /* Below limitations aren't valid for Broadwell */
2199 if (IS_BROADWELL(dev))
2200 goto out;
2201
3f51e471
RV		 2202 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2203 S3D_ENABLE) {
2204 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2205 return false;
2206 }
2207
ca73b4f0 2208 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2209 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2210 return false;
2211 }
2212
4c8c7000 2213 out:
a031d709 2214 dev_priv->psr.source_ok = true;
3f51e471
RV		 2215 return true;
2216}
2217
3d739d92 2218static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2219{
7c8f8a70
RV		 2220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2221 struct drm_device *dev = intel_dig_port->base.base.dev;
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2223
3638379c
DV		 2224 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2225 WARN_ON(dev_priv->psr.active);
f0355c4a 2226 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2227
7ca5a41f 2228 /* Enable/Re-enable PSR on the host */
2b28bb1b 2229 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2230
7c8f8a70 2231 dev_priv->psr.active = true;
2b28bb1b
RV		 2232}
2233
3d739d92
RV		 2234void intel_edp_psr_enable(struct intel_dp *intel_dp)
2235{
2236 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2237 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2238
4704c573
RV		 2239 if (!HAS_PSR(dev)) {
2240 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2241 return;
2242 }
2243
34eb7579
RV		 2244 if (!is_edp_psr(intel_dp)) {
2245 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2246 return;
2247 }
2248
f0355c4a 2249 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2250 if (dev_priv->psr.enabled) {
2251 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2252 goto unlock;
109fc2ad
DV		 2253 }
2254
0aa48783
RV		 2255 if (!intel_edp_psr_match_conditions(intel_dp))
2256 goto unlock;
2257
9ca15301
DV		 2258 dev_priv->psr.busy_frontbuffer_bits = 0;
2259
ba80f4d4 2260 intel_edp_psr_setup_vsc(intel_dp);
16487254 2261
ba80f4d4
RV		 2262 /* Avoid continuous PSR exit by masking memup and hpd */
2263 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2264 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2265
7ca5a41f
RV		 2266 /* Enable PSR on the panel */
2267 intel_edp_psr_enable_sink(intel_dp);
2268
0aa48783
RV		 2269 dev_priv->psr.enabled = intel_dp;
2270unlock:
f0355c4a 2271 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2272}
2273
2b28bb1b
RV		 2274void intel_edp_psr_disable(struct intel_dp *intel_dp)
2275{
2276 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278
f0355c4a
DV		 2279 mutex_lock(&dev_priv->psr.lock);
2280 if (!dev_priv->psr.enabled) {
2281 mutex_unlock(&dev_priv->psr.lock);
2282 return;
2283 }
2284
3638379c
DV		 2285 if (dev_priv->psr.active) {
2286 I915_WRITE(EDP_PSR_CTL(dev),
2287 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2288
2289 /* Wait till PSR is idle */
2290 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2291 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2292 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2293
3638379c
DV		 2294 dev_priv->psr.active = false;
2295 } else {
2296 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2297 }
7c8f8a70 2298
2807cf69 2299 dev_priv->psr.enabled = NULL;
f0355c4a 2300 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2301
2302 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2303}
2304
f02a326e 2305static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2306{
2307 struct drm_i915_private *dev_priv =
2308 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2309 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2310
8d7f4fe9
RV		 2311 /* We have to make sure PSR is ready for re-enable
2312 * otherwise it keeps disabled until next full enable/disable cycle.
2313 * PSR might take some time to get fully disabled
2314 * and be ready for re-enable.
2315 */
2316 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2317 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2318 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2319 return;
2320 }
2321
f0355c4a
DV		 2322 mutex_lock(&dev_priv->psr.lock);
2323 intel_dp = dev_priv->psr.enabled;
2324
2807cf69 2325 if (!intel_dp)
f0355c4a 2326 goto unlock;
2807cf69 2327
9ca15301
DV		 2328 /*
2329 * The delayed work can race with an invalidate hence we need to
2330 * recheck. Since psr_flush first clears this and then reschedules we
2331 * won't ever miss a flush when bailing out here.
2332 */
2333 if (dev_priv->psr.busy_frontbuffer_bits)
2334 goto unlock;
2335
2336 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2337unlock:
2338 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2339}
2340
9ca15301 2341static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2342{
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344
3638379c
DV		 2345 if (dev_priv->psr.active) {
2346 u32 val = I915_READ(EDP_PSR_CTL(dev));
2347
2348 WARN_ON(!(val & EDP_PSR_ENABLE));
2349
2350 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2351
2352 dev_priv->psr.active = false;
2353 }
7c8f8a70 2354
9ca15301
DV		 2355}
2356
2357void intel_edp_psr_invalidate(struct drm_device *dev,
2358 unsigned frontbuffer_bits)
2359{
2360 struct drm_i915_private *dev_priv = dev->dev_private;
2361 struct drm_crtc *crtc;
2362 enum pipe pipe;
2363
9ca15301
DV		 2364 mutex_lock(&dev_priv->psr.lock);
2365 if (!dev_priv->psr.enabled) {
2366 mutex_unlock(&dev_priv->psr.lock);
2367 return;
2368 }
2369
2370 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2371 pipe = to_intel_crtc(crtc)->pipe;
2372
2373 intel_edp_psr_do_exit(dev);
2374
2375 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2376
2377 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2378 mutex_unlock(&dev_priv->psr.lock);
2379}
2380
2381void intel_edp_psr_flush(struct drm_device *dev,
2382 unsigned frontbuffer_bits)
2383{
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 struct drm_crtc *crtc;
2386 enum pipe pipe;
2387
9ca15301
DV		 2388 mutex_lock(&dev_priv->psr.lock);
2389 if (!dev_priv->psr.enabled) {
2390 mutex_unlock(&dev_priv->psr.lock);
2391 return;
2392 }
2393
2394 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2395 pipe = to_intel_crtc(crtc)->pipe;
2396 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2397
2398 /*
2399 * On Haswell sprite plane updates don't result in a psr invalidating
2400 * signal in the hardware. Which means we need to manually fake this in
2401 * software for all flushes, not just when we've seen a preceding
2402 * invalidation through frontbuffer rendering.
2403 */
2404 if (IS_HASWELL(dev) &&
2405 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2406 intel_edp_psr_do_exit(dev);
2407
2408 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2409 schedule_delayed_work(&dev_priv->psr.work,
2410 msecs_to_jiffies(100));
f0355c4a 2411 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2412}
2413
2414void intel_edp_psr_init(struct drm_device *dev)
2415{
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417
7c8f8a70 2418 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2419 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2420}
2421
e8cb4558 2422static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2423{
e8cb4558 2424 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2425 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2426
2427 /* Make sure the panel is off before trying to change the mode. But also
2428 * ensure that we have vdd while we switch off the panel. */
24f3e092 2429 intel_edp_panel_vdd_on(intel_dp);
4be73780 2430 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2431 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2432 intel_edp_panel_off(intel_dp);
3739850b 2433
08aff3fe
VS		 2434 /* disable the port before the pipe on g4x */
2435 if (INTEL_INFO(dev)->gen < 5)
3739850b 2436 intel_dp_link_down(intel_dp);
d240f20f
JB		 2437}
2438
08aff3fe 2439static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2440{
2bd2ad64 2441 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2442 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2443
49277c31 2444 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2445 if (port == PORT_A)
2446 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2447}
2448
2449static void vlv_post_disable_dp(struct intel_encoder *encoder)
2450{
2451 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2452
2453 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2454}
2455
580d3811
VS		 2456static void chv_post_disable_dp(struct intel_encoder *encoder)
2457{
2458 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2459 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2460 struct drm_device *dev = encoder->base.dev;
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462 struct intel_crtc *intel_crtc =
2463 to_intel_crtc(encoder->base.crtc);
2464 enum dpio_channel ch = vlv_dport_to_channel(dport);
2465 enum pipe pipe = intel_crtc->pipe;
2466 u32 val;
2467
2468 intel_dp_link_down(intel_dp);
2469
2470 mutex_lock(&dev_priv->dpio_lock);
2471
2472 /* Propagate soft reset to data lane reset */
97fd4d5c 2473 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2474 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2475 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2476
97fd4d5c
VS		 2477 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2478 val |= CHV_PCS_REQ_SOFTRESET_EN;
2479 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2480
2481 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2482 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2483 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2484
2485 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2486 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2487 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2488
2489 mutex_unlock(&dev_priv->dpio_lock);
2490}
2491
7b13b58a
VS		 2492static void
2493_intel_dp_set_link_train(struct intel_dp *intel_dp,
2494 uint32_t *DP,
2495 uint8_t dp_train_pat)
2496{
2497 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2498 struct drm_device *dev = intel_dig_port->base.base.dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 enum port port = intel_dig_port->port;
2501
2502 if (HAS_DDI(dev)) {
2503 uint32_t temp = I915_READ(DP_TP_CTL(port));
2504
2505 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2506 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2507 else
2508 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2509
2510 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2511 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2512 case DP_TRAINING_PATTERN_DISABLE:
2513 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2514
2515 break;
2516 case DP_TRAINING_PATTERN_1:
2517 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2518 break;
2519 case DP_TRAINING_PATTERN_2:
2520 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2521 break;
2522 case DP_TRAINING_PATTERN_3:
2523 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2524 break;
2525 }
2526 I915_WRITE(DP_TP_CTL(port), temp);
2527
2528 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2529 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2530
2531 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2532 case DP_TRAINING_PATTERN_DISABLE:
2533 *DP |= DP_LINK_TRAIN_OFF_CPT;
2534 break;
2535 case DP_TRAINING_PATTERN_1:
2536 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2537 break;
2538 case DP_TRAINING_PATTERN_2:
2539 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2540 break;
2541 case DP_TRAINING_PATTERN_3:
2542 DRM_ERROR("DP training pattern 3 not supported\n");
2543 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2544 break;
2545 }
2546
2547 } else {
2548 if (IS_CHERRYVIEW(dev))
2549 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2550 else
2551 *DP &= ~DP_LINK_TRAIN_MASK;
2552
2553 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2554 case DP_TRAINING_PATTERN_DISABLE:
2555 *DP |= DP_LINK_TRAIN_OFF;
2556 break;
2557 case DP_TRAINING_PATTERN_1:
2558 *DP |= DP_LINK_TRAIN_PAT_1;
2559 break;
2560 case DP_TRAINING_PATTERN_2:
2561 *DP |= DP_LINK_TRAIN_PAT_2;
2562 break;
2563 case DP_TRAINING_PATTERN_3:
2564 if (IS_CHERRYVIEW(dev)) {
2565 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2566 } else {
2567 DRM_ERROR("DP training pattern 3 not supported\n");
2568 *DP |= DP_LINK_TRAIN_PAT_2;
2569 }
2570 break;
2571 }
2572 }
2573}
2574
2575static void intel_dp_enable_port(struct intel_dp *intel_dp)
2576{
2577 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579
7b13b58a
VS		 2580 /* enable with pattern 1 (as per spec) */
2581 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2582 DP_TRAINING_PATTERN_1);
2583
2584 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2585 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2586
2587 /*
2588 * Magic for VLV/CHV. We _must_ first set up the register
2589 * without actually enabling the port, and then do another
2590 * write to enable the port. Otherwise link training will
2591 * fail when the power sequencer is freshly used for this port.
2592 */
2593 intel_dp->DP |= DP_PORT_EN;
2594
2595 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2596 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2597}
2598
e8cb4558 2599static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2600{
e8cb4558
DV		 2601 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2602 struct drm_device *dev = encoder->base.dev;
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2605
0c33d8d7
DV		 2606 if (WARN_ON(dp_reg & DP_PORT_EN))
2607 return;
5d613501 2608
093e3f13
VS		 2609 pps_lock(intel_dp);
2610
2611 if (IS_VALLEYVIEW(dev))
2612 vlv_init_panel_power_sequencer(intel_dp);
2613
7b13b58a 2614 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2615
2616 edp_panel_vdd_on(intel_dp);
2617 edp_panel_on(intel_dp);
2618 edp_panel_vdd_off(intel_dp, true);
2619
2620 pps_unlock(intel_dp);
2621
61234fa5
VS		 2622 if (IS_VALLEYVIEW(dev))
2623 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2624
f01eca2e 2625 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2626 intel_dp_start_link_train(intel_dp);
33a34e4e 2627 intel_dp_complete_link_train(intel_dp);
3ab9c637 2628 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2629}
89b667f8 2630
ecff4f3b
JN		 2631static void g4x_enable_dp(struct intel_encoder *encoder)
2632{
828f5c6e
JN		 2633 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2634
ecff4f3b 2635 intel_enable_dp(encoder);
4be73780 2636 intel_edp_backlight_on(intel_dp);
ab1f90f9 2637}
89b667f8 2638
ab1f90f9
JN		 2639static void vlv_enable_dp(struct intel_encoder *encoder)
2640{
828f5c6e
JN		 2641 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2642
4be73780 2643 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2644}
2645
ecff4f3b 2646static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2647{
2648 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2649 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2650
8ac33ed3
DV		 2651 intel_dp_prepare(encoder);
2652
d41f1efb
DV		 2653 /* Only ilk+ has port A */
2654 if (dport->port == PORT_A) {
2655 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2656 ironlake_edp_pll_on(intel_dp);
d41f1efb 2657 }
ab1f90f9
JN		 2658}
2659
83b84597
VS		 2660static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2661{
2662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2663 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2664 enum pipe pipe = intel_dp->pps_pipe;
2665 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2666
2667 edp_panel_vdd_off_sync(intel_dp);
2668
2669 /*
2670 * VLV seems to get confused when multiple power seqeuencers
2671 * have the same port selected (even if only one has power/vdd
2672 * enabled). The failure manifests as vlv_wait_port_ready() failing
2673 * CHV on the other hand doesn't seem to mind having the same port
2674 * selected in multiple power seqeuencers, but let's clear the
2675 * port select always when logically disconnecting a power sequencer
2676 * from a port.
2677 */
2678 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2679 pipe_name(pipe), port_name(intel_dig_port->port));
2680 I915_WRITE(pp_on_reg, 0);
2681 POSTING_READ(pp_on_reg);
2682
2683 intel_dp->pps_pipe = INVALID_PIPE;
2684}
2685
a4a5d2f8
VS		 2686static void vlv_steal_power_sequencer(struct drm_device *dev,
2687 enum pipe pipe)
2688{
2689 struct drm_i915_private *dev_priv = dev->dev_private;
2690 struct intel_encoder *encoder;
2691
2692 lockdep_assert_held(&dev_priv->pps_mutex);
2693
2694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2695 base.head) {
2696 struct intel_dp *intel_dp;
773538e8 2697 enum port port;
a4a5d2f8
VS		 2698
2699 if (encoder->type != INTEL_OUTPUT_EDP)
2700 continue;
2701
2702 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2703 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2704
2705 if (intel_dp->pps_pipe != pipe)
2706 continue;
2707
2708 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2709 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2710
2711 /* make sure vdd is off before we steal it */
83b84597 2712 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2713 }
2714}
2715
2716static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2717{
2718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2719 struct intel_encoder *encoder = &intel_dig_port->base;
2720 struct drm_device *dev = encoder->base.dev;
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2723
2724 lockdep_assert_held(&dev_priv->pps_mutex);
2725
093e3f13
VS		 2726 if (!is_edp(intel_dp))
2727 return;
2728
a4a5d2f8
VS		 2729 if (intel_dp->pps_pipe == crtc->pipe)
2730 return;
2731
2732 /*
2733 * If another power sequencer was being used on this
2734 * port previously make sure to turn off vdd there while
2735 * we still have control of it.
2736 */
2737 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2738 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2739
2740 /*
2741 * We may be stealing the power
2742 * sequencer from another port.
2743 */
2744 vlv_steal_power_sequencer(dev, crtc->pipe);
2745
2746 /* now it's all ours */
2747 intel_dp->pps_pipe = crtc->pipe;
2748
2749 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2750 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2751
2752 /* init power sequencer on this pipe and port */
36b5f425
VS		 2753 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2754 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2755}
2756
ab1f90f9 2757static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2758{
2bd2ad64 2759 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2760 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2761 struct drm_device *dev = encoder->base.dev;
89b667f8 2762 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2763 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2764 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2765 int pipe = intel_crtc->pipe;
2766 u32 val;
a4fc5ed6 2767
ab1f90f9 2768 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2769
ab3c759a 2770 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2771 val = 0;
2772 if (pipe)
2773 val |= (1<<21);
2774 else
2775 val &= ~(1<<21);
2776 val |= 0x001000c4;
ab3c759a
CML		 2777 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2778 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2779 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2780
ab1f90f9
JN		 2781 mutex_unlock(&dev_priv->dpio_lock);
2782
2783 intel_enable_dp(encoder);
89b667f8
JB		 2784}
2785
ecff4f3b 2786static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2787{
2788 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2789 struct drm_device *dev = encoder->base.dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2791 struct intel_crtc *intel_crtc =
2792 to_intel_crtc(encoder->base.crtc);
e4607fcf 2793 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2794 int pipe = intel_crtc->pipe;
89b667f8 2795
8ac33ed3
DV		 2796 intel_dp_prepare(encoder);
2797
89b667f8 2798 /* Program Tx lane resets to default */
0980a60f 2799 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2800 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2801 DPIO_PCS_TX_LANE2_RESET |
2802 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2803 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2804 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2805 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2806 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2807 DPIO_PCS_CLK_SOFT_RESET);
2808
2809 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2810 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2811 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2812 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2813 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2814}
2815
e4a1d846
CML		 2816static void chv_pre_enable_dp(struct intel_encoder *encoder)
2817{
2818 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2819 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2820 struct drm_device *dev = encoder->base.dev;
2821 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2822 struct intel_crtc *intel_crtc =
2823 to_intel_crtc(encoder->base.crtc);
2824 enum dpio_channel ch = vlv_dport_to_channel(dport);
2825 int pipe = intel_crtc->pipe;
2826 int data, i;
949c1d43 2827 u32 val;
e4a1d846 2828
e4a1d846 2829 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2830
570e2a74
VS		 2831 /* allow hardware to manage TX FIFO reset source */
2832 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2833 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2834 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2835
2836 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2837 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2838 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2839
949c1d43 2840 /* Deassert soft data lane reset*/
97fd4d5c 2841 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2842 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2843 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2844
2845 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2846 val |= CHV_PCS_REQ_SOFTRESET_EN;
2847 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2848
2849 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2850 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2851 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2852
97fd4d5c 2853 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2854 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2855 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2856
2857 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2858 for (i = 0; i < 4; i++) {
2859 /* Set the latency optimal bit */
2860 data = (i == 1) ? 0x0 : 0x6;
2861 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2862 data << DPIO_FRC_LATENCY_SHFIT);
2863
2864 /* Set the upar bit */
2865 data = (i == 1) ? 0x0 : 0x1;
2866 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2867 data << DPIO_UPAR_SHIFT);
2868 }
2869
2870 /* Data lane stagger programming */
2871 /* FIXME: Fix up value only after power analysis */
2872
2873 mutex_unlock(&dev_priv->dpio_lock);
2874
e4a1d846 2875 intel_enable_dp(encoder);
e4a1d846
CML		 2876}
2877
9197c88b
VS		 2878static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2879{
2880 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2881 struct drm_device *dev = encoder->base.dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct intel_crtc *intel_crtc =
2884 to_intel_crtc(encoder->base.crtc);
2885 enum dpio_channel ch = vlv_dport_to_channel(dport);
2886 enum pipe pipe = intel_crtc->pipe;
2887 u32 val;
2888
625695f8
VS		 2889 intel_dp_prepare(encoder);
2890
9197c88b
VS		 2891 mutex_lock(&dev_priv->dpio_lock);
2892
b9e5ac3c
VS		 2893 /* program left/right clock distribution */
2894 if (pipe != PIPE_B) {
2895 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2896 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2897 if (ch == DPIO_CH0)
2898 val |= CHV_BUFLEFTENA1_FORCE;
2899 if (ch == DPIO_CH1)
2900 val |= CHV_BUFRIGHTENA1_FORCE;
2901 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2902 } else {
2903 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2904 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2905 if (ch == DPIO_CH0)
2906 val |= CHV_BUFLEFTENA2_FORCE;
2907 if (ch == DPIO_CH1)
2908 val |= CHV_BUFRIGHTENA2_FORCE;
2909 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2910 }
2911
9197c88b
VS		 2912 /* program clock channel usage */
2913 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2914 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2915 if (pipe != PIPE_B)
2916 val &= ~CHV_PCS_USEDCLKCHANNEL;
2917 else
2918 val |= CHV_PCS_USEDCLKCHANNEL;
2919 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2920
2921 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2922 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2923 if (pipe != PIPE_B)
2924 val &= ~CHV_PCS_USEDCLKCHANNEL;
2925 else
2926 val |= CHV_PCS_USEDCLKCHANNEL;
2927 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2928
2929 /*
2930 * This a a bit weird since generally CL
2931 * matches the pipe, but here we need to
2932 * pick the CL based on the port.
2933 */
2934 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2935 if (pipe != PIPE_B)
2936 val &= ~CHV_CMN_USEDCLKCHANNEL;
2937 else
2938 val |= CHV_CMN_USEDCLKCHANNEL;
2939 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2940
2941 mutex_unlock(&dev_priv->dpio_lock);
2942}
2943
a4fc5ed6 2944/*
df0c237d
JB		 2945 * Native read with retry for link status and receiver capability reads for
2946 * cases where the sink may still be asleep.
9d1a1031
JN		 2947 *
2948 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2949 * supposed to retry 3 times per the spec.
a4fc5ed6 2950 */
9d1a1031
JN		 2951static ssize_t
2952intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2953 void *buffer, size_t size)
a4fc5ed6 2954{
9d1a1031
JN		 2955 ssize_t ret;
2956 int i;
61da5fab 2957
61da5fab 2958 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2959 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2960 if (ret == size)
2961 return ret;
61da5fab
JB		 2962 msleep(1);
2963 }
a4fc5ed6 2964
9d1a1031 2965 return ret;
a4fc5ed6
KP		 2966}
2967
2968/*
2969 * Fetch AUX CH registers 0x202 - 0x207 which contain
2970 * link status information
2971 */
2972static bool
93f62dad 2973intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2974{
9d1a1031
JN		 2975 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2976 DP_LANE0_1_STATUS,
2977 link_status,
2978 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2979}
2980
1100244e 2981/* These are source-specific values. */
a4fc5ed6 2982static uint8_t
1a2eb460 2983intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2984{
30add22d 2985 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2986 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2987
5a9d1f1a
DL		 2988 if (INTEL_INFO(dev)->gen >= 9)
2989 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2990 else if (IS_VALLEYVIEW(dev))
bd60018a 2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2992 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2994 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2995 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2996 else
bd60018a 2997 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2998}
2999
3000static uint8_t
3001intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3002{
30add22d 3003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3004 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3005
5a9d1f1a
DL		 3006 if (INTEL_INFO(dev)->gen >= 9) {
3007 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3011 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3013 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3014 default:
3015 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3016 }
3017 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3018 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3026 default:
bd60018a 3027 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3028 }
e2fa6fba
P		 3029 } else if (IS_VALLEYVIEW(dev)) {
3030 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3038 default:
bd60018a 3039 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3040 }
bc7d38a4 3041 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3042 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3048 default:
bd60018a 3049 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3050 }
3051 } else {
3052 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3054 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3060 default:
bd60018a 3061 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3062 }
a4fc5ed6
KP		 3063 }
3064}
3065
e2fa6fba
P		 3066static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3067{
3068 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3071 struct intel_crtc *intel_crtc =
3072 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3073 unsigned long demph_reg_value, preemph_reg_value,
3074 uniqtranscale_reg_value;
3075 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3076 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3077 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3078
3079 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3080 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3081 preemph_reg_value = 0x0004000;
3082 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3084 demph_reg_value = 0x2B405555;
3085 uniqtranscale_reg_value = 0x552AB83A;
3086 break;
bd60018a 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3088 demph_reg_value = 0x2B404040;
3089 uniqtranscale_reg_value = 0x5548B83A;
3090 break;
bd60018a 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3092 demph_reg_value = 0x2B245555;
3093 uniqtranscale_reg_value = 0x5560B83A;
3094 break;
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3096 demph_reg_value = 0x2B405555;
3097 uniqtranscale_reg_value = 0x5598DA3A;
3098 break;
3099 default:
3100 return 0;
3101 }
3102 break;
bd60018a 3103 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3104 preemph_reg_value = 0x0002000;
3105 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3107 demph_reg_value = 0x2B404040;
3108 uniqtranscale_reg_value = 0x5552B83A;
3109 break;
bd60018a 3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3111 demph_reg_value = 0x2B404848;
3112 uniqtranscale_reg_value = 0x5580B83A;
3113 break;
bd60018a 3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3115 demph_reg_value = 0x2B404040;
3116 uniqtranscale_reg_value = 0x55ADDA3A;
3117 break;
3118 default:
3119 return 0;
3120 }
3121 break;
bd60018a 3122 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3123 preemph_reg_value = 0x0000000;
3124 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3126 demph_reg_value = 0x2B305555;
3127 uniqtranscale_reg_value = 0x5570B83A;
3128 break;
bd60018a 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3130 demph_reg_value = 0x2B2B4040;
3131 uniqtranscale_reg_value = 0x55ADDA3A;
3132 break;
3133 default:
3134 return 0;
3135 }
3136 break;
bd60018a 3137 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3138 preemph_reg_value = 0x0006000;
3139 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3141 demph_reg_value = 0x1B405555;
3142 uniqtranscale_reg_value = 0x55ADDA3A;
3143 break;
3144 default:
3145 return 0;
3146 }
3147 break;
3148 default:
3149 return 0;
3150 }
3151
0980a60f 3152 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3153 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3154 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3155 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3156 uniqtranscale_reg_value);
ab3c759a
CML		 3157 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3158 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3159 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3160 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3161 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3162
3163 return 0;
3164}
3165
e4a1d846
CML		 3166static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3167{
3168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3171 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3172 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3173 uint8_t train_set = intel_dp->train_set[0];
3174 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3175 enum pipe pipe = intel_crtc->pipe;
3176 int i;
e4a1d846
CML		 3177
3178 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3179 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3182 deemph_reg_value = 128;
3183 margin_reg_value = 52;
3184 break;
bd60018a 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3186 deemph_reg_value = 128;
3187 margin_reg_value = 77;
3188 break;
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3190 deemph_reg_value = 128;
3191 margin_reg_value = 102;
3192 break;
bd60018a 3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3194 deemph_reg_value = 128;
3195 margin_reg_value = 154;
3196 /* FIXME extra to set for 1200 */
3197 break;
3198 default:
3199 return 0;
3200 }
3201 break;
bd60018a 3202 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3203 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3205 deemph_reg_value = 85;
3206 margin_reg_value = 78;
3207 break;
bd60018a 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3209 deemph_reg_value = 85;
3210 margin_reg_value = 116;
3211 break;
bd60018a 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3213 deemph_reg_value = 85;
3214 margin_reg_value = 154;
3215 break;
3216 default:
3217 return 0;
3218 }
3219 break;
bd60018a 3220 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3221 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3223 deemph_reg_value = 64;
3224 margin_reg_value = 104;
3225 break;
bd60018a 3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3227 deemph_reg_value = 64;
3228 margin_reg_value = 154;
3229 break;
3230 default:
3231 return 0;
3232 }
3233 break;
bd60018a 3234 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3235 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3237 deemph_reg_value = 43;
3238 margin_reg_value = 154;
3239 break;
3240 default:
3241 return 0;
3242 }
3243 break;
3244 default:
3245 return 0;
3246 }
3247
3248 mutex_lock(&dev_priv->dpio_lock);
3249
3250 /* Clear calc init */
1966e59e
VS		 3251 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3252 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3253 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3254 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3255 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3256
3257 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3258 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3259 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3260 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3261 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3262
a02ef3c7
VS		 3263 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3264 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3265 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3266 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3267
3268 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3269 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3270 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3271 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3272
e4a1d846 3273 /* Program swing deemph */
f72df8db
VS		 3274 for (i = 0; i < 4; i++) {
3275 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3276 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3277 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3278 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3279 }
e4a1d846
CML		 3280
3281 /* Program swing margin */
f72df8db
VS		 3282 for (i = 0; i < 4; i++) {
3283 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3284 val &= ~DPIO_SWING_MARGIN000_MASK;
3285 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3286 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3287 }
e4a1d846
CML		 3288
3289 /* Disable unique transition scale */
f72df8db
VS		 3290 for (i = 0; i < 4; i++) {
3291 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3292 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3293 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3294 }
e4a1d846
CML		 3295
3296 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3297 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3298 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3299 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3300
3301 /*
3302 * The document said it needs to set bit 27 for ch0 and bit 26
3303 * for ch1. Might be a typo in the doc.
3304 * For now, for this unique transition scale selection, set bit
3305 * 27 for ch0 and ch1.
3306 */
f72df8db
VS		 3307 for (i = 0; i < 4; i++) {
3308 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3309 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3310 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3311 }
e4a1d846 3312
f72df8db
VS		 3313 for (i = 0; i < 4; i++) {
3314 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3315 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3316 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3317 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3318 }
e4a1d846
CML		 3319 }
3320
3321 /* Start swing calculation */
1966e59e
VS		 3322 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3323 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3324 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3325
3326 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3327 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3328 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3329
3330 /* LRC Bypass */
3331 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3332 val |= DPIO_LRC_BYPASS;
3333 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3334
3335 mutex_unlock(&dev_priv->dpio_lock);
3336
3337 return 0;
3338}
3339
a4fc5ed6 3340static void
0301b3ac
JN		 3341intel_get_adjust_train(struct intel_dp *intel_dp,
3342 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3343{
3344 uint8_t v = 0;
3345 uint8_t p = 0;
3346 int lane;
1a2eb460
KP		 3347 uint8_t voltage_max;
3348 uint8_t preemph_max;
a4fc5ed6 3349
33a34e4e 3350 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3351 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3352 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3353
3354 if (this_v > v)
3355 v = this_v;
3356 if (this_p > p)
3357 p = this_p;
3358 }
3359
1a2eb460 3360 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3361 if (v >= voltage_max)
3362 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3363
1a2eb460
KP		 3364 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3365 if (p >= preemph_max)
3366 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3367
3368 for (lane = 0; lane < 4; lane++)
33a34e4e 3369 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3370}
3371
3372static uint32_t
f0a3424e 3373intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3374{
3cf2efb1 3375 uint32_t signal_levels = 0;
a4fc5ed6 3376
3cf2efb1 3377 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3378 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3379 default:
3380 signal_levels |= DP_VOLTAGE_0_4;
3381 break;
bd60018a 3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3383 signal_levels |= DP_VOLTAGE_0_6;
3384 break;
bd60018a 3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3386 signal_levels |= DP_VOLTAGE_0_8;
3387 break;
bd60018a 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3389 signal_levels |= DP_VOLTAGE_1_2;
3390 break;
3391 }
3cf2efb1 3392 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3393 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3394 default:
3395 signal_levels |= DP_PRE_EMPHASIS_0;
3396 break;
bd60018a 3397 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3398 signal_levels |= DP_PRE_EMPHASIS_3_5;
3399 break;
bd60018a 3400 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3401 signal_levels |= DP_PRE_EMPHASIS_6;
3402 break;
bd60018a 3403 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3404 signal_levels |= DP_PRE_EMPHASIS_9_5;
3405 break;
3406 }
3407 return signal_levels;
3408}
3409
e3421a18
ZW		 3410/* Gen6's DP voltage swing and pre-emphasis control */
3411static uint32_t
3412intel_gen6_edp_signal_levels(uint8_t train_set)
3413{
3c5a62b5
YL		 3414 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3415 DP_TRAIN_PRE_EMPHASIS_MASK);
3416 switch (signal_levels) {
bd60018a
SJ		 3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3419 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3421 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3424 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3427 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3430 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3431 default:
3c5a62b5
YL		 3432 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3433 "0x%x\n", signal_levels);
3434 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3435 }
3436}
3437
1a2eb460
KP		 3438/* Gen7's DP voltage swing and pre-emphasis control */
3439static uint32_t
3440intel_gen7_edp_signal_levels(uint8_t train_set)
3441{
3442 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3443 DP_TRAIN_PRE_EMPHASIS_MASK);
3444 switch (signal_levels) {
bd60018a 3445 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3446 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3448 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3450 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3451
bd60018a 3452 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3453 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3455 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3456
bd60018a 3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3458 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3460 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3461
3462 default:
3463 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3464 "0x%x\n", signal_levels);
3465 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3466 }
3467}
3468
d6c0d722
PZ		 3469/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3470static uint32_t
f0a3424e 3471intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3472{
d6c0d722
PZ		 3473 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3474 DP_TRAIN_PRE_EMPHASIS_MASK);
3475 switch (signal_levels) {
bd60018a 3476 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3477 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3478 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3479 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3481 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3482 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3483 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3484
bd60018a 3485 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3486 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3488 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3490 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3491
bd60018a 3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3493 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3494 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3495 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3496 default:
3497 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3498 "0x%x\n", signal_levels);
c5fe6a06 3499 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3500 }
a4fc5ed6
KP		 3501}
3502
f0a3424e
PZ		 3503/* Properly updates "DP" with the correct signal levels. */
3504static void
3505intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3506{
3507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3508 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3509 struct drm_device *dev = intel_dig_port->base.base.dev;
3510 uint32_t signal_levels, mask;
3511 uint8_t train_set = intel_dp->train_set[0];
3512
5a9d1f1a 3513 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3514 signal_levels = intel_hsw_signal_levels(train_set);
3515 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3516 } else if (IS_CHERRYVIEW(dev)) {
3517 signal_levels = intel_chv_signal_levels(intel_dp);
3518 mask = 0;
e2fa6fba
P		 3519 } else if (IS_VALLEYVIEW(dev)) {
3520 signal_levels = intel_vlv_signal_levels(intel_dp);
3521 mask = 0;
bc7d38a4 3522 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3523 signal_levels = intel_gen7_edp_signal_levels(train_set);
3524 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3525 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3526 signal_levels = intel_gen6_edp_signal_levels(train_set);
3527 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3528 } else {
3529 signal_levels = intel_gen4_signal_levels(train_set);
3530 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3531 }
3532
3533 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3534
3535 *DP = (*DP & ~mask) | signal_levels;
3536}
3537
a4fc5ed6 3538static bool
ea5b213a 3539intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3540 uint32_t *DP,
58e10eb9 3541 uint8_t dp_train_pat)
a4fc5ed6 3542{
174edf1f
PZ		 3543 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3544 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3545 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3546 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3547 int ret, len;
a4fc5ed6 3548
7b13b58a 3549 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3550
70aff66c 3551 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3552 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3553
2cdfe6c8
JN		 3554 buf[0] = dp_train_pat;
3555 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3556 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3557 /* don't write DP_TRAINING_LANEx_SET on disable */
3558 len = 1;
3559 } else {
3560 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3561 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3562 len = intel_dp->lane_count + 1;
47ea7542 3563 }
a4fc5ed6 3564
9d1a1031
JN		 3565 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3566 buf, len);
2cdfe6c8
JN		 3567
3568 return ret == len;
a4fc5ed6
KP		 3569}
3570
70aff66c
JN		 3571static bool
3572intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3573 uint8_t dp_train_pat)
3574{
953d22e8 3575 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3576 intel_dp_set_signal_levels(intel_dp, DP);
3577 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3578}
3579
3580static bool
3581intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3582 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3583{
3584 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3585 struct drm_device *dev = intel_dig_port->base.base.dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 int ret;
3588
3589 intel_get_adjust_train(intel_dp, link_status);
3590 intel_dp_set_signal_levels(intel_dp, DP);
3591
3592 I915_WRITE(intel_dp->output_reg, *DP);
3593 POSTING_READ(intel_dp->output_reg);
3594
9d1a1031
JN		 3595 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3596 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3597
3598 return ret == intel_dp->lane_count;
3599}
3600
3ab9c637
ID		 3601static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3602{
3603 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3604 struct drm_device *dev = intel_dig_port->base.base.dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 enum port port = intel_dig_port->port;
3607 uint32_t val;
3608
3609 if (!HAS_DDI(dev))
3610 return;
3611
3612 val = I915_READ(DP_TP_CTL(port));
3613 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3614 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3615 I915_WRITE(DP_TP_CTL(port), val);
3616
3617 /*
3618 * On PORT_A we can have only eDP in SST mode. There the only reason
3619 * we need to set idle transmission mode is to work around a HW issue
3620 * where we enable the pipe while not in idle link-training mode.
3621 * In this case there is requirement to wait for a minimum number of
3622 * idle patterns to be sent.
3623 */
3624 if (port == PORT_A)
3625 return;
3626
3627 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3628 1))
3629 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3630}
3631
33a34e4e 3632/* Enable corresponding port and start training pattern 1 */
c19b0669 3633void
33a34e4e 3634intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3635{
da63a9f2 3636 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3637 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3638 int i;
3639 uint8_t voltage;
cdb0e95b 3640 int voltage_tries, loop_tries;
ea5b213a 3641 uint32_t DP = intel_dp->DP;
6aba5b6c 3642 uint8_t link_config[2];
a4fc5ed6 3643
affa9354 3644 if (HAS_DDI(dev))
c19b0669
PZ		 3645 intel_ddi_prepare_link_retrain(encoder);
3646
3cf2efb1 3647 /* Write the link configuration data */
6aba5b6c
JN		 3648 link_config[0] = intel_dp->link_bw;
3649 link_config[1] = intel_dp->lane_count;
3650 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3651 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3652 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3653
3654 link_config[0] = 0;
3655 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3656 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3657
3658 DP |= DP_PORT_EN;
1a2eb460 3659
70aff66c
JN		 3660 /* clock recovery */
3661 if (!intel_dp_reset_link_train(intel_dp, &DP,
3662 DP_TRAINING_PATTERN_1 |
3663 DP_LINK_SCRAMBLING_DISABLE)) {
3664 DRM_ERROR("failed to enable link training\n");
3665 return;
3666 }
3667
a4fc5ed6 3668 voltage = 0xff;
cdb0e95b
KP		 3669 voltage_tries = 0;
3670 loop_tries = 0;
a4fc5ed6 3671 for (;;) {
70aff66c 3672 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3673
a7c9655f 3674 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3675 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3676 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3677 break;
93f62dad 3678 }
a4fc5ed6 3679
01916270 3680 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3681 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3682 break;
3683 }
3684
3685 /* Check to see if we've tried the max voltage */
3686 for (i = 0; i < intel_dp->lane_count; i++)
3687 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3688 break;
3b4f819d 3689 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3690 ++loop_tries;
3691 if (loop_tries == 5) {
3def84b3 3692 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3693 break;
3694 }
70aff66c
JN		 3695 intel_dp_reset_link_train(intel_dp, &DP,
3696 DP_TRAINING_PATTERN_1 |
3697 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3698 voltage_tries = 0;
3699 continue;
3700 }
a4fc5ed6 3701
3cf2efb1 3702 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3703 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3704 ++voltage_tries;
b06fbda3 3705 if (voltage_tries == 5) {
3def84b3 3706 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3707 break;
3708 }
3709 } else
3710 voltage_tries = 0;
3711 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3712
70aff66c
JN		 3713 /* Update training set as requested by target */
3714 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3715 DRM_ERROR("failed to update link training\n");
3716 break;
3717 }
a4fc5ed6
KP		 3718 }
3719
33a34e4e
JB		 3720 intel_dp->DP = DP;
3721}
3722
c19b0669 3723void
33a34e4e
JB		 3724intel_dp_complete_link_train(struct intel_dp *intel_dp)
3725{
33a34e4e 3726 bool channel_eq = false;
37f80975 3727 int tries, cr_tries;
33a34e4e 3728 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3729 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3730
3731 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3732 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3733 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3734
a4fc5ed6 3735 /* channel equalization */
70aff66c 3736 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3737 training_pattern |
70aff66c
JN		 3738 DP_LINK_SCRAMBLING_DISABLE)) {
3739 DRM_ERROR("failed to start channel equalization\n");
3740 return;
3741 }
3742
a4fc5ed6 3743 tries = 0;
37f80975 3744 cr_tries = 0;
a4fc5ed6
KP		 3745 channel_eq = false;
3746 for (;;) {
70aff66c 3747 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3748
37f80975
JB		 3749 if (cr_tries > 5) {
3750 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3751 break;
3752 }
3753
a7c9655f 3754 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3755 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3756 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3757 break;
70aff66c 3758 }
a4fc5ed6 3759
37f80975 3760 /* Make sure clock is still ok */
01916270 3761 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3762 intel_dp_start_link_train(intel_dp);
70aff66c 3763 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3764 training_pattern |
70aff66c 3765 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3766 cr_tries++;
3767 continue;
3768 }
3769
1ffdff13 3770 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3771 channel_eq = true;
3772 break;
3773 }
a4fc5ed6 3774
37f80975
JB		 3775 /* Try 5 times, then try clock recovery if that fails */
3776 if (tries > 5) {
3777 intel_dp_link_down(intel_dp);
3778 intel_dp_start_link_train(intel_dp);
70aff66c 3779 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3780 training_pattern |
70aff66c 3781 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3782 tries = 0;
3783 cr_tries++;
3784 continue;
3785 }
a4fc5ed6 3786
70aff66c
JN		 3787 /* Update training set as requested by target */
3788 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3789 DRM_ERROR("failed to update link training\n");
3790 break;
3791 }
3cf2efb1 3792 ++tries;
869184a6 3793 }
3cf2efb1 3794
3ab9c637
ID		 3795 intel_dp_set_idle_link_train(intel_dp);
3796
3797 intel_dp->DP = DP;
3798
d6c0d722 3799 if (channel_eq)
07f42258 3800 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3801
3ab9c637
ID		 3802}
3803
3804void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3805{
70aff66c 3806 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3807 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3808}
3809
3810static void
ea5b213a 3811intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3812{
da63a9f2 3813 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3814 enum port port = intel_dig_port->port;
da63a9f2 3815 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3816 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3817 struct intel_crtc *intel_crtc =
3818 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3819 uint32_t DP = intel_dp->DP;
a4fc5ed6 3820
bc76e320 3821 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3822 return;
3823
0c33d8d7 3824 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3825 return;
3826
28c97730 3827 DRM_DEBUG_KMS("\n");
32f9d658 3828
bc7d38a4 3829 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3830 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3831 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3832 } else {
aad3d14d
VS		 3833 if (IS_CHERRYVIEW(dev))
3834 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3835 else
3836 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3837 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3838 }
fe255d00 3839 POSTING_READ(intel_dp->output_reg);
5eb08b69 3840
493a7081 3841 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3842 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3843 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3844
5bddd17f
EA		 3845 /* Hardware workaround: leaving our transcoder select
3846 * set to transcoder B while it's off will prevent the
3847 * corresponding HDMI output on transcoder A.
3848 *
3849 * Combine this with another hardware workaround:
3850 * transcoder select bit can only be cleared while the
3851 * port is enabled.
3852 */
3853 DP &= ~DP_PIPEB_SELECT;
3854 I915_WRITE(intel_dp->output_reg, DP);
3855
3856 /* Changes to enable or select take place the vblank
3857 * after being written.
3858 */
ff50afe9
DV		 3859 if (WARN_ON(crtc == NULL)) {
3860 /* We should never try to disable a port without a crtc
3861 * attached. For paranoia keep the code around for a
3862 * bit. */
31acbcc4
CW		 3863 POSTING_READ(intel_dp->output_reg);
3864 msleep(50);
3865 } else
ab527efc 3866 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3867 }
3868
832afda6 3869 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3870 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3871 POSTING_READ(intel_dp->output_reg);
f01eca2e 3872 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3873}
3874
26d61aad
KP		 3875static bool
3876intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3877{
a031d709
RV		 3878 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3879 struct drm_device *dev = dig_port->base.base.dev;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881
9d1a1031
JN		 3882 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3883 sizeof(intel_dp->dpcd)) < 0)
edb39244 3884 return false; /* aux transfer failed */
92fd8fd1 3885
a8e98153 3886 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3887
edb39244
AJ		 3888 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3889 return false; /* DPCD not present */
3890
2293bb5c
SK		 3891 /* Check if the panel supports PSR */
3892 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3893 if (is_edp(intel_dp)) {
9d1a1031
JN		 3894 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3895 intel_dp->psr_dpcd,
3896 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3897 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3898 dev_priv->psr.sink_support = true;
50003939 3899 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3900 }
50003939
JN		 3901 }
3902
06ea66b6
TP		 3903 /* Training Pattern 3 support */
3904 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3905 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3906 intel_dp->use_tps3 = true;
f8d8a672 3907 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3908 } else
3909 intel_dp->use_tps3 = false;
3910
edb39244
AJ		 3911 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3912 DP_DWN_STRM_PORT_PRESENT))
3913 return true; /* native DP sink */
3914
3915 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3916 return true; /* no per-port downstream info */
3917
9d1a1031
JN		 3918 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3919 intel_dp->downstream_ports,
3920 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3921 return false; /* downstream port status fetch failed */
3922
3923 return true;
92fd8fd1
KP		 3924}
3925
0d198328
AJ		 3926static void
3927intel_dp_probe_oui(struct intel_dp *intel_dp)
3928{
3929 u8 buf[3];
3930
3931 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3932 return;
3933
9d1a1031 3934 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3935 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3936 buf[0], buf[1], buf[2]);
3937
9d1a1031 3938 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3939 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3940 buf[0], buf[1], buf[2]);
3941}
3942
0e32b39c
DA		 3943static bool
3944intel_dp_probe_mst(struct intel_dp *intel_dp)
3945{
3946 u8 buf[1];
3947
3948 if (!intel_dp->can_mst)
3949 return false;
3950
3951 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3952 return false;
3953
0e32b39c
DA		 3954 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3955 if (buf[0] & DP_MST_CAP) {
3956 DRM_DEBUG_KMS("Sink is MST capable\n");
3957 intel_dp->is_mst = true;
3958 } else {
3959 DRM_DEBUG_KMS("Sink is not MST capable\n");
3960 intel_dp->is_mst = false;
3961 }
3962 }
0e32b39c
DA		 3963
3964 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3965 return intel_dp->is_mst;
3966}
3967
d2e216d0
RV		 3968int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3969{
3970 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3971 struct drm_device *dev = intel_dig_port->base.base.dev;
3972 struct intel_crtc *intel_crtc =
3973 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3974 u8 buf;
3975 int test_crc_count;
3976 int attempts = 6;
d2e216d0 3977
ad9dc91b 3978 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3979 return -EIO;
d2e216d0 3980
ad9dc91b 3981 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3982 return -ENOTTY;
3983
1dda5f93
RV		 3984 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3985 return -EIO;
3986
9d1a1031 3987 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3988 buf | DP_TEST_SINK_START) < 0)
bda0381e 3989 return -EIO;
d2e216d0 3990
1dda5f93 3991 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3992 return -EIO;
ad9dc91b 3993 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3994
ad9dc91b 3995 do {
1dda5f93
RV		 3996 if (drm_dp_dpcd_readb(&intel_dp->aux,
3997 DP_TEST_SINK_MISC, &buf) < 0)
3998 return -EIO;
ad9dc91b
RV		 3999 intel_wait_for_vblank(dev, intel_crtc->pipe);
4000 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4001
4002 if (attempts == 0) {
4003 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
4004 return -EIO;
4005 }
d2e216d0 4006
9d1a1031 4007 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 4008 return -EIO;
d2e216d0 4009
1dda5f93
RV		 4010 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4011 return -EIO;
4012 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4013 buf & ~DP_TEST_SINK_START) < 0)
4014 return -EIO;
ce31d9f4 4015
d2e216d0
RV		 4016 return 0;
4017}
4018
a60f0e38
JB		 4019static bool
4020intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4021{
9d1a1031
JN		 4022 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4023 DP_DEVICE_SERVICE_IRQ_VECTOR,
4024 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4025}
4026
0e32b39c
DA		 4027static bool
4028intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4029{
4030 int ret;
4031
4032 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4033 DP_SINK_COUNT_ESI,
4034 sink_irq_vector, 14);
4035 if (ret != 14)
4036 return false;
4037
4038 return true;
4039}
4040
a60f0e38
JB		 4041static void
4042intel_dp_handle_test_request(struct intel_dp *intel_dp)
4043{
4044 /* NAK by default */
9d1a1031 4045 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 4046}
4047
0e32b39c
DA		 4048static int
4049intel_dp_check_mst_status(struct intel_dp *intel_dp)
4050{
4051 bool bret;
4052
4053 if (intel_dp->is_mst) {
4054 u8 esi[16] = { 0 };
4055 int ret = 0;
4056 int retry;
4057 bool handled;
4058 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4059go_again:
4060 if (bret == true) {
4061
4062 /* check link status - esi[10] = 0x200c */
4063 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4064 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4065 intel_dp_start_link_train(intel_dp);
4066 intel_dp_complete_link_train(intel_dp);
4067 intel_dp_stop_link_train(intel_dp);
4068 }
4069
4070 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4071 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4072
4073 if (handled) {
4074 for (retry = 0; retry < 3; retry++) {
4075 int wret;
4076 wret = drm_dp_dpcd_write(&intel_dp->aux,
4077 DP_SINK_COUNT_ESI+1,
4078 &esi[1], 3);
4079 if (wret == 3) {
4080 break;
4081 }
4082 }
4083
4084 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4085 if (bret == true) {
4086 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4087 goto go_again;
4088 }
4089 } else
4090 ret = 0;
4091
4092 return ret;
4093 } else {
4094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4095 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4096 intel_dp->is_mst = false;
4097 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4098 /* send a hotplug event */
4099 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4100 }
4101 }
4102 return -EINVAL;
4103}
4104
a4fc5ed6
KP		 4105/*
4106 * According to DP spec
4107 * 5.1.2:
4108 * 1. Read DPCD
4109 * 2. Configure link according to Receiver Capabilities
4110 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4111 * 4. Check link status on receipt of hot-plug interrupt
4112 */
00c09d70 4113void
ea5b213a 4114intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4115{
5b215bcf 4116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4117 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4118 u8 sink_irq_vector;
93f62dad 4119 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4120
5b215bcf
DA		 4121 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4122
da63a9f2 4123 if (!intel_encoder->connectors_active)
d2b996ac 4124 return;
59cd09e1 4125
da63a9f2 4126 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4127 return;
4128
1a125d8a
ID		 4129 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4130 return;
4131
92fd8fd1 4132 /* Try to read receiver status if the link appears to be up */
93f62dad 4133 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4134 return;
4135 }
4136
92fd8fd1 4137 /* Now read the DPCD to see if it's actually running */
26d61aad 4138 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4139 return;
4140 }
4141
a60f0e38
JB		 4142 /* Try to read the source of the interrupt */
4143 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4144 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4145 /* Clear interrupt source */
9d1a1031
JN		 4146 drm_dp_dpcd_writeb(&intel_dp->aux,
4147 DP_DEVICE_SERVICE_IRQ_VECTOR,
4148 sink_irq_vector);
a60f0e38
JB		 4149
4150 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4151 intel_dp_handle_test_request(intel_dp);
4152 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4153 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4154 }
4155
1ffdff13 4156 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4157 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4158 intel_encoder->base.name);
33a34e4e
JB		 4159 intel_dp_start_link_train(intel_dp);
4160 intel_dp_complete_link_train(intel_dp);
3ab9c637 4161 intel_dp_stop_link_train(intel_dp);
33a34e4e 4162 }
a4fc5ed6 4163}
a4fc5ed6 4164
caf9ab24 4165/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4166static enum drm_connector_status
26d61aad 4167intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4168{
caf9ab24 4169 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4170 uint8_t type;
4171
4172 if (!intel_dp_get_dpcd(intel_dp))
4173 return connector_status_disconnected;
4174
4175 /* if there's no downstream port, we're done */
4176 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4177 return connector_status_connected;
caf9ab24
AJ		 4178
4179 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4180 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4181 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4182 uint8_t reg;
9d1a1031
JN		 4183
4184 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4185 &reg, 1) < 0)
caf9ab24 4186 return connector_status_unknown;
9d1a1031 4187
23235177
AJ		 4188 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4189 : connector_status_disconnected;
caf9ab24
AJ		 4190 }
4191
4192 /* If no HPD, poke DDC gently */
0b99836f 4193 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4194 return connector_status_connected;
caf9ab24
AJ		 4195
4196 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4197 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4198 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4199 if (type == DP_DS_PORT_TYPE_VGA ||
4200 type == DP_DS_PORT_TYPE_NON_EDID)
4201 return connector_status_unknown;
4202 } else {
4203 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4204 DP_DWN_STRM_PORT_TYPE_MASK;
4205 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4206 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4207 return connector_status_unknown;
4208 }
caf9ab24
AJ		 4209
4210 /* Anything else is out of spec, warn and ignore */
4211 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4212 return connector_status_disconnected;
71ba9000
AJ		 4213}
4214
d410b56d
CW		 4215static enum drm_connector_status
4216edp_detect(struct intel_dp *intel_dp)
4217{
4218 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4219 enum drm_connector_status status;
4220
4221 status = intel_panel_detect(dev);
4222 if (status == connector_status_unknown)
4223 status = connector_status_connected;
4224
4225 return status;
4226}
4227
5eb08b69 4228static enum drm_connector_status
a9756bb5 4229ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4230{
30add22d 4231 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4232 struct drm_i915_private *dev_priv = dev->dev_private;
4233 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4234
1b469639
DL		 4235 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4236 return connector_status_disconnected;
4237
26d61aad 4238 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4239}
4240
2a592bec
DA		 4241static int g4x_digital_port_connected(struct drm_device *dev,
4242 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4243{
a4fc5ed6 4244 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4245 uint32_t bit;
5eb08b69 4246
232a6ee9
TP		 4247 if (IS_VALLEYVIEW(dev)) {
4248 switch (intel_dig_port->port) {
4249 case PORT_B:
4250 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4251 break;
4252 case PORT_C:
4253 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4254 break;
4255 case PORT_D:
4256 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4257 break;
4258 default:
2a592bec 4259 return -EINVAL;
232a6ee9
TP		 4260 }
4261 } else {
4262 switch (intel_dig_port->port) {
4263 case PORT_B:
4264 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4265 break;
4266 case PORT_C:
4267 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4268 break;
4269 case PORT_D:
4270 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4271 break;
4272 default:
2a592bec 4273 return -EINVAL;
232a6ee9 4274 }
a4fc5ed6
KP		 4275 }
4276
10f76a38 4277 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4278 return 0;
4279 return 1;
4280}
4281
4282static enum drm_connector_status
4283g4x_dp_detect(struct intel_dp *intel_dp)
4284{
4285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4287 int ret;
4288
4289 /* Can't disconnect eDP, but you can close the lid... */
4290 if (is_edp(intel_dp)) {
4291 enum drm_connector_status status;
4292
4293 status = intel_panel_detect(dev);
4294 if (status == connector_status_unknown)
4295 status = connector_status_connected;
4296 return status;
4297 }
4298
4299 ret = g4x_digital_port_connected(dev, intel_dig_port);
4300 if (ret == -EINVAL)
4301 return connector_status_unknown;
4302 else if (ret == 0)
a4fc5ed6
KP		 4303 return connector_status_disconnected;
4304
26d61aad 4305 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4306}
4307
8c241fef 4308static struct edid *
beb60608 4309intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4310{
beb60608 4311 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4312
9cd300e0
JN		 4313 /* use cached edid if we have one */
4314 if (intel_connector->edid) {
9cd300e0
JN		 4315 /* invalid edid */
4316 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4317 return NULL;
4318
55e9edeb 4319 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4320 } else
4321 return drm_get_edid(&intel_connector->base,
4322 &intel_dp->aux.ddc);
4323}
8c241fef 4324
beb60608
CW		 4325static void
4326intel_dp_set_edid(struct intel_dp *intel_dp)
4327{
4328 struct intel_connector *intel_connector = intel_dp->attached_connector;
4329 struct edid *edid;
8c241fef 4330
beb60608
CW		 4331 edid = intel_dp_get_edid(intel_dp);
4332 intel_connector->detect_edid = edid;
4333
4334 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4335 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4336 else
4337 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4338}
4339
beb60608
CW		 4340static void
4341intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4342{
beb60608 4343 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4344
beb60608
CW		 4345 kfree(intel_connector->detect_edid);
4346 intel_connector->detect_edid = NULL;
9cd300e0 4347
beb60608
CW		 4348 intel_dp->has_audio = false;
4349}
d6f24d0f 4350
beb60608
CW		 4351static enum intel_display_power_domain
4352intel_dp_power_get(struct intel_dp *dp)
4353{
4354 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4355 enum intel_display_power_domain power_domain;
4356
4357 power_domain = intel_display_port_power_domain(encoder);
4358 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4359
4360 return power_domain;
4361}
d6f24d0f 4362
beb60608
CW		 4363static void
4364intel_dp_power_put(struct intel_dp *dp,
4365 enum intel_display_power_domain power_domain)
4366{
4367 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4368 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4369}
4370
a9756bb5
ZW		 4371static enum drm_connector_status
4372intel_dp_detect(struct drm_connector *connector, bool force)
4373{
4374 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4376 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4377 struct drm_device *dev = connector->dev;
a9756bb5 4378 enum drm_connector_status status;
671dedd2 4379 enum intel_display_power_domain power_domain;
0e32b39c 4380 bool ret;
a9756bb5 4381
164c8598 4382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4383 connector->base.id, connector->name);
beb60608 4384 intel_dp_unset_edid(intel_dp);
164c8598 4385
0e32b39c
DA		 4386 if (intel_dp->is_mst) {
4387 /* MST devices are disconnected from a monitor POV */
4388 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4389 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4390 return connector_status_disconnected;
0e32b39c
DA		 4391 }
4392
beb60608 4393 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4394
d410b56d
CW		 4395 /* Can't disconnect eDP, but you can close the lid... */
4396 if (is_edp(intel_dp))
4397 status = edp_detect(intel_dp);
4398 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4399 status = ironlake_dp_detect(intel_dp);
4400 else
4401 status = g4x_dp_detect(intel_dp);
4402 if (status != connector_status_connected)
c8c8fb33 4403 goto out;
a9756bb5 4404
0d198328
AJ		 4405 intel_dp_probe_oui(intel_dp);
4406
0e32b39c
DA		 4407 ret = intel_dp_probe_mst(intel_dp);
4408 if (ret) {
4409 /* if we are in MST mode then this connector
4410 won't appear connected or have anything with EDID on it */
4411 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4412 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4413 status = connector_status_disconnected;
4414 goto out;
4415 }
4416
beb60608 4417 intel_dp_set_edid(intel_dp);
a9756bb5 4418
d63885da
PZ		 4419 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4420 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4421 status = connector_status_connected;
4422
4423out:
beb60608 4424 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4425 return status;
a4fc5ed6
KP		 4426}
4427
beb60608
CW		 4428static void
4429intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4430{
df0e9248 4431 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4432 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4433 enum intel_display_power_domain power_domain;
a4fc5ed6 4434
beb60608
CW		 4435 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4436 connector->base.id, connector->name);
4437 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4438
beb60608
CW		 4439 if (connector->status != connector_status_connected)
4440 return;
671dedd2 4441
beb60608
CW		 4442 power_domain = intel_dp_power_get(intel_dp);
4443
4444 intel_dp_set_edid(intel_dp);
4445
4446 intel_dp_power_put(intel_dp, power_domain);
4447
4448 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4449 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4450}
4451
4452static int intel_dp_get_modes(struct drm_connector *connector)
4453{
4454 struct intel_connector *intel_connector = to_intel_connector(connector);
4455 struct edid *edid;
4456
4457 edid = intel_connector->detect_edid;
4458 if (edid) {
4459 int ret = intel_connector_update_modes(connector, edid);
4460 if (ret)
4461 return ret;
4462 }
32f9d658 4463
f8779fda 4464 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4465 if (is_edp(intel_attached_dp(connector)) &&
4466 intel_connector->panel.fixed_mode) {
f8779fda 4467 struct drm_display_mode *mode;
beb60608
CW		 4468
4469 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4470 intel_connector->panel.fixed_mode);
f8779fda 4471 if (mode) {
32f9d658
ZW		 4472 drm_mode_probed_add(connector, mode);
4473 return 1;
4474 }
4475 }
beb60608 4476
32f9d658 4477 return 0;
a4fc5ed6
KP		 4478}
4479
1aad7ac0
CW		 4480static bool
4481intel_dp_detect_audio(struct drm_connector *connector)
4482{
1aad7ac0 4483 bool has_audio = false;
beb60608 4484 struct edid *edid;
1aad7ac0 4485
beb60608
CW		 4486 edid = to_intel_connector(connector)->detect_edid;
4487 if (edid)
1aad7ac0 4488 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4489
1aad7ac0
CW		 4490 return has_audio;
4491}
4492
f684960e
CW		 4493static int
4494intel_dp_set_property(struct drm_connector *connector,
4495 struct drm_property *property,
4496 uint64_t val)
4497{
e953fd7b 4498 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4499 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4500 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4501 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4502 int ret;
4503
662595df 4504 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4505 if (ret)
4506 return ret;
4507
3f43c48d 4508 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4509 int i = val;
4510 bool has_audio;
4511
4512 if (i == intel_dp->force_audio)
f684960e
CW		 4513 return 0;
4514
1aad7ac0 4515 intel_dp->force_audio = i;
f684960e 4516
c3e5f67b 4517 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4518 has_audio = intel_dp_detect_audio(connector);
4519 else
c3e5f67b 4520 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4521
4522 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4523 return 0;
4524
1aad7ac0 4525 intel_dp->has_audio = has_audio;
f684960e
CW		 4526 goto done;
4527 }
4528
e953fd7b 4529 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4530 bool old_auto = intel_dp->color_range_auto;
4531 uint32_t old_range = intel_dp->color_range;
4532
55bc60db
VS		 4533 switch (val) {
4534 case INTEL_BROADCAST_RGB_AUTO:
4535 intel_dp->color_range_auto = true;
4536 break;
4537 case INTEL_BROADCAST_RGB_FULL:
4538 intel_dp->color_range_auto = false;
4539 intel_dp->color_range = 0;
4540 break;
4541 case INTEL_BROADCAST_RGB_LIMITED:
4542 intel_dp->color_range_auto = false;
4543 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4544 break;
4545 default:
4546 return -EINVAL;
4547 }
ae4edb80
DV		 4548
4549 if (old_auto == intel_dp->color_range_auto &&
4550 old_range == intel_dp->color_range)
4551 return 0;
4552
e953fd7b
CW		 4553 goto done;
4554 }
4555
53b41837
YN		 4556 if (is_edp(intel_dp) &&
4557 property == connector->dev->mode_config.scaling_mode_property) {
4558 if (val == DRM_MODE_SCALE_NONE) {
4559 DRM_DEBUG_KMS("no scaling not supported\n");
4560 return -EINVAL;
4561 }
4562
4563 if (intel_connector->panel.fitting_mode == val) {
4564 /* the eDP scaling property is not changed */
4565 return 0;
4566 }
4567 intel_connector->panel.fitting_mode = val;
4568
4569 goto done;
4570 }
4571
f684960e
CW		 4572 return -EINVAL;
4573
4574done:
c0c36b94
CW		 4575 if (intel_encoder->base.crtc)
4576 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4577
4578 return 0;
4579}
4580
a4fc5ed6 4581static void
73845adf 4582intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4583{
1d508706 4584 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4585
10e972d3 4586 kfree(intel_connector->detect_edid);
beb60608 4587
9cd300e0
JN		 4588 if (!IS_ERR_OR_NULL(intel_connector->edid))
4589 kfree(intel_connector->edid);
4590
acd8db10
PZ		 4591 /* Can't call is_edp() since the encoder may have been destroyed
4592 * already. */
4593 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4594 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4595
a4fc5ed6 4596 drm_connector_cleanup(connector);
55f78c43 4597 kfree(connector);
a4fc5ed6
KP		 4598}
4599
00c09d70 4600void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4601{
da63a9f2
PZ		 4602 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4603 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4604
4f71d0cb 4605 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4606 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4607 drm_encoder_cleanup(encoder);
bd943159
KP		 4608 if (is_edp(intel_dp)) {
4609 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4610 /*
4611 * vdd might still be enabled do to the delayed vdd off.
4612 * Make sure vdd is actually turned off here.
4613 */
773538e8 4614 pps_lock(intel_dp);
4be73780 4615 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4616 pps_unlock(intel_dp);
4617
01527b31
CT		 4618 if (intel_dp->edp_notifier.notifier_call) {
4619 unregister_reboot_notifier(&intel_dp->edp_notifier);
4620 intel_dp->edp_notifier.notifier_call = NULL;
4621 }
bd943159 4622 }
da63a9f2 4623 kfree(intel_dig_port);
24d05927
DV		 4624}
4625
07f9cd0b
ID		 4626static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4627{
4628 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4629
4630 if (!is_edp(intel_dp))
4631 return;
4632
951468f3
VS		 4633 /*
4634 * vdd might still be enabled do to the delayed vdd off.
4635 * Make sure vdd is actually turned off here.
4636 */
773538e8 4637 pps_lock(intel_dp);
07f9cd0b 4638 edp_panel_vdd_off_sync(intel_dp);
773538e8 4639 pps_unlock(intel_dp);
07f9cd0b
ID		 4640}
4641
6d93c0c4
ID		 4642static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4643{
4644 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4645}
4646
a4fc5ed6 4647static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4648 .dpms = intel_connector_dpms,
a4fc5ed6 4649 .detect = intel_dp_detect,
beb60608 4650 .force = intel_dp_force,
a4fc5ed6 4651 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4652 .set_property = intel_dp_set_property,
73845adf 4653 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4654};
4655
4656static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4657 .get_modes = intel_dp_get_modes,
4658 .mode_valid = intel_dp_mode_valid,
df0e9248 4659 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4660};
4661
a4fc5ed6 4662static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4663 .reset = intel_dp_encoder_reset,
24d05927 4664 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4665};
4666
0e32b39c 4667void
21d40d37 4668intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4669{
0e32b39c 4670 return;
c8110e52 4671}
6207937d 4672
13cf5504
DA		 4673bool
4674intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4675{
4676 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4677 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4678 struct drm_device *dev = intel_dig_port->base.base.dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4680 enum intel_display_power_domain power_domain;
4681 bool ret = true;
4682
0e32b39c
DA		 4683 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4684 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4685
26fbb774
VS		 4686 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4687 port_name(intel_dig_port->port),
0e32b39c 4688 long_hpd ? "long" : "short");
13cf5504 4689
1c767b33
ID		 4690 power_domain = intel_display_port_power_domain(intel_encoder);
4691 intel_display_power_get(dev_priv, power_domain);
4692
0e32b39c 4693 if (long_hpd) {
2a592bec
DA		 4694
4695 if (HAS_PCH_SPLIT(dev)) {
4696 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4697 goto mst_fail;
4698 } else {
4699 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4700 goto mst_fail;
4701 }
0e32b39c
DA		 4702
4703 if (!intel_dp_get_dpcd(intel_dp)) {
4704 goto mst_fail;
4705 }
4706
4707 intel_dp_probe_oui(intel_dp);
4708
4709 if (!intel_dp_probe_mst(intel_dp))
4710 goto mst_fail;
4711
4712 } else {
4713 if (intel_dp->is_mst) {
1c767b33 4714 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4715 goto mst_fail;
4716 }
4717
4718 if (!intel_dp->is_mst) {
4719 /*
4720 * we'll check the link status via the normal hot plug path later -
4721 * but for short hpds we should check it now
4722 */
5b215bcf 4723 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4724 intel_dp_check_link_status(intel_dp);
5b215bcf 4725 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4726 }
4727 }
1c767b33
ID		 4728 ret = false;
4729 goto put_power;
0e32b39c
DA		 4730mst_fail:
4731 /* if we were in MST mode, and device is not there get out of MST mode */
4732 if (intel_dp->is_mst) {
4733 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4734 intel_dp->is_mst = false;
4735 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4736 }
1c767b33
ID		 4737put_power:
4738 intel_display_power_put(dev_priv, power_domain);
4739
4740 return ret;
13cf5504
DA		 4741}
4742
e3421a18
ZW		 4743/* Return which DP Port should be selected for Transcoder DP control */
4744int
0206e353 4745intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4746{
4747 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4748 struct intel_encoder *intel_encoder;
4749 struct intel_dp *intel_dp;
e3421a18 4750
fa90ecef
PZ		 4751 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4752 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4753
fa90ecef
PZ		 4754 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4755 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4756 return intel_dp->output_reg;
e3421a18 4757 }
ea5b213a 4758
e3421a18
ZW		 4759 return -1;
4760}
4761
36e83a18 4762/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4763bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4764{
4765 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4766 union child_device_config *p_child;
36e83a18 4767 int i;
5d8a7752
VS		 4768 static const short port_mapping[] = {
4769 [PORT_B] = PORT_IDPB,
4770 [PORT_C] = PORT_IDPC,
4771 [PORT_D] = PORT_IDPD,
4772 };
36e83a18 4773
3b32a35b
VS		 4774 if (port == PORT_A)
4775 return true;
4776
41aa3448 4777 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4778 return false;
4779
41aa3448
RV		 4780 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4781 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4782
5d8a7752 4783 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4784 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4785 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4786 return true;
4787 }
4788 return false;
4789}
4790
0e32b39c 4791void
f684960e
CW		 4792intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4793{
53b41837
YN		 4794 struct intel_connector *intel_connector = to_intel_connector(connector);
4795
3f43c48d 4796 intel_attach_force_audio_property(connector);
e953fd7b 4797 intel_attach_broadcast_rgb_property(connector);
55bc60db 4798 intel_dp->color_range_auto = true;
53b41837
YN		 4799
4800 if (is_edp(intel_dp)) {
4801 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4802 drm_object_attach_property(
4803 &connector->base,
53b41837 4804 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4805 DRM_MODE_SCALE_ASPECT);
4806 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4807 }
f684960e
CW		 4808}
4809
dada1a9f
ID		 4810static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4811{
4812 intel_dp->last_power_cycle = jiffies;
4813 intel_dp->last_power_on = jiffies;
4814 intel_dp->last_backlight_off = jiffies;
4815}
4816
67a54566
DV		 4817static void
4818intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4819 struct intel_dp *intel_dp)
67a54566
DV		 4820{
4821 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4822 struct edp_power_seq cur, vbt, spec,
4823 *final = &intel_dp->pps_delays;
67a54566 4824 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4825 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4826
e39b999a
VS		 4827 lockdep_assert_held(&dev_priv->pps_mutex);
4828
81ddbc69
VS		 4829 /* already initialized? */
4830 if (final->t11_t12 != 0)
4831 return;
4832
453c5420 4833 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4834 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4835 pp_on_reg = PCH_PP_ON_DELAYS;
4836 pp_off_reg = PCH_PP_OFF_DELAYS;
4837 pp_div_reg = PCH_PP_DIVISOR;
4838 } else {
bf13e81b
JN		 4839 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4840
4841 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4842 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4843 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4844 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4845 }
67a54566
DV		 4846
4847 /* Workaround: Need to write PP_CONTROL with the unlock key as
4848 * the very first thing. */
453c5420 4849 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4850 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4851
453c5420
JB		 4852 pp_on = I915_READ(pp_on_reg);
4853 pp_off = I915_READ(pp_off_reg);
4854 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4855
4856 /* Pull timing values out of registers */
4857 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4858 PANEL_POWER_UP_DELAY_SHIFT;
4859
4860 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4861 PANEL_LIGHT_ON_DELAY_SHIFT;
4862
4863 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4864 PANEL_LIGHT_OFF_DELAY_SHIFT;
4865
4866 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4867 PANEL_POWER_DOWN_DELAY_SHIFT;
4868
4869 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4870 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4871
4872 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4873 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4874
41aa3448 4875 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4876
4877 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4878 * our hw here, which are all in 100usec. */
4879 spec.t1_t3 = 210 * 10;
4880 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4881 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4882 spec.t10 = 500 * 10;
4883 /* This one is special and actually in units of 100ms, but zero
4884 * based in the hw (so we need to add 100 ms). But the sw vbt
4885 * table multiplies it with 1000 to make it in units of 100usec,
4886 * too. */
4887 spec.t11_t12 = (510 + 100) * 10;
4888
4889 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4890 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4891
4892 /* Use the max of the register settings and vbt. If both are
4893 * unset, fall back to the spec limits. */
36b5f425 4894#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4895 spec.field : \
4896 max(cur.field, vbt.field))
4897 assign_final(t1_t3);
4898 assign_final(t8);
4899 assign_final(t9);
4900 assign_final(t10);
4901 assign_final(t11_t12);
4902#undef assign_final
4903
36b5f425 4904#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4905 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4906 intel_dp->backlight_on_delay = get_delay(t8);
4907 intel_dp->backlight_off_delay = get_delay(t9);
4908 intel_dp->panel_power_down_delay = get_delay(t10);
4909 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4910#undef get_delay
4911
f30d26e4
JN		 4912 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4913 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4914 intel_dp->panel_power_cycle_delay);
4915
4916 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4917 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4918}
4919
4920static void
4921intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4922 struct intel_dp *intel_dp)
f30d26e4
JN		 4923{
4924 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4925 u32 pp_on, pp_off, pp_div, port_sel = 0;
4926 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4927 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4928 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4929 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4930
e39b999a 4931 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4932
4933 if (HAS_PCH_SPLIT(dev)) {
4934 pp_on_reg = PCH_PP_ON_DELAYS;
4935 pp_off_reg = PCH_PP_OFF_DELAYS;
4936 pp_div_reg = PCH_PP_DIVISOR;
4937 } else {
bf13e81b
JN		 4938 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4939
4940 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4941 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4942 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4943 }
4944
b2f19d1a
PZ		 4945 /*
4946 * And finally store the new values in the power sequencer. The
4947 * backlight delays are set to 1 because we do manual waits on them. For
4948 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4949 * we'll end up waiting for the backlight off delay twice: once when we
4950 * do the manual sleep, and once when we disable the panel and wait for
4951 * the PP_STATUS bit to become zero.
4952 */
f30d26e4 4953 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4954 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4955 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4956 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4957 /* Compute the divisor for the pp clock, simply match the Bspec
4958 * formula. */
453c5420 4959 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4960 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4961 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4962
4963 /* Haswell doesn't have any port selection bits for the panel
4964 * power sequencer any more. */
bc7d38a4 4965 if (IS_VALLEYVIEW(dev)) {
ad933b56 4966 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4967 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4968 if (port == PORT_A)
a24c144c 4969 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4970 else
a24c144c 4971 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4972 }
4973
453c5420
JB		 4974 pp_on |= port_sel;
4975
4976 I915_WRITE(pp_on_reg, pp_on);
4977 I915_WRITE(pp_off_reg, pp_off);
4978 I915_WRITE(pp_div_reg, pp_div);
67a54566 4979
67a54566 4980 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4981 I915_READ(pp_on_reg),
4982 I915_READ(pp_off_reg),
4983 I915_READ(pp_div_reg));
f684960e
CW		 4984}
4985
439d7ac0
PB		 4986void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4987{
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_encoder *encoder;
4990 struct intel_dp *intel_dp = NULL;
4991 struct intel_crtc_config *config = NULL;
4992 struct intel_crtc *intel_crtc = NULL;
4993 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4994 u32 reg, val;
4995 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4996
4997 if (refresh_rate <= 0) {
4998 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4999 return;
5000 }
5001
5002 if (intel_connector == NULL) {
5003 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
5004 return;
5005 }
5006
1fcc9d1c
DV		 5007 /*
5008 * FIXME: This needs proper synchronization with psr state. But really
5009 * hard to tell without seeing the user of this function of this code.
5010 * Check locking and ordering once that lands.
5011 */
439d7ac0
PB		 5012 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
5013 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
5014 return;
5015 }
5016
5017 encoder = intel_attached_encoder(&intel_connector->base);
5018 intel_dp = enc_to_intel_dp(&encoder->base);
5019 intel_crtc = encoder->new_crtc;
5020
5021 if (!intel_crtc) {
5022 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5023 return;
5024 }
5025
5026 config = &intel_crtc->config;
5027
5028 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
5029 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5030 return;
5031 }
5032
5033 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
5034 index = DRRS_LOW_RR;
5035
5036 if (index == intel_dp->drrs_state.refresh_rate_type) {
5037 DRM_DEBUG_KMS(
5038 "DRRS requested for previously set RR...ignoring\n");
5039 return;
5040 }
5041
5042 if (!intel_crtc->active) {
5043 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5044 return;
5045 }
5046
5047 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
5048 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
5049 val = I915_READ(reg);
5050 if (index > DRRS_HIGH_RR) {
5051 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 5052 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 5053 } else {
5054 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5055 }
5056 I915_WRITE(reg, val);
5057 }
5058
5059 /*
5060 * mutex taken to ensure that there is no race between differnt
5061 * drrs calls trying to update refresh rate. This scenario may occur
5062 * in future when idleness detection based DRRS in kernel and
5063 * possible calls from user space to set differnt RR are made.
5064 */
5065
5066 mutex_lock(&intel_dp->drrs_state.mutex);
5067
5068 intel_dp->drrs_state.refresh_rate_type = index;
5069
5070 mutex_unlock(&intel_dp->drrs_state.mutex);
5071
5072 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5073}
5074
4f9db5b5
PB		 5075static struct drm_display_mode *
5076intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5077 struct intel_connector *intel_connector,
5078 struct drm_display_mode *fixed_mode)
5079{
5080 struct drm_connector *connector = &intel_connector->base;
5081 struct intel_dp *intel_dp = &intel_dig_port->dp;
5082 struct drm_device *dev = intel_dig_port->base.base.dev;
5083 struct drm_i915_private *dev_priv = dev->dev_private;
5084 struct drm_display_mode *downclock_mode = NULL;
5085
5086 if (INTEL_INFO(dev)->gen <= 6) {
5087 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5088 return NULL;
5089 }
5090
5091 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5092 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5093 return NULL;
5094 }
5095
5096 downclock_mode = intel_find_panel_downclock
5097 (dev, fixed_mode, connector);
5098
5099 if (!downclock_mode) {
4079b8d1 5100 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5101 return NULL;
5102 }
5103
439d7ac0
PB		 5104 dev_priv->drrs.connector = intel_connector;
5105
5106 mutex_init(&intel_dp->drrs_state.mutex);
5107
4f9db5b5
PB		 5108 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5109
5110 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5111 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5112 return downclock_mode;
5113}
5114
aba86890
ID		 5115void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5116{
5117 struct drm_device *dev = intel_encoder->base.dev;
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 struct intel_dp *intel_dp;
5120 enum intel_display_power_domain power_domain;
5121
5122 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5123 return;
5124
5125 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5126
5127 pps_lock(intel_dp);
5128
aba86890 5129 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5130 goto out;
aba86890
ID		 5131 /*
5132 * The VDD bit needs a power domain reference, so if the bit is
5133 * already enabled when we boot or resume, grab this reference and
5134 * schedule a vdd off, so we don't hold on to the reference
5135 * indefinitely.
5136 */
5137 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5138 power_domain = intel_display_port_power_domain(intel_encoder);
5139 intel_display_power_get(dev_priv, power_domain);
5140
5141 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5142 out:
773538e8 5143 pps_unlock(intel_dp);
aba86890
ID		 5144}
5145
ed92f0b2 5146static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5147 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5148{
5149 struct drm_connector *connector = &intel_connector->base;
5150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5151 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5152 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5153 struct drm_i915_private *dev_priv = dev->dev_private;
5154 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5155 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5156 bool has_dpcd;
5157 struct drm_display_mode *scan;
5158 struct edid *edid;
5159
4f9db5b5
PB		 5160 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5161
ed92f0b2
PZ		 5162 if (!is_edp(intel_dp))
5163 return true;
5164
aba86890 5165 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5166
ed92f0b2 5167 /* Cache DPCD and EDID for edp. */
ed92f0b2 5168 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5169
5170 if (has_dpcd) {
5171 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5172 dev_priv->no_aux_handshake =
5173 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5174 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5175 } else {
5176 /* if this fails, presume the device is a ghost */
5177 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5178 return false;
5179 }
5180
5181 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5182 pps_lock(intel_dp);
36b5f425 5183 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5184 pps_unlock(intel_dp);
ed92f0b2 5185
060c8778 5186 mutex_lock(&dev->mode_config.mutex);
0b99836f 5187 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5188 if (edid) {
5189 if (drm_add_edid_modes(connector, edid)) {
5190 drm_mode_connector_update_edid_property(connector,
5191 edid);
5192 drm_edid_to_eld(connector, edid);
5193 } else {
5194 kfree(edid);
5195 edid = ERR_PTR(-EINVAL);
5196 }
5197 } else {
5198 edid = ERR_PTR(-ENOENT);
5199 }
5200 intel_connector->edid = edid;
5201
5202 /* prefer fixed mode from EDID if available */
5203 list_for_each_entry(scan, &connector->probed_modes, head) {
5204 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5205 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5206 downclock_mode = intel_dp_drrs_init(
5207 intel_dig_port,
5208 intel_connector, fixed_mode);
ed92f0b2
PZ		 5209 break;
5210 }
5211 }
5212
5213 /* fallback to VBT if available for eDP */
5214 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5215 fixed_mode = drm_mode_duplicate(dev,
5216 dev_priv->vbt.lfp_lvds_vbt_mode);
5217 if (fixed_mode)
5218 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5219 }
060c8778 5220 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5221
01527b31
CT		 5222 if (IS_VALLEYVIEW(dev)) {
5223 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5224 register_reboot_notifier(&intel_dp->edp_notifier);
5225 }
5226
4f9db5b5 5227 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5228 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5229 intel_panel_setup_backlight(connector);
5230
5231 return true;
5232}
5233
16c25533 5234bool
f0fec3f2
PZ		 5235intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5236 struct intel_connector *intel_connector)
a4fc5ed6 5237{
f0fec3f2
PZ		 5238 struct drm_connector *connector = &intel_connector->base;
5239 struct intel_dp *intel_dp = &intel_dig_port->dp;
5240 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5241 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5242 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5243 enum port port = intel_dig_port->port;
0b99836f 5244 int type;
a4fc5ed6 5245
a4a5d2f8
VS		 5246 intel_dp->pps_pipe = INVALID_PIPE;
5247
ec5b01dd 5248 /* intel_dp vfuncs */
b6b5e383
DL		 5249 if (INTEL_INFO(dev)->gen >= 9)
5250 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5251 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5252 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5253 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5254 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5255 else if (HAS_PCH_SPLIT(dev))
5256 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5257 else
5258 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5259
b9ca5fad
DL		 5260 if (INTEL_INFO(dev)->gen >= 9)
5261 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5262 else
5263 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5264
0767935e
DV		 5265 /* Preserve the current hw state. */
5266 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5267 intel_dp->attached_connector = intel_connector;
3d3dc149 5268
3b32a35b 5269 if (intel_dp_is_edp(dev, port))
b329530c 5270 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5271 else
5272 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5273
f7d24902
ID		 5274 /*
5275 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5276 * for DP the encoder type can be set by the caller to
5277 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5278 */
5279 if (type == DRM_MODE_CONNECTOR_eDP)
5280 intel_encoder->type = INTEL_OUTPUT_EDP;
5281
c17ed5b5
VS		 5282 /* eDP only on port B and/or C on vlv/chv */
5283 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5284 port != PORT_B && port != PORT_C))
5285 return false;
5286
e7281eab
ID		 5287 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5288 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5289 port_name(port));
5290
b329530c 5291 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5292 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5293
a4fc5ed6
KP		 5294 connector->interlace_allowed = true;
5295 connector->doublescan_allowed = 0;
5296
f0fec3f2 5297 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5298 edp_panel_vdd_work);
a4fc5ed6 5299
df0e9248 5300 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5301 drm_connector_register(connector);
a4fc5ed6 5302
affa9354 5303 if (HAS_DDI(dev))
bcbc889b
PZ		 5304 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5305 else
5306 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5307 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5308
0b99836f 5309 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5310 switch (port) {
5311 case PORT_A:
1d843f9d 5312 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5313 break;
5314 case PORT_B:
1d843f9d 5315 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5316 break;
5317 case PORT_C:
1d843f9d 5318 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5319 break;
5320 case PORT_D:
1d843f9d 5321 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5322 break;
5323 default:
ad1c0b19 5324 BUG();
5eb08b69
ZW		 5325 }
5326
dada1a9f 5327 if (is_edp(intel_dp)) {
773538e8 5328 pps_lock(intel_dp);
a4a5d2f8
VS		 5329 if (IS_VALLEYVIEW(dev)) {
5330 vlv_initial_power_sequencer_setup(intel_dp);
5331 } else {
5332 intel_dp_init_panel_power_timestamps(intel_dp);
36b5f425 5333 intel_dp_init_panel_power_sequencer(dev, intel_dp);
a4a5d2f8 5334 }
773538e8 5335 pps_unlock(intel_dp);
dada1a9f 5336 }
0095e6dc 5337
9d1a1031 5338 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5339
0e32b39c
DA		 5340 /* init MST on ports that can support it */
5341 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5342 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5343 intel_dp_mst_encoder_init(intel_dig_port,
5344 intel_connector->base.base.id);
0e32b39c
DA		 5345 }
5346 }
5347
36b5f425 5348 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5349 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5350 if (is_edp(intel_dp)) {
5351 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5352 /*
5353 * vdd might still be enabled do to the delayed vdd off.
5354 * Make sure vdd is actually turned off here.
5355 */
773538e8 5356 pps_lock(intel_dp);
4be73780 5357 edp_panel_vdd_off_sync(intel_dp);
773538e8 5358 pps_unlock(intel_dp);
15b1d171 5359 }
34ea3d38 5360 drm_connector_unregister(connector);
b2f246a8 5361 drm_connector_cleanup(connector);
16c25533 5362 return false;
b2f246a8 5363 }
32f9d658 5364
f684960e
CW		 5365 intel_dp_add_properties(intel_dp, connector);
5366
a4fc5ed6
KP		 5367 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5368 * 0xd. Failure to do so will result in spurious interrupts being
5369 * generated on the port when a cable is not attached.
5370 */
5371 if (IS_G4X(dev) && !IS_GM45(dev)) {
5372 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5373 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5374 }
16c25533
PZ		 5375
5376 return true;
a4fc5ed6 5377}
f0fec3f2
PZ		 5378
5379void
5380intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5381{
13cf5504 5382 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5383 struct intel_digital_port *intel_dig_port;
5384 struct intel_encoder *intel_encoder;
5385 struct drm_encoder *encoder;
5386 struct intel_connector *intel_connector;
5387
b14c5679 5388 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5389 if (!intel_dig_port)
5390 return;
5391
b14c5679 5392 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5393 if (!intel_connector) {
5394 kfree(intel_dig_port);
5395 return;
5396 }
5397
5398 intel_encoder = &intel_dig_port->base;
5399 encoder = &intel_encoder->base;
5400
5401 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5402 DRM_MODE_ENCODER_TMDS);
5403
5bfe2ac0 5404 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5405 intel_encoder->disable = intel_disable_dp;
00c09d70 5406 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5407 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5408 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5409 if (IS_CHERRYVIEW(dev)) {
9197c88b 5410 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5411 intel_encoder->pre_enable = chv_pre_enable_dp;
5412 intel_encoder->enable = vlv_enable_dp;
580d3811 5413 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5414 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5415 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5416 intel_encoder->pre_enable = vlv_pre_enable_dp;
5417 intel_encoder->enable = vlv_enable_dp;
49277c31 5418 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5419 } else {
ecff4f3b
JN		 5420 intel_encoder->pre_enable = g4x_pre_enable_dp;
5421 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5422 if (INTEL_INFO(dev)->gen >= 5)
5423 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5424 }
f0fec3f2 5425
174edf1f 5426 intel_dig_port->port = port;
f0fec3f2
PZ		 5427 intel_dig_port->dp.output_reg = output_reg;
5428
00c09d70 5429 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5430 if (IS_CHERRYVIEW(dev)) {
5431 if (port == PORT_D)
5432 intel_encoder->crtc_mask = 1 << 2;
5433 else
5434 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5435 } else {
5436 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5437 }
bc079e8b 5438 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5439 intel_encoder->hot_plug = intel_dp_hot_plug;
5440
13cf5504
DA		 5441 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5442 dev_priv->hpd_irq_port[port] = intel_dig_port;
5443
15b1d171
PZ		 5444 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5445 drm_encoder_cleanup(encoder);
5446 kfree(intel_dig_port);
b2f246a8 5447 kfree(intel_connector);
15b1d171 5448 }
f0fec3f2 5449}
0e32b39c
DA		 5450
5451void intel_dp_mst_suspend(struct drm_device *dev)
5452{
5453 struct drm_i915_private *dev_priv = dev->dev_private;
5454 int i;
5455
5456 /* disable MST */
5457 for (i = 0; i < I915_MAX_PORTS; i++) {
5458 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5459 if (!intel_dig_port)
5460 continue;
5461
5462 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5463 if (!intel_dig_port->dp.can_mst)
5464 continue;
5465 if (intel_dig_port->dp.is_mst)
5466 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5467 }
5468 }
5469}
5470
5471void intel_dp_mst_resume(struct drm_device *dev)
5472{
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 int i;
5475
5476 for (i = 0; i < I915_MAX_PORTS; i++) {
5477 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5478 if (!intel_dig_port)
5479 continue;
5480 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5481 int ret;
5482
5483 if (!intel_dig_port->dp.can_mst)
5484 continue;
5485
5486 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5487 if (ret != 0) {
5488 intel_dp_check_mst_status(&intel_dig_port->dp);
5489 }
5490 }
5491 }
5492}
Linux kernel - Deliverables
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