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drm/i915: Track which port is using which pipe's power sequencer
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 299 struct intel_encoder *encoder;
300 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
301 struct edp_power_seq power_seq;
bf13e81b 302
e39b999a
VS		 303 lockdep_assert_held(&dev_priv->pps_mutex);
304
a4a5d2f8
VS		 305 if (intel_dp->pps_pipe != INVALID_PIPE)
306 return intel_dp->pps_pipe;
307
308 /*
309 * We don't have power sequencer currently.
310 * Pick one that's not used by other ports.
311 */
312 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
313 base.head) {
314 struct intel_dp *tmp;
315
316 if (encoder->type != INTEL_OUTPUT_EDP)
317 continue;
318
319 tmp = enc_to_intel_dp(&encoder->base);
320
321 if (tmp->pps_pipe != INVALID_PIPE)
322 pipes &= ~(1 << tmp->pps_pipe);
323 }
324
325 /*
326 * Didn't find one. This should not happen since there
327 * are two power sequencers and up to two eDP ports.
328 */
329 if (WARN_ON(pipes == 0))
330 return PIPE_A;
331
332 intel_dp->pps_pipe = ffs(pipes) - 1;
333
334 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
335 pipe_name(intel_dp->pps_pipe),
336 port_name(intel_dig_port->port));
337
338 /* init power sequencer on this pipe and port */
339 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
340 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
341 &power_seq);
342
343 return intel_dp->pps_pipe;
344}
345
346static enum pipe
347vlv_initial_power_sequencer_pipe(struct drm_i915_private *dev_priv,
348 enum port port)
349{
350 enum pipe pipe;
bf13e81b 351
bf13e81b
JN		 352 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
353 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
354 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 355
356 if (port_sel != PANEL_PORT_SELECT_VLV(port))
357 continue;
358
359 return pipe;
bf13e81b
JN		 360 }
361
a4a5d2f8
VS		 362 return INVALID_PIPE;
363}
364
365static void
366vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
367{
368 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
369 struct drm_device *dev = intel_dig_port->base.base.dev;
370 struct drm_i915_private *dev_priv = dev->dev_private;
371 struct edp_power_seq power_seq;
372 enum port port = intel_dig_port->port;
373
374 lockdep_assert_held(&dev_priv->pps_mutex);
375
376 /* try to find a pipe with this port selected */
377 intel_dp->pps_pipe = vlv_initial_power_sequencer_pipe(dev_priv, port);
378
379 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
380 if (intel_dp->pps_pipe == INVALID_PIPE) {
381 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
382 port_name(port));
383 return;
384 }
385
386 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
387 port_name(port), pipe_name(intel_dp->pps_pipe));
388
389 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
390 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
391 &power_seq);
bf13e81b
JN		 392}
393
394static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
395{
396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
397
398 if (HAS_PCH_SPLIT(dev))
399 return PCH_PP_CONTROL;
400 else
401 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
402}
403
404static u32 _pp_stat_reg(struct intel_dp *intel_dp)
405{
406 struct drm_device *dev = intel_dp_to_dev(intel_dp);
407
408 if (HAS_PCH_SPLIT(dev))
409 return PCH_PP_STATUS;
410 else
411 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
412}
413
01527b31
CT		 414/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
415 This function only applicable when panel PM state is not to be tracked */
416static int edp_notify_handler(struct notifier_block *this, unsigned long code,
417 void *unused)
418{
419 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
420 edp_notifier);
421 struct drm_device *dev = intel_dp_to_dev(intel_dp);
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 u32 pp_div;
424 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 425
426 if (!is_edp(intel_dp) || code != SYS_RESTART)
427 return 0;
428
e39b999a
VS		 429 mutex_lock(&dev_priv->pps_mutex);
430
01527b31 431 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 432 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
433
01527b31
CT		 434 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
435 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
436 pp_div = I915_READ(pp_div_reg);
437 pp_div &= PP_REFERENCE_DIVIDER_MASK;
438
439 /* 0x1F write to PP_DIV_REG sets max cycle delay */
440 I915_WRITE(pp_div_reg, pp_div | 0x1F);
441 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
442 msleep(intel_dp->panel_power_cycle_delay);
443 }
444
e39b999a
VS		 445 mutex_unlock(&dev_priv->pps_mutex);
446
01527b31
CT		 447 return 0;
448}
449
4be73780 450static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 451{
30add22d 452 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 453 struct drm_i915_private *dev_priv = dev->dev_private;
454
e39b999a
VS		 455 lockdep_assert_held(&dev_priv->pps_mutex);
456
bf13e81b 457 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 458}
459
4be73780 460static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 461{
30add22d 462 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 463 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct intel_encoder *intel_encoder = &intel_dig_port->base;
466 enum intel_display_power_domain power_domain;
ebf33b18 467
e39b999a
VS		 468 lockdep_assert_held(&dev_priv->pps_mutex);
469
bb4932c4
ID		 470 power_domain = intel_display_port_power_domain(intel_encoder);
471 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 472 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 473}
474
9b984dae
KP		 475static void
476intel_dp_check_edp(struct intel_dp *intel_dp)
477{
30add22d 478 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 479 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 480
9b984dae
KP		 481 if (!is_edp(intel_dp))
482 return;
453c5420 483
4be73780 484 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 485 WARN(1, "eDP powered off while attempting aux channel communication.\n");
486 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 487 I915_READ(_pp_stat_reg(intel_dp)),
488 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 489 }
490}
491
9ee32fea
DV		 492static uint32_t
493intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 498 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 499 uint32_t status;
500 bool done;
501
ef04f00d 502#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 503 if (has_aux_irq)
b18ac466 504 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 505 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 506 else
507 done = wait_for_atomic(C, 10) == 0;
508 if (!done)
509 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
510 has_aux_irq);
511#undef C
512
513 return status;
514}
515
ec5b01dd 516static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 517{
174edf1f
PZ		 518 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
519 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 520
ec5b01dd
DL		 521 /*
522 * The clock divider is based off the hrawclk, and would like to run at
523 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 524 */
ec5b01dd
DL		 525 return index ? 0 : intel_hrawclk(dev) / 2;
526}
527
528static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
529{
530 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
531 struct drm_device *dev = intel_dig_port->base.base.dev;
532
533 if (index)
534 return 0;
535
536 if (intel_dig_port->port == PORT_A) {
537 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 538 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 539 else
b84a1cf8 540 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 541 } else {
542 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
543 }
544}
545
546static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
547{
548 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
549 struct drm_device *dev = intel_dig_port->base.base.dev;
550 struct drm_i915_private *dev_priv = dev->dev_private;
551
552 if (intel_dig_port->port == PORT_A) {
553 if (index)
554 return 0;
555 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 556 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
557 /* Workaround for non-ULT HSW */
bc86625a
CW		 558 switch (index) {
559 case 0: return 63;
560 case 1: return 72;
561 default: return 0;
562 }
ec5b01dd 563 } else {
bc86625a 564 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 565 }
b84a1cf8
RV		 566}
567
ec5b01dd
DL		 568static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
569{
570 return index ? 0 : 100;
571}
572
5ed12a19
DL		 573static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
574 bool has_aux_irq,
575 int send_bytes,
576 uint32_t aux_clock_divider)
577{
578 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
579 struct drm_device *dev = intel_dig_port->base.base.dev;
580 uint32_t precharge, timeout;
581
582 if (IS_GEN6(dev))
583 precharge = 3;
584 else
585 precharge = 5;
586
587 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
588 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
589 else
590 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
591
592 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 593 DP_AUX_CH_CTL_DONE |
5ed12a19 594 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 595 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 596 timeout |
788d4433 597 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 598 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
599 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 600 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 601}
602
b84a1cf8
RV		 603static int
604intel_dp_aux_ch(struct intel_dp *intel_dp,
605 uint8_t *send, int send_bytes,
606 uint8_t *recv, int recv_size)
607{
608 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
609 struct drm_device *dev = intel_dig_port->base.base.dev;
610 struct drm_i915_private *dev_priv = dev->dev_private;
611 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
612 uint32_t ch_data = ch_ctl + 4;
bc86625a 613 uint32_t aux_clock_divider;
b84a1cf8
RV		 614 int i, ret, recv_bytes;
615 uint32_t status;
5ed12a19 616 int try, clock = 0;
4e6b788c 617 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 618 bool vdd;
619
e39b999a
VS		 620 mutex_lock(&dev_priv->pps_mutex);
621
72c3500a
VS		 622 /*
623 * We will be called with VDD already enabled for dpcd/edid/oui reads.
624 * In such cases we want to leave VDD enabled and it's up to upper layers
625 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
626 * ourselves.
627 */
1e0560e0 628 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 629
630 /* dp aux is extremely sensitive to irq latency, hence request the
631 * lowest possible wakeup latency and so prevent the cpu from going into
632 * deep sleep states.
633 */
634 pm_qos_update_request(&dev_priv->pm_qos, 0);
635
636 intel_dp_check_edp(intel_dp);
5eb08b69 637
c67a470b
PZ		 638 intel_aux_display_runtime_get(dev_priv);
639
11bee43e
JB		 640 /* Try to wait for any previous AUX channel activity */
641 for (try = 0; try < 3; try++) {
ef04f00d 642 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 643 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
644 break;
645 msleep(1);
646 }
647
648 if (try == 3) {
649 WARN(1, "dp_aux_ch not started status 0x%08x\n",
650 I915_READ(ch_ctl));
9ee32fea
DV		 651 ret = -EBUSY;
652 goto out;
4f7f7b7e
CW		 653 }
654
46a5ae9f
PZ		 655 /* Only 5 data registers! */
656 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
657 ret = -E2BIG;
658 goto out;
659 }
660
ec5b01dd 661 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 662 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
663 has_aux_irq,
664 send_bytes,
665 aux_clock_divider);
5ed12a19 666
bc86625a
CW		 667 /* Must try at least 3 times according to DP spec */
668 for (try = 0; try < 5; try++) {
669 /* Load the send data into the aux channel data registers */
670 for (i = 0; i < send_bytes; i += 4)
671 I915_WRITE(ch_data + i,
672 pack_aux(send + i, send_bytes - i));
673
674 /* Send the command and wait for it to complete */
5ed12a19 675 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 676
677 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
678
679 /* Clear done status and any errors */
680 I915_WRITE(ch_ctl,
681 status |
682 DP_AUX_CH_CTL_DONE |
683 DP_AUX_CH_CTL_TIME_OUT_ERROR |
684 DP_AUX_CH_CTL_RECEIVE_ERROR);
685
686 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
687 DP_AUX_CH_CTL_RECEIVE_ERROR))
688 continue;
689 if (status & DP_AUX_CH_CTL_DONE)
690 break;
691 }
4f7f7b7e 692 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 693 break;
694 }
695
a4fc5ed6 696 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 697 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 698 ret = -EBUSY;
699 goto out;
a4fc5ed6
KP		 700 }
701
702 /* Check for timeout or receive error.
703 * Timeouts occur when the sink is not connected
704 */
a5b3da54 705 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 706 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 707 ret = -EIO;
708 goto out;
a5b3da54 709 }
1ae8c0a5
KP		 710
711 /* Timeouts occur when the device isn't connected, so they're
712 * "normal" -- don't fill the kernel log with these */
a5b3da54 713 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 714 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 715 ret = -ETIMEDOUT;
716 goto out;
a4fc5ed6
KP		 717 }
718
719 /* Unload any bytes sent back from the other side */
720 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
721 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 722 if (recv_bytes > recv_size)
723 recv_bytes = recv_size;
0206e353 724
4f7f7b7e
CW		 725 for (i = 0; i < recv_bytes; i += 4)
726 unpack_aux(I915_READ(ch_data + i),
727 recv + i, recv_bytes - i);
a4fc5ed6 728
9ee32fea
DV		 729 ret = recv_bytes;
730out:
731 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 732 intel_aux_display_runtime_put(dev_priv);
9ee32fea 733
884f19e9
JN		 734 if (vdd)
735 edp_panel_vdd_off(intel_dp, false);
736
e39b999a
VS		 737 mutex_unlock(&dev_priv->pps_mutex);
738
9ee32fea 739 return ret;
a4fc5ed6
KP		 740}
741
a6c8aff0
JN		 742#define BARE_ADDRESS_SIZE 3
743#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 744static ssize_t
745intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 746{
9d1a1031
JN		 747 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
748 uint8_t txbuf[20], rxbuf[20];
749 size_t txsize, rxsize;
a4fc5ed6 750 int ret;
a4fc5ed6 751
9d1a1031
JN		 752 txbuf[0] = msg->request << 4;
753 txbuf[1] = msg->address >> 8;
754 txbuf[2] = msg->address & 0xff;
755 txbuf[3] = msg->size - 1;
46a5ae9f 756
9d1a1031
JN		 757 switch (msg->request & ~DP_AUX_I2C_MOT) {
758 case DP_AUX_NATIVE_WRITE:
759 case DP_AUX_I2C_WRITE:
a6c8aff0 760 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 761 rxsize = 1;
f51a44b9 762
9d1a1031
JN		 763 if (WARN_ON(txsize > 20))
764 return -E2BIG;
a4fc5ed6 765
9d1a1031 766 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 767
9d1a1031
JN		 768 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
769 if (ret > 0) {
770 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 771
9d1a1031
JN		 772 /* Return payload size. */
773 ret = msg->size;
774 }
775 break;
46a5ae9f 776
9d1a1031
JN		 777 case DP_AUX_NATIVE_READ:
778 case DP_AUX_I2C_READ:
a6c8aff0 779 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 780 rxsize = msg->size + 1;
a4fc5ed6 781
9d1a1031
JN		 782 if (WARN_ON(rxsize > 20))
783 return -E2BIG;
a4fc5ed6 784
9d1a1031
JN		 785 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
786 if (ret > 0) {
787 msg->reply = rxbuf[0] >> 4;
788 /*
789 * Assume happy day, and copy the data. The caller is
790 * expected to check msg->reply before touching it.
791 *
792 * Return payload size.
793 */
794 ret--;
795 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 796 }
9d1a1031
JN		 797 break;
798
799 default:
800 ret = -EINVAL;
801 break;
a4fc5ed6 802 }
f51a44b9 803
9d1a1031 804 return ret;
a4fc5ed6
KP		 805}
806
9d1a1031
JN		 807static void
808intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
809{
810 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
812 enum port port = intel_dig_port->port;
0b99836f 813 const char *name = NULL;
ab2c0672
DA		 814 int ret;
815
33ad6626
JN		 816 switch (port) {
817 case PORT_A:
818 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 819 name = "DPDDC-A";
ab2c0672 820 break;
33ad6626
JN		 821 case PORT_B:
822 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 823 name = "DPDDC-B";
ab2c0672 824 break;
33ad6626
JN		 825 case PORT_C:
826 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 827 name = "DPDDC-C";
ab2c0672 828 break;
33ad6626
JN		 829 case PORT_D:
830 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 831 name = "DPDDC-D";
33ad6626
JN		 832 break;
833 default:
834 BUG();
ab2c0672
DA		 835 }
836
33ad6626
JN		 837 if (!HAS_DDI(dev))
838 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 839
0b99836f 840 intel_dp->aux.name = name;
9d1a1031
JN		 841 intel_dp->aux.dev = dev->dev;
842 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 843
0b99836f
JN		 844 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
845 connector->base.kdev->kobj.name);
8316f337 846
4f71d0cb 847 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 848 if (ret < 0) {
4f71d0cb 849 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 850 name, ret);
851 return;
ab2c0672 852 }
8a5e6aeb 853
0b99836f
JN		 854 ret = sysfs_create_link(&connector->base.kdev->kobj,
855 &intel_dp->aux.ddc.dev.kobj,
856 intel_dp->aux.ddc.dev.kobj.name);
857 if (ret < 0) {
858 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 859 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 860 }
a4fc5ed6
KP		 861}
862
80f65de3
ID		 863static void
864intel_dp_connector_unregister(struct intel_connector *intel_connector)
865{
866 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
867
0e32b39c
DA		 868 if (!intel_connector->mst_port)
869 sysfs_remove_link(&intel_connector->base.kdev->kobj,
870 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 871 intel_connector_unregister(intel_connector);
872}
873
0e50338c
DV		 874static void
875hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
876{
877 switch (link_bw) {
878 case DP_LINK_BW_1_62:
879 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
880 break;
881 case DP_LINK_BW_2_7:
882 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
883 break;
884 case DP_LINK_BW_5_4:
885 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
886 break;
887 }
888}
889
c6bb3538
DV		 890static void
891intel_dp_set_clock(struct intel_encoder *encoder,
892 struct intel_crtc_config *pipe_config, int link_bw)
893{
894 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 895 const struct dp_link_dpll *divisor = NULL;
896 int i, count = 0;
c6bb3538
DV		 897
898 if (IS_G4X(dev)) {
9dd4ffdf
CML		 899 divisor = gen4_dpll;
900 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 901 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 902 divisor = pch_dpll;
903 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 904 } else if (IS_CHERRYVIEW(dev)) {
905 divisor = chv_dpll;
906 count = ARRAY_SIZE(chv_dpll);
c6bb3538 907 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 908 divisor = vlv_dpll;
909 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 910 }
9dd4ffdf
CML		 911
912 if (divisor && count) {
913 for (i = 0; i < count; i++) {
914 if (link_bw == divisor[i].link_bw) {
915 pipe_config->dpll = divisor[i].dpll;
916 pipe_config->clock_set = true;
917 break;
918 }
919 }
c6bb3538
DV		 920 }
921}
922
00c09d70 923bool
5bfe2ac0
DV		 924intel_dp_compute_config(struct intel_encoder *encoder,
925 struct intel_crtc_config *pipe_config)
a4fc5ed6 926{
5bfe2ac0 927 struct drm_device *dev = encoder->base.dev;
36008365 928 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 929 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 930 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 931 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 932 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 933 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 934 int lane_count, clock;
56071a20 935 int min_lane_count = 1;
eeb6324d 936 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 937 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 938 int min_clock = 0;
06ea66b6 939 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 940 int bpp, mode_rate;
06ea66b6 941 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 942 int link_avail, link_clock;
a4fc5ed6 943
bc7d38a4 944 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 945 pipe_config->has_pch_encoder = true;
946
03afc4a2 947 pipe_config->has_dp_encoder = true;
f769cd24 948 pipe_config->has_drrs = false;
9ed109a7 949 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 950
dd06f90e
JN		 951 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
952 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
953 adjusted_mode);
2dd24552
JB		 954 if (!HAS_PCH_SPLIT(dev))
955 intel_gmch_panel_fitting(intel_crtc, pipe_config,
956 intel_connector->panel.fitting_mode);
957 else
b074cec8
JB		 958 intel_pch_panel_fitting(intel_crtc, pipe_config,
959 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 960 }
961
cb1793ce 962 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 963 return false;
964
083f9560
DV		 965 DRM_DEBUG_KMS("DP link computation with max lane count %i "
966 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 967 max_lane_count, bws[max_clock],
968 adjusted_mode->crtc_clock);
083f9560 969
36008365
DV		 970 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
971 * bpc in between. */
3e7ca985 972 bpp = pipe_config->pipe_bpp;
56071a20
JN		 973 if (is_edp(intel_dp)) {
974 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
975 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
976 dev_priv->vbt.edp_bpp);
977 bpp = dev_priv->vbt.edp_bpp;
978 }
979
f4cdbc21
JN		 980 if (IS_BROADWELL(dev)) {
981 /* Yes, it's an ugly hack. */
982 min_lane_count = max_lane_count;
983 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
984 min_lane_count);
985 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 986 min_lane_count = min(dev_priv->vbt.edp_lanes,
987 max_lane_count);
988 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
989 min_lane_count);
990 }
991
992 if (dev_priv->vbt.edp_rate) {
993 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
994 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
995 bws[min_clock]);
996 }
7984211e 997 }
657445fe 998
36008365 999 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1000 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1001 bpp);
36008365 1002
c6930992
DA		 1003 for (clock = min_clock; clock <= max_clock; clock++) {
1004 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1005 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1006 link_avail = intel_dp_max_data_rate(link_clock,
1007 lane_count);
1008
1009 if (mode_rate <= link_avail) {
1010 goto found;
1011 }
1012 }
1013 }
1014 }
c4867936 1015
36008365 1016 return false;
3685a8f3 1017
36008365 1018found:
55bc60db
VS		 1019 if (intel_dp->color_range_auto) {
1020 /*
1021 * See:
1022 * CEA-861-E - 5.1 Default Encoding Parameters
1023 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1024 */
18316c8c 1025 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1026 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1027 else
1028 intel_dp->color_range = 0;
1029 }
1030
3685a8f3 1031 if (intel_dp->color_range)
50f3b016 1032 pipe_config->limited_color_range = true;
a4fc5ed6 1033
36008365
DV		 1034 intel_dp->link_bw = bws[clock];
1035 intel_dp->lane_count = lane_count;
657445fe 1036 pipe_config->pipe_bpp = bpp;
ff9a6750 1037 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1038
36008365
DV		 1039 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1040 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1041 pipe_config->port_clock, bpp);
36008365
DV		 1042 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1043 mode_rate, link_avail);
a4fc5ed6 1044
03afc4a2 1045 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1046 adjusted_mode->crtc_clock,
1047 pipe_config->port_clock,
03afc4a2 1048 &pipe_config->dp_m_n);
9d1a455b 1049
439d7ac0
PB		 1050 if (intel_connector->panel.downclock_mode != NULL &&
1051 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1052 pipe_config->has_drrs = true;
439d7ac0
PB		 1053 intel_link_compute_m_n(bpp, lane_count,
1054 intel_connector->panel.downclock_mode->clock,
1055 pipe_config->port_clock,
1056 &pipe_config->dp_m2_n2);
1057 }
1058
ea155f32 1059 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1060 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1061 else
1062 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1063
03afc4a2 1064 return true;
a4fc5ed6
KP		 1065}
1066
7c62a164 1067static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1068{
7c62a164
DV		 1069 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1070 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1071 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 u32 dpa_ctl;
1074
ff9a6750 1075 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1076 dpa_ctl = I915_READ(DP_A);
1077 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1078
ff9a6750 1079 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1080 /* For a long time we've carried around a ILK-DevA w/a for the
1081 * 160MHz clock. If we're really unlucky, it's still required.
1082 */
1083 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1084 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1085 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1086 } else {
1087 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1088 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1089 }
1ce17038 1090
ea9b6006
DV		 1091 I915_WRITE(DP_A, dpa_ctl);
1092
1093 POSTING_READ(DP_A);
1094 udelay(500);
1095}
1096
8ac33ed3 1097static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1098{
b934223d 1099 struct drm_device *dev = encoder->base.dev;
417e822d 1100 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1101 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1102 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1103 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1104 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1105
417e822d 1106 /*
1a2eb460 1107 * There are four kinds of DP registers:
417e822d
KP		 1108 *
1109 * IBX PCH
1a2eb460
KP		 1110 * SNB CPU
1111 * IVB CPU
417e822d
KP		 1112 * CPT PCH
1113 *
1114 * IBX PCH and CPU are the same for almost everything,
1115 * except that the CPU DP PLL is configured in this
1116 * register
1117 *
1118 * CPT PCH is quite different, having many bits moved
1119 * to the TRANS_DP_CTL register instead. That
1120 * configuration happens (oddly) in ironlake_pch_enable
1121 */
9c9e7927 1122
417e822d
KP		 1123 /* Preserve the BIOS-computed detected bit. This is
1124 * supposed to be read-only.
1125 */
1126 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1127
417e822d 1128 /* Handle DP bits in common between all three register formats */
417e822d 1129 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1130 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1131
9ed109a7 1132 if (crtc->config.has_audio) {
e0dac65e 1133 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1134 pipe_name(crtc->pipe));
ea5b213a 1135 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1136 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1137 }
247d89f6 1138
417e822d 1139 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1140
bc7d38a4 1141 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1142 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1143 intel_dp->DP |= DP_SYNC_HS_HIGH;
1144 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1145 intel_dp->DP |= DP_SYNC_VS_HIGH;
1146 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1147
6aba5b6c 1148 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1149 intel_dp->DP |= DP_ENHANCED_FRAMING;
1150
7c62a164 1151 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1152 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1153 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1154 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1155
1156 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1157 intel_dp->DP |= DP_SYNC_HS_HIGH;
1158 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1159 intel_dp->DP |= DP_SYNC_VS_HIGH;
1160 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1161
6aba5b6c 1162 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1163 intel_dp->DP |= DP_ENHANCED_FRAMING;
1164
44f37d1f
CML		 1165 if (!IS_CHERRYVIEW(dev)) {
1166 if (crtc->pipe == 1)
1167 intel_dp->DP |= DP_PIPEB_SELECT;
1168 } else {
1169 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1170 }
417e822d
KP		 1171 } else {
1172 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1173 }
a4fc5ed6
KP		 1174}
1175
ffd6749d
PZ		 1176#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1177#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1178
1a5ef5b7
PZ		 1179#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1180#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1181
ffd6749d
PZ		 1182#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1183#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1184
4be73780 1185static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1186 u32 mask,
1187 u32 value)
bd943159 1188{
30add22d 1189 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1190 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1191 u32 pp_stat_reg, pp_ctrl_reg;
1192
e39b999a
VS		 1193 lockdep_assert_held(&dev_priv->pps_mutex);
1194
bf13e81b
JN		 1195 pp_stat_reg = _pp_stat_reg(intel_dp);
1196 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1197
99ea7127 1198 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1199 mask, value,
1200 I915_READ(pp_stat_reg),
1201 I915_READ(pp_ctrl_reg));
32ce697c 1202
453c5420 1203 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1204 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1205 I915_READ(pp_stat_reg),
1206 I915_READ(pp_ctrl_reg));
32ce697c 1207 }
54c136d4
CW		 1208
1209 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1210}
32ce697c 1211
4be73780 1212static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1213{
1214 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1215 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1216}
1217
4be73780 1218static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1219{
1220 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1221 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1222}
1223
4be73780 1224static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1225{
1226 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1227
1228 /* When we disable the VDD override bit last we have to do the manual
1229 * wait. */
1230 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1231 intel_dp->panel_power_cycle_delay);
1232
4be73780 1233 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1234}
1235
4be73780 1236static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1237{
1238 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1239 intel_dp->backlight_on_delay);
1240}
1241
4be73780 1242static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1243{
1244 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1245 intel_dp->backlight_off_delay);
1246}
99ea7127 1247
832dd3c1
KP		 1248/* Read the current pp_control value, unlocking the register if it
1249 * is locked
1250 */
1251
453c5420 1252static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1253{
453c5420
JB		 1254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1255 struct drm_i915_private *dev_priv = dev->dev_private;
1256 u32 control;
832dd3c1 1257
e39b999a
VS		 1258 lockdep_assert_held(&dev_priv->pps_mutex);
1259
bf13e81b 1260 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1261 control &= ~PANEL_UNLOCK_MASK;
1262 control |= PANEL_UNLOCK_REGS;
1263 return control;
bd943159
KP		 1264}
1265
1e0560e0 1266static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1267{
30add22d 1268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1270 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1271 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1272 enum intel_display_power_domain power_domain;
5d613501 1273 u32 pp;
453c5420 1274 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1275 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1276
e39b999a
VS		 1277 lockdep_assert_held(&dev_priv->pps_mutex);
1278
97af61f5 1279 if (!is_edp(intel_dp))
adddaaf4 1280 return false;
bd943159
KP		 1281
1282 intel_dp->want_panel_vdd = true;
99ea7127 1283
4be73780 1284 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1285 return need_to_disable;
b0665d57 1286
4e6e1a54
ID		 1287 power_domain = intel_display_port_power_domain(intel_encoder);
1288 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1289
b0665d57 1290 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1291
4be73780
DV		 1292 if (!edp_have_panel_power(intel_dp))
1293 wait_panel_power_cycle(intel_dp);
99ea7127 1294
453c5420 1295 pp = ironlake_get_pp_control(intel_dp);
5d613501 1296 pp |= EDP_FORCE_VDD;
ebf33b18 1297
bf13e81b
JN		 1298 pp_stat_reg = _pp_stat_reg(intel_dp);
1299 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1300
1301 I915_WRITE(pp_ctrl_reg, pp);
1302 POSTING_READ(pp_ctrl_reg);
1303 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1304 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1305 /*
1306 * If the panel wasn't on, delay before accessing aux channel
1307 */
4be73780 1308 if (!edp_have_panel_power(intel_dp)) {
bd943159 1309 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1310 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1311 }
adddaaf4
JN		 1312
1313 return need_to_disable;
1314}
1315
b80d6c78 1316void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1317{
e39b999a
VS		 1318 struct drm_i915_private *dev_priv =
1319 intel_dp_to_dev(intel_dp)->dev_private;
c695b6b6 1320 bool vdd;
adddaaf4 1321
c695b6b6
VS		 1322 if (!is_edp(intel_dp))
1323 return;
1324
e39b999a 1325 mutex_lock(&dev_priv->pps_mutex);
c695b6b6 1326 vdd = edp_panel_vdd_on(intel_dp);
e39b999a 1327 mutex_unlock(&dev_priv->pps_mutex);
c695b6b6
VS		 1328
1329 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1330}
1331
4be73780 1332static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1333{
30add22d 1334 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1335 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1336 struct intel_digital_port *intel_dig_port =
1337 dp_to_dig_port(intel_dp);
1338 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1339 enum intel_display_power_domain power_domain;
5d613501 1340 u32 pp;
453c5420 1341 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1342
e39b999a 1343 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1344
15e899a0
VS		 1345 WARN_ON(intel_dp->want_panel_vdd);
1346
1347 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1348 return;
4e6e1a54 1349
be2c9196 1350 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1351
be2c9196
VS		 1352 pp = ironlake_get_pp_control(intel_dp);
1353 pp &= ~EDP_FORCE_VDD;
bd943159 1354
be2c9196
VS		 1355 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1356 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1357
be2c9196
VS		 1358 I915_WRITE(pp_ctrl_reg, pp);
1359 POSTING_READ(pp_ctrl_reg);
99ea7127 1360
be2c9196
VS		 1361 /* Make sure sequencer is idle before allowing subsequent activity */
1362 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1363 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1364
be2c9196
VS		 1365 if ((pp & POWER_TARGET_ON) == 0)
1366 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1367
be2c9196
VS		 1368 power_domain = intel_display_port_power_domain(intel_encoder);
1369 intel_display_power_put(dev_priv, power_domain);
bd943159 1370}
5d613501 1371
4be73780 1372static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1373{
1374 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1375 struct intel_dp, panel_vdd_work);
e39b999a
VS		 1376 struct drm_i915_private *dev_priv =
1377 intel_dp_to_dev(intel_dp)->dev_private;
bd943159 1378
e39b999a 1379 mutex_lock(&dev_priv->pps_mutex);
15e899a0
VS		 1380 if (!intel_dp->want_panel_vdd)
1381 edp_panel_vdd_off_sync(intel_dp);
e39b999a 1382 mutex_unlock(&dev_priv->pps_mutex);
bd943159
KP		 1383}
1384
aba86890
ID		 1385static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1386{
1387 unsigned long delay;
1388
1389 /*
1390 * Queue the timer to fire a long time from now (relative to the power
1391 * down delay) to keep the panel power up across a sequence of
1392 * operations.
1393 */
1394 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1395 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1396}
1397
4be73780 1398static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1399{
e39b999a
VS		 1400 struct drm_i915_private *dev_priv =
1401 intel_dp_to_dev(intel_dp)->dev_private;
1402
1403 lockdep_assert_held(&dev_priv->pps_mutex);
1404
97af61f5
KP		 1405 if (!is_edp(intel_dp))
1406 return;
5d613501 1407
bd943159 1408 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1409
bd943159
KP		 1410 intel_dp->want_panel_vdd = false;
1411
aba86890 1412 if (sync)
4be73780 1413 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1414 else
1415 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1416}
1417
1e0560e0
VS		 1418static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1419{
e39b999a
VS		 1420 struct drm_i915_private *dev_priv =
1421 intel_dp_to_dev(intel_dp)->dev_private;
1422
1423 if (!is_edp(intel_dp))
1424 return;
1425
1426 mutex_lock(&dev_priv->pps_mutex);
1e0560e0 1427 edp_panel_vdd_off(intel_dp, sync);
e39b999a 1428 mutex_unlock(&dev_priv->pps_mutex);
1e0560e0
VS		 1429}
1430
4be73780 1431void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1432{
30add22d 1433 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1434 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1435 u32 pp;
453c5420 1436 u32 pp_ctrl_reg;
9934c132 1437
97af61f5 1438 if (!is_edp(intel_dp))
bd943159 1439 return;
99ea7127
KP		 1440
1441 DRM_DEBUG_KMS("Turn eDP power on\n");
1442
e39b999a
VS		 1443 mutex_lock(&dev_priv->pps_mutex);
1444
4be73780 1445 if (edp_have_panel_power(intel_dp)) {
99ea7127 1446 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1447 goto out;
99ea7127 1448 }
9934c132 1449
4be73780 1450 wait_panel_power_cycle(intel_dp);
37c6c9b0 1451
bf13e81b 1452 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1453 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1454 if (IS_GEN5(dev)) {
1455 /* ILK workaround: disable reset around power sequence */
1456 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1457 I915_WRITE(pp_ctrl_reg, pp);
1458 POSTING_READ(pp_ctrl_reg);
05ce1a49 1459 }
37c6c9b0 1460
1c0ae80a 1461 pp |= POWER_TARGET_ON;
99ea7127
KP		 1462 if (!IS_GEN5(dev))
1463 pp |= PANEL_POWER_RESET;
1464
453c5420
JB		 1465 I915_WRITE(pp_ctrl_reg, pp);
1466 POSTING_READ(pp_ctrl_reg);
9934c132 1467
4be73780 1468 wait_panel_on(intel_dp);
dce56b3c 1469 intel_dp->last_power_on = jiffies;
9934c132 1470
05ce1a49
KP		 1471 if (IS_GEN5(dev)) {
1472 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1473 I915_WRITE(pp_ctrl_reg, pp);
1474 POSTING_READ(pp_ctrl_reg);
05ce1a49 1475 }
e39b999a
VS		 1476
1477 out:
1478 mutex_unlock(&dev_priv->pps_mutex);
9934c132
JB		 1479}
1480
4be73780 1481void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1482{
4e6e1a54
ID		 1483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1484 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1485 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1486 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1487 enum intel_display_power_domain power_domain;
99ea7127 1488 u32 pp;
453c5420 1489 u32 pp_ctrl_reg;
9934c132 1490
97af61f5
KP		 1491 if (!is_edp(intel_dp))
1492 return;
37c6c9b0 1493
99ea7127 1494 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1495
e39b999a
VS		 1496 mutex_lock(&dev_priv->pps_mutex);
1497
24f3e092
JN		 1498 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1499
453c5420 1500 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1501 /* We need to switch off panel power _and_ force vdd, for otherwise some
1502 * panels get very unhappy and cease to work. */
b3064154
PJ		 1503 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1504 EDP_BLC_ENABLE);
453c5420 1505
bf13e81b 1506 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1507
849e39f5
PZ		 1508 intel_dp->want_panel_vdd = false;
1509
453c5420
JB		 1510 I915_WRITE(pp_ctrl_reg, pp);
1511 POSTING_READ(pp_ctrl_reg);
9934c132 1512
dce56b3c 1513 intel_dp->last_power_cycle = jiffies;
4be73780 1514 wait_panel_off(intel_dp);
849e39f5
PZ		 1515
1516 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1517 power_domain = intel_display_port_power_domain(intel_encoder);
1518 intel_display_power_put(dev_priv, power_domain);
e39b999a
VS		 1519
1520 mutex_unlock(&dev_priv->pps_mutex);
9934c132
JB		 1521}
1522
1250d107
JN		 1523/* Enable backlight in the panel power control. */
1524static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1525{
da63a9f2
PZ		 1526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1527 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 u32 pp;
453c5420 1530 u32 pp_ctrl_reg;
32f9d658 1531
01cb9ea6
JB		 1532 /*
1533 * If we enable the backlight right away following a panel power
1534 * on, we may see slight flicker as the panel syncs with the eDP
1535 * link. So delay a bit to make sure the image is solid before
1536 * allowing it to appear.
1537 */
4be73780 1538 wait_backlight_on(intel_dp);
e39b999a
VS		 1539
1540 mutex_lock(&dev_priv->pps_mutex);
1541
453c5420 1542 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1543 pp |= EDP_BLC_ENABLE;
453c5420 1544
bf13e81b 1545 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1546
1547 I915_WRITE(pp_ctrl_reg, pp);
1548 POSTING_READ(pp_ctrl_reg);
e39b999a
VS		 1549
1550 mutex_unlock(&dev_priv->pps_mutex);
32f9d658
ZW		 1551}
1552
1250d107
JN		 1553/* Enable backlight PWM and backlight PP control. */
1554void intel_edp_backlight_on(struct intel_dp *intel_dp)
1555{
1556 if (!is_edp(intel_dp))
1557 return;
1558
1559 DRM_DEBUG_KMS("\n");
1560
1561 intel_panel_enable_backlight(intel_dp->attached_connector);
1562 _intel_edp_backlight_on(intel_dp);
1563}
1564
1565/* Disable backlight in the panel power control. */
1566static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1567{
30add22d 1568 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570 u32 pp;
453c5420 1571 u32 pp_ctrl_reg;
32f9d658 1572
e39b999a
VS		 1573 if (!is_edp(intel_dp))
1574 return;
1575
1576 mutex_lock(&dev_priv->pps_mutex);
1577
453c5420 1578 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1579 pp &= ~EDP_BLC_ENABLE;
453c5420 1580
bf13e81b 1581 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1582
1583 I915_WRITE(pp_ctrl_reg, pp);
1584 POSTING_READ(pp_ctrl_reg);
f7d2323c 1585
e39b999a
VS		 1586 mutex_unlock(&dev_priv->pps_mutex);
1587
1588 intel_dp->last_backlight_off = jiffies;
f7d2323c 1589 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1590}
1591
1592/* Disable backlight PP control and backlight PWM. */
1593void intel_edp_backlight_off(struct intel_dp *intel_dp)
1594{
1595 if (!is_edp(intel_dp))
1596 return;
1597
1598 DRM_DEBUG_KMS("\n");
f7d2323c 1599
1250d107 1600 _intel_edp_backlight_off(intel_dp);
f7d2323c 1601 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1602}
a4fc5ed6 1603
73580fb7
JN		 1604/*
1605 * Hook for controlling the panel power control backlight through the bl_power
1606 * sysfs attribute. Take care to handle multiple calls.
1607 */
1608static void intel_edp_backlight_power(struct intel_connector *connector,
1609 bool enable)
1610{
e39b999a 1611 struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
73580fb7 1612 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1613 bool is_enabled;
1614
1615 mutex_lock(&dev_priv->pps_mutex);
1616 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1617 mutex_unlock(&dev_priv->pps_mutex);
73580fb7
JN		 1618
1619 if (is_enabled == enable)
1620 return;
1621
23ba9373
JN		 1622 DRM_DEBUG_KMS("panel power control backlight %s\n",
1623 enable ? "enable" : "disable");
73580fb7
JN		 1624
1625 if (enable)
1626 _intel_edp_backlight_on(intel_dp);
1627 else
1628 _intel_edp_backlight_off(intel_dp);
1629}
1630
2bd2ad64 1631static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1632{
da63a9f2
PZ		 1633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1634 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1635 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 u32 dpa_ctl;
1638
2bd2ad64
DV		 1639 assert_pipe_disabled(dev_priv,
1640 to_intel_crtc(crtc)->pipe);
1641
d240f20f
JB		 1642 DRM_DEBUG_KMS("\n");
1643 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1644 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1645 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1646
1647 /* We don't adjust intel_dp->DP while tearing down the link, to
1648 * facilitate link retraining (e.g. after hotplug). Hence clear all
1649 * enable bits here to ensure that we don't enable too much. */
1650 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1651 intel_dp->DP |= DP_PLL_ENABLE;
1652 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1653 POSTING_READ(DP_A);
1654 udelay(200);
d240f20f
JB		 1655}
1656
2bd2ad64 1657static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1658{
da63a9f2
PZ		 1659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1660 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1661 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 u32 dpa_ctl;
1664
2bd2ad64
DV		 1665 assert_pipe_disabled(dev_priv,
1666 to_intel_crtc(crtc)->pipe);
1667
d240f20f 1668 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1669 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1670 "dp pll off, should be on\n");
1671 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1672
1673 /* We can't rely on the value tracked for the DP register in
1674 * intel_dp->DP because link_down must not change that (otherwise link
1675 * re-training will fail. */
298b0b39 1676 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1677 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1678 POSTING_READ(DP_A);
d240f20f
JB		 1679 udelay(200);
1680}
1681
c7ad3810 1682/* If the sink supports it, try to set the power state appropriately */
c19b0669 1683void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1684{
1685 int ret, i;
1686
1687 /* Should have a valid DPCD by this point */
1688 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1689 return;
1690
1691 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1692 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1693 DP_SET_POWER_D3);
c7ad3810
JB		 1694 } else {
1695 /*
1696 * When turning on, we need to retry for 1ms to give the sink
1697 * time to wake up.
1698 */
1699 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1700 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1701 DP_SET_POWER_D0);
c7ad3810
JB		 1702 if (ret == 1)
1703 break;
1704 msleep(1);
1705 }
1706 }
f9cac721
JN		 1707
1708 if (ret != 1)
1709 DRM_DEBUG_KMS("failed to %s sink power state\n",
1710 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1711}
1712
19d8fe15
DV		 1713static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1714 enum pipe *pipe)
d240f20f 1715{
19d8fe15 1716 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1717 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1718 struct drm_device *dev = encoder->base.dev;
1719 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1720 enum intel_display_power_domain power_domain;
1721 u32 tmp;
1722
1723 power_domain = intel_display_port_power_domain(encoder);
1724 if (!intel_display_power_enabled(dev_priv, power_domain))
1725 return false;
1726
1727 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1728
1729 if (!(tmp & DP_PORT_EN))
1730 return false;
1731
bc7d38a4 1732 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1733 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1734 } else if (IS_CHERRYVIEW(dev)) {
1735 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1736 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1737 *pipe = PORT_TO_PIPE(tmp);
1738 } else {
1739 u32 trans_sel;
1740 u32 trans_dp;
1741 int i;
1742
1743 switch (intel_dp->output_reg) {
1744 case PCH_DP_B:
1745 trans_sel = TRANS_DP_PORT_SEL_B;
1746 break;
1747 case PCH_DP_C:
1748 trans_sel = TRANS_DP_PORT_SEL_C;
1749 break;
1750 case PCH_DP_D:
1751 trans_sel = TRANS_DP_PORT_SEL_D;
1752 break;
1753 default:
1754 return true;
1755 }
1756
055e393f 1757 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1758 trans_dp = I915_READ(TRANS_DP_CTL(i));
1759 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1760 *pipe = i;
1761 return true;
1762 }
1763 }
19d8fe15 1764
4a0833ec
DV		 1765 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1766 intel_dp->output_reg);
1767 }
d240f20f 1768
19d8fe15
DV		 1769 return true;
1770}
d240f20f 1771
045ac3b5
JB		 1772static void intel_dp_get_config(struct intel_encoder *encoder,
1773 struct intel_crtc_config *pipe_config)
1774{
1775 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1776 u32 tmp, flags = 0;
63000ef6
XZ		 1777 struct drm_device *dev = encoder->base.dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 enum port port = dp_to_dig_port(intel_dp)->port;
1780 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1781 int dotclock;
045ac3b5 1782
9ed109a7
DV		 1783 tmp = I915_READ(intel_dp->output_reg);
1784 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1785 pipe_config->has_audio = true;
1786
63000ef6 1787 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1788 if (tmp & DP_SYNC_HS_HIGH)
1789 flags |= DRM_MODE_FLAG_PHSYNC;
1790 else
1791 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1792
63000ef6
XZ		 1793 if (tmp & DP_SYNC_VS_HIGH)
1794 flags |= DRM_MODE_FLAG_PVSYNC;
1795 else
1796 flags |= DRM_MODE_FLAG_NVSYNC;
1797 } else {
1798 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1799 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1800 flags |= DRM_MODE_FLAG_PHSYNC;
1801 else
1802 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1803
63000ef6
XZ		 1804 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1805 flags |= DRM_MODE_FLAG_PVSYNC;
1806 else
1807 flags |= DRM_MODE_FLAG_NVSYNC;
1808 }
045ac3b5
JB		 1809
1810 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1811
eb14cb74
VS		 1812 pipe_config->has_dp_encoder = true;
1813
1814 intel_dp_get_m_n(crtc, pipe_config);
1815
18442d08 1816 if (port == PORT_A) {
f1f644dc
JB		 1817 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1818 pipe_config->port_clock = 162000;
1819 else
1820 pipe_config->port_clock = 270000;
1821 }
18442d08
VS		 1822
1823 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1824 &pipe_config->dp_m_n);
1825
1826 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1827 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1828
241bfc38 1829 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1830
c6cd2ee2
JN		 1831 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1832 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1833 /*
1834 * This is a big fat ugly hack.
1835 *
1836 * Some machines in UEFI boot mode provide us a VBT that has 18
1837 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1838 * unknown we fail to light up. Yet the same BIOS boots up with
1839 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1840 * max, not what it tells us to use.
1841 *
1842 * Note: This will still be broken if the eDP panel is not lit
1843 * up by the BIOS, and thus we can't get the mode at module
1844 * load.
1845 */
1846 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1847 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1848 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1849 }
045ac3b5
JB		 1850}
1851
34eb7579 1852static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1853{
34eb7579 1854 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1855}
1856
2b28bb1b
RV		 1857static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1858{
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860
18b5992c 1861 if (!HAS_PSR(dev))
2b28bb1b
RV		 1862 return false;
1863
18b5992c 1864 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1865}
1866
1867static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1868 struct edp_vsc_psr *vsc_psr)
1869{
1870 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1871 struct drm_device *dev = dig_port->base.base.dev;
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1874 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1875 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1876 uint32_t *data = (uint32_t *) vsc_psr;
1877 unsigned int i;
1878
1879 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1880 the video DIP being updated before program video DIP data buffer
1881 registers for DIP being updated. */
1882 I915_WRITE(ctl_reg, 0);
1883 POSTING_READ(ctl_reg);
1884
1885 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1886 if (i < sizeof(struct edp_vsc_psr))
1887 I915_WRITE(data_reg + i, *data++);
1888 else
1889 I915_WRITE(data_reg + i, 0);
1890 }
1891
1892 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1893 POSTING_READ(ctl_reg);
1894}
1895
1896static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1897{
1898 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 struct edp_vsc_psr psr_vsc;
1901
2b28bb1b
RV		 1902 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1903 memset(&psr_vsc, 0, sizeof(psr_vsc));
1904 psr_vsc.sdp_header.HB0 = 0;
1905 psr_vsc.sdp_header.HB1 = 0x7;
1906 psr_vsc.sdp_header.HB2 = 0x2;
1907 psr_vsc.sdp_header.HB3 = 0x8;
1908 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1909
1910 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1911 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1912 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1913}
1914
1915static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1916{
0e0ae652
RV		 1917 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1918 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1919 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1920 uint32_t aux_clock_divider;
2b28bb1b
RV		 1921 int precharge = 0x3;
1922 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1923 bool only_standby = false;
2b28bb1b 1924
ec5b01dd
DL		 1925 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1926
0e0ae652
RV		 1927 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1928 only_standby = true;
1929
2b28bb1b 1930 /* Enable PSR in sink */
0e0ae652 1931 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1932 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1933 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1934 else
9d1a1031
JN		 1935 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1936 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1937
1938 /* Setup AUX registers */
18b5992c
BW		 1939 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1940 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1941 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1942 DP_AUX_CH_CTL_TIME_OUT_400us |
1943 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1944 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1945 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1946}
1947
1948static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1949{
0e0ae652
RV		 1950 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1951 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1952 struct drm_i915_private *dev_priv = dev->dev_private;
1953 uint32_t max_sleep_time = 0x1f;
1954 uint32_t idle_frames = 1;
1955 uint32_t val = 0x0;
ed8546ac 1956 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1957 bool only_standby = false;
1958
1959 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1960 only_standby = true;
2b28bb1b 1961
0e0ae652 1962 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1963 val |= EDP_PSR_LINK_STANDBY;
1964 val |= EDP_PSR_TP2_TP3_TIME_0us;
1965 val |= EDP_PSR_TP1_TIME_0us;
1966 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1967 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1968 } else
1969 val |= EDP_PSR_LINK_DISABLE;
1970
18b5992c 1971 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1972 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1973 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1974 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1975 EDP_PSR_ENABLE);
1976}
1977
3f51e471
RV		 1978static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1979{
1980 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1981 struct drm_device *dev = dig_port->base.base.dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct drm_crtc *crtc = dig_port->base.base.crtc;
1984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1985
f0355c4a 1986 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1987 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1988 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1989
a031d709
RV		 1990 dev_priv->psr.source_ok = false;
1991
9ca15301 1992 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1993 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1994 return false;
1995 }
1996
d330a953 1997 if (!i915.enable_psr) {
105b7c11 1998 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1999 return false;
2000 }
2001
4c8c7000
RV		 2002 /* Below limitations aren't valid for Broadwell */
2003 if (IS_BROADWELL(dev))
2004 goto out;
2005
3f51e471
RV		 2006 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2007 S3D_ENABLE) {
2008 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2009 return false;
2010 }
2011
ca73b4f0 2012 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2013 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2014 return false;
2015 }
2016
4c8c7000 2017 out:
a031d709 2018 dev_priv->psr.source_ok = true;
3f51e471
RV		 2019 return true;
2020}
2021
3d739d92 2022static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2023{
7c8f8a70
RV		 2024 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2025 struct drm_device *dev = intel_dig_port->base.base.dev;
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2027
3638379c
DV		 2028 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2029 WARN_ON(dev_priv->psr.active);
f0355c4a 2030 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2031
2b28bb1b
RV		 2032 /* Enable PSR on the panel */
2033 intel_edp_psr_enable_sink(intel_dp);
2034
2035 /* Enable PSR on the host */
2036 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2037
7c8f8a70 2038 dev_priv->psr.active = true;
2b28bb1b
RV		 2039}
2040
3d739d92
RV		 2041void intel_edp_psr_enable(struct intel_dp *intel_dp)
2042{
2043 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2044 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2045
4704c573
RV		 2046 if (!HAS_PSR(dev)) {
2047 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2048 return;
2049 }
2050
34eb7579
RV		 2051 if (!is_edp_psr(intel_dp)) {
2052 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2053 return;
2054 }
2055
f0355c4a 2056 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2057 if (dev_priv->psr.enabled) {
2058 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2059 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2060 return;
2061 }
2062
9ca15301
DV		 2063 dev_priv->psr.busy_frontbuffer_bits = 0;
2064
16487254
RV		 2065 /* Setup PSR once */
2066 intel_edp_psr_setup(intel_dp);
2067
7c8f8a70 2068 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2069 dev_priv->psr.enabled = intel_dp;
f0355c4a 2070 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2071}
2072
2b28bb1b
RV		 2073void intel_edp_psr_disable(struct intel_dp *intel_dp)
2074{
2075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2076 struct drm_i915_private *dev_priv = dev->dev_private;
2077
f0355c4a
DV		 2078 mutex_lock(&dev_priv->psr.lock);
2079 if (!dev_priv->psr.enabled) {
2080 mutex_unlock(&dev_priv->psr.lock);
2081 return;
2082 }
2083
3638379c
DV		 2084 if (dev_priv->psr.active) {
2085 I915_WRITE(EDP_PSR_CTL(dev),
2086 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2087
2088 /* Wait till PSR is idle */
2089 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2090 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2091 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2092
3638379c
DV		 2093 dev_priv->psr.active = false;
2094 } else {
2095 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2096 }
7c8f8a70 2097
2807cf69 2098 dev_priv->psr.enabled = NULL;
f0355c4a 2099 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2100
2101 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2102}
2103
f02a326e 2104static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2105{
2106 struct drm_i915_private *dev_priv =
2107 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2108 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2109
f0355c4a
DV		 2110 mutex_lock(&dev_priv->psr.lock);
2111 intel_dp = dev_priv->psr.enabled;
2112
2807cf69 2113 if (!intel_dp)
f0355c4a 2114 goto unlock;
2807cf69 2115
9ca15301
DV		 2116 /*
2117 * The delayed work can race with an invalidate hence we need to
2118 * recheck. Since psr_flush first clears this and then reschedules we
2119 * won't ever miss a flush when bailing out here.
2120 */
2121 if (dev_priv->psr.busy_frontbuffer_bits)
2122 goto unlock;
2123
2124 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2125unlock:
2126 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2127}
2128
9ca15301 2129static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2130{
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132
3638379c
DV		 2133 if (dev_priv->psr.active) {
2134 u32 val = I915_READ(EDP_PSR_CTL(dev));
2135
2136 WARN_ON(!(val & EDP_PSR_ENABLE));
2137
2138 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2139
2140 dev_priv->psr.active = false;
2141 }
7c8f8a70 2142
9ca15301
DV		 2143}
2144
2145void intel_edp_psr_invalidate(struct drm_device *dev,
2146 unsigned frontbuffer_bits)
2147{
2148 struct drm_i915_private *dev_priv = dev->dev_private;
2149 struct drm_crtc *crtc;
2150 enum pipe pipe;
2151
9ca15301
DV		 2152 mutex_lock(&dev_priv->psr.lock);
2153 if (!dev_priv->psr.enabled) {
2154 mutex_unlock(&dev_priv->psr.lock);
2155 return;
2156 }
2157
2158 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2159 pipe = to_intel_crtc(crtc)->pipe;
2160
2161 intel_edp_psr_do_exit(dev);
2162
2163 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2164
2165 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2166 mutex_unlock(&dev_priv->psr.lock);
2167}
2168
2169void intel_edp_psr_flush(struct drm_device *dev,
2170 unsigned frontbuffer_bits)
2171{
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct drm_crtc *crtc;
2174 enum pipe pipe;
2175
9ca15301
DV		 2176 mutex_lock(&dev_priv->psr.lock);
2177 if (!dev_priv->psr.enabled) {
2178 mutex_unlock(&dev_priv->psr.lock);
2179 return;
2180 }
2181
2182 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2183 pipe = to_intel_crtc(crtc)->pipe;
2184 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2185
2186 /*
2187 * On Haswell sprite plane updates don't result in a psr invalidating
2188 * signal in the hardware. Which means we need to manually fake this in
2189 * software for all flushes, not just when we've seen a preceding
2190 * invalidation through frontbuffer rendering.
2191 */
2192 if (IS_HASWELL(dev) &&
2193 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2194 intel_edp_psr_do_exit(dev);
2195
2196 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2197 schedule_delayed_work(&dev_priv->psr.work,
2198 msecs_to_jiffies(100));
f0355c4a 2199 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2200}
2201
2202void intel_edp_psr_init(struct drm_device *dev)
2203{
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2205
7c8f8a70 2206 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2207 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2208}
2209
e8cb4558 2210static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2211{
e8cb4558 2212 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2213 enum port port = dp_to_dig_port(intel_dp)->port;
2214 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2215
2216 /* Make sure the panel is off before trying to change the mode. But also
2217 * ensure that we have vdd while we switch off the panel. */
24f3e092 2218 intel_edp_panel_vdd_on(intel_dp);
4be73780 2219 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2220 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2221 intel_edp_panel_off(intel_dp);
3739850b
DV		 2222
2223 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2224 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2225 intel_dp_link_down(intel_dp);
d240f20f
JB		 2226}
2227
49277c31 2228static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2229{
2bd2ad64 2230 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2231 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2232
49277c31
VS		 2233 if (port != PORT_A)
2234 return;
2235
2236 intel_dp_link_down(intel_dp);
2237 ironlake_edp_pll_off(intel_dp);
2238}
2239
2240static void vlv_post_disable_dp(struct intel_encoder *encoder)
2241{
2242 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2243
2244 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2245}
2246
580d3811
VS		 2247static void chv_post_disable_dp(struct intel_encoder *encoder)
2248{
2249 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2250 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2251 struct drm_device *dev = encoder->base.dev;
2252 struct drm_i915_private *dev_priv = dev->dev_private;
2253 struct intel_crtc *intel_crtc =
2254 to_intel_crtc(encoder->base.crtc);
2255 enum dpio_channel ch = vlv_dport_to_channel(dport);
2256 enum pipe pipe = intel_crtc->pipe;
2257 u32 val;
2258
2259 intel_dp_link_down(intel_dp);
2260
2261 mutex_lock(&dev_priv->dpio_lock);
2262
2263 /* Propagate soft reset to data lane reset */
97fd4d5c 2264 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2265 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2266 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2267
97fd4d5c
VS		 2268 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2269 val |= CHV_PCS_REQ_SOFTRESET_EN;
2270 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2271
2272 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2273 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2274 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2275
2276 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2277 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2278 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2279
2280 mutex_unlock(&dev_priv->dpio_lock);
2281}
2282
e8cb4558 2283static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2284{
e8cb4558
DV		 2285 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2286 struct drm_device *dev = encoder->base.dev;
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2289
0c33d8d7
DV		 2290 if (WARN_ON(dp_reg & DP_PORT_EN))
2291 return;
5d613501 2292
24f3e092 2293 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2294 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2295 intel_dp_start_link_train(intel_dp);
4be73780 2296 intel_edp_panel_on(intel_dp);
1e0560e0 2297 intel_edp_panel_vdd_off(intel_dp, true);
33a34e4e 2298 intel_dp_complete_link_train(intel_dp);
3ab9c637 2299 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2300}
89b667f8 2301
ecff4f3b
JN		 2302static void g4x_enable_dp(struct intel_encoder *encoder)
2303{
828f5c6e
JN		 2304 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2305
ecff4f3b 2306 intel_enable_dp(encoder);
4be73780 2307 intel_edp_backlight_on(intel_dp);
ab1f90f9 2308}
89b667f8 2309
ab1f90f9
JN		 2310static void vlv_enable_dp(struct intel_encoder *encoder)
2311{
828f5c6e
JN		 2312 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2313
4be73780 2314 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2315}
2316
ecff4f3b 2317static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2318{
2319 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2320 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2321
8ac33ed3
DV		 2322 intel_dp_prepare(encoder);
2323
d41f1efb
DV		 2324 /* Only ilk+ has port A */
2325 if (dport->port == PORT_A) {
2326 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2327 ironlake_edp_pll_on(intel_dp);
d41f1efb 2328 }
ab1f90f9
JN		 2329}
2330
a4a5d2f8
VS		 2331static void vlv_steal_power_sequencer(struct drm_device *dev,
2332 enum pipe pipe)
2333{
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_encoder *encoder;
2336
2337 lockdep_assert_held(&dev_priv->pps_mutex);
2338
2339 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2340 base.head) {
2341 struct intel_dp *intel_dp;
2342
2343 if (encoder->type != INTEL_OUTPUT_EDP)
2344 continue;
2345
2346 intel_dp = enc_to_intel_dp(&encoder->base);
2347
2348 if (intel_dp->pps_pipe != pipe)
2349 continue;
2350
2351 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2352 pipe_name(pipe),
2353 port_name(dp_to_dig_port(intel_dp)->port));
2354
2355 /* make sure vdd is off before we steal it */
2356 edp_panel_vdd_off_sync(intel_dp);
2357
2358 intel_dp->pps_pipe = INVALID_PIPE;
2359 }
2360}
2361
2362static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2363{
2364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2365 struct intel_encoder *encoder = &intel_dig_port->base;
2366 struct drm_device *dev = encoder->base.dev;
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2369 struct edp_power_seq power_seq;
2370
2371 lockdep_assert_held(&dev_priv->pps_mutex);
2372
2373 if (intel_dp->pps_pipe == crtc->pipe)
2374 return;
2375
2376 /*
2377 * If another power sequencer was being used on this
2378 * port previously make sure to turn off vdd there while
2379 * we still have control of it.
2380 */
2381 if (intel_dp->pps_pipe != INVALID_PIPE)
2382 edp_panel_vdd_off_sync(intel_dp);
2383
2384 /*
2385 * We may be stealing the power
2386 * sequencer from another port.
2387 */
2388 vlv_steal_power_sequencer(dev, crtc->pipe);
2389
2390 /* now it's all ours */
2391 intel_dp->pps_pipe = crtc->pipe;
2392
2393 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2394 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2395
2396 /* init power sequencer on this pipe and port */
2397 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2398 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2399 &power_seq);
2400}
2401
ab1f90f9 2402static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2403{
2bd2ad64 2404 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2405 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2406 struct drm_device *dev = encoder->base.dev;
89b667f8 2407 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2408 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2409 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2410 int pipe = intel_crtc->pipe;
2411 u32 val;
a4fc5ed6 2412
ab1f90f9 2413 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2414
ab3c759a 2415 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2416 val = 0;
2417 if (pipe)
2418 val |= (1<<21);
2419 else
2420 val &= ~(1<<21);
2421 val |= 0x001000c4;
ab3c759a
CML		 2422 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2423 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2424 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2425
ab1f90f9
JN		 2426 mutex_unlock(&dev_priv->dpio_lock);
2427
2cac613b 2428 if (is_edp(intel_dp)) {
e39b999a 2429 mutex_lock(&dev_priv->pps_mutex);
a4a5d2f8 2430 vlv_init_panel_power_sequencer(intel_dp);
e39b999a 2431 mutex_unlock(&dev_priv->pps_mutex);
2cac613b 2432 }
bf13e81b 2433
ab1f90f9
JN		 2434 intel_enable_dp(encoder);
2435
e4607fcf 2436 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2437}
2438
ecff4f3b 2439static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2440{
2441 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2442 struct drm_device *dev = encoder->base.dev;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2444 struct intel_crtc *intel_crtc =
2445 to_intel_crtc(encoder->base.crtc);
e4607fcf 2446 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2447 int pipe = intel_crtc->pipe;
89b667f8 2448
8ac33ed3
DV		 2449 intel_dp_prepare(encoder);
2450
89b667f8 2451 /* Program Tx lane resets to default */
0980a60f 2452 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2453 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2454 DPIO_PCS_TX_LANE2_RESET |
2455 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2456 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2457 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2458 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2459 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2460 DPIO_PCS_CLK_SOFT_RESET);
2461
2462 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2463 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2464 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2465 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2466 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2467}
2468
e4a1d846
CML		 2469static void chv_pre_enable_dp(struct intel_encoder *encoder)
2470{
2471 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2472 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2473 struct drm_device *dev = encoder->base.dev;
2474 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2475 struct intel_crtc *intel_crtc =
2476 to_intel_crtc(encoder->base.crtc);
2477 enum dpio_channel ch = vlv_dport_to_channel(dport);
2478 int pipe = intel_crtc->pipe;
2479 int data, i;
949c1d43 2480 u32 val;
e4a1d846 2481
e4a1d846 2482 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2483
2484 /* Deassert soft data lane reset*/
97fd4d5c 2485 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2486 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2487 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2488
2489 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2490 val |= CHV_PCS_REQ_SOFTRESET_EN;
2491 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2492
2493 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2494 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2495 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2496
97fd4d5c 2497 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2498 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2499 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2500
2501 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2502 for (i = 0; i < 4; i++) {
2503 /* Set the latency optimal bit */
2504 data = (i == 1) ? 0x0 : 0x6;
2505 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2506 data << DPIO_FRC_LATENCY_SHFIT);
2507
2508 /* Set the upar bit */
2509 data = (i == 1) ? 0x0 : 0x1;
2510 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2511 data << DPIO_UPAR_SHIFT);
2512 }
2513
2514 /* Data lane stagger programming */
2515 /* FIXME: Fix up value only after power analysis */
2516
2517 mutex_unlock(&dev_priv->dpio_lock);
2518
2519 if (is_edp(intel_dp)) {
e39b999a 2520 mutex_lock(&dev_priv->pps_mutex);
a4a5d2f8 2521 vlv_init_panel_power_sequencer(intel_dp);
e39b999a 2522 mutex_unlock(&dev_priv->pps_mutex);
e4a1d846
CML		 2523 }
2524
2525 intel_enable_dp(encoder);
2526
2527 vlv_wait_port_ready(dev_priv, dport);
2528}
2529
9197c88b
VS		 2530static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2531{
2532 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2533 struct drm_device *dev = encoder->base.dev;
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535 struct intel_crtc *intel_crtc =
2536 to_intel_crtc(encoder->base.crtc);
2537 enum dpio_channel ch = vlv_dport_to_channel(dport);
2538 enum pipe pipe = intel_crtc->pipe;
2539 u32 val;
2540
625695f8
VS		 2541 intel_dp_prepare(encoder);
2542
9197c88b
VS		 2543 mutex_lock(&dev_priv->dpio_lock);
2544
b9e5ac3c
VS		 2545 /* program left/right clock distribution */
2546 if (pipe != PIPE_B) {
2547 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2548 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2549 if (ch == DPIO_CH0)
2550 val |= CHV_BUFLEFTENA1_FORCE;
2551 if (ch == DPIO_CH1)
2552 val |= CHV_BUFRIGHTENA1_FORCE;
2553 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2554 } else {
2555 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2556 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2557 if (ch == DPIO_CH0)
2558 val |= CHV_BUFLEFTENA2_FORCE;
2559 if (ch == DPIO_CH1)
2560 val |= CHV_BUFRIGHTENA2_FORCE;
2561 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2562 }
2563
9197c88b
VS		 2564 /* program clock channel usage */
2565 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2566 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2567 if (pipe != PIPE_B)
2568 val &= ~CHV_PCS_USEDCLKCHANNEL;
2569 else
2570 val |= CHV_PCS_USEDCLKCHANNEL;
2571 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2572
2573 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2574 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2575 if (pipe != PIPE_B)
2576 val &= ~CHV_PCS_USEDCLKCHANNEL;
2577 else
2578 val |= CHV_PCS_USEDCLKCHANNEL;
2579 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2580
2581 /*
2582 * This a a bit weird since generally CL
2583 * matches the pipe, but here we need to
2584 * pick the CL based on the port.
2585 */
2586 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2587 if (pipe != PIPE_B)
2588 val &= ~CHV_CMN_USEDCLKCHANNEL;
2589 else
2590 val |= CHV_CMN_USEDCLKCHANNEL;
2591 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2592
2593 mutex_unlock(&dev_priv->dpio_lock);
2594}
2595
a4fc5ed6 2596/*
df0c237d
JB		 2597 * Native read with retry for link status and receiver capability reads for
2598 * cases where the sink may still be asleep.
9d1a1031
JN		 2599 *
2600 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2601 * supposed to retry 3 times per the spec.
a4fc5ed6 2602 */
9d1a1031
JN		 2603static ssize_t
2604intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2605 void *buffer, size_t size)
a4fc5ed6 2606{
9d1a1031
JN		 2607 ssize_t ret;
2608 int i;
61da5fab 2609
61da5fab 2610 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2611 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2612 if (ret == size)
2613 return ret;
61da5fab
JB		 2614 msleep(1);
2615 }
a4fc5ed6 2616
9d1a1031 2617 return ret;
a4fc5ed6
KP		 2618}
2619
2620/*
2621 * Fetch AUX CH registers 0x202 - 0x207 which contain
2622 * link status information
2623 */
2624static bool
93f62dad 2625intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2626{
9d1a1031
JN		 2627 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2628 DP_LANE0_1_STATUS,
2629 link_status,
2630 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2631}
2632
1100244e 2633/* These are source-specific values. */
a4fc5ed6 2634static uint8_t
1a2eb460 2635intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2636{
30add22d 2637 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2638 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2639
9576c27f 2640 if (IS_VALLEYVIEW(dev))
bd60018a 2641 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2642 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2643 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2644 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2645 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2646 else
bd60018a 2647 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2648}
2649
2650static uint8_t
2651intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2652{
30add22d 2653 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2654 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2655
9576c27f 2656 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2657 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2658 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2659 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2660 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2661 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2662 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2663 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2664 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2665 default:
bd60018a 2666 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2667 }
e2fa6fba
P		 2668 } else if (IS_VALLEYVIEW(dev)) {
2669 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2670 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2671 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2672 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2673 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2674 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2675 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2676 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2677 default:
bd60018a 2678 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2679 }
bc7d38a4 2680 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2681 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2682 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2683 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2684 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2685 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2686 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2687 default:
bd60018a 2688 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2689 }
2690 } else {
2691 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2692 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2693 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2694 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2695 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2696 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2697 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2698 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2699 default:
bd60018a 2700 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2701 }
a4fc5ed6
KP		 2702 }
2703}
2704
e2fa6fba
P		 2705static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2706{
2707 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2708 struct drm_i915_private *dev_priv = dev->dev_private;
2709 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2710 struct intel_crtc *intel_crtc =
2711 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2712 unsigned long demph_reg_value, preemph_reg_value,
2713 uniqtranscale_reg_value;
2714 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2715 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2716 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2717
2718 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2719 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2720 preemph_reg_value = 0x0004000;
2721 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2722 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2723 demph_reg_value = 0x2B405555;
2724 uniqtranscale_reg_value = 0x552AB83A;
2725 break;
bd60018a 2726 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2727 demph_reg_value = 0x2B404040;
2728 uniqtranscale_reg_value = 0x5548B83A;
2729 break;
bd60018a 2730 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2731 demph_reg_value = 0x2B245555;
2732 uniqtranscale_reg_value = 0x5560B83A;
2733 break;
bd60018a 2734 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2735 demph_reg_value = 0x2B405555;
2736 uniqtranscale_reg_value = 0x5598DA3A;
2737 break;
2738 default:
2739 return 0;
2740 }
2741 break;
bd60018a 2742 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2743 preemph_reg_value = 0x0002000;
2744 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2745 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2746 demph_reg_value = 0x2B404040;
2747 uniqtranscale_reg_value = 0x5552B83A;
2748 break;
bd60018a 2749 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2750 demph_reg_value = 0x2B404848;
2751 uniqtranscale_reg_value = 0x5580B83A;
2752 break;
bd60018a 2753 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2754 demph_reg_value = 0x2B404040;
2755 uniqtranscale_reg_value = 0x55ADDA3A;
2756 break;
2757 default:
2758 return 0;
2759 }
2760 break;
bd60018a 2761 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2762 preemph_reg_value = 0x0000000;
2763 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2764 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2765 demph_reg_value = 0x2B305555;
2766 uniqtranscale_reg_value = 0x5570B83A;
2767 break;
bd60018a 2768 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2769 demph_reg_value = 0x2B2B4040;
2770 uniqtranscale_reg_value = 0x55ADDA3A;
2771 break;
2772 default:
2773 return 0;
2774 }
2775 break;
bd60018a 2776 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2777 preemph_reg_value = 0x0006000;
2778 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2779 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2780 demph_reg_value = 0x1B405555;
2781 uniqtranscale_reg_value = 0x55ADDA3A;
2782 break;
2783 default:
2784 return 0;
2785 }
2786 break;
2787 default:
2788 return 0;
2789 }
2790
0980a60f 2791 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2792 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2793 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2794 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2795 uniqtranscale_reg_value);
ab3c759a
CML		 2796 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2797 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2798 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2799 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2800 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2801
2802 return 0;
2803}
2804
e4a1d846
CML		 2805static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2806{
2807 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2810 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2811 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2812 uint8_t train_set = intel_dp->train_set[0];
2813 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2814 enum pipe pipe = intel_crtc->pipe;
2815 int i;
e4a1d846
CML		 2816
2817 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2818 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2819 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2820 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2821 deemph_reg_value = 128;
2822 margin_reg_value = 52;
2823 break;
bd60018a 2824 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2825 deemph_reg_value = 128;
2826 margin_reg_value = 77;
2827 break;
bd60018a 2828 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2829 deemph_reg_value = 128;
2830 margin_reg_value = 102;
2831 break;
bd60018a 2832 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2833 deemph_reg_value = 128;
2834 margin_reg_value = 154;
2835 /* FIXME extra to set for 1200 */
2836 break;
2837 default:
2838 return 0;
2839 }
2840 break;
bd60018a 2841 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2842 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2843 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2844 deemph_reg_value = 85;
2845 margin_reg_value = 78;
2846 break;
bd60018a 2847 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2848 deemph_reg_value = 85;
2849 margin_reg_value = 116;
2850 break;
bd60018a 2851 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2852 deemph_reg_value = 85;
2853 margin_reg_value = 154;
2854 break;
2855 default:
2856 return 0;
2857 }
2858 break;
bd60018a 2859 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2860 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2861 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2862 deemph_reg_value = 64;
2863 margin_reg_value = 104;
2864 break;
bd60018a 2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2866 deemph_reg_value = 64;
2867 margin_reg_value = 154;
2868 break;
2869 default:
2870 return 0;
2871 }
2872 break;
bd60018a 2873 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2874 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2875 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2876 deemph_reg_value = 43;
2877 margin_reg_value = 154;
2878 break;
2879 default:
2880 return 0;
2881 }
2882 break;
2883 default:
2884 return 0;
2885 }
2886
2887 mutex_lock(&dev_priv->dpio_lock);
2888
2889 /* Clear calc init */
1966e59e
VS		 2890 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2891 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2892 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2893
2894 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2895 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2896 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2897
2898 /* Program swing deemph */
f72df8db
VS		 2899 for (i = 0; i < 4; i++) {
2900 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2901 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2902 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2903 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2904 }
e4a1d846
CML		 2905
2906 /* Program swing margin */
f72df8db
VS		 2907 for (i = 0; i < 4; i++) {
2908 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2909 val &= ~DPIO_SWING_MARGIN000_MASK;
2910 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2911 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2912 }
e4a1d846
CML		 2913
2914 /* Disable unique transition scale */
f72df8db
VS		 2915 for (i = 0; i < 4; i++) {
2916 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2917 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2918 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2919 }
e4a1d846
CML		 2920
2921 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 2922 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 2923 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 2924 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 2925
2926 /*
2927 * The document said it needs to set bit 27 for ch0 and bit 26
2928 * for ch1. Might be a typo in the doc.
2929 * For now, for this unique transition scale selection, set bit
2930 * 27 for ch0 and ch1.
2931 */
f72df8db
VS		 2932 for (i = 0; i < 4; i++) {
2933 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2934 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2935 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2936 }
e4a1d846 2937
f72df8db
VS		 2938 for (i = 0; i < 4; i++) {
2939 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2940 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2941 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2942 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2943 }
e4a1d846
CML		 2944 }
2945
2946 /* Start swing calculation */
1966e59e
VS		 2947 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2948 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2949 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2950
2951 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2952 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2953 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2954
2955 /* LRC Bypass */
2956 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2957 val |= DPIO_LRC_BYPASS;
2958 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2959
2960 mutex_unlock(&dev_priv->dpio_lock);
2961
2962 return 0;
2963}
2964
a4fc5ed6 2965static void
0301b3ac
JN		 2966intel_get_adjust_train(struct intel_dp *intel_dp,
2967 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2968{
2969 uint8_t v = 0;
2970 uint8_t p = 0;
2971 int lane;
1a2eb460
KP		 2972 uint8_t voltage_max;
2973 uint8_t preemph_max;
a4fc5ed6 2974
33a34e4e 2975 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2976 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2977 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2978
2979 if (this_v > v)
2980 v = this_v;
2981 if (this_p > p)
2982 p = this_p;
2983 }
2984
1a2eb460 2985 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2986 if (v >= voltage_max)
2987 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2988
1a2eb460
KP		 2989 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2990 if (p >= preemph_max)
2991 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2992
2993 for (lane = 0; lane < 4; lane++)
33a34e4e 2994 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2995}
2996
2997static uint32_t
f0a3424e 2998intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2999{
3cf2efb1 3000 uint32_t signal_levels = 0;
a4fc5ed6 3001
3cf2efb1 3002 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3004 default:
3005 signal_levels |= DP_VOLTAGE_0_4;
3006 break;
bd60018a 3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3008 signal_levels |= DP_VOLTAGE_0_6;
3009 break;
bd60018a 3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3011 signal_levels |= DP_VOLTAGE_0_8;
3012 break;
bd60018a 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3014 signal_levels |= DP_VOLTAGE_1_2;
3015 break;
3016 }
3cf2efb1 3017 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3018 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3019 default:
3020 signal_levels |= DP_PRE_EMPHASIS_0;
3021 break;
bd60018a 3022 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3023 signal_levels |= DP_PRE_EMPHASIS_3_5;
3024 break;
bd60018a 3025 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3026 signal_levels |= DP_PRE_EMPHASIS_6;
3027 break;
bd60018a 3028 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3029 signal_levels |= DP_PRE_EMPHASIS_9_5;
3030 break;
3031 }
3032 return signal_levels;
3033}
3034
e3421a18
ZW		 3035/* Gen6's DP voltage swing and pre-emphasis control */
3036static uint32_t
3037intel_gen6_edp_signal_levels(uint8_t train_set)
3038{
3c5a62b5
YL		 3039 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3040 DP_TRAIN_PRE_EMPHASIS_MASK);
3041 switch (signal_levels) {
bd60018a
SJ		 3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3044 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3046 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3049 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3052 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3055 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3056 default:
3c5a62b5
YL		 3057 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3058 "0x%x\n", signal_levels);
3059 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3060 }
3061}
3062
1a2eb460
KP		 3063/* Gen7's DP voltage swing and pre-emphasis control */
3064static uint32_t
3065intel_gen7_edp_signal_levels(uint8_t train_set)
3066{
3067 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3068 DP_TRAIN_PRE_EMPHASIS_MASK);
3069 switch (signal_levels) {
bd60018a 3070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3071 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3073 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3074 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3075 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3076
bd60018a 3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3078 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3079 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3080 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3081
bd60018a 3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3083 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3085 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3086
3087 default:
3088 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3089 "0x%x\n", signal_levels);
3090 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3091 }
3092}
3093
d6c0d722
PZ		 3094/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3095static uint32_t
f0a3424e 3096intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3097{
d6c0d722
PZ		 3098 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3099 DP_TRAIN_PRE_EMPHASIS_MASK);
3100 switch (signal_levels) {
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3102 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3104 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3106 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3108 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3109
bd60018a 3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3111 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3113 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3115 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3116
bd60018a 3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3118 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3120 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3121 default:
3122 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3123 "0x%x\n", signal_levels);
c5fe6a06 3124 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3125 }
a4fc5ed6
KP		 3126}
3127
f0a3424e
PZ		 3128/* Properly updates "DP" with the correct signal levels. */
3129static void
3130intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3131{
3132 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3133 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3134 struct drm_device *dev = intel_dig_port->base.base.dev;
3135 uint32_t signal_levels, mask;
3136 uint8_t train_set = intel_dp->train_set[0];
3137
9576c27f 3138 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3139 signal_levels = intel_hsw_signal_levels(train_set);
3140 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3141 } else if (IS_CHERRYVIEW(dev)) {
3142 signal_levels = intel_chv_signal_levels(intel_dp);
3143 mask = 0;
e2fa6fba
P		 3144 } else if (IS_VALLEYVIEW(dev)) {
3145 signal_levels = intel_vlv_signal_levels(intel_dp);
3146 mask = 0;
bc7d38a4 3147 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3148 signal_levels = intel_gen7_edp_signal_levels(train_set);
3149 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3150 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3151 signal_levels = intel_gen6_edp_signal_levels(train_set);
3152 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3153 } else {
3154 signal_levels = intel_gen4_signal_levels(train_set);
3155 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3156 }
3157
3158 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3159
3160 *DP = (*DP & ~mask) | signal_levels;
3161}
3162
a4fc5ed6 3163static bool
ea5b213a 3164intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3165 uint32_t *DP,
58e10eb9 3166 uint8_t dp_train_pat)
a4fc5ed6 3167{
174edf1f
PZ		 3168 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3169 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3170 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3171 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 3172 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3173 int ret, len;
a4fc5ed6 3174
22b8bf17 3175 if (HAS_DDI(dev)) {
3ab9c637 3176 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 3177
3178 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3179 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3180 else
3181 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3182
3183 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3184 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3185 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 3186 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3187
3188 break;
3189 case DP_TRAINING_PATTERN_1:
3190 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3191 break;
3192 case DP_TRAINING_PATTERN_2:
3193 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3194 break;
3195 case DP_TRAINING_PATTERN_3:
3196 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3197 break;
3198 }
174edf1f 3199 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 3200
bc7d38a4 3201 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 3202 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 3203
3204 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3205 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3206 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 3207 break;
3208 case DP_TRAINING_PATTERN_1:
70aff66c 3209 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 3210 break;
3211 case DP_TRAINING_PATTERN_2:
70aff66c 3212 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3213 break;
3214 case DP_TRAINING_PATTERN_3:
3215 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 3216 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3217 break;
3218 }
3219
3220 } else {
aad3d14d
VS		 3221 if (IS_CHERRYVIEW(dev))
3222 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3223 else
3224 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3225
3226 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3227 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3228 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3229 break;
3230 case DP_TRAINING_PATTERN_1:
70aff66c 3231 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3232 break;
3233 case DP_TRAINING_PATTERN_2:
70aff66c 3234 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3235 break;
3236 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3237 if (IS_CHERRYVIEW(dev)) {
3238 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3239 } else {
3240 DRM_ERROR("DP training pattern 3 not supported\n");
3241 *DP |= DP_LINK_TRAIN_PAT_2;
3242 }
47ea7542
PZ		 3243 break;
3244 }
3245 }
3246
70aff66c 3247 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3248 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3249
2cdfe6c8
JN		 3250 buf[0] = dp_train_pat;
3251 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3252 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3253 /* don't write DP_TRAINING_LANEx_SET on disable */
3254 len = 1;
3255 } else {
3256 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3257 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3258 len = intel_dp->lane_count + 1;
47ea7542 3259 }
a4fc5ed6 3260
9d1a1031
JN		 3261 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3262 buf, len);
2cdfe6c8
JN		 3263
3264 return ret == len;
a4fc5ed6
KP		 3265}
3266
70aff66c
JN		 3267static bool
3268intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3269 uint8_t dp_train_pat)
3270{
953d22e8 3271 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3272 intel_dp_set_signal_levels(intel_dp, DP);
3273 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3274}
3275
3276static bool
3277intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3278 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3279{
3280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3281 struct drm_device *dev = intel_dig_port->base.base.dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 int ret;
3284
3285 intel_get_adjust_train(intel_dp, link_status);
3286 intel_dp_set_signal_levels(intel_dp, DP);
3287
3288 I915_WRITE(intel_dp->output_reg, *DP);
3289 POSTING_READ(intel_dp->output_reg);
3290
9d1a1031
JN		 3291 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3292 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3293
3294 return ret == intel_dp->lane_count;
3295}
3296
3ab9c637
ID		 3297static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3298{
3299 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3300 struct drm_device *dev = intel_dig_port->base.base.dev;
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 enum port port = intel_dig_port->port;
3303 uint32_t val;
3304
3305 if (!HAS_DDI(dev))
3306 return;
3307
3308 val = I915_READ(DP_TP_CTL(port));
3309 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3310 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3311 I915_WRITE(DP_TP_CTL(port), val);
3312
3313 /*
3314 * On PORT_A we can have only eDP in SST mode. There the only reason
3315 * we need to set idle transmission mode is to work around a HW issue
3316 * where we enable the pipe while not in idle link-training mode.
3317 * In this case there is requirement to wait for a minimum number of
3318 * idle patterns to be sent.
3319 */
3320 if (port == PORT_A)
3321 return;
3322
3323 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3324 1))
3325 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3326}
3327
33a34e4e 3328/* Enable corresponding port and start training pattern 1 */
c19b0669 3329void
33a34e4e 3330intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3331{
da63a9f2 3332 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3333 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3334 int i;
3335 uint8_t voltage;
cdb0e95b 3336 int voltage_tries, loop_tries;
ea5b213a 3337 uint32_t DP = intel_dp->DP;
6aba5b6c 3338 uint8_t link_config[2];
a4fc5ed6 3339
affa9354 3340 if (HAS_DDI(dev))
c19b0669
PZ		 3341 intel_ddi_prepare_link_retrain(encoder);
3342
3cf2efb1 3343 /* Write the link configuration data */
6aba5b6c
JN		 3344 link_config[0] = intel_dp->link_bw;
3345 link_config[1] = intel_dp->lane_count;
3346 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3347 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3348 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3349
3350 link_config[0] = 0;
3351 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3352 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3353
3354 DP |= DP_PORT_EN;
1a2eb460 3355
70aff66c
JN		 3356 /* clock recovery */
3357 if (!intel_dp_reset_link_train(intel_dp, &DP,
3358 DP_TRAINING_PATTERN_1 |
3359 DP_LINK_SCRAMBLING_DISABLE)) {
3360 DRM_ERROR("failed to enable link training\n");
3361 return;
3362 }
3363
a4fc5ed6 3364 voltage = 0xff;
cdb0e95b
KP		 3365 voltage_tries = 0;
3366 loop_tries = 0;
a4fc5ed6 3367 for (;;) {
70aff66c 3368 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3369
a7c9655f 3370 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3371 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3372 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3373 break;
93f62dad 3374 }
a4fc5ed6 3375
01916270 3376 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3377 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3378 break;
3379 }
3380
3381 /* Check to see if we've tried the max voltage */
3382 for (i = 0; i < intel_dp->lane_count; i++)
3383 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3384 break;
3b4f819d 3385 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3386 ++loop_tries;
3387 if (loop_tries == 5) {
3def84b3 3388 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3389 break;
3390 }
70aff66c
JN		 3391 intel_dp_reset_link_train(intel_dp, &DP,
3392 DP_TRAINING_PATTERN_1 |
3393 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3394 voltage_tries = 0;
3395 continue;
3396 }
a4fc5ed6 3397
3cf2efb1 3398 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3399 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3400 ++voltage_tries;
b06fbda3 3401 if (voltage_tries == 5) {
3def84b3 3402 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3403 break;
3404 }
3405 } else
3406 voltage_tries = 0;
3407 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3408
70aff66c
JN		 3409 /* Update training set as requested by target */
3410 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3411 DRM_ERROR("failed to update link training\n");
3412 break;
3413 }
a4fc5ed6
KP		 3414 }
3415
33a34e4e
JB		 3416 intel_dp->DP = DP;
3417}
3418
c19b0669 3419void
33a34e4e
JB		 3420intel_dp_complete_link_train(struct intel_dp *intel_dp)
3421{
33a34e4e 3422 bool channel_eq = false;
37f80975 3423 int tries, cr_tries;
33a34e4e 3424 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3425 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3426
3427 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3428 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3429 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3430
a4fc5ed6 3431 /* channel equalization */
70aff66c 3432 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3433 training_pattern |
70aff66c
JN		 3434 DP_LINK_SCRAMBLING_DISABLE)) {
3435 DRM_ERROR("failed to start channel equalization\n");
3436 return;
3437 }
3438
a4fc5ed6 3439 tries = 0;
37f80975 3440 cr_tries = 0;
a4fc5ed6
KP		 3441 channel_eq = false;
3442 for (;;) {
70aff66c 3443 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3444
37f80975
JB		 3445 if (cr_tries > 5) {
3446 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3447 break;
3448 }
3449
a7c9655f 3450 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3451 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3452 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3453 break;
70aff66c 3454 }
a4fc5ed6 3455
37f80975 3456 /* Make sure clock is still ok */
01916270 3457 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3458 intel_dp_start_link_train(intel_dp);
70aff66c 3459 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3460 training_pattern |
70aff66c 3461 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3462 cr_tries++;
3463 continue;
3464 }
3465
1ffdff13 3466 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3467 channel_eq = true;
3468 break;
3469 }
a4fc5ed6 3470
37f80975
JB		 3471 /* Try 5 times, then try clock recovery if that fails */
3472 if (tries > 5) {
3473 intel_dp_link_down(intel_dp);
3474 intel_dp_start_link_train(intel_dp);
70aff66c 3475 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3476 training_pattern |
70aff66c 3477 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3478 tries = 0;
3479 cr_tries++;
3480 continue;
3481 }
a4fc5ed6 3482
70aff66c
JN		 3483 /* Update training set as requested by target */
3484 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3485 DRM_ERROR("failed to update link training\n");
3486 break;
3487 }
3cf2efb1 3488 ++tries;
869184a6 3489 }
3cf2efb1 3490
3ab9c637
ID		 3491 intel_dp_set_idle_link_train(intel_dp);
3492
3493 intel_dp->DP = DP;
3494
d6c0d722 3495 if (channel_eq)
07f42258 3496 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3497
3ab9c637
ID		 3498}
3499
3500void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3501{
70aff66c 3502 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3503 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3504}
3505
3506static void
ea5b213a 3507intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3508{
da63a9f2 3509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3510 enum port port = intel_dig_port->port;
da63a9f2 3511 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3512 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3513 struct intel_crtc *intel_crtc =
3514 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3515 uint32_t DP = intel_dp->DP;
a4fc5ed6 3516
bc76e320 3517 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3518 return;
3519
0c33d8d7 3520 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3521 return;
3522
28c97730 3523 DRM_DEBUG_KMS("\n");
32f9d658 3524
bc7d38a4 3525 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3526 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3527 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3528 } else {
aad3d14d
VS		 3529 if (IS_CHERRYVIEW(dev))
3530 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3531 else
3532 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3533 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3534 }
fe255d00 3535 POSTING_READ(intel_dp->output_reg);
5eb08b69 3536
493a7081 3537 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3538 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3539 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3540
5bddd17f
EA		 3541 /* Hardware workaround: leaving our transcoder select
3542 * set to transcoder B while it's off will prevent the
3543 * corresponding HDMI output on transcoder A.
3544 *
3545 * Combine this with another hardware workaround:
3546 * transcoder select bit can only be cleared while the
3547 * port is enabled.
3548 */
3549 DP &= ~DP_PIPEB_SELECT;
3550 I915_WRITE(intel_dp->output_reg, DP);
3551
3552 /* Changes to enable or select take place the vblank
3553 * after being written.
3554 */
ff50afe9
DV		 3555 if (WARN_ON(crtc == NULL)) {
3556 /* We should never try to disable a port without a crtc
3557 * attached. For paranoia keep the code around for a
3558 * bit. */
31acbcc4
CW		 3559 POSTING_READ(intel_dp->output_reg);
3560 msleep(50);
3561 } else
ab527efc 3562 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3563 }
3564
832afda6 3565 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3566 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3567 POSTING_READ(intel_dp->output_reg);
f01eca2e 3568 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3569}
3570
26d61aad
KP		 3571static bool
3572intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3573{
a031d709
RV		 3574 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3575 struct drm_device *dev = dig_port->base.base.dev;
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577
9d1a1031
JN		 3578 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3579 sizeof(intel_dp->dpcd)) < 0)
edb39244 3580 return false; /* aux transfer failed */
92fd8fd1 3581
a8e98153 3582 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3583
edb39244
AJ		 3584 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3585 return false; /* DPCD not present */
3586
2293bb5c
SK		 3587 /* Check if the panel supports PSR */
3588 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3589 if (is_edp(intel_dp)) {
9d1a1031
JN		 3590 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3591 intel_dp->psr_dpcd,
3592 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3593 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3594 dev_priv->psr.sink_support = true;
50003939 3595 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3596 }
50003939
JN		 3597 }
3598
06ea66b6
TP		 3599 /* Training Pattern 3 support */
3600 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3601 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3602 intel_dp->use_tps3 = true;
3603 DRM_DEBUG_KMS("Displayport TPS3 supported");
3604 } else
3605 intel_dp->use_tps3 = false;
3606
edb39244
AJ		 3607 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3608 DP_DWN_STRM_PORT_PRESENT))
3609 return true; /* native DP sink */
3610
3611 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3612 return true; /* no per-port downstream info */
3613
9d1a1031
JN		 3614 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3615 intel_dp->downstream_ports,
3616 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3617 return false; /* downstream port status fetch failed */
3618
3619 return true;
92fd8fd1
KP		 3620}
3621
0d198328
AJ		 3622static void
3623intel_dp_probe_oui(struct intel_dp *intel_dp)
3624{
3625 u8 buf[3];
3626
3627 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3628 return;
3629
24f3e092 3630 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3631
9d1a1031 3632 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3633 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3634 buf[0], buf[1], buf[2]);
3635
9d1a1031 3636 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3637 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3638 buf[0], buf[1], buf[2]);
351cfc34 3639
1e0560e0 3640 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3641}
3642
0e32b39c
DA		 3643static bool
3644intel_dp_probe_mst(struct intel_dp *intel_dp)
3645{
3646 u8 buf[1];
3647
3648 if (!intel_dp->can_mst)
3649 return false;
3650
3651 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3652 return false;
3653
d337a341 3654 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3655 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3656 if (buf[0] & DP_MST_CAP) {
3657 DRM_DEBUG_KMS("Sink is MST capable\n");
3658 intel_dp->is_mst = true;
3659 } else {
3660 DRM_DEBUG_KMS("Sink is not MST capable\n");
3661 intel_dp->is_mst = false;
3662 }
3663 }
1e0560e0 3664 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3665
3666 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3667 return intel_dp->is_mst;
3668}
3669
d2e216d0
RV		 3670int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3671{
3672 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3673 struct drm_device *dev = intel_dig_port->base.base.dev;
3674 struct intel_crtc *intel_crtc =
3675 to_intel_crtc(intel_dig_port->base.base.crtc);
3676 u8 buf[1];
3677
9d1a1031 3678 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3679 return -EAGAIN;
3680
3681 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3682 return -ENOTTY;
3683
9d1a1031
JN		 3684 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3685 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3686 return -EAGAIN;
3687
3688 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3689 intel_wait_for_vblank(dev, intel_crtc->pipe);
3690 intel_wait_for_vblank(dev, intel_crtc->pipe);
3691
9d1a1031 3692 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3693 return -EAGAIN;
3694
9d1a1031 3695 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3696 return 0;
3697}
3698
a60f0e38
JB		 3699static bool
3700intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3701{
9d1a1031
JN		 3702 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3703 DP_DEVICE_SERVICE_IRQ_VECTOR,
3704 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3705}
3706
0e32b39c
DA		 3707static bool
3708intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3709{
3710 int ret;
3711
3712 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3713 DP_SINK_COUNT_ESI,
3714 sink_irq_vector, 14);
3715 if (ret != 14)
3716 return false;
3717
3718 return true;
3719}
3720
a60f0e38
JB		 3721static void
3722intel_dp_handle_test_request(struct intel_dp *intel_dp)
3723{
3724 /* NAK by default */
9d1a1031 3725 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3726}
3727
0e32b39c
DA		 3728static int
3729intel_dp_check_mst_status(struct intel_dp *intel_dp)
3730{
3731 bool bret;
3732
3733 if (intel_dp->is_mst) {
3734 u8 esi[16] = { 0 };
3735 int ret = 0;
3736 int retry;
3737 bool handled;
3738 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3739go_again:
3740 if (bret == true) {
3741
3742 /* check link status - esi[10] = 0x200c */
3743 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3744 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3745 intel_dp_start_link_train(intel_dp);
3746 intel_dp_complete_link_train(intel_dp);
3747 intel_dp_stop_link_train(intel_dp);
3748 }
3749
3750 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3751 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3752
3753 if (handled) {
3754 for (retry = 0; retry < 3; retry++) {
3755 int wret;
3756 wret = drm_dp_dpcd_write(&intel_dp->aux,
3757 DP_SINK_COUNT_ESI+1,
3758 &esi[1], 3);
3759 if (wret == 3) {
3760 break;
3761 }
3762 }
3763
3764 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3765 if (bret == true) {
3766 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3767 goto go_again;
3768 }
3769 } else
3770 ret = 0;
3771
3772 return ret;
3773 } else {
3774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3775 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3776 intel_dp->is_mst = false;
3777 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3778 /* send a hotplug event */
3779 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3780 }
3781 }
3782 return -EINVAL;
3783}
3784
a4fc5ed6
KP		 3785/*
3786 * According to DP spec
3787 * 5.1.2:
3788 * 1. Read DPCD
3789 * 2. Configure link according to Receiver Capabilities
3790 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3791 * 4. Check link status on receipt of hot-plug interrupt
3792 */
00c09d70 3793void
ea5b213a 3794intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3795{
5b215bcf 3796 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3797 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3798 u8 sink_irq_vector;
93f62dad 3799 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3800
5b215bcf
DA		 3801 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3802
da63a9f2 3803 if (!intel_encoder->connectors_active)
d2b996ac 3804 return;
59cd09e1 3805
da63a9f2 3806 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3807 return;
3808
1a125d8a
ID		 3809 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3810 return;
3811
92fd8fd1 3812 /* Try to read receiver status if the link appears to be up */
93f62dad 3813 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3814 return;
3815 }
3816
92fd8fd1 3817 /* Now read the DPCD to see if it's actually running */
26d61aad 3818 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3819 return;
3820 }
3821
a60f0e38
JB		 3822 /* Try to read the source of the interrupt */
3823 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3824 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3825 /* Clear interrupt source */
9d1a1031
JN		 3826 drm_dp_dpcd_writeb(&intel_dp->aux,
3827 DP_DEVICE_SERVICE_IRQ_VECTOR,
3828 sink_irq_vector);
a60f0e38
JB		 3829
3830 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3831 intel_dp_handle_test_request(intel_dp);
3832 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3833 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3834 }
3835
1ffdff13 3836 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3837 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3838 intel_encoder->base.name);
33a34e4e
JB		 3839 intel_dp_start_link_train(intel_dp);
3840 intel_dp_complete_link_train(intel_dp);
3ab9c637 3841 intel_dp_stop_link_train(intel_dp);
33a34e4e 3842 }
a4fc5ed6 3843}
a4fc5ed6 3844
caf9ab24 3845/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3846static enum drm_connector_status
26d61aad 3847intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3848{
caf9ab24 3849 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3850 uint8_t type;
3851
3852 if (!intel_dp_get_dpcd(intel_dp))
3853 return connector_status_disconnected;
3854
3855 /* if there's no downstream port, we're done */
3856 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3857 return connector_status_connected;
caf9ab24
AJ		 3858
3859 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3860 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3861 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3862 uint8_t reg;
9d1a1031
JN		 3863
3864 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3865 &reg, 1) < 0)
caf9ab24 3866 return connector_status_unknown;
9d1a1031 3867
23235177
AJ		 3868 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3869 : connector_status_disconnected;
caf9ab24
AJ		 3870 }
3871
3872 /* If no HPD, poke DDC gently */
0b99836f 3873 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3874 return connector_status_connected;
caf9ab24
AJ		 3875
3876 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3877 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3878 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3879 if (type == DP_DS_PORT_TYPE_VGA ||
3880 type == DP_DS_PORT_TYPE_NON_EDID)
3881 return connector_status_unknown;
3882 } else {
3883 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3884 DP_DWN_STRM_PORT_TYPE_MASK;
3885 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3886 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3887 return connector_status_unknown;
3888 }
caf9ab24
AJ		 3889
3890 /* Anything else is out of spec, warn and ignore */
3891 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3892 return connector_status_disconnected;
71ba9000
AJ		 3893}
3894
d410b56d
CW		 3895static enum drm_connector_status
3896edp_detect(struct intel_dp *intel_dp)
3897{
3898 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3899 enum drm_connector_status status;
3900
3901 status = intel_panel_detect(dev);
3902 if (status == connector_status_unknown)
3903 status = connector_status_connected;
3904
3905 return status;
3906}
3907
5eb08b69 3908static enum drm_connector_status
a9756bb5 3909ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3910{
30add22d 3911 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3914
1b469639
DL		 3915 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3916 return connector_status_disconnected;
3917
26d61aad 3918 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3919}
3920
a4fc5ed6 3921static enum drm_connector_status
a9756bb5 3922g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3923{
30add22d 3924 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3925 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3926 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3927 uint32_t bit;
5eb08b69 3928
232a6ee9
TP		 3929 if (IS_VALLEYVIEW(dev)) {
3930 switch (intel_dig_port->port) {
3931 case PORT_B:
3932 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3933 break;
3934 case PORT_C:
3935 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3936 break;
3937 case PORT_D:
3938 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3939 break;
3940 default:
3941 return connector_status_unknown;
3942 }
3943 } else {
3944 switch (intel_dig_port->port) {
3945 case PORT_B:
3946 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3947 break;
3948 case PORT_C:
3949 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3950 break;
3951 case PORT_D:
3952 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3953 break;
3954 default:
3955 return connector_status_unknown;
3956 }
a4fc5ed6
KP		 3957 }
3958
10f76a38 3959 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3960 return connector_status_disconnected;
3961
26d61aad 3962 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3963}
3964
8c241fef 3965static struct edid *
beb60608 3966intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 3967{
beb60608 3968 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 3969
9cd300e0
JN		 3970 /* use cached edid if we have one */
3971 if (intel_connector->edid) {
9cd300e0
JN		 3972 /* invalid edid */
3973 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3974 return NULL;
3975
55e9edeb 3976 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 3977 } else
3978 return drm_get_edid(&intel_connector->base,
3979 &intel_dp->aux.ddc);
3980}
8c241fef 3981
beb60608
CW		 3982static void
3983intel_dp_set_edid(struct intel_dp *intel_dp)
3984{
3985 struct intel_connector *intel_connector = intel_dp->attached_connector;
3986 struct edid *edid;
3987
3988 edid = intel_dp_get_edid(intel_dp);
3989 intel_connector->detect_edid = edid;
3990
3991 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
3992 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
3993 else
3994 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 3995}
3996
beb60608
CW		 3997static void
3998intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 3999{
beb60608 4000 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4001
beb60608
CW		 4002 kfree(intel_connector->detect_edid);
4003 intel_connector->detect_edid = NULL;
9cd300e0 4004
beb60608
CW		 4005 intel_dp->has_audio = false;
4006}
d6f24d0f 4007
beb60608
CW		 4008static enum intel_display_power_domain
4009intel_dp_power_get(struct intel_dp *dp)
4010{
4011 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4012 enum intel_display_power_domain power_domain;
4013
4014 power_domain = intel_display_port_power_domain(encoder);
4015 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4016
4017 return power_domain;
4018}
4019
4020static void
4021intel_dp_power_put(struct intel_dp *dp,
4022 enum intel_display_power_domain power_domain)
4023{
4024 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4025 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4026}
4027
a9756bb5
ZW		 4028static enum drm_connector_status
4029intel_dp_detect(struct drm_connector *connector, bool force)
4030{
4031 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4032 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4033 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4034 struct drm_device *dev = connector->dev;
a9756bb5 4035 enum drm_connector_status status;
671dedd2 4036 enum intel_display_power_domain power_domain;
0e32b39c 4037 bool ret;
a9756bb5 4038
164c8598 4039 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4040 connector->base.id, connector->name);
beb60608 4041 intel_dp_unset_edid(intel_dp);
164c8598 4042
0e32b39c
DA		 4043 if (intel_dp->is_mst) {
4044 /* MST devices are disconnected from a monitor POV */
4045 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4046 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4047 return connector_status_disconnected;
0e32b39c
DA		 4048 }
4049
beb60608 4050 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4051
d410b56d
CW		 4052 /* Can't disconnect eDP, but you can close the lid... */
4053 if (is_edp(intel_dp))
4054 status = edp_detect(intel_dp);
4055 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4056 status = ironlake_dp_detect(intel_dp);
4057 else
4058 status = g4x_dp_detect(intel_dp);
4059 if (status != connector_status_connected)
c8c8fb33 4060 goto out;
a9756bb5 4061
0d198328
AJ		 4062 intel_dp_probe_oui(intel_dp);
4063
0e32b39c
DA		 4064 ret = intel_dp_probe_mst(intel_dp);
4065 if (ret) {
4066 /* if we are in MST mode then this connector
4067 won't appear connected or have anything with EDID on it */
4068 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4069 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4070 status = connector_status_disconnected;
4071 goto out;
4072 }
4073
beb60608 4074 intel_dp_set_edid(intel_dp);
a9756bb5 4075
d63885da
PZ		 4076 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4077 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4078 status = connector_status_connected;
4079
4080out:
beb60608 4081 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4082 return status;
a4fc5ed6
KP		 4083}
4084
beb60608
CW		 4085static void
4086intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4087{
df0e9248 4088 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4089 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4090 enum intel_display_power_domain power_domain;
a4fc5ed6 4091
beb60608
CW		 4092 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4093 connector->base.id, connector->name);
4094 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4095
beb60608
CW		 4096 if (connector->status != connector_status_connected)
4097 return;
671dedd2 4098
beb60608
CW		 4099 power_domain = intel_dp_power_get(intel_dp);
4100
4101 intel_dp_set_edid(intel_dp);
4102
4103 intel_dp_power_put(intel_dp, power_domain);
4104
4105 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4106 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4107}
4108
4109static int intel_dp_get_modes(struct drm_connector *connector)
4110{
4111 struct intel_connector *intel_connector = to_intel_connector(connector);
4112 struct edid *edid;
4113
4114 edid = intel_connector->detect_edid;
4115 if (edid) {
4116 int ret = intel_connector_update_modes(connector, edid);
4117 if (ret)
4118 return ret;
4119 }
32f9d658 4120
f8779fda 4121 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4122 if (is_edp(intel_attached_dp(connector)) &&
4123 intel_connector->panel.fixed_mode) {
f8779fda 4124 struct drm_display_mode *mode;
beb60608
CW		 4125
4126 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4127 intel_connector->panel.fixed_mode);
f8779fda 4128 if (mode) {
32f9d658
ZW		 4129 drm_mode_probed_add(connector, mode);
4130 return 1;
4131 }
4132 }
beb60608 4133
32f9d658 4134 return 0;
a4fc5ed6
KP		 4135}
4136
1aad7ac0
CW		 4137static bool
4138intel_dp_detect_audio(struct drm_connector *connector)
4139{
1aad7ac0 4140 bool has_audio = false;
beb60608 4141 struct edid *edid;
1aad7ac0 4142
beb60608
CW		 4143 edid = to_intel_connector(connector)->detect_edid;
4144 if (edid)
1aad7ac0 4145 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4146
1aad7ac0
CW		 4147 return has_audio;
4148}
4149
f684960e
CW		 4150static int
4151intel_dp_set_property(struct drm_connector *connector,
4152 struct drm_property *property,
4153 uint64_t val)
4154{
e953fd7b 4155 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4156 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4157 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4158 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4159 int ret;
4160
662595df 4161 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4162 if (ret)
4163 return ret;
4164
3f43c48d 4165 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4166 int i = val;
4167 bool has_audio;
4168
4169 if (i == intel_dp->force_audio)
f684960e
CW		 4170 return 0;
4171
1aad7ac0 4172 intel_dp->force_audio = i;
f684960e 4173
c3e5f67b 4174 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4175 has_audio = intel_dp_detect_audio(connector);
4176 else
c3e5f67b 4177 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4178
4179 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4180 return 0;
4181
1aad7ac0 4182 intel_dp->has_audio = has_audio;
f684960e
CW		 4183 goto done;
4184 }
4185
e953fd7b 4186 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4187 bool old_auto = intel_dp->color_range_auto;
4188 uint32_t old_range = intel_dp->color_range;
4189
55bc60db
VS		 4190 switch (val) {
4191 case INTEL_BROADCAST_RGB_AUTO:
4192 intel_dp->color_range_auto = true;
4193 break;
4194 case INTEL_BROADCAST_RGB_FULL:
4195 intel_dp->color_range_auto = false;
4196 intel_dp->color_range = 0;
4197 break;
4198 case INTEL_BROADCAST_RGB_LIMITED:
4199 intel_dp->color_range_auto = false;
4200 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4201 break;
4202 default:
4203 return -EINVAL;
4204 }
ae4edb80
DV		 4205
4206 if (old_auto == intel_dp->color_range_auto &&
4207 old_range == intel_dp->color_range)
4208 return 0;
4209
e953fd7b
CW		 4210 goto done;
4211 }
4212
53b41837
YN		 4213 if (is_edp(intel_dp) &&
4214 property == connector->dev->mode_config.scaling_mode_property) {
4215 if (val == DRM_MODE_SCALE_NONE) {
4216 DRM_DEBUG_KMS("no scaling not supported\n");
4217 return -EINVAL;
4218 }
4219
4220 if (intel_connector->panel.fitting_mode == val) {
4221 /* the eDP scaling property is not changed */
4222 return 0;
4223 }
4224 intel_connector->panel.fitting_mode = val;
4225
4226 goto done;
4227 }
4228
f684960e
CW		 4229 return -EINVAL;
4230
4231done:
c0c36b94
CW		 4232 if (intel_encoder->base.crtc)
4233 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4234
4235 return 0;
4236}
4237
a4fc5ed6 4238static void
73845adf 4239intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4240{
1d508706 4241 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4242
beb60608
CW		 4243 intel_dp_unset_edid(intel_attached_dp(connector));
4244
9cd300e0
JN		 4245 if (!IS_ERR_OR_NULL(intel_connector->edid))
4246 kfree(intel_connector->edid);
4247
acd8db10
PZ		 4248 /* Can't call is_edp() since the encoder may have been destroyed
4249 * already. */
4250 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4251 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4252
a4fc5ed6 4253 drm_connector_cleanup(connector);
55f78c43 4254 kfree(connector);
a4fc5ed6
KP		 4255}
4256
00c09d70 4257void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4258{
da63a9f2
PZ		 4259 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4260 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
e39b999a 4262 struct drm_i915_private *dev_priv = dev->dev_private;
24d05927 4263
4f71d0cb 4264 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4265 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4266 drm_encoder_cleanup(encoder);
bd943159
KP		 4267 if (is_edp(intel_dp)) {
4268 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
e39b999a 4269 mutex_lock(&dev_priv->pps_mutex);
4be73780 4270 edp_panel_vdd_off_sync(intel_dp);
e39b999a 4271 mutex_unlock(&dev_priv->pps_mutex);
01527b31
CT		 4272 if (intel_dp->edp_notifier.notifier_call) {
4273 unregister_reboot_notifier(&intel_dp->edp_notifier);
4274 intel_dp->edp_notifier.notifier_call = NULL;
4275 }
bd943159 4276 }
da63a9f2 4277 kfree(intel_dig_port);
24d05927
DV		 4278}
4279
07f9cd0b
ID		 4280static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4281{
4282 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
e39b999a
VS		 4283 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4284 struct drm_i915_private *dev_priv = dev->dev_private;
07f9cd0b
ID		 4285
4286 if (!is_edp(intel_dp))
4287 return;
4288
e39b999a 4289 mutex_lock(&dev_priv->pps_mutex);
07f9cd0b 4290 edp_panel_vdd_off_sync(intel_dp);
e39b999a 4291 mutex_unlock(&dev_priv->pps_mutex);
07f9cd0b
ID		 4292}
4293
6d93c0c4
ID		 4294static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4295{
4296 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4297}
4298
a4fc5ed6 4299static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4300 .dpms = intel_connector_dpms,
a4fc5ed6 4301 .detect = intel_dp_detect,
beb60608 4302 .force = intel_dp_force,
a4fc5ed6 4303 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4304 .set_property = intel_dp_set_property,
73845adf 4305 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4306};
4307
4308static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4309 .get_modes = intel_dp_get_modes,
4310 .mode_valid = intel_dp_mode_valid,
df0e9248 4311 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4312};
4313
a4fc5ed6 4314static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4315 .reset = intel_dp_encoder_reset,
24d05927 4316 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4317};
4318
0e32b39c 4319void
21d40d37 4320intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4321{
0e32b39c 4322 return;
c8110e52 4323}
6207937d 4324
13cf5504
DA		 4325bool
4326intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4327{
4328 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4329 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4330 struct drm_device *dev = intel_dig_port->base.base.dev;
4331 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4332 enum intel_display_power_domain power_domain;
4333 bool ret = true;
4334
0e32b39c
DA		 4335 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4336 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4337
26fbb774
VS		 4338 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4339 port_name(intel_dig_port->port),
0e32b39c 4340 long_hpd ? "long" : "short");
13cf5504 4341
1c767b33
ID		 4342 power_domain = intel_display_port_power_domain(intel_encoder);
4343 intel_display_power_get(dev_priv, power_domain);
4344
0e32b39c
DA		 4345 if (long_hpd) {
4346 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4347 goto mst_fail;
4348
4349 if (!intel_dp_get_dpcd(intel_dp)) {
4350 goto mst_fail;
4351 }
4352
4353 intel_dp_probe_oui(intel_dp);
4354
4355 if (!intel_dp_probe_mst(intel_dp))
4356 goto mst_fail;
4357
4358 } else {
4359 if (intel_dp->is_mst) {
1c767b33 4360 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4361 goto mst_fail;
4362 }
4363
4364 if (!intel_dp->is_mst) {
4365 /*
4366 * we'll check the link status via the normal hot plug path later -
4367 * but for short hpds we should check it now
4368 */
5b215bcf 4369 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4370 intel_dp_check_link_status(intel_dp);
5b215bcf 4371 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4372 }
4373 }
1c767b33
ID		 4374 ret = false;
4375 goto put_power;
0e32b39c
DA		 4376mst_fail:
4377 /* if we were in MST mode, and device is not there get out of MST mode */
4378 if (intel_dp->is_mst) {
4379 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4380 intel_dp->is_mst = false;
4381 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4382 }
1c767b33
ID		 4383put_power:
4384 intel_display_power_put(dev_priv, power_domain);
4385
4386 return ret;
13cf5504
DA		 4387}
4388
e3421a18
ZW		 4389/* Return which DP Port should be selected for Transcoder DP control */
4390int
0206e353 4391intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4392{
4393 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4394 struct intel_encoder *intel_encoder;
4395 struct intel_dp *intel_dp;
e3421a18 4396
fa90ecef
PZ		 4397 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4398 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4399
fa90ecef
PZ		 4400 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4401 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4402 return intel_dp->output_reg;
e3421a18 4403 }
ea5b213a 4404
e3421a18
ZW		 4405 return -1;
4406}
4407
36e83a18 4408/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4409bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4410{
4411 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4412 union child_device_config *p_child;
36e83a18 4413 int i;
5d8a7752
VS		 4414 static const short port_mapping[] = {
4415 [PORT_B] = PORT_IDPB,
4416 [PORT_C] = PORT_IDPC,
4417 [PORT_D] = PORT_IDPD,
4418 };
36e83a18 4419
3b32a35b
VS		 4420 if (port == PORT_A)
4421 return true;
4422
41aa3448 4423 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4424 return false;
4425
41aa3448
RV		 4426 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4427 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4428
5d8a7752 4429 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4430 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4431 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4432 return true;
4433 }
4434 return false;
4435}
4436
0e32b39c 4437void
f684960e
CW		 4438intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4439{
53b41837
YN		 4440 struct intel_connector *intel_connector = to_intel_connector(connector);
4441
3f43c48d 4442 intel_attach_force_audio_property(connector);
e953fd7b 4443 intel_attach_broadcast_rgb_property(connector);
55bc60db 4444 intel_dp->color_range_auto = true;
53b41837
YN		 4445
4446 if (is_edp(intel_dp)) {
4447 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4448 drm_object_attach_property(
4449 &connector->base,
53b41837 4450 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4451 DRM_MODE_SCALE_ASPECT);
4452 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4453 }
f684960e
CW		 4454}
4455
dada1a9f
ID		 4456static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4457{
4458 intel_dp->last_power_cycle = jiffies;
4459 intel_dp->last_power_on = jiffies;
4460 intel_dp->last_backlight_off = jiffies;
4461}
4462
67a54566
DV		 4463static void
4464intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4465 struct intel_dp *intel_dp,
4466 struct edp_power_seq *out)
67a54566
DV		 4467{
4468 struct drm_i915_private *dev_priv = dev->dev_private;
4469 struct edp_power_seq cur, vbt, spec, final;
4470 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4471 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4472
e39b999a
VS		 4473 lockdep_assert_held(&dev_priv->pps_mutex);
4474
453c5420 4475 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4476 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4477 pp_on_reg = PCH_PP_ON_DELAYS;
4478 pp_off_reg = PCH_PP_OFF_DELAYS;
4479 pp_div_reg = PCH_PP_DIVISOR;
4480 } else {
bf13e81b
JN		 4481 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4482
4483 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4484 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4485 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4486 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4487 }
67a54566
DV		 4488
4489 /* Workaround: Need to write PP_CONTROL with the unlock key as
4490 * the very first thing. */
453c5420 4491 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4492 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4493
453c5420
JB		 4494 pp_on = I915_READ(pp_on_reg);
4495 pp_off = I915_READ(pp_off_reg);
4496 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4497
4498 /* Pull timing values out of registers */
4499 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4500 PANEL_POWER_UP_DELAY_SHIFT;
4501
4502 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4503 PANEL_LIGHT_ON_DELAY_SHIFT;
4504
4505 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4506 PANEL_LIGHT_OFF_DELAY_SHIFT;
4507
4508 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4509 PANEL_POWER_DOWN_DELAY_SHIFT;
4510
4511 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4512 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4513
4514 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4515 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4516
41aa3448 4517 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4518
4519 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4520 * our hw here, which are all in 100usec. */
4521 spec.t1_t3 = 210 * 10;
4522 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4523 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4524 spec.t10 = 500 * 10;
4525 /* This one is special and actually in units of 100ms, but zero
4526 * based in the hw (so we need to add 100 ms). But the sw vbt
4527 * table multiplies it with 1000 to make it in units of 100usec,
4528 * too. */
4529 spec.t11_t12 = (510 + 100) * 10;
4530
4531 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4532 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4533
4534 /* Use the max of the register settings and vbt. If both are
4535 * unset, fall back to the spec limits. */
4536#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4537 spec.field : \
4538 max(cur.field, vbt.field))
4539 assign_final(t1_t3);
4540 assign_final(t8);
4541 assign_final(t9);
4542 assign_final(t10);
4543 assign_final(t11_t12);
4544#undef assign_final
4545
4546#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4547 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4548 intel_dp->backlight_on_delay = get_delay(t8);
4549 intel_dp->backlight_off_delay = get_delay(t9);
4550 intel_dp->panel_power_down_delay = get_delay(t10);
4551 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4552#undef get_delay
4553
f30d26e4
JN		 4554 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4555 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4556 intel_dp->panel_power_cycle_delay);
4557
4558 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4559 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4560
4561 if (out)
4562 *out = final;
4563}
4564
4565static void
4566intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4567 struct intel_dp *intel_dp,
4568 struct edp_power_seq *seq)
4569{
4570 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4571 u32 pp_on, pp_off, pp_div, port_sel = 0;
4572 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4573 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4574 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4575
e39b999a
VS		 4576 lockdep_assert_held(&dev_priv->pps_mutex);
4577
453c5420
JB		 4578 if (HAS_PCH_SPLIT(dev)) {
4579 pp_on_reg = PCH_PP_ON_DELAYS;
4580 pp_off_reg = PCH_PP_OFF_DELAYS;
4581 pp_div_reg = PCH_PP_DIVISOR;
4582 } else {
bf13e81b
JN		 4583 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4584
4585 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4586 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4587 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4588 }
4589
b2f19d1a
PZ		 4590 /*
4591 * And finally store the new values in the power sequencer. The
4592 * backlight delays are set to 1 because we do manual waits on them. For
4593 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4594 * we'll end up waiting for the backlight off delay twice: once when we
4595 * do the manual sleep, and once when we disable the panel and wait for
4596 * the PP_STATUS bit to become zero.
4597 */
f30d26e4 4598 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4599 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4600 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4601 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4602 /* Compute the divisor for the pp clock, simply match the Bspec
4603 * formula. */
453c5420 4604 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4605 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4606 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4607
4608 /* Haswell doesn't have any port selection bits for the panel
4609 * power sequencer any more. */
bc7d38a4 4610 if (IS_VALLEYVIEW(dev)) {
ad933b56 4611 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4612 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4613 if (port == PORT_A)
a24c144c 4614 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4615 else
a24c144c 4616 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4617 }
4618
453c5420
JB		 4619 pp_on |= port_sel;
4620
4621 I915_WRITE(pp_on_reg, pp_on);
4622 I915_WRITE(pp_off_reg, pp_off);
4623 I915_WRITE(pp_div_reg, pp_div);
67a54566 4624
67a54566 4625 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4626 I915_READ(pp_on_reg),
4627 I915_READ(pp_off_reg),
4628 I915_READ(pp_div_reg));
f684960e
CW		 4629}
4630
439d7ac0
PB		 4631void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4632{
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 struct intel_encoder *encoder;
4635 struct intel_dp *intel_dp = NULL;
4636 struct intel_crtc_config *config = NULL;
4637 struct intel_crtc *intel_crtc = NULL;
4638 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4639 u32 reg, val;
4640 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4641
4642 if (refresh_rate <= 0) {
4643 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4644 return;
4645 }
4646
4647 if (intel_connector == NULL) {
4648 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4649 return;
4650 }
4651
1fcc9d1c
DV		 4652 /*
4653 * FIXME: This needs proper synchronization with psr state. But really
4654 * hard to tell without seeing the user of this function of this code.
4655 * Check locking and ordering once that lands.
4656 */
439d7ac0
PB		 4657 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4658 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4659 return;
4660 }
4661
4662 encoder = intel_attached_encoder(&intel_connector->base);
4663 intel_dp = enc_to_intel_dp(&encoder->base);
4664 intel_crtc = encoder->new_crtc;
4665
4666 if (!intel_crtc) {
4667 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4668 return;
4669 }
4670
4671 config = &intel_crtc->config;
4672
4673 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4674 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4675 return;
4676 }
4677
4678 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4679 index = DRRS_LOW_RR;
4680
4681 if (index == intel_dp->drrs_state.refresh_rate_type) {
4682 DRM_DEBUG_KMS(
4683 "DRRS requested for previously set RR...ignoring\n");
4684 return;
4685 }
4686
4687 if (!intel_crtc->active) {
4688 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4689 return;
4690 }
4691
4692 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4693 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4694 val = I915_READ(reg);
4695 if (index > DRRS_HIGH_RR) {
4696 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4697 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4698 } else {
4699 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4700 }
4701 I915_WRITE(reg, val);
4702 }
4703
4704 /*
4705 * mutex taken to ensure that there is no race between differnt
4706 * drrs calls trying to update refresh rate. This scenario may occur
4707 * in future when idleness detection based DRRS in kernel and
4708 * possible calls from user space to set differnt RR are made.
4709 */
4710
4711 mutex_lock(&intel_dp->drrs_state.mutex);
4712
4713 intel_dp->drrs_state.refresh_rate_type = index;
4714
4715 mutex_unlock(&intel_dp->drrs_state.mutex);
4716
4717 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4718}
4719
4f9db5b5
PB		 4720static struct drm_display_mode *
4721intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4722 struct intel_connector *intel_connector,
4723 struct drm_display_mode *fixed_mode)
4724{
4725 struct drm_connector *connector = &intel_connector->base;
4726 struct intel_dp *intel_dp = &intel_dig_port->dp;
4727 struct drm_device *dev = intel_dig_port->base.base.dev;
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 struct drm_display_mode *downclock_mode = NULL;
4730
4731 if (INTEL_INFO(dev)->gen <= 6) {
4732 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4733 return NULL;
4734 }
4735
4736 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4737 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4738 return NULL;
4739 }
4740
4741 downclock_mode = intel_find_panel_downclock
4742 (dev, fixed_mode, connector);
4743
4744 if (!downclock_mode) {
4079b8d1 4745 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4746 return NULL;
4747 }
4748
439d7ac0
PB		 4749 dev_priv->drrs.connector = intel_connector;
4750
4751 mutex_init(&intel_dp->drrs_state.mutex);
4752
4f9db5b5
PB		 4753 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4754
4755 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4756 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4757 return downclock_mode;
4758}
4759
aba86890
ID		 4760void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4761{
4762 struct drm_device *dev = intel_encoder->base.dev;
4763 struct drm_i915_private *dev_priv = dev->dev_private;
4764 struct intel_dp *intel_dp;
4765 enum intel_display_power_domain power_domain;
4766
4767 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4768 return;
4769
e39b999a
VS		 4770 mutex_lock(&dev_priv->pps_mutex);
4771
aba86890
ID		 4772 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4773 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4774 goto out;
aba86890
ID		 4775 /*
4776 * The VDD bit needs a power domain reference, so if the bit is
4777 * already enabled when we boot or resume, grab this reference and
4778 * schedule a vdd off, so we don't hold on to the reference
4779 * indefinitely.
4780 */
4781 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4782 power_domain = intel_display_port_power_domain(intel_encoder);
4783 intel_display_power_get(dev_priv, power_domain);
4784
4785 edp_panel_vdd_schedule_off(intel_dp);
e39b999a
VS		 4786 out:
4787 mutex_unlock(&dev_priv->pps_mutex);
aba86890
ID		 4788}
4789
ed92f0b2 4790static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4791 struct intel_connector *intel_connector,
4792 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4793{
4794 struct drm_connector *connector = &intel_connector->base;
4795 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4796 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4797 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4798 struct drm_i915_private *dev_priv = dev->dev_private;
4799 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4800 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4801 bool has_dpcd;
4802 struct drm_display_mode *scan;
4803 struct edid *edid;
4804
4f9db5b5
PB		 4805 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4806
ed92f0b2
PZ		 4807 if (!is_edp(intel_dp))
4808 return true;
4809
aba86890 4810 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4811
ed92f0b2 4812 /* Cache DPCD and EDID for edp. */
24f3e092 4813 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4814 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4815 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4816
4817 if (has_dpcd) {
4818 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4819 dev_priv->no_aux_handshake =
4820 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4821 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4822 } else {
4823 /* if this fails, presume the device is a ghost */
4824 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4825 return false;
4826 }
4827
4828 /* We now know it's not a ghost, init power sequence regs. */
e39b999a 4829 mutex_lock(&dev_priv->pps_mutex);
0095e6dc 4830 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
e39b999a 4831 mutex_unlock(&dev_priv->pps_mutex);
ed92f0b2 4832
060c8778 4833 mutex_lock(&dev->mode_config.mutex);
0b99836f 4834 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4835 if (edid) {
4836 if (drm_add_edid_modes(connector, edid)) {
4837 drm_mode_connector_update_edid_property(connector,
4838 edid);
4839 drm_edid_to_eld(connector, edid);
4840 } else {
4841 kfree(edid);
4842 edid = ERR_PTR(-EINVAL);
4843 }
4844 } else {
4845 edid = ERR_PTR(-ENOENT);
4846 }
4847 intel_connector->edid = edid;
4848
4849 /* prefer fixed mode from EDID if available */
4850 list_for_each_entry(scan, &connector->probed_modes, head) {
4851 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4852 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4853 downclock_mode = intel_dp_drrs_init(
4854 intel_dig_port,
4855 intel_connector, fixed_mode);
ed92f0b2
PZ		 4856 break;
4857 }
4858 }
4859
4860 /* fallback to VBT if available for eDP */
4861 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4862 fixed_mode = drm_mode_duplicate(dev,
4863 dev_priv->vbt.lfp_lvds_vbt_mode);
4864 if (fixed_mode)
4865 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4866 }
060c8778 4867 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4868
01527b31
CT		 4869 if (IS_VALLEYVIEW(dev)) {
4870 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4871 register_reboot_notifier(&intel_dp->edp_notifier);
4872 }
4873
4f9db5b5 4874 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4875 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4876 intel_panel_setup_backlight(connector);
4877
4878 return true;
4879}
4880
16c25533 4881bool
f0fec3f2
PZ		 4882intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4883 struct intel_connector *intel_connector)
a4fc5ed6 4884{
f0fec3f2
PZ		 4885 struct drm_connector *connector = &intel_connector->base;
4886 struct intel_dp *intel_dp = &intel_dig_port->dp;
4887 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4888 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4889 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4890 enum port port = intel_dig_port->port;
0095e6dc 4891 struct edp_power_seq power_seq = { 0 };
0b99836f 4892 int type;
a4fc5ed6 4893
a4a5d2f8
VS		 4894 intel_dp->pps_pipe = INVALID_PIPE;
4895
ec5b01dd
DL		 4896 /* intel_dp vfuncs */
4897 if (IS_VALLEYVIEW(dev))
4898 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4899 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4900 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4901 else if (HAS_PCH_SPLIT(dev))
4902 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4903 else
4904 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4905
153b1100
DL		 4906 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4907
0767935e
DV		 4908 /* Preserve the current hw state. */
4909 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4910 intel_dp->attached_connector = intel_connector;
3d3dc149 4911
3b32a35b 4912 if (intel_dp_is_edp(dev, port))
b329530c 4913 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4914 else
4915 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4916
f7d24902
ID		 4917 /*
4918 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4919 * for DP the encoder type can be set by the caller to
4920 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4921 */
4922 if (type == DRM_MODE_CONNECTOR_eDP)
4923 intel_encoder->type = INTEL_OUTPUT_EDP;
4924
e7281eab
ID		 4925 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4926 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4927 port_name(port));
4928
b329530c 4929 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4930 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4931
a4fc5ed6
KP		 4932 connector->interlace_allowed = true;
4933 connector->doublescan_allowed = 0;
4934
f0fec3f2 4935 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4936 edp_panel_vdd_work);
a4fc5ed6 4937
df0e9248 4938 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4939 drm_connector_register(connector);
a4fc5ed6 4940
affa9354 4941 if (HAS_DDI(dev))
bcbc889b
PZ		 4942 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4943 else
4944 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4945 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4946
0b99836f 4947 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4948 switch (port) {
4949 case PORT_A:
1d843f9d 4950 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4951 break;
4952 case PORT_B:
1d843f9d 4953 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4954 break;
4955 case PORT_C:
1d843f9d 4956 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4957 break;
4958 case PORT_D:
1d843f9d 4959 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4960 break;
4961 default:
ad1c0b19 4962 BUG();
5eb08b69
ZW		 4963 }
4964
dada1a9f 4965 if (is_edp(intel_dp)) {
e39b999a 4966 mutex_lock(&dev_priv->pps_mutex);
a4a5d2f8
VS		 4967 if (IS_VALLEYVIEW(dev)) {
4968 vlv_initial_power_sequencer_setup(intel_dp);
4969 } else {
4970 intel_dp_init_panel_power_timestamps(intel_dp);
4971 intel_dp_init_panel_power_sequencer(dev, intel_dp,
4972 &power_seq);
4973 }
dada1a9f 4974 }
a4a5d2f8 4975 mutex_unlock(&dev_priv->pps_mutex);
0095e6dc 4976
9d1a1031 4977 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4978
0e32b39c
DA		 4979 /* init MST on ports that can support it */
4980 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4981 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 4982 intel_dp_mst_encoder_init(intel_dig_port,
4983 intel_connector->base.base.id);
0e32b39c
DA		 4984 }
4985 }
4986
0095e6dc 4987 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4988 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4989 if (is_edp(intel_dp)) {
4990 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
e39b999a 4991 mutex_lock(&dev_priv->pps_mutex);
4be73780 4992 edp_panel_vdd_off_sync(intel_dp);
e39b999a 4993 mutex_unlock(&dev_priv->pps_mutex);
15b1d171 4994 }
34ea3d38 4995 drm_connector_unregister(connector);
b2f246a8 4996 drm_connector_cleanup(connector);
16c25533 4997 return false;
b2f246a8 4998 }
32f9d658 4999
f684960e
CW		 5000 intel_dp_add_properties(intel_dp, connector);
5001
a4fc5ed6
KP		 5002 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5003 * 0xd. Failure to do so will result in spurious interrupts being
5004 * generated on the port when a cable is not attached.
5005 */
5006 if (IS_G4X(dev) && !IS_GM45(dev)) {
5007 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5008 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5009 }
16c25533
PZ		 5010
5011 return true;
a4fc5ed6 5012}
f0fec3f2
PZ		 5013
5014void
5015intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5016{
13cf5504 5017 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5018 struct intel_digital_port *intel_dig_port;
5019 struct intel_encoder *intel_encoder;
5020 struct drm_encoder *encoder;
5021 struct intel_connector *intel_connector;
5022
b14c5679 5023 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5024 if (!intel_dig_port)
5025 return;
5026
b14c5679 5027 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5028 if (!intel_connector) {
5029 kfree(intel_dig_port);
5030 return;
5031 }
5032
5033 intel_encoder = &intel_dig_port->base;
5034 encoder = &intel_encoder->base;
5035
5036 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5037 DRM_MODE_ENCODER_TMDS);
5038
5bfe2ac0 5039 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5040 intel_encoder->disable = intel_disable_dp;
00c09d70 5041 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5042 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5043 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5044 if (IS_CHERRYVIEW(dev)) {
9197c88b 5045 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5046 intel_encoder->pre_enable = chv_pre_enable_dp;
5047 intel_encoder->enable = vlv_enable_dp;
580d3811 5048 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5049 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5050 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5051 intel_encoder->pre_enable = vlv_pre_enable_dp;
5052 intel_encoder->enable = vlv_enable_dp;
49277c31 5053 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5054 } else {
ecff4f3b
JN		 5055 intel_encoder->pre_enable = g4x_pre_enable_dp;
5056 intel_encoder->enable = g4x_enable_dp;
49277c31 5057 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 5058 }
f0fec3f2 5059
174edf1f 5060 intel_dig_port->port = port;
f0fec3f2
PZ		 5061 intel_dig_port->dp.output_reg = output_reg;
5062
00c09d70 5063 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5064 if (IS_CHERRYVIEW(dev)) {
5065 if (port == PORT_D)
5066 intel_encoder->crtc_mask = 1 << 2;
5067 else
5068 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5069 } else {
5070 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5071 }
bc079e8b 5072 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5073 intel_encoder->hot_plug = intel_dp_hot_plug;
5074
13cf5504
DA		 5075 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5076 dev_priv->hpd_irq_port[port] = intel_dig_port;
5077
15b1d171
PZ		 5078 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5079 drm_encoder_cleanup(encoder);
5080 kfree(intel_dig_port);
b2f246a8 5081 kfree(intel_connector);
15b1d171 5082 }
f0fec3f2 5083}
0e32b39c
DA		 5084
5085void intel_dp_mst_suspend(struct drm_device *dev)
5086{
5087 struct drm_i915_private *dev_priv = dev->dev_private;
5088 int i;
5089
5090 /* disable MST */
5091 for (i = 0; i < I915_MAX_PORTS; i++) {
5092 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5093 if (!intel_dig_port)
5094 continue;
5095
5096 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5097 if (!intel_dig_port->dp.can_mst)
5098 continue;
5099 if (intel_dig_port->dp.is_mst)
5100 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5101 }
5102 }
5103}
5104
5105void intel_dp_mst_resume(struct drm_device *dev)
5106{
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 int i;
5109
5110 for (i = 0; i < I915_MAX_PORTS; i++) {
5111 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5112 if (!intel_dig_port)
5113 continue;
5114 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5115 int ret;
5116
5117 if (!intel_dig_port->dp.can_mst)
5118 continue;
5119
5120 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5121 if (ret != 0) {
5122 intel_dp_check_mst_status(&intel_dig_port->dp);
5123 }
5124 }
5125 }
5126}
Linux kernel - Deliverables
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