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drm/i915: Track whether cursor needs physical address in intel_device_info
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include "drmP.h"
30#include "drm.h"
31#include "drm_crtc.h"
32#include "drm_crtc_helper.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
ab2c0672 36#include "drm_dp_helper.h"
a4fc5ed6 37
ae266c98 38
a4fc5ed6
KP		 39#define DP_LINK_STATUS_SIZE 6
40#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41
42#define DP_LINK_CONFIGURATION_SIZE 9
43
32f9d658
ZW		 44#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
45
a4fc5ed6
KP		 46struct intel_dp_priv {
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 uint32_t save_DP;
51 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
52 bool has_audio;
c8110e52 53 int dpms_mode;
a4fc5ed6
KP		 54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[4];
57 struct intel_output *intel_output;
58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
60};
61
62static void
63intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
64 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
65
66static void
67intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
68
32f9d658
ZW		 69void
70intel_edp_link_config (struct intel_output *intel_output,
71 int *lane_num, int *link_bw)
72{
73 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
74
75 *lane_num = dp_priv->lane_count;
76 if (dp_priv->link_bw == DP_LINK_BW_1_62)
77 *link_bw = 162000;
78 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
79 *link_bw = 270000;
80}
81
a4fc5ed6
KP		 82static int
83intel_dp_max_lane_count(struct intel_output *intel_output)
84{
85 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
86 int max_lane_count = 4;
87
88 if (dp_priv->dpcd[0] >= 0x11) {
89 max_lane_count = dp_priv->dpcd[2] & 0x1f;
90 switch (max_lane_count) {
91 case 1: case 2: case 4:
92 break;
93 default:
94 max_lane_count = 4;
95 }
96 }
97 return max_lane_count;
98}
99
100static int
101intel_dp_max_link_bw(struct intel_output *intel_output)
102{
103 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
104 int max_link_bw = dp_priv->dpcd[1];
105
106 switch (max_link_bw) {
107 case DP_LINK_BW_1_62:
108 case DP_LINK_BW_2_7:
109 break;
110 default:
111 max_link_bw = DP_LINK_BW_1_62;
112 break;
113 }
114 return max_link_bw;
115}
116
117static int
118intel_dp_link_clock(uint8_t link_bw)
119{
120 if (link_bw == DP_LINK_BW_2_7)
121 return 270000;
122 else
123 return 162000;
124}
125
126/* I think this is a fiction */
127static int
128intel_dp_link_required(int pixel_clock)
129{
130 return pixel_clock * 3;
131}
132
133static int
134intel_dp_mode_valid(struct drm_connector *connector,
135 struct drm_display_mode *mode)
136{
137 struct intel_output *intel_output = to_intel_output(connector);
138 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
139 int max_lanes = intel_dp_max_lane_count(intel_output);
140
141 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
142 return MODE_CLOCK_HIGH;
143
144 if (mode->clock < 10000)
145 return MODE_CLOCK_LOW;
146
147 return MODE_OK;
148}
149
150static uint32_t
151pack_aux(uint8_t *src, int src_bytes)
152{
153 int i;
154 uint32_t v = 0;
155
156 if (src_bytes > 4)
157 src_bytes = 4;
158 for (i = 0; i < src_bytes; i++)
159 v |= ((uint32_t) src[i]) << ((3-i) * 8);
160 return v;
161}
162
163static void
164unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
165{
166 int i;
167 if (dst_bytes > 4)
168 dst_bytes = 4;
169 for (i = 0; i < dst_bytes; i++)
170 dst[i] = src >> ((3-i) * 8);
171}
172
fb0f8fbf
KP		 173/* hrawclock is 1/4 the FSB frequency */
174static int
175intel_hrawclk(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 uint32_t clkcfg;
179
180 clkcfg = I915_READ(CLKCFG);
181 switch (clkcfg & CLKCFG_FSB_MASK) {
182 case CLKCFG_FSB_400:
183 return 100;
184 case CLKCFG_FSB_533:
185 return 133;
186 case CLKCFG_FSB_667:
187 return 166;
188 case CLKCFG_FSB_800:
189 return 200;
190 case CLKCFG_FSB_1067:
191 return 266;
192 case CLKCFG_FSB_1333:
193 return 333;
194 /* these two are just a guess; one of them might be right */
195 case CLKCFG_FSB_1600:
196 case CLKCFG_FSB_1600_ALT:
197 return 400;
198 default:
199 return 133;
200 }
201}
202
a4fc5ed6
KP		 203static int
204intel_dp_aux_ch(struct intel_output *intel_output,
205 uint8_t *send, int send_bytes,
206 uint8_t *recv, int recv_size)
207{
208 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
209 uint32_t output_reg = dp_priv->output_reg;
210 struct drm_device *dev = intel_output->base.dev;
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 uint32_t ch_ctl = output_reg + 0x10;
213 uint32_t ch_data = ch_ctl + 4;
214 int i;
215 int recv_bytes;
216 uint32_t ctl;
217 uint32_t status;
fb0f8fbf
KP		 218 uint32_t aux_clock_divider;
219 int try;
a4fc5ed6
KP		 220
221 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 222 * and would like to run at 2MHz. So, take the
223 * hrawclk value and divide by 2 and use that
a4fc5ed6 224 */
32f9d658
ZW		 225 if (IS_eDP(intel_output))
226 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
f2b115e6
AJ		 227 else if (IS_IRONLAKE(dev))
228 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 229 else
230 aux_clock_divider = intel_hrawclk(dev) / 2;
231
fb0f8fbf
KP		 232 /* Must try at least 3 times according to DP spec */
233 for (try = 0; try < 5; try++) {
234 /* Load the send data into the aux channel data registers */
235 for (i = 0; i < send_bytes; i += 4) {
a419aef8 236 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 237
238 I915_WRITE(ch_data + i, d);
239 }
240
241 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
242 DP_AUX_CH_CTL_TIME_OUT_400us |
243 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
244 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
245 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
246 DP_AUX_CH_CTL_DONE |
247 DP_AUX_CH_CTL_TIME_OUT_ERROR |
248 DP_AUX_CH_CTL_RECEIVE_ERROR);
249
250 /* Send the command and wait for it to complete */
251 I915_WRITE(ch_ctl, ctl);
252 (void) I915_READ(ch_ctl);
253 for (;;) {
254 udelay(100);
255 status = I915_READ(ch_ctl);
256 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
257 break;
258 }
259
260 /* Clear done status and any errors */
eebc863e 261 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 262 DP_AUX_CH_CTL_DONE |
263 DP_AUX_CH_CTL_TIME_OUT_ERROR |
264 DP_AUX_CH_CTL_RECEIVE_ERROR));
265 (void) I915_READ(ch_ctl);
266 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 267 break;
268 }
269
a4fc5ed6 270 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 271 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 272 return -EBUSY;
a4fc5ed6
KP		 273 }
274
275 /* Check for timeout or receive error.
276 * Timeouts occur when the sink is not connected
277 */
a5b3da54 278 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 279 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 280 return -EIO;
281 }
1ae8c0a5
KP		 282
283 /* Timeouts occur when the device isn't connected, so they're
284 * "normal" -- don't fill the kernel log with these */
a5b3da54 285 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 286 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 287 return -ETIMEDOUT;
a4fc5ed6
KP		 288 }
289
290 /* Unload any bytes sent back from the other side */
291 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
292 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
293
294 if (recv_bytes > recv_size)
295 recv_bytes = recv_size;
296
297 for (i = 0; i < recv_bytes; i += 4) {
298 uint32_t d = I915_READ(ch_data + i);
299
300 unpack_aux(d, recv + i, recv_bytes - i);
301 }
302
303 return recv_bytes;
304}
305
306/* Write data to the aux channel in native mode */
307static int
308intel_dp_aux_native_write(struct intel_output *intel_output,
309 uint16_t address, uint8_t *send, int send_bytes)
310{
311 int ret;
312 uint8_t msg[20];
313 int msg_bytes;
314 uint8_t ack;
315
316 if (send_bytes > 16)
317 return -1;
318 msg[0] = AUX_NATIVE_WRITE << 4;
319 msg[1] = address >> 8;
eebc863e 320 msg[2] = address & 0xff;
a4fc5ed6
KP		 321 msg[3] = send_bytes - 1;
322 memcpy(&msg[4], send, send_bytes);
323 msg_bytes = send_bytes + 4;
324 for (;;) {
325 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
326 if (ret < 0)
327 return ret;
328 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
329 break;
330 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
331 udelay(100);
332 else
a5b3da54 333 return -EIO;
a4fc5ed6
KP		 334 }
335 return send_bytes;
336}
337
338/* Write a single byte to the aux channel in native mode */
339static int
340intel_dp_aux_native_write_1(struct intel_output *intel_output,
341 uint16_t address, uint8_t byte)
342{
343 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
344}
345
346/* read bytes from a native aux channel */
347static int
348intel_dp_aux_native_read(struct intel_output *intel_output,
349 uint16_t address, uint8_t *recv, int recv_bytes)
350{
351 uint8_t msg[4];
352 int msg_bytes;
353 uint8_t reply[20];
354 int reply_bytes;
355 uint8_t ack;
356 int ret;
357
358 msg[0] = AUX_NATIVE_READ << 4;
359 msg[1] = address >> 8;
360 msg[2] = address & 0xff;
361 msg[3] = recv_bytes - 1;
362
363 msg_bytes = 4;
364 reply_bytes = recv_bytes + 1;
365
366 for (;;) {
367 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
368 reply, reply_bytes);
a5b3da54
KP		 369 if (ret == 0)
370 return -EPROTO;
371 if (ret < 0)
a4fc5ed6
KP		 372 return ret;
373 ack = reply[0];
374 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
375 memcpy(recv, reply + 1, ret - 1);
376 return ret - 1;
377 }
378 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
379 udelay(100);
380 else
a5b3da54 381 return -EIO;
a4fc5ed6
KP		 382 }
383}
384
385static int
ab2c0672
DA		 386intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
387 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 388{
ab2c0672 389 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 390 struct intel_dp_priv *dp_priv = container_of(adapter,
391 struct intel_dp_priv,
392 adapter);
393 struct intel_output *intel_output = dp_priv->intel_output;
ab2c0672
DA		 394 uint16_t address = algo_data->address;
395 uint8_t msg[5];
396 uint8_t reply[2];
397 int msg_bytes;
398 int reply_bytes;
399 int ret;
400
401 /* Set up the command byte */
402 if (mode & MODE_I2C_READ)
403 msg[0] = AUX_I2C_READ << 4;
404 else
405 msg[0] = AUX_I2C_WRITE << 4;
406
407 if (!(mode & MODE_I2C_STOP))
408 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 409
ab2c0672
DA		 410 msg[1] = address >> 8;
411 msg[2] = address;
412
413 switch (mode) {
414 case MODE_I2C_WRITE:
415 msg[3] = 0;
416 msg[4] = write_byte;
417 msg_bytes = 5;
418 reply_bytes = 1;
419 break;
420 case MODE_I2C_READ:
421 msg[3] = 0;
422 msg_bytes = 4;
423 reply_bytes = 2;
424 break;
425 default:
426 msg_bytes = 3;
427 reply_bytes = 1;
428 break;
429 }
430
431 for (;;) {
432 ret = intel_dp_aux_ch(intel_output,
433 msg, msg_bytes,
434 reply, reply_bytes);
435 if (ret < 0) {
3ff99164 436 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 437 return ret;
438 }
439 switch (reply[0] & AUX_I2C_REPLY_MASK) {
440 case AUX_I2C_REPLY_ACK:
441 if (mode == MODE_I2C_READ) {
442 *read_byte = reply[1];
443 }
444 return reply_bytes - 1;
445 case AUX_I2C_REPLY_NACK:
3ff99164 446 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 447 return -EREMOTEIO;
448 case AUX_I2C_REPLY_DEFER:
3ff99164 449 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 450 udelay(100);
451 break;
452 default:
453 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
454 return -EREMOTEIO;
455 }
456 }
a4fc5ed6
KP		 457}
458
459static int
460intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
461{
462 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
463
d54e9d28 464 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 465 dp_priv->algo.running = false;
466 dp_priv->algo.address = 0;
467 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
468
469 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
470 dp_priv->adapter.owner = THIS_MODULE;
471 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 472 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
473 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6
KP		 474 dp_priv->adapter.algo_data = &dp_priv->algo;
475 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
476
477 return i2c_dp_aux_add_bus(&dp_priv->adapter);
478}
479
480static bool
481intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
482 struct drm_display_mode *adjusted_mode)
483{
484 struct intel_output *intel_output = enc_to_intel_output(encoder);
485 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
486 int lane_count, clock;
487 int max_lane_count = intel_dp_max_lane_count(intel_output);
488 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
489 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
490
491 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
492 for (clock = 0; clock <= max_clock; clock++) {
493 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
494
495 if (intel_dp_link_required(mode->clock) <= link_avail) {
496 dp_priv->link_bw = bws[clock];
497 dp_priv->lane_count = lane_count;
498 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 499 DRM_DEBUG_KMS("Display port link bw %02x lane "
500 "count %d clock %d\n",
a4fc5ed6
KP		 501 dp_priv->link_bw, dp_priv->lane_count,
502 adjusted_mode->clock);
503 return true;
504 }
505 }
506 }
507 return false;
508}
509
510struct intel_dp_m_n {
511 uint32_t tu;
512 uint32_t gmch_m;
513 uint32_t gmch_n;
514 uint32_t link_m;
515 uint32_t link_n;
516};
517
518static void
519intel_reduce_ratio(uint32_t *num, uint32_t *den)
520{
521 while (*num > 0xffffff || *den > 0xffffff) {
522 *num >>= 1;
523 *den >>= 1;
524 }
525}
526
527static void
528intel_dp_compute_m_n(int bytes_per_pixel,
529 int nlanes,
530 int pixel_clock,
531 int link_clock,
532 struct intel_dp_m_n *m_n)
533{
534 m_n->tu = 64;
535 m_n->gmch_m = pixel_clock * bytes_per_pixel;
536 m_n->gmch_n = link_clock * nlanes;
537 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
538 m_n->link_m = pixel_clock;
539 m_n->link_n = link_clock;
540 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
541}
542
543void
544intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
545 struct drm_display_mode *adjusted_mode)
546{
547 struct drm_device *dev = crtc->dev;
548 struct drm_mode_config *mode_config = &dev->mode_config;
549 struct drm_connector *connector;
550 struct drm_i915_private *dev_priv = dev->dev_private;
551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
552 int lane_count = 4;
553 struct intel_dp_m_n m_n;
554
555 /*
556 * Find the lane count in the intel_output private
557 */
558 list_for_each_entry(connector, &mode_config->connector_list, head) {
559 struct intel_output *intel_output = to_intel_output(connector);
560 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
561
562 if (!connector->encoder || connector->encoder->crtc != crtc)
563 continue;
564
565 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
566 lane_count = dp_priv->lane_count;
567 break;
568 }
569 }
570
571 /*
572 * Compute the GMCH and Link ratios. The '3' here is
573 * the number of bytes_per_pixel post-LUT, which we always
574 * set up for 8-bits of R/G/B, or 3 bytes total.
575 */
576 intel_dp_compute_m_n(3, lane_count,
577 mode->clock, adjusted_mode->clock, &m_n);
578
f2b115e6 579 if (IS_IRONLAKE(dev)) {
5eb08b69
ZW		 580 if (intel_crtc->pipe == 0) {
581 I915_WRITE(TRANSA_DATA_M1,
582 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
583 m_n.gmch_m);
584 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
585 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
586 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
587 } else {
588 I915_WRITE(TRANSB_DATA_M1,
589 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
590 m_n.gmch_m);
591 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
592 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
593 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
594 }
a4fc5ed6 595 } else {
5eb08b69
ZW		 596 if (intel_crtc->pipe == 0) {
597 I915_WRITE(PIPEA_GMCH_DATA_M,
598 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
599 m_n.gmch_m);
600 I915_WRITE(PIPEA_GMCH_DATA_N,
601 m_n.gmch_n);
602 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
603 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
604 } else {
605 I915_WRITE(PIPEB_GMCH_DATA_M,
606 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
607 m_n.gmch_m);
608 I915_WRITE(PIPEB_GMCH_DATA_N,
609 m_n.gmch_n);
610 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
611 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
612 }
a4fc5ed6
KP		 613 }
614}
615
616static void
617intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
618 struct drm_display_mode *adjusted_mode)
619{
620 struct intel_output *intel_output = enc_to_intel_output(encoder);
621 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
622 struct drm_crtc *crtc = intel_output->enc.crtc;
623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
624
625 dp_priv->DP = (DP_LINK_TRAIN_OFF |
626 DP_VOLTAGE_0_4 |
627 DP_PRE_EMPHASIS_0 |
628 DP_SYNC_VS_HIGH |
629 DP_SYNC_HS_HIGH);
630
631 switch (dp_priv->lane_count) {
632 case 1:
633 dp_priv->DP |= DP_PORT_WIDTH_1;
634 break;
635 case 2:
636 dp_priv->DP |= DP_PORT_WIDTH_2;
637 break;
638 case 4:
639 dp_priv->DP |= DP_PORT_WIDTH_4;
640 break;
641 }
642 if (dp_priv->has_audio)
643 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
644
645 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
646 dp_priv->link_configuration[0] = dp_priv->link_bw;
647 dp_priv->link_configuration[1] = dp_priv->lane_count;
648
649 /*
650 * Check for DPCD version > 1.1,
651 * enable enahanced frame stuff in that case
652 */
653 if (dp_priv->dpcd[0] >= 0x11) {
654 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
655 dp_priv->DP |= DP_ENHANCED_FRAMING;
656 }
657
658 if (intel_crtc->pipe == 1)
659 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658
ZW		 660
661 if (IS_eDP(intel_output)) {
662 /* don't miss out required setting for eDP */
663 dp_priv->DP |= DP_PLL_ENABLE;
664 if (adjusted_mode->clock < 200000)
665 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
666 else
667 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
668 }
a4fc5ed6
KP		 669}
670
f2b115e6 671static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 672{
673 struct drm_i915_private *dev_priv = dev->dev_private;
674 u32 pp;
675
28c97730 676 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 677 pp = I915_READ(PCH_PP_CONTROL);
678 pp |= EDP_BLC_ENABLE;
679 I915_WRITE(PCH_PP_CONTROL, pp);
680}
681
f2b115e6 682static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 683{
684 struct drm_i915_private *dev_priv = dev->dev_private;
685 u32 pp;
686
28c97730 687 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 688 pp = I915_READ(PCH_PP_CONTROL);
689 pp &= ~EDP_BLC_ENABLE;
690 I915_WRITE(PCH_PP_CONTROL, pp);
691}
a4fc5ed6
KP		 692
693static void
694intel_dp_dpms(struct drm_encoder *encoder, int mode)
695{
696 struct intel_output *intel_output = enc_to_intel_output(encoder);
697 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
698 struct drm_device *dev = intel_output->base.dev;
699 struct drm_i915_private *dev_priv = dev->dev_private;
700 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
701
702 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 703 if (dp_reg & DP_PORT_EN) {
a4fc5ed6 704 intel_dp_link_down(intel_output, dp_priv->DP);
32f9d658 705 if (IS_eDP(intel_output))
f2b115e6 706 ironlake_edp_backlight_off(dev);
32f9d658 707 }
a4fc5ed6 708 } else {
32f9d658 709 if (!(dp_reg & DP_PORT_EN)) {
a4fc5ed6 710 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
32f9d658 711 if (IS_eDP(intel_output))
f2b115e6 712 ironlake_edp_backlight_on(dev);
32f9d658 713 }
a4fc5ed6 714 }
c8110e52 715 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 716}
717
718/*
719 * Fetch AUX CH registers 0x202 - 0x207 which contain
720 * link status information
721 */
722static bool
723intel_dp_get_link_status(struct intel_output *intel_output,
724 uint8_t link_status[DP_LINK_STATUS_SIZE])
725{
726 int ret;
727
728 ret = intel_dp_aux_native_read(intel_output,
729 DP_LANE0_1_STATUS,
730 link_status, DP_LINK_STATUS_SIZE);
731 if (ret != DP_LINK_STATUS_SIZE)
732 return false;
733 return true;
734}
735
736static uint8_t
737intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
738 int r)
739{
740 return link_status[r - DP_LANE0_1_STATUS];
741}
742
743static void
744intel_dp_save(struct drm_connector *connector)
745{
746 struct intel_output *intel_output = to_intel_output(connector);
747 struct drm_device *dev = intel_output->base.dev;
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
750
751 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
752 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
753 dp_priv->save_link_configuration,
754 sizeof (dp_priv->save_link_configuration));
755}
756
757static uint8_t
758intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
759 int lane)
760{
761 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
762 int s = ((lane & 1) ?
763 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
764 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
765 uint8_t l = intel_dp_link_status(link_status, i);
766
767 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
768}
769
770static uint8_t
771intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
772 int lane)
773{
774 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
775 int s = ((lane & 1) ?
776 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
777 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
778 uint8_t l = intel_dp_link_status(link_status, i);
779
780 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
781}
782
783
784#if 0
785static char *voltage_names[] = {
786 "0.4V", "0.6V", "0.8V", "1.2V"
787};
788static char *pre_emph_names[] = {
789 "0dB", "3.5dB", "6dB", "9.5dB"
790};
791static char *link_train_names[] = {
792 "pattern 1", "pattern 2", "idle", "off"
793};
794#endif
795
796/*
797 * These are source-specific values; current Intel hardware supports
798 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
799 */
800#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
801
802static uint8_t
803intel_dp_pre_emphasis_max(uint8_t voltage_swing)
804{
805 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
806 case DP_TRAIN_VOLTAGE_SWING_400:
807 return DP_TRAIN_PRE_EMPHASIS_6;
808 case DP_TRAIN_VOLTAGE_SWING_600:
809 return DP_TRAIN_PRE_EMPHASIS_6;
810 case DP_TRAIN_VOLTAGE_SWING_800:
811 return DP_TRAIN_PRE_EMPHASIS_3_5;
812 case DP_TRAIN_VOLTAGE_SWING_1200:
813 default:
814 return DP_TRAIN_PRE_EMPHASIS_0;
815 }
816}
817
818static void
819intel_get_adjust_train(struct intel_output *intel_output,
820 uint8_t link_status[DP_LINK_STATUS_SIZE],
821 int lane_count,
822 uint8_t train_set[4])
823{
824 uint8_t v = 0;
825 uint8_t p = 0;
826 int lane;
827
828 for (lane = 0; lane < lane_count; lane++) {
829 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
830 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
831
832 if (this_v > v)
833 v = this_v;
834 if (this_p > p)
835 p = this_p;
836 }
837
838 if (v >= I830_DP_VOLTAGE_MAX)
839 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
840
841 if (p >= intel_dp_pre_emphasis_max(v))
842 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
843
844 for (lane = 0; lane < 4; lane++)
845 train_set[lane] = v | p;
846}
847
848static uint32_t
849intel_dp_signal_levels(uint8_t train_set, int lane_count)
850{
851 uint32_t signal_levels = 0;
852
853 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
854 case DP_TRAIN_VOLTAGE_SWING_400:
855 default:
856 signal_levels |= DP_VOLTAGE_0_4;
857 break;
858 case DP_TRAIN_VOLTAGE_SWING_600:
859 signal_levels |= DP_VOLTAGE_0_6;
860 break;
861 case DP_TRAIN_VOLTAGE_SWING_800:
862 signal_levels |= DP_VOLTAGE_0_8;
863 break;
864 case DP_TRAIN_VOLTAGE_SWING_1200:
865 signal_levels |= DP_VOLTAGE_1_2;
866 break;
867 }
868 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
869 case DP_TRAIN_PRE_EMPHASIS_0:
870 default:
871 signal_levels |= DP_PRE_EMPHASIS_0;
872 break;
873 case DP_TRAIN_PRE_EMPHASIS_3_5:
874 signal_levels |= DP_PRE_EMPHASIS_3_5;
875 break;
876 case DP_TRAIN_PRE_EMPHASIS_6:
877 signal_levels |= DP_PRE_EMPHASIS_6;
878 break;
879 case DP_TRAIN_PRE_EMPHASIS_9_5:
880 signal_levels |= DP_PRE_EMPHASIS_9_5;
881 break;
882 }
883 return signal_levels;
884}
885
886static uint8_t
887intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
888 int lane)
889{
890 int i = DP_LANE0_1_STATUS + (lane >> 1);
891 int s = (lane & 1) * 4;
892 uint8_t l = intel_dp_link_status(link_status, i);
893
894 return (l >> s) & 0xf;
895}
896
897/* Check for clock recovery is done on all channels */
898static bool
899intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
900{
901 int lane;
902 uint8_t lane_status;
903
904 for (lane = 0; lane < lane_count; lane++) {
905 lane_status = intel_get_lane_status(link_status, lane);
906 if ((lane_status & DP_LANE_CR_DONE) == 0)
907 return false;
908 }
909 return true;
910}
911
912/* Check to see if channel eq is done on all channels */
913#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
914 DP_LANE_CHANNEL_EQ_DONE|\
915 DP_LANE_SYMBOL_LOCKED)
916static bool
917intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
918{
919 uint8_t lane_align;
920 uint8_t lane_status;
921 int lane;
922
923 lane_align = intel_dp_link_status(link_status,
924 DP_LANE_ALIGN_STATUS_UPDATED);
925 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
926 return false;
927 for (lane = 0; lane < lane_count; lane++) {
928 lane_status = intel_get_lane_status(link_status, lane);
929 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
930 return false;
931 }
932 return true;
933}
934
935static bool
936intel_dp_set_link_train(struct intel_output *intel_output,
937 uint32_t dp_reg_value,
938 uint8_t dp_train_pat,
939 uint8_t train_set[4],
940 bool first)
941{
942 struct drm_device *dev = intel_output->base.dev;
943 struct drm_i915_private *dev_priv = dev->dev_private;
944 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
945 int ret;
946
947 I915_WRITE(dp_priv->output_reg, dp_reg_value);
948 POSTING_READ(dp_priv->output_reg);
949 if (first)
950 intel_wait_for_vblank(dev);
951
952 intel_dp_aux_native_write_1(intel_output,
953 DP_TRAINING_PATTERN_SET,
954 dp_train_pat);
955
956 ret = intel_dp_aux_native_write(intel_output,
957 DP_TRAINING_LANE0_SET, train_set, 4);
958 if (ret != 4)
959 return false;
960
961 return true;
962}
963
964static void
965intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
966 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
967{
968 struct drm_device *dev = intel_output->base.dev;
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
971 uint8_t train_set[4];
972 uint8_t link_status[DP_LINK_STATUS_SIZE];
973 int i;
974 uint8_t voltage;
975 bool clock_recovery = false;
976 bool channel_eq = false;
977 bool first = true;
978 int tries;
979
980 /* Write the link configuration data */
981 intel_dp_aux_native_write(intel_output, 0x100,
982 link_configuration, DP_LINK_CONFIGURATION_SIZE);
983
984 DP |= DP_PORT_EN;
985 DP &= ~DP_LINK_TRAIN_MASK;
986 memset(train_set, 0, 4);
987 voltage = 0xff;
988 tries = 0;
989 clock_recovery = false;
990 for (;;) {
991 /* Use train_set[0] to set the voltage and pre emphasis values */
992 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
993 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
994
995 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
996 DP_TRAINING_PATTERN_1, train_set, first))
997 break;
998 first = false;
999 /* Set training pattern 1 */
1000
1001 udelay(100);
1002 if (!intel_dp_get_link_status(intel_output, link_status))
1003 break;
1004
1005 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1006 clock_recovery = true;
1007 break;
1008 }
1009
1010 /* Check to see if we've tried the max voltage */
1011 for (i = 0; i < dp_priv->lane_count; i++)
1012 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1013 break;
1014 if (i == dp_priv->lane_count)
1015 break;
1016
1017 /* Check to see if we've tried the same voltage 5 times */
1018 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1019 ++tries;
1020 if (tries == 5)
1021 break;
1022 } else
1023 tries = 0;
1024 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1025
1026 /* Compute new train_set as requested by target */
1027 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1028 }
1029
1030 /* channel equalization */
1031 tries = 0;
1032 channel_eq = false;
1033 for (;;) {
1034 /* Use train_set[0] to set the voltage and pre emphasis values */
1035 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1036 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1037
1038 /* channel eq pattern */
1039 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
1040 DP_TRAINING_PATTERN_2, train_set,
1041 false))
1042 break;
1043
1044 udelay(400);
1045 if (!intel_dp_get_link_status(intel_output, link_status))
1046 break;
1047
1048 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1049 channel_eq = true;
1050 break;
1051 }
1052
1053 /* Try 5 times */
1054 if (tries > 5)
1055 break;
1056
1057 /* Compute new train_set as requested by target */
1058 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1059 ++tries;
1060 }
1061
1062 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1063 POSTING_READ(dp_priv->output_reg);
1064 intel_dp_aux_native_write_1(intel_output,
1065 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1066}
1067
1068static void
1069intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1070{
1071 struct drm_device *dev = intel_output->base.dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1074
28c97730 1075 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 1076
1077 if (IS_eDP(intel_output)) {
1078 DP &= ~DP_PLL_ENABLE;
1079 I915_WRITE(dp_priv->output_reg, DP);
1080 POSTING_READ(dp_priv->output_reg);
1081 udelay(100);
1082 }
1083
5eb08b69
ZW		 1084 DP &= ~DP_LINK_TRAIN_MASK;
1085 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1086 POSTING_READ(dp_priv->output_reg);
1087
1088 udelay(17000);
1089
32f9d658
ZW		 1090 if (IS_eDP(intel_output))
1091 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1092 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1093 POSTING_READ(dp_priv->output_reg);
1094}
1095
1096static void
1097intel_dp_restore(struct drm_connector *connector)
1098{
1099 struct intel_output *intel_output = to_intel_output(connector);
1100 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1101
1102 if (dp_priv->save_DP & DP_PORT_EN)
1103 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
1104 else
1105 intel_dp_link_down(intel_output, dp_priv->save_DP);
1106}
1107
a4fc5ed6
KP		 1108/*
1109 * According to DP spec
1110 * 5.1.2:
1111 * 1. Read DPCD
1112 * 2. Configure link according to Receiver Capabilities
1113 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1114 * 4. Check link status on receipt of hot-plug interrupt
1115 */
1116
1117static void
1118intel_dp_check_link_status(struct intel_output *intel_output)
1119{
1120 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1121 uint8_t link_status[DP_LINK_STATUS_SIZE];
1122
1123 if (!intel_output->enc.crtc)
1124 return;
1125
1126 if (!intel_dp_get_link_status(intel_output, link_status)) {
1127 intel_dp_link_down(intel_output, dp_priv->DP);
1128 return;
1129 }
1130
1131 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1132 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
1133}
a4fc5ed6 1134
5eb08b69 1135static enum drm_connector_status
f2b115e6 1136ironlake_dp_detect(struct drm_connector *connector)
5eb08b69
ZW		 1137{
1138 struct intel_output *intel_output = to_intel_output(connector);
1139 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1140 enum drm_connector_status status;
1141
1142 status = connector_status_disconnected;
1143 if (intel_dp_aux_native_read(intel_output,
1144 0x000, dp_priv->dpcd,
1145 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1146 {
1147 if (dp_priv->dpcd[0] != 0)
1148 status = connector_status_connected;
1149 }
1150 return status;
1151}
1152
a4fc5ed6
KP		 1153/**
1154 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1155 *
1156 * \return true if DP port is connected.
1157 * \return false if DP port is disconnected.
1158 */
1159static enum drm_connector_status
1160intel_dp_detect(struct drm_connector *connector)
1161{
1162 struct intel_output *intel_output = to_intel_output(connector);
1163 struct drm_device *dev = intel_output->base.dev;
1164 struct drm_i915_private *dev_priv = dev->dev_private;
1165 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1166 uint32_t temp, bit;
1167 enum drm_connector_status status;
1168
1169 dp_priv->has_audio = false;
1170
f2b115e6
AJ		 1171 if (IS_IRONLAKE(dev))
1172 return ironlake_dp_detect(connector);
5eb08b69 1173
a4fc5ed6
KP		 1174 temp = I915_READ(PORT_HOTPLUG_EN);
1175
1176 I915_WRITE(PORT_HOTPLUG_EN,
1177 temp |
1178 DPB_HOTPLUG_INT_EN |
1179 DPC_HOTPLUG_INT_EN |
1180 DPD_HOTPLUG_INT_EN);
1181
1182 POSTING_READ(PORT_HOTPLUG_EN);
1183
1184 switch (dp_priv->output_reg) {
1185 case DP_B:
1186 bit = DPB_HOTPLUG_INT_STATUS;
1187 break;
1188 case DP_C:
1189 bit = DPC_HOTPLUG_INT_STATUS;
1190 break;
1191 case DP_D:
1192 bit = DPD_HOTPLUG_INT_STATUS;
1193 break;
1194 default:
1195 return connector_status_unknown;
1196 }
1197
1198 temp = I915_READ(PORT_HOTPLUG_STAT);
1199
1200 if ((temp & bit) == 0)
1201 return connector_status_disconnected;
1202
1203 status = connector_status_disconnected;
1204 if (intel_dp_aux_native_read(intel_output,
1205 0x000, dp_priv->dpcd,
1206 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1207 {
1208 if (dp_priv->dpcd[0] != 0)
1209 status = connector_status_connected;
1210 }
1211 return status;
1212}
1213
1214static int intel_dp_get_modes(struct drm_connector *connector)
1215{
1216 struct intel_output *intel_output = to_intel_output(connector);
32f9d658
ZW		 1217 struct drm_device *dev = intel_output->base.dev;
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 int ret;
a4fc5ed6
KP		 1220
1221 /* We should parse the EDID data and find out if it has an audio sink
1222 */
1223
32f9d658
ZW		 1224 ret = intel_ddc_get_modes(intel_output);
1225 if (ret)
1226 return ret;
1227
1228 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1229 if (IS_eDP(intel_output)) {
1230 if (dev_priv->panel_fixed_mode != NULL) {
1231 struct drm_display_mode *mode;
1232 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1233 drm_mode_probed_add(connector, mode);
1234 return 1;
1235 }
1236 }
1237 return 0;
a4fc5ed6
KP		 1238}
1239
1240static void
1241intel_dp_destroy (struct drm_connector *connector)
1242{
1243 struct intel_output *intel_output = to_intel_output(connector);
1244
1245 if (intel_output->i2c_bus)
1246 intel_i2c_destroy(intel_output->i2c_bus);
1247 drm_sysfs_connector_remove(connector);
1248 drm_connector_cleanup(connector);
1249 kfree(intel_output);
1250}
1251
1252static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1253 .dpms = intel_dp_dpms,
1254 .mode_fixup = intel_dp_mode_fixup,
1255 .prepare = intel_encoder_prepare,
1256 .mode_set = intel_dp_mode_set,
1257 .commit = intel_encoder_commit,
1258};
1259
1260static const struct drm_connector_funcs intel_dp_connector_funcs = {
1261 .dpms = drm_helper_connector_dpms,
1262 .save = intel_dp_save,
1263 .restore = intel_dp_restore,
1264 .detect = intel_dp_detect,
1265 .fill_modes = drm_helper_probe_single_connector_modes,
1266 .destroy = intel_dp_destroy,
1267};
1268
1269static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1270 .get_modes = intel_dp_get_modes,
1271 .mode_valid = intel_dp_mode_valid,
1272 .best_encoder = intel_best_encoder,
1273};
1274
1275static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1276{
1277 drm_encoder_cleanup(encoder);
1278}
1279
1280static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1281 .destroy = intel_dp_enc_destroy,
1282};
1283
c8110e52
KP		 1284void
1285intel_dp_hot_plug(struct intel_output *intel_output)
1286{
1287 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1288
1289 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1290 intel_dp_check_link_status(intel_output);
1291}
ae266c98
ZY		 1292/*
1293 * Enumerate the child dev array parsed from VBT to check whether
1294 * the given DP is present.
1295 * If it is present, return 1.
1296 * If it is not present, return false.
1297 * If no child dev is parsed from VBT, it is assumed that the given
1298 * DP is present.
1299 */
6e36595a 1300static int dp_is_present_in_vbt(struct drm_device *dev, int dp_reg)
ae266c98
ZY		 1301{
1302 struct drm_i915_private *dev_priv = dev->dev_private;
1303 struct child_device_config *p_child;
1304 int i, dp_port, ret;
1305
1306 if (!dev_priv->child_dev_num)
1307 return 1;
1308
1309 dp_port = 0;
f24bc39f 1310 if (dp_reg == DP_B || dp_reg == PCH_DP_B)
ae266c98 1311 dp_port = PORT_IDPB;
f24bc39f 1312 else if (dp_reg == DP_C || dp_reg == PCH_DP_C)
ae266c98 1313 dp_port = PORT_IDPC;
f24bc39f 1314 else if (dp_reg == DP_D || dp_reg == PCH_DP_D)
ae266c98
ZY		 1315 dp_port = PORT_IDPD;
1316
1317 ret = 0;
1318 for (i = 0; i < dev_priv->child_dev_num; i++) {
1319 p_child = dev_priv->child_dev + i;
1320 /*
1321 * If the device type is not DP, continue.
1322 */
1323 if (p_child->device_type != DEVICE_TYPE_DP &&
1324 p_child->device_type != DEVICE_TYPE_eDP)
1325 continue;
1326 /* Find the eDP port */
1327 if (dp_reg == DP_A && p_child->device_type == DEVICE_TYPE_eDP) {
1328 ret = 1;
1329 break;
1330 }
1331 /* Find the DP port */
1332 if (p_child->dvo_port == dp_port) {
1333 ret = 1;
1334 break;
1335 }
1336 }
1337 return ret;
1338}
a4fc5ed6
KP		 1339void
1340intel_dp_init(struct drm_device *dev, int output_reg)
1341{
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 struct drm_connector *connector;
1344 struct intel_output *intel_output;
1345 struct intel_dp_priv *dp_priv;
5eb08b69 1346 const char *name = NULL;
a4fc5ed6 1347
ae266c98
ZY		 1348 if (!dp_is_present_in_vbt(dev, output_reg)) {
1349 DRM_DEBUG_KMS("DP is not present. Ignore it\n");
1350 return;
1351 }
a4fc5ed6
KP		 1352 intel_output = kcalloc(sizeof(struct intel_output) +
1353 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1354 if (!intel_output)
1355 return;
1356
1357 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1358
1359 connector = &intel_output->base;
1360 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1361 DRM_MODE_CONNECTOR_DisplayPort);
1362 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1363
32f9d658
ZW		 1364 if (output_reg == DP_A)
1365 intel_output->type = INTEL_OUTPUT_EDP;
1366 else
1367 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1368
652af9d7 1369 if (output_reg == DP_B || output_reg == PCH_DP_B)
f8aed700 1370 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1371 else if (output_reg == DP_C || output_reg == PCH_DP_C)
f8aed700 1372 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1373 else if (output_reg == DP_D || output_reg == PCH_DP_D)
f8aed700
ML		 1374 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1375
1376 if (IS_eDP(intel_output)) {
1377 intel_output->crtc_mask = (1 << 1);
7c8460db 1378 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
f8aed700
ML		 1379 } else
1380 intel_output->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1381 connector->interlace_allowed = true;
1382 connector->doublescan_allowed = 0;
1383
1384 dp_priv->intel_output = intel_output;
1385 dp_priv->output_reg = output_reg;
1386 dp_priv->has_audio = false;
c8110e52 1387 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6
KP		 1388 intel_output->dev_priv = dp_priv;
1389
1390 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1391 DRM_MODE_ENCODER_TMDS);
1392 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1393
1394 drm_mode_connector_attach_encoder(&intel_output->base,
1395 &intel_output->enc);
1396 drm_sysfs_connector_add(connector);
1397
1398 /* Set up the DDC bus. */
5eb08b69 1399 switch (output_reg) {
32f9d658
ZW		 1400 case DP_A:
1401 name = "DPDDC-A";
1402 break;
5eb08b69
ZW		 1403 case DP_B:
1404 case PCH_DP_B:
1405 name = "DPDDC-B";
1406 break;
1407 case DP_C:
1408 case PCH_DP_C:
1409 name = "DPDDC-C";
1410 break;
1411 case DP_D:
1412 case PCH_DP_D:
1413 name = "DPDDC-D";
1414 break;
1415 }
1416
1417 intel_dp_i2c_init(intel_output, name);
32f9d658 1418
a4fc5ed6 1419 intel_output->ddc_bus = &dp_priv->adapter;
c8110e52 1420 intel_output->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1421
32f9d658
ZW		 1422 if (output_reg == DP_A) {
1423 /* initialize panel mode from VBT if available for eDP */
1424 if (dev_priv->lfp_lvds_vbt_mode) {
1425 dev_priv->panel_fixed_mode =
1426 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1427 if (dev_priv->panel_fixed_mode) {
1428 dev_priv->panel_fixed_mode->type |=
1429 DRM_MODE_TYPE_PREFERRED;
1430 }
1431 }
1432 }
1433
a4fc5ed6
KP		 1434 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1435 * 0xd. Failure to do so will result in spurious interrupts being
1436 * generated on the port when a cable is not attached.
1437 */
1438 if (IS_G4X(dev) && !IS_GM45(dev)) {
1439 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1440 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1441 }
1442}
Linux kernel - Deliverables
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