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drm/i915/skl: Implement the get_aux_clock_divider() DP vfunc
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
b6b5e383
DL		 664static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
665{
666 /*
667 * SKL doesn't need us to program the AUX clock divider (Hardware will
668 * derive the clock from CDCLK automatically). We still implement the
669 * get_aux_clock_divider vfunc to plug-in into the existing code.
670 */
671 return index ? 0 : 1;
672}
673
5ed12a19
DL		 674static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
675 bool has_aux_irq,
676 int send_bytes,
677 uint32_t aux_clock_divider)
678{
679 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
680 struct drm_device *dev = intel_dig_port->base.base.dev;
681 uint32_t precharge, timeout;
682
683 if (IS_GEN6(dev))
684 precharge = 3;
685 else
686 precharge = 5;
687
688 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
689 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
690 else
691 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
692
693 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 694 DP_AUX_CH_CTL_DONE |
5ed12a19 695 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 696 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 697 timeout |
788d4433 698 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 699 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
700 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 701 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 702}
703
b84a1cf8
RV		 704static int
705intel_dp_aux_ch(struct intel_dp *intel_dp,
706 uint8_t *send, int send_bytes,
707 uint8_t *recv, int recv_size)
708{
709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
710 struct drm_device *dev = intel_dig_port->base.base.dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
713 uint32_t ch_data = ch_ctl + 4;
bc86625a 714 uint32_t aux_clock_divider;
b84a1cf8
RV		 715 int i, ret, recv_bytes;
716 uint32_t status;
5ed12a19 717 int try, clock = 0;
4e6b788c 718 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 719 bool vdd;
720
773538e8 721 pps_lock(intel_dp);
e39b999a 722
72c3500a
VS		 723 /*
724 * We will be called with VDD already enabled for dpcd/edid/oui reads.
725 * In such cases we want to leave VDD enabled and it's up to upper layers
726 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
727 * ourselves.
728 */
1e0560e0 729 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 730
731 /* dp aux is extremely sensitive to irq latency, hence request the
732 * lowest possible wakeup latency and so prevent the cpu from going into
733 * deep sleep states.
734 */
735 pm_qos_update_request(&dev_priv->pm_qos, 0);
736
737 intel_dp_check_edp(intel_dp);
5eb08b69 738
c67a470b
PZ		 739 intel_aux_display_runtime_get(dev_priv);
740
11bee43e
JB		 741 /* Try to wait for any previous AUX channel activity */
742 for (try = 0; try < 3; try++) {
ef04f00d 743 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 744 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
745 break;
746 msleep(1);
747 }
748
749 if (try == 3) {
750 WARN(1, "dp_aux_ch not started status 0x%08x\n",
751 I915_READ(ch_ctl));
9ee32fea
DV		 752 ret = -EBUSY;
753 goto out;
4f7f7b7e
CW		 754 }
755
46a5ae9f
PZ		 756 /* Only 5 data registers! */
757 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
758 ret = -E2BIG;
759 goto out;
760 }
761
ec5b01dd 762 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 763 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
764 has_aux_irq,
765 send_bytes,
766 aux_clock_divider);
5ed12a19 767
bc86625a
CW		 768 /* Must try at least 3 times according to DP spec */
769 for (try = 0; try < 5; try++) {
770 /* Load the send data into the aux channel data registers */
771 for (i = 0; i < send_bytes; i += 4)
772 I915_WRITE(ch_data + i,
773 pack_aux(send + i, send_bytes - i));
774
775 /* Send the command and wait for it to complete */
5ed12a19 776 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 777
778 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
779
780 /* Clear done status and any errors */
781 I915_WRITE(ch_ctl,
782 status |
783 DP_AUX_CH_CTL_DONE |
784 DP_AUX_CH_CTL_TIME_OUT_ERROR |
785 DP_AUX_CH_CTL_RECEIVE_ERROR);
786
787 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
788 DP_AUX_CH_CTL_RECEIVE_ERROR))
789 continue;
790 if (status & DP_AUX_CH_CTL_DONE)
791 break;
792 }
4f7f7b7e 793 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 794 break;
795 }
796
a4fc5ed6 797 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 798 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 799 ret = -EBUSY;
800 goto out;
a4fc5ed6
KP		 801 }
802
803 /* Check for timeout or receive error.
804 * Timeouts occur when the sink is not connected
805 */
a5b3da54 806 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 807 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 808 ret = -EIO;
809 goto out;
a5b3da54 810 }
1ae8c0a5
KP		 811
812 /* Timeouts occur when the device isn't connected, so they're
813 * "normal" -- don't fill the kernel log with these */
a5b3da54 814 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 815 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 816 ret = -ETIMEDOUT;
817 goto out;
a4fc5ed6
KP		 818 }
819
820 /* Unload any bytes sent back from the other side */
821 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
822 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 823 if (recv_bytes > recv_size)
824 recv_bytes = recv_size;
0206e353 825
4f7f7b7e
CW		 826 for (i = 0; i < recv_bytes; i += 4)
827 unpack_aux(I915_READ(ch_data + i),
828 recv + i, recv_bytes - i);
a4fc5ed6 829
9ee32fea
DV		 830 ret = recv_bytes;
831out:
832 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 833 intel_aux_display_runtime_put(dev_priv);
9ee32fea 834
884f19e9
JN		 835 if (vdd)
836 edp_panel_vdd_off(intel_dp, false);
837
773538e8 838 pps_unlock(intel_dp);
e39b999a 839
9ee32fea 840 return ret;
a4fc5ed6
KP		 841}
842
a6c8aff0
JN		 843#define BARE_ADDRESS_SIZE 3
844#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 845static ssize_t
846intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 847{
9d1a1031
JN		 848 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
849 uint8_t txbuf[20], rxbuf[20];
850 size_t txsize, rxsize;
a4fc5ed6 851 int ret;
a4fc5ed6 852
9d1a1031
JN		 853 txbuf[0] = msg->request << 4;
854 txbuf[1] = msg->address >> 8;
855 txbuf[2] = msg->address & 0xff;
856 txbuf[3] = msg->size - 1;
46a5ae9f 857
9d1a1031
JN		 858 switch (msg->request & ~DP_AUX_I2C_MOT) {
859 case DP_AUX_NATIVE_WRITE:
860 case DP_AUX_I2C_WRITE:
a6c8aff0 861 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 862 rxsize = 1;
f51a44b9 863
9d1a1031
JN		 864 if (WARN_ON(txsize > 20))
865 return -E2BIG;
a4fc5ed6 866
9d1a1031 867 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 868
9d1a1031
JN		 869 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
870 if (ret > 0) {
871 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 872
9d1a1031
JN		 873 /* Return payload size. */
874 ret = msg->size;
875 }
876 break;
46a5ae9f 877
9d1a1031
JN		 878 case DP_AUX_NATIVE_READ:
879 case DP_AUX_I2C_READ:
a6c8aff0 880 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 881 rxsize = msg->size + 1;
a4fc5ed6 882
9d1a1031
JN		 883 if (WARN_ON(rxsize > 20))
884 return -E2BIG;
a4fc5ed6 885
9d1a1031
JN		 886 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
887 if (ret > 0) {
888 msg->reply = rxbuf[0] >> 4;
889 /*
890 * Assume happy day, and copy the data. The caller is
891 * expected to check msg->reply before touching it.
892 *
893 * Return payload size.
894 */
895 ret--;
896 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 897 }
9d1a1031
JN		 898 break;
899
900 default:
901 ret = -EINVAL;
902 break;
a4fc5ed6 903 }
f51a44b9 904
9d1a1031 905 return ret;
a4fc5ed6
KP		 906}
907
9d1a1031
JN		 908static void
909intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
910{
911 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 912 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
913 enum port port = intel_dig_port->port;
0b99836f 914 const char *name = NULL;
ab2c0672
DA		 915 int ret;
916
33ad6626
JN		 917 switch (port) {
918 case PORT_A:
919 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 920 name = "DPDDC-A";
ab2c0672 921 break;
33ad6626
JN		 922 case PORT_B:
923 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 924 name = "DPDDC-B";
ab2c0672 925 break;
33ad6626
JN		 926 case PORT_C:
927 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 928 name = "DPDDC-C";
ab2c0672 929 break;
33ad6626
JN		 930 case PORT_D:
931 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 932 name = "DPDDC-D";
33ad6626
JN		 933 break;
934 default:
935 BUG();
ab2c0672
DA		 936 }
937
1b1aad75
DL		 938 /*
939 * The AUX_CTL register is usually DP_CTL + 0x10.
940 *
941 * On Haswell and Broadwell though:
942 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
943 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
944 *
945 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
946 */
947 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 948 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 949
0b99836f 950 intel_dp->aux.name = name;
9d1a1031
JN		 951 intel_dp->aux.dev = dev->dev;
952 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 953
0b99836f
JN		 954 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
955 connector->base.kdev->kobj.name);
8316f337 956
4f71d0cb 957 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 958 if (ret < 0) {
4f71d0cb 959 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 960 name, ret);
961 return;
ab2c0672 962 }
8a5e6aeb 963
0b99836f
JN		 964 ret = sysfs_create_link(&connector->base.kdev->kobj,
965 &intel_dp->aux.ddc.dev.kobj,
966 intel_dp->aux.ddc.dev.kobj.name);
967 if (ret < 0) {
968 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 969 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 970 }
a4fc5ed6
KP		 971}
972
80f65de3
ID		 973static void
974intel_dp_connector_unregister(struct intel_connector *intel_connector)
975{
976 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
977
0e32b39c
DA		 978 if (!intel_connector->mst_port)
979 sysfs_remove_link(&intel_connector->base.kdev->kobj,
980 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 981 intel_connector_unregister(intel_connector);
982}
983
0e50338c
DV		 984static void
985hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
986{
987 switch (link_bw) {
988 case DP_LINK_BW_1_62:
989 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
990 break;
991 case DP_LINK_BW_2_7:
992 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
993 break;
994 case DP_LINK_BW_5_4:
995 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
996 break;
997 }
998}
999
c6bb3538
DV		 1000static void
1001intel_dp_set_clock(struct intel_encoder *encoder,
1002 struct intel_crtc_config *pipe_config, int link_bw)
1003{
1004 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1005 const struct dp_link_dpll *divisor = NULL;
1006 int i, count = 0;
c6bb3538
DV		 1007
1008 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1009 divisor = gen4_dpll;
1010 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1011 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1012 divisor = pch_dpll;
1013 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1014 } else if (IS_CHERRYVIEW(dev)) {
1015 divisor = chv_dpll;
1016 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1017 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1018 divisor = vlv_dpll;
1019 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1020 }
9dd4ffdf
CML		 1021
1022 if (divisor && count) {
1023 for (i = 0; i < count; i++) {
1024 if (link_bw == divisor[i].link_bw) {
1025 pipe_config->dpll = divisor[i].dpll;
1026 pipe_config->clock_set = true;
1027 break;
1028 }
1029 }
c6bb3538
DV		 1030 }
1031}
1032
00c09d70 1033bool
5bfe2ac0
DV		 1034intel_dp_compute_config(struct intel_encoder *encoder,
1035 struct intel_crtc_config *pipe_config)
a4fc5ed6 1036{
5bfe2ac0 1037 struct drm_device *dev = encoder->base.dev;
36008365 1038 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1039 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1040 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1041 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1042 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1043 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1044 int lane_count, clock;
56071a20 1045 int min_lane_count = 1;
eeb6324d 1046 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1047 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1048 int min_clock = 0;
06ea66b6 1049 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1050 int bpp, mode_rate;
06ea66b6 1051 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1052 int link_avail, link_clock;
a4fc5ed6 1053
bc7d38a4 1054 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1055 pipe_config->has_pch_encoder = true;
1056
03afc4a2 1057 pipe_config->has_dp_encoder = true;
f769cd24 1058 pipe_config->has_drrs = false;
9ed109a7 1059 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1060
dd06f90e
JN		 1061 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1062 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1063 adjusted_mode);
2dd24552
JB		 1064 if (!HAS_PCH_SPLIT(dev))
1065 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1066 intel_connector->panel.fitting_mode);
1067 else
b074cec8
JB		 1068 intel_pch_panel_fitting(intel_crtc, pipe_config,
1069 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1070 }
1071
cb1793ce 1072 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1073 return false;
1074
083f9560
DV		 1075 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1076 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1077 max_lane_count, bws[max_clock],
1078 adjusted_mode->crtc_clock);
083f9560 1079
36008365
DV		 1080 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1081 * bpc in between. */
3e7ca985 1082 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1083 if (is_edp(intel_dp)) {
1084 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1085 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1086 dev_priv->vbt.edp_bpp);
1087 bpp = dev_priv->vbt.edp_bpp;
1088 }
1089
f4cdbc21
JN		 1090 if (IS_BROADWELL(dev)) {
1091 /* Yes, it's an ugly hack. */
1092 min_lane_count = max_lane_count;
1093 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1094 min_lane_count);
1095 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 1096 min_lane_count = min(dev_priv->vbt.edp_lanes,
1097 max_lane_count);
1098 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1099 min_lane_count);
1100 }
1101
1102 if (dev_priv->vbt.edp_rate) {
1103 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
1104 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1105 bws[min_clock]);
1106 }
7984211e 1107 }
657445fe 1108
36008365 1109 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1110 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1111 bpp);
36008365 1112
c6930992
DA		 1113 for (clock = min_clock; clock <= max_clock; clock++) {
1114 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1115 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1116 link_avail = intel_dp_max_data_rate(link_clock,
1117 lane_count);
1118
1119 if (mode_rate <= link_avail) {
1120 goto found;
1121 }
1122 }
1123 }
1124 }
c4867936 1125
36008365 1126 return false;
3685a8f3 1127
36008365 1128found:
55bc60db
VS		 1129 if (intel_dp->color_range_auto) {
1130 /*
1131 * See:
1132 * CEA-861-E - 5.1 Default Encoding Parameters
1133 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1134 */
18316c8c 1135 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1136 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1137 else
1138 intel_dp->color_range = 0;
1139 }
1140
3685a8f3 1141 if (intel_dp->color_range)
50f3b016 1142 pipe_config->limited_color_range = true;
a4fc5ed6 1143
36008365
DV		 1144 intel_dp->link_bw = bws[clock];
1145 intel_dp->lane_count = lane_count;
657445fe 1146 pipe_config->pipe_bpp = bpp;
ff9a6750 1147 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1148
36008365
DV		 1149 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1150 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1151 pipe_config->port_clock, bpp);
36008365
DV		 1152 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1153 mode_rate, link_avail);
a4fc5ed6 1154
03afc4a2 1155 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1156 adjusted_mode->crtc_clock,
1157 pipe_config->port_clock,
03afc4a2 1158 &pipe_config->dp_m_n);
9d1a455b 1159
439d7ac0
PB		 1160 if (intel_connector->panel.downclock_mode != NULL &&
1161 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1162 pipe_config->has_drrs = true;
439d7ac0
PB		 1163 intel_link_compute_m_n(bpp, lane_count,
1164 intel_connector->panel.downclock_mode->clock,
1165 pipe_config->port_clock,
1166 &pipe_config->dp_m2_n2);
1167 }
1168
ea155f32 1169 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1170 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1171 else
1172 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1173
03afc4a2 1174 return true;
a4fc5ed6
KP		 1175}
1176
7c62a164 1177static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1178{
7c62a164
DV		 1179 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1180 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1181 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 u32 dpa_ctl;
1184
ff9a6750 1185 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1186 dpa_ctl = I915_READ(DP_A);
1187 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1188
ff9a6750 1189 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1190 /* For a long time we've carried around a ILK-DevA w/a for the
1191 * 160MHz clock. If we're really unlucky, it's still required.
1192 */
1193 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1194 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1195 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1196 } else {
1197 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1198 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1199 }
1ce17038 1200
ea9b6006
DV		 1201 I915_WRITE(DP_A, dpa_ctl);
1202
1203 POSTING_READ(DP_A);
1204 udelay(500);
1205}
1206
8ac33ed3 1207static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1208{
b934223d 1209 struct drm_device *dev = encoder->base.dev;
417e822d 1210 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1211 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1212 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1213 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1214 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1215
417e822d 1216 /*
1a2eb460 1217 * There are four kinds of DP registers:
417e822d
KP		 1218 *
1219 * IBX PCH
1a2eb460
KP		 1220 * SNB CPU
1221 * IVB CPU
417e822d
KP		 1222 * CPT PCH
1223 *
1224 * IBX PCH and CPU are the same for almost everything,
1225 * except that the CPU DP PLL is configured in this
1226 * register
1227 *
1228 * CPT PCH is quite different, having many bits moved
1229 * to the TRANS_DP_CTL register instead. That
1230 * configuration happens (oddly) in ironlake_pch_enable
1231 */
9c9e7927 1232
417e822d
KP		 1233 /* Preserve the BIOS-computed detected bit. This is
1234 * supposed to be read-only.
1235 */
1236 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1237
417e822d 1238 /* Handle DP bits in common between all three register formats */
417e822d 1239 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1240 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1241
9ed109a7 1242 if (crtc->config.has_audio) {
e0dac65e 1243 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1244 pipe_name(crtc->pipe));
ea5b213a 1245 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1246 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1247 }
247d89f6 1248
417e822d 1249 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1250
bc7d38a4 1251 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1252 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1253 intel_dp->DP |= DP_SYNC_HS_HIGH;
1254 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1255 intel_dp->DP |= DP_SYNC_VS_HIGH;
1256 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1257
6aba5b6c 1258 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1259 intel_dp->DP |= DP_ENHANCED_FRAMING;
1260
7c62a164 1261 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1262 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1263 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1264 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1265
1266 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1267 intel_dp->DP |= DP_SYNC_HS_HIGH;
1268 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1269 intel_dp->DP |= DP_SYNC_VS_HIGH;
1270 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1271
6aba5b6c 1272 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1273 intel_dp->DP |= DP_ENHANCED_FRAMING;
1274
44f37d1f
CML		 1275 if (!IS_CHERRYVIEW(dev)) {
1276 if (crtc->pipe == 1)
1277 intel_dp->DP |= DP_PIPEB_SELECT;
1278 } else {
1279 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1280 }
417e822d
KP		 1281 } else {
1282 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1283 }
a4fc5ed6
KP		 1284}
1285
ffd6749d
PZ		 1286#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1287#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1288
1a5ef5b7
PZ		 1289#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1290#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1291
ffd6749d
PZ		 1292#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1293#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1294
4be73780 1295static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1296 u32 mask,
1297 u32 value)
bd943159 1298{
30add22d 1299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1300 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1301 u32 pp_stat_reg, pp_ctrl_reg;
1302
e39b999a
VS		 1303 lockdep_assert_held(&dev_priv->pps_mutex);
1304
bf13e81b
JN		 1305 pp_stat_reg = _pp_stat_reg(intel_dp);
1306 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1307
99ea7127 1308 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1309 mask, value,
1310 I915_READ(pp_stat_reg),
1311 I915_READ(pp_ctrl_reg));
32ce697c 1312
453c5420 1313 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1314 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1315 I915_READ(pp_stat_reg),
1316 I915_READ(pp_ctrl_reg));
32ce697c 1317 }
54c136d4
CW		 1318
1319 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1320}
32ce697c 1321
4be73780 1322static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1323{
1324 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1325 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1326}
1327
4be73780 1328static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1329{
1330 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1331 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1332}
1333
4be73780 1334static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1335{
1336 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1337
1338 /* When we disable the VDD override bit last we have to do the manual
1339 * wait. */
1340 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1341 intel_dp->panel_power_cycle_delay);
1342
4be73780 1343 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1344}
1345
4be73780 1346static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1347{
1348 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1349 intel_dp->backlight_on_delay);
1350}
1351
4be73780 1352static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1353{
1354 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1355 intel_dp->backlight_off_delay);
1356}
99ea7127 1357
832dd3c1
KP		 1358/* Read the current pp_control value, unlocking the register if it
1359 * is locked
1360 */
1361
453c5420 1362static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1363{
453c5420
JB		 1364 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 u32 control;
832dd3c1 1367
e39b999a
VS		 1368 lockdep_assert_held(&dev_priv->pps_mutex);
1369
bf13e81b 1370 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1371 control &= ~PANEL_UNLOCK_MASK;
1372 control |= PANEL_UNLOCK_REGS;
1373 return control;
bd943159
KP		 1374}
1375
951468f3
VS		 1376/*
1377 * Must be paired with edp_panel_vdd_off().
1378 * Must hold pps_mutex around the whole on/off sequence.
1379 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1380 */
1e0560e0 1381static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1382{
30add22d 1383 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1385 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1386 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1387 enum intel_display_power_domain power_domain;
5d613501 1388 u32 pp;
453c5420 1389 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1390 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1391
e39b999a
VS		 1392 lockdep_assert_held(&dev_priv->pps_mutex);
1393
97af61f5 1394 if (!is_edp(intel_dp))
adddaaf4 1395 return false;
bd943159
KP		 1396
1397 intel_dp->want_panel_vdd = true;
99ea7127 1398
4be73780 1399 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1400 return need_to_disable;
b0665d57 1401
4e6e1a54
ID		 1402 power_domain = intel_display_port_power_domain(intel_encoder);
1403 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1404
b0665d57 1405 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1406
4be73780
DV		 1407 if (!edp_have_panel_power(intel_dp))
1408 wait_panel_power_cycle(intel_dp);
99ea7127 1409
453c5420 1410 pp = ironlake_get_pp_control(intel_dp);
5d613501 1411 pp |= EDP_FORCE_VDD;
ebf33b18 1412
bf13e81b
JN		 1413 pp_stat_reg = _pp_stat_reg(intel_dp);
1414 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1415
1416 I915_WRITE(pp_ctrl_reg, pp);
1417 POSTING_READ(pp_ctrl_reg);
1418 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1419 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1420 /*
1421 * If the panel wasn't on, delay before accessing aux channel
1422 */
4be73780 1423 if (!edp_have_panel_power(intel_dp)) {
bd943159 1424 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1425 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1426 }
adddaaf4
JN		 1427
1428 return need_to_disable;
1429}
1430
951468f3
VS		 1431/*
1432 * Must be paired with intel_edp_panel_vdd_off() or
1433 * intel_edp_panel_off().
1434 * Nested calls to these functions are not allowed since
1435 * we drop the lock. Caller must use some higher level
1436 * locking to prevent nested calls from other threads.
1437 */
b80d6c78 1438void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1439{
c695b6b6 1440 bool vdd;
adddaaf4 1441
c695b6b6
VS		 1442 if (!is_edp(intel_dp))
1443 return;
1444
773538e8 1445 pps_lock(intel_dp);
c695b6b6 1446 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1447 pps_unlock(intel_dp);
c695b6b6
VS		 1448
1449 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1450}
1451
4be73780 1452static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1453{
30add22d 1454 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1455 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1456 struct intel_digital_port *intel_dig_port =
1457 dp_to_dig_port(intel_dp);
1458 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1459 enum intel_display_power_domain power_domain;
5d613501 1460 u32 pp;
453c5420 1461 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1462
e39b999a 1463 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1464
15e899a0 1465 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1466
15e899a0 1467 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1468 return;
b0665d57 1469
be2c9196 1470 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1471
be2c9196
VS		 1472 pp = ironlake_get_pp_control(intel_dp);
1473 pp &= ~EDP_FORCE_VDD;
453c5420 1474
be2c9196
VS		 1475 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1476 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1477
be2c9196
VS		 1478 I915_WRITE(pp_ctrl_reg, pp);
1479 POSTING_READ(pp_ctrl_reg);
99ea7127 1480
be2c9196
VS		 1481 /* Make sure sequencer is idle before allowing subsequent activity */
1482 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1483 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1484
be2c9196
VS		 1485 if ((pp & POWER_TARGET_ON) == 0)
1486 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1487
be2c9196
VS		 1488 power_domain = intel_display_port_power_domain(intel_encoder);
1489 intel_display_power_put(dev_priv, power_domain);
bd943159 1490}
5d613501 1491
4be73780 1492static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1493{
1494 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1495 struct intel_dp, panel_vdd_work);
bd943159 1496
773538e8 1497 pps_lock(intel_dp);
15e899a0
VS		 1498 if (!intel_dp->want_panel_vdd)
1499 edp_panel_vdd_off_sync(intel_dp);
773538e8 1500 pps_unlock(intel_dp);
bd943159
KP		 1501}
1502
aba86890
ID		 1503static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1504{
1505 unsigned long delay;
1506
1507 /*
1508 * Queue the timer to fire a long time from now (relative to the power
1509 * down delay) to keep the panel power up across a sequence of
1510 * operations.
1511 */
1512 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1513 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1514}
1515
951468f3
VS		 1516/*
1517 * Must be paired with edp_panel_vdd_on().
1518 * Must hold pps_mutex around the whole on/off sequence.
1519 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1520 */
4be73780 1521static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1522{
e39b999a
VS		 1523 struct drm_i915_private *dev_priv =
1524 intel_dp_to_dev(intel_dp)->dev_private;
1525
1526 lockdep_assert_held(&dev_priv->pps_mutex);
1527
97af61f5
KP		 1528 if (!is_edp(intel_dp))
1529 return;
5d613501 1530
bd943159 1531 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1532
bd943159
KP		 1533 intel_dp->want_panel_vdd = false;
1534
aba86890 1535 if (sync)
4be73780 1536 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1537 else
1538 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1539}
1540
951468f3
VS		 1541/*
1542 * Must be paired with intel_edp_panel_vdd_on().
1543 * Nested calls to these functions are not allowed since
1544 * we drop the lock. Caller must use some higher level
1545 * locking to prevent nested calls from other threads.
1546 */
1e0560e0
VS		 1547static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1548{
e39b999a
VS		 1549 if (!is_edp(intel_dp))
1550 return;
1551
773538e8 1552 pps_lock(intel_dp);
1e0560e0 1553 edp_panel_vdd_off(intel_dp, sync);
773538e8 1554 pps_unlock(intel_dp);
1e0560e0
VS		 1555}
1556
4be73780 1557void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1558{
30add22d 1559 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1560 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1561 u32 pp;
453c5420 1562 u32 pp_ctrl_reg;
9934c132 1563
97af61f5 1564 if (!is_edp(intel_dp))
bd943159 1565 return;
99ea7127
KP		 1566
1567 DRM_DEBUG_KMS("Turn eDP power on\n");
1568
773538e8 1569 pps_lock(intel_dp);
e39b999a 1570
4be73780 1571 if (edp_have_panel_power(intel_dp)) {
99ea7127 1572 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1573 goto out;
99ea7127 1574 }
9934c132 1575
4be73780 1576 wait_panel_power_cycle(intel_dp);
37c6c9b0 1577
bf13e81b 1578 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1579 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1580 if (IS_GEN5(dev)) {
1581 /* ILK workaround: disable reset around power sequence */
1582 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1583 I915_WRITE(pp_ctrl_reg, pp);
1584 POSTING_READ(pp_ctrl_reg);
05ce1a49 1585 }
37c6c9b0 1586
1c0ae80a 1587 pp |= POWER_TARGET_ON;
99ea7127
KP		 1588 if (!IS_GEN5(dev))
1589 pp |= PANEL_POWER_RESET;
1590
453c5420
JB		 1591 I915_WRITE(pp_ctrl_reg, pp);
1592 POSTING_READ(pp_ctrl_reg);
9934c132 1593
4be73780 1594 wait_panel_on(intel_dp);
dce56b3c 1595 intel_dp->last_power_on = jiffies;
9934c132 1596
05ce1a49
KP		 1597 if (IS_GEN5(dev)) {
1598 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1599 I915_WRITE(pp_ctrl_reg, pp);
1600 POSTING_READ(pp_ctrl_reg);
05ce1a49 1601 }
e39b999a
VS		 1602
1603 out:
773538e8 1604 pps_unlock(intel_dp);
9934c132
JB		 1605}
1606
4be73780 1607void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1608{
4e6e1a54
ID		 1609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1610 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1611 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1612 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1613 enum intel_display_power_domain power_domain;
99ea7127 1614 u32 pp;
453c5420 1615 u32 pp_ctrl_reg;
9934c132 1616
97af61f5
KP		 1617 if (!is_edp(intel_dp))
1618 return;
37c6c9b0 1619
99ea7127 1620 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1621
773538e8 1622 pps_lock(intel_dp);
e39b999a 1623
24f3e092
JN		 1624 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1625
453c5420 1626 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1627 /* We need to switch off panel power _and_ force vdd, for otherwise some
1628 * panels get very unhappy and cease to work. */
b3064154
PJ		 1629 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1630 EDP_BLC_ENABLE);
453c5420 1631
bf13e81b 1632 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1633
849e39f5
PZ		 1634 intel_dp->want_panel_vdd = false;
1635
453c5420
JB		 1636 I915_WRITE(pp_ctrl_reg, pp);
1637 POSTING_READ(pp_ctrl_reg);
9934c132 1638
dce56b3c 1639 intel_dp->last_power_cycle = jiffies;
4be73780 1640 wait_panel_off(intel_dp);
849e39f5
PZ		 1641
1642 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1643 power_domain = intel_display_port_power_domain(intel_encoder);
1644 intel_display_power_put(dev_priv, power_domain);
e39b999a 1645
773538e8 1646 pps_unlock(intel_dp);
9934c132
JB		 1647}
1648
1250d107
JN		 1649/* Enable backlight in the panel power control. */
1650static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1651{
da63a9f2
PZ		 1652 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1653 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1654 struct drm_i915_private *dev_priv = dev->dev_private;
1655 u32 pp;
453c5420 1656 u32 pp_ctrl_reg;
32f9d658 1657
01cb9ea6
JB		 1658 /*
1659 * If we enable the backlight right away following a panel power
1660 * on, we may see slight flicker as the panel syncs with the eDP
1661 * link. So delay a bit to make sure the image is solid before
1662 * allowing it to appear.
1663 */
4be73780 1664 wait_backlight_on(intel_dp);
e39b999a 1665
773538e8 1666 pps_lock(intel_dp);
e39b999a 1667
453c5420 1668 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1669 pp |= EDP_BLC_ENABLE;
453c5420 1670
bf13e81b 1671 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1672
1673 I915_WRITE(pp_ctrl_reg, pp);
1674 POSTING_READ(pp_ctrl_reg);
e39b999a 1675
773538e8 1676 pps_unlock(intel_dp);
32f9d658
ZW		 1677}
1678
1250d107
JN		 1679/* Enable backlight PWM and backlight PP control. */
1680void intel_edp_backlight_on(struct intel_dp *intel_dp)
1681{
1682 if (!is_edp(intel_dp))
1683 return;
1684
1685 DRM_DEBUG_KMS("\n");
1686
1687 intel_panel_enable_backlight(intel_dp->attached_connector);
1688 _intel_edp_backlight_on(intel_dp);
1689}
1690
1691/* Disable backlight in the panel power control. */
1692static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1693{
30add22d 1694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 u32 pp;
453c5420 1697 u32 pp_ctrl_reg;
32f9d658 1698
f01eca2e
KP		 1699 if (!is_edp(intel_dp))
1700 return;
1701
773538e8 1702 pps_lock(intel_dp);
e39b999a 1703
453c5420 1704 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1705 pp &= ~EDP_BLC_ENABLE;
453c5420 1706
bf13e81b 1707 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1708
1709 I915_WRITE(pp_ctrl_reg, pp);
1710 POSTING_READ(pp_ctrl_reg);
f7d2323c 1711
773538e8 1712 pps_unlock(intel_dp);
e39b999a
VS		 1713
1714 intel_dp->last_backlight_off = jiffies;
f7d2323c 1715 edp_wait_backlight_off(intel_dp);
1250d107 1716}
f7d2323c 1717
1250d107
JN		 1718/* Disable backlight PP control and backlight PWM. */
1719void intel_edp_backlight_off(struct intel_dp *intel_dp)
1720{
1721 if (!is_edp(intel_dp))
1722 return;
1723
1724 DRM_DEBUG_KMS("\n");
f7d2323c 1725
1250d107 1726 _intel_edp_backlight_off(intel_dp);
f7d2323c 1727 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1728}
a4fc5ed6 1729
73580fb7
JN		 1730/*
1731 * Hook for controlling the panel power control backlight through the bl_power
1732 * sysfs attribute. Take care to handle multiple calls.
1733 */
1734static void intel_edp_backlight_power(struct intel_connector *connector,
1735 bool enable)
1736{
1737 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1738 bool is_enabled;
1739
773538e8 1740 pps_lock(intel_dp);
e39b999a 1741 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1742 pps_unlock(intel_dp);
73580fb7
JN		 1743
1744 if (is_enabled == enable)
1745 return;
1746
23ba9373
JN		 1747 DRM_DEBUG_KMS("panel power control backlight %s\n",
1748 enable ? "enable" : "disable");
73580fb7
JN		 1749
1750 if (enable)
1751 _intel_edp_backlight_on(intel_dp);
1752 else
1753 _intel_edp_backlight_off(intel_dp);
1754}
1755
2bd2ad64 1756static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1757{
da63a9f2
PZ		 1758 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1759 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1760 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 u32 dpa_ctl;
1763
2bd2ad64
DV		 1764 assert_pipe_disabled(dev_priv,
1765 to_intel_crtc(crtc)->pipe);
1766
d240f20f
JB		 1767 DRM_DEBUG_KMS("\n");
1768 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1769 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1770 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1771
1772 /* We don't adjust intel_dp->DP while tearing down the link, to
1773 * facilitate link retraining (e.g. after hotplug). Hence clear all
1774 * enable bits here to ensure that we don't enable too much. */
1775 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1776 intel_dp->DP |= DP_PLL_ENABLE;
1777 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1778 POSTING_READ(DP_A);
1779 udelay(200);
d240f20f
JB		 1780}
1781
2bd2ad64 1782static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1783{
da63a9f2
PZ		 1784 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1785 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1786 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 u32 dpa_ctl;
1789
2bd2ad64
DV		 1790 assert_pipe_disabled(dev_priv,
1791 to_intel_crtc(crtc)->pipe);
1792
d240f20f 1793 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1794 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1795 "dp pll off, should be on\n");
1796 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1797
1798 /* We can't rely on the value tracked for the DP register in
1799 * intel_dp->DP because link_down must not change that (otherwise link
1800 * re-training will fail. */
298b0b39 1801 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1802 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1803 POSTING_READ(DP_A);
d240f20f
JB		 1804 udelay(200);
1805}
1806
c7ad3810 1807/* If the sink supports it, try to set the power state appropriately */
c19b0669 1808void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1809{
1810 int ret, i;
1811
1812 /* Should have a valid DPCD by this point */
1813 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1814 return;
1815
1816 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1817 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1818 DP_SET_POWER_D3);
c7ad3810
JB		 1819 } else {
1820 /*
1821 * When turning on, we need to retry for 1ms to give the sink
1822 * time to wake up.
1823 */
1824 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1825 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1826 DP_SET_POWER_D0);
c7ad3810
JB		 1827 if (ret == 1)
1828 break;
1829 msleep(1);
1830 }
1831 }
f9cac721
JN		 1832
1833 if (ret != 1)
1834 DRM_DEBUG_KMS("failed to %s sink power state\n",
1835 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1836}
1837
19d8fe15
DV		 1838static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1839 enum pipe *pipe)
d240f20f 1840{
19d8fe15 1841 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1842 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1843 struct drm_device *dev = encoder->base.dev;
1844 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1845 enum intel_display_power_domain power_domain;
1846 u32 tmp;
1847
1848 power_domain = intel_display_port_power_domain(encoder);
1849 if (!intel_display_power_enabled(dev_priv, power_domain))
1850 return false;
1851
1852 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1853
1854 if (!(tmp & DP_PORT_EN))
1855 return false;
1856
bc7d38a4 1857 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1858 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1859 } else if (IS_CHERRYVIEW(dev)) {
1860 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1861 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1862 *pipe = PORT_TO_PIPE(tmp);
1863 } else {
1864 u32 trans_sel;
1865 u32 trans_dp;
1866 int i;
1867
1868 switch (intel_dp->output_reg) {
1869 case PCH_DP_B:
1870 trans_sel = TRANS_DP_PORT_SEL_B;
1871 break;
1872 case PCH_DP_C:
1873 trans_sel = TRANS_DP_PORT_SEL_C;
1874 break;
1875 case PCH_DP_D:
1876 trans_sel = TRANS_DP_PORT_SEL_D;
1877 break;
1878 default:
1879 return true;
1880 }
1881
055e393f 1882 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1883 trans_dp = I915_READ(TRANS_DP_CTL(i));
1884 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1885 *pipe = i;
1886 return true;
1887 }
1888 }
19d8fe15 1889
4a0833ec
DV		 1890 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1891 intel_dp->output_reg);
1892 }
d240f20f 1893
19d8fe15
DV		 1894 return true;
1895}
d240f20f 1896
045ac3b5
JB		 1897static void intel_dp_get_config(struct intel_encoder *encoder,
1898 struct intel_crtc_config *pipe_config)
1899{
1900 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1901 u32 tmp, flags = 0;
63000ef6
XZ		 1902 struct drm_device *dev = encoder->base.dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 enum port port = dp_to_dig_port(intel_dp)->port;
1905 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1906 int dotclock;
045ac3b5 1907
9ed109a7
DV		 1908 tmp = I915_READ(intel_dp->output_reg);
1909 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1910 pipe_config->has_audio = true;
1911
63000ef6 1912 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1913 if (tmp & DP_SYNC_HS_HIGH)
1914 flags |= DRM_MODE_FLAG_PHSYNC;
1915 else
1916 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1917
63000ef6
XZ		 1918 if (tmp & DP_SYNC_VS_HIGH)
1919 flags |= DRM_MODE_FLAG_PVSYNC;
1920 else
1921 flags |= DRM_MODE_FLAG_NVSYNC;
1922 } else {
1923 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1924 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1925 flags |= DRM_MODE_FLAG_PHSYNC;
1926 else
1927 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1928
63000ef6
XZ		 1929 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1930 flags |= DRM_MODE_FLAG_PVSYNC;
1931 else
1932 flags |= DRM_MODE_FLAG_NVSYNC;
1933 }
045ac3b5
JB		 1934
1935 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1936
eb14cb74
VS		 1937 pipe_config->has_dp_encoder = true;
1938
1939 intel_dp_get_m_n(crtc, pipe_config);
1940
18442d08 1941 if (port == PORT_A) {
f1f644dc
JB		 1942 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1943 pipe_config->port_clock = 162000;
1944 else
1945 pipe_config->port_clock = 270000;
1946 }
18442d08
VS		 1947
1948 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1949 &pipe_config->dp_m_n);
1950
1951 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1952 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1953
241bfc38 1954 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1955
c6cd2ee2
JN		 1956 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1957 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1958 /*
1959 * This is a big fat ugly hack.
1960 *
1961 * Some machines in UEFI boot mode provide us a VBT that has 18
1962 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1963 * unknown we fail to light up. Yet the same BIOS boots up with
1964 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1965 * max, not what it tells us to use.
1966 *
1967 * Note: This will still be broken if the eDP panel is not lit
1968 * up by the BIOS, and thus we can't get the mode at module
1969 * load.
1970 */
1971 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1972 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1973 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1974 }
045ac3b5
JB		 1975}
1976
34eb7579 1977static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1978{
34eb7579 1979 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1980}
1981
2b28bb1b
RV		 1982static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1983{
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985
18b5992c 1986 if (!HAS_PSR(dev))
2b28bb1b
RV		 1987 return false;
1988
18b5992c 1989 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1990}
1991
1992static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1993 struct edp_vsc_psr *vsc_psr)
1994{
1995 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1996 struct drm_device *dev = dig_port->base.base.dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1999 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2000 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2001 uint32_t *data = (uint32_t *) vsc_psr;
2002 unsigned int i;
2003
2004 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2005 the video DIP being updated before program video DIP data buffer
2006 registers for DIP being updated. */
2007 I915_WRITE(ctl_reg, 0);
2008 POSTING_READ(ctl_reg);
2009
2010 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2011 if (i < sizeof(struct edp_vsc_psr))
2012 I915_WRITE(data_reg + i, *data++);
2013 else
2014 I915_WRITE(data_reg + i, 0);
2015 }
2016
2017 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2018 POSTING_READ(ctl_reg);
2019}
2020
2021static void intel_edp_psr_setup(struct intel_dp *intel_dp)
2022{
2023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2025 struct edp_vsc_psr psr_vsc;
2026
2b28bb1b
RV		 2027 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2028 memset(&psr_vsc, 0, sizeof(psr_vsc));
2029 psr_vsc.sdp_header.HB0 = 0;
2030 psr_vsc.sdp_header.HB1 = 0x7;
2031 psr_vsc.sdp_header.HB2 = 0x2;
2032 psr_vsc.sdp_header.HB3 = 0x8;
2033 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2034
2035 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 2036 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 2037 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 2038}
2039
2040static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2041{
0e0ae652
RV		 2042 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2043 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2044 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2045 uint32_t aux_clock_divider;
2b28bb1b
RV		 2046 int precharge = 0x3;
2047 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2048 bool only_standby = false;
2b28bb1b 2049
ec5b01dd
DL		 2050 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2051
0e0ae652
RV		 2052 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2053 only_standby = true;
2054
2b28bb1b 2055 /* Enable PSR in sink */
0e0ae652 2056 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2057 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2058 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2059 else
9d1a1031
JN		 2060 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2061 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2062
2063 /* Setup AUX registers */
18b5992c
BW		 2064 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2065 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2066 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2067 DP_AUX_CH_CTL_TIME_OUT_400us |
2068 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2069 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2070 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2071}
2072
2073static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2074{
0e0ae652
RV		 2075 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2076 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 uint32_t max_sleep_time = 0x1f;
2079 uint32_t idle_frames = 1;
2080 uint32_t val = 0x0;
ed8546ac 2081 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2082 bool only_standby = false;
2083
2084 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2085 only_standby = true;
2b28bb1b 2086
0e0ae652 2087 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2088 val |= EDP_PSR_LINK_STANDBY;
2089 val |= EDP_PSR_TP2_TP3_TIME_0us;
2090 val |= EDP_PSR_TP1_TIME_0us;
2091 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2092 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2093 } else
2094 val |= EDP_PSR_LINK_DISABLE;
2095
18b5992c 2096 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2097 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2098 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2099 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2100 EDP_PSR_ENABLE);
2101}
2102
3f51e471
RV		 2103static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2104{
2105 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2106 struct drm_device *dev = dig_port->base.base.dev;
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct drm_crtc *crtc = dig_port->base.base.crtc;
2109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2110
f0355c4a 2111 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2112 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2113 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2114
a031d709
RV		 2115 dev_priv->psr.source_ok = false;
2116
9ca15301 2117 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2118 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2119 return false;
2120 }
2121
d330a953 2122 if (!i915.enable_psr) {
105b7c11 2123 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2124 return false;
2125 }
2126
4c8c7000
RV		 2127 /* Below limitations aren't valid for Broadwell */
2128 if (IS_BROADWELL(dev))
2129 goto out;
2130
3f51e471
RV		 2131 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2132 S3D_ENABLE) {
2133 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2134 return false;
2135 }
2136
ca73b4f0 2137 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2138 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2139 return false;
2140 }
2141
4c8c7000 2142 out:
a031d709 2143 dev_priv->psr.source_ok = true;
3f51e471
RV		 2144 return true;
2145}
2146
3d739d92 2147static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2148{
7c8f8a70
RV		 2149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2150 struct drm_device *dev = intel_dig_port->base.base.dev;
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2152
3638379c
DV		 2153 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2154 WARN_ON(dev_priv->psr.active);
f0355c4a 2155 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2156
2b28bb1b
RV		 2157 /* Enable PSR on the panel */
2158 intel_edp_psr_enable_sink(intel_dp);
2159
2160 /* Enable PSR on the host */
2161 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2162
7c8f8a70 2163 dev_priv->psr.active = true;
2b28bb1b
RV		 2164}
2165
3d739d92
RV		 2166void intel_edp_psr_enable(struct intel_dp *intel_dp)
2167{
2168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2169 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2170
4704c573
RV		 2171 if (!HAS_PSR(dev)) {
2172 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2173 return;
2174 }
2175
34eb7579
RV		 2176 if (!is_edp_psr(intel_dp)) {
2177 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2178 return;
2179 }
2180
f0355c4a 2181 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2182 if (dev_priv->psr.enabled) {
2183 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2184 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2185 return;
2186 }
2187
9ca15301
DV		 2188 dev_priv->psr.busy_frontbuffer_bits = 0;
2189
16487254
RV		 2190 /* Setup PSR once */
2191 intel_edp_psr_setup(intel_dp);
2192
7c8f8a70 2193 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2194 dev_priv->psr.enabled = intel_dp;
f0355c4a 2195 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2196}
2197
2b28bb1b
RV		 2198void intel_edp_psr_disable(struct intel_dp *intel_dp)
2199{
2200 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2202
f0355c4a
DV		 2203 mutex_lock(&dev_priv->psr.lock);
2204 if (!dev_priv->psr.enabled) {
2205 mutex_unlock(&dev_priv->psr.lock);
2206 return;
2207 }
2208
3638379c
DV		 2209 if (dev_priv->psr.active) {
2210 I915_WRITE(EDP_PSR_CTL(dev),
2211 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2212
2213 /* Wait till PSR is idle */
2214 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2215 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2216 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2217
3638379c
DV		 2218 dev_priv->psr.active = false;
2219 } else {
2220 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2221 }
7c8f8a70 2222
2807cf69 2223 dev_priv->psr.enabled = NULL;
f0355c4a 2224 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2225
2226 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2227}
2228
f02a326e 2229static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2230{
2231 struct drm_i915_private *dev_priv =
2232 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2233 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2234
f0355c4a
DV		 2235 mutex_lock(&dev_priv->psr.lock);
2236 intel_dp = dev_priv->psr.enabled;
2237
2807cf69 2238 if (!intel_dp)
f0355c4a 2239 goto unlock;
2807cf69 2240
9ca15301
DV		 2241 /*
2242 * The delayed work can race with an invalidate hence we need to
2243 * recheck. Since psr_flush first clears this and then reschedules we
2244 * won't ever miss a flush when bailing out here.
2245 */
2246 if (dev_priv->psr.busy_frontbuffer_bits)
2247 goto unlock;
2248
2249 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2250unlock:
2251 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2252}
2253
9ca15301 2254static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2255{
2256 struct drm_i915_private *dev_priv = dev->dev_private;
2257
3638379c
DV		 2258 if (dev_priv->psr.active) {
2259 u32 val = I915_READ(EDP_PSR_CTL(dev));
2260
2261 WARN_ON(!(val & EDP_PSR_ENABLE));
2262
2263 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2264
2265 dev_priv->psr.active = false;
2266 }
7c8f8a70 2267
9ca15301
DV		 2268}
2269
2270void intel_edp_psr_invalidate(struct drm_device *dev,
2271 unsigned frontbuffer_bits)
2272{
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 struct drm_crtc *crtc;
2275 enum pipe pipe;
2276
9ca15301
DV		 2277 mutex_lock(&dev_priv->psr.lock);
2278 if (!dev_priv->psr.enabled) {
2279 mutex_unlock(&dev_priv->psr.lock);
2280 return;
2281 }
2282
2283 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2284 pipe = to_intel_crtc(crtc)->pipe;
2285
2286 intel_edp_psr_do_exit(dev);
2287
2288 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2289
2290 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2291 mutex_unlock(&dev_priv->psr.lock);
2292}
2293
2294void intel_edp_psr_flush(struct drm_device *dev,
2295 unsigned frontbuffer_bits)
2296{
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2298 struct drm_crtc *crtc;
2299 enum pipe pipe;
2300
9ca15301
DV		 2301 mutex_lock(&dev_priv->psr.lock);
2302 if (!dev_priv->psr.enabled) {
2303 mutex_unlock(&dev_priv->psr.lock);
2304 return;
2305 }
2306
2307 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2308 pipe = to_intel_crtc(crtc)->pipe;
2309 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2310
2311 /*
2312 * On Haswell sprite plane updates don't result in a psr invalidating
2313 * signal in the hardware. Which means we need to manually fake this in
2314 * software for all flushes, not just when we've seen a preceding
2315 * invalidation through frontbuffer rendering.
2316 */
2317 if (IS_HASWELL(dev) &&
2318 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2319 intel_edp_psr_do_exit(dev);
2320
2321 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2322 schedule_delayed_work(&dev_priv->psr.work,
2323 msecs_to_jiffies(100));
f0355c4a 2324 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2325}
2326
2327void intel_edp_psr_init(struct drm_device *dev)
2328{
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330
7c8f8a70 2331 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2332 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2333}
2334
e8cb4558 2335static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2336{
e8cb4558 2337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2338 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2339
2340 /* Make sure the panel is off before trying to change the mode. But also
2341 * ensure that we have vdd while we switch off the panel. */
24f3e092 2342 intel_edp_panel_vdd_on(intel_dp);
4be73780 2343 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2344 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2345 intel_edp_panel_off(intel_dp);
3739850b 2346
08aff3fe
VS		 2347 /* disable the port before the pipe on g4x */
2348 if (INTEL_INFO(dev)->gen < 5)
3739850b 2349 intel_dp_link_down(intel_dp);
d240f20f
JB		 2350}
2351
08aff3fe 2352static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2353{
2bd2ad64 2354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2355 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2356
49277c31 2357 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2358 if (port == PORT_A)
2359 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2360}
2361
2362static void vlv_post_disable_dp(struct intel_encoder *encoder)
2363{
2364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2365
2366 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2367}
2368
580d3811
VS		 2369static void chv_post_disable_dp(struct intel_encoder *encoder)
2370{
2371 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2372 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2373 struct drm_device *dev = encoder->base.dev;
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *intel_crtc =
2376 to_intel_crtc(encoder->base.crtc);
2377 enum dpio_channel ch = vlv_dport_to_channel(dport);
2378 enum pipe pipe = intel_crtc->pipe;
2379 u32 val;
2380
2381 intel_dp_link_down(intel_dp);
2382
2383 mutex_lock(&dev_priv->dpio_lock);
2384
2385 /* Propagate soft reset to data lane reset */
97fd4d5c 2386 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2387 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2388 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2389
97fd4d5c
VS		 2390 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2391 val |= CHV_PCS_REQ_SOFTRESET_EN;
2392 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2393
2394 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2395 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2396 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2397
2398 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2399 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2400 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2401
2402 mutex_unlock(&dev_priv->dpio_lock);
2403}
2404
7b13b58a
VS		 2405static void
2406_intel_dp_set_link_train(struct intel_dp *intel_dp,
2407 uint32_t *DP,
2408 uint8_t dp_train_pat)
2409{
2410 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2411 struct drm_device *dev = intel_dig_port->base.base.dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 enum port port = intel_dig_port->port;
2414
2415 if (HAS_DDI(dev)) {
2416 uint32_t temp = I915_READ(DP_TP_CTL(port));
2417
2418 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2419 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2420 else
2421 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2422
2423 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2424 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2425 case DP_TRAINING_PATTERN_DISABLE:
2426 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2427
2428 break;
2429 case DP_TRAINING_PATTERN_1:
2430 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2431 break;
2432 case DP_TRAINING_PATTERN_2:
2433 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2434 break;
2435 case DP_TRAINING_PATTERN_3:
2436 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2437 break;
2438 }
2439 I915_WRITE(DP_TP_CTL(port), temp);
2440
2441 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2442 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2443
2444 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2445 case DP_TRAINING_PATTERN_DISABLE:
2446 *DP |= DP_LINK_TRAIN_OFF_CPT;
2447 break;
2448 case DP_TRAINING_PATTERN_1:
2449 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2450 break;
2451 case DP_TRAINING_PATTERN_2:
2452 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2453 break;
2454 case DP_TRAINING_PATTERN_3:
2455 DRM_ERROR("DP training pattern 3 not supported\n");
2456 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2457 break;
2458 }
2459
2460 } else {
2461 if (IS_CHERRYVIEW(dev))
2462 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2463 else
2464 *DP &= ~DP_LINK_TRAIN_MASK;
2465
2466 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2467 case DP_TRAINING_PATTERN_DISABLE:
2468 *DP |= DP_LINK_TRAIN_OFF;
2469 break;
2470 case DP_TRAINING_PATTERN_1:
2471 *DP |= DP_LINK_TRAIN_PAT_1;
2472 break;
2473 case DP_TRAINING_PATTERN_2:
2474 *DP |= DP_LINK_TRAIN_PAT_2;
2475 break;
2476 case DP_TRAINING_PATTERN_3:
2477 if (IS_CHERRYVIEW(dev)) {
2478 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2479 } else {
2480 DRM_ERROR("DP training pattern 3 not supported\n");
2481 *DP |= DP_LINK_TRAIN_PAT_2;
2482 }
2483 break;
2484 }
2485 }
2486}
2487
2488static void intel_dp_enable_port(struct intel_dp *intel_dp)
2489{
2490 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492
2493 intel_dp->DP |= DP_PORT_EN;
2494
2495 /* enable with pattern 1 (as per spec) */
2496 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2497 DP_TRAINING_PATTERN_1);
2498
2499 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2500 POSTING_READ(intel_dp->output_reg);
2501}
2502
e8cb4558 2503static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2504{
e8cb4558
DV		 2505 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2506 struct drm_device *dev = encoder->base.dev;
2507 struct drm_i915_private *dev_priv = dev->dev_private;
2508 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2509
0c33d8d7
DV		 2510 if (WARN_ON(dp_reg & DP_PORT_EN))
2511 return;
5d613501 2512
7b13b58a 2513 intel_dp_enable_port(intel_dp);
24f3e092 2514 intel_edp_panel_vdd_on(intel_dp);
4be73780 2515 intel_edp_panel_on(intel_dp);
1e0560e0 2516 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2517 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2518 intel_dp_start_link_train(intel_dp);
33a34e4e 2519 intel_dp_complete_link_train(intel_dp);
3ab9c637 2520 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2521}
89b667f8 2522
ecff4f3b
JN		 2523static void g4x_enable_dp(struct intel_encoder *encoder)
2524{
828f5c6e
JN		 2525 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2526
ecff4f3b 2527 intel_enable_dp(encoder);
4be73780 2528 intel_edp_backlight_on(intel_dp);
ab1f90f9 2529}
89b667f8 2530
ab1f90f9
JN		 2531static void vlv_enable_dp(struct intel_encoder *encoder)
2532{
828f5c6e
JN		 2533 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2534
4be73780 2535 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2536}
2537
ecff4f3b 2538static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2539{
2540 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2541 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2542
8ac33ed3
DV		 2543 intel_dp_prepare(encoder);
2544
d41f1efb
DV		 2545 /* Only ilk+ has port A */
2546 if (dport->port == PORT_A) {
2547 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2548 ironlake_edp_pll_on(intel_dp);
d41f1efb 2549 }
ab1f90f9
JN		 2550}
2551
a4a5d2f8
VS		 2552static void vlv_steal_power_sequencer(struct drm_device *dev,
2553 enum pipe pipe)
2554{
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556 struct intel_encoder *encoder;
2557
2558 lockdep_assert_held(&dev_priv->pps_mutex);
2559
2560 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2561 base.head) {
2562 struct intel_dp *intel_dp;
773538e8 2563 enum port port;
a4a5d2f8
VS		 2564
2565 if (encoder->type != INTEL_OUTPUT_EDP)
2566 continue;
2567
2568 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2569 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2570
2571 if (intel_dp->pps_pipe != pipe)
2572 continue;
2573
2574 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2575 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2576
2577 /* make sure vdd is off before we steal it */
2578 edp_panel_vdd_off_sync(intel_dp);
2579
2580 intel_dp->pps_pipe = INVALID_PIPE;
2581 }
2582}
2583
2584static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2585{
2586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2587 struct intel_encoder *encoder = &intel_dig_port->base;
2588 struct drm_device *dev = encoder->base.dev;
2589 struct drm_i915_private *dev_priv = dev->dev_private;
2590 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2591 struct edp_power_seq power_seq;
2592
2593 lockdep_assert_held(&dev_priv->pps_mutex);
2594
2595 if (intel_dp->pps_pipe == crtc->pipe)
2596 return;
2597
2598 /*
2599 * If another power sequencer was being used on this
2600 * port previously make sure to turn off vdd there while
2601 * we still have control of it.
2602 */
2603 if (intel_dp->pps_pipe != INVALID_PIPE)
2604 edp_panel_vdd_off_sync(intel_dp);
2605
2606 /*
2607 * We may be stealing the power
2608 * sequencer from another port.
2609 */
2610 vlv_steal_power_sequencer(dev, crtc->pipe);
2611
2612 /* now it's all ours */
2613 intel_dp->pps_pipe = crtc->pipe;
2614
2615 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2616 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2617
2618 /* init power sequencer on this pipe and port */
2619 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2620 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2621 &power_seq);
2622}
2623
ab1f90f9 2624static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2625{
2bd2ad64 2626 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2627 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2628 struct drm_device *dev = encoder->base.dev;
89b667f8 2629 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2630 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2631 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2632 int pipe = intel_crtc->pipe;
2633 u32 val;
a4fc5ed6 2634
ab1f90f9 2635 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2636
ab3c759a 2637 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2638 val = 0;
2639 if (pipe)
2640 val |= (1<<21);
2641 else
2642 val &= ~(1<<21);
2643 val |= 0x001000c4;
ab3c759a
CML		 2644 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2645 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2646 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2647
ab1f90f9
JN		 2648 mutex_unlock(&dev_priv->dpio_lock);
2649
2cac613b 2650 if (is_edp(intel_dp)) {
773538e8 2651 pps_lock(intel_dp);
a4a5d2f8 2652 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2653 pps_unlock(intel_dp);
2cac613b 2654 }
bf13e81b 2655
ab1f90f9
JN		 2656 intel_enable_dp(encoder);
2657
e4607fcf 2658 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2659}
2660
ecff4f3b 2661static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2662{
2663 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2664 struct drm_device *dev = encoder->base.dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2666 struct intel_crtc *intel_crtc =
2667 to_intel_crtc(encoder->base.crtc);
e4607fcf 2668 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2669 int pipe = intel_crtc->pipe;
89b667f8 2670
8ac33ed3
DV		 2671 intel_dp_prepare(encoder);
2672
89b667f8 2673 /* Program Tx lane resets to default */
0980a60f 2674 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2675 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2676 DPIO_PCS_TX_LANE2_RESET |
2677 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2678 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2679 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2680 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2681 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2682 DPIO_PCS_CLK_SOFT_RESET);
2683
2684 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2685 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2686 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2687 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2688 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2689}
2690
e4a1d846
CML		 2691static void chv_pre_enable_dp(struct intel_encoder *encoder)
2692{
2693 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2694 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2695 struct drm_device *dev = encoder->base.dev;
2696 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2697 struct intel_crtc *intel_crtc =
2698 to_intel_crtc(encoder->base.crtc);
2699 enum dpio_channel ch = vlv_dport_to_channel(dport);
2700 int pipe = intel_crtc->pipe;
2701 int data, i;
949c1d43 2702 u32 val;
e4a1d846 2703
e4a1d846 2704 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2705
2706 /* Deassert soft data lane reset*/
97fd4d5c 2707 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2708 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2709 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2710
2711 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2712 val |= CHV_PCS_REQ_SOFTRESET_EN;
2713 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2714
2715 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2716 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2717 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2718
97fd4d5c 2719 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2720 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2721 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2722
2723 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2724 for (i = 0; i < 4; i++) {
2725 /* Set the latency optimal bit */
2726 data = (i == 1) ? 0x0 : 0x6;
2727 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2728 data << DPIO_FRC_LATENCY_SHFIT);
2729
2730 /* Set the upar bit */
2731 data = (i == 1) ? 0x0 : 0x1;
2732 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2733 data << DPIO_UPAR_SHIFT);
2734 }
2735
2736 /* Data lane stagger programming */
2737 /* FIXME: Fix up value only after power analysis */
2738
2739 mutex_unlock(&dev_priv->dpio_lock);
2740
2741 if (is_edp(intel_dp)) {
773538e8 2742 pps_lock(intel_dp);
a4a5d2f8 2743 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2744 pps_unlock(intel_dp);
e4a1d846
CML		 2745 }
2746
2747 intel_enable_dp(encoder);
2748
2749 vlv_wait_port_ready(dev_priv, dport);
2750}
2751
9197c88b
VS		 2752static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2753{
2754 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2755 struct drm_device *dev = encoder->base.dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 struct intel_crtc *intel_crtc =
2758 to_intel_crtc(encoder->base.crtc);
2759 enum dpio_channel ch = vlv_dport_to_channel(dport);
2760 enum pipe pipe = intel_crtc->pipe;
2761 u32 val;
2762
625695f8
VS		 2763 intel_dp_prepare(encoder);
2764
9197c88b
VS		 2765 mutex_lock(&dev_priv->dpio_lock);
2766
b9e5ac3c
VS		 2767 /* program left/right clock distribution */
2768 if (pipe != PIPE_B) {
2769 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2770 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2771 if (ch == DPIO_CH0)
2772 val |= CHV_BUFLEFTENA1_FORCE;
2773 if (ch == DPIO_CH1)
2774 val |= CHV_BUFRIGHTENA1_FORCE;
2775 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2776 } else {
2777 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2778 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2779 if (ch == DPIO_CH0)
2780 val |= CHV_BUFLEFTENA2_FORCE;
2781 if (ch == DPIO_CH1)
2782 val |= CHV_BUFRIGHTENA2_FORCE;
2783 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2784 }
2785
9197c88b
VS		 2786 /* program clock channel usage */
2787 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2788 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2789 if (pipe != PIPE_B)
2790 val &= ~CHV_PCS_USEDCLKCHANNEL;
2791 else
2792 val |= CHV_PCS_USEDCLKCHANNEL;
2793 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2794
2795 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2796 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2797 if (pipe != PIPE_B)
2798 val &= ~CHV_PCS_USEDCLKCHANNEL;
2799 else
2800 val |= CHV_PCS_USEDCLKCHANNEL;
2801 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2802
2803 /*
2804 * This a a bit weird since generally CL
2805 * matches the pipe, but here we need to
2806 * pick the CL based on the port.
2807 */
2808 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2809 if (pipe != PIPE_B)
2810 val &= ~CHV_CMN_USEDCLKCHANNEL;
2811 else
2812 val |= CHV_CMN_USEDCLKCHANNEL;
2813 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2814
2815 mutex_unlock(&dev_priv->dpio_lock);
2816}
2817
a4fc5ed6 2818/*
df0c237d
JB		 2819 * Native read with retry for link status and receiver capability reads for
2820 * cases where the sink may still be asleep.
9d1a1031
JN		 2821 *
2822 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2823 * supposed to retry 3 times per the spec.
a4fc5ed6 2824 */
9d1a1031
JN		 2825static ssize_t
2826intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2827 void *buffer, size_t size)
a4fc5ed6 2828{
9d1a1031
JN		 2829 ssize_t ret;
2830 int i;
61da5fab 2831
61da5fab 2832 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2833 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2834 if (ret == size)
2835 return ret;
61da5fab
JB		 2836 msleep(1);
2837 }
a4fc5ed6 2838
9d1a1031 2839 return ret;
a4fc5ed6
KP		 2840}
2841
2842/*
2843 * Fetch AUX CH registers 0x202 - 0x207 which contain
2844 * link status information
2845 */
2846static bool
93f62dad 2847intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2848{
9d1a1031
JN		 2849 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2850 DP_LANE0_1_STATUS,
2851 link_status,
2852 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2853}
2854
1100244e 2855/* These are source-specific values. */
a4fc5ed6 2856static uint8_t
1a2eb460 2857intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2858{
30add22d 2859 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2860 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2861
5a9d1f1a
DL		 2862 if (INTEL_INFO(dev)->gen >= 9)
2863 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2864 else if (IS_VALLEYVIEW(dev))
bd60018a 2865 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2866 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2867 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2868 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2869 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2870 else
bd60018a 2871 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2872}
2873
2874static uint8_t
2875intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2876{
30add22d 2877 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2878 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2879
5a9d1f1a
DL		 2880 if (INTEL_INFO(dev)->gen >= 9) {
2881 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2882 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2883 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2884 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2885 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2886 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2887 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2888 default:
2889 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2890 }
2891 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2892 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2893 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2894 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2895 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2896 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2898 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2900 default:
bd60018a 2901 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2902 }
e2fa6fba
P		 2903 } else if (IS_VALLEYVIEW(dev)) {
2904 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2905 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2906 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2908 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2910 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2911 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2912 default:
bd60018a 2913 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2914 }
bc7d38a4 2915 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2916 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2918 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2922 default:
bd60018a 2923 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2924 }
2925 } else {
2926 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2928 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2932 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2934 default:
bd60018a 2935 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2936 }
a4fc5ed6
KP		 2937 }
2938}
2939
e2fa6fba
P		 2940static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2941{
2942 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2945 struct intel_crtc *intel_crtc =
2946 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2947 unsigned long demph_reg_value, preemph_reg_value,
2948 uniqtranscale_reg_value;
2949 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2950 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2951 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2952
2953 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2954 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2955 preemph_reg_value = 0x0004000;
2956 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2958 demph_reg_value = 0x2B405555;
2959 uniqtranscale_reg_value = 0x552AB83A;
2960 break;
bd60018a 2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2962 demph_reg_value = 0x2B404040;
2963 uniqtranscale_reg_value = 0x5548B83A;
2964 break;
bd60018a 2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2966 demph_reg_value = 0x2B245555;
2967 uniqtranscale_reg_value = 0x5560B83A;
2968 break;
bd60018a 2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2970 demph_reg_value = 0x2B405555;
2971 uniqtranscale_reg_value = 0x5598DA3A;
2972 break;
2973 default:
2974 return 0;
2975 }
2976 break;
bd60018a 2977 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2978 preemph_reg_value = 0x0002000;
2979 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2981 demph_reg_value = 0x2B404040;
2982 uniqtranscale_reg_value = 0x5552B83A;
2983 break;
bd60018a 2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2985 demph_reg_value = 0x2B404848;
2986 uniqtranscale_reg_value = 0x5580B83A;
2987 break;
bd60018a 2988 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2989 demph_reg_value = 0x2B404040;
2990 uniqtranscale_reg_value = 0x55ADDA3A;
2991 break;
2992 default:
2993 return 0;
2994 }
2995 break;
bd60018a 2996 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2997 preemph_reg_value = 0x0000000;
2998 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3000 demph_reg_value = 0x2B305555;
3001 uniqtranscale_reg_value = 0x5570B83A;
3002 break;
bd60018a 3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3004 demph_reg_value = 0x2B2B4040;
3005 uniqtranscale_reg_value = 0x55ADDA3A;
3006 break;
3007 default:
3008 return 0;
3009 }
3010 break;
bd60018a 3011 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3012 preemph_reg_value = 0x0006000;
3013 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3015 demph_reg_value = 0x1B405555;
3016 uniqtranscale_reg_value = 0x55ADDA3A;
3017 break;
3018 default:
3019 return 0;
3020 }
3021 break;
3022 default:
3023 return 0;
3024 }
3025
0980a60f 3026 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3027 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3028 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3029 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3030 uniqtranscale_reg_value);
ab3c759a
CML		 3031 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3032 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3033 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3034 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3035 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3036
3037 return 0;
3038}
3039
e4a1d846
CML		 3040static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3041{
3042 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3045 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3046 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3047 uint8_t train_set = intel_dp->train_set[0];
3048 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3049 enum pipe pipe = intel_crtc->pipe;
3050 int i;
e4a1d846
CML		 3051
3052 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3053 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3054 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3056 deemph_reg_value = 128;
3057 margin_reg_value = 52;
3058 break;
bd60018a 3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3060 deemph_reg_value = 128;
3061 margin_reg_value = 77;
3062 break;
bd60018a 3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3064 deemph_reg_value = 128;
3065 margin_reg_value = 102;
3066 break;
bd60018a 3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3068 deemph_reg_value = 128;
3069 margin_reg_value = 154;
3070 /* FIXME extra to set for 1200 */
3071 break;
3072 default:
3073 return 0;
3074 }
3075 break;
bd60018a 3076 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3079 deemph_reg_value = 85;
3080 margin_reg_value = 78;
3081 break;
bd60018a 3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3083 deemph_reg_value = 85;
3084 margin_reg_value = 116;
3085 break;
bd60018a 3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3087 deemph_reg_value = 85;
3088 margin_reg_value = 154;
3089 break;
3090 default:
3091 return 0;
3092 }
3093 break;
bd60018a 3094 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3095 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3097 deemph_reg_value = 64;
3098 margin_reg_value = 104;
3099 break;
bd60018a 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3101 deemph_reg_value = 64;
3102 margin_reg_value = 154;
3103 break;
3104 default:
3105 return 0;
3106 }
3107 break;
bd60018a 3108 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3109 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3111 deemph_reg_value = 43;
3112 margin_reg_value = 154;
3113 break;
3114 default:
3115 return 0;
3116 }
3117 break;
3118 default:
3119 return 0;
3120 }
3121
3122 mutex_lock(&dev_priv->dpio_lock);
3123
3124 /* Clear calc init */
1966e59e
VS		 3125 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3126 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3127 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3128
3129 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3130 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3131 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3132
3133 /* Program swing deemph */
f72df8db
VS		 3134 for (i = 0; i < 4; i++) {
3135 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3136 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3137 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3138 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3139 }
e4a1d846
CML		 3140
3141 /* Program swing margin */
f72df8db
VS		 3142 for (i = 0; i < 4; i++) {
3143 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3144 val &= ~DPIO_SWING_MARGIN000_MASK;
3145 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3146 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3147 }
e4a1d846
CML		 3148
3149 /* Disable unique transition scale */
f72df8db
VS		 3150 for (i = 0; i < 4; i++) {
3151 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3152 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3153 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3154 }
e4a1d846
CML		 3155
3156 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3157 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3158 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3159 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3160
3161 /*
3162 * The document said it needs to set bit 27 for ch0 and bit 26
3163 * for ch1. Might be a typo in the doc.
3164 * For now, for this unique transition scale selection, set bit
3165 * 27 for ch0 and ch1.
3166 */
f72df8db
VS		 3167 for (i = 0; i < 4; i++) {
3168 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3169 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3170 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3171 }
e4a1d846 3172
f72df8db
VS		 3173 for (i = 0; i < 4; i++) {
3174 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3175 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3176 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3177 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3178 }
e4a1d846
CML		 3179 }
3180
3181 /* Start swing calculation */
1966e59e
VS		 3182 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3183 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3184 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3185
3186 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3187 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3188 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3189
3190 /* LRC Bypass */
3191 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3192 val |= DPIO_LRC_BYPASS;
3193 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3194
3195 mutex_unlock(&dev_priv->dpio_lock);
3196
3197 return 0;
3198}
3199
a4fc5ed6 3200static void
0301b3ac
JN		 3201intel_get_adjust_train(struct intel_dp *intel_dp,
3202 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3203{
3204 uint8_t v = 0;
3205 uint8_t p = 0;
3206 int lane;
1a2eb460
KP		 3207 uint8_t voltage_max;
3208 uint8_t preemph_max;
a4fc5ed6 3209
33a34e4e 3210 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3211 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3212 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3213
3214 if (this_v > v)
3215 v = this_v;
3216 if (this_p > p)
3217 p = this_p;
3218 }
3219
1a2eb460 3220 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3221 if (v >= voltage_max)
3222 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3223
1a2eb460
KP		 3224 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3225 if (p >= preemph_max)
3226 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3227
3228 for (lane = 0; lane < 4; lane++)
33a34e4e 3229 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3230}
3231
3232static uint32_t
f0a3424e 3233intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3234{
3cf2efb1 3235 uint32_t signal_levels = 0;
a4fc5ed6 3236
3cf2efb1 3237 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3239 default:
3240 signal_levels |= DP_VOLTAGE_0_4;
3241 break;
bd60018a 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3243 signal_levels |= DP_VOLTAGE_0_6;
3244 break;
bd60018a 3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3246 signal_levels |= DP_VOLTAGE_0_8;
3247 break;
bd60018a 3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3249 signal_levels |= DP_VOLTAGE_1_2;
3250 break;
3251 }
3cf2efb1 3252 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3253 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3254 default:
3255 signal_levels |= DP_PRE_EMPHASIS_0;
3256 break;
bd60018a 3257 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3258 signal_levels |= DP_PRE_EMPHASIS_3_5;
3259 break;
bd60018a 3260 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3261 signal_levels |= DP_PRE_EMPHASIS_6;
3262 break;
bd60018a 3263 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3264 signal_levels |= DP_PRE_EMPHASIS_9_5;
3265 break;
3266 }
3267 return signal_levels;
3268}
3269
e3421a18
ZW		 3270/* Gen6's DP voltage swing and pre-emphasis control */
3271static uint32_t
3272intel_gen6_edp_signal_levels(uint8_t train_set)
3273{
3c5a62b5
YL		 3274 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3275 DP_TRAIN_PRE_EMPHASIS_MASK);
3276 switch (signal_levels) {
bd60018a
SJ		 3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3279 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3281 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3284 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3287 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3290 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3291 default:
3c5a62b5
YL		 3292 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3293 "0x%x\n", signal_levels);
3294 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3295 }
3296}
3297
1a2eb460
KP		 3298/* Gen7's DP voltage swing and pre-emphasis control */
3299static uint32_t
3300intel_gen7_edp_signal_levels(uint8_t train_set)
3301{
3302 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3303 DP_TRAIN_PRE_EMPHASIS_MASK);
3304 switch (signal_levels) {
bd60018a 3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3306 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3308 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3310 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3311
bd60018a 3312 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3313 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3315 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3316
bd60018a 3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3318 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3319 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3320 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3321
3322 default:
3323 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3324 "0x%x\n", signal_levels);
3325 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3326 }
3327}
3328
d6c0d722
PZ		 3329/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3330static uint32_t
f0a3424e 3331intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3332{
d6c0d722
PZ		 3333 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3334 DP_TRAIN_PRE_EMPHASIS_MASK);
3335 switch (signal_levels) {
bd60018a 3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3337 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3339 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3341 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3343 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3344
bd60018a 3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3346 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3347 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3348 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3349 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3350 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3351
bd60018a 3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3353 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3354 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3355 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3356 default:
3357 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3358 "0x%x\n", signal_levels);
c5fe6a06 3359 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3360 }
a4fc5ed6
KP		 3361}
3362
f0a3424e
PZ		 3363/* Properly updates "DP" with the correct signal levels. */
3364static void
3365intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3366{
3367 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3368 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3369 struct drm_device *dev = intel_dig_port->base.base.dev;
3370 uint32_t signal_levels, mask;
3371 uint8_t train_set = intel_dp->train_set[0];
3372
5a9d1f1a 3373 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3374 signal_levels = intel_hsw_signal_levels(train_set);
3375 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3376 } else if (IS_CHERRYVIEW(dev)) {
3377 signal_levels = intel_chv_signal_levels(intel_dp);
3378 mask = 0;
e2fa6fba
P		 3379 } else if (IS_VALLEYVIEW(dev)) {
3380 signal_levels = intel_vlv_signal_levels(intel_dp);
3381 mask = 0;
bc7d38a4 3382 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3383 signal_levels = intel_gen7_edp_signal_levels(train_set);
3384 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3385 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3386 signal_levels = intel_gen6_edp_signal_levels(train_set);
3387 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3388 } else {
3389 signal_levels = intel_gen4_signal_levels(train_set);
3390 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3391 }
3392
3393 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3394
3395 *DP = (*DP & ~mask) | signal_levels;
3396}
3397
a4fc5ed6 3398static bool
ea5b213a 3399intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3400 uint32_t *DP,
58e10eb9 3401 uint8_t dp_train_pat)
a4fc5ed6 3402{
174edf1f
PZ		 3403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3404 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3405 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3406 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3407 int ret, len;
a4fc5ed6 3408
7b13b58a 3409 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3410
70aff66c 3411 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3412 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3413
2cdfe6c8
JN		 3414 buf[0] = dp_train_pat;
3415 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3416 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3417 /* don't write DP_TRAINING_LANEx_SET on disable */
3418 len = 1;
3419 } else {
3420 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3421 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3422 len = intel_dp->lane_count + 1;
47ea7542 3423 }
a4fc5ed6 3424
9d1a1031
JN		 3425 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3426 buf, len);
2cdfe6c8
JN		 3427
3428 return ret == len;
a4fc5ed6
KP		 3429}
3430
70aff66c
JN		 3431static bool
3432intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3433 uint8_t dp_train_pat)
3434{
953d22e8 3435 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3436 intel_dp_set_signal_levels(intel_dp, DP);
3437 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3438}
3439
3440static bool
3441intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3442 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3443{
3444 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3445 struct drm_device *dev = intel_dig_port->base.base.dev;
3446 struct drm_i915_private *dev_priv = dev->dev_private;
3447 int ret;
3448
3449 intel_get_adjust_train(intel_dp, link_status);
3450 intel_dp_set_signal_levels(intel_dp, DP);
3451
3452 I915_WRITE(intel_dp->output_reg, *DP);
3453 POSTING_READ(intel_dp->output_reg);
3454
9d1a1031
JN		 3455 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3456 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3457
3458 return ret == intel_dp->lane_count;
3459}
3460
3ab9c637
ID		 3461static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3462{
3463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3464 struct drm_device *dev = intel_dig_port->base.base.dev;
3465 struct drm_i915_private *dev_priv = dev->dev_private;
3466 enum port port = intel_dig_port->port;
3467 uint32_t val;
3468
3469 if (!HAS_DDI(dev))
3470 return;
3471
3472 val = I915_READ(DP_TP_CTL(port));
3473 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3474 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3475 I915_WRITE(DP_TP_CTL(port), val);
3476
3477 /*
3478 * On PORT_A we can have only eDP in SST mode. There the only reason
3479 * we need to set idle transmission mode is to work around a HW issue
3480 * where we enable the pipe while not in idle link-training mode.
3481 * In this case there is requirement to wait for a minimum number of
3482 * idle patterns to be sent.
3483 */
3484 if (port == PORT_A)
3485 return;
3486
3487 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3488 1))
3489 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3490}
3491
33a34e4e 3492/* Enable corresponding port and start training pattern 1 */
c19b0669 3493void
33a34e4e 3494intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3495{
da63a9f2 3496 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3497 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3498 int i;
3499 uint8_t voltage;
cdb0e95b 3500 int voltage_tries, loop_tries;
ea5b213a 3501 uint32_t DP = intel_dp->DP;
6aba5b6c 3502 uint8_t link_config[2];
a4fc5ed6 3503
affa9354 3504 if (HAS_DDI(dev))
c19b0669
PZ		 3505 intel_ddi_prepare_link_retrain(encoder);
3506
3cf2efb1 3507 /* Write the link configuration data */
6aba5b6c
JN		 3508 link_config[0] = intel_dp->link_bw;
3509 link_config[1] = intel_dp->lane_count;
3510 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3511 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3512 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3513
3514 link_config[0] = 0;
3515 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3516 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3517
3518 DP |= DP_PORT_EN;
1a2eb460 3519
70aff66c
JN		 3520 /* clock recovery */
3521 if (!intel_dp_reset_link_train(intel_dp, &DP,
3522 DP_TRAINING_PATTERN_1 |
3523 DP_LINK_SCRAMBLING_DISABLE)) {
3524 DRM_ERROR("failed to enable link training\n");
3525 return;
3526 }
3527
a4fc5ed6 3528 voltage = 0xff;
cdb0e95b
KP		 3529 voltage_tries = 0;
3530 loop_tries = 0;
a4fc5ed6 3531 for (;;) {
70aff66c 3532 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3533
a7c9655f 3534 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3535 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3536 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3537 break;
93f62dad 3538 }
a4fc5ed6 3539
01916270 3540 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3541 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3542 break;
3543 }
3544
3545 /* Check to see if we've tried the max voltage */
3546 for (i = 0; i < intel_dp->lane_count; i++)
3547 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3548 break;
3b4f819d 3549 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3550 ++loop_tries;
3551 if (loop_tries == 5) {
3def84b3 3552 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3553 break;
3554 }
70aff66c
JN		 3555 intel_dp_reset_link_train(intel_dp, &DP,
3556 DP_TRAINING_PATTERN_1 |
3557 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3558 voltage_tries = 0;
3559 continue;
3560 }
a4fc5ed6 3561
3cf2efb1 3562 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3563 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3564 ++voltage_tries;
b06fbda3 3565 if (voltage_tries == 5) {
3def84b3 3566 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3567 break;
3568 }
3569 } else
3570 voltage_tries = 0;
3571 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3572
70aff66c
JN		 3573 /* Update training set as requested by target */
3574 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3575 DRM_ERROR("failed to update link training\n");
3576 break;
3577 }
a4fc5ed6
KP		 3578 }
3579
33a34e4e
JB		 3580 intel_dp->DP = DP;
3581}
3582
c19b0669 3583void
33a34e4e
JB		 3584intel_dp_complete_link_train(struct intel_dp *intel_dp)
3585{
33a34e4e 3586 bool channel_eq = false;
37f80975 3587 int tries, cr_tries;
33a34e4e 3588 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3589 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3590
3591 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3592 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3593 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3594
a4fc5ed6 3595 /* channel equalization */
70aff66c 3596 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3597 training_pattern |
70aff66c
JN		 3598 DP_LINK_SCRAMBLING_DISABLE)) {
3599 DRM_ERROR("failed to start channel equalization\n");
3600 return;
3601 }
3602
a4fc5ed6 3603 tries = 0;
37f80975 3604 cr_tries = 0;
a4fc5ed6
KP		 3605 channel_eq = false;
3606 for (;;) {
70aff66c 3607 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3608
37f80975
JB		 3609 if (cr_tries > 5) {
3610 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3611 break;
3612 }
3613
a7c9655f 3614 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3615 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3616 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3617 break;
70aff66c 3618 }
a4fc5ed6 3619
37f80975 3620 /* Make sure clock is still ok */
01916270 3621 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3622 intel_dp_start_link_train(intel_dp);
70aff66c 3623 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3624 training_pattern |
70aff66c 3625 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3626 cr_tries++;
3627 continue;
3628 }
3629
1ffdff13 3630 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3631 channel_eq = true;
3632 break;
3633 }
a4fc5ed6 3634
37f80975
JB		 3635 /* Try 5 times, then try clock recovery if that fails */
3636 if (tries > 5) {
3637 intel_dp_link_down(intel_dp);
3638 intel_dp_start_link_train(intel_dp);
70aff66c 3639 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3640 training_pattern |
70aff66c 3641 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3642 tries = 0;
3643 cr_tries++;
3644 continue;
3645 }
a4fc5ed6 3646
70aff66c
JN		 3647 /* Update training set as requested by target */
3648 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3649 DRM_ERROR("failed to update link training\n");
3650 break;
3651 }
3cf2efb1 3652 ++tries;
869184a6 3653 }
3cf2efb1 3654
3ab9c637
ID		 3655 intel_dp_set_idle_link_train(intel_dp);
3656
3657 intel_dp->DP = DP;
3658
d6c0d722 3659 if (channel_eq)
07f42258 3660 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3661
3ab9c637
ID		 3662}
3663
3664void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3665{
70aff66c 3666 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3667 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3668}
3669
3670static void
ea5b213a 3671intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3672{
da63a9f2 3673 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3674 enum port port = intel_dig_port->port;
da63a9f2 3675 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3676 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3677 struct intel_crtc *intel_crtc =
3678 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3679 uint32_t DP = intel_dp->DP;
a4fc5ed6 3680
bc76e320 3681 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3682 return;
3683
0c33d8d7 3684 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3685 return;
3686
28c97730 3687 DRM_DEBUG_KMS("\n");
32f9d658 3688
bc7d38a4 3689 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3690 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3691 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3692 } else {
aad3d14d
VS		 3693 if (IS_CHERRYVIEW(dev))
3694 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3695 else
3696 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3697 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3698 }
fe255d00 3699 POSTING_READ(intel_dp->output_reg);
5eb08b69 3700
493a7081 3701 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3702 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3703 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3704
5bddd17f
EA		 3705 /* Hardware workaround: leaving our transcoder select
3706 * set to transcoder B while it's off will prevent the
3707 * corresponding HDMI output on transcoder A.
3708 *
3709 * Combine this with another hardware workaround:
3710 * transcoder select bit can only be cleared while the
3711 * port is enabled.
3712 */
3713 DP &= ~DP_PIPEB_SELECT;
3714 I915_WRITE(intel_dp->output_reg, DP);
3715
3716 /* Changes to enable or select take place the vblank
3717 * after being written.
3718 */
ff50afe9
DV		 3719 if (WARN_ON(crtc == NULL)) {
3720 /* We should never try to disable a port without a crtc
3721 * attached. For paranoia keep the code around for a
3722 * bit. */
31acbcc4
CW		 3723 POSTING_READ(intel_dp->output_reg);
3724 msleep(50);
3725 } else
ab527efc 3726 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3727 }
3728
832afda6 3729 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3730 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3731 POSTING_READ(intel_dp->output_reg);
f01eca2e 3732 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3733}
3734
26d61aad
KP		 3735static bool
3736intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3737{
a031d709
RV		 3738 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3739 struct drm_device *dev = dig_port->base.base.dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741
9d1a1031
JN		 3742 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3743 sizeof(intel_dp->dpcd)) < 0)
edb39244 3744 return false; /* aux transfer failed */
92fd8fd1 3745
a8e98153 3746 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3747
edb39244
AJ		 3748 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3749 return false; /* DPCD not present */
3750
2293bb5c
SK		 3751 /* Check if the panel supports PSR */
3752 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3753 if (is_edp(intel_dp)) {
9d1a1031
JN		 3754 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3755 intel_dp->psr_dpcd,
3756 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3757 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3758 dev_priv->psr.sink_support = true;
50003939 3759 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3760 }
50003939
JN		 3761 }
3762
06ea66b6
TP		 3763 /* Training Pattern 3 support */
3764 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3765 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3766 intel_dp->use_tps3 = true;
3767 DRM_DEBUG_KMS("Displayport TPS3 supported");
3768 } else
3769 intel_dp->use_tps3 = false;
3770
edb39244
AJ		 3771 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3772 DP_DWN_STRM_PORT_PRESENT))
3773 return true; /* native DP sink */
3774
3775 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3776 return true; /* no per-port downstream info */
3777
9d1a1031
JN		 3778 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3779 intel_dp->downstream_ports,
3780 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3781 return false; /* downstream port status fetch failed */
3782
3783 return true;
92fd8fd1
KP		 3784}
3785
0d198328
AJ		 3786static void
3787intel_dp_probe_oui(struct intel_dp *intel_dp)
3788{
3789 u8 buf[3];
3790
3791 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3792 return;
3793
24f3e092 3794 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3795
9d1a1031 3796 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3797 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3798 buf[0], buf[1], buf[2]);
3799
9d1a1031 3800 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3801 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3802 buf[0], buf[1], buf[2]);
351cfc34 3803
1e0560e0 3804 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3805}
3806
0e32b39c
DA		 3807static bool
3808intel_dp_probe_mst(struct intel_dp *intel_dp)
3809{
3810 u8 buf[1];
3811
3812 if (!intel_dp->can_mst)
3813 return false;
3814
3815 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3816 return false;
3817
d337a341 3818 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3819 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3820 if (buf[0] & DP_MST_CAP) {
3821 DRM_DEBUG_KMS("Sink is MST capable\n");
3822 intel_dp->is_mst = true;
3823 } else {
3824 DRM_DEBUG_KMS("Sink is not MST capable\n");
3825 intel_dp->is_mst = false;
3826 }
3827 }
1e0560e0 3828 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3829
3830 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3831 return intel_dp->is_mst;
3832}
3833
d2e216d0
RV		 3834int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3835{
3836 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3837 struct drm_device *dev = intel_dig_port->base.base.dev;
3838 struct intel_crtc *intel_crtc =
3839 to_intel_crtc(intel_dig_port->base.base.crtc);
3840 u8 buf[1];
3841
9d1a1031 3842 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3843 return -EAGAIN;
3844
3845 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3846 return -ENOTTY;
3847
9d1a1031
JN		 3848 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3849 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3850 return -EAGAIN;
3851
3852 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3853 intel_wait_for_vblank(dev, intel_crtc->pipe);
3854 intel_wait_for_vblank(dev, intel_crtc->pipe);
3855
9d1a1031 3856 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3857 return -EAGAIN;
3858
9d1a1031 3859 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3860 return 0;
3861}
3862
a60f0e38
JB		 3863static bool
3864intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3865{
9d1a1031
JN		 3866 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3867 DP_DEVICE_SERVICE_IRQ_VECTOR,
3868 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3869}
3870
0e32b39c
DA		 3871static bool
3872intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3873{
3874 int ret;
3875
3876 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3877 DP_SINK_COUNT_ESI,
3878 sink_irq_vector, 14);
3879 if (ret != 14)
3880 return false;
3881
3882 return true;
3883}
3884
a60f0e38
JB		 3885static void
3886intel_dp_handle_test_request(struct intel_dp *intel_dp)
3887{
3888 /* NAK by default */
9d1a1031 3889 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3890}
3891
0e32b39c
DA		 3892static int
3893intel_dp_check_mst_status(struct intel_dp *intel_dp)
3894{
3895 bool bret;
3896
3897 if (intel_dp->is_mst) {
3898 u8 esi[16] = { 0 };
3899 int ret = 0;
3900 int retry;
3901 bool handled;
3902 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3903go_again:
3904 if (bret == true) {
3905
3906 /* check link status - esi[10] = 0x200c */
3907 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3908 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3909 intel_dp_start_link_train(intel_dp);
3910 intel_dp_complete_link_train(intel_dp);
3911 intel_dp_stop_link_train(intel_dp);
3912 }
3913
3914 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3915 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3916
3917 if (handled) {
3918 for (retry = 0; retry < 3; retry++) {
3919 int wret;
3920 wret = drm_dp_dpcd_write(&intel_dp->aux,
3921 DP_SINK_COUNT_ESI+1,
3922 &esi[1], 3);
3923 if (wret == 3) {
3924 break;
3925 }
3926 }
3927
3928 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3929 if (bret == true) {
3930 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3931 goto go_again;
3932 }
3933 } else
3934 ret = 0;
3935
3936 return ret;
3937 } else {
3938 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3939 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3940 intel_dp->is_mst = false;
3941 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3942 /* send a hotplug event */
3943 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3944 }
3945 }
3946 return -EINVAL;
3947}
3948
a4fc5ed6
KP		 3949/*
3950 * According to DP spec
3951 * 5.1.2:
3952 * 1. Read DPCD
3953 * 2. Configure link according to Receiver Capabilities
3954 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3955 * 4. Check link status on receipt of hot-plug interrupt
3956 */
00c09d70 3957void
ea5b213a 3958intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3959{
5b215bcf 3960 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3961 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3962 u8 sink_irq_vector;
93f62dad 3963 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3964
5b215bcf
DA		 3965 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3966
da63a9f2 3967 if (!intel_encoder->connectors_active)
d2b996ac 3968 return;
59cd09e1 3969
da63a9f2 3970 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3971 return;
3972
1a125d8a
ID		 3973 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3974 return;
3975
92fd8fd1 3976 /* Try to read receiver status if the link appears to be up */
93f62dad 3977 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3978 return;
3979 }
3980
92fd8fd1 3981 /* Now read the DPCD to see if it's actually running */
26d61aad 3982 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3983 return;
3984 }
3985
a60f0e38
JB		 3986 /* Try to read the source of the interrupt */
3987 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3988 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3989 /* Clear interrupt source */
9d1a1031
JN		 3990 drm_dp_dpcd_writeb(&intel_dp->aux,
3991 DP_DEVICE_SERVICE_IRQ_VECTOR,
3992 sink_irq_vector);
a60f0e38
JB		 3993
3994 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3995 intel_dp_handle_test_request(intel_dp);
3996 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3997 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3998 }
3999
1ffdff13 4000 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4001 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4002 intel_encoder->base.name);
33a34e4e
JB		 4003 intel_dp_start_link_train(intel_dp);
4004 intel_dp_complete_link_train(intel_dp);
3ab9c637 4005 intel_dp_stop_link_train(intel_dp);
33a34e4e 4006 }
a4fc5ed6 4007}
a4fc5ed6 4008
caf9ab24 4009/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4010static enum drm_connector_status
26d61aad 4011intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4012{
caf9ab24 4013 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4014 uint8_t type;
4015
4016 if (!intel_dp_get_dpcd(intel_dp))
4017 return connector_status_disconnected;
4018
4019 /* if there's no downstream port, we're done */
4020 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4021 return connector_status_connected;
caf9ab24
AJ		 4022
4023 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4024 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4025 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4026 uint8_t reg;
9d1a1031
JN		 4027
4028 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4029 &reg, 1) < 0)
caf9ab24 4030 return connector_status_unknown;
9d1a1031 4031
23235177
AJ		 4032 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4033 : connector_status_disconnected;
caf9ab24
AJ		 4034 }
4035
4036 /* If no HPD, poke DDC gently */
0b99836f 4037 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4038 return connector_status_connected;
caf9ab24
AJ		 4039
4040 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4041 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4042 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4043 if (type == DP_DS_PORT_TYPE_VGA ||
4044 type == DP_DS_PORT_TYPE_NON_EDID)
4045 return connector_status_unknown;
4046 } else {
4047 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4048 DP_DWN_STRM_PORT_TYPE_MASK;
4049 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4050 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4051 return connector_status_unknown;
4052 }
caf9ab24
AJ		 4053
4054 /* Anything else is out of spec, warn and ignore */
4055 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4056 return connector_status_disconnected;
71ba9000
AJ		 4057}
4058
d410b56d
CW		 4059static enum drm_connector_status
4060edp_detect(struct intel_dp *intel_dp)
4061{
4062 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4063 enum drm_connector_status status;
4064
4065 status = intel_panel_detect(dev);
4066 if (status == connector_status_unknown)
4067 status = connector_status_connected;
4068
4069 return status;
4070}
4071
5eb08b69 4072static enum drm_connector_status
a9756bb5 4073ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4074{
30add22d 4075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4078
1b469639
DL		 4079 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4080 return connector_status_disconnected;
4081
26d61aad 4082 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4083}
4084
2a592bec
DA		 4085static int g4x_digital_port_connected(struct drm_device *dev,
4086 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4087{
a4fc5ed6 4088 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4089 uint32_t bit;
5eb08b69 4090
232a6ee9
TP		 4091 if (IS_VALLEYVIEW(dev)) {
4092 switch (intel_dig_port->port) {
4093 case PORT_B:
4094 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4095 break;
4096 case PORT_C:
4097 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4098 break;
4099 case PORT_D:
4100 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4101 break;
4102 default:
2a592bec 4103 return -EINVAL;
232a6ee9
TP		 4104 }
4105 } else {
4106 switch (intel_dig_port->port) {
4107 case PORT_B:
4108 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4109 break;
4110 case PORT_C:
4111 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4112 break;
4113 case PORT_D:
4114 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4115 break;
4116 default:
2a592bec 4117 return -EINVAL;
232a6ee9 4118 }
a4fc5ed6
KP		 4119 }
4120
10f76a38 4121 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4122 return 0;
4123 return 1;
4124}
4125
4126static enum drm_connector_status
4127g4x_dp_detect(struct intel_dp *intel_dp)
4128{
4129 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4130 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4131 int ret;
4132
4133 /* Can't disconnect eDP, but you can close the lid... */
4134 if (is_edp(intel_dp)) {
4135 enum drm_connector_status status;
4136
4137 status = intel_panel_detect(dev);
4138 if (status == connector_status_unknown)
4139 status = connector_status_connected;
4140 return status;
4141 }
4142
4143 ret = g4x_digital_port_connected(dev, intel_dig_port);
4144 if (ret == -EINVAL)
4145 return connector_status_unknown;
4146 else if (ret == 0)
a4fc5ed6
KP		 4147 return connector_status_disconnected;
4148
26d61aad 4149 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4150}
4151
8c241fef 4152static struct edid *
beb60608 4153intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4154{
beb60608 4155 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4156
9cd300e0
JN		 4157 /* use cached edid if we have one */
4158 if (intel_connector->edid) {
9cd300e0
JN		 4159 /* invalid edid */
4160 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4161 return NULL;
4162
55e9edeb 4163 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4164 } else
4165 return drm_get_edid(&intel_connector->base,
4166 &intel_dp->aux.ddc);
4167}
8c241fef 4168
beb60608
CW		 4169static void
4170intel_dp_set_edid(struct intel_dp *intel_dp)
4171{
4172 struct intel_connector *intel_connector = intel_dp->attached_connector;
4173 struct edid *edid;
8c241fef 4174
beb60608
CW		 4175 edid = intel_dp_get_edid(intel_dp);
4176 intel_connector->detect_edid = edid;
4177
4178 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4179 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4180 else
4181 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4182}
4183
beb60608
CW		 4184static void
4185intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4186{
beb60608 4187 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4188
beb60608
CW		 4189 kfree(intel_connector->detect_edid);
4190 intel_connector->detect_edid = NULL;
9cd300e0 4191
beb60608
CW		 4192 intel_dp->has_audio = false;
4193}
d6f24d0f 4194
beb60608
CW		 4195static enum intel_display_power_domain
4196intel_dp_power_get(struct intel_dp *dp)
4197{
4198 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4199 enum intel_display_power_domain power_domain;
4200
4201 power_domain = intel_display_port_power_domain(encoder);
4202 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4203
4204 return power_domain;
4205}
d6f24d0f 4206
beb60608
CW		 4207static void
4208intel_dp_power_put(struct intel_dp *dp,
4209 enum intel_display_power_domain power_domain)
4210{
4211 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4212 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4213}
4214
a9756bb5
ZW		 4215static enum drm_connector_status
4216intel_dp_detect(struct drm_connector *connector, bool force)
4217{
4218 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4220 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4221 struct drm_device *dev = connector->dev;
a9756bb5 4222 enum drm_connector_status status;
671dedd2 4223 enum intel_display_power_domain power_domain;
0e32b39c 4224 bool ret;
a9756bb5 4225
164c8598 4226 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4227 connector->base.id, connector->name);
beb60608 4228 intel_dp_unset_edid(intel_dp);
164c8598 4229
0e32b39c
DA		 4230 if (intel_dp->is_mst) {
4231 /* MST devices are disconnected from a monitor POV */
4232 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4233 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4234 return connector_status_disconnected;
0e32b39c
DA		 4235 }
4236
beb60608 4237 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4238
d410b56d
CW		 4239 /* Can't disconnect eDP, but you can close the lid... */
4240 if (is_edp(intel_dp))
4241 status = edp_detect(intel_dp);
4242 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4243 status = ironlake_dp_detect(intel_dp);
4244 else
4245 status = g4x_dp_detect(intel_dp);
4246 if (status != connector_status_connected)
c8c8fb33 4247 goto out;
a9756bb5 4248
0d198328
AJ		 4249 intel_dp_probe_oui(intel_dp);
4250
0e32b39c
DA		 4251 ret = intel_dp_probe_mst(intel_dp);
4252 if (ret) {
4253 /* if we are in MST mode then this connector
4254 won't appear connected or have anything with EDID on it */
4255 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4256 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4257 status = connector_status_disconnected;
4258 goto out;
4259 }
4260
beb60608 4261 intel_dp_set_edid(intel_dp);
a9756bb5 4262
d63885da
PZ		 4263 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4264 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4265 status = connector_status_connected;
4266
4267out:
beb60608 4268 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4269 return status;
a4fc5ed6
KP		 4270}
4271
beb60608
CW		 4272static void
4273intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4274{
df0e9248 4275 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4276 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4277 enum intel_display_power_domain power_domain;
a4fc5ed6 4278
beb60608
CW		 4279 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4280 connector->base.id, connector->name);
4281 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4282
beb60608
CW		 4283 if (connector->status != connector_status_connected)
4284 return;
671dedd2 4285
beb60608
CW		 4286 power_domain = intel_dp_power_get(intel_dp);
4287
4288 intel_dp_set_edid(intel_dp);
4289
4290 intel_dp_power_put(intel_dp, power_domain);
4291
4292 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4293 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4294}
4295
4296static int intel_dp_get_modes(struct drm_connector *connector)
4297{
4298 struct intel_connector *intel_connector = to_intel_connector(connector);
4299 struct edid *edid;
4300
4301 edid = intel_connector->detect_edid;
4302 if (edid) {
4303 int ret = intel_connector_update_modes(connector, edid);
4304 if (ret)
4305 return ret;
4306 }
32f9d658 4307
f8779fda 4308 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4309 if (is_edp(intel_attached_dp(connector)) &&
4310 intel_connector->panel.fixed_mode) {
f8779fda 4311 struct drm_display_mode *mode;
beb60608
CW		 4312
4313 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4314 intel_connector->panel.fixed_mode);
f8779fda 4315 if (mode) {
32f9d658
ZW		 4316 drm_mode_probed_add(connector, mode);
4317 return 1;
4318 }
4319 }
beb60608 4320
32f9d658 4321 return 0;
a4fc5ed6
KP		 4322}
4323
1aad7ac0
CW		 4324static bool
4325intel_dp_detect_audio(struct drm_connector *connector)
4326{
1aad7ac0 4327 bool has_audio = false;
beb60608 4328 struct edid *edid;
1aad7ac0 4329
beb60608
CW		 4330 edid = to_intel_connector(connector)->detect_edid;
4331 if (edid)
1aad7ac0 4332 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4333
1aad7ac0
CW		 4334 return has_audio;
4335}
4336
f684960e
CW		 4337static int
4338intel_dp_set_property(struct drm_connector *connector,
4339 struct drm_property *property,
4340 uint64_t val)
4341{
e953fd7b 4342 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4343 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4344 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4345 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4346 int ret;
4347
662595df 4348 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4349 if (ret)
4350 return ret;
4351
3f43c48d 4352 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4353 int i = val;
4354 bool has_audio;
4355
4356 if (i == intel_dp->force_audio)
f684960e
CW		 4357 return 0;
4358
1aad7ac0 4359 intel_dp->force_audio = i;
f684960e 4360
c3e5f67b 4361 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4362 has_audio = intel_dp_detect_audio(connector);
4363 else
c3e5f67b 4364 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4365
4366 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4367 return 0;
4368
1aad7ac0 4369 intel_dp->has_audio = has_audio;
f684960e
CW		 4370 goto done;
4371 }
4372
e953fd7b 4373 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4374 bool old_auto = intel_dp->color_range_auto;
4375 uint32_t old_range = intel_dp->color_range;
4376
55bc60db
VS		 4377 switch (val) {
4378 case INTEL_BROADCAST_RGB_AUTO:
4379 intel_dp->color_range_auto = true;
4380 break;
4381 case INTEL_BROADCAST_RGB_FULL:
4382 intel_dp->color_range_auto = false;
4383 intel_dp->color_range = 0;
4384 break;
4385 case INTEL_BROADCAST_RGB_LIMITED:
4386 intel_dp->color_range_auto = false;
4387 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4388 break;
4389 default:
4390 return -EINVAL;
4391 }
ae4edb80
DV		 4392
4393 if (old_auto == intel_dp->color_range_auto &&
4394 old_range == intel_dp->color_range)
4395 return 0;
4396
e953fd7b
CW		 4397 goto done;
4398 }
4399
53b41837
YN		 4400 if (is_edp(intel_dp) &&
4401 property == connector->dev->mode_config.scaling_mode_property) {
4402 if (val == DRM_MODE_SCALE_NONE) {
4403 DRM_DEBUG_KMS("no scaling not supported\n");
4404 return -EINVAL;
4405 }
4406
4407 if (intel_connector->panel.fitting_mode == val) {
4408 /* the eDP scaling property is not changed */
4409 return 0;
4410 }
4411 intel_connector->panel.fitting_mode = val;
4412
4413 goto done;
4414 }
4415
f684960e
CW		 4416 return -EINVAL;
4417
4418done:
c0c36b94
CW		 4419 if (intel_encoder->base.crtc)
4420 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4421
4422 return 0;
4423}
4424
a4fc5ed6 4425static void
73845adf 4426intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4427{
1d508706 4428 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4429
beb60608
CW		 4430 intel_dp_unset_edid(intel_attached_dp(connector));
4431
9cd300e0
JN		 4432 if (!IS_ERR_OR_NULL(intel_connector->edid))
4433 kfree(intel_connector->edid);
4434
acd8db10
PZ		 4435 /* Can't call is_edp() since the encoder may have been destroyed
4436 * already. */
4437 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4438 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4439
a4fc5ed6 4440 drm_connector_cleanup(connector);
55f78c43 4441 kfree(connector);
a4fc5ed6
KP		 4442}
4443
00c09d70 4444void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4445{
da63a9f2
PZ		 4446 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4447 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4448
4f71d0cb 4449 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4450 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4451 drm_encoder_cleanup(encoder);
bd943159
KP		 4452 if (is_edp(intel_dp)) {
4453 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4454 /*
4455 * vdd might still be enabled do to the delayed vdd off.
4456 * Make sure vdd is actually turned off here.
4457 */
773538e8 4458 pps_lock(intel_dp);
4be73780 4459 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4460 pps_unlock(intel_dp);
4461
01527b31
CT		 4462 if (intel_dp->edp_notifier.notifier_call) {
4463 unregister_reboot_notifier(&intel_dp->edp_notifier);
4464 intel_dp->edp_notifier.notifier_call = NULL;
4465 }
bd943159 4466 }
da63a9f2 4467 kfree(intel_dig_port);
24d05927
DV		 4468}
4469
07f9cd0b
ID		 4470static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4471{
4472 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4473
4474 if (!is_edp(intel_dp))
4475 return;
4476
951468f3
VS		 4477 /*
4478 * vdd might still be enabled do to the delayed vdd off.
4479 * Make sure vdd is actually turned off here.
4480 */
773538e8 4481 pps_lock(intel_dp);
07f9cd0b 4482 edp_panel_vdd_off_sync(intel_dp);
773538e8 4483 pps_unlock(intel_dp);
07f9cd0b
ID		 4484}
4485
6d93c0c4
ID		 4486static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4487{
4488 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4489}
4490
a4fc5ed6 4491static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4492 .dpms = intel_connector_dpms,
a4fc5ed6 4493 .detect = intel_dp_detect,
beb60608 4494 .force = intel_dp_force,
a4fc5ed6 4495 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4496 .set_property = intel_dp_set_property,
73845adf 4497 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4498};
4499
4500static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4501 .get_modes = intel_dp_get_modes,
4502 .mode_valid = intel_dp_mode_valid,
df0e9248 4503 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4504};
4505
a4fc5ed6 4506static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4507 .reset = intel_dp_encoder_reset,
24d05927 4508 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4509};
4510
0e32b39c 4511void
21d40d37 4512intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4513{
0e32b39c 4514 return;
c8110e52 4515}
6207937d 4516
13cf5504
DA		 4517bool
4518intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4519{
4520 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4521 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4522 struct drm_device *dev = intel_dig_port->base.base.dev;
4523 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4524 enum intel_display_power_domain power_domain;
4525 bool ret = true;
4526
0e32b39c
DA		 4527 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4528 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4529
26fbb774
VS		 4530 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4531 port_name(intel_dig_port->port),
0e32b39c 4532 long_hpd ? "long" : "short");
13cf5504 4533
1c767b33
ID		 4534 power_domain = intel_display_port_power_domain(intel_encoder);
4535 intel_display_power_get(dev_priv, power_domain);
4536
0e32b39c 4537 if (long_hpd) {
2a592bec
DA		 4538
4539 if (HAS_PCH_SPLIT(dev)) {
4540 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4541 goto mst_fail;
4542 } else {
4543 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4544 goto mst_fail;
4545 }
0e32b39c
DA		 4546
4547 if (!intel_dp_get_dpcd(intel_dp)) {
4548 goto mst_fail;
4549 }
4550
4551 intel_dp_probe_oui(intel_dp);
4552
4553 if (!intel_dp_probe_mst(intel_dp))
4554 goto mst_fail;
4555
4556 } else {
4557 if (intel_dp->is_mst) {
1c767b33 4558 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4559 goto mst_fail;
4560 }
4561
4562 if (!intel_dp->is_mst) {
4563 /*
4564 * we'll check the link status via the normal hot plug path later -
4565 * but for short hpds we should check it now
4566 */
5b215bcf 4567 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4568 intel_dp_check_link_status(intel_dp);
5b215bcf 4569 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4570 }
4571 }
1c767b33
ID		 4572 ret = false;
4573 goto put_power;
0e32b39c
DA		 4574mst_fail:
4575 /* if we were in MST mode, and device is not there get out of MST mode */
4576 if (intel_dp->is_mst) {
4577 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4578 intel_dp->is_mst = false;
4579 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4580 }
1c767b33
ID		 4581put_power:
4582 intel_display_power_put(dev_priv, power_domain);
4583
4584 return ret;
13cf5504
DA		 4585}
4586
e3421a18
ZW		 4587/* Return which DP Port should be selected for Transcoder DP control */
4588int
0206e353 4589intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4590{
4591 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4592 struct intel_encoder *intel_encoder;
4593 struct intel_dp *intel_dp;
e3421a18 4594
fa90ecef
PZ		 4595 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4596 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4597
fa90ecef
PZ		 4598 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4599 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4600 return intel_dp->output_reg;
e3421a18 4601 }
ea5b213a 4602
e3421a18
ZW		 4603 return -1;
4604}
4605
36e83a18 4606/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4607bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4608{
4609 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4610 union child_device_config *p_child;
36e83a18 4611 int i;
5d8a7752
VS		 4612 static const short port_mapping[] = {
4613 [PORT_B] = PORT_IDPB,
4614 [PORT_C] = PORT_IDPC,
4615 [PORT_D] = PORT_IDPD,
4616 };
36e83a18 4617
3b32a35b
VS		 4618 if (port == PORT_A)
4619 return true;
4620
41aa3448 4621 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4622 return false;
4623
41aa3448
RV		 4624 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4625 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4626
5d8a7752 4627 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4628 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4629 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4630 return true;
4631 }
4632 return false;
4633}
4634
0e32b39c 4635void
f684960e
CW		 4636intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4637{
53b41837
YN		 4638 struct intel_connector *intel_connector = to_intel_connector(connector);
4639
3f43c48d 4640 intel_attach_force_audio_property(connector);
e953fd7b 4641 intel_attach_broadcast_rgb_property(connector);
55bc60db 4642 intel_dp->color_range_auto = true;
53b41837
YN		 4643
4644 if (is_edp(intel_dp)) {
4645 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4646 drm_object_attach_property(
4647 &connector->base,
53b41837 4648 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4649 DRM_MODE_SCALE_ASPECT);
4650 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4651 }
f684960e
CW		 4652}
4653
dada1a9f
ID		 4654static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4655{
4656 intel_dp->last_power_cycle = jiffies;
4657 intel_dp->last_power_on = jiffies;
4658 intel_dp->last_backlight_off = jiffies;
4659}
4660
67a54566
DV		 4661static void
4662intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4663 struct intel_dp *intel_dp,
4664 struct edp_power_seq *out)
67a54566
DV		 4665{
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 struct edp_power_seq cur, vbt, spec, final;
4668 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4669 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4670
e39b999a
VS		 4671 lockdep_assert_held(&dev_priv->pps_mutex);
4672
453c5420 4673 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4674 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4675 pp_on_reg = PCH_PP_ON_DELAYS;
4676 pp_off_reg = PCH_PP_OFF_DELAYS;
4677 pp_div_reg = PCH_PP_DIVISOR;
4678 } else {
bf13e81b
JN		 4679 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4680
4681 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4682 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4683 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4684 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4685 }
67a54566
DV		 4686
4687 /* Workaround: Need to write PP_CONTROL with the unlock key as
4688 * the very first thing. */
453c5420 4689 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4690 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4691
453c5420
JB		 4692 pp_on = I915_READ(pp_on_reg);
4693 pp_off = I915_READ(pp_off_reg);
4694 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4695
4696 /* Pull timing values out of registers */
4697 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4698 PANEL_POWER_UP_DELAY_SHIFT;
4699
4700 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4701 PANEL_LIGHT_ON_DELAY_SHIFT;
4702
4703 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4704 PANEL_LIGHT_OFF_DELAY_SHIFT;
4705
4706 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4707 PANEL_POWER_DOWN_DELAY_SHIFT;
4708
4709 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4710 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4711
4712 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4713 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4714
41aa3448 4715 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4716
4717 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4718 * our hw here, which are all in 100usec. */
4719 spec.t1_t3 = 210 * 10;
4720 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4721 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4722 spec.t10 = 500 * 10;
4723 /* This one is special and actually in units of 100ms, but zero
4724 * based in the hw (so we need to add 100 ms). But the sw vbt
4725 * table multiplies it with 1000 to make it in units of 100usec,
4726 * too. */
4727 spec.t11_t12 = (510 + 100) * 10;
4728
4729 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4730 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4731
4732 /* Use the max of the register settings and vbt. If both are
4733 * unset, fall back to the spec limits. */
4734#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4735 spec.field : \
4736 max(cur.field, vbt.field))
4737 assign_final(t1_t3);
4738 assign_final(t8);
4739 assign_final(t9);
4740 assign_final(t10);
4741 assign_final(t11_t12);
4742#undef assign_final
4743
4744#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4745 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4746 intel_dp->backlight_on_delay = get_delay(t8);
4747 intel_dp->backlight_off_delay = get_delay(t9);
4748 intel_dp->panel_power_down_delay = get_delay(t10);
4749 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4750#undef get_delay
4751
f30d26e4
JN		 4752 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4753 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4754 intel_dp->panel_power_cycle_delay);
4755
4756 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4757 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4758
4759 if (out)
4760 *out = final;
4761}
4762
4763static void
4764intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4765 struct intel_dp *intel_dp,
4766 struct edp_power_seq *seq)
4767{
4768 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4769 u32 pp_on, pp_off, pp_div, port_sel = 0;
4770 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4771 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4772 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4773
e39b999a 4774 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4775
4776 if (HAS_PCH_SPLIT(dev)) {
4777 pp_on_reg = PCH_PP_ON_DELAYS;
4778 pp_off_reg = PCH_PP_OFF_DELAYS;
4779 pp_div_reg = PCH_PP_DIVISOR;
4780 } else {
bf13e81b
JN		 4781 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4782
4783 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4784 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4785 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4786 }
4787
b2f19d1a
PZ		 4788 /*
4789 * And finally store the new values in the power sequencer. The
4790 * backlight delays are set to 1 because we do manual waits on them. For
4791 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4792 * we'll end up waiting for the backlight off delay twice: once when we
4793 * do the manual sleep, and once when we disable the panel and wait for
4794 * the PP_STATUS bit to become zero.
4795 */
f30d26e4 4796 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4797 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4798 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4799 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4800 /* Compute the divisor for the pp clock, simply match the Bspec
4801 * formula. */
453c5420 4802 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4803 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4804 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4805
4806 /* Haswell doesn't have any port selection bits for the panel
4807 * power sequencer any more. */
bc7d38a4 4808 if (IS_VALLEYVIEW(dev)) {
ad933b56 4809 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4810 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4811 if (port == PORT_A)
a24c144c 4812 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4813 else
a24c144c 4814 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4815 }
4816
453c5420
JB		 4817 pp_on |= port_sel;
4818
4819 I915_WRITE(pp_on_reg, pp_on);
4820 I915_WRITE(pp_off_reg, pp_off);
4821 I915_WRITE(pp_div_reg, pp_div);
67a54566 4822
67a54566 4823 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4824 I915_READ(pp_on_reg),
4825 I915_READ(pp_off_reg),
4826 I915_READ(pp_div_reg));
f684960e
CW		 4827}
4828
439d7ac0
PB		 4829void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4830{
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 struct intel_encoder *encoder;
4833 struct intel_dp *intel_dp = NULL;
4834 struct intel_crtc_config *config = NULL;
4835 struct intel_crtc *intel_crtc = NULL;
4836 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4837 u32 reg, val;
4838 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4839
4840 if (refresh_rate <= 0) {
4841 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4842 return;
4843 }
4844
4845 if (intel_connector == NULL) {
4846 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4847 return;
4848 }
4849
1fcc9d1c
DV		 4850 /*
4851 * FIXME: This needs proper synchronization with psr state. But really
4852 * hard to tell without seeing the user of this function of this code.
4853 * Check locking and ordering once that lands.
4854 */
439d7ac0
PB		 4855 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4856 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4857 return;
4858 }
4859
4860 encoder = intel_attached_encoder(&intel_connector->base);
4861 intel_dp = enc_to_intel_dp(&encoder->base);
4862 intel_crtc = encoder->new_crtc;
4863
4864 if (!intel_crtc) {
4865 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4866 return;
4867 }
4868
4869 config = &intel_crtc->config;
4870
4871 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4872 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4873 return;
4874 }
4875
4876 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4877 index = DRRS_LOW_RR;
4878
4879 if (index == intel_dp->drrs_state.refresh_rate_type) {
4880 DRM_DEBUG_KMS(
4881 "DRRS requested for previously set RR...ignoring\n");
4882 return;
4883 }
4884
4885 if (!intel_crtc->active) {
4886 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4887 return;
4888 }
4889
4890 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4891 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4892 val = I915_READ(reg);
4893 if (index > DRRS_HIGH_RR) {
4894 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4895 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4896 } else {
4897 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4898 }
4899 I915_WRITE(reg, val);
4900 }
4901
4902 /*
4903 * mutex taken to ensure that there is no race between differnt
4904 * drrs calls trying to update refresh rate. This scenario may occur
4905 * in future when idleness detection based DRRS in kernel and
4906 * possible calls from user space to set differnt RR are made.
4907 */
4908
4909 mutex_lock(&intel_dp->drrs_state.mutex);
4910
4911 intel_dp->drrs_state.refresh_rate_type = index;
4912
4913 mutex_unlock(&intel_dp->drrs_state.mutex);
4914
4915 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4916}
4917
4f9db5b5
PB		 4918static struct drm_display_mode *
4919intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4920 struct intel_connector *intel_connector,
4921 struct drm_display_mode *fixed_mode)
4922{
4923 struct drm_connector *connector = &intel_connector->base;
4924 struct intel_dp *intel_dp = &intel_dig_port->dp;
4925 struct drm_device *dev = intel_dig_port->base.base.dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 struct drm_display_mode *downclock_mode = NULL;
4928
4929 if (INTEL_INFO(dev)->gen <= 6) {
4930 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4931 return NULL;
4932 }
4933
4934 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4935 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4936 return NULL;
4937 }
4938
4939 downclock_mode = intel_find_panel_downclock
4940 (dev, fixed_mode, connector);
4941
4942 if (!downclock_mode) {
4079b8d1 4943 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4944 return NULL;
4945 }
4946
439d7ac0
PB		 4947 dev_priv->drrs.connector = intel_connector;
4948
4949 mutex_init(&intel_dp->drrs_state.mutex);
4950
4f9db5b5
PB		 4951 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4952
4953 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4954 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4955 return downclock_mode;
4956}
4957
aba86890
ID		 4958void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4959{
4960 struct drm_device *dev = intel_encoder->base.dev;
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 struct intel_dp *intel_dp;
4963 enum intel_display_power_domain power_domain;
4964
4965 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4966 return;
4967
4968 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4969
4970 pps_lock(intel_dp);
4971
aba86890 4972 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4973 goto out;
aba86890
ID		 4974 /*
4975 * The VDD bit needs a power domain reference, so if the bit is
4976 * already enabled when we boot or resume, grab this reference and
4977 * schedule a vdd off, so we don't hold on to the reference
4978 * indefinitely.
4979 */
4980 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4981 power_domain = intel_display_port_power_domain(intel_encoder);
4982 intel_display_power_get(dev_priv, power_domain);
4983
4984 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4985 out:
773538e8 4986 pps_unlock(intel_dp);
aba86890
ID		 4987}
4988
ed92f0b2 4989static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4990 struct intel_connector *intel_connector,
4991 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4992{
4993 struct drm_connector *connector = &intel_connector->base;
4994 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4995 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4996 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4999 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5000 bool has_dpcd;
5001 struct drm_display_mode *scan;
5002 struct edid *edid;
5003
4f9db5b5
PB		 5004 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5005
ed92f0b2
PZ		 5006 if (!is_edp(intel_dp))
5007 return true;
5008
aba86890 5009 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5010
ed92f0b2 5011 /* Cache DPCD and EDID for edp. */
24f3e092 5012 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 5013 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 5014 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 5015
5016 if (has_dpcd) {
5017 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5018 dev_priv->no_aux_handshake =
5019 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5020 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5021 } else {
5022 /* if this fails, presume the device is a ghost */
5023 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5024 return false;
5025 }
5026
5027 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5028 pps_lock(intel_dp);
0095e6dc 5029 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 5030 pps_unlock(intel_dp);
ed92f0b2 5031
060c8778 5032 mutex_lock(&dev->mode_config.mutex);
0b99836f 5033 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5034 if (edid) {
5035 if (drm_add_edid_modes(connector, edid)) {
5036 drm_mode_connector_update_edid_property(connector,
5037 edid);
5038 drm_edid_to_eld(connector, edid);
5039 } else {
5040 kfree(edid);
5041 edid = ERR_PTR(-EINVAL);
5042 }
5043 } else {
5044 edid = ERR_PTR(-ENOENT);
5045 }
5046 intel_connector->edid = edid;
5047
5048 /* prefer fixed mode from EDID if available */
5049 list_for_each_entry(scan, &connector->probed_modes, head) {
5050 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5051 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5052 downclock_mode = intel_dp_drrs_init(
5053 intel_dig_port,
5054 intel_connector, fixed_mode);
ed92f0b2
PZ		 5055 break;
5056 }
5057 }
5058
5059 /* fallback to VBT if available for eDP */
5060 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5061 fixed_mode = drm_mode_duplicate(dev,
5062 dev_priv->vbt.lfp_lvds_vbt_mode);
5063 if (fixed_mode)
5064 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5065 }
060c8778 5066 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5067
01527b31
CT		 5068 if (IS_VALLEYVIEW(dev)) {
5069 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5070 register_reboot_notifier(&intel_dp->edp_notifier);
5071 }
5072
4f9db5b5 5073 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5074 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5075 intel_panel_setup_backlight(connector);
5076
5077 return true;
5078}
5079
16c25533 5080bool
f0fec3f2
PZ		 5081intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5082 struct intel_connector *intel_connector)
a4fc5ed6 5083{
f0fec3f2
PZ		 5084 struct drm_connector *connector = &intel_connector->base;
5085 struct intel_dp *intel_dp = &intel_dig_port->dp;
5086 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5087 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5088 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5089 enum port port = intel_dig_port->port;
0095e6dc 5090 struct edp_power_seq power_seq = { 0 };
0b99836f 5091 int type;
a4fc5ed6 5092
a4a5d2f8
VS		 5093 intel_dp->pps_pipe = INVALID_PIPE;
5094
ec5b01dd 5095 /* intel_dp vfuncs */
b6b5e383
DL		 5096 if (INTEL_INFO(dev)->gen >= 9)
5097 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5098 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5099 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5100 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5101 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5102 else if (HAS_PCH_SPLIT(dev))
5103 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5104 else
5105 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5106
153b1100
DL		 5107 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5108
0767935e
DV		 5109 /* Preserve the current hw state. */
5110 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5111 intel_dp->attached_connector = intel_connector;
3d3dc149 5112
3b32a35b 5113 if (intel_dp_is_edp(dev, port))
b329530c 5114 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5115 else
5116 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5117
f7d24902
ID		 5118 /*
5119 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5120 * for DP the encoder type can be set by the caller to
5121 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5122 */
5123 if (type == DRM_MODE_CONNECTOR_eDP)
5124 intel_encoder->type = INTEL_OUTPUT_EDP;
5125
e7281eab
ID		 5126 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5127 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5128 port_name(port));
5129
b329530c 5130 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5131 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5132
a4fc5ed6
KP		 5133 connector->interlace_allowed = true;
5134 connector->doublescan_allowed = 0;
5135
f0fec3f2 5136 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5137 edp_panel_vdd_work);
a4fc5ed6 5138
df0e9248 5139 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5140 drm_connector_register(connector);
a4fc5ed6 5141
affa9354 5142 if (HAS_DDI(dev))
bcbc889b
PZ		 5143 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5144 else
5145 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5146 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5147
0b99836f 5148 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5149 switch (port) {
5150 case PORT_A:
1d843f9d 5151 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5152 break;
5153 case PORT_B:
1d843f9d 5154 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5155 break;
5156 case PORT_C:
1d843f9d 5157 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5158 break;
5159 case PORT_D:
1d843f9d 5160 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5161 break;
5162 default:
ad1c0b19 5163 BUG();
5eb08b69
ZW		 5164 }
5165
dada1a9f 5166 if (is_edp(intel_dp)) {
773538e8 5167 pps_lock(intel_dp);
a4a5d2f8
VS		 5168 if (IS_VALLEYVIEW(dev)) {
5169 vlv_initial_power_sequencer_setup(intel_dp);
5170 } else {
5171 intel_dp_init_panel_power_timestamps(intel_dp);
5172 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5173 &power_seq);
5174 }
773538e8 5175 pps_unlock(intel_dp);
dada1a9f 5176 }
0095e6dc 5177
9d1a1031 5178 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5179
0e32b39c
DA		 5180 /* init MST on ports that can support it */
5181 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5182 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5183 intel_dp_mst_encoder_init(intel_dig_port,
5184 intel_connector->base.base.id);
0e32b39c
DA		 5185 }
5186 }
5187
0095e6dc 5188 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5189 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5190 if (is_edp(intel_dp)) {
5191 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5192 /*
5193 * vdd might still be enabled do to the delayed vdd off.
5194 * Make sure vdd is actually turned off here.
5195 */
773538e8 5196 pps_lock(intel_dp);
4be73780 5197 edp_panel_vdd_off_sync(intel_dp);
773538e8 5198 pps_unlock(intel_dp);
15b1d171 5199 }
34ea3d38 5200 drm_connector_unregister(connector);
b2f246a8 5201 drm_connector_cleanup(connector);
16c25533 5202 return false;
b2f246a8 5203 }
32f9d658 5204
f684960e
CW		 5205 intel_dp_add_properties(intel_dp, connector);
5206
a4fc5ed6
KP		 5207 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5208 * 0xd. Failure to do so will result in spurious interrupts being
5209 * generated on the port when a cable is not attached.
5210 */
5211 if (IS_G4X(dev) && !IS_GM45(dev)) {
5212 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5213 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5214 }
16c25533
PZ		 5215
5216 return true;
a4fc5ed6 5217}
f0fec3f2
PZ		 5218
5219void
5220intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5221{
13cf5504 5222 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5223 struct intel_digital_port *intel_dig_port;
5224 struct intel_encoder *intel_encoder;
5225 struct drm_encoder *encoder;
5226 struct intel_connector *intel_connector;
5227
b14c5679 5228 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5229 if (!intel_dig_port)
5230 return;
5231
b14c5679 5232 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5233 if (!intel_connector) {
5234 kfree(intel_dig_port);
5235 return;
5236 }
5237
5238 intel_encoder = &intel_dig_port->base;
5239 encoder = &intel_encoder->base;
5240
5241 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5242 DRM_MODE_ENCODER_TMDS);
5243
5bfe2ac0 5244 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5245 intel_encoder->disable = intel_disable_dp;
00c09d70 5246 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5247 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5248 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5249 if (IS_CHERRYVIEW(dev)) {
9197c88b 5250 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5251 intel_encoder->pre_enable = chv_pre_enable_dp;
5252 intel_encoder->enable = vlv_enable_dp;
580d3811 5253 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5254 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5255 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5256 intel_encoder->pre_enable = vlv_pre_enable_dp;
5257 intel_encoder->enable = vlv_enable_dp;
49277c31 5258 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5259 } else {
ecff4f3b
JN		 5260 intel_encoder->pre_enable = g4x_pre_enable_dp;
5261 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5262 if (INTEL_INFO(dev)->gen >= 5)
5263 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5264 }
f0fec3f2 5265
174edf1f 5266 intel_dig_port->port = port;
f0fec3f2
PZ		 5267 intel_dig_port->dp.output_reg = output_reg;
5268
00c09d70 5269 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5270 if (IS_CHERRYVIEW(dev)) {
5271 if (port == PORT_D)
5272 intel_encoder->crtc_mask = 1 << 2;
5273 else
5274 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5275 } else {
5276 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5277 }
bc079e8b 5278 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5279 intel_encoder->hot_plug = intel_dp_hot_plug;
5280
13cf5504
DA		 5281 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5282 dev_priv->hpd_irq_port[port] = intel_dig_port;
5283
15b1d171
PZ		 5284 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5285 drm_encoder_cleanup(encoder);
5286 kfree(intel_dig_port);
b2f246a8 5287 kfree(intel_connector);
15b1d171 5288 }
f0fec3f2 5289}
0e32b39c
DA		 5290
5291void intel_dp_mst_suspend(struct drm_device *dev)
5292{
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 int i;
5295
5296 /* disable MST */
5297 for (i = 0; i < I915_MAX_PORTS; i++) {
5298 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5299 if (!intel_dig_port)
5300 continue;
5301
5302 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5303 if (!intel_dig_port->dp.can_mst)
5304 continue;
5305 if (intel_dig_port->dp.is_mst)
5306 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5307 }
5308 }
5309}
5310
5311void intel_dp_mst_resume(struct drm_device *dev)
5312{
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314 int i;
5315
5316 for (i = 0; i < I915_MAX_PORTS; i++) {
5317 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5318 if (!intel_dig_port)
5319 continue;
5320 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5321 int ret;
5322
5323 if (!intel_dig_port->dp.can_mst)
5324 continue;
5325
5326 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5327 if (ret != 0) {
5328 intel_dp_check_mst_status(&intel_dig_port->dp);
5329 }
5330 }
5331 }
5332}
Linux kernel - Deliverables
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