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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
d2b996ac | 53 | int dpms_mode; |
a4fc5ed6 KP |
54 | uint8_t link_bw; |
55 | uint8_t lane_count; | |
9de88e6e | 56 | uint8_t dpcd[8]; |
a4fc5ed6 KP |
57 | struct i2c_adapter adapter; |
58 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 59 | bool is_pch_edp; |
33a34e4e JB |
60 | uint8_t train_set[4]; |
61 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
a4fc5ed6 KP |
62 | }; |
63 | ||
cfcb0fc9 JB |
64 | /** |
65 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
66 | * @intel_dp: DP struct | |
67 | * | |
68 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
69 | * will return true, and false otherwise. | |
70 | */ | |
71 | static bool is_edp(struct intel_dp *intel_dp) | |
72 | { | |
73 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
74 | } | |
75 | ||
76 | /** | |
77 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
78 | * @intel_dp: DP struct | |
79 | * | |
80 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
81 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
82 | * may need FDI resources for a given DP output or not. | |
83 | */ | |
84 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
85 | { | |
86 | return intel_dp->is_pch_edp; | |
87 | } | |
88 | ||
ea5b213a CW |
89 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
90 | { | |
4ef69c7a | 91 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 92 | } |
a4fc5ed6 | 93 | |
df0e9248 CW |
94 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
95 | { | |
96 | return container_of(intel_attached_encoder(connector), | |
97 | struct intel_dp, base); | |
98 | } | |
99 | ||
814948ad JB |
100 | /** |
101 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
102 | * @encoder: DRM encoder | |
103 | * | |
104 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
105 | * by intel_display.c. | |
106 | */ | |
107 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
108 | { | |
109 | struct intel_dp *intel_dp; | |
110 | ||
111 | if (!encoder) | |
112 | return false; | |
113 | ||
114 | intel_dp = enc_to_intel_dp(encoder); | |
115 | ||
116 | return is_pch_edp(intel_dp); | |
117 | } | |
118 | ||
33a34e4e JB |
119 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
120 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 121 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 122 | |
32f9d658 | 123 | void |
21d40d37 | 124 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 125 | int *lane_num, int *link_bw) |
32f9d658 | 126 | { |
ea5b213a | 127 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 128 | |
ea5b213a CW |
129 | *lane_num = intel_dp->lane_count; |
130 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 131 | *link_bw = 162000; |
ea5b213a | 132 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
133 | *link_bw = 270000; |
134 | } | |
135 | ||
a4fc5ed6 | 136 | static int |
ea5b213a | 137 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 138 | { |
a4fc5ed6 KP |
139 | int max_lane_count = 4; |
140 | ||
7183dc29 JB |
141 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
142 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
143 | switch (max_lane_count) { |
144 | case 1: case 2: case 4: | |
145 | break; | |
146 | default: | |
147 | max_lane_count = 4; | |
148 | } | |
149 | } | |
150 | return max_lane_count; | |
151 | } | |
152 | ||
153 | static int | |
ea5b213a | 154 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 155 | { |
7183dc29 | 156 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
157 | |
158 | switch (max_link_bw) { | |
159 | case DP_LINK_BW_1_62: | |
160 | case DP_LINK_BW_2_7: | |
161 | break; | |
162 | default: | |
163 | max_link_bw = DP_LINK_BW_1_62; | |
164 | break; | |
165 | } | |
166 | return max_link_bw; | |
167 | } | |
168 | ||
169 | static int | |
170 | intel_dp_link_clock(uint8_t link_bw) | |
171 | { | |
172 | if (link_bw == DP_LINK_BW_2_7) | |
173 | return 270000; | |
174 | else | |
175 | return 162000; | |
176 | } | |
177 | ||
178 | /* I think this is a fiction */ | |
179 | static int | |
ea5b213a | 180 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 181 | { |
89c61432 JB |
182 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
184 | int bpp = 24; | |
885a5fb5 | 185 | |
89c61432 JB |
186 | if (intel_crtc) |
187 | bpp = intel_crtc->bpp; | |
188 | ||
189 | return (pixel_clock * bpp + 7) / 8; | |
a4fc5ed6 KP |
190 | } |
191 | ||
fe27d53e DA |
192 | static int |
193 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
194 | { | |
195 | return (max_link_clock * max_lanes * 8) / 10; | |
196 | } | |
197 | ||
a4fc5ed6 KP |
198 | static int |
199 | intel_dp_mode_valid(struct drm_connector *connector, | |
200 | struct drm_display_mode *mode) | |
201 | { | |
df0e9248 | 202 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
7de56f43 ZY |
203 | struct drm_device *dev = connector->dev; |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
205 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
206 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 207 | |
4d926461 | 208 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
7de56f43 ZY |
209 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) |
210 | return MODE_PANEL; | |
211 | ||
212 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
213 | return MODE_PANEL; | |
214 | } | |
215 | ||
25985edc | 216 | /* only refuse the mode on non eDP since we have seen some weird eDP panels |
fe27d53e | 217 | which are outside spec tolerances but somehow work by magic */ |
cfcb0fc9 | 218 | if (!is_edp(intel_dp) && |
ea5b213a | 219 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
fe27d53e | 220 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
221 | return MODE_CLOCK_HIGH; |
222 | ||
223 | if (mode->clock < 10000) | |
224 | return MODE_CLOCK_LOW; | |
225 | ||
226 | return MODE_OK; | |
227 | } | |
228 | ||
229 | static uint32_t | |
230 | pack_aux(uint8_t *src, int src_bytes) | |
231 | { | |
232 | int i; | |
233 | uint32_t v = 0; | |
234 | ||
235 | if (src_bytes > 4) | |
236 | src_bytes = 4; | |
237 | for (i = 0; i < src_bytes; i++) | |
238 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
239 | return v; | |
240 | } | |
241 | ||
242 | static void | |
243 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
244 | { | |
245 | int i; | |
246 | if (dst_bytes > 4) | |
247 | dst_bytes = 4; | |
248 | for (i = 0; i < dst_bytes; i++) | |
249 | dst[i] = src >> ((3-i) * 8); | |
250 | } | |
251 | ||
fb0f8fbf KP |
252 | /* hrawclock is 1/4 the FSB frequency */ |
253 | static int | |
254 | intel_hrawclk(struct drm_device *dev) | |
255 | { | |
256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
257 | uint32_t clkcfg; | |
258 | ||
259 | clkcfg = I915_READ(CLKCFG); | |
260 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
261 | case CLKCFG_FSB_400: | |
262 | return 100; | |
263 | case CLKCFG_FSB_533: | |
264 | return 133; | |
265 | case CLKCFG_FSB_667: | |
266 | return 166; | |
267 | case CLKCFG_FSB_800: | |
268 | return 200; | |
269 | case CLKCFG_FSB_1067: | |
270 | return 266; | |
271 | case CLKCFG_FSB_1333: | |
272 | return 333; | |
273 | /* these two are just a guess; one of them might be right */ | |
274 | case CLKCFG_FSB_1600: | |
275 | case CLKCFG_FSB_1600_ALT: | |
276 | return 400; | |
277 | default: | |
278 | return 133; | |
279 | } | |
280 | } | |
281 | ||
9b984dae KP |
282 | static void |
283 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
284 | { | |
285 | struct drm_device *dev = intel_dp->base.base.dev; | |
286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
287 | u32 pp_status, pp_control; | |
288 | if (!is_edp(intel_dp)) | |
289 | return; | |
290 | pp_status = I915_READ(PCH_PP_STATUS); | |
291 | pp_control = I915_READ(PCH_PP_CONTROL); | |
292 | if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) { | |
293 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); | |
294 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
295 | pp_status, | |
296 | I915_READ(PCH_PP_CONTROL)); | |
297 | } | |
298 | } | |
299 | ||
a4fc5ed6 | 300 | static int |
ea5b213a | 301 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
302 | uint8_t *send, int send_bytes, |
303 | uint8_t *recv, int recv_size) | |
304 | { | |
ea5b213a | 305 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 306 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
307 | struct drm_i915_private *dev_priv = dev->dev_private; |
308 | uint32_t ch_ctl = output_reg + 0x10; | |
309 | uint32_t ch_data = ch_ctl + 4; | |
310 | int i; | |
311 | int recv_bytes; | |
a4fc5ed6 | 312 | uint32_t status; |
fb0f8fbf | 313 | uint32_t aux_clock_divider; |
e3421a18 | 314 | int try, precharge; |
a4fc5ed6 | 315 | |
9b984dae | 316 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 317 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
318 | * and would like to run at 2MHz. So, take the |
319 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
320 | * |
321 | * Note that PCH attached eDP panels should use a 125MHz input | |
322 | * clock divider. | |
a4fc5ed6 | 323 | */ |
cfcb0fc9 | 324 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
e3421a18 ZW |
325 | if (IS_GEN6(dev)) |
326 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
327 | else | |
328 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
329 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 330 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
331 | else |
332 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
333 | ||
e3421a18 ZW |
334 | if (IS_GEN6(dev)) |
335 | precharge = 3; | |
336 | else | |
337 | precharge = 5; | |
338 | ||
11bee43e JB |
339 | /* Try to wait for any previous AUX channel activity */ |
340 | for (try = 0; try < 3; try++) { | |
341 | status = I915_READ(ch_ctl); | |
342 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
343 | break; | |
344 | msleep(1); | |
345 | } | |
346 | ||
347 | if (try == 3) { | |
348 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
349 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
350 | return -EBUSY; |
351 | } | |
352 | ||
fb0f8fbf KP |
353 | /* Must try at least 3 times according to DP spec */ |
354 | for (try = 0; try < 5; try++) { | |
355 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
356 | for (i = 0; i < send_bytes; i += 4) |
357 | I915_WRITE(ch_data + i, | |
358 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
359 | |
360 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
361 | I915_WRITE(ch_ctl, |
362 | DP_AUX_CH_CTL_SEND_BUSY | | |
363 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
364 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
365 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
366 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
367 | DP_AUX_CH_CTL_DONE | | |
368 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
369 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 370 | for (;;) { |
fb0f8fbf KP |
371 | status = I915_READ(ch_ctl); |
372 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
373 | break; | |
4f7f7b7e | 374 | udelay(100); |
fb0f8fbf KP |
375 | } |
376 | ||
377 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
378 | I915_WRITE(ch_ctl, |
379 | status | | |
380 | DP_AUX_CH_CTL_DONE | | |
381 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
382 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
383 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
384 | break; |
385 | } | |
386 | ||
a4fc5ed6 | 387 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 388 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 389 | return -EBUSY; |
a4fc5ed6 KP |
390 | } |
391 | ||
392 | /* Check for timeout or receive error. | |
393 | * Timeouts occur when the sink is not connected | |
394 | */ | |
a5b3da54 | 395 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 396 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
397 | return -EIO; |
398 | } | |
1ae8c0a5 KP |
399 | |
400 | /* Timeouts occur when the device isn't connected, so they're | |
401 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 402 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 403 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 404 | return -ETIMEDOUT; |
a4fc5ed6 KP |
405 | } |
406 | ||
407 | /* Unload any bytes sent back from the other side */ | |
408 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
409 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
410 | if (recv_bytes > recv_size) |
411 | recv_bytes = recv_size; | |
412 | ||
4f7f7b7e CW |
413 | for (i = 0; i < recv_bytes; i += 4) |
414 | unpack_aux(I915_READ(ch_data + i), | |
415 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
416 | |
417 | return recv_bytes; | |
418 | } | |
419 | ||
420 | /* Write data to the aux channel in native mode */ | |
421 | static int | |
ea5b213a | 422 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
423 | uint16_t address, uint8_t *send, int send_bytes) |
424 | { | |
425 | int ret; | |
426 | uint8_t msg[20]; | |
427 | int msg_bytes; | |
428 | uint8_t ack; | |
429 | ||
9b984dae | 430 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
431 | if (send_bytes > 16) |
432 | return -1; | |
433 | msg[0] = AUX_NATIVE_WRITE << 4; | |
434 | msg[1] = address >> 8; | |
eebc863e | 435 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
436 | msg[3] = send_bytes - 1; |
437 | memcpy(&msg[4], send, send_bytes); | |
438 | msg_bytes = send_bytes + 4; | |
439 | for (;;) { | |
ea5b213a | 440 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
441 | if (ret < 0) |
442 | return ret; | |
443 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
444 | break; | |
445 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
446 | udelay(100); | |
447 | else | |
a5b3da54 | 448 | return -EIO; |
a4fc5ed6 KP |
449 | } |
450 | return send_bytes; | |
451 | } | |
452 | ||
453 | /* Write a single byte to the aux channel in native mode */ | |
454 | static int | |
ea5b213a | 455 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
456 | uint16_t address, uint8_t byte) |
457 | { | |
ea5b213a | 458 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
459 | } |
460 | ||
461 | /* read bytes from a native aux channel */ | |
462 | static int | |
ea5b213a | 463 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
464 | uint16_t address, uint8_t *recv, int recv_bytes) |
465 | { | |
466 | uint8_t msg[4]; | |
467 | int msg_bytes; | |
468 | uint8_t reply[20]; | |
469 | int reply_bytes; | |
470 | uint8_t ack; | |
471 | int ret; | |
472 | ||
9b984dae | 473 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
474 | msg[0] = AUX_NATIVE_READ << 4; |
475 | msg[1] = address >> 8; | |
476 | msg[2] = address & 0xff; | |
477 | msg[3] = recv_bytes - 1; | |
478 | ||
479 | msg_bytes = 4; | |
480 | reply_bytes = recv_bytes + 1; | |
481 | ||
482 | for (;;) { | |
ea5b213a | 483 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 484 | reply, reply_bytes); |
a5b3da54 KP |
485 | if (ret == 0) |
486 | return -EPROTO; | |
487 | if (ret < 0) | |
a4fc5ed6 KP |
488 | return ret; |
489 | ack = reply[0]; | |
490 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
491 | memcpy(recv, reply + 1, ret - 1); | |
492 | return ret - 1; | |
493 | } | |
494 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
495 | udelay(100); | |
496 | else | |
a5b3da54 | 497 | return -EIO; |
a4fc5ed6 KP |
498 | } |
499 | } | |
500 | ||
501 | static int | |
ab2c0672 DA |
502 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
503 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 504 | { |
ab2c0672 | 505 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
506 | struct intel_dp *intel_dp = container_of(adapter, |
507 | struct intel_dp, | |
508 | adapter); | |
ab2c0672 DA |
509 | uint16_t address = algo_data->address; |
510 | uint8_t msg[5]; | |
511 | uint8_t reply[2]; | |
8316f337 | 512 | unsigned retry; |
ab2c0672 DA |
513 | int msg_bytes; |
514 | int reply_bytes; | |
515 | int ret; | |
516 | ||
9b984dae | 517 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
518 | /* Set up the command byte */ |
519 | if (mode & MODE_I2C_READ) | |
520 | msg[0] = AUX_I2C_READ << 4; | |
521 | else | |
522 | msg[0] = AUX_I2C_WRITE << 4; | |
523 | ||
524 | if (!(mode & MODE_I2C_STOP)) | |
525 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 526 | |
ab2c0672 DA |
527 | msg[1] = address >> 8; |
528 | msg[2] = address; | |
529 | ||
530 | switch (mode) { | |
531 | case MODE_I2C_WRITE: | |
532 | msg[3] = 0; | |
533 | msg[4] = write_byte; | |
534 | msg_bytes = 5; | |
535 | reply_bytes = 1; | |
536 | break; | |
537 | case MODE_I2C_READ: | |
538 | msg[3] = 0; | |
539 | msg_bytes = 4; | |
540 | reply_bytes = 2; | |
541 | break; | |
542 | default: | |
543 | msg_bytes = 3; | |
544 | reply_bytes = 1; | |
545 | break; | |
546 | } | |
547 | ||
8316f337 DF |
548 | for (retry = 0; retry < 5; retry++) { |
549 | ret = intel_dp_aux_ch(intel_dp, | |
550 | msg, msg_bytes, | |
551 | reply, reply_bytes); | |
ab2c0672 | 552 | if (ret < 0) { |
3ff99164 | 553 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
554 | return ret; |
555 | } | |
8316f337 DF |
556 | |
557 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
558 | case AUX_NATIVE_REPLY_ACK: | |
559 | /* I2C-over-AUX Reply field is only valid | |
560 | * when paired with AUX ACK. | |
561 | */ | |
562 | break; | |
563 | case AUX_NATIVE_REPLY_NACK: | |
564 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
565 | return -EREMOTEIO; | |
566 | case AUX_NATIVE_REPLY_DEFER: | |
567 | udelay(100); | |
568 | continue; | |
569 | default: | |
570 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
571 | reply[0]); | |
572 | return -EREMOTEIO; | |
573 | } | |
574 | ||
ab2c0672 DA |
575 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
576 | case AUX_I2C_REPLY_ACK: | |
577 | if (mode == MODE_I2C_READ) { | |
578 | *read_byte = reply[1]; | |
579 | } | |
580 | return reply_bytes - 1; | |
581 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 582 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
583 | return -EREMOTEIO; |
584 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 585 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
586 | udelay(100); |
587 | break; | |
588 | default: | |
8316f337 | 589 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
590 | return -EREMOTEIO; |
591 | } | |
592 | } | |
8316f337 DF |
593 | |
594 | DRM_ERROR("too many retries, giving up\n"); | |
595 | return -EREMOTEIO; | |
a4fc5ed6 KP |
596 | } |
597 | ||
598 | static int | |
ea5b213a | 599 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 600 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 601 | { |
d54e9d28 | 602 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
603 | intel_dp->algo.running = false; |
604 | intel_dp->algo.address = 0; | |
605 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
606 | ||
607 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
608 | intel_dp->adapter.owner = THIS_MODULE; | |
609 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
610 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
611 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
612 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
613 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
614 | ||
615 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
616 | } |
617 | ||
618 | static bool | |
619 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
620 | struct drm_display_mode *adjusted_mode) | |
621 | { | |
0d3a1bee ZY |
622 | struct drm_device *dev = encoder->dev; |
623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 624 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 625 | int lane_count, clock; |
ea5b213a CW |
626 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
627 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
628 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
629 | ||
4d926461 | 630 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
631 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
632 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
633 | mode, adjusted_mode); | |
0d3a1bee ZY |
634 | /* |
635 | * the mode->clock is used to calculate the Data&Link M/N | |
636 | * of the pipe. For the eDP the fixed clock should be used. | |
637 | */ | |
638 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
639 | } | |
640 | ||
a4fc5ed6 KP |
641 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
642 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 643 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 644 | |
ea5b213a | 645 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 646 | <= link_avail) { |
ea5b213a CW |
647 | intel_dp->link_bw = bws[clock]; |
648 | intel_dp->lane_count = lane_count; | |
649 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
650 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
651 | "count %d clock %d\n", | |
ea5b213a | 652 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
653 | adjusted_mode->clock); |
654 | return true; | |
655 | } | |
656 | } | |
657 | } | |
fe27d53e | 658 | |
3cf2efb1 CW |
659 | if (is_edp(intel_dp)) { |
660 | /* okay we failed just pick the highest */ | |
661 | intel_dp->lane_count = max_lane_count; | |
662 | intel_dp->link_bw = bws[max_clock]; | |
663 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
664 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " | |
665 | "count %d clock %d\n", | |
666 | intel_dp->link_bw, intel_dp->lane_count, | |
667 | adjusted_mode->clock); | |
668 | ||
669 | return true; | |
670 | } | |
671 | ||
a4fc5ed6 KP |
672 | return false; |
673 | } | |
674 | ||
675 | struct intel_dp_m_n { | |
676 | uint32_t tu; | |
677 | uint32_t gmch_m; | |
678 | uint32_t gmch_n; | |
679 | uint32_t link_m; | |
680 | uint32_t link_n; | |
681 | }; | |
682 | ||
683 | static void | |
684 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
685 | { | |
686 | while (*num > 0xffffff || *den > 0xffffff) { | |
687 | *num >>= 1; | |
688 | *den >>= 1; | |
689 | } | |
690 | } | |
691 | ||
692 | static void | |
36e83a18 | 693 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
694 | int nlanes, |
695 | int pixel_clock, | |
696 | int link_clock, | |
697 | struct intel_dp_m_n *m_n) | |
698 | { | |
699 | m_n->tu = 64; | |
36e83a18 | 700 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
701 | m_n->gmch_n = link_clock * nlanes; |
702 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
703 | m_n->link_m = pixel_clock; | |
704 | m_n->link_n = link_clock; | |
705 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
706 | } | |
707 | ||
708 | void | |
709 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
710 | struct drm_display_mode *adjusted_mode) | |
711 | { | |
712 | struct drm_device *dev = crtc->dev; | |
713 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 714 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
715 | struct drm_i915_private *dev_priv = dev->dev_private; |
716 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 717 | int lane_count = 4; |
a4fc5ed6 | 718 | struct intel_dp_m_n m_n; |
9db4a9c7 | 719 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
720 | |
721 | /* | |
21d40d37 | 722 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 723 | */ |
55f78c43 | 724 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 725 | struct intel_dp *intel_dp; |
a4fc5ed6 | 726 | |
d8201ab6 | 727 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
728 | continue; |
729 | ||
ea5b213a CW |
730 | intel_dp = enc_to_intel_dp(encoder); |
731 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
732 | lane_count = intel_dp->lane_count; | |
51190667 JB |
733 | break; |
734 | } else if (is_edp(intel_dp)) { | |
735 | lane_count = dev_priv->edp.lanes; | |
a4fc5ed6 KP |
736 | break; |
737 | } | |
738 | } | |
739 | ||
740 | /* | |
741 | * Compute the GMCH and Link ratios. The '3' here is | |
742 | * the number of bytes_per_pixel post-LUT, which we always | |
743 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
744 | */ | |
858fa035 | 745 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
746 | mode->clock, adjusted_mode->clock, &m_n); |
747 | ||
c619eed4 | 748 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
749 | I915_WRITE(TRANSDATA_M1(pipe), |
750 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
751 | m_n.gmch_m); | |
752 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
753 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
754 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 755 | } else { |
9db4a9c7 JB |
756 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
757 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
758 | m_n.gmch_m); | |
759 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
760 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
761 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
762 | } |
763 | } | |
764 | ||
765 | static void | |
766 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
767 | struct drm_display_mode *adjusted_mode) | |
768 | { | |
e3421a18 | 769 | struct drm_device *dev = encoder->dev; |
ea5b213a | 770 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 771 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
773 | ||
e953fd7b CW |
774 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
775 | intel_dp->DP |= intel_dp->color_range; | |
9c9e7927 AJ |
776 | |
777 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 778 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 779 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 780 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 781 | |
cfcb0fc9 | 782 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
ea5b213a | 783 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 784 | else |
ea5b213a | 785 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 786 | |
ea5b213a | 787 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 788 | case 1: |
ea5b213a | 789 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
790 | break; |
791 | case 2: | |
ea5b213a | 792 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
793 | break; |
794 | case 4: | |
ea5b213a | 795 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
796 | break; |
797 | } | |
ea5b213a CW |
798 | if (intel_dp->has_audio) |
799 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 800 | |
ea5b213a CW |
801 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
802 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
803 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 804 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 KP |
805 | |
806 | /* | |
9962c925 | 807 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 808 | */ |
7183dc29 JB |
809 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
810 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a CW |
811 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
812 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
813 | } |
814 | ||
e3421a18 ZW |
815 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
816 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 817 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 818 | |
895692be | 819 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
32f9d658 | 820 | /* don't miss out required setting for eDP */ |
ea5b213a | 821 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 822 | if (adjusted_mode->clock < 200000) |
ea5b213a | 823 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 824 | else |
ea5b213a | 825 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 826 | } |
a4fc5ed6 KP |
827 | } |
828 | ||
5d613501 JB |
829 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
830 | { | |
831 | struct drm_device *dev = intel_dp->base.base.dev; | |
832 | struct drm_i915_private *dev_priv = dev->dev_private; | |
833 | u32 pp; | |
834 | ||
97af61f5 KP |
835 | if (!is_edp(intel_dp)) |
836 | return; | |
5d613501 JB |
837 | /* |
838 | * If the panel wasn't on, make sure there's not a currently | |
839 | * active PP sequence before enabling AUX VDD. | |
840 | */ | |
841 | if (!(I915_READ(PCH_PP_STATUS) & PP_ON)) | |
842 | msleep(dev_priv->panel_t3); | |
843 | ||
844 | pp = I915_READ(PCH_PP_CONTROL); | |
1c0ae80a KP |
845 | pp &= ~PANEL_UNLOCK_MASK; |
846 | pp |= PANEL_UNLOCK_REGS; | |
5d613501 JB |
847 | pp |= EDP_FORCE_VDD; |
848 | I915_WRITE(PCH_PP_CONTROL, pp); | |
849 | POSTING_READ(PCH_PP_CONTROL); | |
850 | } | |
851 | ||
852 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) | |
853 | { | |
854 | struct drm_device *dev = intel_dp->base.base.dev; | |
855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
856 | u32 pp; | |
857 | ||
97af61f5 KP |
858 | if (!is_edp(intel_dp)) |
859 | return; | |
5d613501 | 860 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
861 | pp &= ~PANEL_UNLOCK_MASK; |
862 | pp |= PANEL_UNLOCK_REGS; | |
5d613501 JB |
863 | pp &= ~EDP_FORCE_VDD; |
864 | I915_WRITE(PCH_PP_CONTROL, pp); | |
865 | POSTING_READ(PCH_PP_CONTROL); | |
866 | ||
867 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
868 | msleep(dev_priv->panel_t12); | |
869 | } | |
870 | ||
7eaf5547 | 871 | /* Returns true if the panel was already on when called */ |
01cb9ea6 | 872 | static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) |
9934c132 | 873 | { |
01cb9ea6 | 874 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 875 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 876 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 877 | |
97af61f5 KP |
878 | if (!is_edp(intel_dp)) |
879 | return; | |
913d8d11 | 880 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
7eaf5547 | 881 | return true; |
9934c132 JB |
882 | |
883 | pp = I915_READ(PCH_PP_CONTROL); | |
1c0ae80a KP |
884 | pp &= ~PANEL_UNLOCK_MASK; |
885 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 JB |
886 | |
887 | /* ILK workaround: disable reset around power sequence */ | |
888 | pp &= ~PANEL_POWER_RESET; | |
889 | I915_WRITE(PCH_PP_CONTROL, pp); | |
890 | POSTING_READ(PCH_PP_CONTROL); | |
891 | ||
1c0ae80a | 892 | pp |= POWER_TARGET_ON; |
9934c132 | 893 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 894 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 895 | |
01cb9ea6 JB |
896 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
897 | 5000)) | |
913d8d11 CW |
898 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
899 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 900 | |
37c6c9b0 | 901 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 902 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 903 | POSTING_READ(PCH_PP_CONTROL); |
7eaf5547 JB |
904 | |
905 | return false; | |
9934c132 JB |
906 | } |
907 | ||
908 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
909 | { | |
910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01cb9ea6 JB |
911 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
912 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 | 913 | |
97af61f5 KP |
914 | if (!is_edp(intel_dp)) |
915 | return; | |
9934c132 | 916 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
917 | pp &= ~PANEL_UNLOCK_MASK; |
918 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 JB |
919 | |
920 | /* ILK workaround: disable reset around power sequence */ | |
921 | pp &= ~PANEL_POWER_RESET; | |
922 | I915_WRITE(PCH_PP_CONTROL, pp); | |
923 | POSTING_READ(PCH_PP_CONTROL); | |
924 | ||
9934c132 JB |
925 | pp &= ~POWER_TARGET_ON; |
926 | I915_WRITE(PCH_PP_CONTROL, pp); | |
01cb9ea6 | 927 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 928 | |
01cb9ea6 | 929 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
913d8d11 CW |
930 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
931 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 932 | |
3969c9c9 | 933 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 934 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 935 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
936 | } |
937 | ||
f2b115e6 | 938 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
939 | { |
940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
941 | u32 pp; | |
942 | ||
28c97730 | 943 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
944 | /* |
945 | * If we enable the backlight right away following a panel power | |
946 | * on, we may see slight flicker as the panel syncs with the eDP | |
947 | * link. So delay a bit to make sure the image is solid before | |
948 | * allowing it to appear. | |
949 | */ | |
950 | msleep(300); | |
32f9d658 | 951 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
952 | pp &= ~PANEL_UNLOCK_MASK; |
953 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
954 | pp |= EDP_BLC_ENABLE; |
955 | I915_WRITE(PCH_PP_CONTROL, pp); | |
956 | } | |
957 | ||
f2b115e6 | 958 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
959 | { |
960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
961 | u32 pp; | |
962 | ||
28c97730 | 963 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 964 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
965 | pp &= ~PANEL_UNLOCK_MASK; |
966 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
967 | pp &= ~EDP_BLC_ENABLE; |
968 | I915_WRITE(PCH_PP_CONTROL, pp); | |
969 | } | |
a4fc5ed6 | 970 | |
d240f20f JB |
971 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
972 | { | |
973 | struct drm_device *dev = encoder->dev; | |
974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
975 | u32 dpa_ctl; | |
976 | ||
977 | DRM_DEBUG_KMS("\n"); | |
978 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 979 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 980 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
981 | POSTING_READ(DP_A); |
982 | udelay(200); | |
d240f20f JB |
983 | } |
984 | ||
985 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
986 | { | |
987 | struct drm_device *dev = encoder->dev; | |
988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
989 | u32 dpa_ctl; | |
990 | ||
991 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 992 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 993 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 994 | POSTING_READ(DP_A); |
d240f20f JB |
995 | udelay(200); |
996 | } | |
997 | ||
c7ad3810 JB |
998 | /* If the sink supports it, try to set the power state appropriately */ |
999 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1000 | { | |
1001 | int ret, i; | |
1002 | ||
1003 | /* Should have a valid DPCD by this point */ | |
1004 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1005 | return; | |
1006 | ||
1007 | if (mode != DRM_MODE_DPMS_ON) { | |
1008 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1009 | DP_SET_POWER_D3); | |
1010 | if (ret != 1) | |
1011 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1012 | } else { | |
1013 | /* | |
1014 | * When turning on, we need to retry for 1ms to give the sink | |
1015 | * time to wake up. | |
1016 | */ | |
1017 | for (i = 0; i < 3; i++) { | |
1018 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1019 | DP_SET_POWER, | |
1020 | DP_SET_POWER_D0); | |
1021 | if (ret == 1) | |
1022 | break; | |
1023 | msleep(1); | |
1024 | } | |
1025 | } | |
1026 | } | |
1027 | ||
d240f20f JB |
1028 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1029 | { | |
1030 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1031 | struct drm_device *dev = encoder->dev; | |
d240f20f | 1032 | |
c7ad3810 JB |
1033 | /* Wake up the sink first */ |
1034 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1035 | ||
4d926461 | 1036 | if (is_edp(intel_dp)) { |
d240f20f | 1037 | ironlake_edp_backlight_off(dev); |
5d613501 | 1038 | ironlake_edp_panel_off(dev); |
01cb9ea6 JB |
1039 | if (!is_pch_edp(intel_dp)) |
1040 | ironlake_edp_pll_on(encoder); | |
1041 | else | |
1042 | ironlake_edp_pll_off(encoder); | |
d240f20f | 1043 | } |
736085bc | 1044 | intel_dp_link_down(intel_dp); |
d240f20f JB |
1045 | } |
1046 | ||
1047 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1048 | { | |
1049 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1050 | struct drm_device *dev = encoder->dev; | |
d240f20f | 1051 | |
97af61f5 | 1052 | ironlake_edp_panel_vdd_on(intel_dp); |
5d613501 | 1053 | |
33a34e4e JB |
1054 | intel_dp_start_link_train(intel_dp); |
1055 | ||
97af61f5 KP |
1056 | ironlake_edp_panel_on(intel_dp); |
1057 | ironlake_edp_panel_vdd_off(intel_dp); | |
33a34e4e JB |
1058 | |
1059 | intel_dp_complete_link_train(intel_dp); | |
1060 | ||
4d926461 | 1061 | if (is_edp(intel_dp)) |
d240f20f | 1062 | ironlake_edp_backlight_on(dev); |
d2b996ac KP |
1063 | |
1064 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d240f20f JB |
1065 | } |
1066 | ||
a4fc5ed6 KP |
1067 | static void |
1068 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1069 | { | |
ea5b213a | 1070 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1071 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1072 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1073 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1074 | |
1075 | if (mode != DRM_MODE_DPMS_ON) { | |
01cb9ea6 | 1076 | if (is_edp(intel_dp)) |
7643a7fa | 1077 | ironlake_edp_backlight_off(dev); |
c7ad3810 | 1078 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1079 | intel_dp_link_down(intel_dp); |
97af61f5 | 1080 | ironlake_edp_panel_off(dev); |
01cb9ea6 | 1081 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
d240f20f | 1082 | ironlake_edp_pll_off(encoder); |
a4fc5ed6 | 1083 | } else { |
97af61f5 | 1084 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1085 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1086 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1087 | intel_dp_start_link_train(intel_dp); |
97af61f5 KP |
1088 | ironlake_edp_panel_on(intel_dp); |
1089 | ironlake_edp_panel_vdd_off(intel_dp); | |
33a34e4e | 1090 | intel_dp_complete_link_train(intel_dp); |
bee7eb2d KP |
1091 | } else |
1092 | ironlake_edp_panel_vdd_off(intel_dp); | |
736085bc JB |
1093 | if (is_edp(intel_dp)) |
1094 | ironlake_edp_backlight_on(dev); | |
a4fc5ed6 | 1095 | } |
d2b996ac | 1096 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1097 | } |
1098 | ||
1099 | /* | |
df0c237d JB |
1100 | * Native read with retry for link status and receiver capability reads for |
1101 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1102 | */ |
1103 | static bool | |
df0c237d JB |
1104 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1105 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1106 | { |
61da5fab JB |
1107 | int ret, i; |
1108 | ||
df0c237d JB |
1109 | /* |
1110 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1111 | * but we're also supposed to retry 3 times per the spec. | |
1112 | */ | |
61da5fab | 1113 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1114 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1115 | recv_bytes); | |
1116 | if (ret == recv_bytes) | |
61da5fab JB |
1117 | return true; |
1118 | msleep(1); | |
1119 | } | |
a4fc5ed6 | 1120 | |
61da5fab | 1121 | return false; |
a4fc5ed6 KP |
1122 | } |
1123 | ||
1124 | /* | |
1125 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1126 | * link status information | |
1127 | */ | |
1128 | static bool | |
33a34e4e | 1129 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1130 | { |
df0c237d JB |
1131 | return intel_dp_aux_native_read_retry(intel_dp, |
1132 | DP_LANE0_1_STATUS, | |
1133 | intel_dp->link_status, | |
1134 | DP_LINK_STATUS_SIZE); | |
a4fc5ed6 KP |
1135 | } |
1136 | ||
1137 | static uint8_t | |
1138 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1139 | int r) | |
1140 | { | |
1141 | return link_status[r - DP_LANE0_1_STATUS]; | |
1142 | } | |
1143 | ||
a4fc5ed6 KP |
1144 | static uint8_t |
1145 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1146 | int lane) | |
1147 | { | |
1148 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1149 | int s = ((lane & 1) ? | |
1150 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1151 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1152 | uint8_t l = intel_dp_link_status(link_status, i); | |
1153 | ||
1154 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1155 | } | |
1156 | ||
1157 | static uint8_t | |
1158 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1159 | int lane) | |
1160 | { | |
1161 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1162 | int s = ((lane & 1) ? | |
1163 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1164 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1165 | uint8_t l = intel_dp_link_status(link_status, i); | |
1166 | ||
1167 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1168 | } | |
1169 | ||
1170 | ||
1171 | #if 0 | |
1172 | static char *voltage_names[] = { | |
1173 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1174 | }; | |
1175 | static char *pre_emph_names[] = { | |
1176 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1177 | }; | |
1178 | static char *link_train_names[] = { | |
1179 | "pattern 1", "pattern 2", "idle", "off" | |
1180 | }; | |
1181 | #endif | |
1182 | ||
1183 | /* | |
1184 | * These are source-specific values; current Intel hardware supports | |
1185 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1186 | */ | |
1187 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1188 | ||
1189 | static uint8_t | |
1190 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1191 | { | |
1192 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1193 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1194 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1195 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1196 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1197 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1198 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1199 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1200 | default: | |
1201 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1202 | } | |
1203 | } | |
1204 | ||
1205 | static void | |
33a34e4e | 1206 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1207 | { |
1208 | uint8_t v = 0; | |
1209 | uint8_t p = 0; | |
1210 | int lane; | |
1211 | ||
33a34e4e JB |
1212 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1213 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1214 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1215 | |
1216 | if (this_v > v) | |
1217 | v = this_v; | |
1218 | if (this_p > p) | |
1219 | p = this_p; | |
1220 | } | |
1221 | ||
1222 | if (v >= I830_DP_VOLTAGE_MAX) | |
1223 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1224 | ||
1225 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1226 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1227 | ||
1228 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1229 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1230 | } |
1231 | ||
1232 | static uint32_t | |
3cf2efb1 | 1233 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
a4fc5ed6 | 1234 | { |
3cf2efb1 | 1235 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1236 | |
3cf2efb1 | 1237 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1238 | case DP_TRAIN_VOLTAGE_SWING_400: |
1239 | default: | |
1240 | signal_levels |= DP_VOLTAGE_0_4; | |
1241 | break; | |
1242 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1243 | signal_levels |= DP_VOLTAGE_0_6; | |
1244 | break; | |
1245 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1246 | signal_levels |= DP_VOLTAGE_0_8; | |
1247 | break; | |
1248 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1249 | signal_levels |= DP_VOLTAGE_1_2; | |
1250 | break; | |
1251 | } | |
3cf2efb1 | 1252 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1253 | case DP_TRAIN_PRE_EMPHASIS_0: |
1254 | default: | |
1255 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1256 | break; | |
1257 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1258 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1259 | break; | |
1260 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1261 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1262 | break; | |
1263 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1264 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1265 | break; | |
1266 | } | |
1267 | return signal_levels; | |
1268 | } | |
1269 | ||
e3421a18 ZW |
1270 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1271 | static uint32_t | |
1272 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1273 | { | |
3c5a62b5 YL |
1274 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1275 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1276 | switch (signal_levels) { | |
e3421a18 | 1277 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1278 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1279 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1280 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1281 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1282 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1283 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1284 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1285 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1286 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1287 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1288 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1289 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1290 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1291 | default: |
3c5a62b5 YL |
1292 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1293 | "0x%x\n", signal_levels); | |
1294 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1295 | } |
1296 | } | |
1297 | ||
a4fc5ed6 KP |
1298 | static uint8_t |
1299 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1300 | int lane) | |
1301 | { | |
1302 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1303 | int s = (lane & 1) * 4; | |
1304 | uint8_t l = intel_dp_link_status(link_status, i); | |
1305 | ||
1306 | return (l >> s) & 0xf; | |
1307 | } | |
1308 | ||
1309 | /* Check for clock recovery is done on all channels */ | |
1310 | static bool | |
1311 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1312 | { | |
1313 | int lane; | |
1314 | uint8_t lane_status; | |
1315 | ||
1316 | for (lane = 0; lane < lane_count; lane++) { | |
1317 | lane_status = intel_get_lane_status(link_status, lane); | |
1318 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1319 | return false; | |
1320 | } | |
1321 | return true; | |
1322 | } | |
1323 | ||
1324 | /* Check to see if channel eq is done on all channels */ | |
1325 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1326 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1327 | DP_LANE_SYMBOL_LOCKED) | |
1328 | static bool | |
33a34e4e | 1329 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1330 | { |
1331 | uint8_t lane_align; | |
1332 | uint8_t lane_status; | |
1333 | int lane; | |
1334 | ||
33a34e4e | 1335 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1336 | DP_LANE_ALIGN_STATUS_UPDATED); |
1337 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1338 | return false; | |
33a34e4e JB |
1339 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1340 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1341 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1342 | return false; | |
1343 | } | |
1344 | return true; | |
1345 | } | |
1346 | ||
1347 | static bool | |
ea5b213a | 1348 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1349 | uint32_t dp_reg_value, |
58e10eb9 | 1350 | uint8_t dp_train_pat) |
a4fc5ed6 | 1351 | { |
4ef69c7a | 1352 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1353 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1354 | int ret; |
1355 | ||
ea5b213a CW |
1356 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1357 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1358 | |
ea5b213a | 1359 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1360 | DP_TRAINING_PATTERN_SET, |
1361 | dp_train_pat); | |
1362 | ||
ea5b213a | 1363 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1364 | DP_TRAINING_LANE0_SET, |
1365 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1366 | if (ret != 4) |
1367 | return false; | |
1368 | ||
1369 | return true; | |
1370 | } | |
1371 | ||
33a34e4e | 1372 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1373 | static void |
33a34e4e | 1374 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1375 | { |
4ef69c7a | 1376 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1377 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1378 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1379 | int i; |
1380 | uint8_t voltage; | |
1381 | bool clock_recovery = false; | |
a4fc5ed6 | 1382 | int tries; |
e3421a18 | 1383 | u32 reg; |
ea5b213a | 1384 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1385 | |
e8519464 AJ |
1386 | /* |
1387 | * On CPT we have to enable the port in training pattern 1, which | |
1388 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1389 | * the port and wait for it to become active. | |
1390 | */ | |
1391 | if (!HAS_PCH_CPT(dev)) { | |
1392 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1393 | POSTING_READ(intel_dp->output_reg); | |
1394 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1395 | } | |
a4fc5ed6 | 1396 | |
3cf2efb1 CW |
1397 | /* Write the link configuration data */ |
1398 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1399 | intel_dp->link_configuration, | |
1400 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1401 | |
1402 | DP |= DP_PORT_EN; | |
cfcb0fc9 | 1403 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1404 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1405 | else | |
1406 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1407 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1408 | voltage = 0xff; |
1409 | tries = 0; | |
1410 | clock_recovery = false; | |
1411 | for (;;) { | |
33a34e4e | 1412 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1413 | uint32_t signal_levels; |
cfcb0fc9 | 1414 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1415 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1416 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1417 | } else { | |
3cf2efb1 | 1418 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1419 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1420 | } | |
a4fc5ed6 | 1421 | |
cfcb0fc9 | 1422 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1423 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1424 | else | |
1425 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1426 | ||
ea5b213a | 1427 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1428 | DP_TRAINING_PATTERN_1 | |
1429 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1430 | break; |
a4fc5ed6 KP |
1431 | /* Set training pattern 1 */ |
1432 | ||
3cf2efb1 CW |
1433 | udelay(100); |
1434 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1435 | break; |
a4fc5ed6 | 1436 | |
3cf2efb1 CW |
1437 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1438 | clock_recovery = true; | |
1439 | break; | |
1440 | } | |
1441 | ||
1442 | /* Check to see if we've tried the max voltage */ | |
1443 | for (i = 0; i < intel_dp->lane_count; i++) | |
1444 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1445 | break; |
3cf2efb1 CW |
1446 | if (i == intel_dp->lane_count) |
1447 | break; | |
a4fc5ed6 | 1448 | |
3cf2efb1 CW |
1449 | /* Check to see if we've tried the same voltage 5 times */ |
1450 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1451 | ++tries; | |
1452 | if (tries == 5) | |
a4fc5ed6 | 1453 | break; |
3cf2efb1 CW |
1454 | } else |
1455 | tries = 0; | |
1456 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1457 | |
3cf2efb1 CW |
1458 | /* Compute new intel_dp->train_set as requested by target */ |
1459 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1460 | } |
1461 | ||
33a34e4e JB |
1462 | intel_dp->DP = DP; |
1463 | } | |
1464 | ||
1465 | static void | |
1466 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1467 | { | |
4ef69c7a | 1468 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1469 | struct drm_i915_private *dev_priv = dev->dev_private; |
1470 | bool channel_eq = false; | |
37f80975 | 1471 | int tries, cr_tries; |
33a34e4e JB |
1472 | u32 reg; |
1473 | uint32_t DP = intel_dp->DP; | |
1474 | ||
a4fc5ed6 KP |
1475 | /* channel equalization */ |
1476 | tries = 0; | |
37f80975 | 1477 | cr_tries = 0; |
a4fc5ed6 KP |
1478 | channel_eq = false; |
1479 | for (;;) { | |
33a34e4e | 1480 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1481 | uint32_t signal_levels; |
1482 | ||
37f80975 JB |
1483 | if (cr_tries > 5) { |
1484 | DRM_ERROR("failed to train DP, aborting\n"); | |
1485 | intel_dp_link_down(intel_dp); | |
1486 | break; | |
1487 | } | |
1488 | ||
cfcb0fc9 | 1489 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1490 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1491 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1492 | } else { | |
3cf2efb1 | 1493 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1494 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1495 | } | |
1496 | ||
cfcb0fc9 | 1497 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1498 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1499 | else | |
1500 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1501 | |
1502 | /* channel eq pattern */ | |
ea5b213a | 1503 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1504 | DP_TRAINING_PATTERN_2 | |
1505 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1506 | break; |
1507 | ||
3cf2efb1 CW |
1508 | udelay(400); |
1509 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1510 | break; |
a4fc5ed6 | 1511 | |
37f80975 JB |
1512 | /* Make sure clock is still ok */ |
1513 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { | |
1514 | intel_dp_start_link_train(intel_dp); | |
1515 | cr_tries++; | |
1516 | continue; | |
1517 | } | |
1518 | ||
3cf2efb1 CW |
1519 | if (intel_channel_eq_ok(intel_dp)) { |
1520 | channel_eq = true; | |
1521 | break; | |
1522 | } | |
a4fc5ed6 | 1523 | |
37f80975 JB |
1524 | /* Try 5 times, then try clock recovery if that fails */ |
1525 | if (tries > 5) { | |
1526 | intel_dp_link_down(intel_dp); | |
1527 | intel_dp_start_link_train(intel_dp); | |
1528 | tries = 0; | |
1529 | cr_tries++; | |
1530 | continue; | |
1531 | } | |
a4fc5ed6 | 1532 | |
3cf2efb1 CW |
1533 | /* Compute new intel_dp->train_set as requested by target */ |
1534 | intel_get_adjust_train(intel_dp); | |
1535 | ++tries; | |
869184a6 | 1536 | } |
3cf2efb1 | 1537 | |
cfcb0fc9 | 1538 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1539 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1540 | else | |
1541 | reg = DP | DP_LINK_TRAIN_OFF; | |
1542 | ||
ea5b213a CW |
1543 | I915_WRITE(intel_dp->output_reg, reg); |
1544 | POSTING_READ(intel_dp->output_reg); | |
1545 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1546 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1547 | } | |
1548 | ||
1549 | static void | |
ea5b213a | 1550 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1551 | { |
4ef69c7a | 1552 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1553 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1554 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1555 | |
1b39d6f3 CW |
1556 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1557 | return; | |
1558 | ||
28c97730 | 1559 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1560 | |
cfcb0fc9 | 1561 | if (is_edp(intel_dp)) { |
32f9d658 | 1562 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1563 | I915_WRITE(intel_dp->output_reg, DP); |
1564 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1565 | udelay(100); |
1566 | } | |
1567 | ||
cfcb0fc9 | 1568 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
e3421a18 | 1569 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1570 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1571 | } else { |
1572 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1573 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1574 | } |
fe255d00 | 1575 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1576 | |
fe255d00 | 1577 | msleep(17); |
5eb08b69 | 1578 | |
cfcb0fc9 | 1579 | if (is_edp(intel_dp)) |
32f9d658 | 1580 | DP |= DP_LINK_TRAIN_OFF; |
5bddd17f | 1581 | |
1b39d6f3 CW |
1582 | if (!HAS_PCH_CPT(dev) && |
1583 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1584 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1585 | ||
5bddd17f EA |
1586 | /* Hardware workaround: leaving our transcoder select |
1587 | * set to transcoder B while it's off will prevent the | |
1588 | * corresponding HDMI output on transcoder A. | |
1589 | * | |
1590 | * Combine this with another hardware workaround: | |
1591 | * transcoder select bit can only be cleared while the | |
1592 | * port is enabled. | |
1593 | */ | |
1594 | DP &= ~DP_PIPEB_SELECT; | |
1595 | I915_WRITE(intel_dp->output_reg, DP); | |
1596 | ||
1597 | /* Changes to enable or select take place the vblank | |
1598 | * after being written. | |
1599 | */ | |
31acbcc4 CW |
1600 | if (crtc == NULL) { |
1601 | /* We can arrive here never having been attached | |
1602 | * to a CRTC, for instance, due to inheriting | |
1603 | * random state from the BIOS. | |
1604 | * | |
1605 | * If the pipe is not running, play safe and | |
1606 | * wait for the clocks to stabilise before | |
1607 | * continuing. | |
1608 | */ | |
1609 | POSTING_READ(intel_dp->output_reg); | |
1610 | msleep(50); | |
1611 | } else | |
1612 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1613 | } |
1614 | ||
ea5b213a CW |
1615 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1616 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1617 | } |
1618 | ||
26d61aad KP |
1619 | static bool |
1620 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1621 | { |
92fd8fd1 KP |
1622 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
1623 | sizeof (intel_dp->dpcd)) && | |
1624 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { | |
26d61aad | 1625 | return true; |
92fd8fd1 KP |
1626 | } |
1627 | ||
26d61aad | 1628 | return false; |
92fd8fd1 KP |
1629 | } |
1630 | ||
a4fc5ed6 KP |
1631 | /* |
1632 | * According to DP spec | |
1633 | * 5.1.2: | |
1634 | * 1. Read DPCD | |
1635 | * 2. Configure link according to Receiver Capabilities | |
1636 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1637 | * 4. Check link status on receipt of hot-plug interrupt | |
1638 | */ | |
1639 | ||
1640 | static void | |
ea5b213a | 1641 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1642 | { |
d2b996ac KP |
1643 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1644 | return; | |
59cd09e1 | 1645 | |
4ef69c7a | 1646 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1647 | return; |
1648 | ||
92fd8fd1 | 1649 | /* Try to read receiver status if the link appears to be up */ |
33a34e4e | 1650 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1651 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1652 | return; |
1653 | } | |
1654 | ||
92fd8fd1 | 1655 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1656 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1657 | intel_dp_link_down(intel_dp); |
1658 | return; | |
1659 | } | |
1660 | ||
33a34e4e | 1661 | if (!intel_channel_eq_ok(intel_dp)) { |
92fd8fd1 KP |
1662 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1663 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1664 | intel_dp_start_link_train(intel_dp); |
1665 | intel_dp_complete_link_train(intel_dp); | |
1666 | } | |
a4fc5ed6 | 1667 | } |
a4fc5ed6 | 1668 | |
71ba9000 | 1669 | static enum drm_connector_status |
26d61aad | 1670 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1671 | { |
26d61aad KP |
1672 | if (intel_dp_get_dpcd(intel_dp)) |
1673 | return connector_status_connected; | |
1674 | return connector_status_disconnected; | |
71ba9000 AJ |
1675 | } |
1676 | ||
5eb08b69 | 1677 | static enum drm_connector_status |
a9756bb5 | 1678 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1679 | { |
5eb08b69 ZW |
1680 | enum drm_connector_status status; |
1681 | ||
fe16d949 CW |
1682 | /* Can't disconnect eDP, but you can close the lid... */ |
1683 | if (is_edp(intel_dp)) { | |
1684 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1685 | if (status == connector_status_unknown) | |
1686 | status = connector_status_connected; | |
1687 | return status; | |
1688 | } | |
01cb9ea6 | 1689 | |
26d61aad | 1690 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1691 | } |
1692 | ||
a4fc5ed6 | 1693 | static enum drm_connector_status |
a9756bb5 | 1694 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1695 | { |
4ef69c7a | 1696 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1697 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1698 | uint32_t temp, bit; |
5eb08b69 | 1699 | |
ea5b213a | 1700 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1701 | case DP_B: |
1702 | bit = DPB_HOTPLUG_INT_STATUS; | |
1703 | break; | |
1704 | case DP_C: | |
1705 | bit = DPC_HOTPLUG_INT_STATUS; | |
1706 | break; | |
1707 | case DP_D: | |
1708 | bit = DPD_HOTPLUG_INT_STATUS; | |
1709 | break; | |
1710 | default: | |
1711 | return connector_status_unknown; | |
1712 | } | |
1713 | ||
1714 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1715 | ||
1716 | if ((temp & bit) == 0) | |
1717 | return connector_status_disconnected; | |
1718 | ||
26d61aad | 1719 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1720 | } |
1721 | ||
1722 | /** | |
1723 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1724 | * | |
1725 | * \return true if DP port is connected. | |
1726 | * \return false if DP port is disconnected. | |
1727 | */ | |
1728 | static enum drm_connector_status | |
1729 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1730 | { | |
1731 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1732 | struct drm_device *dev = intel_dp->base.base.dev; | |
1733 | enum drm_connector_status status; | |
1734 | struct edid *edid = NULL; | |
1735 | ||
1736 | intel_dp->has_audio = false; | |
1737 | ||
1738 | if (HAS_PCH_SPLIT(dev)) | |
1739 | status = ironlake_dp_detect(intel_dp); | |
1740 | else | |
1741 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 1742 | |
ac66ae83 AJ |
1743 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
1744 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
1745 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
1746 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 1747 | |
a9756bb5 ZW |
1748 | if (status != connector_status_connected) |
1749 | return status; | |
1750 | ||
f684960e CW |
1751 | if (intel_dp->force_audio) { |
1752 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
1753 | } else { | |
1754 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
1755 | if (edid) { | |
1756 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
1757 | connector->display_info.raw_edid = NULL; | |
1758 | kfree(edid); | |
1759 | } | |
a9756bb5 ZW |
1760 | } |
1761 | ||
1762 | return connector_status_connected; | |
a4fc5ed6 KP |
1763 | } |
1764 | ||
1765 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1766 | { | |
df0e9248 | 1767 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1768 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1769 | struct drm_i915_private *dev_priv = dev->dev_private; |
1770 | int ret; | |
a4fc5ed6 KP |
1771 | |
1772 | /* We should parse the EDID data and find out if it has an audio sink | |
1773 | */ | |
1774 | ||
f899fc64 | 1775 | ret = intel_ddc_get_modes(connector, &intel_dp->adapter); |
b9efc480 | 1776 | if (ret) { |
4d926461 | 1777 | if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { |
b9efc480 ZY |
1778 | struct drm_display_mode *newmode; |
1779 | list_for_each_entry(newmode, &connector->probed_modes, | |
1780 | head) { | |
1781 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1782 | dev_priv->panel_fixed_mode = | |
1783 | drm_mode_duplicate(dev, newmode); | |
1784 | break; | |
1785 | } | |
1786 | } | |
1787 | } | |
1788 | ||
32f9d658 | 1789 | return ret; |
b9efc480 | 1790 | } |
32f9d658 ZW |
1791 | |
1792 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 1793 | if (is_edp(intel_dp)) { |
47f0eb22 KP |
1794 | /* initialize panel mode from VBT if available for eDP */ |
1795 | if (dev_priv->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { | |
1796 | dev_priv->panel_fixed_mode = | |
1797 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
1798 | if (dev_priv->panel_fixed_mode) { | |
1799 | dev_priv->panel_fixed_mode->type |= | |
1800 | DRM_MODE_TYPE_PREFERRED; | |
1801 | } | |
1802 | } | |
1803 | if (dev_priv->panel_fixed_mode) { | |
32f9d658 ZW |
1804 | struct drm_display_mode *mode; |
1805 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1806 | drm_mode_probed_add(connector, mode); | |
1807 | return 1; | |
1808 | } | |
1809 | } | |
1810 | return 0; | |
a4fc5ed6 KP |
1811 | } |
1812 | ||
1aad7ac0 CW |
1813 | static bool |
1814 | intel_dp_detect_audio(struct drm_connector *connector) | |
1815 | { | |
1816 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1817 | struct edid *edid; | |
1818 | bool has_audio = false; | |
1819 | ||
1820 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
1821 | if (edid) { | |
1822 | has_audio = drm_detect_monitor_audio(edid); | |
1823 | ||
1824 | connector->display_info.raw_edid = NULL; | |
1825 | kfree(edid); | |
1826 | } | |
1827 | ||
1828 | return has_audio; | |
1829 | } | |
1830 | ||
f684960e CW |
1831 | static int |
1832 | intel_dp_set_property(struct drm_connector *connector, | |
1833 | struct drm_property *property, | |
1834 | uint64_t val) | |
1835 | { | |
e953fd7b | 1836 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
1837 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
1838 | int ret; | |
1839 | ||
1840 | ret = drm_connector_property_set_value(connector, property, val); | |
1841 | if (ret) | |
1842 | return ret; | |
1843 | ||
3f43c48d | 1844 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1845 | int i = val; |
1846 | bool has_audio; | |
1847 | ||
1848 | if (i == intel_dp->force_audio) | |
f684960e CW |
1849 | return 0; |
1850 | ||
1aad7ac0 | 1851 | intel_dp->force_audio = i; |
f684960e | 1852 | |
1aad7ac0 CW |
1853 | if (i == 0) |
1854 | has_audio = intel_dp_detect_audio(connector); | |
1855 | else | |
1856 | has_audio = i > 0; | |
1857 | ||
1858 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
1859 | return 0; |
1860 | ||
1aad7ac0 | 1861 | intel_dp->has_audio = has_audio; |
f684960e CW |
1862 | goto done; |
1863 | } | |
1864 | ||
e953fd7b CW |
1865 | if (property == dev_priv->broadcast_rgb_property) { |
1866 | if (val == !!intel_dp->color_range) | |
1867 | return 0; | |
1868 | ||
1869 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
1870 | goto done; | |
1871 | } | |
1872 | ||
f684960e CW |
1873 | return -EINVAL; |
1874 | ||
1875 | done: | |
1876 | if (intel_dp->base.base.crtc) { | |
1877 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
1878 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
1879 | crtc->x, crtc->y, | |
1880 | crtc->fb); | |
1881 | } | |
1882 | ||
1883 | return 0; | |
1884 | } | |
1885 | ||
a4fc5ed6 KP |
1886 | static void |
1887 | intel_dp_destroy (struct drm_connector *connector) | |
1888 | { | |
aaa6fd2a MG |
1889 | struct drm_device *dev = connector->dev; |
1890 | ||
1891 | if (intel_dpd_is_edp(dev)) | |
1892 | intel_panel_destroy_backlight(dev); | |
1893 | ||
a4fc5ed6 KP |
1894 | drm_sysfs_connector_remove(connector); |
1895 | drm_connector_cleanup(connector); | |
55f78c43 | 1896 | kfree(connector); |
a4fc5ed6 KP |
1897 | } |
1898 | ||
24d05927 DV |
1899 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
1900 | { | |
1901 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1902 | ||
1903 | i2c_del_adapter(&intel_dp->adapter); | |
1904 | drm_encoder_cleanup(encoder); | |
1905 | kfree(intel_dp); | |
1906 | } | |
1907 | ||
a4fc5ed6 KP |
1908 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
1909 | .dpms = intel_dp_dpms, | |
1910 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1911 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1912 | .mode_set = intel_dp_mode_set, |
d240f20f | 1913 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1914 | }; |
1915 | ||
1916 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1917 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1918 | .detect = intel_dp_detect, |
1919 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 1920 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
1921 | .destroy = intel_dp_destroy, |
1922 | }; | |
1923 | ||
1924 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1925 | .get_modes = intel_dp_get_modes, | |
1926 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 1927 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
1928 | }; |
1929 | ||
a4fc5ed6 | 1930 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 1931 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
1932 | }; |
1933 | ||
995b6762 | 1934 | static void |
21d40d37 | 1935 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1936 | { |
ea5b213a | 1937 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1938 | |
885a5014 | 1939 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 1940 | } |
6207937d | 1941 | |
e3421a18 ZW |
1942 | /* Return which DP Port should be selected for Transcoder DP control */ |
1943 | int | |
1944 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1945 | { | |
1946 | struct drm_device *dev = crtc->dev; | |
1947 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1948 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1949 | |
1950 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1951 | struct intel_dp *intel_dp; |
1952 | ||
d8201ab6 | 1953 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1954 | continue; |
1955 | ||
ea5b213a CW |
1956 | intel_dp = enc_to_intel_dp(encoder); |
1957 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1958 | return intel_dp->output_reg; | |
e3421a18 | 1959 | } |
ea5b213a | 1960 | |
e3421a18 ZW |
1961 | return -1; |
1962 | } | |
1963 | ||
36e83a18 | 1964 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1965 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1966 | { |
1967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1968 | struct child_device_config *p_child; | |
1969 | int i; | |
1970 | ||
1971 | if (!dev_priv->child_dev_num) | |
1972 | return false; | |
1973 | ||
1974 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1975 | p_child = dev_priv->child_dev + i; | |
1976 | ||
1977 | if (p_child->dvo_port == PORT_IDPD && | |
1978 | p_child->device_type == DEVICE_TYPE_eDP) | |
1979 | return true; | |
1980 | } | |
1981 | return false; | |
1982 | } | |
1983 | ||
f684960e CW |
1984 | static void |
1985 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
1986 | { | |
3f43c48d | 1987 | intel_attach_force_audio_property(connector); |
e953fd7b | 1988 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
1989 | } |
1990 | ||
a4fc5ed6 KP |
1991 | void |
1992 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1993 | { | |
1994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1995 | struct drm_connector *connector; | |
ea5b213a | 1996 | struct intel_dp *intel_dp; |
21d40d37 | 1997 | struct intel_encoder *intel_encoder; |
55f78c43 | 1998 | struct intel_connector *intel_connector; |
5eb08b69 | 1999 | const char *name = NULL; |
b329530c | 2000 | int type; |
a4fc5ed6 | 2001 | |
ea5b213a CW |
2002 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2003 | if (!intel_dp) | |
a4fc5ed6 KP |
2004 | return; |
2005 | ||
3d3dc149 | 2006 | intel_dp->output_reg = output_reg; |
d2b996ac | 2007 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2008 | |
55f78c43 ZW |
2009 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2010 | if (!intel_connector) { | |
ea5b213a | 2011 | kfree(intel_dp); |
55f78c43 ZW |
2012 | return; |
2013 | } | |
ea5b213a | 2014 | intel_encoder = &intel_dp->base; |
55f78c43 | 2015 | |
ea5b213a | 2016 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2017 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2018 | intel_dp->is_pch_edp = true; |
b329530c | 2019 | |
cfcb0fc9 | 2020 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2021 | type = DRM_MODE_CONNECTOR_eDP; |
2022 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2023 | } else { | |
2024 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2025 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2026 | } | |
2027 | ||
55f78c43 | 2028 | connector = &intel_connector->base; |
b329530c | 2029 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2030 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2031 | ||
eb1f8e4f DA |
2032 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2033 | ||
652af9d7 | 2034 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2035 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2036 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2037 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2038 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2039 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2040 | |
cfcb0fc9 | 2041 | if (is_edp(intel_dp)) |
21d40d37 | 2042 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 2043 | |
21d40d37 | 2044 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
2045 | connector->interlace_allowed = true; |
2046 | connector->doublescan_allowed = 0; | |
2047 | ||
4ef69c7a | 2048 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2049 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2050 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2051 | |
df0e9248 | 2052 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2053 | drm_sysfs_connector_add(connector); |
2054 | ||
2055 | /* Set up the DDC bus. */ | |
5eb08b69 | 2056 | switch (output_reg) { |
32f9d658 ZW |
2057 | case DP_A: |
2058 | name = "DPDDC-A"; | |
2059 | break; | |
5eb08b69 ZW |
2060 | case DP_B: |
2061 | case PCH_DP_B: | |
b01f2c3a JB |
2062 | dev_priv->hotplug_supported_mask |= |
2063 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2064 | name = "DPDDC-B"; |
2065 | break; | |
2066 | case DP_C: | |
2067 | case PCH_DP_C: | |
b01f2c3a JB |
2068 | dev_priv->hotplug_supported_mask |= |
2069 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2070 | name = "DPDDC-C"; |
2071 | break; | |
2072 | case DP_D: | |
2073 | case PCH_DP_D: | |
b01f2c3a JB |
2074 | dev_priv->hotplug_supported_mask |= |
2075 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2076 | name = "DPDDC-D"; |
2077 | break; | |
2078 | } | |
2079 | ||
ea5b213a | 2080 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 2081 | |
89667383 JB |
2082 | /* Cache some DPCD data in the eDP case */ |
2083 | if (is_edp(intel_dp)) { | |
59f3e272 | 2084 | bool ret; |
5d613501 JB |
2085 | u32 pp_on, pp_div; |
2086 | ||
2087 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
2088 | pp_div = I915_READ(PCH_PP_DIVISOR); | |
89667383 | 2089 | |
5d613501 JB |
2090 | /* Get T3 & T12 values (note: VESA not bspec terminology) */ |
2091 | dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16; | |
2092 | dev_priv->panel_t3 /= 10; /* t3 in 100us units */ | |
2093 | dev_priv->panel_t12 = pp_div & 0xf; | |
2094 | dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ | |
2095 | ||
2096 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2097 | ret = intel_dp_get_dpcd(intel_dp); |
3d3dc149 | 2098 | ironlake_edp_panel_vdd_off(intel_dp); |
59f3e272 | 2099 | if (ret) { |
7183dc29 JB |
2100 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2101 | dev_priv->no_aux_handshake = | |
2102 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2103 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2104 | } else { | |
3d3dc149 | 2105 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2106 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2107 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2108 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2109 | return; |
89667383 | 2110 | } |
89667383 JB |
2111 | } |
2112 | ||
21d40d37 | 2113 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2114 | |
4d926461 | 2115 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2116 | dev_priv->int_edp_connector = connector; |
2117 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2118 | } |
2119 | ||
f684960e CW |
2120 | intel_dp_add_properties(intel_dp, connector); |
2121 | ||
a4fc5ed6 KP |
2122 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2123 | * 0xd. Failure to do so will result in spurious interrupts being | |
2124 | * generated on the port when a cable is not attached. | |
2125 | */ | |
2126 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2127 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2128 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2129 | } | |
2130 | } |