drm/i915: Remove mention of Haswell in DDI code
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB
41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB
53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ
68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ
81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW
86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW
89}
90
814948ad
JB
91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
a4fc5ed6 112static int
ea5b213a 113intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 114{
7183dc29 115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP
116
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
119 case DP_LINK_BW_2_7:
120 break;
121 default:
122 max_link_bw = DP_LINK_BW_1_62;
123 break;
124 }
125 return max_link_bw;
126}
127
cd9dde44
AJ
128/*
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
131 *
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
133 *
134 * 270000 * 1 * 8 / 10 == 216000
135 *
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
140 *
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
143 */
144
a4fc5ed6 145static int
c898261c 146intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 147{
cd9dde44 148 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP
149}
150
fe27d53e
DA
151static int
152intel_dp_max_data_rate(int max_link_clock, int max_lanes)
153{
154 return (max_link_clock * max_lanes * 8) / 10;
155}
156
a4fc5ed6
KP
157static int
158intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
160{
df0e9248 161 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN
162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV
164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 166
dd06f90e
JN
167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY
169 return MODE_PANEL;
170
dd06f90e 171 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 172 return MODE_PANEL;
03afc4a2
DV
173
174 target_clock = fixed_mode->clock;
7de56f43
ZY
175 }
176
36008365
DV
177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
c4867936 184 return MODE_CLOCK_HIGH;
a4fc5ed6
KP
185
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
188
0af78a2b
DV
189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
191
a4fc5ed6
KP
192 return MODE_OK;
193}
194
195static uint32_t
196pack_aux(uint8_t *src, int src_bytes)
197{
198 int i;
199 uint32_t v = 0;
200
201 if (src_bytes > 4)
202 src_bytes = 4;
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 return v;
206}
207
208static void
209unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210{
211 int i;
212 if (dst_bytes > 4)
213 dst_bytes = 4;
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
216}
217
fb0f8fbf
KP
218/* hrawclock is 1/4 the FSB frequency */
219static int
220intel_hrawclk(struct drm_device *dev)
221{
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 uint32_t clkcfg;
224
9473c8f4
VP
225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
227 return 200;
228
fb0f8fbf
KP
229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
231 case CLKCFG_FSB_400:
232 return 100;
233 case CLKCFG_FSB_533:
234 return 133;
235 case CLKCFG_FSB_667:
236 return 166;
237 case CLKCFG_FSB_800:
238 return 200;
239 case CLKCFG_FSB_1067:
240 return 266;
241 case CLKCFG_FSB_1333:
242 return 333;
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
246 return 400;
247 default:
248 return 133;
249 }
250}
251
ebf33b18
KP
252static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
253{
30add22d 254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 255 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 256 u32 pp_stat_reg;
ebf33b18 257
453c5420
JB
258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP
260}
261
262static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
263{
30add22d 264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 265 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 266 u32 pp_ctrl_reg;
ebf33b18 267
453c5420
JB
268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP
270}
271
9b984dae
KP
272static void
273intel_dp_check_edp(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 276 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 277 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 278
9b984dae
KP
279 if (!is_edp(intel_dp))
280 return;
453c5420
JB
281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
ebf33b18 285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP
286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB
288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
9b984dae
KP
290 }
291}
292
9ee32fea
DV
293static uint32_t
294intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV
300 uint32_t status;
301 bool done;
302
ef04f00d 303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 304 if (has_aux_irq)
b90f5176
PZ
305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
9ee32fea
DV
307 else
308 done = wait_for_atomic(C, 10) == 0;
309 if (!done)
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
311 has_aux_irq);
312#undef C
313
314 return status;
315}
316
a4fc5ed6 317static int
ea5b213a 318intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP
319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
321{
174edf1f
PZ
322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 324 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 326 uint32_t ch_data = ch_ctl + 4;
9ee32fea 327 int i, ret, recv_bytes;
a4fc5ed6 328 uint32_t status;
fb0f8fbf 329 uint32_t aux_clock_divider;
6b4e0a93 330 int try, precharge;
9ee32fea
DV
331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
332
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
335 * deep sleep states.
336 */
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 338
9b984dae 339 intel_dp_check_edp(intel_dp);
a4fc5ed6 340 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP
341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
6176b8f9
JB
343 *
344 * Note that PCH attached eDP panels should use a 125MHz input
345 * clock divider.
a4fc5ed6 346 */
1c95822a 347 if (is_cpu_edp(intel_dp)) {
affa9354 348 if (HAS_DDI(dev))
b8fc2f6a
PZ
349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP
351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW
354 else
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN
356 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider = 74;
359 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 360 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 361 } else {
5eb08b69 362 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 363 }
5eb08b69 364
6b4e0a93
DV
365 if (IS_GEN6(dev))
366 precharge = 3;
367 else
368 precharge = 5;
369
11bee43e
JB
370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
ef04f00d 372 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB
373 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
374 break;
375 msleep(1);
376 }
377
378 if (try == 3) {
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
380 I915_READ(ch_ctl));
9ee32fea
DV
381 ret = -EBUSY;
382 goto out;
4f7f7b7e
CW
383 }
384
fb0f8fbf
KP
385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW
388 for (i = 0; i < send_bytes; i += 4)
389 I915_WRITE(ch_data + i,
390 pack_aux(send + i, send_bytes - i));
0206e353 391
fb0f8fbf 392 /* Send the command and wait for it to complete */
4f7f7b7e
CW
393 I915_WRITE(ch_ctl,
394 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 395 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW
396 DP_AUX_CH_CTL_TIME_OUT_400us |
397 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
398 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
399 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
400 DP_AUX_CH_CTL_DONE |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR |
402 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV
403
404 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 405
fb0f8fbf 406 /* Clear done status and any errors */
4f7f7b7e
CW
407 I915_WRITE(ch_ctl,
408 status |
409 DP_AUX_CH_CTL_DONE |
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ
412
413 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR))
415 continue;
4f7f7b7e 416 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP
417 break;
418 }
419
a4fc5ed6 420 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV
422 ret = -EBUSY;
423 goto out;
a4fc5ed6
KP
424 }
425
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
428 */
a5b3da54 429 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV
431 ret = -EIO;
432 goto out;
a5b3da54 433 }
1ae8c0a5
KP
434
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
a5b3da54 437 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV
439 ret = -ETIMEDOUT;
440 goto out;
a4fc5ed6
KP
441 }
442
443 /* Unload any bytes sent back from the other side */
444 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP
446 if (recv_bytes > recv_size)
447 recv_bytes = recv_size;
0206e353 448
4f7f7b7e
CW
449 for (i = 0; i < recv_bytes; i += 4)
450 unpack_aux(I915_READ(ch_data + i),
451 recv + i, recv_bytes - i);
a4fc5ed6 452
9ee32fea
DV
453 ret = recv_bytes;
454out:
455 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
456
457 return ret;
a4fc5ed6
KP
458}
459
460/* Write data to the aux channel in native mode */
461static int
ea5b213a 462intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP
463 uint16_t address, uint8_t *send, int send_bytes)
464{
465 int ret;
466 uint8_t msg[20];
467 int msg_bytes;
468 uint8_t ack;
469
9b984dae 470 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP
471 if (send_bytes > 16)
472 return -1;
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
eebc863e 475 msg[2] = address & 0xff;
a4fc5ed6
KP
476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
479 for (;;) {
ea5b213a 480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP
481 if (ret < 0)
482 return ret;
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
484 break;
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
486 udelay(100);
487 else
a5b3da54 488 return -EIO;
a4fc5ed6
KP
489 }
490 return send_bytes;
491}
492
493/* Write a single byte to the aux channel in native mode */
494static int
ea5b213a 495intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP
496 uint16_t address, uint8_t byte)
497{
ea5b213a 498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP
499}
500
501/* read bytes from a native aux channel */
502static int
ea5b213a 503intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP
504 uint16_t address, uint8_t *recv, int recv_bytes)
505{
506 uint8_t msg[4];
507 int msg_bytes;
508 uint8_t reply[20];
509 int reply_bytes;
510 uint8_t ack;
511 int ret;
512
9b984dae 513 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP
514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
518
519 msg_bytes = 4;
520 reply_bytes = recv_bytes + 1;
521
522 for (;;) {
ea5b213a 523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 524 reply, reply_bytes);
a5b3da54
KP
525 if (ret == 0)
526 return -EPROTO;
527 if (ret < 0)
a4fc5ed6
KP
528 return ret;
529 ack = reply[0];
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
532 return ret - 1;
533 }
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
535 udelay(100);
536 else
a5b3da54 537 return -EIO;
a4fc5ed6
KP
538 }
539}
540
541static int
ab2c0672
DA
542intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 544{
ab2c0672 545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW
546 struct intel_dp *intel_dp = container_of(adapter,
547 struct intel_dp,
548 adapter);
ab2c0672
DA
549 uint16_t address = algo_data->address;
550 uint8_t msg[5];
551 uint8_t reply[2];
8316f337 552 unsigned retry;
ab2c0672
DA
553 int msg_bytes;
554 int reply_bytes;
555 int ret;
556
9b984dae 557 intel_dp_check_edp(intel_dp);
ab2c0672
DA
558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
561 else
562 msg[0] = AUX_I2C_WRITE << 4;
563
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 566
ab2c0672
DA
567 msg[1] = address >> 8;
568 msg[2] = address;
569
570 switch (mode) {
571 case MODE_I2C_WRITE:
572 msg[3] = 0;
573 msg[4] = write_byte;
574 msg_bytes = 5;
575 reply_bytes = 1;
576 break;
577 case MODE_I2C_READ:
578 msg[3] = 0;
579 msg_bytes = 4;
580 reply_bytes = 2;
581 break;
582 default:
583 msg_bytes = 3;
584 reply_bytes = 1;
585 break;
586 }
587
8316f337
DF
588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
590 msg, msg_bytes,
591 reply, reply_bytes);
ab2c0672 592 if (ret < 0) {
3ff99164 593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA
594 return ret;
595 }
8316f337
DF
596
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
601 */
602 break;
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
605 return -EREMOTEIO;
606 case AUX_NATIVE_REPLY_DEFER:
607 udelay(100);
608 continue;
609 default:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
611 reply[0]);
612 return -EREMOTEIO;
613 }
614
ab2c0672
DA
615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
619 }
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
8316f337 622 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA
623 return -EREMOTEIO;
624 case AUX_I2C_REPLY_DEFER:
8316f337 625 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA
626 udelay(100);
627 break;
628 default:
8316f337 629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA
630 return -EREMOTEIO;
631 }
632 }
8316f337
DF
633
634 DRM_ERROR("too many retries, giving up\n");
635 return -EREMOTEIO;
a4fc5ed6
KP
636}
637
638static int
ea5b213a 639intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 640 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 641{
0b5c541b
KP
642 int ret;
643
d54e9d28 644 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW
645 intel_dp->algo.running = false;
646 intel_dp->algo.address = 0;
647 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
648
0206e353 649 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW
650 intel_dp->adapter.owner = THIS_MODULE;
651 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 652 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW
653 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
654 intel_dp->adapter.algo_data = &intel_dp->algo;
655 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
656
0b5c541b
KP
657 ironlake_edp_panel_vdd_on(intel_dp);
658 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 659 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 660 return ret;
a4fc5ed6
KP
661}
662
00c09d70 663bool
5bfe2ac0
DV
664intel_dp_compute_config(struct intel_encoder *encoder,
665 struct intel_crtc_config *pipe_config)
a4fc5ed6 666{
5bfe2ac0 667 struct drm_device *dev = encoder->base.dev;
36008365 668 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV
669 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
670 struct drm_display_mode *mode = &pipe_config->requested_mode;
671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
dd06f90e 672 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 673 int lane_count, clock;
397fe157 674 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 675 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 676 int bpp, mode_rate;
a4fc5ed6 677 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 678 int target_clock, link_avail, link_clock;
a4fc5ed6 679
5bfe2ac0
DV
680 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
681 pipe_config->has_pch_encoder = true;
682
03afc4a2
DV
683 pipe_config->has_dp_encoder = true;
684
dd06f90e
JN
685 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
686 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
687 adjusted_mode);
53b41837
YN
688 intel_pch_panel_fitting(dev,
689 intel_connector->panel.fitting_mode,
1d8e1c75 690 mode, adjusted_mode);
0d3a1bee 691 }
36008365
DV
692 /* We need to take the panel's fixed mode into account. */
693 target_clock = adjusted_mode->clock;
0d3a1bee 694
cb1793ce 695 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV
696 return false;
697
083f9560
DV
698 DRM_DEBUG_KMS("DP link computation with max lane count %i "
699 "max bw %02x pixel clock %iKHz\n",
71244653 700 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 701
36008365
DV
702 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
703 * bpc in between. */
03afc4a2 704 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
36008365
DV
705 for (; bpp >= 6*3; bpp -= 2*3) {
706 mode_rate = intel_dp_link_required(target_clock, bpp);
707
708 for (clock = 0; clock <= max_clock; clock++) {
709 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
710 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
711 link_avail = intel_dp_max_data_rate(link_clock,
712 lane_count);
713
714 if (mode_rate <= link_avail) {
715 goto found;
716 }
717 }
718 }
719 }
c4867936 720
36008365 721 return false;
3685a8f3 722
36008365 723found:
55bc60db
VS
724 if (intel_dp->color_range_auto) {
725 /*
726 * See:
727 * CEA-861-E - 5.1 Default Encoding Parameters
728 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
729 */
18316c8c 730 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS
731 intel_dp->color_range = DP_COLOR_RANGE_16_235;
732 else
733 intel_dp->color_range = 0;
734 }
735
3685a8f3 736 if (intel_dp->color_range)
50f3b016 737 pipe_config->limited_color_range = true;
3685a8f3 738
36008365
DV
739 intel_dp->link_bw = bws[clock];
740 intel_dp->lane_count = lane_count;
741 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
df92b1e6 742 pipe_config->pixel_target_clock = target_clock;
fe27d53e 743
36008365
DV
744 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
745 intel_dp->link_bw, intel_dp->lane_count,
746 adjusted_mode->clock, bpp);
747 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
748 mode_rate, link_avail);
749
03afc4a2
DV
750 intel_link_compute_m_n(bpp, lane_count,
751 target_clock, adjusted_mode->clock,
752 &pipe_config->dp_m_n);
a4fc5ed6 753
57c21963
DV
754 /*
755 * XXX: We have a strange regression where using the vbt edp bpp value
756 * for the link bw computation results in black screens, the panel only
757 * works when we do the computation at the usual 24bpp (but still
758 * requires us to use 18bpp). Until that's fully debugged, stay
759 * bug-for-bug compatible with the old code.
760 */
761 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
762 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
763 bpp, dev_priv->edp.bpp);
764 bpp = min_t(int, bpp, dev_priv->edp.bpp);
765 }
766 pipe_config->pipe_bpp = bpp;
767
03afc4a2 768 return true;
a4fc5ed6
KP
769}
770
247d89f6
PZ
771void intel_dp_init_link_config(struct intel_dp *intel_dp)
772{
773 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
774 intel_dp->link_configuration[0] = intel_dp->link_bw;
775 intel_dp->link_configuration[1] = intel_dp->lane_count;
776 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
777 /*
778 * Check for DPCD version > 1.1 and enhanced framing support
779 */
780 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
781 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
782 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
783 }
784}
785
ea9b6006
DV
786static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
787{
788 struct drm_device *dev = crtc->dev;
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 dpa_ctl;
791
792 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
793 dpa_ctl = I915_READ(DP_A);
794 dpa_ctl &= ~DP_PLL_FREQ_MASK;
795
796 if (clock < 200000) {
1ce17038
DV
797 /* For a long time we've carried around a ILK-DevA w/a for the
798 * 160MHz clock. If we're really unlucky, it's still required.
799 */
800 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 801 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV
802 } else {
803 dpa_ctl |= DP_PLL_FREQ_270MHZ;
804 }
1ce17038 805
ea9b6006
DV
806 I915_WRITE(DP_A, dpa_ctl);
807
808 POSTING_READ(DP_A);
809 udelay(500);
810}
811
a4fc5ed6
KP
812static void
813intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
814 struct drm_display_mode *adjusted_mode)
815{
e3421a18 816 struct drm_device *dev = encoder->dev;
417e822d 817 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 818 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 819 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP
820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
821
417e822d 822 /*
1a2eb460 823 * There are four kinds of DP registers:
417e822d
KP
824 *
825 * IBX PCH
1a2eb460
KP
826 * SNB CPU
827 * IVB CPU
417e822d
KP
828 * CPT PCH
829 *
830 * IBX PCH and CPU are the same for almost everything,
831 * except that the CPU DP PLL is configured in this
832 * register
833 *
834 * CPT PCH is quite different, having many bits moved
835 * to the TRANS_DP_CTL register instead. That
836 * configuration happens (oddly) in ironlake_pch_enable
837 */
9c9e7927 838
417e822d
KP
839 /* Preserve the BIOS-computed detected bit. This is
840 * supposed to be read-only.
841 */
842 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 843
417e822d 844 /* Handle DP bits in common between all three register formats */
417e822d 845 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 846
ea5b213a 847 switch (intel_dp->lane_count) {
a4fc5ed6 848 case 1:
ea5b213a 849 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP
850 break;
851 case 2:
ea5b213a 852 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP
853 break;
854 case 4:
ea5b213a 855 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP
856 break;
857 }
e0dac65e
WF
858 if (intel_dp->has_audio) {
859 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
860 pipe_name(intel_crtc->pipe));
ea5b213a 861 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF
862 intel_write_eld(encoder, adjusted_mode);
863 }
247d89f6
PZ
864
865 intel_dp_init_link_config(intel_dp);
a4fc5ed6 866
417e822d 867 /* Split out the IBX/CPU vs CPT settings */
32f9d658 868
19c03924 869 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP
870 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
871 intel_dp->DP |= DP_SYNC_HS_HIGH;
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
873 intel_dp->DP |= DP_SYNC_VS_HIGH;
874 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
875
876 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
877 intel_dp->DP |= DP_ENHANCED_FRAMING;
878
879 intel_dp->DP |= intel_crtc->pipe << 29;
880
881 /* don't miss out required setting for eDP */
1a2eb460
KP
882 if (adjusted_mode->clock < 200000)
883 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
884 else
885 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
886 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 887 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 888 intel_dp->DP |= intel_dp->color_range;
417e822d
KP
889
890 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
891 intel_dp->DP |= DP_SYNC_HS_HIGH;
892 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
893 intel_dp->DP |= DP_SYNC_VS_HIGH;
894 intel_dp->DP |= DP_LINK_TRAIN_OFF;
895
896 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
897 intel_dp->DP |= DP_ENHANCED_FRAMING;
898
899 if (intel_crtc->pipe == 1)
900 intel_dp->DP |= DP_PIPEB_SELECT;
901
b2634017 902 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 903 /* don't miss out required setting for eDP */
417e822d
KP
904 if (adjusted_mode->clock < 200000)
905 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
906 else
907 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
908 }
909 } else {
910 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 911 }
ea9b6006 912
5d66d5b6 913 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 914 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP
915}
916
99ea7127
KP
917#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
918#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
919
920#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
921#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
922
923#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
924#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
925
926static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
927 u32 mask,
928 u32 value)
bd943159 929{
30add22d 930 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 931 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB
932 u32 pp_stat_reg, pp_ctrl_reg;
933
934 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
935 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 936
99ea7127 937 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB
938 mask, value,
939 I915_READ(pp_stat_reg),
940 I915_READ(pp_ctrl_reg));
32ce697c 941
453c5420 942 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 943 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB
944 I915_READ(pp_stat_reg),
945 I915_READ(pp_ctrl_reg));
32ce697c 946 }
99ea7127 947}
32ce697c 948
99ea7127
KP
949static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
950{
951 DRM_DEBUG_KMS("Wait for panel power on\n");
952 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP
953}
954
99ea7127
KP
955static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
956{
957 DRM_DEBUG_KMS("Wait for panel power off time\n");
958 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
959}
960
961static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
962{
963 DRM_DEBUG_KMS("Wait for panel power cycle\n");
964 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
965}
966
967
832dd3c1
KP
968/* Read the current pp_control value, unlocking the register if it
969 * is locked
970 */
971
453c5420 972static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 973{
453c5420
JB
974 struct drm_device *dev = intel_dp_to_dev(intel_dp);
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u32 control;
977 u32 pp_ctrl_reg;
978
979 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
980 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP
981
982 control &= ~PANEL_UNLOCK_MASK;
983 control |= PANEL_UNLOCK_REGS;
984 return control;
bd943159
KP
985}
986
82a4d9c0 987void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 988{
30add22d 989 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u32 pp;
453c5420 992 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 993
97af61f5
KP
994 if (!is_edp(intel_dp))
995 return;
f01eca2e 996 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 997
bd943159
KP
998 WARN(intel_dp->want_panel_vdd,
999 "eDP VDD already requested on\n");
1000
1001 intel_dp->want_panel_vdd = true;
99ea7127 1002
bd943159
KP
1003 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1004 DRM_DEBUG_KMS("eDP VDD already on\n");
1005 return;
1006 }
1007
99ea7127
KP
1008 if (!ironlake_edp_have_panel_power(intel_dp))
1009 ironlake_wait_panel_power_cycle(intel_dp);
1010
453c5420 1011 pp = ironlake_get_pp_control(intel_dp);
5d613501 1012 pp |= EDP_FORCE_VDD;
ebf33b18 1013
453c5420
JB
1014 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1015 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1016
1017 I915_WRITE(pp_ctrl_reg, pp);
1018 POSTING_READ(pp_ctrl_reg);
1019 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1020 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP
1021 /*
1022 * If the panel wasn't on, delay before accessing aux channel
1023 */
1024 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1025 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1026 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1027 }
5d613501
JB
1028}
1029
bd943159 1030static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1031{
30add22d 1032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u32 pp;
453c5420 1035 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1036
a0e99e68
DV
1037 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1038
bd943159 1039 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1040 pp = ironlake_get_pp_control(intel_dp);
bd943159 1041 pp &= ~EDP_FORCE_VDD;
bd943159 1042
453c5420
JB
1043 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1044 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1045
1046 I915_WRITE(pp_ctrl_reg, pp);
1047 POSTING_READ(pp_ctrl_reg);
99ea7127 1048
453c5420
JB
1049 /* Make sure sequencer is idle before allowing subsequent activity */
1050 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1051 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1052 msleep(intel_dp->panel_power_down_delay);
bd943159
KP
1053 }
1054}
5d613501 1055
bd943159
KP
1056static void ironlake_panel_vdd_work(struct work_struct *__work)
1057{
1058 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1059 struct intel_dp, panel_vdd_work);
30add22d 1060 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1061
627f7675 1062 mutex_lock(&dev->mode_config.mutex);
bd943159 1063 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1064 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP
1065}
1066
82a4d9c0 1067void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1068{
97af61f5
KP
1069 if (!is_edp(intel_dp))
1070 return;
5d613501 1071
bd943159
KP
1072 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1073 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1074
bd943159
KP
1075 intel_dp->want_panel_vdd = false;
1076
1077 if (sync) {
1078 ironlake_panel_vdd_off_sync(intel_dp);
1079 } else {
1080 /*
1081 * Queue the timer to fire a long
1082 * time from now (relative to the power down delay)
1083 * to keep the panel power up across a sequence of operations
1084 */
1085 schedule_delayed_work(&intel_dp->panel_vdd_work,
1086 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1087 }
5d613501
JB
1088}
1089
82a4d9c0 1090void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1091{
30add22d 1092 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1093 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1094 u32 pp;
453c5420 1095 u32 pp_ctrl_reg;
9934c132 1096
97af61f5 1097 if (!is_edp(intel_dp))
bd943159 1098 return;
99ea7127
KP
1099
1100 DRM_DEBUG_KMS("Turn eDP power on\n");
1101
1102 if (ironlake_edp_have_panel_power(intel_dp)) {
1103 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1104 return;
99ea7127 1105 }
9934c132 1106
99ea7127 1107 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1108
453c5420 1109 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP
1110 if (IS_GEN5(dev)) {
1111 /* ILK workaround: disable reset around power sequence */
1112 pp &= ~PANEL_POWER_RESET;
1113 I915_WRITE(PCH_PP_CONTROL, pp);
1114 POSTING_READ(PCH_PP_CONTROL);
1115 }
37c6c9b0 1116
1c0ae80a 1117 pp |= POWER_TARGET_ON;
99ea7127
KP
1118 if (!IS_GEN5(dev))
1119 pp |= PANEL_POWER_RESET;
1120
453c5420
JB
1121 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1122
1123 I915_WRITE(pp_ctrl_reg, pp);
1124 POSTING_READ(pp_ctrl_reg);
9934c132 1125
99ea7127 1126 ironlake_wait_panel_on(intel_dp);
9934c132 1127
05ce1a49
KP
1128 if (IS_GEN5(dev)) {
1129 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1130 I915_WRITE(PCH_PP_CONTROL, pp);
1131 POSTING_READ(PCH_PP_CONTROL);
1132 }
9934c132
JB
1133}
1134
82a4d9c0 1135void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1136{
30add22d 1137 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1138 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1139 u32 pp;
453c5420 1140 u32 pp_ctrl_reg;
9934c132 1141
97af61f5
KP
1142 if (!is_edp(intel_dp))
1143 return;
37c6c9b0 1144
99ea7127 1145 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1146
6cb49835 1147 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1148
453c5420 1149 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV
1150 /* We need to switch off panel power _and_ force vdd, for otherwise some
1151 * panels get very unhappy and cease to work. */
1152 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB
1153
1154 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1155
1156 I915_WRITE(pp_ctrl_reg, pp);
1157 POSTING_READ(pp_ctrl_reg);
9934c132 1158
35a38556
DV
1159 intel_dp->want_panel_vdd = false;
1160
99ea7127 1161 ironlake_wait_panel_off(intel_dp);
9934c132
JB
1162}
1163
d6c50ff8 1164void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1165{
da63a9f2
PZ
1166 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1167 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1168 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1169 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1170 u32 pp;
453c5420 1171 u32 pp_ctrl_reg;
32f9d658 1172
f01eca2e
KP
1173 if (!is_edp(intel_dp))
1174 return;
1175
28c97730 1176 DRM_DEBUG_KMS("\n");
01cb9ea6
JB
1177 /*
1178 * If we enable the backlight right away following a panel power
1179 * on, we may see slight flicker as the panel syncs with the eDP
1180 * link. So delay a bit to make sure the image is solid before
1181 * allowing it to appear.
1182 */
f01eca2e 1183 msleep(intel_dp->backlight_on_delay);
453c5420 1184 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1185 pp |= EDP_BLC_ENABLE;
453c5420
JB
1186
1187 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1188
1189 I915_WRITE(pp_ctrl_reg, pp);
1190 POSTING_READ(pp_ctrl_reg);
035aa3de
DV
1191
1192 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW
1193}
1194
d6c50ff8 1195void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1196{
30add22d 1197 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 u32 pp;
453c5420 1200 u32 pp_ctrl_reg;
32f9d658 1201
f01eca2e
KP
1202 if (!is_edp(intel_dp))
1203 return;
1204
035aa3de
DV
1205 intel_panel_disable_backlight(dev);
1206
28c97730 1207 DRM_DEBUG_KMS("\n");
453c5420 1208 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1209 pp &= ~EDP_BLC_ENABLE;
453c5420
JB
1210
1211 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1212
1213 I915_WRITE(pp_ctrl_reg, pp);
1214 POSTING_READ(pp_ctrl_reg);
f01eca2e 1215 msleep(intel_dp->backlight_off_delay);
32f9d658 1216}
a4fc5ed6 1217
2bd2ad64 1218static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1219{
da63a9f2
PZ
1220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222 struct drm_device *dev = crtc->dev;
d240f20f
JB
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
2bd2ad64
DV
1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1228
d240f20f
JB
1229 DRM_DEBUG_KMS("\n");
1230 dpa_ctl = I915_READ(DP_A);
0767935e
DV
1231 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234 /* We don't adjust intel_dp->DP while tearing down the link, to
1235 * facilitate link retraining (e.g. after hotplug). Hence clear all
1236 * enable bits here to ensure that we don't enable too much. */
1237 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1238 intel_dp->DP |= DP_PLL_ENABLE;
1239 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB
1240 POSTING_READ(DP_A);
1241 udelay(200);
d240f20f
JB
1242}
1243
2bd2ad64 1244static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1245{
da63a9f2
PZ
1246 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1247 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1248 struct drm_device *dev = crtc->dev;
d240f20f
JB
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 u32 dpa_ctl;
1251
2bd2ad64
DV
1252 assert_pipe_disabled(dev_priv,
1253 to_intel_crtc(crtc)->pipe);
1254
d240f20f 1255 dpa_ctl = I915_READ(DP_A);
0767935e
DV
1256 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1257 "dp pll off, should be on\n");
1258 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1259
1260 /* We can't rely on the value tracked for the DP register in
1261 * intel_dp->DP because link_down must not change that (otherwise link
1262 * re-training will fail. */
298b0b39 1263 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1264 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1265 POSTING_READ(DP_A);
d240f20f
JB
1266 udelay(200);
1267}
1268
c7ad3810 1269/* If the sink supports it, try to set the power state appropriately */
c19b0669 1270void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB
1271{
1272 int ret, i;
1273
1274 /* Should have a valid DPCD by this point */
1275 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1276 return;
1277
1278 if (mode != DRM_MODE_DPMS_ON) {
1279 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1280 DP_SET_POWER_D3);
1281 if (ret != 1)
1282 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1283 } else {
1284 /*
1285 * When turning on, we need to retry for 1ms to give the sink
1286 * time to wake up.
1287 */
1288 for (i = 0; i < 3; i++) {
1289 ret = intel_dp_aux_native_write_1(intel_dp,
1290 DP_SET_POWER,
1291 DP_SET_POWER_D0);
1292 if (ret == 1)
1293 break;
1294 msleep(1);
1295 }
1296 }
1297}
1298
19d8fe15
DV
1299static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1300 enum pipe *pipe)
d240f20f 1301{
19d8fe15
DV
1302 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1303 struct drm_device *dev = encoder->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 u32 tmp = I915_READ(intel_dp->output_reg);
1306
1307 if (!(tmp & DP_PORT_EN))
1308 return false;
1309
5d66d5b6 1310 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV
1311 *pipe = PORT_TO_PIPE_CPT(tmp);
1312 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1313 *pipe = PORT_TO_PIPE(tmp);
1314 } else {
1315 u32 trans_sel;
1316 u32 trans_dp;
1317 int i;
1318
1319 switch (intel_dp->output_reg) {
1320 case PCH_DP_B:
1321 trans_sel = TRANS_DP_PORT_SEL_B;
1322 break;
1323 case PCH_DP_C:
1324 trans_sel = TRANS_DP_PORT_SEL_C;
1325 break;
1326 case PCH_DP_D:
1327 trans_sel = TRANS_DP_PORT_SEL_D;
1328 break;
1329 default:
1330 return true;
1331 }
1332
1333 for_each_pipe(i) {
1334 trans_dp = I915_READ(TRANS_DP_CTL(i));
1335 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1336 *pipe = i;
1337 return true;
1338 }
1339 }
19d8fe15 1340
4a0833ec
DV
1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342 intel_dp->output_reg);
1343 }
d240f20f 1344
2af8898b 1345 return true;
19d8fe15 1346}
d240f20f 1347
e8cb4558 1348static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1349{
e8cb4558 1350 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV
1351
1352 /* Make sure the panel is off before trying to change the mode. But also
1353 * ensure that we have vdd while we switch off the panel. */
1354 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1355 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1356 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1357 ironlake_edp_panel_off(intel_dp);
3739850b
DV
1358
1359 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1360 if (!is_cpu_edp(intel_dp))
1361 intel_dp_link_down(intel_dp);
d240f20f
JB
1362}
1363
2bd2ad64 1364static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1365{
2bd2ad64 1366 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1367 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1368
3739850b
DV
1369 if (is_cpu_edp(intel_dp)) {
1370 intel_dp_link_down(intel_dp);
b2634017
JB
1371 if (!IS_VALLEYVIEW(dev))
1372 ironlake_edp_pll_off(intel_dp);
3739850b 1373 }
2bd2ad64
DV
1374}
1375
e8cb4558 1376static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1377{
e8cb4558
DV
1378 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1382
0c33d8d7
DV
1383 if (WARN_ON(dp_reg & DP_PORT_EN))
1384 return;
5d613501 1385
97af61f5 1386 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1387 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1388 intel_dp_start_link_train(intel_dp);
97af61f5 1389 ironlake_edp_panel_on(intel_dp);
bd943159 1390 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1391 intel_dp_complete_link_train(intel_dp);
f01eca2e 1392 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB
1393
1394 if (IS_VALLEYVIEW(dev)) {
1395 struct intel_digital_port *dport =
1396 enc_to_dig_port(&encoder->base);
1397 int channel = vlv_dport_to_channel(dport);
1398
1399 vlv_wait_port_ready(dev_priv, channel);
1400 }
d240f20f
JB
1401}
1402
2bd2ad64 1403static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1404{
2bd2ad64 1405 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1406 struct drm_device *dev = encoder->base.dev;
89b667f8 1407 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1408
b2634017 1409 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1410 ironlake_edp_pll_on(intel_dp);
89b667f8
JB
1411
1412 if (IS_VALLEYVIEW(dev)) {
1413 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1414 struct intel_crtc *intel_crtc =
1415 to_intel_crtc(encoder->base.crtc);
1416 int port = vlv_dport_to_channel(dport);
1417 int pipe = intel_crtc->pipe;
1418 u32 val;
1419
1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1421
1422 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1423 val = 0;
1424 if (pipe)
1425 val |= (1<<21);
1426 else
1427 val &= ~(1<<21);
1428 val |= 0x001000c4;
1429 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1430
1431 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1432 0x00760018);
1433 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1434 0x00400888);
1435 }
1436}
1437
1438static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1439{
1440 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1441 struct drm_device *dev = encoder->base.dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 int port = vlv_dport_to_channel(dport);
1444
1445 if (!IS_VALLEYVIEW(dev))
1446 return;
1447
1448 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1449
1450 /* Program Tx lane resets to default */
1451 intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1452 DPIO_PCS_TX_LANE2_RESET |
1453 DPIO_PCS_TX_LANE1_RESET);
1454 intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1455 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1456 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1457 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1458 DPIO_PCS_CLK_SOFT_RESET);
1459
1460 /* Fix up inter-pair skew failure */
1461 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1462 intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1463 intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP
1464}
1465
1466/*
df0c237d
JB
1467 * Native read with retry for link status and receiver capability reads for
1468 * cases where the sink may still be asleep.
a4fc5ed6
KP
1469 */
1470static bool
df0c237d
JB
1471intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1472 uint8_t *recv, int recv_bytes)
a4fc5ed6 1473{
61da5fab
JB
1474 int ret, i;
1475
df0c237d
JB
1476 /*
1477 * Sinks are *supposed* to come up within 1ms from an off state,
1478 * but we're also supposed to retry 3 times per the spec.
1479 */
61da5fab 1480 for (i = 0; i < 3; i++) {
df0c237d
JB
1481 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1482 recv_bytes);
1483 if (ret == recv_bytes)
61da5fab
JB
1484 return true;
1485 msleep(1);
1486 }
a4fc5ed6 1487
61da5fab 1488 return false;
a4fc5ed6
KP
1489}
1490
1491/*
1492 * Fetch AUX CH registers 0x202 - 0x207 which contain
1493 * link status information
1494 */
1495static bool
93f62dad 1496intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1497{
df0c237d
JB
1498 return intel_dp_aux_native_read_retry(intel_dp,
1499 DP_LANE0_1_STATUS,
93f62dad 1500 link_status,
df0c237d 1501 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP
1502}
1503
a4fc5ed6
KP
1504#if 0
1505static char *voltage_names[] = {
1506 "0.4V", "0.6V", "0.8V", "1.2V"
1507};
1508static char *pre_emph_names[] = {
1509 "0dB", "3.5dB", "6dB", "9.5dB"
1510};
1511static char *link_train_names[] = {
1512 "pattern 1", "pattern 2", "idle", "off"
1513};
1514#endif
1515
1516/*
1517 * These are source-specific values; current Intel hardware supports
1518 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1519 */
a4fc5ed6
KP
1520
1521static uint8_t
1a2eb460 1522intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1523{
30add22d 1524 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1525
e2fa6fba
P
1526 if (IS_VALLEYVIEW(dev))
1527 return DP_TRAIN_VOLTAGE_SWING_1200;
1528 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1a2eb460
KP
1529 return DP_TRAIN_VOLTAGE_SWING_800;
1530 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1531 return DP_TRAIN_VOLTAGE_SWING_1200;
1532 else
1533 return DP_TRAIN_VOLTAGE_SWING_800;
1534}
1535
1536static uint8_t
1537intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1538{
30add22d 1539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1540
22b8bf17 1541 if (HAS_DDI(dev)) {
d6c0d722
PZ
1542 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1543 case DP_TRAIN_VOLTAGE_SWING_400:
1544 return DP_TRAIN_PRE_EMPHASIS_9_5;
1545 case DP_TRAIN_VOLTAGE_SWING_600:
1546 return DP_TRAIN_PRE_EMPHASIS_6;
1547 case DP_TRAIN_VOLTAGE_SWING_800:
1548 return DP_TRAIN_PRE_EMPHASIS_3_5;
1549 case DP_TRAIN_VOLTAGE_SWING_1200:
1550 default:
1551 return DP_TRAIN_PRE_EMPHASIS_0;
1552 }
e2fa6fba
P
1553 } else if (IS_VALLEYVIEW(dev)) {
1554 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1555 case DP_TRAIN_VOLTAGE_SWING_400:
1556 return DP_TRAIN_PRE_EMPHASIS_9_5;
1557 case DP_TRAIN_VOLTAGE_SWING_600:
1558 return DP_TRAIN_PRE_EMPHASIS_6;
1559 case DP_TRAIN_VOLTAGE_SWING_800:
1560 return DP_TRAIN_PRE_EMPHASIS_3_5;
1561 case DP_TRAIN_VOLTAGE_SWING_1200:
1562 default:
1563 return DP_TRAIN_PRE_EMPHASIS_0;
1564 }
1565 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1a2eb460
KP
1566 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1567 case DP_TRAIN_VOLTAGE_SWING_400:
1568 return DP_TRAIN_PRE_EMPHASIS_6;
1569 case DP_TRAIN_VOLTAGE_SWING_600:
1570 case DP_TRAIN_VOLTAGE_SWING_800:
1571 return DP_TRAIN_PRE_EMPHASIS_3_5;
1572 default:
1573 return DP_TRAIN_PRE_EMPHASIS_0;
1574 }
1575 } else {
1576 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1577 case DP_TRAIN_VOLTAGE_SWING_400:
1578 return DP_TRAIN_PRE_EMPHASIS_6;
1579 case DP_TRAIN_VOLTAGE_SWING_600:
1580 return DP_TRAIN_PRE_EMPHASIS_6;
1581 case DP_TRAIN_VOLTAGE_SWING_800:
1582 return DP_TRAIN_PRE_EMPHASIS_3_5;
1583 case DP_TRAIN_VOLTAGE_SWING_1200:
1584 default:
1585 return DP_TRAIN_PRE_EMPHASIS_0;
1586 }
a4fc5ed6
KP
1587 }
1588}
1589
e2fa6fba
P
1590static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1591{
1592 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1595 unsigned long demph_reg_value, preemph_reg_value,
1596 uniqtranscale_reg_value;
1597 uint8_t train_set = intel_dp->train_set[0];
1598 int port;
1599
1600 if (dport->port == PORT_B)
1601 port = 0;
1602 else if (dport->port == PORT_C)
1603 port = 1;
1604 else
1605 BUG();
1606
89b667f8
JB
1607 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1608
e2fa6fba
P
1609 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1610 case DP_TRAIN_PRE_EMPHASIS_0:
1611 preemph_reg_value = 0x0004000;
1612 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1613 case DP_TRAIN_VOLTAGE_SWING_400:
1614 demph_reg_value = 0x2B405555;
1615 uniqtranscale_reg_value = 0x552AB83A;
1616 break;
1617 case DP_TRAIN_VOLTAGE_SWING_600:
1618 demph_reg_value = 0x2B404040;
1619 uniqtranscale_reg_value = 0x5548B83A;
1620 break;
1621 case DP_TRAIN_VOLTAGE_SWING_800:
1622 demph_reg_value = 0x2B245555;
1623 uniqtranscale_reg_value = 0x5560B83A;
1624 break;
1625 case DP_TRAIN_VOLTAGE_SWING_1200:
1626 demph_reg_value = 0x2B405555;
1627 uniqtranscale_reg_value = 0x5598DA3A;
1628 break;
1629 default:
1630 return 0;
1631 }
1632 break;
1633 case DP_TRAIN_PRE_EMPHASIS_3_5:
1634 preemph_reg_value = 0x0002000;
1635 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1636 case DP_TRAIN_VOLTAGE_SWING_400:
1637 demph_reg_value = 0x2B404040;
1638 uniqtranscale_reg_value = 0x5552B83A;
1639 break;
1640 case DP_TRAIN_VOLTAGE_SWING_600:
1641 demph_reg_value = 0x2B404848;
1642 uniqtranscale_reg_value = 0x5580B83A;
1643 break;
1644 case DP_TRAIN_VOLTAGE_SWING_800:
1645 demph_reg_value = 0x2B404040;
1646 uniqtranscale_reg_value = 0x55ADDA3A;
1647 break;
1648 default:
1649 return 0;
1650 }
1651 break;
1652 case DP_TRAIN_PRE_EMPHASIS_6:
1653 preemph_reg_value = 0x0000000;
1654 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1655 case DP_TRAIN_VOLTAGE_SWING_400:
1656 demph_reg_value = 0x2B305555;
1657 uniqtranscale_reg_value = 0x5570B83A;
1658 break;
1659 case DP_TRAIN_VOLTAGE_SWING_600:
1660 demph_reg_value = 0x2B2B4040;
1661 uniqtranscale_reg_value = 0x55ADDA3A;
1662 break;
1663 default:
1664 return 0;
1665 }
1666 break;
1667 case DP_TRAIN_PRE_EMPHASIS_9_5:
1668 preemph_reg_value = 0x0006000;
1669 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1670 case DP_TRAIN_VOLTAGE_SWING_400:
1671 demph_reg_value = 0x1B405555;
1672 uniqtranscale_reg_value = 0x55ADDA3A;
1673 break;
1674 default:
1675 return 0;
1676 }
1677 break;
1678 default:
1679 return 0;
1680 }
1681
e2fa6fba
P
1682 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1683 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1684 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1685 uniqtranscale_reg_value);
1686 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1687 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1688 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1689 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P
1690
1691 return 0;
1692}
1693
a4fc5ed6 1694static void
93f62dad 1695intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP
1696{
1697 uint8_t v = 0;
1698 uint8_t p = 0;
1699 int lane;
1a2eb460
KP
1700 uint8_t voltage_max;
1701 uint8_t preemph_max;
a4fc5ed6 1702
33a34e4e 1703 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV
1704 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1705 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP
1706
1707 if (this_v > v)
1708 v = this_v;
1709 if (this_p > p)
1710 p = this_p;
1711 }
1712
1a2eb460 1713 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP
1714 if (v >= voltage_max)
1715 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1716
1a2eb460
KP
1717 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1718 if (p >= preemph_max)
1719 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP
1720
1721 for (lane = 0; lane < 4; lane++)
33a34e4e 1722 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP
1723}
1724
1725static uint32_t
f0a3424e 1726intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1727{
3cf2efb1 1728 uint32_t signal_levels = 0;
a4fc5ed6 1729
3cf2efb1 1730 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP
1731 case DP_TRAIN_VOLTAGE_SWING_400:
1732 default:
1733 signal_levels |= DP_VOLTAGE_0_4;
1734 break;
1735 case DP_TRAIN_VOLTAGE_SWING_600:
1736 signal_levels |= DP_VOLTAGE_0_6;
1737 break;
1738 case DP_TRAIN_VOLTAGE_SWING_800:
1739 signal_levels |= DP_VOLTAGE_0_8;
1740 break;
1741 case DP_TRAIN_VOLTAGE_SWING_1200:
1742 signal_levels |= DP_VOLTAGE_1_2;
1743 break;
1744 }
3cf2efb1 1745 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP
1746 case DP_TRAIN_PRE_EMPHASIS_0:
1747 default:
1748 signal_levels |= DP_PRE_EMPHASIS_0;
1749 break;
1750 case DP_TRAIN_PRE_EMPHASIS_3_5:
1751 signal_levels |= DP_PRE_EMPHASIS_3_5;
1752 break;
1753 case DP_TRAIN_PRE_EMPHASIS_6:
1754 signal_levels |= DP_PRE_EMPHASIS_6;
1755 break;
1756 case DP_TRAIN_PRE_EMPHASIS_9_5:
1757 signal_levels |= DP_PRE_EMPHASIS_9_5;
1758 break;
1759 }
1760 return signal_levels;
1761}
1762
e3421a18
ZW
1763/* Gen6's DP voltage swing and pre-emphasis control */
1764static uint32_t
1765intel_gen6_edp_signal_levels(uint8_t train_set)
1766{
3c5a62b5
YL
1767 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1768 DP_TRAIN_PRE_EMPHASIS_MASK);
1769 switch (signal_levels) {
e3421a18 1770 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL
1771 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1772 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1773 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1774 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1775 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL
1776 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1777 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1778 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL
1779 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1780 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1781 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL
1782 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1783 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1784 default:
3c5a62b5
YL
1785 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1786 "0x%x\n", signal_levels);
1787 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW
1788 }
1789}
1790
1a2eb460
KP
1791/* Gen7's DP voltage swing and pre-emphasis control */
1792static uint32_t
1793intel_gen7_edp_signal_levels(uint8_t train_set)
1794{
1795 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1796 DP_TRAIN_PRE_EMPHASIS_MASK);
1797 switch (signal_levels) {
1798 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1799 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1800 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1801 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1802 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1803 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1804
1805 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1806 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1807 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1808 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1809
1810 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1811 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1812 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1813 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1814
1815 default:
1816 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1817 "0x%x\n", signal_levels);
1818 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1819 }
1820}
1821
d6c0d722
PZ
1822/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1823static uint32_t
f0a3424e 1824intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1825{
d6c0d722
PZ
1826 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1827 DP_TRAIN_PRE_EMPHASIS_MASK);
1828 switch (signal_levels) {
1829 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1830 return DDI_BUF_EMP_400MV_0DB_HSW;
1831 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1832 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1833 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1834 return DDI_BUF_EMP_400MV_6DB_HSW;
1835 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1836 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1837
d6c0d722
PZ
1838 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1839 return DDI_BUF_EMP_600MV_0DB_HSW;
1840 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1841 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1842 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1843 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1844
d6c0d722
PZ
1845 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1846 return DDI_BUF_EMP_800MV_0DB_HSW;
1847 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1848 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1849 default:
1850 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1851 "0x%x\n", signal_levels);
1852 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1853 }
a4fc5ed6
KP
1854}
1855
f0a3424e
PZ
1856/* Properly updates "DP" with the correct signal levels. */
1857static void
1858intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1859{
1860 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1861 struct drm_device *dev = intel_dig_port->base.base.dev;
1862 uint32_t signal_levels, mask;
1863 uint8_t train_set = intel_dp->train_set[0];
1864
22b8bf17 1865 if (HAS_DDI(dev)) {
f0a3424e
PZ
1866 signal_levels = intel_hsw_signal_levels(train_set);
1867 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P
1868 } else if (IS_VALLEYVIEW(dev)) {
1869 signal_levels = intel_vlv_signal_levels(intel_dp);
1870 mask = 0;
1871 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
f0a3424e
PZ
1872 signal_levels = intel_gen7_edp_signal_levels(train_set);
1873 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1874 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1875 signal_levels = intel_gen6_edp_signal_levels(train_set);
1876 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1877 } else {
1878 signal_levels = intel_gen4_signal_levels(train_set);
1879 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1880 }
1881
1882 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1883
1884 *DP = (*DP & ~mask) | signal_levels;
1885}
1886
a4fc5ed6 1887static bool
ea5b213a 1888intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1889 uint32_t dp_reg_value,
58e10eb9 1890 uint8_t dp_train_pat)
a4fc5ed6 1891{
174edf1f
PZ
1892 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1893 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1894 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1895 enum port port = intel_dig_port->port;
a4fc5ed6 1896 int ret;
d6c0d722 1897 uint32_t temp;
a4fc5ed6 1898
22b8bf17 1899 if (HAS_DDI(dev)) {
174edf1f 1900 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ
1901
1902 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1903 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1904 else
1905 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1906
1907 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1908 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1909 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1910
10aa17c8
PZ
1911 if (port != PORT_A) {
1912 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1913 I915_WRITE(DP_TP_CTL(port), temp);
1914
1915 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1916 DP_TP_STATUS_IDLE_DONE), 1))
1917 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1918
1919 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1920 }
d6c0d722 1921
d6c0d722
PZ
1922 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1923
1924 break;
1925 case DP_TRAINING_PATTERN_1:
1926 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1927 break;
1928 case DP_TRAINING_PATTERN_2:
1929 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1930 break;
1931 case DP_TRAINING_PATTERN_3:
1932 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1933 break;
1934 }
174edf1f 1935 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ
1936
1937 } else if (HAS_PCH_CPT(dev) &&
1938 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ
1939 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1940
1941 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1942 case DP_TRAINING_PATTERN_DISABLE:
1943 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1944 break;
1945 case DP_TRAINING_PATTERN_1:
1946 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1947 break;
1948 case DP_TRAINING_PATTERN_2:
1949 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1950 break;
1951 case DP_TRAINING_PATTERN_3:
1952 DRM_ERROR("DP training pattern 3 not supported\n");
1953 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1954 break;
1955 }
1956
1957 } else {
1958 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1959
1960 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1961 case DP_TRAINING_PATTERN_DISABLE:
1962 dp_reg_value |= DP_LINK_TRAIN_OFF;
1963 break;
1964 case DP_TRAINING_PATTERN_1:
1965 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1966 break;
1967 case DP_TRAINING_PATTERN_2:
1968 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1969 break;
1970 case DP_TRAINING_PATTERN_3:
1971 DRM_ERROR("DP training pattern 3 not supported\n");
1972 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1973 break;
1974 }
1975 }
1976
ea5b213a
CW
1977 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1978 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1979
ea5b213a 1980 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP
1981 DP_TRAINING_PATTERN_SET,
1982 dp_train_pat);
1983
47ea7542
PZ
1984 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1985 DP_TRAINING_PATTERN_DISABLE) {
1986 ret = intel_dp_aux_native_write(intel_dp,
1987 DP_TRAINING_LANE0_SET,
1988 intel_dp->train_set,
1989 intel_dp->lane_count);
1990 if (ret != intel_dp->lane_count)
1991 return false;
1992 }
a4fc5ed6
KP
1993
1994 return true;
1995}
1996
33a34e4e 1997/* Enable corresponding port and start training pattern 1 */
c19b0669 1998void
33a34e4e 1999intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2000{
da63a9f2 2001 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2002 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP
2003 int i;
2004 uint8_t voltage;
2005 bool clock_recovery = false;
cdb0e95b 2006 int voltage_tries, loop_tries;
ea5b213a 2007 uint32_t DP = intel_dp->DP;
a4fc5ed6 2008
affa9354 2009 if (HAS_DDI(dev))
c19b0669
PZ
2010 intel_ddi_prepare_link_retrain(encoder);
2011
3cf2efb1
CW
2012 /* Write the link configuration data */
2013 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2014 intel_dp->link_configuration,
2015 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP
2016
2017 DP |= DP_PORT_EN;
1a2eb460 2018
33a34e4e 2019 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2020 voltage = 0xff;
cdb0e95b
KP
2021 voltage_tries = 0;
2022 loop_tries = 0;
a4fc5ed6
KP
2023 clock_recovery = false;
2024 for (;;) {
33a34e4e 2025 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2026 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ
2027
2028 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2029
a7c9655f 2030 /* Set training pattern 1 */
47ea7542 2031 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ
2032 DP_TRAINING_PATTERN_1 |
2033 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2034 break;
a4fc5ed6 2035
a7c9655f 2036 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP
2037 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2038 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2039 break;
93f62dad 2040 }
a4fc5ed6 2041
01916270 2042 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2043 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW
2044 clock_recovery = true;
2045 break;
2046 }
2047
2048 /* Check to see if we've tried the max voltage */
2049 for (i = 0; i < intel_dp->lane_count; i++)
2050 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2051 break;
3b4f819d 2052 if (i == intel_dp->lane_count) {
b06fbda3
DV
2053 ++loop_tries;
2054 if (loop_tries == 5) {
cdb0e95b
KP
2055 DRM_DEBUG_KMS("too many full retries, give up\n");
2056 break;
2057 }
2058 memset(intel_dp->train_set, 0, 4);
2059 voltage_tries = 0;
2060 continue;
2061 }
a4fc5ed6 2062
3cf2efb1 2063 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2064 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2065 ++voltage_tries;
b06fbda3
DV
2066 if (voltage_tries == 5) {
2067 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2068 break;
2069 }
2070 } else
2071 voltage_tries = 0;
2072 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2073
3cf2efb1 2074 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2075 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP
2076 }
2077
33a34e4e
JB
2078 intel_dp->DP = DP;
2079}
2080
c19b0669 2081void
33a34e4e
JB
2082intel_dp_complete_link_train(struct intel_dp *intel_dp)
2083{
33a34e4e 2084 bool channel_eq = false;
37f80975 2085 int tries, cr_tries;
33a34e4e
JB
2086 uint32_t DP = intel_dp->DP;
2087
a4fc5ed6
KP
2088 /* channel equalization */
2089 tries = 0;
37f80975 2090 cr_tries = 0;
a4fc5ed6
KP
2091 channel_eq = false;
2092 for (;;) {
93f62dad 2093 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2094
37f80975
JB
2095 if (cr_tries > 5) {
2096 DRM_ERROR("failed to train DP, aborting\n");
2097 intel_dp_link_down(intel_dp);
2098 break;
2099 }
2100
f0a3424e 2101 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2102
a4fc5ed6 2103 /* channel eq pattern */
47ea7542 2104 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ
2105 DP_TRAINING_PATTERN_2 |
2106 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP
2107 break;
2108
a7c9655f 2109 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2110 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2111 break;
a4fc5ed6 2112
37f80975 2113 /* Make sure clock is still ok */
01916270 2114 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB
2115 intel_dp_start_link_train(intel_dp);
2116 cr_tries++;
2117 continue;
2118 }
2119
1ffdff13 2120 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW
2121 channel_eq = true;
2122 break;
2123 }
a4fc5ed6 2124
37f80975
JB
2125 /* Try 5 times, then try clock recovery if that fails */
2126 if (tries > 5) {
2127 intel_dp_link_down(intel_dp);
2128 intel_dp_start_link_train(intel_dp);
2129 tries = 0;
2130 cr_tries++;
2131 continue;
2132 }
a4fc5ed6 2133
3cf2efb1 2134 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2135 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2136 ++tries;
869184a6 2137 }
3cf2efb1 2138
d6c0d722
PZ
2139 if (channel_eq)
2140 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2141
47ea7542 2142 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP
2143}
2144
2145static void
ea5b213a 2146intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2147{
da63a9f2
PZ
2148 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2149 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2150 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV
2151 struct intel_crtc *intel_crtc =
2152 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2153 uint32_t DP = intel_dp->DP;
a4fc5ed6 2154
c19b0669
PZ
2155 /*
2156 * DDI code has a strict mode set sequence and we should try to respect
2157 * it, otherwise we might hang the machine in many different ways. So we
2158 * really should be disabling the port only on a complete crtc_disable
2159 * sequence. This function is just called under two conditions on DDI
2160 * code:
2161 * - Link train failed while doing crtc_enable, and on this case we
2162 * really should respect the mode set sequence and wait for a
2163 * crtc_disable.
2164 * - Someone turned the monitor off and intel_dp_check_link_status
2165 * called us. We don't need to disable the whole port on this case, so
2166 * when someone turns the monitor on again,
2167 * intel_ddi_prepare_link_retrain will take care of redoing the link
2168 * train.
2169 */
affa9354 2170 if (HAS_DDI(dev))
c19b0669
PZ
2171 return;
2172
0c33d8d7 2173 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW
2174 return;
2175
28c97730 2176 DRM_DEBUG_KMS("\n");
32f9d658 2177
1a2eb460 2178 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2179 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2180 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW
2181 } else {
2182 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2183 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2184 }
fe255d00 2185 POSTING_READ(intel_dp->output_reg);
5eb08b69 2186
ab527efc
DV
2187 /* We don't really know why we're doing this */
2188 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2189
493a7081 2190 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2191 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2192 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2193
5bddd17f
EA
2194 /* Hardware workaround: leaving our transcoder select
2195 * set to transcoder B while it's off will prevent the
2196 * corresponding HDMI output on transcoder A.
2197 *
2198 * Combine this with another hardware workaround:
2199 * transcoder select bit can only be cleared while the
2200 * port is enabled.
2201 */
2202 DP &= ~DP_PIPEB_SELECT;
2203 I915_WRITE(intel_dp->output_reg, DP);
2204
2205 /* Changes to enable or select take place the vblank
2206 * after being written.
2207 */
ff50afe9
DV
2208 if (WARN_ON(crtc == NULL)) {
2209 /* We should never try to disable a port without a crtc
2210 * attached. For paranoia keep the code around for a
2211 * bit. */
31acbcc4
CW
2212 POSTING_READ(intel_dp->output_reg);
2213 msleep(50);
2214 } else
ab527efc 2215 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA
2216 }
2217
832afda6 2218 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW
2219 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2220 POSTING_READ(intel_dp->output_reg);
f01eca2e 2221 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP
2222}
2223
26d61aad
KP
2224static bool
2225intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2226{
577c7a50
DL
2227 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2228
92fd8fd1 2229 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ
2230 sizeof(intel_dp->dpcd)) == 0)
2231 return false; /* aux transfer failed */
92fd8fd1 2232
577c7a50
DL
2233 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2234 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2235 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2236
edb39244
AJ
2237 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2238 return false; /* DPCD not present */
2239
2240 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2241 DP_DWN_STRM_PORT_PRESENT))
2242 return true; /* native DP sink */
2243
2244 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2245 return true; /* no per-port downstream info */
2246
2247 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2248 intel_dp->downstream_ports,
2249 DP_MAX_DOWNSTREAM_PORTS) == 0)
2250 return false; /* downstream port status fetch failed */
2251
2252 return true;
92fd8fd1
KP
2253}
2254
0d198328
AJ
2255static void
2256intel_dp_probe_oui(struct intel_dp *intel_dp)
2257{
2258 u8 buf[3];
2259
2260 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2261 return;
2262
351cfc34
DV
2263 ironlake_edp_panel_vdd_on(intel_dp);
2264
0d198328
AJ
2265 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2266 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2267 buf[0], buf[1], buf[2]);
2268
2269 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2270 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2271 buf[0], buf[1], buf[2]);
351cfc34
DV
2272
2273 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ
2274}
2275
a60f0e38
JB
2276static bool
2277intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2278{
2279 int ret;
2280
2281 ret = intel_dp_aux_native_read_retry(intel_dp,
2282 DP_DEVICE_SERVICE_IRQ_VECTOR,
2283 sink_irq_vector, 1);
2284 if (!ret)
2285 return false;
2286
2287 return true;
2288}
2289
2290static void
2291intel_dp_handle_test_request(struct intel_dp *intel_dp)
2292{
2293 /* NAK by default */
9324cf7f 2294 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB
2295}
2296
a4fc5ed6
KP
2297/*
2298 * According to DP spec
2299 * 5.1.2:
2300 * 1. Read DPCD
2301 * 2. Configure link according to Receiver Capabilities
2302 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2303 * 4. Check link status on receipt of hot-plug interrupt
2304 */
2305
00c09d70 2306void
ea5b213a 2307intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2308{
da63a9f2 2309 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2310 u8 sink_irq_vector;
93f62dad 2311 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2312
da63a9f2 2313 if (!intel_encoder->connectors_active)
d2b996ac 2314 return;
59cd09e1 2315
da63a9f2 2316 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP
2317 return;
2318
92fd8fd1 2319 /* Try to read receiver status if the link appears to be up */
93f62dad 2320 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2321 intel_dp_link_down(intel_dp);
a4fc5ed6
KP
2322 return;
2323 }
2324
92fd8fd1 2325 /* Now read the DPCD to see if it's actually running */
26d61aad 2326 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB
2327 intel_dp_link_down(intel_dp);
2328 return;
2329 }
2330
a60f0e38
JB
2331 /* Try to read the source of the interrupt */
2332 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2333 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2334 /* Clear interrupt source */
2335 intel_dp_aux_native_write_1(intel_dp,
2336 DP_DEVICE_SERVICE_IRQ_VECTOR,
2337 sink_irq_vector);
2338
2339 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2340 intel_dp_handle_test_request(intel_dp);
2341 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2342 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2343 }
2344
1ffdff13 2345 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2346 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2347 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB
2348 intel_dp_start_link_train(intel_dp);
2349 intel_dp_complete_link_train(intel_dp);
2350 }
a4fc5ed6 2351}
a4fc5ed6 2352
caf9ab24 2353/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2354static enum drm_connector_status
26d61aad 2355intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2356{
caf9ab24
AJ
2357 uint8_t *dpcd = intel_dp->dpcd;
2358 bool hpd;
2359 uint8_t type;
2360
2361 if (!intel_dp_get_dpcd(intel_dp))
2362 return connector_status_disconnected;
2363
2364 /* if there's no downstream port, we're done */
2365 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2366 return connector_status_connected;
caf9ab24
AJ
2367
2368 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2369 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2370 if (hpd) {
23235177 2371 uint8_t reg;
caf9ab24 2372 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2373 &reg, 1))
caf9ab24 2374 return connector_status_unknown;
23235177
AJ
2375 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2376 : connector_status_disconnected;
caf9ab24
AJ
2377 }
2378
2379 /* If no HPD, poke DDC gently */
2380 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2381 return connector_status_connected;
caf9ab24
AJ
2382
2383 /* Well we tried, say unknown for unreliable port types */
2384 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2385 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2386 return connector_status_unknown;
2387
2388 /* Anything else is out of spec, warn and ignore */
2389 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2390 return connector_status_disconnected;
71ba9000
AJ
2391}
2392
5eb08b69 2393static enum drm_connector_status
a9756bb5 2394ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2395{
30add22d 2396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL
2397 struct drm_i915_private *dev_priv = dev->dev_private;
2398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW
2399 enum drm_connector_status status;
2400
fe16d949
CW
2401 /* Can't disconnect eDP, but you can close the lid... */
2402 if (is_edp(intel_dp)) {
30add22d 2403 status = intel_panel_detect(dev);
fe16d949
CW
2404 if (status == connector_status_unknown)
2405 status = connector_status_connected;
2406 return status;
2407 }
01cb9ea6 2408
1b469639
DL
2409 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2410 return connector_status_disconnected;
2411
26d61aad 2412 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW
2413}
2414
a4fc5ed6 2415static enum drm_connector_status
a9756bb5 2416g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2417{
30add22d 2418 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2419 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2420 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2421 uint32_t bit;
5eb08b69 2422
35aad75f
JB
2423 /* Can't disconnect eDP, but you can close the lid... */
2424 if (is_edp(intel_dp)) {
2425 enum drm_connector_status status;
2426
2427 status = intel_panel_detect(dev);
2428 if (status == connector_status_unknown)
2429 status = connector_status_connected;
2430 return status;
2431 }
2432
34f2be46
VS
2433 switch (intel_dig_port->port) {
2434 case PORT_B:
26739f12 2435 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2436 break;
34f2be46 2437 case PORT_C:
26739f12 2438 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2439 break;
34f2be46 2440 case PORT_D:
26739f12 2441 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP
2442 break;
2443 default:
2444 return connector_status_unknown;
2445 }
2446
10f76a38 2447 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP
2448 return connector_status_disconnected;
2449
26d61aad 2450 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW
2451}
2452
8c241fef
KP
2453static struct edid *
2454intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2455{
9cd300e0 2456 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2457
9cd300e0
JN
2458 /* use cached edid if we have one */
2459 if (intel_connector->edid) {
2460 struct edid *edid;
2461 int size;
2462
2463 /* invalid edid */
2464 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB
2465 return NULL;
2466
9cd300e0 2467 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB
2468 edid = kmalloc(size, GFP_KERNEL);
2469 if (!edid)
2470 return NULL;
2471
9cd300e0 2472 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB
2473 return edid;
2474 }
8c241fef 2475
9cd300e0 2476 return drm_get_edid(connector, adapter);
8c241fef
KP
2477}
2478
2479static int
2480intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2481{
9cd300e0 2482 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2483
9cd300e0
JN
2484 /* use cached edid if we have one */
2485 if (intel_connector->edid) {
2486 /* invalid edid */
2487 if (IS_ERR(intel_connector->edid))
2488 return 0;
2489
2490 return intel_connector_update_modes(connector,
2491 intel_connector->edid);
d6f24d0f
JB
2492 }
2493
9cd300e0 2494 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP
2495}
2496
a9756bb5
ZW
2497static enum drm_connector_status
2498intel_dp_detect(struct drm_connector *connector, bool force)
2499{
2500 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ
2501 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2502 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2503 struct drm_device *dev = connector->dev;
a9756bb5
ZW
2504 enum drm_connector_status status;
2505 struct edid *edid = NULL;
2506
2507 intel_dp->has_audio = false;
2508
2509 if (HAS_PCH_SPLIT(dev))
2510 status = ironlake_dp_detect(intel_dp);
2511 else
2512 status = g4x_dp_detect(intel_dp);
1b9be9d0 2513
a9756bb5
ZW
2514 if (status != connector_status_connected)
2515 return status;
2516
0d198328
AJ
2517 intel_dp_probe_oui(intel_dp);
2518
c3e5f67b
DV
2519 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2520 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2521 } else {
8c241fef 2522 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW
2523 if (edid) {
2524 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW
2525 kfree(edid);
2526 }
a9756bb5
ZW
2527 }
2528
d63885da
PZ
2529 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2530 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2531 return connector_status_connected;
a4fc5ed6
KP
2532}
2533
2534static int intel_dp_get_modes(struct drm_connector *connector)
2535{
df0e9248 2536 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2537 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2538 struct drm_device *dev = connector->dev;
32f9d658 2539 int ret;
a4fc5ed6
KP
2540
2541 /* We should parse the EDID data and find out if it has an audio sink
2542 */
2543
8c241fef 2544 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2545 if (ret)
32f9d658
ZW
2546 return ret;
2547
f8779fda 2548 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2549 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2550 struct drm_display_mode *mode;
dd06f90e
JN
2551 mode = drm_mode_duplicate(dev,
2552 intel_connector->panel.fixed_mode);
f8779fda 2553 if (mode) {
32f9d658
ZW
2554 drm_mode_probed_add(connector, mode);
2555 return 1;
2556 }
2557 }
2558 return 0;
a4fc5ed6
KP
2559}
2560
1aad7ac0
CW
2561static bool
2562intel_dp_detect_audio(struct drm_connector *connector)
2563{
2564 struct intel_dp *intel_dp = intel_attached_dp(connector);
2565 struct edid *edid;
2566 bool has_audio = false;
2567
8c241fef 2568 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW
2569 if (edid) {
2570 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW
2571 kfree(edid);
2572 }
2573
2574 return has_audio;
2575}
2576
f684960e
CW
2577static int
2578intel_dp_set_property(struct drm_connector *connector,
2579 struct drm_property *property,
2580 uint64_t val)
2581{
e953fd7b 2582 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2583 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ
2584 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2585 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW
2586 int ret;
2587
662595df 2588 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW
2589 if (ret)
2590 return ret;
2591
3f43c48d 2592 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW
2593 int i = val;
2594 bool has_audio;
2595
2596 if (i == intel_dp->force_audio)
f684960e
CW
2597 return 0;
2598
1aad7ac0 2599 intel_dp->force_audio = i;
f684960e 2600
c3e5f67b 2601 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW
2602 has_audio = intel_dp_detect_audio(connector);
2603 else
c3e5f67b 2604 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW
2605
2606 if (has_audio == intel_dp->has_audio)
f684960e
CW
2607 return 0;
2608
1aad7ac0 2609 intel_dp->has_audio = has_audio;
f684960e
CW
2610 goto done;
2611 }
2612
e953fd7b 2613 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS
2614 switch (val) {
2615 case INTEL_BROADCAST_RGB_AUTO:
2616 intel_dp->color_range_auto = true;
2617 break;
2618 case INTEL_BROADCAST_RGB_FULL:
2619 intel_dp->color_range_auto = false;
2620 intel_dp->color_range = 0;
2621 break;
2622 case INTEL_BROADCAST_RGB_LIMITED:
2623 intel_dp->color_range_auto = false;
2624 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2625 break;
2626 default:
2627 return -EINVAL;
2628 }
e953fd7b
CW
2629 goto done;
2630 }
2631
53b41837
YN
2632 if (is_edp(intel_dp) &&
2633 property == connector->dev->mode_config.scaling_mode_property) {
2634 if (val == DRM_MODE_SCALE_NONE) {
2635 DRM_DEBUG_KMS("no scaling not supported\n");
2636 return -EINVAL;
2637 }
2638
2639 if (intel_connector->panel.fitting_mode == val) {
2640 /* the eDP scaling property is not changed */
2641 return 0;
2642 }
2643 intel_connector->panel.fitting_mode = val;
2644
2645 goto done;
2646 }
2647
f684960e
CW
2648 return -EINVAL;
2649
2650done:
c0c36b94
CW
2651 if (intel_encoder->base.crtc)
2652 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW
2653
2654 return 0;
2655}
2656
a4fc5ed6 2657static void
0206e353 2658intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2659{
be3cd5e3 2660 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2661 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2662
9cd300e0
JN
2663 if (!IS_ERR_OR_NULL(intel_connector->edid))
2664 kfree(intel_connector->edid);
2665
dc652f90 2666 if (is_edp(intel_dp))
1d508706 2667 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2668
a4fc5ed6
KP
2669 drm_sysfs_connector_remove(connector);
2670 drm_connector_cleanup(connector);
55f78c43 2671 kfree(connector);
a4fc5ed6
KP
2672}
2673
00c09d70 2674void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2675{
da63a9f2
PZ
2676 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2677 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV
2678
2679 i2c_del_adapter(&intel_dp->adapter);
2680 drm_encoder_cleanup(encoder);
bd943159
KP
2681 if (is_edp(intel_dp)) {
2682 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2683 ironlake_panel_vdd_off_sync(intel_dp);
2684 }
da63a9f2 2685 kfree(intel_dig_port);
24d05927
DV
2686}
2687
a4fc5ed6 2688static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2689 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP
2690};
2691
2692static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2693 .dpms = intel_connector_dpms,
a4fc5ed6
KP
2694 .detect = intel_dp_detect,
2695 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2696 .set_property = intel_dp_set_property,
a4fc5ed6
KP
2697 .destroy = intel_dp_destroy,
2698};
2699
2700static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2701 .get_modes = intel_dp_get_modes,
2702 .mode_valid = intel_dp_mode_valid,
df0e9248 2703 .best_encoder = intel_best_encoder,
a4fc5ed6
KP
2704};
2705
a4fc5ed6 2706static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2707 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP
2708};
2709
995b6762 2710static void
21d40d37 2711intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2712{
fa90ecef 2713 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2714
885a5014 2715 intel_dp_check_link_status(intel_dp);
c8110e52 2716}
6207937d 2717
e3421a18
ZW
2718/* Return which DP Port should be selected for Transcoder DP control */
2719int
0206e353 2720intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW
2721{
2722 struct drm_device *dev = crtc->dev;
fa90ecef
PZ
2723 struct intel_encoder *intel_encoder;
2724 struct intel_dp *intel_dp;
e3421a18 2725
fa90ecef
PZ
2726 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2727 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2728
fa90ecef
PZ
2729 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2730 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2731 return intel_dp->output_reg;
e3421a18 2732 }
ea5b213a 2733
e3421a18
ZW
2734 return -1;
2735}
2736
36e83a18 2737/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2738bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY
2739{
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct child_device_config *p_child;
2742 int i;
2743
2744 if (!dev_priv->child_dev_num)
2745 return false;
2746
2747 for (i = 0; i < dev_priv->child_dev_num; i++) {
2748 p_child = dev_priv->child_dev + i;
2749
2750 if (p_child->dvo_port == PORT_IDPD &&
2751 p_child->device_type == DEVICE_TYPE_eDP)
2752 return true;
2753 }
2754 return false;
2755}
2756
f684960e
CW
2757static void
2758intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2759{
53b41837
YN
2760 struct intel_connector *intel_connector = to_intel_connector(connector);
2761
3f43c48d 2762 intel_attach_force_audio_property(connector);
e953fd7b 2763 intel_attach_broadcast_rgb_property(connector);
55bc60db 2764 intel_dp->color_range_auto = true;
53b41837
YN
2765
2766 if (is_edp(intel_dp)) {
2767 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC
2768 drm_object_attach_property(
2769 &connector->base,
53b41837 2770 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN
2771 DRM_MODE_SCALE_ASPECT);
2772 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2773 }
f684960e
CW
2774}
2775
67a54566
DV
2776static void
2777intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN
2778 struct intel_dp *intel_dp,
2779 struct edp_power_seq *out)
67a54566
DV
2780{
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct edp_power_seq cur, vbt, spec, final;
2783 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB
2784 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2785
2786 if (HAS_PCH_SPLIT(dev)) {
2787 pp_control_reg = PCH_PP_CONTROL;
2788 pp_on_reg = PCH_PP_ON_DELAYS;
2789 pp_off_reg = PCH_PP_OFF_DELAYS;
2790 pp_div_reg = PCH_PP_DIVISOR;
2791 } else {
2792 pp_control_reg = PIPEA_PP_CONTROL;
2793 pp_on_reg = PIPEA_PP_ON_DELAYS;
2794 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2795 pp_div_reg = PIPEA_PP_DIVISOR;
2796 }
67a54566
DV
2797
2798 /* Workaround: Need to write PP_CONTROL with the unlock key as
2799 * the very first thing. */
453c5420
JB
2800 pp = ironlake_get_pp_control(intel_dp);
2801 I915_WRITE(pp_control_reg, pp);
67a54566 2802
453c5420
JB
2803 pp_on = I915_READ(pp_on_reg);
2804 pp_off = I915_READ(pp_off_reg);
2805 pp_div = I915_READ(pp_div_reg);
67a54566
DV
2806
2807 /* Pull timing values out of registers */
2808 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2809 PANEL_POWER_UP_DELAY_SHIFT;
2810
2811 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2812 PANEL_LIGHT_ON_DELAY_SHIFT;
2813
2814 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2815 PANEL_LIGHT_OFF_DELAY_SHIFT;
2816
2817 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2818 PANEL_POWER_DOWN_DELAY_SHIFT;
2819
2820 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2821 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2822
2823 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2824 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2825
2826 vbt = dev_priv->edp.pps;
2827
2828 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2829 * our hw here, which are all in 100usec. */
2830 spec.t1_t3 = 210 * 10;
2831 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2832 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2833 spec.t10 = 500 * 10;
2834 /* This one is special and actually in units of 100ms, but zero
2835 * based in the hw (so we need to add 100 ms). But the sw vbt
2836 * table multiplies it with 1000 to make it in units of 100usec,
2837 * too. */
2838 spec.t11_t12 = (510 + 100) * 10;
2839
2840 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2841 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2842
2843 /* Use the max of the register settings and vbt. If both are
2844 * unset, fall back to the spec limits. */
2845#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2846 spec.field : \
2847 max(cur.field, vbt.field))
2848 assign_final(t1_t3);
2849 assign_final(t8);
2850 assign_final(t9);
2851 assign_final(t10);
2852 assign_final(t11_t12);
2853#undef assign_final
2854
2855#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2856 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2857 intel_dp->backlight_on_delay = get_delay(t8);
2858 intel_dp->backlight_off_delay = get_delay(t9);
2859 intel_dp->panel_power_down_delay = get_delay(t10);
2860 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2861#undef get_delay
2862
f30d26e4
JN
2863 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2864 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2865 intel_dp->panel_power_cycle_delay);
2866
2867 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2868 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2869
2870 if (out)
2871 *out = final;
2872}
2873
2874static void
2875intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2876 struct intel_dp *intel_dp,
2877 struct edp_power_seq *seq)
2878{
2879 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB
2880 u32 pp_on, pp_off, pp_div, port_sel = 0;
2881 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2882 int pp_on_reg, pp_off_reg, pp_div_reg;
2883
2884 if (HAS_PCH_SPLIT(dev)) {
2885 pp_on_reg = PCH_PP_ON_DELAYS;
2886 pp_off_reg = PCH_PP_OFF_DELAYS;
2887 pp_div_reg = PCH_PP_DIVISOR;
2888 } else {
2889 pp_on_reg = PIPEA_PP_ON_DELAYS;
2890 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2891 pp_div_reg = PIPEA_PP_DIVISOR;
2892 }
2893
2894 if (IS_VALLEYVIEW(dev))
2895 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
f30d26e4 2896
67a54566 2897 /* And finally store the new values in the power sequencer. */
f30d26e4
JN
2898 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2899 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2900 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2901 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV
2902 /* Compute the divisor for the pp clock, simply match the Bspec
2903 * formula. */
453c5420 2904 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2905 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV
2906 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2907
2908 /* Haswell doesn't have any port selection bits for the panel
2909 * power sequencer any more. */
2910 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2911 if (is_cpu_edp(intel_dp))
453c5420 2912 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2913 else
453c5420 2914 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV
2915 }
2916
453c5420
JB
2917 pp_on |= port_sel;
2918
2919 I915_WRITE(pp_on_reg, pp_on);
2920 I915_WRITE(pp_off_reg, pp_off);
2921 I915_WRITE(pp_div_reg, pp_div);
67a54566 2922
67a54566 2923 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB
2924 I915_READ(pp_on_reg),
2925 I915_READ(pp_off_reg),
2926 I915_READ(pp_div_reg));
f684960e
CW
2927}
2928
a4fc5ed6 2929void
f0fec3f2
PZ
2930intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2931 struct intel_connector *intel_connector)
a4fc5ed6 2932{
f0fec3f2
PZ
2933 struct drm_connector *connector = &intel_connector->base;
2934 struct intel_dp *intel_dp = &intel_dig_port->dp;
2935 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2936 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2937 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2938 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2939 struct edp_power_seq power_seq = { 0 };
174edf1f 2940 enum port port = intel_dig_port->port;
5eb08b69 2941 const char *name = NULL;
b329530c 2942 int type;
a4fc5ed6 2943
0767935e
DV
2944 /* Preserve the current hw state. */
2945 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2946 intel_dp->attached_connector = intel_connector;
3d3dc149 2947
f0fec3f2 2948 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2949 if (intel_dpd_is_edp(dev))
ea5b213a 2950 intel_dp->is_pch_edp = true;
b329530c 2951
19c03924
GB
2952 /*
2953 * FIXME : We need to initialize built-in panels before external panels.
2954 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2955 */
f0fec3f2 2956 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB
2957 type = DRM_MODE_CONNECTOR_eDP;
2958 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2959 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ
2960 type = DRM_MODE_CONNECTOR_eDP;
2961 intel_encoder->type = INTEL_OUTPUT_EDP;
2962 } else {
00c09d70
PZ
2963 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2964 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2965 * rewrite it.
2966 */
b329530c 2967 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ
2968 }
2969
b329530c 2970 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP
2971 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2972
a4fc5ed6
KP
2973 connector->interlace_allowed = true;
2974 connector->doublescan_allowed = 0;
2975
f0fec3f2
PZ
2976 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2977 ironlake_panel_vdd_work);
a4fc5ed6 2978
df0e9248 2979 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP
2980 drm_sysfs_connector_add(connector);
2981
affa9354 2982 if (HAS_DDI(dev))
bcbc889b
PZ
2983 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2984 else
2985 intel_connector->get_hw_state = intel_connector_get_hw_state;
2986
9ed35ab1
PZ
2987 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2988 if (HAS_DDI(dev)) {
2989 switch (intel_dig_port->port) {
2990 case PORT_A:
2991 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2992 break;
2993 case PORT_B:
2994 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2995 break;
2996 case PORT_C:
2997 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2998 break;
2999 case PORT_D:
3000 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3001 break;
3002 default:
3003 BUG();
3004 }
3005 }
e8cb4558 3006
a4fc5ed6 3007 /* Set up the DDC bus. */
ab9d7c30
PZ
3008 switch (port) {
3009 case PORT_A:
1d843f9d 3010 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ
3011 name = "DPDDC-A";
3012 break;
3013 case PORT_B:
1d843f9d 3014 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ
3015 name = "DPDDC-B";
3016 break;
3017 case PORT_C:
1d843f9d 3018 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ
3019 name = "DPDDC-C";
3020 break;
3021 case PORT_D:
1d843f9d 3022 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ
3023 name = "DPDDC-D";
3024 break;
3025 default:
ad1c0b19 3026 BUG();
5eb08b69
ZW
3027 }
3028
67a54566 3029 if (is_edp(intel_dp))
f30d26e4 3030 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA
3031
3032 intel_dp_i2c_init(intel_dp, intel_connector, name);
3033
67a54566 3034 /* Cache DPCD and EDID for edp. */
c1f05264
DA
3035 if (is_edp(intel_dp)) {
3036 bool ret;
f8779fda 3037 struct drm_display_mode *scan;
c1f05264 3038 struct edid *edid;
5d613501
JB
3039
3040 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 3041 ret = intel_dp_get_dpcd(intel_dp);
bd943159 3042 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 3043
59f3e272 3044 if (ret) {
7183dc29
JB
3045 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3046 dev_priv->no_aux_handshake =
3047 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB
3048 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3049 } else {
3d3dc149 3050 /* if this fails, presume the device is a ghost */
48898b03 3051 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ
3052 intel_dp_encoder_destroy(&intel_encoder->base);
3053 intel_dp_destroy(connector);
3d3dc149 3054 return;
89667383 3055 }
89667383 3056
f30d26e4
JN
3057 /* We now know it's not a ghost, init power sequence regs. */
3058 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3059 &power_seq);
3060
d6f24d0f
JB
3061 ironlake_edp_panel_vdd_on(intel_dp);
3062 edid = drm_get_edid(connector, &intel_dp->adapter);
3063 if (edid) {
9cd300e0
JN
3064 if (drm_add_edid_modes(connector, edid)) {
3065 drm_mode_connector_update_edid_property(connector, edid);
3066 drm_edid_to_eld(connector, edid);
3067 } else {
3068 kfree(edid);
3069 edid = ERR_PTR(-EINVAL);
3070 }
3071 } else {
3072 edid = ERR_PTR(-ENOENT);
d6f24d0f 3073 }
9cd300e0 3074 intel_connector->edid = edid;
f8779fda
JN
3075
3076 /* prefer fixed mode from EDID if available */
3077 list_for_each_entry(scan, &connector->probed_modes, head) {
3078 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3079 fixed_mode = drm_mode_duplicate(dev, scan);
3080 break;
3081 }
d6f24d0f 3082 }
f8779fda
JN
3083
3084 /* fallback to VBT if available for eDP */
3085 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3086 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3087 if (fixed_mode)
3088 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3089 }
f8779fda 3090
d6f24d0f
JB
3091 ironlake_edp_panel_vdd_off(intel_dp, false);
3092 }
552fb0b7 3093
4d926461 3094 if (is_edp(intel_dp)) {
dd06f90e 3095 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 3096 intel_panel_setup_backlight(connector);
32f9d658
ZW
3097 }
3098
f684960e
CW
3099 intel_dp_add_properties(intel_dp, connector);
3100
a4fc5ed6
KP
3101 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3102 * 0xd. Failure to do so will result in spurious interrupts being
3103 * generated on the port when a cable is not attached.
3104 */
3105 if (IS_G4X(dev) && !IS_GM45(dev)) {
3106 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3107 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3108 }
3109}
f0fec3f2
PZ
3110
3111void
3112intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3113{
3114 struct intel_digital_port *intel_dig_port;
3115 struct intel_encoder *intel_encoder;
3116 struct drm_encoder *encoder;
3117 struct intel_connector *intel_connector;
3118
3119 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3120 if (!intel_dig_port)
3121 return;
3122
3123 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3124 if (!intel_connector) {
3125 kfree(intel_dig_port);
3126 return;
3127 }
3128
3129 intel_encoder = &intel_dig_port->base;
3130 encoder = &intel_encoder->base;
3131
3132 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3133 DRM_MODE_ENCODER_TMDS);
00c09d70 3134 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3135
5bfe2ac0 3136 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ
3137 intel_encoder->enable = intel_enable_dp;
3138 intel_encoder->pre_enable = intel_pre_enable_dp;
3139 intel_encoder->disable = intel_disable_dp;
3140 intel_encoder->post_disable = intel_post_disable_dp;
3141 intel_encoder->get_hw_state = intel_dp_get_hw_state;
89b667f8
JB
3142 if (IS_VALLEYVIEW(dev))
3143 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3144
174edf1f 3145 intel_dig_port->port = port;
f0fec3f2
PZ
3146 intel_dig_port->dp.output_reg = output_reg;
3147
00c09d70 3148 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ
3149 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3150 intel_encoder->cloneable = false;
3151 intel_encoder->hot_plug = intel_dp_hot_plug;
3152
3153 intel_dp_init_connector(intel_dig_port, intel_connector);
3154}
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