projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: remove PSR BDW single frame update.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 117static void vlv_steal_power_sequencer(struct drm_device *dev,
118 enum pipe pipe);
a4fc5ed6 119
0e32b39c 120int
ea5b213a 121intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 122{
7183dc29 123 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 124 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 125
126 switch (max_link_bw) {
127 case DP_LINK_BW_1_62:
128 case DP_LINK_BW_2_7:
129 break;
d4eead50 130 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 131 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
132 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 133 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
134 max_link_bw = DP_LINK_BW_5_4;
135 else
136 max_link_bw = DP_LINK_BW_2_7;
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
36008365 212 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
a4f1289e 230uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 231{
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240}
241
a4f1289e 242void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 331 bool pll_enabled;
961a0db0
VS		 332 uint32_t DP;
333
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe), port_name(intel_dig_port->port)))
337 return;
338
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe), port_name(intel_dig_port->port));
341
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
344 */
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
347 DP |= DP_PORT_WIDTH(1);
348 DP |= DP_LINK_TRAIN_PAT_1;
349
350 if (IS_CHERRYVIEW(dev))
351 DP |= DP_PIPE_SELECT_CHV(pipe);
352 else if (pipe == PIPE_B)
353 DP |= DP_PIPEB_SELECT;
354
d288f65f
VS		 355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
356
357 /*
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
360 */
361 if (!pll_enabled)
362 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
364
961a0db0
VS		 365 /*
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
370 */
371 I915_WRITE(intel_dp->output_reg, DP);
372 POSTING_READ(intel_dp->output_reg);
373
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
375 POSTING_READ(intel_dp->output_reg);
376
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
378 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 379
380 if (!pll_enabled)
381 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 382}
383
bf13e81b
JN		 384static enum pipe
385vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386{
387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 388 struct drm_device *dev = intel_dig_port->base.base.dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 390 struct intel_encoder *encoder;
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 392 enum pipe pipe;
bf13e81b 393
e39b999a 394 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 395
a8c3344e
VS		 396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp));
398
a4a5d2f8
VS		 399 if (intel_dp->pps_pipe != INVALID_PIPE)
400 return intel_dp->pps_pipe;
401
402 /*
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
405 */
406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 base.head) {
408 struct intel_dp *tmp;
409
410 if (encoder->type != INTEL_OUTPUT_EDP)
411 continue;
412
413 tmp = enc_to_intel_dp(&encoder->base);
414
415 if (tmp->pps_pipe != INVALID_PIPE)
416 pipes &= ~(1 << tmp->pps_pipe);
417 }
418
419 /*
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
422 */
423 if (WARN_ON(pipes == 0))
a8c3344e
VS		 424 pipe = PIPE_A;
425 else
426 pipe = ffs(pipes) - 1;
a4a5d2f8 427
a8c3344e
VS		 428 vlv_steal_power_sequencer(dev, pipe);
429 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 430
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp->pps_pipe),
433 port_name(intel_dig_port->port));
434
435 /* init power sequencer on this pipe and port */
36b5f425
VS		 436 intel_dp_init_panel_power_sequencer(dev, intel_dp);
437 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 438
961a0db0
VS		 439 /*
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
442 */
443 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 444
445 return intel_dp->pps_pipe;
446}
447
6491ab27
VS		 448typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
449 enum pipe pipe);
450
451static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
455}
456
457static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
461}
462
463static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return true;
467}
bf13e81b 468
a4a5d2f8 469static enum pipe
6491ab27
VS		 470vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 enum port port,
472 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 473{
474 enum pipe pipe;
bf13e81b 475
bf13e81b
JN		 476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
478 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 479
480 if (port_sel != PANEL_PORT_SELECT_VLV(port))
481 continue;
482
6491ab27
VS		 483 if (!pipe_check(dev_priv, pipe))
484 continue;
485
a4a5d2f8 486 return pipe;
bf13e81b
JN		 487 }
488
a4a5d2f8
VS		 489 return INVALID_PIPE;
490}
491
492static void
493vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 498 enum port port = intel_dig_port->port;
499
500 lockdep_assert_held(&dev_priv->pps_mutex);
501
502 /* try to find a pipe with this port selected */
6491ab27
VS		 503 /* first pick one where the panel is on */
504 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 vlv_pipe_has_pp_on);
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp->pps_pipe == INVALID_PIPE)
508 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
509 vlv_pipe_has_vdd_on);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp->pps_pipe == INVALID_PIPE)
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_any);
a4a5d2f8
VS		 514
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp->pps_pipe == INVALID_PIPE) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
518 port_name(port));
519 return;
bf13e81b
JN		 520 }
521
a4a5d2f8
VS		 522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port), pipe_name(intel_dp->pps_pipe));
524
36b5f425
VS		 525 intel_dp_init_panel_power_sequencer(dev, intel_dp);
526 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 527}
528
773538e8
VS		 529void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530{
531 struct drm_device *dev = dev_priv->dev;
532 struct intel_encoder *encoder;
533
534 if (WARN_ON(!IS_VALLEYVIEW(dev)))
535 return;
536
537 /*
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
545 */
546
547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
548 struct intel_dp *intel_dp;
549
550 if (encoder->type != INTEL_OUTPUT_EDP)
551 continue;
552
553 intel_dp = enc_to_intel_dp(&encoder->base);
554 intel_dp->pps_pipe = INVALID_PIPE;
555 }
bf13e81b
JN		 556}
557
558static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
562 if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_CONTROL;
564 else
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
566}
567
568static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569{
570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571
572 if (HAS_PCH_SPLIT(dev))
573 return PCH_PP_STATUS;
574 else
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
576}
577
01527b31
CT		 578/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580static int edp_notify_handler(struct notifier_block *this, unsigned long code,
581 void *unused)
582{
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
584 edp_notifier);
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 u32 pp_div;
588 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 589
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
591 return 0;
592
773538e8 593 pps_lock(intel_dp);
e39b999a 594
01527b31 595 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
597
01527b31
CT		 598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
602
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
607 }
608
773538e8 609 pps_unlock(intel_dp);
e39b999a 610
01527b31
CT		 611 return 0;
612}
613
4be73780 614static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 617 struct drm_i915_private *dev_priv = dev->dev_private;
618
e39b999a
VS		 619 lockdep_assert_held(&dev_priv->pps_mutex);
620
9a42356b
VS		 621 if (IS_VALLEYVIEW(dev) &&
622 intel_dp->pps_pipe == INVALID_PIPE)
623 return false;
624
bf13e81b 625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 626}
627
4be73780 628static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 629{
30add22d 630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 631 struct drm_i915_private *dev_priv = dev->dev_private;
632
e39b999a
VS		 633 lockdep_assert_held(&dev_priv->pps_mutex);
634
9a42356b
VS		 635 if (IS_VALLEYVIEW(dev) &&
636 intel_dp->pps_pipe == INVALID_PIPE)
637 return false;
638
773538e8 639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 640}
641
9b984dae
KP		 642static void
643intel_dp_check_edp(struct intel_dp *intel_dp)
644{
30add22d 645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 646 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 647
9b984dae
KP		 648 if (!is_edp(intel_dp))
649 return;
453c5420 650
4be73780 651 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 654 I915_READ(_pp_stat_reg(intel_dp)),
655 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 656 }
657}
658
9ee32fea
DV		 659static uint32_t
660intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
661{
662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
663 struct drm_device *dev = intel_dig_port->base.base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 665 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 666 uint32_t status;
667 bool done;
668
ef04f00d 669#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 670 if (has_aux_irq)
b18ac466 671 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 672 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 673 else
674 done = wait_for_atomic(C, 10) == 0;
675 if (!done)
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
677 has_aux_irq);
678#undef C
679
680 return status;
681}
682
ec5b01dd 683static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 684{
174edf1f
PZ		 685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 687
ec5b01dd
DL		 688 /*
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 691 */
ec5b01dd
DL		 692 return index ? 0 : intel_hrawclk(dev) / 2;
693}
694
695static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696{
697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
699
700 if (index)
701 return 0;
702
703 if (intel_dig_port->port == PORT_A) {
704 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 705 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 706 else
b84a1cf8 707 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 708 } else {
709 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
710 }
711}
712
713static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
714{
715 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
716 struct drm_device *dev = intel_dig_port->base.base.dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718
719 if (intel_dig_port->port == PORT_A) {
720 if (index)
721 return 0;
722 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 723 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
724 /* Workaround for non-ULT HSW */
bc86625a
CW		 725 switch (index) {
726 case 0: return 63;
727 case 1: return 72;
728 default: return 0;
729 }
ec5b01dd 730 } else {
bc86625a 731 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 732 }
b84a1cf8
RV		 733}
734
ec5b01dd
DL		 735static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
736{
737 return index ? 0 : 100;
738}
739
b6b5e383
DL		 740static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
741{
742 /*
743 * SKL doesn't need us to program the AUX clock divider (Hardware will
744 * derive the clock from CDCLK automatically). We still implement the
745 * get_aux_clock_divider vfunc to plug-in into the existing code.
746 */
747 return index ? 0 : 1;
748}
749
5ed12a19
DL		 750static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
751 bool has_aux_irq,
752 int send_bytes,
753 uint32_t aux_clock_divider)
754{
755 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
756 struct drm_device *dev = intel_dig_port->base.base.dev;
757 uint32_t precharge, timeout;
758
759 if (IS_GEN6(dev))
760 precharge = 3;
761 else
762 precharge = 5;
763
764 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
765 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
766 else
767 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
768
769 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 770 DP_AUX_CH_CTL_DONE |
5ed12a19 771 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 772 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 773 timeout |
788d4433 774 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 775 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
776 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 777 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 778}
779
b9ca5fad
DL		 780static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
781 bool has_aux_irq,
782 int send_bytes,
783 uint32_t unused)
784{
785 return DP_AUX_CH_CTL_SEND_BUSY |
786 DP_AUX_CH_CTL_DONE |
787 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788 DP_AUX_CH_CTL_TIME_OUT_ERROR |
789 DP_AUX_CH_CTL_TIME_OUT_1600us |
790 DP_AUX_CH_CTL_RECEIVE_ERROR |
791 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
792 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
793}
794
b84a1cf8
RV		 795static int
796intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 797 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 798 uint8_t *recv, int recv_size)
799{
800 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
801 struct drm_device *dev = intel_dig_port->base.base.dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
804 uint32_t ch_data = ch_ctl + 4;
bc86625a 805 uint32_t aux_clock_divider;
b84a1cf8
RV		 806 int i, ret, recv_bytes;
807 uint32_t status;
5ed12a19 808 int try, clock = 0;
4e6b788c 809 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 810 bool vdd;
811
773538e8 812 pps_lock(intel_dp);
e39b999a 813
72c3500a
VS		 814 /*
815 * We will be called with VDD already enabled for dpcd/edid/oui reads.
816 * In such cases we want to leave VDD enabled and it's up to upper layers
817 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
818 * ourselves.
819 */
1e0560e0 820 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 821
822 /* dp aux is extremely sensitive to irq latency, hence request the
823 * lowest possible wakeup latency and so prevent the cpu from going into
824 * deep sleep states.
825 */
826 pm_qos_update_request(&dev_priv->pm_qos, 0);
827
828 intel_dp_check_edp(intel_dp);
5eb08b69 829
c67a470b
PZ		 830 intel_aux_display_runtime_get(dev_priv);
831
11bee43e
JB		 832 /* Try to wait for any previous AUX channel activity */
833 for (try = 0; try < 3; try++) {
ef04f00d 834 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 835 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
836 break;
837 msleep(1);
838 }
839
840 if (try == 3) {
841 WARN(1, "dp_aux_ch not started status 0x%08x\n",
842 I915_READ(ch_ctl));
9ee32fea
DV		 843 ret = -EBUSY;
844 goto out;
4f7f7b7e
CW		 845 }
846
46a5ae9f
PZ		 847 /* Only 5 data registers! */
848 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
849 ret = -E2BIG;
850 goto out;
851 }
852
ec5b01dd 853 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 854 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
855 has_aux_irq,
856 send_bytes,
857 aux_clock_divider);
5ed12a19 858
bc86625a
CW		 859 /* Must try at least 3 times according to DP spec */
860 for (try = 0; try < 5; try++) {
861 /* Load the send data into the aux channel data registers */
862 for (i = 0; i < send_bytes; i += 4)
863 I915_WRITE(ch_data + i,
a4f1289e
RV		 864 intel_dp_pack_aux(send + i,
865 send_bytes - i));
bc86625a
CW		 866
867 /* Send the command and wait for it to complete */
5ed12a19 868 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 869
870 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
871
872 /* Clear done status and any errors */
873 I915_WRITE(ch_ctl,
874 status |
875 DP_AUX_CH_CTL_DONE |
876 DP_AUX_CH_CTL_TIME_OUT_ERROR |
877 DP_AUX_CH_CTL_RECEIVE_ERROR);
878
879 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
880 DP_AUX_CH_CTL_RECEIVE_ERROR))
881 continue;
882 if (status & DP_AUX_CH_CTL_DONE)
883 break;
884 }
4f7f7b7e 885 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 886 break;
887 }
888
a4fc5ed6 889 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 891 ret = -EBUSY;
892 goto out;
a4fc5ed6
KP		 893 }
894
895 /* Check for timeout or receive error.
896 * Timeouts occur when the sink is not connected
897 */
a5b3da54 898 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 899 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 900 ret = -EIO;
901 goto out;
a5b3da54 902 }
1ae8c0a5
KP		 903
904 /* Timeouts occur when the device isn't connected, so they're
905 * "normal" -- don't fill the kernel log with these */
a5b3da54 906 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 907 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 908 ret = -ETIMEDOUT;
909 goto out;
a4fc5ed6
KP		 910 }
911
912 /* Unload any bytes sent back from the other side */
913 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
914 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 915 if (recv_bytes > recv_size)
916 recv_bytes = recv_size;
0206e353 917
4f7f7b7e 918 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 919 intel_dp_unpack_aux(I915_READ(ch_data + i),
920 recv + i, recv_bytes - i);
a4fc5ed6 921
9ee32fea
DV		 922 ret = recv_bytes;
923out:
924 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 925 intel_aux_display_runtime_put(dev_priv);
9ee32fea 926
884f19e9
JN		 927 if (vdd)
928 edp_panel_vdd_off(intel_dp, false);
929
773538e8 930 pps_unlock(intel_dp);
e39b999a 931
9ee32fea 932 return ret;
a4fc5ed6
KP		 933}
934
a6c8aff0
JN		 935#define BARE_ADDRESS_SIZE 3
936#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 937static ssize_t
938intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 939{
9d1a1031
JN		 940 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
941 uint8_t txbuf[20], rxbuf[20];
942 size_t txsize, rxsize;
a4fc5ed6 943 int ret;
a4fc5ed6 944
9d1a1031
JN		 945 txbuf[0] = msg->request << 4;
946 txbuf[1] = msg->address >> 8;
947 txbuf[2] = msg->address & 0xff;
948 txbuf[3] = msg->size - 1;
46a5ae9f 949
9d1a1031
JN		 950 switch (msg->request & ~DP_AUX_I2C_MOT) {
951 case DP_AUX_NATIVE_WRITE:
952 case DP_AUX_I2C_WRITE:
a6c8aff0 953 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 954 rxsize = 1;
f51a44b9 955
9d1a1031
JN		 956 if (WARN_ON(txsize > 20))
957 return -E2BIG;
a4fc5ed6 958
9d1a1031 959 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 960
9d1a1031
JN		 961 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
962 if (ret > 0) {
963 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 964
9d1a1031
JN		 965 /* Return payload size. */
966 ret = msg->size;
967 }
968 break;
46a5ae9f 969
9d1a1031
JN		 970 case DP_AUX_NATIVE_READ:
971 case DP_AUX_I2C_READ:
a6c8aff0 972 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 973 rxsize = msg->size + 1;
a4fc5ed6 974
9d1a1031
JN		 975 if (WARN_ON(rxsize > 20))
976 return -E2BIG;
a4fc5ed6 977
9d1a1031
JN		 978 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
979 if (ret > 0) {
980 msg->reply = rxbuf[0] >> 4;
981 /*
982 * Assume happy day, and copy the data. The caller is
983 * expected to check msg->reply before touching it.
984 *
985 * Return payload size.
986 */
987 ret--;
988 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 989 }
9d1a1031
JN		 990 break;
991
992 default:
993 ret = -EINVAL;
994 break;
a4fc5ed6 995 }
f51a44b9 996
9d1a1031 997 return ret;
a4fc5ed6
KP		 998}
999
9d1a1031
JN		 1000static void
1001intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1002{
1003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1004 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1005 enum port port = intel_dig_port->port;
0b99836f 1006 const char *name = NULL;
ab2c0672
DA		 1007 int ret;
1008
33ad6626
JN		 1009 switch (port) {
1010 case PORT_A:
1011 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1012 name = "DPDDC-A";
ab2c0672 1013 break;
33ad6626
JN		 1014 case PORT_B:
1015 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1016 name = "DPDDC-B";
ab2c0672 1017 break;
33ad6626
JN		 1018 case PORT_C:
1019 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1020 name = "DPDDC-C";
ab2c0672 1021 break;
33ad6626
JN		 1022 case PORT_D:
1023 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1024 name = "DPDDC-D";
33ad6626
JN		 1025 break;
1026 default:
1027 BUG();
ab2c0672
DA		 1028 }
1029
1b1aad75
DL		 1030 /*
1031 * The AUX_CTL register is usually DP_CTL + 0x10.
1032 *
1033 * On Haswell and Broadwell though:
1034 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1035 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1036 *
1037 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1038 */
1039 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1040 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1041
0b99836f 1042 intel_dp->aux.name = name;
9d1a1031
JN		 1043 intel_dp->aux.dev = dev->dev;
1044 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1045
0b99836f
JN		 1046 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1047 connector->base.kdev->kobj.name);
8316f337 1048
4f71d0cb 1049 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1050 if (ret < 0) {
4f71d0cb 1051 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1052 name, ret);
1053 return;
ab2c0672 1054 }
8a5e6aeb 1055
0b99836f
JN		 1056 ret = sysfs_create_link(&connector->base.kdev->kobj,
1057 &intel_dp->aux.ddc.dev.kobj,
1058 intel_dp->aux.ddc.dev.kobj.name);
1059 if (ret < 0) {
1060 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1061 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1062 }
a4fc5ed6
KP		 1063}
1064
80f65de3
ID		 1065static void
1066intel_dp_connector_unregister(struct intel_connector *intel_connector)
1067{
1068 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1069
0e32b39c
DA		 1070 if (!intel_connector->mst_port)
1071 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1072 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1073 intel_connector_unregister(intel_connector);
1074}
1075
5416d871
DL		 1076static void
1077skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw)
1078{
1079 u32 ctrl1;
1080
1081 pipe_config->ddi_pll_sel = SKL_DPLL0;
1082 pipe_config->dpll_hw_state.cfgcr1 = 0;
1083 pipe_config->dpll_hw_state.cfgcr2 = 0;
1084
1085 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1086 switch (link_bw) {
1087 case DP_LINK_BW_1_62:
1088 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1089 SKL_DPLL0);
1090 break;
1091 case DP_LINK_BW_2_7:
1092 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1093 SKL_DPLL0);
1094 break;
1095 case DP_LINK_BW_5_4:
1096 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1097 SKL_DPLL0);
1098 break;
1099 }
1100 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1101}
1102
0e50338c
DV		 1103static void
1104hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1105{
1106 switch (link_bw) {
1107 case DP_LINK_BW_1_62:
1108 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1109 break;
1110 case DP_LINK_BW_2_7:
1111 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1112 break;
1113 case DP_LINK_BW_5_4:
1114 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1115 break;
1116 }
1117}
1118
c6bb3538
DV		 1119static void
1120intel_dp_set_clock(struct intel_encoder *encoder,
1121 struct intel_crtc_config *pipe_config, int link_bw)
1122{
1123 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1124 const struct dp_link_dpll *divisor = NULL;
1125 int i, count = 0;
c6bb3538
DV		 1126
1127 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1128 divisor = gen4_dpll;
1129 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1130 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1131 divisor = pch_dpll;
1132 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1133 } else if (IS_CHERRYVIEW(dev)) {
1134 divisor = chv_dpll;
1135 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1136 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1137 divisor = vlv_dpll;
1138 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1139 }
9dd4ffdf
CML		 1140
1141 if (divisor && count) {
1142 for (i = 0; i < count; i++) {
1143 if (link_bw == divisor[i].link_bw) {
1144 pipe_config->dpll = divisor[i].dpll;
1145 pipe_config->clock_set = true;
1146 break;
1147 }
1148 }
c6bb3538
DV		 1149 }
1150}
1151
00c09d70 1152bool
5bfe2ac0
DV		 1153intel_dp_compute_config(struct intel_encoder *encoder,
1154 struct intel_crtc_config *pipe_config)
a4fc5ed6 1155{
5bfe2ac0 1156 struct drm_device *dev = encoder->base.dev;
36008365 1157 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1158 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1159 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1160 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1161 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1162 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1163 int lane_count, clock;
56071a20 1164 int min_lane_count = 1;
eeb6324d 1165 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1166 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1167 int min_clock = 0;
06ea66b6 1168 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1169 int bpp, mode_rate;
06ea66b6 1170 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1171 int link_avail, link_clock;
a4fc5ed6 1172
bc7d38a4 1173 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1174 pipe_config->has_pch_encoder = true;
1175
03afc4a2 1176 pipe_config->has_dp_encoder = true;
f769cd24 1177 pipe_config->has_drrs = false;
9ed109a7 1178 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1179
dd06f90e
JN		 1180 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1181 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1182 adjusted_mode);
2dd24552
JB		 1183 if (!HAS_PCH_SPLIT(dev))
1184 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1185 intel_connector->panel.fitting_mode);
1186 else
b074cec8
JB		 1187 intel_pch_panel_fitting(intel_crtc, pipe_config,
1188 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1189 }
1190
cb1793ce 1191 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1192 return false;
1193
083f9560
DV		 1194 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1195 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1196 max_lane_count, bws[max_clock],
1197 adjusted_mode->crtc_clock);
083f9560 1198
36008365
DV		 1199 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1200 * bpc in between. */
3e7ca985 1201 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1202 if (is_edp(intel_dp)) {
1203 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1204 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1205 dev_priv->vbt.edp_bpp);
1206 bpp = dev_priv->vbt.edp_bpp;
1207 }
1208
344c5bbc
JN		 1209 /*
1210 * Use the maximum clock and number of lanes the eDP panel
1211 * advertizes being capable of. The panels are generally
1212 * designed to support only a single clock and lane
1213 * configuration, and typically these values correspond to the
1214 * native resolution of the panel.
1215 */
1216 min_lane_count = max_lane_count;
1217 min_clock = max_clock;
7984211e 1218 }
657445fe 1219
36008365 1220 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1221 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1222 bpp);
36008365 1223
c6930992
DA		 1224 for (clock = min_clock; clock <= max_clock; clock++) {
1225 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1226 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1227 link_avail = intel_dp_max_data_rate(link_clock,
1228 lane_count);
1229
1230 if (mode_rate <= link_avail) {
1231 goto found;
1232 }
1233 }
1234 }
1235 }
c4867936 1236
36008365 1237 return false;
3685a8f3 1238
36008365 1239found:
55bc60db
VS		 1240 if (intel_dp->color_range_auto) {
1241 /*
1242 * See:
1243 * CEA-861-E - 5.1 Default Encoding Parameters
1244 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1245 */
18316c8c 1246 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1247 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1248 else
1249 intel_dp->color_range = 0;
1250 }
1251
3685a8f3 1252 if (intel_dp->color_range)
50f3b016 1253 pipe_config->limited_color_range = true;
a4fc5ed6 1254
36008365
DV		 1255 intel_dp->link_bw = bws[clock];
1256 intel_dp->lane_count = lane_count;
657445fe 1257 pipe_config->pipe_bpp = bpp;
ff9a6750 1258 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1259
36008365
DV		 1260 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1261 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1262 pipe_config->port_clock, bpp);
36008365
DV		 1263 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1264 mode_rate, link_avail);
a4fc5ed6 1265
03afc4a2 1266 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1267 adjusted_mode->crtc_clock,
1268 pipe_config->port_clock,
03afc4a2 1269 &pipe_config->dp_m_n);
9d1a455b 1270
439d7ac0
PB		 1271 if (intel_connector->panel.downclock_mode != NULL &&
1272 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1273 pipe_config->has_drrs = true;
439d7ac0
PB		 1274 intel_link_compute_m_n(bpp, lane_count,
1275 intel_connector->panel.downclock_mode->clock,
1276 pipe_config->port_clock,
1277 &pipe_config->dp_m2_n2);
1278 }
1279
5416d871
DL		 1280 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1281 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1282 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1283 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1284 else
1285 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1286
03afc4a2 1287 return true;
a4fc5ed6
KP		 1288}
1289
7c62a164 1290static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1291{
7c62a164
DV		 1292 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1293 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1294 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 u32 dpa_ctl;
1297
ff9a6750 1298 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1299 dpa_ctl = I915_READ(DP_A);
1300 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1301
ff9a6750 1302 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1303 /* For a long time we've carried around a ILK-DevA w/a for the
1304 * 160MHz clock. If we're really unlucky, it's still required.
1305 */
1306 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1307 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1308 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1309 } else {
1310 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1311 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1312 }
1ce17038 1313
ea9b6006
DV		 1314 I915_WRITE(DP_A, dpa_ctl);
1315
1316 POSTING_READ(DP_A);
1317 udelay(500);
1318}
1319
8ac33ed3 1320static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1321{
b934223d 1322 struct drm_device *dev = encoder->base.dev;
417e822d 1323 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1324 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1325 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1326 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1327 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1328
417e822d 1329 /*
1a2eb460 1330 * There are four kinds of DP registers:
417e822d
KP		 1331 *
1332 * IBX PCH
1a2eb460
KP		 1333 * SNB CPU
1334 * IVB CPU
417e822d
KP		 1335 * CPT PCH
1336 *
1337 * IBX PCH and CPU are the same for almost everything,
1338 * except that the CPU DP PLL is configured in this
1339 * register
1340 *
1341 * CPT PCH is quite different, having many bits moved
1342 * to the TRANS_DP_CTL register instead. That
1343 * configuration happens (oddly) in ironlake_pch_enable
1344 */
9c9e7927 1345
417e822d
KP		 1346 /* Preserve the BIOS-computed detected bit. This is
1347 * supposed to be read-only.
1348 */
1349 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1350
417e822d 1351 /* Handle DP bits in common between all three register formats */
417e822d 1352 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1353 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1354
c1dec79a 1355 if (crtc->config.has_audio)
ea5b213a 1356 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1357
417e822d 1358 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1359
bc7d38a4 1360 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1361 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1362 intel_dp->DP |= DP_SYNC_HS_HIGH;
1363 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1364 intel_dp->DP |= DP_SYNC_VS_HIGH;
1365 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1366
6aba5b6c 1367 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1368 intel_dp->DP |= DP_ENHANCED_FRAMING;
1369
7c62a164 1370 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1371 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1372 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1373 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1374
1375 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1376 intel_dp->DP |= DP_SYNC_HS_HIGH;
1377 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1378 intel_dp->DP |= DP_SYNC_VS_HIGH;
1379 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1380
6aba5b6c 1381 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1382 intel_dp->DP |= DP_ENHANCED_FRAMING;
1383
44f37d1f
CML		 1384 if (!IS_CHERRYVIEW(dev)) {
1385 if (crtc->pipe == 1)
1386 intel_dp->DP |= DP_PIPEB_SELECT;
1387 } else {
1388 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1389 }
417e822d
KP		 1390 } else {
1391 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1392 }
a4fc5ed6
KP		 1393}
1394
ffd6749d
PZ		 1395#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1396#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1397
1a5ef5b7
PZ		 1398#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1399#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1400
ffd6749d
PZ		 1401#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1402#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1403
4be73780 1404static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1405 u32 mask,
1406 u32 value)
bd943159 1407{
30add22d 1408 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1409 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1410 u32 pp_stat_reg, pp_ctrl_reg;
1411
e39b999a
VS		 1412 lockdep_assert_held(&dev_priv->pps_mutex);
1413
bf13e81b
JN		 1414 pp_stat_reg = _pp_stat_reg(intel_dp);
1415 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1416
99ea7127 1417 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1418 mask, value,
1419 I915_READ(pp_stat_reg),
1420 I915_READ(pp_ctrl_reg));
32ce697c 1421
453c5420 1422 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1423 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1424 I915_READ(pp_stat_reg),
1425 I915_READ(pp_ctrl_reg));
32ce697c 1426 }
54c136d4
CW		 1427
1428 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1429}
32ce697c 1430
4be73780 1431static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1432{
1433 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1434 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1435}
1436
4be73780 1437static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1438{
1439 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1440 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1441}
1442
4be73780 1443static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1444{
1445 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1446
1447 /* When we disable the VDD override bit last we have to do the manual
1448 * wait. */
1449 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1450 intel_dp->panel_power_cycle_delay);
1451
4be73780 1452 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1453}
1454
4be73780 1455static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1456{
1457 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1458 intel_dp->backlight_on_delay);
1459}
1460
4be73780 1461static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1462{
1463 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1464 intel_dp->backlight_off_delay);
1465}
99ea7127 1466
832dd3c1
KP		 1467/* Read the current pp_control value, unlocking the register if it
1468 * is locked
1469 */
1470
453c5420 1471static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1472{
453c5420
JB		 1473 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 u32 control;
832dd3c1 1476
e39b999a
VS		 1477 lockdep_assert_held(&dev_priv->pps_mutex);
1478
bf13e81b 1479 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1480 control &= ~PANEL_UNLOCK_MASK;
1481 control |= PANEL_UNLOCK_REGS;
1482 return control;
bd943159
KP		 1483}
1484
951468f3
VS		 1485/*
1486 * Must be paired with edp_panel_vdd_off().
1487 * Must hold pps_mutex around the whole on/off sequence.
1488 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1489 */
1e0560e0 1490static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1491{
30add22d 1492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1494 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1495 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1496 enum intel_display_power_domain power_domain;
5d613501 1497 u32 pp;
453c5420 1498 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1499 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1500
e39b999a
VS		 1501 lockdep_assert_held(&dev_priv->pps_mutex);
1502
97af61f5 1503 if (!is_edp(intel_dp))
adddaaf4 1504 return false;
bd943159 1505
2c623c11 1506 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1507 intel_dp->want_panel_vdd = true;
99ea7127 1508
4be73780 1509 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1510 return need_to_disable;
b0665d57 1511
4e6e1a54
ID		 1512 power_domain = intel_display_port_power_domain(intel_encoder);
1513 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1514
3936fcf4
VS		 1515 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1516 port_name(intel_dig_port->port));
bd943159 1517
4be73780
DV		 1518 if (!edp_have_panel_power(intel_dp))
1519 wait_panel_power_cycle(intel_dp);
99ea7127 1520
453c5420 1521 pp = ironlake_get_pp_control(intel_dp);
5d613501 1522 pp |= EDP_FORCE_VDD;
ebf33b18 1523
bf13e81b
JN		 1524 pp_stat_reg = _pp_stat_reg(intel_dp);
1525 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1526
1527 I915_WRITE(pp_ctrl_reg, pp);
1528 POSTING_READ(pp_ctrl_reg);
1529 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1530 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1531 /*
1532 * If the panel wasn't on, delay before accessing aux channel
1533 */
4be73780 1534 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1535 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1536 port_name(intel_dig_port->port));
f01eca2e 1537 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1538 }
adddaaf4
JN		 1539
1540 return need_to_disable;
1541}
1542
951468f3
VS		 1543/*
1544 * Must be paired with intel_edp_panel_vdd_off() or
1545 * intel_edp_panel_off().
1546 * Nested calls to these functions are not allowed since
1547 * we drop the lock. Caller must use some higher level
1548 * locking to prevent nested calls from other threads.
1549 */
b80d6c78 1550void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1551{
c695b6b6 1552 bool vdd;
adddaaf4 1553
c695b6b6
VS		 1554 if (!is_edp(intel_dp))
1555 return;
1556
773538e8 1557 pps_lock(intel_dp);
c695b6b6 1558 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1559 pps_unlock(intel_dp);
c695b6b6 1560
3936fcf4
VS		 1561 WARN(!vdd, "eDP port %c VDD already requested on\n",
1562 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1563}
1564
4be73780 1565static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1566{
30add22d 1567 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1568 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1569 struct intel_digital_port *intel_dig_port =
1570 dp_to_dig_port(intel_dp);
1571 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1572 enum intel_display_power_domain power_domain;
5d613501 1573 u32 pp;
453c5420 1574 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1575
e39b999a 1576 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1577
15e899a0 1578 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1579
15e899a0 1580 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1581 return;
b0665d57 1582
3936fcf4
VS		 1583 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1584 port_name(intel_dig_port->port));
bd943159 1585
be2c9196
VS		 1586 pp = ironlake_get_pp_control(intel_dp);
1587 pp &= ~EDP_FORCE_VDD;
453c5420 1588
be2c9196
VS		 1589 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1590 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1591
be2c9196
VS		 1592 I915_WRITE(pp_ctrl_reg, pp);
1593 POSTING_READ(pp_ctrl_reg);
90791a5c 1594
be2c9196
VS		 1595 /* Make sure sequencer is idle before allowing subsequent activity */
1596 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1597 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1598
be2c9196
VS		 1599 if ((pp & POWER_TARGET_ON) == 0)
1600 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1601
be2c9196
VS		 1602 power_domain = intel_display_port_power_domain(intel_encoder);
1603 intel_display_power_put(dev_priv, power_domain);
bd943159 1604}
5d613501 1605
4be73780 1606static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1607{
1608 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1609 struct intel_dp, panel_vdd_work);
bd943159 1610
773538e8 1611 pps_lock(intel_dp);
15e899a0
VS		 1612 if (!intel_dp->want_panel_vdd)
1613 edp_panel_vdd_off_sync(intel_dp);
773538e8 1614 pps_unlock(intel_dp);
bd943159
KP		 1615}
1616
aba86890
ID		 1617static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1618{
1619 unsigned long delay;
1620
1621 /*
1622 * Queue the timer to fire a long time from now (relative to the power
1623 * down delay) to keep the panel power up across a sequence of
1624 * operations.
1625 */
1626 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1627 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1628}
1629
951468f3
VS		 1630/*
1631 * Must be paired with edp_panel_vdd_on().
1632 * Must hold pps_mutex around the whole on/off sequence.
1633 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1634 */
4be73780 1635static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1636{
e39b999a
VS		 1637 struct drm_i915_private *dev_priv =
1638 intel_dp_to_dev(intel_dp)->dev_private;
1639
1640 lockdep_assert_held(&dev_priv->pps_mutex);
1641
97af61f5
KP		 1642 if (!is_edp(intel_dp))
1643 return;
5d613501 1644
3936fcf4
VS		 1645 WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1646 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1647
bd943159
KP		 1648 intel_dp->want_panel_vdd = false;
1649
aba86890 1650 if (sync)
4be73780 1651 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1652 else
1653 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1654}
1655
9f0fb5be 1656static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1657{
30add22d 1658 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1659 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1660 u32 pp;
453c5420 1661 u32 pp_ctrl_reg;
9934c132 1662
9f0fb5be
VS		 1663 lockdep_assert_held(&dev_priv->pps_mutex);
1664
97af61f5 1665 if (!is_edp(intel_dp))
bd943159 1666 return;
99ea7127 1667
3936fcf4
VS		 1668 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1669 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1670
e7a89ace
VS		 1671 if (WARN(edp_have_panel_power(intel_dp),
1672 "eDP port %c panel power already on\n",
1673 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1674 return;
9934c132 1675
4be73780 1676 wait_panel_power_cycle(intel_dp);
37c6c9b0 1677
bf13e81b 1678 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1679 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1680 if (IS_GEN5(dev)) {
1681 /* ILK workaround: disable reset around power sequence */
1682 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1683 I915_WRITE(pp_ctrl_reg, pp);
1684 POSTING_READ(pp_ctrl_reg);
05ce1a49 1685 }
37c6c9b0 1686
1c0ae80a 1687 pp |= POWER_TARGET_ON;
99ea7127
KP		 1688 if (!IS_GEN5(dev))
1689 pp |= PANEL_POWER_RESET;
1690
453c5420
JB		 1691 I915_WRITE(pp_ctrl_reg, pp);
1692 POSTING_READ(pp_ctrl_reg);
9934c132 1693
4be73780 1694 wait_panel_on(intel_dp);
dce56b3c 1695 intel_dp->last_power_on = jiffies;
9934c132 1696
05ce1a49
KP		 1697 if (IS_GEN5(dev)) {
1698 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1699 I915_WRITE(pp_ctrl_reg, pp);
1700 POSTING_READ(pp_ctrl_reg);
05ce1a49 1701 }
9f0fb5be 1702}
e39b999a 1703
9f0fb5be
VS		 1704void intel_edp_panel_on(struct intel_dp *intel_dp)
1705{
1706 if (!is_edp(intel_dp))
1707 return;
1708
1709 pps_lock(intel_dp);
1710 edp_panel_on(intel_dp);
773538e8 1711 pps_unlock(intel_dp);
9934c132
JB		 1712}
1713
9f0fb5be
VS		 1714
1715static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1716{
4e6e1a54
ID		 1717 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1718 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1719 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1720 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1721 enum intel_display_power_domain power_domain;
99ea7127 1722 u32 pp;
453c5420 1723 u32 pp_ctrl_reg;
9934c132 1724
9f0fb5be
VS		 1725 lockdep_assert_held(&dev_priv->pps_mutex);
1726
97af61f5
KP		 1727 if (!is_edp(intel_dp))
1728 return;
37c6c9b0 1729
3936fcf4
VS		 1730 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1731 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1732
3936fcf4
VS		 1733 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1734 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1735
453c5420 1736 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1737 /* We need to switch off panel power _and_ force vdd, for otherwise some
1738 * panels get very unhappy and cease to work. */
b3064154
PJ		 1739 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1740 EDP_BLC_ENABLE);
453c5420 1741
bf13e81b 1742 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1743
849e39f5
PZ		 1744 intel_dp->want_panel_vdd = false;
1745
453c5420
JB		 1746 I915_WRITE(pp_ctrl_reg, pp);
1747 POSTING_READ(pp_ctrl_reg);
9934c132 1748
dce56b3c 1749 intel_dp->last_power_cycle = jiffies;
4be73780 1750 wait_panel_off(intel_dp);
849e39f5
PZ		 1751
1752 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1753 power_domain = intel_display_port_power_domain(intel_encoder);
1754 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1755}
e39b999a 1756
9f0fb5be
VS		 1757void intel_edp_panel_off(struct intel_dp *intel_dp)
1758{
1759 if (!is_edp(intel_dp))
1760 return;
e39b999a 1761
9f0fb5be
VS		 1762 pps_lock(intel_dp);
1763 edp_panel_off(intel_dp);
773538e8 1764 pps_unlock(intel_dp);
9934c132
JB		 1765}
1766
1250d107
JN		 1767/* Enable backlight in the panel power control. */
1768static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1769{
da63a9f2
PZ		 1770 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1771 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 u32 pp;
453c5420 1774 u32 pp_ctrl_reg;
32f9d658 1775
01cb9ea6
JB		 1776 /*
1777 * If we enable the backlight right away following a panel power
1778 * on, we may see slight flicker as the panel syncs with the eDP
1779 * link. So delay a bit to make sure the image is solid before
1780 * allowing it to appear.
1781 */
4be73780 1782 wait_backlight_on(intel_dp);
e39b999a 1783
773538e8 1784 pps_lock(intel_dp);
e39b999a 1785
453c5420 1786 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1787 pp |= EDP_BLC_ENABLE;
453c5420 1788
bf13e81b 1789 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1790
1791 I915_WRITE(pp_ctrl_reg, pp);
1792 POSTING_READ(pp_ctrl_reg);
e39b999a 1793
773538e8 1794 pps_unlock(intel_dp);
32f9d658
ZW		 1795}
1796
1250d107
JN		 1797/* Enable backlight PWM and backlight PP control. */
1798void intel_edp_backlight_on(struct intel_dp *intel_dp)
1799{
1800 if (!is_edp(intel_dp))
1801 return;
1802
1803 DRM_DEBUG_KMS("\n");
1804
1805 intel_panel_enable_backlight(intel_dp->attached_connector);
1806 _intel_edp_backlight_on(intel_dp);
1807}
1808
1809/* Disable backlight in the panel power control. */
1810static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1811{
30add22d 1812 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 u32 pp;
453c5420 1815 u32 pp_ctrl_reg;
32f9d658 1816
f01eca2e
KP		 1817 if (!is_edp(intel_dp))
1818 return;
1819
773538e8 1820 pps_lock(intel_dp);
e39b999a 1821
453c5420 1822 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1823 pp &= ~EDP_BLC_ENABLE;
453c5420 1824
bf13e81b 1825 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1826
1827 I915_WRITE(pp_ctrl_reg, pp);
1828 POSTING_READ(pp_ctrl_reg);
f7d2323c 1829
773538e8 1830 pps_unlock(intel_dp);
e39b999a
VS		 1831
1832 intel_dp->last_backlight_off = jiffies;
f7d2323c 1833 edp_wait_backlight_off(intel_dp);
1250d107 1834}
f7d2323c 1835
1250d107
JN		 1836/* Disable backlight PP control and backlight PWM. */
1837void intel_edp_backlight_off(struct intel_dp *intel_dp)
1838{
1839 if (!is_edp(intel_dp))
1840 return;
1841
1842 DRM_DEBUG_KMS("\n");
f7d2323c 1843
1250d107 1844 _intel_edp_backlight_off(intel_dp);
f7d2323c 1845 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1846}
a4fc5ed6 1847
73580fb7
JN		 1848/*
1849 * Hook for controlling the panel power control backlight through the bl_power
1850 * sysfs attribute. Take care to handle multiple calls.
1851 */
1852static void intel_edp_backlight_power(struct intel_connector *connector,
1853 bool enable)
1854{
1855 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1856 bool is_enabled;
1857
773538e8 1858 pps_lock(intel_dp);
e39b999a 1859 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1860 pps_unlock(intel_dp);
73580fb7
JN		 1861
1862 if (is_enabled == enable)
1863 return;
1864
23ba9373
JN		 1865 DRM_DEBUG_KMS("panel power control backlight %s\n",
1866 enable ? "enable" : "disable");
73580fb7
JN		 1867
1868 if (enable)
1869 _intel_edp_backlight_on(intel_dp);
1870 else
1871 _intel_edp_backlight_off(intel_dp);
1872}
1873
2bd2ad64 1874static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1875{
da63a9f2
PZ		 1876 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1877 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1878 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 u32 dpa_ctl;
1881
2bd2ad64
DV		 1882 assert_pipe_disabled(dev_priv,
1883 to_intel_crtc(crtc)->pipe);
1884
d240f20f
JB		 1885 DRM_DEBUG_KMS("\n");
1886 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1887 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1888 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1889
1890 /* We don't adjust intel_dp->DP while tearing down the link, to
1891 * facilitate link retraining (e.g. after hotplug). Hence clear all
1892 * enable bits here to ensure that we don't enable too much. */
1893 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1894 intel_dp->DP |= DP_PLL_ENABLE;
1895 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1896 POSTING_READ(DP_A);
1897 udelay(200);
d240f20f
JB		 1898}
1899
2bd2ad64 1900static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1901{
da63a9f2
PZ		 1902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1903 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1904 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 u32 dpa_ctl;
1907
2bd2ad64
DV		 1908 assert_pipe_disabled(dev_priv,
1909 to_intel_crtc(crtc)->pipe);
1910
d240f20f 1911 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1912 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1913 "dp pll off, should be on\n");
1914 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1915
1916 /* We can't rely on the value tracked for the DP register in
1917 * intel_dp->DP because link_down must not change that (otherwise link
1918 * re-training will fail. */
298b0b39 1919 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1920 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1921 POSTING_READ(DP_A);
d240f20f
JB		 1922 udelay(200);
1923}
1924
c7ad3810 1925/* If the sink supports it, try to set the power state appropriately */
c19b0669 1926void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1927{
1928 int ret, i;
1929
1930 /* Should have a valid DPCD by this point */
1931 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1932 return;
1933
1934 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1935 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1936 DP_SET_POWER_D3);
c7ad3810
JB		 1937 } else {
1938 /*
1939 * When turning on, we need to retry for 1ms to give the sink
1940 * time to wake up.
1941 */
1942 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1943 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1944 DP_SET_POWER_D0);
c7ad3810
JB		 1945 if (ret == 1)
1946 break;
1947 msleep(1);
1948 }
1949 }
f9cac721
JN		 1950
1951 if (ret != 1)
1952 DRM_DEBUG_KMS("failed to %s sink power state\n",
1953 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1954}
1955
19d8fe15
DV		 1956static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1957 enum pipe *pipe)
d240f20f 1958{
19d8fe15 1959 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1960 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1961 struct drm_device *dev = encoder->base.dev;
1962 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1963 enum intel_display_power_domain power_domain;
1964 u32 tmp;
1965
1966 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1967 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1968 return false;
1969
1970 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1971
1972 if (!(tmp & DP_PORT_EN))
1973 return false;
1974
bc7d38a4 1975 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1976 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1977 } else if (IS_CHERRYVIEW(dev)) {
1978 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1979 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1980 *pipe = PORT_TO_PIPE(tmp);
1981 } else {
1982 u32 trans_sel;
1983 u32 trans_dp;
1984 int i;
1985
1986 switch (intel_dp->output_reg) {
1987 case PCH_DP_B:
1988 trans_sel = TRANS_DP_PORT_SEL_B;
1989 break;
1990 case PCH_DP_C:
1991 trans_sel = TRANS_DP_PORT_SEL_C;
1992 break;
1993 case PCH_DP_D:
1994 trans_sel = TRANS_DP_PORT_SEL_D;
1995 break;
1996 default:
1997 return true;
1998 }
1999
055e393f 2000 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2001 trans_dp = I915_READ(TRANS_DP_CTL(i));
2002 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2003 *pipe = i;
2004 return true;
2005 }
2006 }
19d8fe15 2007
4a0833ec
DV		 2008 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2009 intel_dp->output_reg);
2010 }
d240f20f 2011
19d8fe15
DV		 2012 return true;
2013}
d240f20f 2014
045ac3b5
JB		 2015static void intel_dp_get_config(struct intel_encoder *encoder,
2016 struct intel_crtc_config *pipe_config)
2017{
2018 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2019 u32 tmp, flags = 0;
63000ef6
XZ		 2020 struct drm_device *dev = encoder->base.dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 enum port port = dp_to_dig_port(intel_dp)->port;
2023 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2024 int dotclock;
045ac3b5 2025
9ed109a7
DV		 2026 tmp = I915_READ(intel_dp->output_reg);
2027 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2028 pipe_config->has_audio = true;
2029
63000ef6 2030 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2031 if (tmp & DP_SYNC_HS_HIGH)
2032 flags |= DRM_MODE_FLAG_PHSYNC;
2033 else
2034 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2035
63000ef6
XZ		 2036 if (tmp & DP_SYNC_VS_HIGH)
2037 flags |= DRM_MODE_FLAG_PVSYNC;
2038 else
2039 flags |= DRM_MODE_FLAG_NVSYNC;
2040 } else {
2041 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2042 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2043 flags |= DRM_MODE_FLAG_PHSYNC;
2044 else
2045 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2046
63000ef6
XZ		 2047 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2048 flags |= DRM_MODE_FLAG_PVSYNC;
2049 else
2050 flags |= DRM_MODE_FLAG_NVSYNC;
2051 }
045ac3b5
JB		 2052
2053 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 2054
8c875fca
VS		 2055 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2056 tmp & DP_COLOR_RANGE_16_235)
2057 pipe_config->limited_color_range = true;
2058
eb14cb74
VS		 2059 pipe_config->has_dp_encoder = true;
2060
2061 intel_dp_get_m_n(crtc, pipe_config);
2062
18442d08 2063 if (port == PORT_A) {
f1f644dc
JB		 2064 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2065 pipe_config->port_clock = 162000;
2066 else
2067 pipe_config->port_clock = 270000;
2068 }
18442d08
VS		 2069
2070 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2071 &pipe_config->dp_m_n);
2072
2073 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2074 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2075
241bfc38 2076 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2077
c6cd2ee2
JN		 2078 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2079 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2080 /*
2081 * This is a big fat ugly hack.
2082 *
2083 * Some machines in UEFI boot mode provide us a VBT that has 18
2084 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2085 * unknown we fail to light up. Yet the same BIOS boots up with
2086 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2087 * max, not what it tells us to use.
2088 *
2089 * Note: This will still be broken if the eDP panel is not lit
2090 * up by the BIOS, and thus we can't get the mode at module
2091 * load.
2092 */
2093 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2094 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2095 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2096 }
045ac3b5
JB		 2097}
2098
e8cb4558 2099static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2100{
e8cb4558 2101 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2102 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2103 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2104
2105 if (crtc->config.has_audio)
2106 intel_audio_codec_disable(encoder);
6cb49835
DV		 2107
2108 /* Make sure the panel is off before trying to change the mode. But also
2109 * ensure that we have vdd while we switch off the panel. */
24f3e092 2110 intel_edp_panel_vdd_on(intel_dp);
4be73780 2111 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2112 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2113 intel_edp_panel_off(intel_dp);
3739850b 2114
08aff3fe
VS		 2115 /* disable the port before the pipe on g4x */
2116 if (INTEL_INFO(dev)->gen < 5)
3739850b 2117 intel_dp_link_down(intel_dp);
d240f20f
JB		 2118}
2119
08aff3fe 2120static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2121{
2bd2ad64 2122 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2123 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2124
49277c31 2125 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2126 if (port == PORT_A)
2127 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2128}
2129
2130static void vlv_post_disable_dp(struct intel_encoder *encoder)
2131{
2132 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2133
2134 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2135}
2136
580d3811
VS		 2137static void chv_post_disable_dp(struct intel_encoder *encoder)
2138{
2139 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2140 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2141 struct drm_device *dev = encoder->base.dev;
2142 struct drm_i915_private *dev_priv = dev->dev_private;
2143 struct intel_crtc *intel_crtc =
2144 to_intel_crtc(encoder->base.crtc);
2145 enum dpio_channel ch = vlv_dport_to_channel(dport);
2146 enum pipe pipe = intel_crtc->pipe;
2147 u32 val;
2148
2149 intel_dp_link_down(intel_dp);
2150
2151 mutex_lock(&dev_priv->dpio_lock);
2152
2153 /* Propagate soft reset to data lane reset */
97fd4d5c 2154 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2155 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2156 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2157
97fd4d5c
VS		 2158 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2159 val |= CHV_PCS_REQ_SOFTRESET_EN;
2160 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2161
2162 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2163 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2164 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2165
2166 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2167 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2168 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2169
2170 mutex_unlock(&dev_priv->dpio_lock);
2171}
2172
7b13b58a
VS		 2173static void
2174_intel_dp_set_link_train(struct intel_dp *intel_dp,
2175 uint32_t *DP,
2176 uint8_t dp_train_pat)
2177{
2178 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2179 struct drm_device *dev = intel_dig_port->base.base.dev;
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 enum port port = intel_dig_port->port;
2182
2183 if (HAS_DDI(dev)) {
2184 uint32_t temp = I915_READ(DP_TP_CTL(port));
2185
2186 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2187 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2188 else
2189 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2190
2191 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2192 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2193 case DP_TRAINING_PATTERN_DISABLE:
2194 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2195
2196 break;
2197 case DP_TRAINING_PATTERN_1:
2198 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2199 break;
2200 case DP_TRAINING_PATTERN_2:
2201 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2202 break;
2203 case DP_TRAINING_PATTERN_3:
2204 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2205 break;
2206 }
2207 I915_WRITE(DP_TP_CTL(port), temp);
2208
2209 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2210 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2211
2212 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2213 case DP_TRAINING_PATTERN_DISABLE:
2214 *DP |= DP_LINK_TRAIN_OFF_CPT;
2215 break;
2216 case DP_TRAINING_PATTERN_1:
2217 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2218 break;
2219 case DP_TRAINING_PATTERN_2:
2220 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2221 break;
2222 case DP_TRAINING_PATTERN_3:
2223 DRM_ERROR("DP training pattern 3 not supported\n");
2224 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2225 break;
2226 }
2227
2228 } else {
2229 if (IS_CHERRYVIEW(dev))
2230 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2231 else
2232 *DP &= ~DP_LINK_TRAIN_MASK;
2233
2234 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2235 case DP_TRAINING_PATTERN_DISABLE:
2236 *DP |= DP_LINK_TRAIN_OFF;
2237 break;
2238 case DP_TRAINING_PATTERN_1:
2239 *DP |= DP_LINK_TRAIN_PAT_1;
2240 break;
2241 case DP_TRAINING_PATTERN_2:
2242 *DP |= DP_LINK_TRAIN_PAT_2;
2243 break;
2244 case DP_TRAINING_PATTERN_3:
2245 if (IS_CHERRYVIEW(dev)) {
2246 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2247 } else {
2248 DRM_ERROR("DP training pattern 3 not supported\n");
2249 *DP |= DP_LINK_TRAIN_PAT_2;
2250 }
2251 break;
2252 }
2253 }
2254}
2255
2256static void intel_dp_enable_port(struct intel_dp *intel_dp)
2257{
2258 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260
7b13b58a
VS		 2261 /* enable with pattern 1 (as per spec) */
2262 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2263 DP_TRAINING_PATTERN_1);
2264
2265 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2266 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2267
2268 /*
2269 * Magic for VLV/CHV. We _must_ first set up the register
2270 * without actually enabling the port, and then do another
2271 * write to enable the port. Otherwise link training will
2272 * fail when the power sequencer is freshly used for this port.
2273 */
2274 intel_dp->DP |= DP_PORT_EN;
2275
2276 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2277 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2278}
2279
e8cb4558 2280static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2281{
e8cb4558
DV		 2282 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2283 struct drm_device *dev = encoder->base.dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2285 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2286 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2287
0c33d8d7
DV		 2288 if (WARN_ON(dp_reg & DP_PORT_EN))
2289 return;
5d613501 2290
093e3f13
VS		 2291 pps_lock(intel_dp);
2292
2293 if (IS_VALLEYVIEW(dev))
2294 vlv_init_panel_power_sequencer(intel_dp);
2295
7b13b58a 2296 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2297
2298 edp_panel_vdd_on(intel_dp);
2299 edp_panel_on(intel_dp);
2300 edp_panel_vdd_off(intel_dp, true);
2301
2302 pps_unlock(intel_dp);
2303
61234fa5
VS		 2304 if (IS_VALLEYVIEW(dev))
2305 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2306
f01eca2e 2307 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2308 intel_dp_start_link_train(intel_dp);
33a34e4e 2309 intel_dp_complete_link_train(intel_dp);
3ab9c637 2310 intel_dp_stop_link_train(intel_dp);
c1dec79a
JN		 2311
2312 if (crtc->config.has_audio) {
2313 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2314 pipe_name(crtc->pipe));
2315 intel_audio_codec_enable(encoder);
2316 }
ab1f90f9 2317}
89b667f8 2318
ecff4f3b
JN		 2319static void g4x_enable_dp(struct intel_encoder *encoder)
2320{
828f5c6e
JN		 2321 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2322
ecff4f3b 2323 intel_enable_dp(encoder);
4be73780 2324 intel_edp_backlight_on(intel_dp);
ab1f90f9 2325}
89b667f8 2326
ab1f90f9
JN		 2327static void vlv_enable_dp(struct intel_encoder *encoder)
2328{
828f5c6e
JN		 2329 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2330
4be73780 2331 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2332}
2333
ecff4f3b 2334static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2335{
2336 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2337 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2338
8ac33ed3
DV		 2339 intel_dp_prepare(encoder);
2340
d41f1efb
DV		 2341 /* Only ilk+ has port A */
2342 if (dport->port == PORT_A) {
2343 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2344 ironlake_edp_pll_on(intel_dp);
d41f1efb 2345 }
ab1f90f9
JN		 2346}
2347
83b84597
VS		 2348static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2349{
2350 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2351 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2352 enum pipe pipe = intel_dp->pps_pipe;
2353 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2354
2355 edp_panel_vdd_off_sync(intel_dp);
2356
2357 /*
2358 * VLV seems to get confused when multiple power seqeuencers
2359 * have the same port selected (even if only one has power/vdd
2360 * enabled). The failure manifests as vlv_wait_port_ready() failing
2361 * CHV on the other hand doesn't seem to mind having the same port
2362 * selected in multiple power seqeuencers, but let's clear the
2363 * port select always when logically disconnecting a power sequencer
2364 * from a port.
2365 */
2366 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2367 pipe_name(pipe), port_name(intel_dig_port->port));
2368 I915_WRITE(pp_on_reg, 0);
2369 POSTING_READ(pp_on_reg);
2370
2371 intel_dp->pps_pipe = INVALID_PIPE;
2372}
2373
a4a5d2f8
VS		 2374static void vlv_steal_power_sequencer(struct drm_device *dev,
2375 enum pipe pipe)
2376{
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_encoder *encoder;
2379
2380 lockdep_assert_held(&dev_priv->pps_mutex);
2381
ac3c12e4
VS		 2382 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2383 return;
2384
a4a5d2f8
VS		 2385 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2386 base.head) {
2387 struct intel_dp *intel_dp;
773538e8 2388 enum port port;
a4a5d2f8
VS		 2389
2390 if (encoder->type != INTEL_OUTPUT_EDP)
2391 continue;
2392
2393 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2394 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2395
2396 if (intel_dp->pps_pipe != pipe)
2397 continue;
2398
2399 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2400 pipe_name(pipe), port_name(port));
a4a5d2f8 2401
034e43c6
VS		 2402 WARN(encoder->connectors_active,
2403 "stealing pipe %c power sequencer from active eDP port %c\n",
2404 pipe_name(pipe), port_name(port));
a4a5d2f8 2405
a4a5d2f8 2406 /* make sure vdd is off before we steal it */
83b84597 2407 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2408 }
2409}
2410
2411static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2412{
2413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2414 struct intel_encoder *encoder = &intel_dig_port->base;
2415 struct drm_device *dev = encoder->base.dev;
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2418
2419 lockdep_assert_held(&dev_priv->pps_mutex);
2420
093e3f13
VS		 2421 if (!is_edp(intel_dp))
2422 return;
2423
a4a5d2f8
VS		 2424 if (intel_dp->pps_pipe == crtc->pipe)
2425 return;
2426
2427 /*
2428 * If another power sequencer was being used on this
2429 * port previously make sure to turn off vdd there while
2430 * we still have control of it.
2431 */
2432 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2433 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2434
2435 /*
2436 * We may be stealing the power
2437 * sequencer from another port.
2438 */
2439 vlv_steal_power_sequencer(dev, crtc->pipe);
2440
2441 /* now it's all ours */
2442 intel_dp->pps_pipe = crtc->pipe;
2443
2444 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2445 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2446
2447 /* init power sequencer on this pipe and port */
36b5f425
VS		 2448 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2449 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2450}
2451
ab1f90f9 2452static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2453{
2bd2ad64 2454 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2455 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2456 struct drm_device *dev = encoder->base.dev;
89b667f8 2457 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2458 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2459 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2460 int pipe = intel_crtc->pipe;
2461 u32 val;
a4fc5ed6 2462
ab1f90f9 2463 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2464
ab3c759a 2465 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2466 val = 0;
2467 if (pipe)
2468 val |= (1<<21);
2469 else
2470 val &= ~(1<<21);
2471 val |= 0x001000c4;
ab3c759a
CML		 2472 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2473 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2474 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2475
ab1f90f9
JN		 2476 mutex_unlock(&dev_priv->dpio_lock);
2477
2478 intel_enable_dp(encoder);
89b667f8
JB		 2479}
2480
ecff4f3b 2481static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2482{
2483 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2484 struct drm_device *dev = encoder->base.dev;
2485 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2486 struct intel_crtc *intel_crtc =
2487 to_intel_crtc(encoder->base.crtc);
e4607fcf 2488 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2489 int pipe = intel_crtc->pipe;
89b667f8 2490
8ac33ed3
DV		 2491 intel_dp_prepare(encoder);
2492
89b667f8 2493 /* Program Tx lane resets to default */
0980a60f 2494 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2495 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2496 DPIO_PCS_TX_LANE2_RESET |
2497 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2498 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2499 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2500 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2501 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2502 DPIO_PCS_CLK_SOFT_RESET);
2503
2504 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2505 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2506 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2507 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2508 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2509}
2510
e4a1d846
CML		 2511static void chv_pre_enable_dp(struct intel_encoder *encoder)
2512{
2513 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2514 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2515 struct drm_device *dev = encoder->base.dev;
2516 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2517 struct intel_crtc *intel_crtc =
2518 to_intel_crtc(encoder->base.crtc);
2519 enum dpio_channel ch = vlv_dport_to_channel(dport);
2520 int pipe = intel_crtc->pipe;
2521 int data, i;
949c1d43 2522 u32 val;
e4a1d846 2523
e4a1d846 2524 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2525
570e2a74
VS		 2526 /* allow hardware to manage TX FIFO reset source */
2527 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2528 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2529 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2530
2531 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2532 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2533 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2534
949c1d43 2535 /* Deassert soft data lane reset*/
97fd4d5c 2536 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2537 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2538 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2539
2540 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2541 val |= CHV_PCS_REQ_SOFTRESET_EN;
2542 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2543
2544 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2545 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2546 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2547
97fd4d5c 2548 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2549 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2550 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2551
2552 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2553 for (i = 0; i < 4; i++) {
2554 /* Set the latency optimal bit */
2555 data = (i == 1) ? 0x0 : 0x6;
2556 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2557 data << DPIO_FRC_LATENCY_SHFIT);
2558
2559 /* Set the upar bit */
2560 data = (i == 1) ? 0x0 : 0x1;
2561 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2562 data << DPIO_UPAR_SHIFT);
2563 }
2564
2565 /* Data lane stagger programming */
2566 /* FIXME: Fix up value only after power analysis */
2567
2568 mutex_unlock(&dev_priv->dpio_lock);
2569
e4a1d846 2570 intel_enable_dp(encoder);
e4a1d846
CML		 2571}
2572
9197c88b
VS		 2573static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2574{
2575 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2576 struct drm_device *dev = encoder->base.dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct intel_crtc *intel_crtc =
2579 to_intel_crtc(encoder->base.crtc);
2580 enum dpio_channel ch = vlv_dport_to_channel(dport);
2581 enum pipe pipe = intel_crtc->pipe;
2582 u32 val;
2583
625695f8
VS		 2584 intel_dp_prepare(encoder);
2585
9197c88b
VS		 2586 mutex_lock(&dev_priv->dpio_lock);
2587
b9e5ac3c
VS		 2588 /* program left/right clock distribution */
2589 if (pipe != PIPE_B) {
2590 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2591 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2592 if (ch == DPIO_CH0)
2593 val |= CHV_BUFLEFTENA1_FORCE;
2594 if (ch == DPIO_CH1)
2595 val |= CHV_BUFRIGHTENA1_FORCE;
2596 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2597 } else {
2598 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2599 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2600 if (ch == DPIO_CH0)
2601 val |= CHV_BUFLEFTENA2_FORCE;
2602 if (ch == DPIO_CH1)
2603 val |= CHV_BUFRIGHTENA2_FORCE;
2604 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2605 }
2606
9197c88b
VS		 2607 /* program clock channel usage */
2608 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2609 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2610 if (pipe != PIPE_B)
2611 val &= ~CHV_PCS_USEDCLKCHANNEL;
2612 else
2613 val |= CHV_PCS_USEDCLKCHANNEL;
2614 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2615
2616 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2617 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2618 if (pipe != PIPE_B)
2619 val &= ~CHV_PCS_USEDCLKCHANNEL;
2620 else
2621 val |= CHV_PCS_USEDCLKCHANNEL;
2622 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2623
2624 /*
2625 * This a a bit weird since generally CL
2626 * matches the pipe, but here we need to
2627 * pick the CL based on the port.
2628 */
2629 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2630 if (pipe != PIPE_B)
2631 val &= ~CHV_CMN_USEDCLKCHANNEL;
2632 else
2633 val |= CHV_CMN_USEDCLKCHANNEL;
2634 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2635
2636 mutex_unlock(&dev_priv->dpio_lock);
2637}
2638
a4fc5ed6 2639/*
df0c237d
JB		 2640 * Native read with retry for link status and receiver capability reads for
2641 * cases where the sink may still be asleep.
9d1a1031
JN		 2642 *
2643 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2644 * supposed to retry 3 times per the spec.
a4fc5ed6 2645 */
9d1a1031
JN		 2646static ssize_t
2647intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2648 void *buffer, size_t size)
a4fc5ed6 2649{
9d1a1031
JN		 2650 ssize_t ret;
2651 int i;
61da5fab 2652
f6a19066
VS		 2653 /*
2654 * Sometime we just get the same incorrect byte repeated
2655 * over the entire buffer. Doing just one throw away read
2656 * initially seems to "solve" it.
2657 */
2658 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2659
61da5fab 2660 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2661 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2662 if (ret == size)
2663 return ret;
61da5fab
JB		 2664 msleep(1);
2665 }
a4fc5ed6 2666
9d1a1031 2667 return ret;
a4fc5ed6
KP		 2668}
2669
2670/*
2671 * Fetch AUX CH registers 0x202 - 0x207 which contain
2672 * link status information
2673 */
2674static bool
93f62dad 2675intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2676{
9d1a1031
JN		 2677 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2678 DP_LANE0_1_STATUS,
2679 link_status,
2680 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2681}
2682
1100244e 2683/* These are source-specific values. */
a4fc5ed6 2684static uint8_t
1a2eb460 2685intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2686{
30add22d 2687 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2688 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2689
5a9d1f1a
DL		 2690 if (INTEL_INFO(dev)->gen >= 9)
2691 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2692 else if (IS_VALLEYVIEW(dev))
bd60018a 2693 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2694 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2695 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2696 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2697 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2698 else
bd60018a 2699 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2700}
2701
2702static uint8_t
2703intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2704{
30add22d 2705 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2706 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2707
5a9d1f1a
DL		 2708 if (INTEL_INFO(dev)->gen >= 9) {
2709 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2710 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2711 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2712 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2713 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2714 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2715 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2716 default:
2717 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2718 }
2719 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2720 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2721 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2722 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2723 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2724 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2725 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2726 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2727 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2728 default:
bd60018a 2729 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2730 }
e2fa6fba
P		 2731 } else if (IS_VALLEYVIEW(dev)) {
2732 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2733 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2734 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2735 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2736 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2737 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2738 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2739 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2740 default:
bd60018a 2741 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2742 }
bc7d38a4 2743 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2744 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2745 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2746 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2747 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2748 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2749 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2750 default:
bd60018a 2751 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2752 }
2753 } else {
2754 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2755 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2756 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2757 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2758 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2759 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2760 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2761 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2762 default:
bd60018a 2763 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2764 }
a4fc5ed6
KP		 2765 }
2766}
2767
e2fa6fba
P		 2768static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2769{
2770 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2773 struct intel_crtc *intel_crtc =
2774 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2775 unsigned long demph_reg_value, preemph_reg_value,
2776 uniqtranscale_reg_value;
2777 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2778 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2779 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2780
2781 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2782 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2783 preemph_reg_value = 0x0004000;
2784 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2785 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2786 demph_reg_value = 0x2B405555;
2787 uniqtranscale_reg_value = 0x552AB83A;
2788 break;
bd60018a 2789 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2790 demph_reg_value = 0x2B404040;
2791 uniqtranscale_reg_value = 0x5548B83A;
2792 break;
bd60018a 2793 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2794 demph_reg_value = 0x2B245555;
2795 uniqtranscale_reg_value = 0x5560B83A;
2796 break;
bd60018a 2797 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2798 demph_reg_value = 0x2B405555;
2799 uniqtranscale_reg_value = 0x5598DA3A;
2800 break;
2801 default:
2802 return 0;
2803 }
2804 break;
bd60018a 2805 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2806 preemph_reg_value = 0x0002000;
2807 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2808 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2809 demph_reg_value = 0x2B404040;
2810 uniqtranscale_reg_value = 0x5552B83A;
2811 break;
bd60018a 2812 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2813 demph_reg_value = 0x2B404848;
2814 uniqtranscale_reg_value = 0x5580B83A;
2815 break;
bd60018a 2816 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2817 demph_reg_value = 0x2B404040;
2818 uniqtranscale_reg_value = 0x55ADDA3A;
2819 break;
2820 default:
2821 return 0;
2822 }
2823 break;
bd60018a 2824 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2825 preemph_reg_value = 0x0000000;
2826 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2827 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2828 demph_reg_value = 0x2B305555;
2829 uniqtranscale_reg_value = 0x5570B83A;
2830 break;
bd60018a 2831 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2832 demph_reg_value = 0x2B2B4040;
2833 uniqtranscale_reg_value = 0x55ADDA3A;
2834 break;
2835 default:
2836 return 0;
2837 }
2838 break;
bd60018a 2839 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2840 preemph_reg_value = 0x0006000;
2841 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2842 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2843 demph_reg_value = 0x1B405555;
2844 uniqtranscale_reg_value = 0x55ADDA3A;
2845 break;
2846 default:
2847 return 0;
2848 }
2849 break;
2850 default:
2851 return 0;
2852 }
2853
0980a60f 2854 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2855 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2856 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2857 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2858 uniqtranscale_reg_value);
ab3c759a
CML		 2859 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2860 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2861 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2862 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2863 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2864
2865 return 0;
2866}
2867
e4a1d846
CML		 2868static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2869{
2870 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2871 struct drm_i915_private *dev_priv = dev->dev_private;
2872 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2873 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2874 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2875 uint8_t train_set = intel_dp->train_set[0];
2876 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2877 enum pipe pipe = intel_crtc->pipe;
2878 int i;
e4a1d846
CML		 2879
2880 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2881 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2882 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2883 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2884 deemph_reg_value = 128;
2885 margin_reg_value = 52;
2886 break;
bd60018a 2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2888 deemph_reg_value = 128;
2889 margin_reg_value = 77;
2890 break;
bd60018a 2891 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2892 deemph_reg_value = 128;
2893 margin_reg_value = 102;
2894 break;
bd60018a 2895 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2896 deemph_reg_value = 128;
2897 margin_reg_value = 154;
2898 /* FIXME extra to set for 1200 */
2899 break;
2900 default:
2901 return 0;
2902 }
2903 break;
bd60018a 2904 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2905 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2907 deemph_reg_value = 85;
2908 margin_reg_value = 78;
2909 break;
bd60018a 2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2911 deemph_reg_value = 85;
2912 margin_reg_value = 116;
2913 break;
bd60018a 2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2915 deemph_reg_value = 85;
2916 margin_reg_value = 154;
2917 break;
2918 default:
2919 return 0;
2920 }
2921 break;
bd60018a 2922 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2923 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2925 deemph_reg_value = 64;
2926 margin_reg_value = 104;
2927 break;
bd60018a 2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2929 deemph_reg_value = 64;
2930 margin_reg_value = 154;
2931 break;
2932 default:
2933 return 0;
2934 }
2935 break;
bd60018a 2936 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2937 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2939 deemph_reg_value = 43;
2940 margin_reg_value = 154;
2941 break;
2942 default:
2943 return 0;
2944 }
2945 break;
2946 default:
2947 return 0;
2948 }
2949
2950 mutex_lock(&dev_priv->dpio_lock);
2951
2952 /* Clear calc init */
1966e59e
VS		 2953 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2954 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2955 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2956 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 2957 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2958
2959 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2960 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2961 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2962 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 2963 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 2964
a02ef3c7
VS		 2965 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2966 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2967 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2968 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2969
2970 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2971 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2972 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2973 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2974
e4a1d846 2975 /* Program swing deemph */
f72df8db
VS		 2976 for (i = 0; i < 4; i++) {
2977 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2978 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2979 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2980 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2981 }
e4a1d846
CML		 2982
2983 /* Program swing margin */
f72df8db
VS		 2984 for (i = 0; i < 4; i++) {
2985 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2986 val &= ~DPIO_SWING_MARGIN000_MASK;
2987 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2988 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2989 }
e4a1d846
CML		 2990
2991 /* Disable unique transition scale */
f72df8db
VS		 2992 for (i = 0; i < 4; i++) {
2993 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2994 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2995 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2996 }
e4a1d846
CML		 2997
2998 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 2999 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3000 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3001 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3002
3003 /*
3004 * The document said it needs to set bit 27 for ch0 and bit 26
3005 * for ch1. Might be a typo in the doc.
3006 * For now, for this unique transition scale selection, set bit
3007 * 27 for ch0 and ch1.
3008 */
f72df8db
VS		 3009 for (i = 0; i < 4; i++) {
3010 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3011 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3012 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3013 }
e4a1d846 3014
f72df8db
VS		 3015 for (i = 0; i < 4; i++) {
3016 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3017 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3018 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3019 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3020 }
e4a1d846
CML		 3021 }
3022
3023 /* Start swing calculation */
1966e59e
VS		 3024 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3025 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3026 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3027
3028 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3029 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3030 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3031
3032 /* LRC Bypass */
3033 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3034 val |= DPIO_LRC_BYPASS;
3035 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3036
3037 mutex_unlock(&dev_priv->dpio_lock);
3038
3039 return 0;
3040}
3041
a4fc5ed6 3042static void
0301b3ac
JN		 3043intel_get_adjust_train(struct intel_dp *intel_dp,
3044 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3045{
3046 uint8_t v = 0;
3047 uint8_t p = 0;
3048 int lane;
1a2eb460
KP		 3049 uint8_t voltage_max;
3050 uint8_t preemph_max;
a4fc5ed6 3051
33a34e4e 3052 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3053 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3054 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3055
3056 if (this_v > v)
3057 v = this_v;
3058 if (this_p > p)
3059 p = this_p;
3060 }
3061
1a2eb460 3062 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3063 if (v >= voltage_max)
3064 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3065
1a2eb460
KP		 3066 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3067 if (p >= preemph_max)
3068 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3069
3070 for (lane = 0; lane < 4; lane++)
33a34e4e 3071 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3072}
3073
3074static uint32_t
f0a3424e 3075intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3076{
3cf2efb1 3077 uint32_t signal_levels = 0;
a4fc5ed6 3078
3cf2efb1 3079 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3081 default:
3082 signal_levels |= DP_VOLTAGE_0_4;
3083 break;
bd60018a 3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3085 signal_levels |= DP_VOLTAGE_0_6;
3086 break;
bd60018a 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3088 signal_levels |= DP_VOLTAGE_0_8;
3089 break;
bd60018a 3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3091 signal_levels |= DP_VOLTAGE_1_2;
3092 break;
3093 }
3cf2efb1 3094 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3095 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3096 default:
3097 signal_levels |= DP_PRE_EMPHASIS_0;
3098 break;
bd60018a 3099 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3100 signal_levels |= DP_PRE_EMPHASIS_3_5;
3101 break;
bd60018a 3102 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3103 signal_levels |= DP_PRE_EMPHASIS_6;
3104 break;
bd60018a 3105 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3106 signal_levels |= DP_PRE_EMPHASIS_9_5;
3107 break;
3108 }
3109 return signal_levels;
3110}
3111
e3421a18
ZW		 3112/* Gen6's DP voltage swing and pre-emphasis control */
3113static uint32_t
3114intel_gen6_edp_signal_levels(uint8_t train_set)
3115{
3c5a62b5
YL		 3116 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3117 DP_TRAIN_PRE_EMPHASIS_MASK);
3118 switch (signal_levels) {
bd60018a
SJ		 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3121 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3123 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3126 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3129 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3132 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3133 default:
3c5a62b5
YL		 3134 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3135 "0x%x\n", signal_levels);
3136 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3137 }
3138}
3139
1a2eb460
KP		 3140/* Gen7's DP voltage swing and pre-emphasis control */
3141static uint32_t
3142intel_gen7_edp_signal_levels(uint8_t train_set)
3143{
3144 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3145 DP_TRAIN_PRE_EMPHASIS_MASK);
3146 switch (signal_levels) {
bd60018a 3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3148 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3150 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3151 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3152 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3153
bd60018a 3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3155 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3157 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3158
bd60018a 3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3160 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3162 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3163
3164 default:
3165 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3166 "0x%x\n", signal_levels);
3167 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3168 }
3169}
3170
d6c0d722
PZ		 3171/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3172static uint32_t
f0a3424e 3173intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3174{
d6c0d722
PZ		 3175 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3176 DP_TRAIN_PRE_EMPHASIS_MASK);
3177 switch (signal_levels) {
bd60018a 3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3179 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3181 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3183 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3185 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3186
bd60018a 3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3188 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3190 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3192 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3193
bd60018a 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3195 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3197 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3198 default:
3199 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3200 "0x%x\n", signal_levels);
c5fe6a06 3201 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3202 }
a4fc5ed6
KP		 3203}
3204
f0a3424e
PZ		 3205/* Properly updates "DP" with the correct signal levels. */
3206static void
3207intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3208{
3209 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3210 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3211 struct drm_device *dev = intel_dig_port->base.base.dev;
3212 uint32_t signal_levels, mask;
3213 uint8_t train_set = intel_dp->train_set[0];
3214
5a9d1f1a 3215 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3216 signal_levels = intel_hsw_signal_levels(train_set);
3217 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3218 } else if (IS_CHERRYVIEW(dev)) {
3219 signal_levels = intel_chv_signal_levels(intel_dp);
3220 mask = 0;
e2fa6fba
P		 3221 } else if (IS_VALLEYVIEW(dev)) {
3222 signal_levels = intel_vlv_signal_levels(intel_dp);
3223 mask = 0;
bc7d38a4 3224 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3225 signal_levels = intel_gen7_edp_signal_levels(train_set);
3226 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3227 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3228 signal_levels = intel_gen6_edp_signal_levels(train_set);
3229 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3230 } else {
3231 signal_levels = intel_gen4_signal_levels(train_set);
3232 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3233 }
3234
3235 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3236
3237 *DP = (*DP & ~mask) | signal_levels;
3238}
3239
a4fc5ed6 3240static bool
ea5b213a 3241intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3242 uint32_t *DP,
58e10eb9 3243 uint8_t dp_train_pat)
a4fc5ed6 3244{
174edf1f
PZ		 3245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3246 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3247 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3248 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3249 int ret, len;
a4fc5ed6 3250
7b13b58a 3251 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3252
70aff66c 3253 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3254 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3255
2cdfe6c8
JN		 3256 buf[0] = dp_train_pat;
3257 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3258 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3259 /* don't write DP_TRAINING_LANEx_SET on disable */
3260 len = 1;
3261 } else {
3262 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3263 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3264 len = intel_dp->lane_count + 1;
47ea7542 3265 }
a4fc5ed6 3266
9d1a1031
JN		 3267 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3268 buf, len);
2cdfe6c8
JN		 3269
3270 return ret == len;
a4fc5ed6
KP		 3271}
3272
70aff66c
JN		 3273static bool
3274intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3275 uint8_t dp_train_pat)
3276{
953d22e8 3277 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3278 intel_dp_set_signal_levels(intel_dp, DP);
3279 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3280}
3281
3282static bool
3283intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3284 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3285{
3286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3287 struct drm_device *dev = intel_dig_port->base.base.dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 int ret;
3290
3291 intel_get_adjust_train(intel_dp, link_status);
3292 intel_dp_set_signal_levels(intel_dp, DP);
3293
3294 I915_WRITE(intel_dp->output_reg, *DP);
3295 POSTING_READ(intel_dp->output_reg);
3296
9d1a1031
JN		 3297 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3298 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3299
3300 return ret == intel_dp->lane_count;
3301}
3302
3ab9c637
ID		 3303static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3304{
3305 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3306 struct drm_device *dev = intel_dig_port->base.base.dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 enum port port = intel_dig_port->port;
3309 uint32_t val;
3310
3311 if (!HAS_DDI(dev))
3312 return;
3313
3314 val = I915_READ(DP_TP_CTL(port));
3315 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3316 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3317 I915_WRITE(DP_TP_CTL(port), val);
3318
3319 /*
3320 * On PORT_A we can have only eDP in SST mode. There the only reason
3321 * we need to set idle transmission mode is to work around a HW issue
3322 * where we enable the pipe while not in idle link-training mode.
3323 * In this case there is requirement to wait for a minimum number of
3324 * idle patterns to be sent.
3325 */
3326 if (port == PORT_A)
3327 return;
3328
3329 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3330 1))
3331 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3332}
3333
33a34e4e 3334/* Enable corresponding port and start training pattern 1 */
c19b0669 3335void
33a34e4e 3336intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3337{
da63a9f2 3338 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3339 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3340 int i;
3341 uint8_t voltage;
cdb0e95b 3342 int voltage_tries, loop_tries;
ea5b213a 3343 uint32_t DP = intel_dp->DP;
6aba5b6c 3344 uint8_t link_config[2];
a4fc5ed6 3345
affa9354 3346 if (HAS_DDI(dev))
c19b0669
PZ		 3347 intel_ddi_prepare_link_retrain(encoder);
3348
3cf2efb1 3349 /* Write the link configuration data */
6aba5b6c
JN		 3350 link_config[0] = intel_dp->link_bw;
3351 link_config[1] = intel_dp->lane_count;
3352 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3353 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3354 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3355
3356 link_config[0] = 0;
3357 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3358 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3359
3360 DP |= DP_PORT_EN;
1a2eb460 3361
70aff66c
JN		 3362 /* clock recovery */
3363 if (!intel_dp_reset_link_train(intel_dp, &DP,
3364 DP_TRAINING_PATTERN_1 |
3365 DP_LINK_SCRAMBLING_DISABLE)) {
3366 DRM_ERROR("failed to enable link training\n");
3367 return;
3368 }
3369
a4fc5ed6 3370 voltage = 0xff;
cdb0e95b
KP		 3371 voltage_tries = 0;
3372 loop_tries = 0;
a4fc5ed6 3373 for (;;) {
70aff66c 3374 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3375
a7c9655f 3376 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3377 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3378 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3379 break;
93f62dad 3380 }
a4fc5ed6 3381
01916270 3382 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3383 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3384 break;
3385 }
3386
3387 /* Check to see if we've tried the max voltage */
3388 for (i = 0; i < intel_dp->lane_count; i++)
3389 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3390 break;
3b4f819d 3391 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3392 ++loop_tries;
3393 if (loop_tries == 5) {
3def84b3 3394 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3395 break;
3396 }
70aff66c
JN		 3397 intel_dp_reset_link_train(intel_dp, &DP,
3398 DP_TRAINING_PATTERN_1 |
3399 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3400 voltage_tries = 0;
3401 continue;
3402 }
a4fc5ed6 3403
3cf2efb1 3404 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3405 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3406 ++voltage_tries;
b06fbda3 3407 if (voltage_tries == 5) {
3def84b3 3408 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3409 break;
3410 }
3411 } else
3412 voltage_tries = 0;
3413 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3414
70aff66c
JN		 3415 /* Update training set as requested by target */
3416 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3417 DRM_ERROR("failed to update link training\n");
3418 break;
3419 }
a4fc5ed6
KP		 3420 }
3421
33a34e4e
JB		 3422 intel_dp->DP = DP;
3423}
3424
c19b0669 3425void
33a34e4e
JB		 3426intel_dp_complete_link_train(struct intel_dp *intel_dp)
3427{
33a34e4e 3428 bool channel_eq = false;
37f80975 3429 int tries, cr_tries;
33a34e4e 3430 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3431 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3432
3433 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3434 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3435 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3436
a4fc5ed6 3437 /* channel equalization */
70aff66c 3438 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3439 training_pattern |
70aff66c
JN		 3440 DP_LINK_SCRAMBLING_DISABLE)) {
3441 DRM_ERROR("failed to start channel equalization\n");
3442 return;
3443 }
3444
a4fc5ed6 3445 tries = 0;
37f80975 3446 cr_tries = 0;
a4fc5ed6
KP		 3447 channel_eq = false;
3448 for (;;) {
70aff66c 3449 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3450
37f80975
JB		 3451 if (cr_tries > 5) {
3452 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3453 break;
3454 }
3455
a7c9655f 3456 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3457 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3458 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3459 break;
70aff66c 3460 }
a4fc5ed6 3461
37f80975 3462 /* Make sure clock is still ok */
01916270 3463 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3464 intel_dp_start_link_train(intel_dp);
70aff66c 3465 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3466 training_pattern |
70aff66c 3467 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3468 cr_tries++;
3469 continue;
3470 }
3471
1ffdff13 3472 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3473 channel_eq = true;
3474 break;
3475 }
a4fc5ed6 3476
37f80975
JB		 3477 /* Try 5 times, then try clock recovery if that fails */
3478 if (tries > 5) {
37f80975 3479 intel_dp_start_link_train(intel_dp);
70aff66c 3480 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3481 training_pattern |
70aff66c 3482 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3483 tries = 0;
3484 cr_tries++;
3485 continue;
3486 }
a4fc5ed6 3487
70aff66c
JN		 3488 /* Update training set as requested by target */
3489 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3490 DRM_ERROR("failed to update link training\n");
3491 break;
3492 }
3cf2efb1 3493 ++tries;
869184a6 3494 }
3cf2efb1 3495
3ab9c637
ID		 3496 intel_dp_set_idle_link_train(intel_dp);
3497
3498 intel_dp->DP = DP;
3499
d6c0d722 3500 if (channel_eq)
07f42258 3501 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3502
3ab9c637
ID		 3503}
3504
3505void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3506{
70aff66c 3507 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3508 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3509}
3510
3511static void
ea5b213a 3512intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3513{
da63a9f2 3514 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3515 enum port port = intel_dig_port->port;
da63a9f2 3516 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3517 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3518 struct intel_crtc *intel_crtc =
3519 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3520 uint32_t DP = intel_dp->DP;
a4fc5ed6 3521
bc76e320 3522 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3523 return;
3524
0c33d8d7 3525 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3526 return;
3527
28c97730 3528 DRM_DEBUG_KMS("\n");
32f9d658 3529
bc7d38a4 3530 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3531 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3532 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3533 } else {
aad3d14d
VS		 3534 if (IS_CHERRYVIEW(dev))
3535 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3536 else
3537 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3538 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3539 }
fe255d00 3540 POSTING_READ(intel_dp->output_reg);
5eb08b69 3541
493a7081 3542 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3543 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3544 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3545
5bddd17f
EA		 3546 /* Hardware workaround: leaving our transcoder select
3547 * set to transcoder B while it's off will prevent the
3548 * corresponding HDMI output on transcoder A.
3549 *
3550 * Combine this with another hardware workaround:
3551 * transcoder select bit can only be cleared while the
3552 * port is enabled.
3553 */
3554 DP &= ~DP_PIPEB_SELECT;
3555 I915_WRITE(intel_dp->output_reg, DP);
3556
3557 /* Changes to enable or select take place the vblank
3558 * after being written.
3559 */
ff50afe9
DV		 3560 if (WARN_ON(crtc == NULL)) {
3561 /* We should never try to disable a port without a crtc
3562 * attached. For paranoia keep the code around for a
3563 * bit. */
31acbcc4
CW		 3564 POSTING_READ(intel_dp->output_reg);
3565 msleep(50);
3566 } else
ab527efc 3567 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3568 }
3569
832afda6 3570 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3571 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3572 POSTING_READ(intel_dp->output_reg);
f01eca2e 3573 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3574}
3575
26d61aad
KP		 3576static bool
3577intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3578{
a031d709
RV		 3579 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3580 struct drm_device *dev = dig_port->base.base.dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582
9d1a1031
JN		 3583 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3584 sizeof(intel_dp->dpcd)) < 0)
edb39244 3585 return false; /* aux transfer failed */
92fd8fd1 3586
a8e98153 3587 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3588
edb39244
AJ		 3589 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3590 return false; /* DPCD not present */
3591
2293bb5c
SK		 3592 /* Check if the panel supports PSR */
3593 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3594 if (is_edp(intel_dp)) {
9d1a1031
JN		 3595 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3596 intel_dp->psr_dpcd,
3597 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3598 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3599 dev_priv->psr.sink_support = true;
50003939 3600 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3601 }
50003939
JN		 3602 }
3603
7809a611 3604 /* Training Pattern 3 support, both source and sink */
06ea66b6 3605 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3606 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3607 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3608 intel_dp->use_tps3 = true;
f8d8a672 3609 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3610 } else
3611 intel_dp->use_tps3 = false;
3612
edb39244
AJ		 3613 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3614 DP_DWN_STRM_PORT_PRESENT))
3615 return true; /* native DP sink */
3616
3617 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3618 return true; /* no per-port downstream info */
3619
9d1a1031
JN		 3620 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3621 intel_dp->downstream_ports,
3622 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3623 return false; /* downstream port status fetch failed */
3624
3625 return true;
92fd8fd1
KP		 3626}
3627
0d198328
AJ		 3628static void
3629intel_dp_probe_oui(struct intel_dp *intel_dp)
3630{
3631 u8 buf[3];
3632
3633 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3634 return;
3635
9d1a1031 3636 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3637 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3638 buf[0], buf[1], buf[2]);
3639
9d1a1031 3640 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3641 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3642 buf[0], buf[1], buf[2]);
3643}
3644
0e32b39c
DA		 3645static bool
3646intel_dp_probe_mst(struct intel_dp *intel_dp)
3647{
3648 u8 buf[1];
3649
3650 if (!intel_dp->can_mst)
3651 return false;
3652
3653 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3654 return false;
3655
0e32b39c
DA		 3656 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3657 if (buf[0] & DP_MST_CAP) {
3658 DRM_DEBUG_KMS("Sink is MST capable\n");
3659 intel_dp->is_mst = true;
3660 } else {
3661 DRM_DEBUG_KMS("Sink is not MST capable\n");
3662 intel_dp->is_mst = false;
3663 }
3664 }
0e32b39c
DA		 3665
3666 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3667 return intel_dp->is_mst;
3668}
3669
d2e216d0
RV		 3670int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3671{
3672 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3673 struct drm_device *dev = intel_dig_port->base.base.dev;
3674 struct intel_crtc *intel_crtc =
3675 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3676 u8 buf;
3677 int test_crc_count;
3678 int attempts = 6;
d2e216d0 3679
ad9dc91b 3680 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3681 return -EIO;
d2e216d0 3682
ad9dc91b 3683 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3684 return -ENOTTY;
3685
1dda5f93
RV		 3686 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3687 return -EIO;
3688
9d1a1031 3689 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3690 buf | DP_TEST_SINK_START) < 0)
bda0381e 3691 return -EIO;
d2e216d0 3692
1dda5f93 3693 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3694 return -EIO;
ad9dc91b 3695 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3696
ad9dc91b 3697 do {
1dda5f93
RV		 3698 if (drm_dp_dpcd_readb(&intel_dp->aux,
3699 DP_TEST_SINK_MISC, &buf) < 0)
3700 return -EIO;
ad9dc91b
RV		 3701 intel_wait_for_vblank(dev, intel_crtc->pipe);
3702 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3703
3704 if (attempts == 0) {
90bd1f46
DV		 3705 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3706 return -ETIMEDOUT;
ad9dc91b 3707 }
d2e216d0 3708
9d1a1031 3709 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3710 return -EIO;
d2e216d0 3711
1dda5f93
RV		 3712 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3713 return -EIO;
3714 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3715 buf & ~DP_TEST_SINK_START) < 0)
3716 return -EIO;
ce31d9f4 3717
d2e216d0
RV		 3718 return 0;
3719}
3720
a60f0e38
JB		 3721static bool
3722intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3723{
9d1a1031
JN		 3724 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3725 DP_DEVICE_SERVICE_IRQ_VECTOR,
3726 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3727}
3728
0e32b39c
DA		 3729static bool
3730intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3731{
3732 int ret;
3733
3734 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3735 DP_SINK_COUNT_ESI,
3736 sink_irq_vector, 14);
3737 if (ret != 14)
3738 return false;
3739
3740 return true;
3741}
3742
a60f0e38
JB		 3743static void
3744intel_dp_handle_test_request(struct intel_dp *intel_dp)
3745{
3746 /* NAK by default */
9d1a1031 3747 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3748}
3749
0e32b39c
DA		 3750static int
3751intel_dp_check_mst_status(struct intel_dp *intel_dp)
3752{
3753 bool bret;
3754
3755 if (intel_dp->is_mst) {
3756 u8 esi[16] = { 0 };
3757 int ret = 0;
3758 int retry;
3759 bool handled;
3760 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3761go_again:
3762 if (bret == true) {
3763
3764 /* check link status - esi[10] = 0x200c */
3765 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3766 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3767 intel_dp_start_link_train(intel_dp);
3768 intel_dp_complete_link_train(intel_dp);
3769 intel_dp_stop_link_train(intel_dp);
3770 }
3771
3772 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3773 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3774
3775 if (handled) {
3776 for (retry = 0; retry < 3; retry++) {
3777 int wret;
3778 wret = drm_dp_dpcd_write(&intel_dp->aux,
3779 DP_SINK_COUNT_ESI+1,
3780 &esi[1], 3);
3781 if (wret == 3) {
3782 break;
3783 }
3784 }
3785
3786 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3787 if (bret == true) {
3788 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3789 goto go_again;
3790 }
3791 } else
3792 ret = 0;
3793
3794 return ret;
3795 } else {
3796 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3797 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3798 intel_dp->is_mst = false;
3799 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3800 /* send a hotplug event */
3801 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3802 }
3803 }
3804 return -EINVAL;
3805}
3806
a4fc5ed6
KP		 3807/*
3808 * According to DP spec
3809 * 5.1.2:
3810 * 1. Read DPCD
3811 * 2. Configure link according to Receiver Capabilities
3812 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3813 * 4. Check link status on receipt of hot-plug interrupt
3814 */
00c09d70 3815void
ea5b213a 3816intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3817{
5b215bcf 3818 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3819 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3820 u8 sink_irq_vector;
93f62dad 3821 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3822
5b215bcf
DA		 3823 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3824
da63a9f2 3825 if (!intel_encoder->connectors_active)
d2b996ac 3826 return;
59cd09e1 3827
da63a9f2 3828 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3829 return;
3830
1a125d8a
ID		 3831 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3832 return;
3833
92fd8fd1 3834 /* Try to read receiver status if the link appears to be up */
93f62dad 3835 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3836 return;
3837 }
3838
92fd8fd1 3839 /* Now read the DPCD to see if it's actually running */
26d61aad 3840 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3841 return;
3842 }
3843
a60f0e38
JB		 3844 /* Try to read the source of the interrupt */
3845 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3846 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3847 /* Clear interrupt source */
9d1a1031
JN		 3848 drm_dp_dpcd_writeb(&intel_dp->aux,
3849 DP_DEVICE_SERVICE_IRQ_VECTOR,
3850 sink_irq_vector);
a60f0e38
JB		 3851
3852 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3853 intel_dp_handle_test_request(intel_dp);
3854 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3855 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3856 }
3857
1ffdff13 3858 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3859 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3860 intel_encoder->base.name);
33a34e4e
JB		 3861 intel_dp_start_link_train(intel_dp);
3862 intel_dp_complete_link_train(intel_dp);
3ab9c637 3863 intel_dp_stop_link_train(intel_dp);
33a34e4e 3864 }
a4fc5ed6 3865}
a4fc5ed6 3866
caf9ab24 3867/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3868static enum drm_connector_status
26d61aad 3869intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3870{
caf9ab24 3871 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3872 uint8_t type;
3873
3874 if (!intel_dp_get_dpcd(intel_dp))
3875 return connector_status_disconnected;
3876
3877 /* if there's no downstream port, we're done */
3878 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3879 return connector_status_connected;
caf9ab24
AJ		 3880
3881 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3882 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3883 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3884 uint8_t reg;
9d1a1031
JN		 3885
3886 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3887 &reg, 1) < 0)
caf9ab24 3888 return connector_status_unknown;
9d1a1031 3889
23235177
AJ		 3890 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3891 : connector_status_disconnected;
caf9ab24
AJ		 3892 }
3893
3894 /* If no HPD, poke DDC gently */
0b99836f 3895 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3896 return connector_status_connected;
caf9ab24
AJ		 3897
3898 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3899 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3900 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3901 if (type == DP_DS_PORT_TYPE_VGA ||
3902 type == DP_DS_PORT_TYPE_NON_EDID)
3903 return connector_status_unknown;
3904 } else {
3905 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3906 DP_DWN_STRM_PORT_TYPE_MASK;
3907 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3908 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3909 return connector_status_unknown;
3910 }
caf9ab24
AJ		 3911
3912 /* Anything else is out of spec, warn and ignore */
3913 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3914 return connector_status_disconnected;
71ba9000
AJ		 3915}
3916
d410b56d
CW		 3917static enum drm_connector_status
3918edp_detect(struct intel_dp *intel_dp)
3919{
3920 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3921 enum drm_connector_status status;
3922
3923 status = intel_panel_detect(dev);
3924 if (status == connector_status_unknown)
3925 status = connector_status_connected;
3926
3927 return status;
3928}
3929
5eb08b69 3930static enum drm_connector_status
a9756bb5 3931ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3932{
30add22d 3933 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3934 struct drm_i915_private *dev_priv = dev->dev_private;
3935 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3936
1b469639
DL		 3937 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3938 return connector_status_disconnected;
3939
26d61aad 3940 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3941}
3942
2a592bec
DA		 3943static int g4x_digital_port_connected(struct drm_device *dev,
3944 struct intel_digital_port *intel_dig_port)
a4fc5ed6 3945{
a4fc5ed6 3946 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 3947 uint32_t bit;
5eb08b69 3948
232a6ee9
TP		 3949 if (IS_VALLEYVIEW(dev)) {
3950 switch (intel_dig_port->port) {
3951 case PORT_B:
3952 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3953 break;
3954 case PORT_C:
3955 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3956 break;
3957 case PORT_D:
3958 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3959 break;
3960 default:
2a592bec 3961 return -EINVAL;
232a6ee9
TP		 3962 }
3963 } else {
3964 switch (intel_dig_port->port) {
3965 case PORT_B:
3966 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3967 break;
3968 case PORT_C:
3969 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3970 break;
3971 case PORT_D:
3972 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3973 break;
3974 default:
2a592bec 3975 return -EINVAL;
232a6ee9 3976 }
a4fc5ed6
KP		 3977 }
3978
10f76a38 3979 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 3980 return 0;
3981 return 1;
3982}
3983
3984static enum drm_connector_status
3985g4x_dp_detect(struct intel_dp *intel_dp)
3986{
3987 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3988 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3989 int ret;
3990
3991 /* Can't disconnect eDP, but you can close the lid... */
3992 if (is_edp(intel_dp)) {
3993 enum drm_connector_status status;
3994
3995 status = intel_panel_detect(dev);
3996 if (status == connector_status_unknown)
3997 status = connector_status_connected;
3998 return status;
3999 }
4000
4001 ret = g4x_digital_port_connected(dev, intel_dig_port);
4002 if (ret == -EINVAL)
4003 return connector_status_unknown;
4004 else if (ret == 0)
a4fc5ed6
KP		 4005 return connector_status_disconnected;
4006
26d61aad 4007 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4008}
4009
8c241fef 4010static struct edid *
beb60608 4011intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4012{
beb60608 4013 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4014
9cd300e0
JN		 4015 /* use cached edid if we have one */
4016 if (intel_connector->edid) {
9cd300e0
JN		 4017 /* invalid edid */
4018 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4019 return NULL;
4020
55e9edeb 4021 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4022 } else
4023 return drm_get_edid(&intel_connector->base,
4024 &intel_dp->aux.ddc);
4025}
8c241fef 4026
beb60608
CW		 4027static void
4028intel_dp_set_edid(struct intel_dp *intel_dp)
4029{
4030 struct intel_connector *intel_connector = intel_dp->attached_connector;
4031 struct edid *edid;
8c241fef 4032
beb60608
CW		 4033 edid = intel_dp_get_edid(intel_dp);
4034 intel_connector->detect_edid = edid;
4035
4036 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4037 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4038 else
4039 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4040}
4041
beb60608
CW		 4042static void
4043intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4044{
beb60608 4045 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4046
beb60608
CW		 4047 kfree(intel_connector->detect_edid);
4048 intel_connector->detect_edid = NULL;
9cd300e0 4049
beb60608
CW		 4050 intel_dp->has_audio = false;
4051}
d6f24d0f 4052
beb60608
CW		 4053static enum intel_display_power_domain
4054intel_dp_power_get(struct intel_dp *dp)
4055{
4056 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4057 enum intel_display_power_domain power_domain;
4058
4059 power_domain = intel_display_port_power_domain(encoder);
4060 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4061
4062 return power_domain;
4063}
d6f24d0f 4064
beb60608
CW		 4065static void
4066intel_dp_power_put(struct intel_dp *dp,
4067 enum intel_display_power_domain power_domain)
4068{
4069 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4070 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4071}
4072
a9756bb5
ZW		 4073static enum drm_connector_status
4074intel_dp_detect(struct drm_connector *connector, bool force)
4075{
4076 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4077 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4078 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4079 struct drm_device *dev = connector->dev;
a9756bb5 4080 enum drm_connector_status status;
671dedd2 4081 enum intel_display_power_domain power_domain;
0e32b39c 4082 bool ret;
a9756bb5 4083
164c8598 4084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4085 connector->base.id, connector->name);
beb60608 4086 intel_dp_unset_edid(intel_dp);
164c8598 4087
0e32b39c
DA		 4088 if (intel_dp->is_mst) {
4089 /* MST devices are disconnected from a monitor POV */
4090 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4091 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4092 return connector_status_disconnected;
0e32b39c
DA		 4093 }
4094
beb60608 4095 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4096
d410b56d
CW		 4097 /* Can't disconnect eDP, but you can close the lid... */
4098 if (is_edp(intel_dp))
4099 status = edp_detect(intel_dp);
4100 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4101 status = ironlake_dp_detect(intel_dp);
4102 else
4103 status = g4x_dp_detect(intel_dp);
4104 if (status != connector_status_connected)
c8c8fb33 4105 goto out;
a9756bb5 4106
0d198328
AJ		 4107 intel_dp_probe_oui(intel_dp);
4108
0e32b39c
DA		 4109 ret = intel_dp_probe_mst(intel_dp);
4110 if (ret) {
4111 /* if we are in MST mode then this connector
4112 won't appear connected or have anything with EDID on it */
4113 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4114 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4115 status = connector_status_disconnected;
4116 goto out;
4117 }
4118
beb60608 4119 intel_dp_set_edid(intel_dp);
a9756bb5 4120
d63885da
PZ		 4121 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4122 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4123 status = connector_status_connected;
4124
4125out:
beb60608 4126 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4127 return status;
a4fc5ed6
KP		 4128}
4129
beb60608
CW		 4130static void
4131intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4132{
df0e9248 4133 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4134 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4135 enum intel_display_power_domain power_domain;
a4fc5ed6 4136
beb60608
CW		 4137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4138 connector->base.id, connector->name);
4139 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4140
beb60608
CW		 4141 if (connector->status != connector_status_connected)
4142 return;
671dedd2 4143
beb60608
CW		 4144 power_domain = intel_dp_power_get(intel_dp);
4145
4146 intel_dp_set_edid(intel_dp);
4147
4148 intel_dp_power_put(intel_dp, power_domain);
4149
4150 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4151 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4152}
4153
4154static int intel_dp_get_modes(struct drm_connector *connector)
4155{
4156 struct intel_connector *intel_connector = to_intel_connector(connector);
4157 struct edid *edid;
4158
4159 edid = intel_connector->detect_edid;
4160 if (edid) {
4161 int ret = intel_connector_update_modes(connector, edid);
4162 if (ret)
4163 return ret;
4164 }
32f9d658 4165
f8779fda 4166 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4167 if (is_edp(intel_attached_dp(connector)) &&
4168 intel_connector->panel.fixed_mode) {
f8779fda 4169 struct drm_display_mode *mode;
beb60608
CW		 4170
4171 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4172 intel_connector->panel.fixed_mode);
f8779fda 4173 if (mode) {
32f9d658
ZW		 4174 drm_mode_probed_add(connector, mode);
4175 return 1;
4176 }
4177 }
beb60608 4178
32f9d658 4179 return 0;
a4fc5ed6
KP		 4180}
4181
1aad7ac0
CW		 4182static bool
4183intel_dp_detect_audio(struct drm_connector *connector)
4184{
1aad7ac0 4185 bool has_audio = false;
beb60608 4186 struct edid *edid;
1aad7ac0 4187
beb60608
CW		 4188 edid = to_intel_connector(connector)->detect_edid;
4189 if (edid)
1aad7ac0 4190 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4191
1aad7ac0
CW		 4192 return has_audio;
4193}
4194
f684960e
CW		 4195static int
4196intel_dp_set_property(struct drm_connector *connector,
4197 struct drm_property *property,
4198 uint64_t val)
4199{
e953fd7b 4200 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4201 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4202 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4203 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4204 int ret;
4205
662595df 4206 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4207 if (ret)
4208 return ret;
4209
3f43c48d 4210 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4211 int i = val;
4212 bool has_audio;
4213
4214 if (i == intel_dp->force_audio)
f684960e
CW		 4215 return 0;
4216
1aad7ac0 4217 intel_dp->force_audio = i;
f684960e 4218
c3e5f67b 4219 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4220 has_audio = intel_dp_detect_audio(connector);
4221 else
c3e5f67b 4222 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4223
4224 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4225 return 0;
4226
1aad7ac0 4227 intel_dp->has_audio = has_audio;
f684960e
CW		 4228 goto done;
4229 }
4230
e953fd7b 4231 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4232 bool old_auto = intel_dp->color_range_auto;
4233 uint32_t old_range = intel_dp->color_range;
4234
55bc60db
VS		 4235 switch (val) {
4236 case INTEL_BROADCAST_RGB_AUTO:
4237 intel_dp->color_range_auto = true;
4238 break;
4239 case INTEL_BROADCAST_RGB_FULL:
4240 intel_dp->color_range_auto = false;
4241 intel_dp->color_range = 0;
4242 break;
4243 case INTEL_BROADCAST_RGB_LIMITED:
4244 intel_dp->color_range_auto = false;
4245 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4246 break;
4247 default:
4248 return -EINVAL;
4249 }
ae4edb80
DV		 4250
4251 if (old_auto == intel_dp->color_range_auto &&
4252 old_range == intel_dp->color_range)
4253 return 0;
4254
e953fd7b
CW		 4255 goto done;
4256 }
4257
53b41837
YN		 4258 if (is_edp(intel_dp) &&
4259 property == connector->dev->mode_config.scaling_mode_property) {
4260 if (val == DRM_MODE_SCALE_NONE) {
4261 DRM_DEBUG_KMS("no scaling not supported\n");
4262 return -EINVAL;
4263 }
4264
4265 if (intel_connector->panel.fitting_mode == val) {
4266 /* the eDP scaling property is not changed */
4267 return 0;
4268 }
4269 intel_connector->panel.fitting_mode = val;
4270
4271 goto done;
4272 }
4273
f684960e
CW		 4274 return -EINVAL;
4275
4276done:
c0c36b94
CW		 4277 if (intel_encoder->base.crtc)
4278 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4279
4280 return 0;
4281}
4282
a4fc5ed6 4283static void
73845adf 4284intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4285{
1d508706 4286 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4287
10e972d3 4288 kfree(intel_connector->detect_edid);
beb60608 4289
9cd300e0
JN		 4290 if (!IS_ERR_OR_NULL(intel_connector->edid))
4291 kfree(intel_connector->edid);
4292
acd8db10
PZ		 4293 /* Can't call is_edp() since the encoder may have been destroyed
4294 * already. */
4295 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4296 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4297
a4fc5ed6 4298 drm_connector_cleanup(connector);
55f78c43 4299 kfree(connector);
a4fc5ed6
KP		 4300}
4301
00c09d70 4302void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4303{
da63a9f2
PZ		 4304 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4305 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4306
4f71d0cb 4307 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4308 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4309 drm_encoder_cleanup(encoder);
bd943159
KP		 4310 if (is_edp(intel_dp)) {
4311 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4312 /*
4313 * vdd might still be enabled do to the delayed vdd off.
4314 * Make sure vdd is actually turned off here.
4315 */
773538e8 4316 pps_lock(intel_dp);
4be73780 4317 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4318 pps_unlock(intel_dp);
4319
01527b31
CT		 4320 if (intel_dp->edp_notifier.notifier_call) {
4321 unregister_reboot_notifier(&intel_dp->edp_notifier);
4322 intel_dp->edp_notifier.notifier_call = NULL;
4323 }
bd943159 4324 }
da63a9f2 4325 kfree(intel_dig_port);
24d05927
DV		 4326}
4327
07f9cd0b
ID		 4328static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4329{
4330 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4331
4332 if (!is_edp(intel_dp))
4333 return;
4334
951468f3
VS		 4335 /*
4336 * vdd might still be enabled do to the delayed vdd off.
4337 * Make sure vdd is actually turned off here.
4338 */
afa4e53a 4339 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4340 pps_lock(intel_dp);
07f9cd0b 4341 edp_panel_vdd_off_sync(intel_dp);
773538e8 4342 pps_unlock(intel_dp);
07f9cd0b
ID		 4343}
4344
49e6bc51
VS		 4345static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4346{
4347 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4348 struct drm_device *dev = intel_dig_port->base.base.dev;
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350 enum intel_display_power_domain power_domain;
4351
4352 lockdep_assert_held(&dev_priv->pps_mutex);
4353
4354 if (!edp_have_panel_vdd(intel_dp))
4355 return;
4356
4357 /*
4358 * The VDD bit needs a power domain reference, so if the bit is
4359 * already enabled when we boot or resume, grab this reference and
4360 * schedule a vdd off, so we don't hold on to the reference
4361 * indefinitely.
4362 */
4363 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4364 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4365 intel_display_power_get(dev_priv, power_domain);
4366
4367 edp_panel_vdd_schedule_off(intel_dp);
4368}
4369
6d93c0c4
ID		 4370static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4371{
49e6bc51
VS		 4372 struct intel_dp *intel_dp;
4373
4374 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4375 return;
4376
4377 intel_dp = enc_to_intel_dp(encoder);
4378
4379 pps_lock(intel_dp);
4380
4381 /*
4382 * Read out the current power sequencer assignment,
4383 * in case the BIOS did something with it.
4384 */
4385 if (IS_VALLEYVIEW(encoder->dev))
4386 vlv_initial_power_sequencer_setup(intel_dp);
4387
4388 intel_edp_panel_vdd_sanitize(intel_dp);
4389
4390 pps_unlock(intel_dp);
6d93c0c4
ID		 4391}
4392
a4fc5ed6 4393static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4394 .dpms = intel_connector_dpms,
a4fc5ed6 4395 .detect = intel_dp_detect,
beb60608 4396 .force = intel_dp_force,
a4fc5ed6 4397 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4398 .set_property = intel_dp_set_property,
73845adf 4399 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4400};
4401
4402static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4403 .get_modes = intel_dp_get_modes,
4404 .mode_valid = intel_dp_mode_valid,
df0e9248 4405 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4406};
4407
a4fc5ed6 4408static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4409 .reset = intel_dp_encoder_reset,
24d05927 4410 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4411};
4412
0e32b39c 4413void
21d40d37 4414intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4415{
0e32b39c 4416 return;
c8110e52 4417}
6207937d 4418
13cf5504
DA		 4419bool
4420intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4421{
4422 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4423 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4424 struct drm_device *dev = intel_dig_port->base.base.dev;
4425 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4426 enum intel_display_power_domain power_domain;
4427 bool ret = true;
4428
0e32b39c
DA		 4429 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4430 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4431
7a7f84cc
VS		 4432 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4433 /*
4434 * vdd off can generate a long pulse on eDP which
4435 * would require vdd on to handle it, and thus we
4436 * would end up in an endless cycle of
4437 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4438 */
4439 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4440 port_name(intel_dig_port->port));
4441 return false;
4442 }
4443
26fbb774
VS		 4444 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4445 port_name(intel_dig_port->port),
0e32b39c 4446 long_hpd ? "long" : "short");
13cf5504 4447
1c767b33
ID		 4448 power_domain = intel_display_port_power_domain(intel_encoder);
4449 intel_display_power_get(dev_priv, power_domain);
4450
0e32b39c 4451 if (long_hpd) {
2a592bec
DA		 4452
4453 if (HAS_PCH_SPLIT(dev)) {
4454 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4455 goto mst_fail;
4456 } else {
4457 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4458 goto mst_fail;
4459 }
0e32b39c
DA		 4460
4461 if (!intel_dp_get_dpcd(intel_dp)) {
4462 goto mst_fail;
4463 }
4464
4465 intel_dp_probe_oui(intel_dp);
4466
4467 if (!intel_dp_probe_mst(intel_dp))
4468 goto mst_fail;
4469
4470 } else {
4471 if (intel_dp->is_mst) {
1c767b33 4472 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4473 goto mst_fail;
4474 }
4475
4476 if (!intel_dp->is_mst) {
4477 /*
4478 * we'll check the link status via the normal hot plug path later -
4479 * but for short hpds we should check it now
4480 */
5b215bcf 4481 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4482 intel_dp_check_link_status(intel_dp);
5b215bcf 4483 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4484 }
4485 }
1c767b33
ID		 4486 ret = false;
4487 goto put_power;
0e32b39c
DA		 4488mst_fail:
4489 /* if we were in MST mode, and device is not there get out of MST mode */
4490 if (intel_dp->is_mst) {
4491 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4492 intel_dp->is_mst = false;
4493 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4494 }
1c767b33
ID		 4495put_power:
4496 intel_display_power_put(dev_priv, power_domain);
4497
4498 return ret;
13cf5504
DA		 4499}
4500
e3421a18
ZW		 4501/* Return which DP Port should be selected for Transcoder DP control */
4502int
0206e353 4503intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4504{
4505 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4506 struct intel_encoder *intel_encoder;
4507 struct intel_dp *intel_dp;
e3421a18 4508
fa90ecef
PZ		 4509 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4510 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4511
fa90ecef
PZ		 4512 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4513 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4514 return intel_dp->output_reg;
e3421a18 4515 }
ea5b213a 4516
e3421a18
ZW		 4517 return -1;
4518}
4519
36e83a18 4520/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4521bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4522{
4523 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4524 union child_device_config *p_child;
36e83a18 4525 int i;
5d8a7752
VS		 4526 static const short port_mapping[] = {
4527 [PORT_B] = PORT_IDPB,
4528 [PORT_C] = PORT_IDPC,
4529 [PORT_D] = PORT_IDPD,
4530 };
36e83a18 4531
3b32a35b
VS		 4532 if (port == PORT_A)
4533 return true;
4534
41aa3448 4535 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4536 return false;
4537
41aa3448
RV		 4538 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4539 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4540
5d8a7752 4541 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4542 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4543 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4544 return true;
4545 }
4546 return false;
4547}
4548
0e32b39c 4549void
f684960e
CW		 4550intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4551{
53b41837
YN		 4552 struct intel_connector *intel_connector = to_intel_connector(connector);
4553
3f43c48d 4554 intel_attach_force_audio_property(connector);
e953fd7b 4555 intel_attach_broadcast_rgb_property(connector);
55bc60db 4556 intel_dp->color_range_auto = true;
53b41837
YN		 4557
4558 if (is_edp(intel_dp)) {
4559 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4560 drm_object_attach_property(
4561 &connector->base,
53b41837 4562 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4563 DRM_MODE_SCALE_ASPECT);
4564 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4565 }
f684960e
CW		 4566}
4567
dada1a9f
ID		 4568static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4569{
4570 intel_dp->last_power_cycle = jiffies;
4571 intel_dp->last_power_on = jiffies;
4572 intel_dp->last_backlight_off = jiffies;
4573}
4574
67a54566
DV		 4575static void
4576intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4577 struct intel_dp *intel_dp)
67a54566
DV		 4578{
4579 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4580 struct edp_power_seq cur, vbt, spec,
4581 *final = &intel_dp->pps_delays;
67a54566 4582 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4583 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4584
e39b999a
VS		 4585 lockdep_assert_held(&dev_priv->pps_mutex);
4586
81ddbc69
VS		 4587 /* already initialized? */
4588 if (final->t11_t12 != 0)
4589 return;
4590
453c5420 4591 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4592 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4593 pp_on_reg = PCH_PP_ON_DELAYS;
4594 pp_off_reg = PCH_PP_OFF_DELAYS;
4595 pp_div_reg = PCH_PP_DIVISOR;
4596 } else {
bf13e81b
JN		 4597 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4598
4599 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4600 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4601 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4602 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4603 }
67a54566
DV		 4604
4605 /* Workaround: Need to write PP_CONTROL with the unlock key as
4606 * the very first thing. */
453c5420 4607 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4608 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4609
453c5420
JB		 4610 pp_on = I915_READ(pp_on_reg);
4611 pp_off = I915_READ(pp_off_reg);
4612 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4613
4614 /* Pull timing values out of registers */
4615 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4616 PANEL_POWER_UP_DELAY_SHIFT;
4617
4618 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4619 PANEL_LIGHT_ON_DELAY_SHIFT;
4620
4621 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4622 PANEL_LIGHT_OFF_DELAY_SHIFT;
4623
4624 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4625 PANEL_POWER_DOWN_DELAY_SHIFT;
4626
4627 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4628 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4629
4630 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4631 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4632
41aa3448 4633 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4634
4635 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4636 * our hw here, which are all in 100usec. */
4637 spec.t1_t3 = 210 * 10;
4638 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4639 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4640 spec.t10 = 500 * 10;
4641 /* This one is special and actually in units of 100ms, but zero
4642 * based in the hw (so we need to add 100 ms). But the sw vbt
4643 * table multiplies it with 1000 to make it in units of 100usec,
4644 * too. */
4645 spec.t11_t12 = (510 + 100) * 10;
4646
4647 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4648 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4649
4650 /* Use the max of the register settings and vbt. If both are
4651 * unset, fall back to the spec limits. */
36b5f425 4652#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4653 spec.field : \
4654 max(cur.field, vbt.field))
4655 assign_final(t1_t3);
4656 assign_final(t8);
4657 assign_final(t9);
4658 assign_final(t10);
4659 assign_final(t11_t12);
4660#undef assign_final
4661
36b5f425 4662#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4663 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4664 intel_dp->backlight_on_delay = get_delay(t8);
4665 intel_dp->backlight_off_delay = get_delay(t9);
4666 intel_dp->panel_power_down_delay = get_delay(t10);
4667 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4668#undef get_delay
4669
f30d26e4
JN		 4670 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4671 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4672 intel_dp->panel_power_cycle_delay);
4673
4674 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4675 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4676}
4677
4678static void
4679intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4680 struct intel_dp *intel_dp)
f30d26e4
JN		 4681{
4682 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4683 u32 pp_on, pp_off, pp_div, port_sel = 0;
4684 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4685 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4686 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4687 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4688
e39b999a 4689 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4690
4691 if (HAS_PCH_SPLIT(dev)) {
4692 pp_on_reg = PCH_PP_ON_DELAYS;
4693 pp_off_reg = PCH_PP_OFF_DELAYS;
4694 pp_div_reg = PCH_PP_DIVISOR;
4695 } else {
bf13e81b
JN		 4696 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4697
4698 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4699 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4700 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4701 }
4702
b2f19d1a
PZ		 4703 /*
4704 * And finally store the new values in the power sequencer. The
4705 * backlight delays are set to 1 because we do manual waits on them. For
4706 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4707 * we'll end up waiting for the backlight off delay twice: once when we
4708 * do the manual sleep, and once when we disable the panel and wait for
4709 * the PP_STATUS bit to become zero.
4710 */
f30d26e4 4711 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4712 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4713 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4714 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4715 /* Compute the divisor for the pp clock, simply match the Bspec
4716 * formula. */
453c5420 4717 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4718 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4719 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4720
4721 /* Haswell doesn't have any port selection bits for the panel
4722 * power sequencer any more. */
bc7d38a4 4723 if (IS_VALLEYVIEW(dev)) {
ad933b56 4724 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4725 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4726 if (port == PORT_A)
a24c144c 4727 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4728 else
a24c144c 4729 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4730 }
4731
453c5420
JB		 4732 pp_on |= port_sel;
4733
4734 I915_WRITE(pp_on_reg, pp_on);
4735 I915_WRITE(pp_off_reg, pp_off);
4736 I915_WRITE(pp_div_reg, pp_div);
67a54566 4737
67a54566 4738 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4739 I915_READ(pp_on_reg),
4740 I915_READ(pp_off_reg),
4741 I915_READ(pp_div_reg));
f684960e
CW		 4742}
4743
439d7ac0
PB		 4744void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4745{
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct intel_encoder *encoder;
4748 struct intel_dp *intel_dp = NULL;
4749 struct intel_crtc_config *config = NULL;
4750 struct intel_crtc *intel_crtc = NULL;
4751 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4752 u32 reg, val;
4753 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4754
4755 if (refresh_rate <= 0) {
4756 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4757 return;
4758 }
4759
4760 if (intel_connector == NULL) {
4761 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4762 return;
4763 }
4764
1fcc9d1c
DV		 4765 /*
4766 * FIXME: This needs proper synchronization with psr state. But really
4767 * hard to tell without seeing the user of this function of this code.
4768 * Check locking and ordering once that lands.
4769 */
0bc12bcb 4770 if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
439d7ac0
PB		 4771 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4772 return;
4773 }
4774
4775 encoder = intel_attached_encoder(&intel_connector->base);
4776 intel_dp = enc_to_intel_dp(&encoder->base);
4777 intel_crtc = encoder->new_crtc;
4778
4779 if (!intel_crtc) {
4780 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4781 return;
4782 }
4783
4784 config = &intel_crtc->config;
4785
4786 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4787 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4788 return;
4789 }
4790
4791 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4792 index = DRRS_LOW_RR;
4793
4794 if (index == intel_dp->drrs_state.refresh_rate_type) {
4795 DRM_DEBUG_KMS(
4796 "DRRS requested for previously set RR...ignoring\n");
4797 return;
4798 }
4799
4800 if (!intel_crtc->active) {
4801 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4802 return;
4803 }
4804
4805 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4806 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4807 val = I915_READ(reg);
4808 if (index > DRRS_HIGH_RR) {
4809 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4810 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4811 } else {
4812 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4813 }
4814 I915_WRITE(reg, val);
4815 }
4816
4817 /*
4818 * mutex taken to ensure that there is no race between differnt
4819 * drrs calls trying to update refresh rate. This scenario may occur
4820 * in future when idleness detection based DRRS in kernel and
4821 * possible calls from user space to set differnt RR are made.
4822 */
4823
4824 mutex_lock(&intel_dp->drrs_state.mutex);
4825
4826 intel_dp->drrs_state.refresh_rate_type = index;
4827
4828 mutex_unlock(&intel_dp->drrs_state.mutex);
4829
4830 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4831}
4832
4f9db5b5
PB		 4833static struct drm_display_mode *
4834intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4835 struct intel_connector *intel_connector,
4836 struct drm_display_mode *fixed_mode)
4837{
4838 struct drm_connector *connector = &intel_connector->base;
4839 struct intel_dp *intel_dp = &intel_dig_port->dp;
4840 struct drm_device *dev = intel_dig_port->base.base.dev;
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 struct drm_display_mode *downclock_mode = NULL;
4843
4844 if (INTEL_INFO(dev)->gen <= 6) {
4845 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4846 return NULL;
4847 }
4848
4849 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4850 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4851 return NULL;
4852 }
4853
4854 downclock_mode = intel_find_panel_downclock
4855 (dev, fixed_mode, connector);
4856
4857 if (!downclock_mode) {
4079b8d1 4858 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4859 return NULL;
4860 }
4861
439d7ac0
PB		 4862 dev_priv->drrs.connector = intel_connector;
4863
4864 mutex_init(&intel_dp->drrs_state.mutex);
4865
4f9db5b5
PB		 4866 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4867
4868 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4869 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4870 return downclock_mode;
4871}
4872
ed92f0b2 4873static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 4874 struct intel_connector *intel_connector)
ed92f0b2
PZ		 4875{
4876 struct drm_connector *connector = &intel_connector->base;
4877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4878 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4879 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4882 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4883 bool has_dpcd;
4884 struct drm_display_mode *scan;
4885 struct edid *edid;
6517d273 4886 enum pipe pipe = INVALID_PIPE;
ed92f0b2 4887
4f9db5b5
PB		 4888 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4889
ed92f0b2
PZ		 4890 if (!is_edp(intel_dp))
4891 return true;
4892
49e6bc51
VS		 4893 pps_lock(intel_dp);
4894 intel_edp_panel_vdd_sanitize(intel_dp);
4895 pps_unlock(intel_dp);
63635217 4896
ed92f0b2 4897 /* Cache DPCD and EDID for edp. */
ed92f0b2 4898 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 4899
4900 if (has_dpcd) {
4901 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4902 dev_priv->no_aux_handshake =
4903 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4904 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4905 } else {
4906 /* if this fails, presume the device is a ghost */
4907 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4908 return false;
4909 }
4910
4911 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4912 pps_lock(intel_dp);
36b5f425 4913 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 4914 pps_unlock(intel_dp);
ed92f0b2 4915
060c8778 4916 mutex_lock(&dev->mode_config.mutex);
0b99836f 4917 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4918 if (edid) {
4919 if (drm_add_edid_modes(connector, edid)) {
4920 drm_mode_connector_update_edid_property(connector,
4921 edid);
4922 drm_edid_to_eld(connector, edid);
4923 } else {
4924 kfree(edid);
4925 edid = ERR_PTR(-EINVAL);
4926 }
4927 } else {
4928 edid = ERR_PTR(-ENOENT);
4929 }
4930 intel_connector->edid = edid;
4931
4932 /* prefer fixed mode from EDID if available */
4933 list_for_each_entry(scan, &connector->probed_modes, head) {
4934 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4935 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4936 downclock_mode = intel_dp_drrs_init(
4937 intel_dig_port,
4938 intel_connector, fixed_mode);
ed92f0b2
PZ		 4939 break;
4940 }
4941 }
4942
4943 /* fallback to VBT if available for eDP */
4944 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4945 fixed_mode = drm_mode_duplicate(dev,
4946 dev_priv->vbt.lfp_lvds_vbt_mode);
4947 if (fixed_mode)
4948 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4949 }
060c8778 4950 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4951
01527b31
CT		 4952 if (IS_VALLEYVIEW(dev)) {
4953 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4954 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 4955
4956 /*
4957 * Figure out the current pipe for the initial backlight setup.
4958 * If the current pipe isn't valid, try the PPS pipe, and if that
4959 * fails just assume pipe A.
4960 */
4961 if (IS_CHERRYVIEW(dev))
4962 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4963 else
4964 pipe = PORT_TO_PIPE(intel_dp->DP);
4965
4966 if (pipe != PIPE_A && pipe != PIPE_B)
4967 pipe = intel_dp->pps_pipe;
4968
4969 if (pipe != PIPE_A && pipe != PIPE_B)
4970 pipe = PIPE_A;
4971
4972 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
4973 pipe_name(pipe));
01527b31
CT		 4974 }
4975
4f9db5b5 4976 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4977 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 4978 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 4979
4980 return true;
4981}
4982
16c25533 4983bool
f0fec3f2
PZ		 4984intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4985 struct intel_connector *intel_connector)
a4fc5ed6 4986{
f0fec3f2
PZ		 4987 struct drm_connector *connector = &intel_connector->base;
4988 struct intel_dp *intel_dp = &intel_dig_port->dp;
4989 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4990 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4991 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4992 enum port port = intel_dig_port->port;
0b99836f 4993 int type;
a4fc5ed6 4994
a4a5d2f8
VS		 4995 intel_dp->pps_pipe = INVALID_PIPE;
4996
ec5b01dd 4997 /* intel_dp vfuncs */
b6b5e383
DL		 4998 if (INTEL_INFO(dev)->gen >= 9)
4999 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5000 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5001 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5002 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5003 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5004 else if (HAS_PCH_SPLIT(dev))
5005 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5006 else
5007 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5008
b9ca5fad
DL		 5009 if (INTEL_INFO(dev)->gen >= 9)
5010 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5011 else
5012 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5013
0767935e
DV		 5014 /* Preserve the current hw state. */
5015 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5016 intel_dp->attached_connector = intel_connector;
3d3dc149 5017
3b32a35b 5018 if (intel_dp_is_edp(dev, port))
b329530c 5019 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5020 else
5021 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5022
f7d24902
ID		 5023 /*
5024 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5025 * for DP the encoder type can be set by the caller to
5026 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5027 */
5028 if (type == DRM_MODE_CONNECTOR_eDP)
5029 intel_encoder->type = INTEL_OUTPUT_EDP;
5030
c17ed5b5
VS		 5031 /* eDP only on port B and/or C on vlv/chv */
5032 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5033 port != PORT_B && port != PORT_C))
5034 return false;
5035
e7281eab
ID		 5036 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5037 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5038 port_name(port));
5039
b329530c 5040 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5041 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5042
a4fc5ed6
KP		 5043 connector->interlace_allowed = true;
5044 connector->doublescan_allowed = 0;
5045
f0fec3f2 5046 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5047 edp_panel_vdd_work);
a4fc5ed6 5048
df0e9248 5049 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5050 drm_connector_register(connector);
a4fc5ed6 5051
affa9354 5052 if (HAS_DDI(dev))
bcbc889b
PZ		 5053 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5054 else
5055 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5056 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5057
0b99836f 5058 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5059 switch (port) {
5060 case PORT_A:
1d843f9d 5061 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5062 break;
5063 case PORT_B:
1d843f9d 5064 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5065 break;
5066 case PORT_C:
1d843f9d 5067 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5068 break;
5069 case PORT_D:
1d843f9d 5070 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5071 break;
5072 default:
ad1c0b19 5073 BUG();
5eb08b69
ZW		 5074 }
5075
dada1a9f 5076 if (is_edp(intel_dp)) {
773538e8 5077 pps_lock(intel_dp);
1e74a324
VS		 5078 intel_dp_init_panel_power_timestamps(intel_dp);
5079 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5080 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5081 else
36b5f425 5082 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5083 pps_unlock(intel_dp);
dada1a9f 5084 }
0095e6dc 5085
9d1a1031 5086 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5087
0e32b39c
DA		 5088 /* init MST on ports that can support it */
5089 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5090 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5091 intel_dp_mst_encoder_init(intel_dig_port,
5092 intel_connector->base.base.id);
0e32b39c
DA		 5093 }
5094 }
5095
36b5f425 5096 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5097 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5098 if (is_edp(intel_dp)) {
5099 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5100 /*
5101 * vdd might still be enabled do to the delayed vdd off.
5102 * Make sure vdd is actually turned off here.
5103 */
773538e8 5104 pps_lock(intel_dp);
4be73780 5105 edp_panel_vdd_off_sync(intel_dp);
773538e8 5106 pps_unlock(intel_dp);
15b1d171 5107 }
34ea3d38 5108 drm_connector_unregister(connector);
b2f246a8 5109 drm_connector_cleanup(connector);
16c25533 5110 return false;
b2f246a8 5111 }
32f9d658 5112
f684960e
CW		 5113 intel_dp_add_properties(intel_dp, connector);
5114
a4fc5ed6
KP		 5115 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5116 * 0xd. Failure to do so will result in spurious interrupts being
5117 * generated on the port when a cable is not attached.
5118 */
5119 if (IS_G4X(dev) && !IS_GM45(dev)) {
5120 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5121 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5122 }
16c25533
PZ		 5123
5124 return true;
a4fc5ed6 5125}
f0fec3f2
PZ		 5126
5127void
5128intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5129{
13cf5504 5130 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5131 struct intel_digital_port *intel_dig_port;
5132 struct intel_encoder *intel_encoder;
5133 struct drm_encoder *encoder;
5134 struct intel_connector *intel_connector;
5135
b14c5679 5136 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5137 if (!intel_dig_port)
5138 return;
5139
b14c5679 5140 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5141 if (!intel_connector) {
5142 kfree(intel_dig_port);
5143 return;
5144 }
5145
5146 intel_encoder = &intel_dig_port->base;
5147 encoder = &intel_encoder->base;
5148
5149 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5150 DRM_MODE_ENCODER_TMDS);
5151
5bfe2ac0 5152 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5153 intel_encoder->disable = intel_disable_dp;
00c09d70 5154 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5155 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5156 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5157 if (IS_CHERRYVIEW(dev)) {
9197c88b 5158 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5159 intel_encoder->pre_enable = chv_pre_enable_dp;
5160 intel_encoder->enable = vlv_enable_dp;
580d3811 5161 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5162 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5163 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5164 intel_encoder->pre_enable = vlv_pre_enable_dp;
5165 intel_encoder->enable = vlv_enable_dp;
49277c31 5166 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5167 } else {
ecff4f3b
JN		 5168 intel_encoder->pre_enable = g4x_pre_enable_dp;
5169 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5170 if (INTEL_INFO(dev)->gen >= 5)
5171 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5172 }
f0fec3f2 5173
174edf1f 5174 intel_dig_port->port = port;
f0fec3f2
PZ		 5175 intel_dig_port->dp.output_reg = output_reg;
5176
00c09d70 5177 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5178 if (IS_CHERRYVIEW(dev)) {
5179 if (port == PORT_D)
5180 intel_encoder->crtc_mask = 1 << 2;
5181 else
5182 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5183 } else {
5184 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5185 }
bc079e8b 5186 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5187 intel_encoder->hot_plug = intel_dp_hot_plug;
5188
13cf5504
DA		 5189 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5190 dev_priv->hpd_irq_port[port] = intel_dig_port;
5191
15b1d171
PZ		 5192 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5193 drm_encoder_cleanup(encoder);
5194 kfree(intel_dig_port);
b2f246a8 5195 kfree(intel_connector);
15b1d171 5196 }
f0fec3f2 5197}
0e32b39c
DA		 5198
5199void intel_dp_mst_suspend(struct drm_device *dev)
5200{
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202 int i;
5203
5204 /* disable MST */
5205 for (i = 0; i < I915_MAX_PORTS; i++) {
5206 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5207 if (!intel_dig_port)
5208 continue;
5209
5210 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5211 if (!intel_dig_port->dp.can_mst)
5212 continue;
5213 if (intel_dig_port->dp.is_mst)
5214 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5215 }
5216 }
5217}
5218
5219void intel_dp_mst_resume(struct drm_device *dev)
5220{
5221 struct drm_i915_private *dev_priv = dev->dev_private;
5222 int i;
5223
5224 for (i = 0; i < I915_MAX_PORTS; i++) {
5225 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5226 if (!intel_dig_port)
5227 continue;
5228 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5229 int ret;
5230
5231 if (!intel_dig_port->dp.can_mst)
5232 continue;
5233
5234 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5235 if (ret != 0) {
5236 intel_dp_check_mst_status(&intel_dig_port->dp);
5237 }
5238 }
5239 }
5240}
Linux kernel - Deliverables
This page took 0.841 seconds and 5 git commands to generate.