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drm/i915: clean up VBT eDP link param decoding
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 108 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
109 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
111 max_link_bw = DP_LINK_BW_5_4;
112 else
113 max_link_bw = DP_LINK_BW_2_7;
d4eead50 114 break;
a4fc5ed6 115 default:
d4eead50
ID		 116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw);
a4fc5ed6
KP		 118 max_link_bw = DP_LINK_BW_1_62;
119 break;
120 }
121 return max_link_bw;
122}
123
eeb6324d
PZ		 124static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
125{
126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
127 struct drm_device *dev = intel_dig_port->base.base.dev;
128 u8 source_max, sink_max;
129
130 source_max = 4;
131 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
132 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
133 source_max = 2;
134
135 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 return min(source_max, sink_max);
138}
139
cd9dde44
AJ		 140/*
141 * The units on the numbers in the next two are... bizarre. Examples will
142 * make it clearer; this one parallels an example in the eDP spec.
143 *
144 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
145 *
146 * 270000 * 1 * 8 / 10 == 216000
147 *
148 * The actual data capacity of that configuration is 2.16Gbit/s, so the
149 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
150 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
151 * 119000. At 18bpp that's 2142000 kilobits per second.
152 *
153 * Thus the strange-looking division by 10 in intel_dp_link_required, to
154 * get the result in decakilobits instead of kilobits.
155 */
156
a4fc5ed6 157static int
c898261c 158intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 159{
cd9dde44 160 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 161}
162
fe27d53e
DA		 163static int
164intel_dp_max_data_rate(int max_link_clock, int max_lanes)
165{
166 return (max_link_clock * max_lanes * 8) / 10;
167}
168
c19de8eb 169static enum drm_mode_status
a4fc5ed6
KP		 170intel_dp_mode_valid(struct drm_connector *connector,
171 struct drm_display_mode *mode)
172{
df0e9248 173 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 174 struct intel_connector *intel_connector = to_intel_connector(connector);
175 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 176 int target_clock = mode->clock;
177 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 178
dd06f90e
JN		 179 if (is_edp(intel_dp) && fixed_mode) {
180 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 181 return MODE_PANEL;
182
dd06f90e 183 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 184 return MODE_PANEL;
03afc4a2
DV		 185
186 target_clock = fixed_mode->clock;
7de56f43
ZY		 187 }
188
36008365 189 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 190 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 191
192 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
193 mode_rate = intel_dp_link_required(target_clock, 18);
194
195 if (mode_rate > max_rate)
c4867936 196 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 197
198 if (mode->clock < 10000)
199 return MODE_CLOCK_LOW;
200
0af78a2b
DV		 201 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
202 return MODE_H_ILLEGAL;
203
a4fc5ed6
KP		 204 return MODE_OK;
205}
206
207static uint32_t
208pack_aux(uint8_t *src, int src_bytes)
209{
210 int i;
211 uint32_t v = 0;
212
213 if (src_bytes > 4)
214 src_bytes = 4;
215 for (i = 0; i < src_bytes; i++)
216 v |= ((uint32_t) src[i]) << ((3-i) * 8);
217 return v;
218}
219
220static void
221unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
222{
223 int i;
224 if (dst_bytes > 4)
225 dst_bytes = 4;
226 for (i = 0; i < dst_bytes; i++)
227 dst[i] = src >> ((3-i) * 8);
228}
229
fb0f8fbf
KP		 230/* hrawclock is 1/4 the FSB frequency */
231static int
232intel_hrawclk(struct drm_device *dev)
233{
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 uint32_t clkcfg;
236
9473c8f4
VP		 237 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
238 if (IS_VALLEYVIEW(dev))
239 return 200;
240
fb0f8fbf
KP		 241 clkcfg = I915_READ(CLKCFG);
242 switch (clkcfg & CLKCFG_FSB_MASK) {
243 case CLKCFG_FSB_400:
244 return 100;
245 case CLKCFG_FSB_533:
246 return 133;
247 case CLKCFG_FSB_667:
248 return 166;
249 case CLKCFG_FSB_800:
250 return 200;
251 case CLKCFG_FSB_1067:
252 return 266;
253 case CLKCFG_FSB_1333:
254 return 333;
255 /* these two are just a guess; one of them might be right */
256 case CLKCFG_FSB_1600:
257 case CLKCFG_FSB_1600_ALT:
258 return 400;
259 default:
260 return 133;
261 }
262}
263
bf13e81b
JN		 264static void
265intel_dp_init_panel_power_sequencer(struct drm_device *dev,
266 struct intel_dp *intel_dp,
267 struct edp_power_seq *out);
268static void
269intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
270 struct intel_dp *intel_dp,
271 struct edp_power_seq *out);
272
273static enum pipe
274vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
275{
276 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
277 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
278 struct drm_device *dev = intel_dig_port->base.base.dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 enum port port = intel_dig_port->port;
281 enum pipe pipe;
282
283 /* modeset should have pipe */
284 if (crtc)
285 return to_intel_crtc(crtc)->pipe;
286
287 /* init time, try to find a pipe with this port selected */
288 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
289 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
290 PANEL_PORT_SELECT_MASK;
291 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
292 return pipe;
293 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
294 return pipe;
295 }
296
297 /* shrug */
298 return PIPE_A;
299}
300
301static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
302{
303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
304
305 if (HAS_PCH_SPLIT(dev))
306 return PCH_PP_CONTROL;
307 else
308 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
309}
310
311static u32 _pp_stat_reg(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp_to_dev(intel_dp);
314
315 if (HAS_PCH_SPLIT(dev))
316 return PCH_PP_STATUS;
317 else
318 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
319}
320
4be73780 321static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 322{
30add22d 323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 324 struct drm_i915_private *dev_priv = dev->dev_private;
325
bf13e81b 326 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 327}
328
4be73780 329static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 330{
30add22d 331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 332 struct drm_i915_private *dev_priv = dev->dev_private;
333
efbc20ab
PZ		 334 return !dev_priv->pm.suspended &&
335 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 336}
337
9b984dae
KP		 338static void
339intel_dp_check_edp(struct intel_dp *intel_dp)
340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 342 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 343
9b984dae
KP		 344 if (!is_edp(intel_dp))
345 return;
453c5420 346
4be73780 347 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 348 WARN(1, "eDP powered off while attempting aux channel communication.\n");
349 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 350 I915_READ(_pp_stat_reg(intel_dp)),
351 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 352 }
353}
354
9ee32fea
DV		 355static uint32_t
356intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
357{
358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
359 struct drm_device *dev = intel_dig_port->base.base.dev;
360 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 361 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 362 uint32_t status;
363 bool done;
364
ef04f00d 365#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 366 if (has_aux_irq)
b18ac466 367 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 368 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 369 else
370 done = wait_for_atomic(C, 10) == 0;
371 if (!done)
372 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
373 has_aux_irq);
374#undef C
375
376 return status;
377}
378
ec5b01dd 379static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 380{
174edf1f
PZ		 381 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
382 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 383
ec5b01dd
DL		 384 /*
385 * The clock divider is based off the hrawclk, and would like to run at
386 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 387 */
ec5b01dd
DL		 388 return index ? 0 : intel_hrawclk(dev) / 2;
389}
390
391static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392{
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395
396 if (index)
397 return 0;
398
399 if (intel_dig_port->port == PORT_A) {
400 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 401 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 402 else
b84a1cf8 403 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 404 } else {
405 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
406 }
407}
408
409static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
410{
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 if (intel_dig_port->port == PORT_A) {
416 if (index)
417 return 0;
418 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 419 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
420 /* Workaround for non-ULT HSW */
bc86625a
CW		 421 switch (index) {
422 case 0: return 63;
423 case 1: return 72;
424 default: return 0;
425 }
ec5b01dd 426 } else {
bc86625a 427 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 428 }
b84a1cf8
RV		 429}
430
ec5b01dd
DL		 431static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 return index ? 0 : 100;
434}
435
5ed12a19
DL		 436static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
437 bool has_aux_irq,
438 int send_bytes,
439 uint32_t aux_clock_divider)
440{
441 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
442 struct drm_device *dev = intel_dig_port->base.base.dev;
443 uint32_t precharge, timeout;
444
445 if (IS_GEN6(dev))
446 precharge = 3;
447 else
448 precharge = 5;
449
450 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
451 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
452 else
453 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
454
455 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 456 DP_AUX_CH_CTL_DONE |
5ed12a19 457 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 458 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 459 timeout |
788d4433 460 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 461 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
462 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 463 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 464}
465
b84a1cf8
RV		 466static int
467intel_dp_aux_ch(struct intel_dp *intel_dp,
468 uint8_t *send, int send_bytes,
469 uint8_t *recv, int recv_size)
470{
471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
472 struct drm_device *dev = intel_dig_port->base.base.dev;
473 struct drm_i915_private *dev_priv = dev->dev_private;
474 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
475 uint32_t ch_data = ch_ctl + 4;
bc86625a 476 uint32_t aux_clock_divider;
b84a1cf8
RV		 477 int i, ret, recv_bytes;
478 uint32_t status;
5ed12a19 479 int try, clock = 0;
4e6b788c 480 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 481 bool vdd;
482
483 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 484
485 /* dp aux is extremely sensitive to irq latency, hence request the
486 * lowest possible wakeup latency and so prevent the cpu from going into
487 * deep sleep states.
488 */
489 pm_qos_update_request(&dev_priv->pm_qos, 0);
490
491 intel_dp_check_edp(intel_dp);
5eb08b69 492
c67a470b
PZ		 493 intel_aux_display_runtime_get(dev_priv);
494
11bee43e
JB		 495 /* Try to wait for any previous AUX channel activity */
496 for (try = 0; try < 3; try++) {
ef04f00d 497 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 498 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
499 break;
500 msleep(1);
501 }
502
503 if (try == 3) {
504 WARN(1, "dp_aux_ch not started status 0x%08x\n",
505 I915_READ(ch_ctl));
9ee32fea
DV		 506 ret = -EBUSY;
507 goto out;
4f7f7b7e
CW		 508 }
509
46a5ae9f
PZ		 510 /* Only 5 data registers! */
511 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
512 ret = -E2BIG;
513 goto out;
514 }
515
ec5b01dd 516 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 517 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
518 has_aux_irq,
519 send_bytes,
520 aux_clock_divider);
5ed12a19 521
bc86625a
CW		 522 /* Must try at least 3 times according to DP spec */
523 for (try = 0; try < 5; try++) {
524 /* Load the send data into the aux channel data registers */
525 for (i = 0; i < send_bytes; i += 4)
526 I915_WRITE(ch_data + i,
527 pack_aux(send + i, send_bytes - i));
528
529 /* Send the command and wait for it to complete */
5ed12a19 530 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 531
532 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
533
534 /* Clear done status and any errors */
535 I915_WRITE(ch_ctl,
536 status |
537 DP_AUX_CH_CTL_DONE |
538 DP_AUX_CH_CTL_TIME_OUT_ERROR |
539 DP_AUX_CH_CTL_RECEIVE_ERROR);
540
541 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
542 DP_AUX_CH_CTL_RECEIVE_ERROR))
543 continue;
544 if (status & DP_AUX_CH_CTL_DONE)
545 break;
546 }
4f7f7b7e 547 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 548 break;
549 }
550
a4fc5ed6 551 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 552 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -EBUSY;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Check for timeout or receive error.
558 * Timeouts occur when the sink is not connected
559 */
a5b3da54 560 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 561 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 562 ret = -EIO;
563 goto out;
a5b3da54 564 }
1ae8c0a5
KP		 565
566 /* Timeouts occur when the device isn't connected, so they're
567 * "normal" -- don't fill the kernel log with these */
a5b3da54 568 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 569 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 570 ret = -ETIMEDOUT;
571 goto out;
a4fc5ed6
KP		 572 }
573
574 /* Unload any bytes sent back from the other side */
575 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
576 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 577 if (recv_bytes > recv_size)
578 recv_bytes = recv_size;
0206e353 579
4f7f7b7e
CW		 580 for (i = 0; i < recv_bytes; i += 4)
581 unpack_aux(I915_READ(ch_data + i),
582 recv + i, recv_bytes - i);
a4fc5ed6 583
9ee32fea
DV		 584 ret = recv_bytes;
585out:
586 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 587 intel_aux_display_runtime_put(dev_priv);
9ee32fea 588
884f19e9
JN		 589 if (vdd)
590 edp_panel_vdd_off(intel_dp, false);
591
9ee32fea 592 return ret;
a4fc5ed6
KP		 593}
594
a6c8aff0
JN		 595#define BARE_ADDRESS_SIZE 3
596#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 597static ssize_t
598intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 599{
9d1a1031
JN		 600 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
601 uint8_t txbuf[20], rxbuf[20];
602 size_t txsize, rxsize;
a4fc5ed6 603 int ret;
a4fc5ed6 604
9d1a1031
JN		 605 txbuf[0] = msg->request << 4;
606 txbuf[1] = msg->address >> 8;
607 txbuf[2] = msg->address & 0xff;
608 txbuf[3] = msg->size - 1;
46a5ae9f 609
9d1a1031
JN		 610 switch (msg->request & ~DP_AUX_I2C_MOT) {
611 case DP_AUX_NATIVE_WRITE:
612 case DP_AUX_I2C_WRITE:
a6c8aff0 613 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 614 rxsize = 1;
f51a44b9 615
9d1a1031
JN		 616 if (WARN_ON(txsize > 20))
617 return -E2BIG;
a4fc5ed6 618
9d1a1031 619 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 620
9d1a1031
JN		 621 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
622 if (ret > 0) {
623 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 624
9d1a1031
JN		 625 /* Return payload size. */
626 ret = msg->size;
627 }
628 break;
46a5ae9f 629
9d1a1031
JN		 630 case DP_AUX_NATIVE_READ:
631 case DP_AUX_I2C_READ:
a6c8aff0 632 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 633 rxsize = msg->size + 1;
a4fc5ed6 634
9d1a1031
JN		 635 if (WARN_ON(rxsize > 20))
636 return -E2BIG;
a4fc5ed6 637
9d1a1031
JN		 638 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
639 if (ret > 0) {
640 msg->reply = rxbuf[0] >> 4;
641 /*
642 * Assume happy day, and copy the data. The caller is
643 * expected to check msg->reply before touching it.
644 *
645 * Return payload size.
646 */
647 ret--;
648 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 649 }
9d1a1031
JN		 650 break;
651
652 default:
653 ret = -EINVAL;
654 break;
a4fc5ed6 655 }
f51a44b9 656
9d1a1031 657 return ret;
a4fc5ed6
KP		 658}
659
9d1a1031
JN		 660static void
661intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
662{
663 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
665 enum port port = intel_dig_port->port;
0b99836f 666 const char *name = NULL;
ab2c0672
DA		 667 int ret;
668
33ad6626
JN		 669 switch (port) {
670 case PORT_A:
671 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 672 name = "DPDDC-A";
ab2c0672 673 break;
33ad6626
JN		 674 case PORT_B:
675 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 676 name = "DPDDC-B";
ab2c0672 677 break;
33ad6626
JN		 678 case PORT_C:
679 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 680 name = "DPDDC-C";
ab2c0672 681 break;
33ad6626
JN		 682 case PORT_D:
683 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 684 name = "DPDDC-D";
33ad6626
JN		 685 break;
686 default:
687 BUG();
ab2c0672
DA		 688 }
689
33ad6626
JN		 690 if (!HAS_DDI(dev))
691 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 692
0b99836f 693 intel_dp->aux.name = name;
9d1a1031
JN		 694 intel_dp->aux.dev = dev->dev;
695 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 696
0b99836f
JN		 697 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
698 connector->base.kdev->kobj.name);
8316f337 699
0b99836f
JN		 700 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
701 if (ret < 0) {
702 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
703 name, ret);
704 return;
ab2c0672 705 }
8a5e6aeb 706
0b99836f
JN		 707 ret = sysfs_create_link(&connector->base.kdev->kobj,
708 &intel_dp->aux.ddc.dev.kobj,
709 intel_dp->aux.ddc.dev.kobj.name);
710 if (ret < 0) {
711 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
712 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 713 }
a4fc5ed6
KP		 714}
715
80f65de3
ID		 716static void
717intel_dp_connector_unregister(struct intel_connector *intel_connector)
718{
719 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
720
721 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 722 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 723 intel_connector_unregister(intel_connector);
724}
725
c6bb3538
DV		 726static void
727intel_dp_set_clock(struct intel_encoder *encoder,
728 struct intel_crtc_config *pipe_config, int link_bw)
729{
730 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 731 const struct dp_link_dpll *divisor = NULL;
732 int i, count = 0;
c6bb3538
DV		 733
734 if (IS_G4X(dev)) {
9dd4ffdf
CML		 735 divisor = gen4_dpll;
736 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 737 } else if (IS_HASWELL(dev)) {
738 /* Haswell has special-purpose DP DDI clocks. */
739 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 740 divisor = pch_dpll;
741 count = ARRAY_SIZE(pch_dpll);
c6bb3538 742 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 743 divisor = vlv_dpll;
744 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 745 }
9dd4ffdf
CML		 746
747 if (divisor && count) {
748 for (i = 0; i < count; i++) {
749 if (link_bw == divisor[i].link_bw) {
750 pipe_config->dpll = divisor[i].dpll;
751 pipe_config->clock_set = true;
752 break;
753 }
754 }
c6bb3538
DV		 755 }
756}
757
00c09d70 758bool
5bfe2ac0
DV		 759intel_dp_compute_config(struct intel_encoder *encoder,
760 struct intel_crtc_config *pipe_config)
a4fc5ed6 761{
5bfe2ac0 762 struct drm_device *dev = encoder->base.dev;
36008365 763 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 764 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 765 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 766 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 767 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 768 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 769 int lane_count, clock;
eeb6324d 770 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6
TP		 771 /* Conveniently, the link BW constants become indices with a shift...*/
772 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 773 int bpp, mode_rate;
06ea66b6 774 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 775 int link_avail, link_clock;
a4fc5ed6 776
bc7d38a4 777 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 778 pipe_config->has_pch_encoder = true;
779
03afc4a2 780 pipe_config->has_dp_encoder = true;
a4fc5ed6 781
dd06f90e
JN		 782 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
783 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
784 adjusted_mode);
2dd24552
JB		 785 if (!HAS_PCH_SPLIT(dev))
786 intel_gmch_panel_fitting(intel_crtc, pipe_config,
787 intel_connector->panel.fitting_mode);
788 else
b074cec8
JB		 789 intel_pch_panel_fitting(intel_crtc, pipe_config,
790 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 791 }
792
cb1793ce 793 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 794 return false;
795
083f9560
DV		 796 DRM_DEBUG_KMS("DP link computation with max lane count %i "
797 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 798 max_lane_count, bws[max_clock],
799 adjusted_mode->crtc_clock);
083f9560 800
36008365
DV		 801 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
802 * bpc in between. */
3e7ca985 803 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 804 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
805 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 806 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
807 dev_priv->vbt.edp_bpp);
6da7f10d 808 bpp = dev_priv->vbt.edp_bpp;
7984211e 809 }
657445fe 810
36008365 811 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 812 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
813 bpp);
36008365 814
38aecea0
DV		 815 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
816 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 817 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
818 link_avail = intel_dp_max_data_rate(link_clock,
819 lane_count);
820
821 if (mode_rate <= link_avail) {
822 goto found;
823 }
824 }
825 }
826 }
c4867936 827
36008365 828 return false;
3685a8f3 829
36008365 830found:
55bc60db
VS		 831 if (intel_dp->color_range_auto) {
832 /*
833 * See:
834 * CEA-861-E - 5.1 Default Encoding Parameters
835 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
836 */
18316c8c 837 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 838 intel_dp->color_range = DP_COLOR_RANGE_16_235;
839 else
840 intel_dp->color_range = 0;
841 }
842
3685a8f3 843 if (intel_dp->color_range)
50f3b016 844 pipe_config->limited_color_range = true;
a4fc5ed6 845
36008365
DV		 846 intel_dp->link_bw = bws[clock];
847 intel_dp->lane_count = lane_count;
657445fe 848 pipe_config->pipe_bpp = bpp;
ff9a6750 849 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 850
36008365
DV		 851 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
852 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 853 pipe_config->port_clock, bpp);
36008365
DV		 854 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
855 mode_rate, link_avail);
a4fc5ed6 856
03afc4a2 857 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 858 adjusted_mode->crtc_clock,
859 pipe_config->port_clock,
03afc4a2 860 &pipe_config->dp_m_n);
9d1a455b 861
c6bb3538
DV		 862 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
863
03afc4a2 864 return true;
a4fc5ed6
KP		 865}
866
7c62a164 867static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 868{
7c62a164
DV		 869 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
870 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
871 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 872 struct drm_i915_private *dev_priv = dev->dev_private;
873 u32 dpa_ctl;
874
ff9a6750 875 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 876 dpa_ctl = I915_READ(DP_A);
877 dpa_ctl &= ~DP_PLL_FREQ_MASK;
878
ff9a6750 879 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 880 /* For a long time we've carried around a ILK-DevA w/a for the
881 * 160MHz clock. If we're really unlucky, it's still required.
882 */
883 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 884 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 885 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 886 } else {
887 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 888 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 889 }
1ce17038 890
ea9b6006
DV		 891 I915_WRITE(DP_A, dpa_ctl);
892
893 POSTING_READ(DP_A);
894 udelay(500);
895}
896
b934223d 897static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 898{
b934223d 899 struct drm_device *dev = encoder->base.dev;
417e822d 900 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 901 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 902 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 903 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
904 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 905
417e822d 906 /*
1a2eb460 907 * There are four kinds of DP registers:
417e822d
KP		 908 *
909 * IBX PCH
1a2eb460
KP		 910 * SNB CPU
911 * IVB CPU
417e822d
KP		 912 * CPT PCH
913 *
914 * IBX PCH and CPU are the same for almost everything,
915 * except that the CPU DP PLL is configured in this
916 * register
917 *
918 * CPT PCH is quite different, having many bits moved
919 * to the TRANS_DP_CTL register instead. That
920 * configuration happens (oddly) in ironlake_pch_enable
921 */
9c9e7927 922
417e822d
KP		 923 /* Preserve the BIOS-computed detected bit. This is
924 * supposed to be read-only.
925 */
926 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 927
417e822d 928 /* Handle DP bits in common between all three register formats */
417e822d 929 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 930 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 931
e0dac65e
WF		 932 if (intel_dp->has_audio) {
933 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 934 pipe_name(crtc->pipe));
ea5b213a 935 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 936 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 937 }
247d89f6 938
417e822d 939 /* Split out the IBX/CPU vs CPT settings */
32f9d658 940
bc7d38a4 941 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 942 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
943 intel_dp->DP |= DP_SYNC_HS_HIGH;
944 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
945 intel_dp->DP |= DP_SYNC_VS_HIGH;
946 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
947
6aba5b6c 948 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 949 intel_dp->DP |= DP_ENHANCED_FRAMING;
950
7c62a164 951 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 952 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 953 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 954 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 955
956 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
957 intel_dp->DP |= DP_SYNC_HS_HIGH;
958 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
959 intel_dp->DP |= DP_SYNC_VS_HIGH;
960 intel_dp->DP |= DP_LINK_TRAIN_OFF;
961
6aba5b6c 962 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 963 intel_dp->DP |= DP_ENHANCED_FRAMING;
964
7c62a164 965 if (crtc->pipe == 1)
417e822d 966 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 967 } else {
968 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 969 }
ea9b6006 970
bc7d38a4 971 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 972 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 973}
974
ffd6749d
PZ		 975#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
976#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 977
1a5ef5b7
PZ		 978#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
979#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 980
ffd6749d
PZ		 981#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
982#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 983
4be73780 984static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 985 u32 mask,
986 u32 value)
bd943159 987{
30add22d 988 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 989 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 990 u32 pp_stat_reg, pp_ctrl_reg;
991
bf13e81b
JN		 992 pp_stat_reg = _pp_stat_reg(intel_dp);
993 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 994
99ea7127 995 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 996 mask, value,
997 I915_READ(pp_stat_reg),
998 I915_READ(pp_ctrl_reg));
32ce697c 999
453c5420 1000 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1001 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1002 I915_READ(pp_stat_reg),
1003 I915_READ(pp_ctrl_reg));
32ce697c 1004 }
54c136d4
CW		 1005
1006 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1007}
32ce697c 1008
4be73780 1009static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1010{
1011 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1012 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1013}
1014
4be73780 1015static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1016{
1017 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1018 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1019}
1020
4be73780 1021static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1022{
1023 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1024
1025 /* When we disable the VDD override bit last we have to do the manual
1026 * wait. */
1027 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1028 intel_dp->panel_power_cycle_delay);
1029
4be73780 1030 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1031}
1032
4be73780 1033static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1034{
1035 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1036 intel_dp->backlight_on_delay);
1037}
1038
4be73780 1039static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1040{
1041 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1042 intel_dp->backlight_off_delay);
1043}
99ea7127 1044
832dd3c1
KP		 1045/* Read the current pp_control value, unlocking the register if it
1046 * is locked
1047 */
1048
453c5420 1049static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1050{
453c5420
JB		 1051 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1052 struct drm_i915_private *dev_priv = dev->dev_private;
1053 u32 control;
832dd3c1 1054
bf13e81b 1055 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1056 control &= ~PANEL_UNLOCK_MASK;
1057 control |= PANEL_UNLOCK_REGS;
1058 return control;
bd943159
KP		 1059}
1060
adddaaf4 1061static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1062{
30add22d 1063 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 u32 pp;
453c5420 1066 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1067 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1068
97af61f5 1069 if (!is_edp(intel_dp))
adddaaf4 1070 return false;
bd943159
KP		 1071
1072 intel_dp->want_panel_vdd = true;
99ea7127 1073
4be73780 1074 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1075 return need_to_disable;
b0665d57 1076
e9cb81a2
PZ		 1077 intel_runtime_pm_get(dev_priv);
1078
b0665d57 1079 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1080
4be73780
DV		 1081 if (!edp_have_panel_power(intel_dp))
1082 wait_panel_power_cycle(intel_dp);
99ea7127 1083
453c5420 1084 pp = ironlake_get_pp_control(intel_dp);
5d613501 1085 pp |= EDP_FORCE_VDD;
ebf33b18 1086
bf13e81b
JN		 1087 pp_stat_reg = _pp_stat_reg(intel_dp);
1088 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1089
1090 I915_WRITE(pp_ctrl_reg, pp);
1091 POSTING_READ(pp_ctrl_reg);
1092 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1093 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1094 /*
1095 * If the panel wasn't on, delay before accessing aux channel
1096 */
4be73780 1097 if (!edp_have_panel_power(intel_dp)) {
bd943159 1098 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1099 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1100 }
adddaaf4
JN		 1101
1102 return need_to_disable;
1103}
1104
b80d6c78 1105void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1106{
1107 if (is_edp(intel_dp)) {
1108 bool vdd = _edp_panel_vdd_on(intel_dp);
1109
1110 WARN(!vdd, "eDP VDD already requested on\n");
1111 }
5d613501
JB		 1112}
1113
4be73780 1114static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1115{
30add22d 1116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 u32 pp;
453c5420 1119 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1120
a0e99e68
DV		 1121 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1122
4be73780 1123 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1124 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1125
453c5420 1126 pp = ironlake_get_pp_control(intel_dp);
bd943159 1127 pp &= ~EDP_FORCE_VDD;
bd943159 1128
9f08ef59
PZ		 1129 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1130 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1131
1132 I915_WRITE(pp_ctrl_reg, pp);
1133 POSTING_READ(pp_ctrl_reg);
99ea7127 1134
453c5420
JB		 1135 /* Make sure sequencer is idle before allowing subsequent activity */
1136 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1137 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1138
1139 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1140 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1141
1142 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1143 }
1144}
5d613501 1145
4be73780 1146static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1147{
1148 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1149 struct intel_dp, panel_vdd_work);
30add22d 1150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1151
627f7675 1152 mutex_lock(&dev->mode_config.mutex);
4be73780 1153 edp_panel_vdd_off_sync(intel_dp);
627f7675 1154 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1155}
1156
4be73780 1157static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1158{
97af61f5
KP		 1159 if (!is_edp(intel_dp))
1160 return;
5d613501 1161
bd943159 1162 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1163
bd943159
KP		 1164 intel_dp->want_panel_vdd = false;
1165
1166 if (sync) {
4be73780 1167 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1168 } else {
1169 /*
1170 * Queue the timer to fire a long
1171 * time from now (relative to the power down delay)
1172 * to keep the panel power up across a sequence of operations
1173 */
1174 schedule_delayed_work(&intel_dp->panel_vdd_work,
1175 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1176 }
5d613501
JB		 1177}
1178
4be73780 1179void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1180{
30add22d 1181 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1182 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1183 u32 pp;
453c5420 1184 u32 pp_ctrl_reg;
9934c132 1185
97af61f5 1186 if (!is_edp(intel_dp))
bd943159 1187 return;
99ea7127
KP		 1188
1189 DRM_DEBUG_KMS("Turn eDP power on\n");
1190
4be73780 1191 if (edp_have_panel_power(intel_dp)) {
99ea7127 1192 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1193 return;
99ea7127 1194 }
9934c132 1195
4be73780 1196 wait_panel_power_cycle(intel_dp);
37c6c9b0 1197
bf13e81b 1198 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1199 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1200 if (IS_GEN5(dev)) {
1201 /* ILK workaround: disable reset around power sequence */
1202 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
05ce1a49 1205 }
37c6c9b0 1206
1c0ae80a 1207 pp |= POWER_TARGET_ON;
99ea7127
KP		 1208 if (!IS_GEN5(dev))
1209 pp |= PANEL_POWER_RESET;
1210
453c5420
JB		 1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
9934c132 1213
4be73780 1214 wait_panel_on(intel_dp);
dce56b3c 1215 intel_dp->last_power_on = jiffies;
9934c132 1216
05ce1a49
KP		 1217 if (IS_GEN5(dev)) {
1218 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1219 I915_WRITE(pp_ctrl_reg, pp);
1220 POSTING_READ(pp_ctrl_reg);
05ce1a49 1221 }
9934c132
JB		 1222}
1223
4be73780 1224void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1225{
30add22d 1226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1227 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1228 u32 pp;
453c5420 1229 u32 pp_ctrl_reg;
9934c132 1230
97af61f5
KP		 1231 if (!is_edp(intel_dp))
1232 return;
37c6c9b0 1233
99ea7127 1234 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1235
4be73780 1236 edp_wait_backlight_off(intel_dp);
dce56b3c 1237
24f3e092
JN		 1238 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1239
453c5420 1240 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1241 /* We need to switch off panel power _and_ force vdd, for otherwise some
1242 * panels get very unhappy and cease to work. */
b3064154
PJ		 1243 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1244 EDP_BLC_ENABLE);
453c5420 1245
bf13e81b 1246 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1247
849e39f5
PZ		 1248 intel_dp->want_panel_vdd = false;
1249
453c5420
JB		 1250 I915_WRITE(pp_ctrl_reg, pp);
1251 POSTING_READ(pp_ctrl_reg);
9934c132 1252
dce56b3c 1253 intel_dp->last_power_cycle = jiffies;
4be73780 1254 wait_panel_off(intel_dp);
849e39f5
PZ		 1255
1256 /* We got a reference when we enabled the VDD. */
1257 intel_runtime_pm_put(dev_priv);
9934c132
JB		 1258}
1259
4be73780 1260void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1261{
da63a9f2
PZ		 1262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1263 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1264 struct drm_i915_private *dev_priv = dev->dev_private;
1265 u32 pp;
453c5420 1266 u32 pp_ctrl_reg;
32f9d658 1267
f01eca2e
KP		 1268 if (!is_edp(intel_dp))
1269 return;
1270
28c97730 1271 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1272 /*
1273 * If we enable the backlight right away following a panel power
1274 * on, we may see slight flicker as the panel syncs with the eDP
1275 * link. So delay a bit to make sure the image is solid before
1276 * allowing it to appear.
1277 */
4be73780 1278 wait_backlight_on(intel_dp);
453c5420 1279 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1280 pp |= EDP_BLC_ENABLE;
453c5420 1281
bf13e81b 1282 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1283
1284 I915_WRITE(pp_ctrl_reg, pp);
1285 POSTING_READ(pp_ctrl_reg);
035aa3de 1286
752aa88a 1287 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1288}
1289
4be73780 1290void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1291{
30add22d 1292 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1293 struct drm_i915_private *dev_priv = dev->dev_private;
1294 u32 pp;
453c5420 1295 u32 pp_ctrl_reg;
32f9d658 1296
f01eca2e
KP		 1297 if (!is_edp(intel_dp))
1298 return;
1299
752aa88a 1300 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1301
28c97730 1302 DRM_DEBUG_KMS("\n");
453c5420 1303 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1304 pp &= ~EDP_BLC_ENABLE;
453c5420 1305
bf13e81b 1306 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1307
1308 I915_WRITE(pp_ctrl_reg, pp);
1309 POSTING_READ(pp_ctrl_reg);
dce56b3c 1310 intel_dp->last_backlight_off = jiffies;
32f9d658 1311}
a4fc5ed6 1312
2bd2ad64 1313static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1314{
da63a9f2
PZ		 1315 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1316 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1317 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 u32 dpa_ctl;
1320
2bd2ad64
DV		 1321 assert_pipe_disabled(dev_priv,
1322 to_intel_crtc(crtc)->pipe);
1323
d240f20f
JB		 1324 DRM_DEBUG_KMS("\n");
1325 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1326 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1327 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1328
1329 /* We don't adjust intel_dp->DP while tearing down the link, to
1330 * facilitate link retraining (e.g. after hotplug). Hence clear all
1331 * enable bits here to ensure that we don't enable too much. */
1332 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1333 intel_dp->DP |= DP_PLL_ENABLE;
1334 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1335 POSTING_READ(DP_A);
1336 udelay(200);
d240f20f
JB		 1337}
1338
2bd2ad64 1339static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1340{
da63a9f2
PZ		 1341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1342 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1343 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 u32 dpa_ctl;
1346
2bd2ad64
DV		 1347 assert_pipe_disabled(dev_priv,
1348 to_intel_crtc(crtc)->pipe);
1349
d240f20f 1350 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1351 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1352 "dp pll off, should be on\n");
1353 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1354
1355 /* We can't rely on the value tracked for the DP register in
1356 * intel_dp->DP because link_down must not change that (otherwise link
1357 * re-training will fail. */
298b0b39 1358 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1359 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1360 POSTING_READ(DP_A);
d240f20f
JB		 1361 udelay(200);
1362}
1363
c7ad3810 1364/* If the sink supports it, try to set the power state appropriately */
c19b0669 1365void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1366{
1367 int ret, i;
1368
1369 /* Should have a valid DPCD by this point */
1370 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1371 return;
1372
1373 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1374 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1375 DP_SET_POWER_D3);
c7ad3810
JB		 1376 if (ret != 1)
1377 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1378 } else {
1379 /*
1380 * When turning on, we need to retry for 1ms to give the sink
1381 * time to wake up.
1382 */
1383 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1384 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1385 DP_SET_POWER_D0);
c7ad3810
JB		 1386 if (ret == 1)
1387 break;
1388 msleep(1);
1389 }
1390 }
1391}
1392
19d8fe15
DV		 1393static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1394 enum pipe *pipe)
d240f20f 1395{
19d8fe15 1396 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1397 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1398 struct drm_device *dev = encoder->base.dev;
1399 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1400 enum intel_display_power_domain power_domain;
1401 u32 tmp;
1402
1403 power_domain = intel_display_port_power_domain(encoder);
1404 if (!intel_display_power_enabled(dev_priv, power_domain))
1405 return false;
1406
1407 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1408
1409 if (!(tmp & DP_PORT_EN))
1410 return false;
1411
bc7d38a4 1412 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1413 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1414 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1415 *pipe = PORT_TO_PIPE(tmp);
1416 } else {
1417 u32 trans_sel;
1418 u32 trans_dp;
1419 int i;
1420
1421 switch (intel_dp->output_reg) {
1422 case PCH_DP_B:
1423 trans_sel = TRANS_DP_PORT_SEL_B;
1424 break;
1425 case PCH_DP_C:
1426 trans_sel = TRANS_DP_PORT_SEL_C;
1427 break;
1428 case PCH_DP_D:
1429 trans_sel = TRANS_DP_PORT_SEL_D;
1430 break;
1431 default:
1432 return true;
1433 }
1434
1435 for_each_pipe(i) {
1436 trans_dp = I915_READ(TRANS_DP_CTL(i));
1437 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1438 *pipe = i;
1439 return true;
1440 }
1441 }
19d8fe15 1442
4a0833ec
DV		 1443 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1444 intel_dp->output_reg);
1445 }
d240f20f 1446
19d8fe15
DV		 1447 return true;
1448}
d240f20f 1449
045ac3b5
JB		 1450static void intel_dp_get_config(struct intel_encoder *encoder,
1451 struct intel_crtc_config *pipe_config)
1452{
1453 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1454 u32 tmp, flags = 0;
63000ef6
XZ		 1455 struct drm_device *dev = encoder->base.dev;
1456 struct drm_i915_private *dev_priv = dev->dev_private;
1457 enum port port = dp_to_dig_port(intel_dp)->port;
1458 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1459 int dotclock;
045ac3b5 1460
63000ef6
XZ		 1461 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1462 tmp = I915_READ(intel_dp->output_reg);
1463 if (tmp & DP_SYNC_HS_HIGH)
1464 flags |= DRM_MODE_FLAG_PHSYNC;
1465 else
1466 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1467
63000ef6
XZ		 1468 if (tmp & DP_SYNC_VS_HIGH)
1469 flags |= DRM_MODE_FLAG_PVSYNC;
1470 else
1471 flags |= DRM_MODE_FLAG_NVSYNC;
1472 } else {
1473 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1474 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1475 flags |= DRM_MODE_FLAG_PHSYNC;
1476 else
1477 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1478
63000ef6
XZ		 1479 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1480 flags |= DRM_MODE_FLAG_PVSYNC;
1481 else
1482 flags |= DRM_MODE_FLAG_NVSYNC;
1483 }
045ac3b5
JB		 1484
1485 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1486
eb14cb74
VS		 1487 pipe_config->has_dp_encoder = true;
1488
1489 intel_dp_get_m_n(crtc, pipe_config);
1490
18442d08 1491 if (port == PORT_A) {
f1f644dc
JB		 1492 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1493 pipe_config->port_clock = 162000;
1494 else
1495 pipe_config->port_clock = 270000;
1496 }
18442d08
VS		 1497
1498 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1499 &pipe_config->dp_m_n);
1500
1501 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1502 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1503
241bfc38 1504 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1505
c6cd2ee2
JN		 1506 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1507 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1508 /*
1509 * This is a big fat ugly hack.
1510 *
1511 * Some machines in UEFI boot mode provide us a VBT that has 18
1512 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1513 * unknown we fail to light up. Yet the same BIOS boots up with
1514 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1515 * max, not what it tells us to use.
1516 *
1517 * Note: This will still be broken if the eDP panel is not lit
1518 * up by the BIOS, and thus we can't get the mode at module
1519 * load.
1520 */
1521 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1522 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1523 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1524 }
045ac3b5
JB		 1525}
1526
a031d709 1527static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1528{
a031d709
RV		 1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530
1531 return dev_priv->psr.sink_support;
2293bb5c
SK		 1532}
1533
2b28bb1b
RV		 1534static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1535{
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
18b5992c 1538 if (!HAS_PSR(dev))
2b28bb1b
RV		 1539 return false;
1540
18b5992c 1541 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1542}
1543
1544static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1545 struct edp_vsc_psr *vsc_psr)
1546{
1547 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1548 struct drm_device *dev = dig_port->base.base.dev;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1551 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1552 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1553 uint32_t *data = (uint32_t *) vsc_psr;
1554 unsigned int i;
1555
1556 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1557 the video DIP being updated before program video DIP data buffer
1558 registers for DIP being updated. */
1559 I915_WRITE(ctl_reg, 0);
1560 POSTING_READ(ctl_reg);
1561
1562 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1563 if (i < sizeof(struct edp_vsc_psr))
1564 I915_WRITE(data_reg + i, *data++);
1565 else
1566 I915_WRITE(data_reg + i, 0);
1567 }
1568
1569 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1570 POSTING_READ(ctl_reg);
1571}
1572
1573static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1574{
1575 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 struct edp_vsc_psr psr_vsc;
1578
1579 if (intel_dp->psr_setup_done)
1580 return;
1581
1582 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1583 memset(&psr_vsc, 0, sizeof(psr_vsc));
1584 psr_vsc.sdp_header.HB0 = 0;
1585 psr_vsc.sdp_header.HB1 = 0x7;
1586 psr_vsc.sdp_header.HB2 = 0x2;
1587 psr_vsc.sdp_header.HB3 = 0x8;
1588 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1589
1590 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1591 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1592 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1593
1594 intel_dp->psr_setup_done = true;
1595}
1596
1597static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1598{
1599 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1600 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1601 uint32_t aux_clock_divider;
2b28bb1b
RV		 1602 int precharge = 0x3;
1603 int msg_size = 5; /* Header(4) + Message(1) */
1604
ec5b01dd
DL		 1605 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1606
2b28bb1b
RV		 1607 /* Enable PSR in sink */
1608 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1609 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1610 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1611 else
9d1a1031
JN		 1612 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1613 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1614
1615 /* Setup AUX registers */
18b5992c
BW		 1616 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1617 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1618 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1619 DP_AUX_CH_CTL_TIME_OUT_400us |
1620 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1621 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1622 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1623}
1624
1625static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1626{
1627 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 uint32_t max_sleep_time = 0x1f;
1630 uint32_t idle_frames = 1;
1631 uint32_t val = 0x0;
ed8546ac 1632 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1633
1634 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1635 val |= EDP_PSR_LINK_STANDBY;
1636 val |= EDP_PSR_TP2_TP3_TIME_0us;
1637 val |= EDP_PSR_TP1_TIME_0us;
1638 val |= EDP_PSR_SKIP_AUX_EXIT;
1639 } else
1640 val |= EDP_PSR_LINK_DISABLE;
1641
18b5992c 1642 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1643 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1644 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1645 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1646 EDP_PSR_ENABLE);
1647}
1648
3f51e471
RV		 1649static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1650{
1651 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1652 struct drm_device *dev = dig_port->base.base.dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 struct drm_crtc *crtc = dig_port->base.base.crtc;
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1656 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1657 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1658
a031d709
RV		 1659 dev_priv->psr.source_ok = false;
1660
18b5992c 1661 if (!HAS_PSR(dev)) {
3f51e471 1662 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1663 return false;
1664 }
1665
1666 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1667 (dig_port->port != PORT_A)) {
1668 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1669 return false;
1670 }
1671
d330a953 1672 if (!i915.enable_psr) {
105b7c11 1673 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1674 return false;
1675 }
1676
cd234b0b
CW		 1677 crtc = dig_port->base.base.crtc;
1678 if (crtc == NULL) {
1679 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1680 return false;
1681 }
1682
1683 intel_crtc = to_intel_crtc(crtc);
20ddf665 1684 if (!intel_crtc_active(crtc)) {
3f51e471 1685 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1686 return false;
1687 }
1688
f4510a27 1689 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1690 if (obj->tiling_mode != I915_TILING_X ||
1691 obj->fence_reg == I915_FENCE_REG_NONE) {
1692 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1693 return false;
1694 }
1695
1696 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1697 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1698 return false;
1699 }
1700
1701 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1702 S3D_ENABLE) {
1703 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1704 return false;
1705 }
1706
ca73b4f0 1707 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1708 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1709 return false;
1710 }
1711
a031d709 1712 dev_priv->psr.source_ok = true;
3f51e471
RV		 1713 return true;
1714}
1715
3d739d92 1716static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1717{
1718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1719
3f51e471
RV		 1720 if (!intel_edp_psr_match_conditions(intel_dp) ||
1721 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1722 return;
1723
1724 /* Setup PSR once */
1725 intel_edp_psr_setup(intel_dp);
1726
1727 /* Enable PSR on the panel */
1728 intel_edp_psr_enable_sink(intel_dp);
1729
1730 /* Enable PSR on the host */
1731 intel_edp_psr_enable_source(intel_dp);
1732}
1733
3d739d92
RV		 1734void intel_edp_psr_enable(struct intel_dp *intel_dp)
1735{
1736 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1737
1738 if (intel_edp_psr_match_conditions(intel_dp) &&
1739 !intel_edp_is_psr_enabled(dev))
1740 intel_edp_psr_do_enable(intel_dp);
1741}
1742
2b28bb1b
RV		 1743void intel_edp_psr_disable(struct intel_dp *intel_dp)
1744{
1745 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 if (!intel_edp_is_psr_enabled(dev))
1749 return;
1750
18b5992c
BW		 1751 I915_WRITE(EDP_PSR_CTL(dev),
1752 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1753
1754 /* Wait till PSR is idle */
18b5992c 1755 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1756 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1757 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1758}
1759
3d739d92
RV		 1760void intel_edp_psr_update(struct drm_device *dev)
1761{
1762 struct intel_encoder *encoder;
1763 struct intel_dp *intel_dp = NULL;
1764
1765 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1766 if (encoder->type == INTEL_OUTPUT_EDP) {
1767 intel_dp = enc_to_intel_dp(&encoder->base);
1768
a031d709 1769 if (!is_edp_psr(dev))
3d739d92
RV		 1770 return;
1771
1772 if (!intel_edp_psr_match_conditions(intel_dp))
1773 intel_edp_psr_disable(intel_dp);
1774 else
1775 if (!intel_edp_is_psr_enabled(dev))
1776 intel_edp_psr_do_enable(intel_dp);
1777 }
1778}
1779
e8cb4558 1780static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1781{
e8cb4558 1782 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1783 enum port port = dp_to_dig_port(intel_dp)->port;
1784 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1785
1786 /* Make sure the panel is off before trying to change the mode. But also
1787 * ensure that we have vdd while we switch off the panel. */
24f3e092 1788 intel_edp_panel_vdd_on(intel_dp);
4be73780 1789 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1790 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1791 intel_edp_panel_off(intel_dp);
3739850b
DV		 1792
1793 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1794 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1795 intel_dp_link_down(intel_dp);
d240f20f
JB		 1796}
1797
2bd2ad64 1798static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1799{
2bd2ad64 1800 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1801 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1802 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1803
982a3866 1804 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1805 intel_dp_link_down(intel_dp);
b2634017
JB		 1806 if (!IS_VALLEYVIEW(dev))
1807 ironlake_edp_pll_off(intel_dp);
3739850b 1808 }
2bd2ad64
DV		 1809}
1810
e8cb4558 1811static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1812{
e8cb4558
DV		 1813 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1814 struct drm_device *dev = encoder->base.dev;
1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1817
0c33d8d7
DV		 1818 if (WARN_ON(dp_reg & DP_PORT_EN))
1819 return;
5d613501 1820
24f3e092 1821 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1822 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1823 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1824 intel_edp_panel_on(intel_dp);
1825 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1826 intel_dp_complete_link_train(intel_dp);
3ab9c637 1827 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1828}
89b667f8 1829
ecff4f3b
JN		 1830static void g4x_enable_dp(struct intel_encoder *encoder)
1831{
828f5c6e
JN		 1832 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1833
ecff4f3b 1834 intel_enable_dp(encoder);
4be73780 1835 intel_edp_backlight_on(intel_dp);
ab1f90f9 1836}
89b667f8 1837
ab1f90f9
JN		 1838static void vlv_enable_dp(struct intel_encoder *encoder)
1839{
828f5c6e
JN		 1840 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1841
4be73780 1842 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1843}
1844
ecff4f3b 1845static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1846{
1847 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1848 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1849
1850 if (dport->port == PORT_A)
1851 ironlake_edp_pll_on(intel_dp);
1852}
1853
1854static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1855{
2bd2ad64 1856 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1857 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1858 struct drm_device *dev = encoder->base.dev;
89b667f8 1859 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1860 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1861 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1862 int pipe = intel_crtc->pipe;
bf13e81b 1863 struct edp_power_seq power_seq;
ab1f90f9 1864 u32 val;
a4fc5ed6 1865
ab1f90f9 1866 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1867
ab3c759a 1868 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1869 val = 0;
1870 if (pipe)
1871 val |= (1<<21);
1872 else
1873 val &= ~(1<<21);
1874 val |= 0x001000c4;
ab3c759a
CML		 1875 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1876 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1877 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1878
ab1f90f9
JN		 1879 mutex_unlock(&dev_priv->dpio_lock);
1880
2cac613b
ID		 1881 if (is_edp(intel_dp)) {
1882 /* init power sequencer on this pipe and port */
1883 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1884 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1885 &power_seq);
1886 }
bf13e81b 1887
ab1f90f9
JN		 1888 intel_enable_dp(encoder);
1889
e4607fcf 1890 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1891}
1892
ecff4f3b 1893static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1894{
1895 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1896 struct drm_device *dev = encoder->base.dev;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1898 struct intel_crtc *intel_crtc =
1899 to_intel_crtc(encoder->base.crtc);
e4607fcf 1900 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1901 int pipe = intel_crtc->pipe;
89b667f8 1902
89b667f8 1903 /* Program Tx lane resets to default */
0980a60f 1904 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1905 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1906 DPIO_PCS_TX_LANE2_RESET |
1907 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1908 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1909 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1910 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1911 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1912 DPIO_PCS_CLK_SOFT_RESET);
1913
1914 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1915 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1916 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1917 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1918 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1919}
1920
1921/*
df0c237d
JB		 1922 * Native read with retry for link status and receiver capability reads for
1923 * cases where the sink may still be asleep.
9d1a1031
JN		 1924 *
1925 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1926 * supposed to retry 3 times per the spec.
a4fc5ed6 1927 */
9d1a1031
JN		 1928static ssize_t
1929intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1930 void *buffer, size_t size)
a4fc5ed6 1931{
9d1a1031
JN		 1932 ssize_t ret;
1933 int i;
61da5fab 1934
61da5fab 1935 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1936 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1937 if (ret == size)
1938 return ret;
61da5fab
JB		 1939 msleep(1);
1940 }
a4fc5ed6 1941
9d1a1031 1942 return ret;
a4fc5ed6
KP		 1943}
1944
1945/*
1946 * Fetch AUX CH registers 0x202 - 0x207 which contain
1947 * link status information
1948 */
1949static bool
93f62dad 1950intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1951{
9d1a1031
JN		 1952 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1953 DP_LANE0_1_STATUS,
1954 link_status,
1955 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1956}
1957
a4fc5ed6
KP		 1958/*
1959 * These are source-specific values; current Intel hardware supports
1960 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1961 */
a4fc5ed6
KP		 1962
1963static uint8_t
1a2eb460 1964intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1965{
30add22d 1966 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1967 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1968
8f93f4f1 1969 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1970 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1971 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1972 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1973 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1974 return DP_TRAIN_VOLTAGE_SWING_1200;
1975 else
1976 return DP_TRAIN_VOLTAGE_SWING_800;
1977}
1978
1979static uint8_t
1980intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1981{
30add22d 1982 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1983 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1984
8f93f4f1
PZ		 1985 if (IS_BROADWELL(dev)) {
1986 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1987 case DP_TRAIN_VOLTAGE_SWING_400:
1988 case DP_TRAIN_VOLTAGE_SWING_600:
1989 return DP_TRAIN_PRE_EMPHASIS_6;
1990 case DP_TRAIN_VOLTAGE_SWING_800:
1991 return DP_TRAIN_PRE_EMPHASIS_3_5;
1992 case DP_TRAIN_VOLTAGE_SWING_1200:
1993 default:
1994 return DP_TRAIN_PRE_EMPHASIS_0;
1995 }
1996 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 1997 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1998 case DP_TRAIN_VOLTAGE_SWING_400:
1999 return DP_TRAIN_PRE_EMPHASIS_9_5;
2000 case DP_TRAIN_VOLTAGE_SWING_600:
2001 return DP_TRAIN_PRE_EMPHASIS_6;
2002 case DP_TRAIN_VOLTAGE_SWING_800:
2003 return DP_TRAIN_PRE_EMPHASIS_3_5;
2004 case DP_TRAIN_VOLTAGE_SWING_1200:
2005 default:
2006 return DP_TRAIN_PRE_EMPHASIS_0;
2007 }
e2fa6fba
P		 2008 } else if (IS_VALLEYVIEW(dev)) {
2009 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2010 case DP_TRAIN_VOLTAGE_SWING_400:
2011 return DP_TRAIN_PRE_EMPHASIS_9_5;
2012 case DP_TRAIN_VOLTAGE_SWING_600:
2013 return DP_TRAIN_PRE_EMPHASIS_6;
2014 case DP_TRAIN_VOLTAGE_SWING_800:
2015 return DP_TRAIN_PRE_EMPHASIS_3_5;
2016 case DP_TRAIN_VOLTAGE_SWING_1200:
2017 default:
2018 return DP_TRAIN_PRE_EMPHASIS_0;
2019 }
bc7d38a4 2020 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2021 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2022 case DP_TRAIN_VOLTAGE_SWING_400:
2023 return DP_TRAIN_PRE_EMPHASIS_6;
2024 case DP_TRAIN_VOLTAGE_SWING_600:
2025 case DP_TRAIN_VOLTAGE_SWING_800:
2026 return DP_TRAIN_PRE_EMPHASIS_3_5;
2027 default:
2028 return DP_TRAIN_PRE_EMPHASIS_0;
2029 }
2030 } else {
2031 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2032 case DP_TRAIN_VOLTAGE_SWING_400:
2033 return DP_TRAIN_PRE_EMPHASIS_6;
2034 case DP_TRAIN_VOLTAGE_SWING_600:
2035 return DP_TRAIN_PRE_EMPHASIS_6;
2036 case DP_TRAIN_VOLTAGE_SWING_800:
2037 return DP_TRAIN_PRE_EMPHASIS_3_5;
2038 case DP_TRAIN_VOLTAGE_SWING_1200:
2039 default:
2040 return DP_TRAIN_PRE_EMPHASIS_0;
2041 }
a4fc5ed6
KP		 2042 }
2043}
2044
e2fa6fba
P		 2045static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2046{
2047 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2048 struct drm_i915_private *dev_priv = dev->dev_private;
2049 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2050 struct intel_crtc *intel_crtc =
2051 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2052 unsigned long demph_reg_value, preemph_reg_value,
2053 uniqtranscale_reg_value;
2054 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2055 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2056 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2057
2058 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2059 case DP_TRAIN_PRE_EMPHASIS_0:
2060 preemph_reg_value = 0x0004000;
2061 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2062 case DP_TRAIN_VOLTAGE_SWING_400:
2063 demph_reg_value = 0x2B405555;
2064 uniqtranscale_reg_value = 0x552AB83A;
2065 break;
2066 case DP_TRAIN_VOLTAGE_SWING_600:
2067 demph_reg_value = 0x2B404040;
2068 uniqtranscale_reg_value = 0x5548B83A;
2069 break;
2070 case DP_TRAIN_VOLTAGE_SWING_800:
2071 demph_reg_value = 0x2B245555;
2072 uniqtranscale_reg_value = 0x5560B83A;
2073 break;
2074 case DP_TRAIN_VOLTAGE_SWING_1200:
2075 demph_reg_value = 0x2B405555;
2076 uniqtranscale_reg_value = 0x5598DA3A;
2077 break;
2078 default:
2079 return 0;
2080 }
2081 break;
2082 case DP_TRAIN_PRE_EMPHASIS_3_5:
2083 preemph_reg_value = 0x0002000;
2084 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2085 case DP_TRAIN_VOLTAGE_SWING_400:
2086 demph_reg_value = 0x2B404040;
2087 uniqtranscale_reg_value = 0x5552B83A;
2088 break;
2089 case DP_TRAIN_VOLTAGE_SWING_600:
2090 demph_reg_value = 0x2B404848;
2091 uniqtranscale_reg_value = 0x5580B83A;
2092 break;
2093 case DP_TRAIN_VOLTAGE_SWING_800:
2094 demph_reg_value = 0x2B404040;
2095 uniqtranscale_reg_value = 0x55ADDA3A;
2096 break;
2097 default:
2098 return 0;
2099 }
2100 break;
2101 case DP_TRAIN_PRE_EMPHASIS_6:
2102 preemph_reg_value = 0x0000000;
2103 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2104 case DP_TRAIN_VOLTAGE_SWING_400:
2105 demph_reg_value = 0x2B305555;
2106 uniqtranscale_reg_value = 0x5570B83A;
2107 break;
2108 case DP_TRAIN_VOLTAGE_SWING_600:
2109 demph_reg_value = 0x2B2B4040;
2110 uniqtranscale_reg_value = 0x55ADDA3A;
2111 break;
2112 default:
2113 return 0;
2114 }
2115 break;
2116 case DP_TRAIN_PRE_EMPHASIS_9_5:
2117 preemph_reg_value = 0x0006000;
2118 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2119 case DP_TRAIN_VOLTAGE_SWING_400:
2120 demph_reg_value = 0x1B405555;
2121 uniqtranscale_reg_value = 0x55ADDA3A;
2122 break;
2123 default:
2124 return 0;
2125 }
2126 break;
2127 default:
2128 return 0;
2129 }
2130
0980a60f 2131 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2132 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2135 uniqtranscale_reg_value);
ab3c759a
CML		 2136 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2137 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2138 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2139 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2140 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2141
2142 return 0;
2143}
2144
a4fc5ed6 2145static void
0301b3ac
JN		 2146intel_get_adjust_train(struct intel_dp *intel_dp,
2147 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2148{
2149 uint8_t v = 0;
2150 uint8_t p = 0;
2151 int lane;
1a2eb460
KP		 2152 uint8_t voltage_max;
2153 uint8_t preemph_max;
a4fc5ed6 2154
33a34e4e 2155 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2156 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2157 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2158
2159 if (this_v > v)
2160 v = this_v;
2161 if (this_p > p)
2162 p = this_p;
2163 }
2164
1a2eb460 2165 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2166 if (v >= voltage_max)
2167 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2168
1a2eb460
KP		 2169 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2170 if (p >= preemph_max)
2171 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2172
2173 for (lane = 0; lane < 4; lane++)
33a34e4e 2174 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2175}
2176
2177static uint32_t
f0a3424e 2178intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2179{
3cf2efb1 2180 uint32_t signal_levels = 0;
a4fc5ed6 2181
3cf2efb1 2182 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2183 case DP_TRAIN_VOLTAGE_SWING_400:
2184 default:
2185 signal_levels |= DP_VOLTAGE_0_4;
2186 break;
2187 case DP_TRAIN_VOLTAGE_SWING_600:
2188 signal_levels |= DP_VOLTAGE_0_6;
2189 break;
2190 case DP_TRAIN_VOLTAGE_SWING_800:
2191 signal_levels |= DP_VOLTAGE_0_8;
2192 break;
2193 case DP_TRAIN_VOLTAGE_SWING_1200:
2194 signal_levels |= DP_VOLTAGE_1_2;
2195 break;
2196 }
3cf2efb1 2197 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2198 case DP_TRAIN_PRE_EMPHASIS_0:
2199 default:
2200 signal_levels |= DP_PRE_EMPHASIS_0;
2201 break;
2202 case DP_TRAIN_PRE_EMPHASIS_3_5:
2203 signal_levels |= DP_PRE_EMPHASIS_3_5;
2204 break;
2205 case DP_TRAIN_PRE_EMPHASIS_6:
2206 signal_levels |= DP_PRE_EMPHASIS_6;
2207 break;
2208 case DP_TRAIN_PRE_EMPHASIS_9_5:
2209 signal_levels |= DP_PRE_EMPHASIS_9_5;
2210 break;
2211 }
2212 return signal_levels;
2213}
2214
e3421a18
ZW		 2215/* Gen6's DP voltage swing and pre-emphasis control */
2216static uint32_t
2217intel_gen6_edp_signal_levels(uint8_t train_set)
2218{
3c5a62b5
YL		 2219 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2220 DP_TRAIN_PRE_EMPHASIS_MASK);
2221 switch (signal_levels) {
e3421a18 2222 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2223 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2224 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2225 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2226 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2227 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2229 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2230 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2231 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2232 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2233 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2234 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2235 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2236 default:
3c5a62b5
YL		 2237 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2238 "0x%x\n", signal_levels);
2239 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2240 }
2241}
2242
1a2eb460
KP		 2243/* Gen7's DP voltage swing and pre-emphasis control */
2244static uint32_t
2245intel_gen7_edp_signal_levels(uint8_t train_set)
2246{
2247 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2248 DP_TRAIN_PRE_EMPHASIS_MASK);
2249 switch (signal_levels) {
2250 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2251 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2252 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2253 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2254 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2255 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2256
2257 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2258 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2259 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2260 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2261
2262 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2263 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2264 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2265 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2266
2267 default:
2268 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2269 "0x%x\n", signal_levels);
2270 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2271 }
2272}
2273
d6c0d722
PZ		 2274/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2275static uint32_t
f0a3424e 2276intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2277{
d6c0d722
PZ		 2278 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2279 DP_TRAIN_PRE_EMPHASIS_MASK);
2280 switch (signal_levels) {
2281 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2282 return DDI_BUF_EMP_400MV_0DB_HSW;
2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2284 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2285 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2286 return DDI_BUF_EMP_400MV_6DB_HSW;
2287 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2288 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2289
d6c0d722
PZ		 2290 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2291 return DDI_BUF_EMP_600MV_0DB_HSW;
2292 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2293 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2294 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2295 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2296
d6c0d722
PZ		 2297 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2298 return DDI_BUF_EMP_800MV_0DB_HSW;
2299 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2300 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2301 default:
2302 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2303 "0x%x\n", signal_levels);
2304 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2305 }
a4fc5ed6
KP		 2306}
2307
8f93f4f1
PZ		 2308static uint32_t
2309intel_bdw_signal_levels(uint8_t train_set)
2310{
2311 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2312 DP_TRAIN_PRE_EMPHASIS_MASK);
2313 switch (signal_levels) {
2314 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2315 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2316 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2317 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2318 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2319 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2320
2321 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2322 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2323 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2324 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2325 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2326 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2327
2328 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2329 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2330 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2331 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2332
2333 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2334 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2335
2336 default:
2337 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2338 "0x%x\n", signal_levels);
2339 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2340 }
2341}
2342
f0a3424e
PZ		 2343/* Properly updates "DP" with the correct signal levels. */
2344static void
2345intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2346{
2347 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2348 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2349 struct drm_device *dev = intel_dig_port->base.base.dev;
2350 uint32_t signal_levels, mask;
2351 uint8_t train_set = intel_dp->train_set[0];
2352
8f93f4f1
PZ		 2353 if (IS_BROADWELL(dev)) {
2354 signal_levels = intel_bdw_signal_levels(train_set);
2355 mask = DDI_BUF_EMP_MASK;
2356 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2357 signal_levels = intel_hsw_signal_levels(train_set);
2358 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2359 } else if (IS_VALLEYVIEW(dev)) {
2360 signal_levels = intel_vlv_signal_levels(intel_dp);
2361 mask = 0;
bc7d38a4 2362 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2363 signal_levels = intel_gen7_edp_signal_levels(train_set);
2364 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2365 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2366 signal_levels = intel_gen6_edp_signal_levels(train_set);
2367 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2368 } else {
2369 signal_levels = intel_gen4_signal_levels(train_set);
2370 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2371 }
2372
2373 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2374
2375 *DP = (*DP & ~mask) | signal_levels;
2376}
2377
a4fc5ed6 2378static bool
ea5b213a 2379intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2380 uint32_t *DP,
58e10eb9 2381 uint8_t dp_train_pat)
a4fc5ed6 2382{
174edf1f
PZ		 2383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2384 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2385 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2386 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2387 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2388 int ret, len;
a4fc5ed6 2389
22b8bf17 2390 if (HAS_DDI(dev)) {
3ab9c637 2391 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2392
2393 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2394 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2395 else
2396 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2397
2398 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2399 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2400 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2401 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2402
2403 break;
2404 case DP_TRAINING_PATTERN_1:
2405 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2406 break;
2407 case DP_TRAINING_PATTERN_2:
2408 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2409 break;
2410 case DP_TRAINING_PATTERN_3:
2411 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2412 break;
2413 }
174edf1f 2414 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2415
bc7d38a4 2416 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2417 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2418
2419 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2420 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2421 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2422 break;
2423 case DP_TRAINING_PATTERN_1:
70aff66c 2424 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2425 break;
2426 case DP_TRAINING_PATTERN_2:
70aff66c 2427 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2428 break;
2429 case DP_TRAINING_PATTERN_3:
2430 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2431 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2432 break;
2433 }
2434
2435 } else {
70aff66c 2436 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2437
2438 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2439 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2440 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2441 break;
2442 case DP_TRAINING_PATTERN_1:
70aff66c 2443 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2444 break;
2445 case DP_TRAINING_PATTERN_2:
70aff66c 2446 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2447 break;
2448 case DP_TRAINING_PATTERN_3:
2449 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2450 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2451 break;
2452 }
2453 }
2454
70aff66c 2455 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2456 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2457
2cdfe6c8
JN		 2458 buf[0] = dp_train_pat;
2459 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2460 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2461 /* don't write DP_TRAINING_LANEx_SET on disable */
2462 len = 1;
2463 } else {
2464 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2465 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2466 len = intel_dp->lane_count + 1;
47ea7542 2467 }
a4fc5ed6 2468
9d1a1031
JN		 2469 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2470 buf, len);
2cdfe6c8
JN		 2471
2472 return ret == len;
a4fc5ed6
KP		 2473}
2474
70aff66c
JN		 2475static bool
2476intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2477 uint8_t dp_train_pat)
2478{
953d22e8 2479 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2480 intel_dp_set_signal_levels(intel_dp, DP);
2481 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2482}
2483
2484static bool
2485intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2486 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2487{
2488 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2489 struct drm_device *dev = intel_dig_port->base.base.dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 int ret;
2492
2493 intel_get_adjust_train(intel_dp, link_status);
2494 intel_dp_set_signal_levels(intel_dp, DP);
2495
2496 I915_WRITE(intel_dp->output_reg, *DP);
2497 POSTING_READ(intel_dp->output_reg);
2498
9d1a1031
JN		 2499 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2500 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2501
2502 return ret == intel_dp->lane_count;
2503}
2504
3ab9c637
ID		 2505static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2506{
2507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2508 struct drm_device *dev = intel_dig_port->base.base.dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 enum port port = intel_dig_port->port;
2511 uint32_t val;
2512
2513 if (!HAS_DDI(dev))
2514 return;
2515
2516 val = I915_READ(DP_TP_CTL(port));
2517 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2518 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2519 I915_WRITE(DP_TP_CTL(port), val);
2520
2521 /*
2522 * On PORT_A we can have only eDP in SST mode. There the only reason
2523 * we need to set idle transmission mode is to work around a HW issue
2524 * where we enable the pipe while not in idle link-training mode.
2525 * In this case there is requirement to wait for a minimum number of
2526 * idle patterns to be sent.
2527 */
2528 if (port == PORT_A)
2529 return;
2530
2531 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2532 1))
2533 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2534}
2535
33a34e4e 2536/* Enable corresponding port and start training pattern 1 */
c19b0669 2537void
33a34e4e 2538intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2539{
da63a9f2 2540 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2541 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2542 int i;
2543 uint8_t voltage;
cdb0e95b 2544 int voltage_tries, loop_tries;
ea5b213a 2545 uint32_t DP = intel_dp->DP;
6aba5b6c 2546 uint8_t link_config[2];
a4fc5ed6 2547
affa9354 2548 if (HAS_DDI(dev))
c19b0669
PZ		 2549 intel_ddi_prepare_link_retrain(encoder);
2550
3cf2efb1 2551 /* Write the link configuration data */
6aba5b6c
JN		 2552 link_config[0] = intel_dp->link_bw;
2553 link_config[1] = intel_dp->lane_count;
2554 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2555 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2556 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2557
2558 link_config[0] = 0;
2559 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2560 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2561
2562 DP |= DP_PORT_EN;
1a2eb460 2563
70aff66c
JN		 2564 /* clock recovery */
2565 if (!intel_dp_reset_link_train(intel_dp, &DP,
2566 DP_TRAINING_PATTERN_1 |
2567 DP_LINK_SCRAMBLING_DISABLE)) {
2568 DRM_ERROR("failed to enable link training\n");
2569 return;
2570 }
2571
a4fc5ed6 2572 voltage = 0xff;
cdb0e95b
KP		 2573 voltage_tries = 0;
2574 loop_tries = 0;
a4fc5ed6 2575 for (;;) {
70aff66c 2576 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2577
a7c9655f 2578 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2579 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2580 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2581 break;
93f62dad 2582 }
a4fc5ed6 2583
01916270 2584 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2585 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2586 break;
2587 }
2588
2589 /* Check to see if we've tried the max voltage */
2590 for (i = 0; i < intel_dp->lane_count; i++)
2591 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2592 break;
3b4f819d 2593 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2594 ++loop_tries;
2595 if (loop_tries == 5) {
3def84b3 2596 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2597 break;
2598 }
70aff66c
JN		 2599 intel_dp_reset_link_train(intel_dp, &DP,
2600 DP_TRAINING_PATTERN_1 |
2601 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2602 voltage_tries = 0;
2603 continue;
2604 }
a4fc5ed6 2605
3cf2efb1 2606 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2607 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2608 ++voltage_tries;
b06fbda3 2609 if (voltage_tries == 5) {
3def84b3 2610 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2611 break;
2612 }
2613 } else
2614 voltage_tries = 0;
2615 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2616
70aff66c
JN		 2617 /* Update training set as requested by target */
2618 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2619 DRM_ERROR("failed to update link training\n");
2620 break;
2621 }
a4fc5ed6
KP		 2622 }
2623
33a34e4e
JB		 2624 intel_dp->DP = DP;
2625}
2626
c19b0669 2627void
33a34e4e
JB		 2628intel_dp_complete_link_train(struct intel_dp *intel_dp)
2629{
33a34e4e 2630 bool channel_eq = false;
37f80975 2631 int tries, cr_tries;
33a34e4e 2632 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2633 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2634
2635 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2636 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2637 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2638
a4fc5ed6 2639 /* channel equalization */
70aff66c 2640 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2641 training_pattern |
70aff66c
JN		 2642 DP_LINK_SCRAMBLING_DISABLE)) {
2643 DRM_ERROR("failed to start channel equalization\n");
2644 return;
2645 }
2646
a4fc5ed6 2647 tries = 0;
37f80975 2648 cr_tries = 0;
a4fc5ed6
KP		 2649 channel_eq = false;
2650 for (;;) {
70aff66c 2651 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2652
37f80975
JB		 2653 if (cr_tries > 5) {
2654 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2655 break;
2656 }
2657
a7c9655f 2658 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2659 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2660 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2661 break;
70aff66c 2662 }
a4fc5ed6 2663
37f80975 2664 /* Make sure clock is still ok */
01916270 2665 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2666 intel_dp_start_link_train(intel_dp);
70aff66c 2667 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2668 training_pattern |
70aff66c 2669 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2670 cr_tries++;
2671 continue;
2672 }
2673
1ffdff13 2674 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2675 channel_eq = true;
2676 break;
2677 }
a4fc5ed6 2678
37f80975
JB		 2679 /* Try 5 times, then try clock recovery if that fails */
2680 if (tries > 5) {
2681 intel_dp_link_down(intel_dp);
2682 intel_dp_start_link_train(intel_dp);
70aff66c 2683 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2684 training_pattern |
70aff66c 2685 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2686 tries = 0;
2687 cr_tries++;
2688 continue;
2689 }
a4fc5ed6 2690
70aff66c
JN		 2691 /* Update training set as requested by target */
2692 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2693 DRM_ERROR("failed to update link training\n");
2694 break;
2695 }
3cf2efb1 2696 ++tries;
869184a6 2697 }
3cf2efb1 2698
3ab9c637
ID		 2699 intel_dp_set_idle_link_train(intel_dp);
2700
2701 intel_dp->DP = DP;
2702
d6c0d722 2703 if (channel_eq)
07f42258 2704 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2705
3ab9c637
ID		 2706}
2707
2708void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2709{
70aff66c 2710 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2711 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2712}
2713
2714static void
ea5b213a 2715intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2716{
da63a9f2 2717 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2718 enum port port = intel_dig_port->port;
da63a9f2 2719 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2720 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2721 struct intel_crtc *intel_crtc =
2722 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2723 uint32_t DP = intel_dp->DP;
a4fc5ed6 2724
c19b0669
PZ		 2725 /*
2726 * DDI code has a strict mode set sequence and we should try to respect
2727 * it, otherwise we might hang the machine in many different ways. So we
2728 * really should be disabling the port only on a complete crtc_disable
2729 * sequence. This function is just called under two conditions on DDI
2730 * code:
2731 * - Link train failed while doing crtc_enable, and on this case we
2732 * really should respect the mode set sequence and wait for a
2733 * crtc_disable.
2734 * - Someone turned the monitor off and intel_dp_check_link_status
2735 * called us. We don't need to disable the whole port on this case, so
2736 * when someone turns the monitor on again,
2737 * intel_ddi_prepare_link_retrain will take care of redoing the link
2738 * train.
2739 */
affa9354 2740 if (HAS_DDI(dev))
c19b0669
PZ		 2741 return;
2742
0c33d8d7 2743 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2744 return;
2745
28c97730 2746 DRM_DEBUG_KMS("\n");
32f9d658 2747
bc7d38a4 2748 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2749 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2750 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2751 } else {
2752 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2753 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2754 }
fe255d00 2755 POSTING_READ(intel_dp->output_reg);
5eb08b69 2756
ab527efc
DV		 2757 /* We don't really know why we're doing this */
2758 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2759
493a7081 2760 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2761 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2762 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2763
5bddd17f
EA		 2764 /* Hardware workaround: leaving our transcoder select
2765 * set to transcoder B while it's off will prevent the
2766 * corresponding HDMI output on transcoder A.
2767 *
2768 * Combine this with another hardware workaround:
2769 * transcoder select bit can only be cleared while the
2770 * port is enabled.
2771 */
2772 DP &= ~DP_PIPEB_SELECT;
2773 I915_WRITE(intel_dp->output_reg, DP);
2774
2775 /* Changes to enable or select take place the vblank
2776 * after being written.
2777 */
ff50afe9
DV		 2778 if (WARN_ON(crtc == NULL)) {
2779 /* We should never try to disable a port without a crtc
2780 * attached. For paranoia keep the code around for a
2781 * bit. */
31acbcc4
CW		 2782 POSTING_READ(intel_dp->output_reg);
2783 msleep(50);
2784 } else
ab527efc 2785 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2786 }
2787
832afda6 2788 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2789 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2790 POSTING_READ(intel_dp->output_reg);
f01eca2e 2791 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2792}
2793
26d61aad
KP		 2794static bool
2795intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2796{
a031d709
RV		 2797 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2798 struct drm_device *dev = dig_port->base.base.dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800
577c7a50
DL		 2801 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2802
9d1a1031
JN		 2803 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2804 sizeof(intel_dp->dpcd)) < 0)
edb39244 2805 return false; /* aux transfer failed */
92fd8fd1 2806
577c7a50
DL		 2807 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2808 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2809 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2810
edb39244
AJ		 2811 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2812 return false; /* DPCD not present */
2813
2293bb5c
SK		 2814 /* Check if the panel supports PSR */
2815 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2816 if (is_edp(intel_dp)) {
9d1a1031
JN		 2817 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2818 intel_dp->psr_dpcd,
2819 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2820 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2821 dev_priv->psr.sink_support = true;
50003939 2822 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2823 }
50003939
JN		 2824 }
2825
06ea66b6
TP		 2826 /* Training Pattern 3 support */
2827 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2828 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2829 intel_dp->use_tps3 = true;
2830 DRM_DEBUG_KMS("Displayport TPS3 supported");
2831 } else
2832 intel_dp->use_tps3 = false;
2833
edb39244
AJ		 2834 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2835 DP_DWN_STRM_PORT_PRESENT))
2836 return true; /* native DP sink */
2837
2838 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2839 return true; /* no per-port downstream info */
2840
9d1a1031
JN		 2841 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2842 intel_dp->downstream_ports,
2843 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2844 return false; /* downstream port status fetch failed */
2845
2846 return true;
92fd8fd1
KP		 2847}
2848
0d198328
AJ		 2849static void
2850intel_dp_probe_oui(struct intel_dp *intel_dp)
2851{
2852 u8 buf[3];
2853
2854 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2855 return;
2856
24f3e092 2857 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2858
9d1a1031 2859 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2860 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2861 buf[0], buf[1], buf[2]);
2862
9d1a1031 2863 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2864 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2865 buf[0], buf[1], buf[2]);
351cfc34 2866
4be73780 2867 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2868}
2869
d2e216d0
RV		 2870int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2871{
2872 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2873 struct drm_device *dev = intel_dig_port->base.base.dev;
2874 struct intel_crtc *intel_crtc =
2875 to_intel_crtc(intel_dig_port->base.base.crtc);
2876 u8 buf[1];
2877
9d1a1031 2878 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2879 return -EAGAIN;
2880
2881 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2882 return -ENOTTY;
2883
9d1a1031
JN		 2884 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2885 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2886 return -EAGAIN;
2887
2888 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2889 intel_wait_for_vblank(dev, intel_crtc->pipe);
2890 intel_wait_for_vblank(dev, intel_crtc->pipe);
2891
9d1a1031 2892 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2893 return -EAGAIN;
2894
9d1a1031 2895 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2896 return 0;
2897}
2898
a60f0e38
JB		 2899static bool
2900intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2901{
9d1a1031
JN		 2902 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2903 DP_DEVICE_SERVICE_IRQ_VECTOR,
2904 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2905}
2906
2907static void
2908intel_dp_handle_test_request(struct intel_dp *intel_dp)
2909{
2910 /* NAK by default */
9d1a1031 2911 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2912}
2913
a4fc5ed6
KP		 2914/*
2915 * According to DP spec
2916 * 5.1.2:
2917 * 1. Read DPCD
2918 * 2. Configure link according to Receiver Capabilities
2919 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2920 * 4. Check link status on receipt of hot-plug interrupt
2921 */
2922
00c09d70 2923void
ea5b213a 2924intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2925{
da63a9f2 2926 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2927 u8 sink_irq_vector;
93f62dad 2928 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2929
da63a9f2 2930 if (!intel_encoder->connectors_active)
d2b996ac 2931 return;
59cd09e1 2932
da63a9f2 2933 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2934 return;
2935
92fd8fd1 2936 /* Try to read receiver status if the link appears to be up */
93f62dad 2937 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2938 return;
2939 }
2940
92fd8fd1 2941 /* Now read the DPCD to see if it's actually running */
26d61aad 2942 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2943 return;
2944 }
2945
a60f0e38
JB		 2946 /* Try to read the source of the interrupt */
2947 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2948 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2949 /* Clear interrupt source */
9d1a1031
JN		 2950 drm_dp_dpcd_writeb(&intel_dp->aux,
2951 DP_DEVICE_SERVICE_IRQ_VECTOR,
2952 sink_irq_vector);
a60f0e38
JB		 2953
2954 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2955 intel_dp_handle_test_request(intel_dp);
2956 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2957 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2958 }
2959
1ffdff13 2960 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2961 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2962 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2963 intel_dp_start_link_train(intel_dp);
2964 intel_dp_complete_link_train(intel_dp);
3ab9c637 2965 intel_dp_stop_link_train(intel_dp);
33a34e4e 2966 }
a4fc5ed6 2967}
a4fc5ed6 2968
caf9ab24 2969/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2970static enum drm_connector_status
26d61aad 2971intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2972{
caf9ab24 2973 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2974 uint8_t type;
2975
2976 if (!intel_dp_get_dpcd(intel_dp))
2977 return connector_status_disconnected;
2978
2979 /* if there's no downstream port, we're done */
2980 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2981 return connector_status_connected;
caf9ab24
AJ		 2982
2983 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2984 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2985 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2986 uint8_t reg;
9d1a1031
JN		 2987
2988 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2989 &reg, 1) < 0)
caf9ab24 2990 return connector_status_unknown;
9d1a1031 2991
23235177
AJ		 2992 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2993 : connector_status_disconnected;
caf9ab24
AJ		 2994 }
2995
2996 /* If no HPD, poke DDC gently */
0b99836f 2997 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 2998 return connector_status_connected;
caf9ab24
AJ		 2999
3000 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3001 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3002 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3003 if (type == DP_DS_PORT_TYPE_VGA ||
3004 type == DP_DS_PORT_TYPE_NON_EDID)
3005 return connector_status_unknown;
3006 } else {
3007 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3008 DP_DWN_STRM_PORT_TYPE_MASK;
3009 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3010 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3011 return connector_status_unknown;
3012 }
caf9ab24
AJ		 3013
3014 /* Anything else is out of spec, warn and ignore */
3015 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3016 return connector_status_disconnected;
71ba9000
AJ		 3017}
3018
5eb08b69 3019static enum drm_connector_status
a9756bb5 3020ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3021{
30add22d 3022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3025 enum drm_connector_status status;
3026
fe16d949
CW		 3027 /* Can't disconnect eDP, but you can close the lid... */
3028 if (is_edp(intel_dp)) {
30add22d 3029 status = intel_panel_detect(dev);
fe16d949
CW		 3030 if (status == connector_status_unknown)
3031 status = connector_status_connected;
3032 return status;
3033 }
01cb9ea6 3034
1b469639
DL		 3035 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3036 return connector_status_disconnected;
3037
26d61aad 3038 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3039}
3040
a4fc5ed6 3041static enum drm_connector_status
a9756bb5 3042g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3043{
30add22d 3044 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3045 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3046 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3047 uint32_t bit;
5eb08b69 3048
35aad75f
JB		 3049 /* Can't disconnect eDP, but you can close the lid... */
3050 if (is_edp(intel_dp)) {
3051 enum drm_connector_status status;
3052
3053 status = intel_panel_detect(dev);
3054 if (status == connector_status_unknown)
3055 status = connector_status_connected;
3056 return status;
3057 }
3058
232a6ee9
TP		 3059 if (IS_VALLEYVIEW(dev)) {
3060 switch (intel_dig_port->port) {
3061 case PORT_B:
3062 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3063 break;
3064 case PORT_C:
3065 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3066 break;
3067 case PORT_D:
3068 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3069 break;
3070 default:
3071 return connector_status_unknown;
3072 }
3073 } else {
3074 switch (intel_dig_port->port) {
3075 case PORT_B:
3076 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3077 break;
3078 case PORT_C:
3079 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3080 break;
3081 case PORT_D:
3082 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3083 break;
3084 default:
3085 return connector_status_unknown;
3086 }
a4fc5ed6
KP		 3087 }
3088
10f76a38 3089 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3090 return connector_status_disconnected;
3091
26d61aad 3092 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3093}
3094
8c241fef
KP		 3095static struct edid *
3096intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3097{
9cd300e0 3098 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3099
9cd300e0
JN		 3100 /* use cached edid if we have one */
3101 if (intel_connector->edid) {
9cd300e0
JN		 3102 /* invalid edid */
3103 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3104 return NULL;
3105
55e9edeb 3106 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3107 }
8c241fef 3108
9cd300e0 3109 return drm_get_edid(connector, adapter);
8c241fef
KP		 3110}
3111
3112static int
3113intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3114{
9cd300e0 3115 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3116
9cd300e0
JN		 3117 /* use cached edid if we have one */
3118 if (intel_connector->edid) {
3119 /* invalid edid */
3120 if (IS_ERR(intel_connector->edid))
3121 return 0;
3122
3123 return intel_connector_update_modes(connector,
3124 intel_connector->edid);
d6f24d0f
JB		 3125 }
3126
9cd300e0 3127 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3128}
3129
a9756bb5
ZW		 3130static enum drm_connector_status
3131intel_dp_detect(struct drm_connector *connector, bool force)
3132{
3133 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3134 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3135 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3136 struct drm_device *dev = connector->dev;
c8c8fb33 3137 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3138 enum drm_connector_status status;
671dedd2 3139 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3140 struct edid *edid = NULL;
3141
c8c8fb33
PZ		 3142 intel_runtime_pm_get(dev_priv);
3143
671dedd2
ID		 3144 power_domain = intel_display_port_power_domain(intel_encoder);
3145 intel_display_power_get(dev_priv, power_domain);
3146
164c8598
CW		 3147 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3148 connector->base.id, drm_get_connector_name(connector));
3149
a9756bb5
ZW		 3150 intel_dp->has_audio = false;
3151
3152 if (HAS_PCH_SPLIT(dev))
3153 status = ironlake_dp_detect(intel_dp);
3154 else
3155 status = g4x_dp_detect(intel_dp);
1b9be9d0 3156
a9756bb5 3157 if (status != connector_status_connected)
c8c8fb33 3158 goto out;
a9756bb5 3159
0d198328
AJ		 3160 intel_dp_probe_oui(intel_dp);
3161
c3e5f67b
DV		 3162 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3163 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3164 } else {
0b99836f 3165 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3166 if (edid) {
3167 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3168 kfree(edid);
3169 }
a9756bb5
ZW		 3170 }
3171
d63885da
PZ		 3172 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3173 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3174 status = connector_status_connected;
3175
3176out:
671dedd2
ID		 3177 intel_display_power_put(dev_priv, power_domain);
3178
c8c8fb33 3179 intel_runtime_pm_put(dev_priv);
671dedd2 3180
c8c8fb33 3181 return status;
a4fc5ed6
KP		 3182}
3183
3184static int intel_dp_get_modes(struct drm_connector *connector)
3185{
df0e9248 3186 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3187 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3188 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3189 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3190 struct drm_device *dev = connector->dev;
671dedd2
ID		 3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 enum intel_display_power_domain power_domain;
32f9d658 3193 int ret;
a4fc5ed6
KP		 3194
3195 /* We should parse the EDID data and find out if it has an audio sink
3196 */
3197
671dedd2
ID		 3198 power_domain = intel_display_port_power_domain(intel_encoder);
3199 intel_display_power_get(dev_priv, power_domain);
3200
0b99836f 3201 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3202 intel_display_power_put(dev_priv, power_domain);
f8779fda 3203 if (ret)
32f9d658
ZW		 3204 return ret;
3205
f8779fda 3206 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3207 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3208 struct drm_display_mode *mode;
dd06f90e
JN		 3209 mode = drm_mode_duplicate(dev,
3210 intel_connector->panel.fixed_mode);
f8779fda 3211 if (mode) {
32f9d658
ZW		 3212 drm_mode_probed_add(connector, mode);
3213 return 1;
3214 }
3215 }
3216 return 0;
a4fc5ed6
KP		 3217}
3218
1aad7ac0
CW		 3219static bool
3220intel_dp_detect_audio(struct drm_connector *connector)
3221{
3222 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3223 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3224 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3225 struct drm_device *dev = connector->dev;
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3228 struct edid *edid;
3229 bool has_audio = false;
3230
671dedd2
ID		 3231 power_domain = intel_display_port_power_domain(intel_encoder);
3232 intel_display_power_get(dev_priv, power_domain);
3233
0b99836f 3234 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3235 if (edid) {
3236 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3237 kfree(edid);
3238 }
3239
671dedd2
ID		 3240 intel_display_power_put(dev_priv, power_domain);
3241
1aad7ac0
CW		 3242 return has_audio;
3243}
3244
f684960e
CW		 3245static int
3246intel_dp_set_property(struct drm_connector *connector,
3247 struct drm_property *property,
3248 uint64_t val)
3249{
e953fd7b 3250 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3251 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3252 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3253 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3254 int ret;
3255
662595df 3256 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3257 if (ret)
3258 return ret;
3259
3f43c48d 3260 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3261 int i = val;
3262 bool has_audio;
3263
3264 if (i == intel_dp->force_audio)
f684960e
CW		 3265 return 0;
3266
1aad7ac0 3267 intel_dp->force_audio = i;
f684960e 3268
c3e5f67b 3269 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3270 has_audio = intel_dp_detect_audio(connector);
3271 else
c3e5f67b 3272 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3273
3274 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3275 return 0;
3276
1aad7ac0 3277 intel_dp->has_audio = has_audio;
f684960e
CW		 3278 goto done;
3279 }
3280
e953fd7b 3281 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3282 bool old_auto = intel_dp->color_range_auto;
3283 uint32_t old_range = intel_dp->color_range;
3284
55bc60db
VS		 3285 switch (val) {
3286 case INTEL_BROADCAST_RGB_AUTO:
3287 intel_dp->color_range_auto = true;
3288 break;
3289 case INTEL_BROADCAST_RGB_FULL:
3290 intel_dp->color_range_auto = false;
3291 intel_dp->color_range = 0;
3292 break;
3293 case INTEL_BROADCAST_RGB_LIMITED:
3294 intel_dp->color_range_auto = false;
3295 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3296 break;
3297 default:
3298 return -EINVAL;
3299 }
ae4edb80
DV		 3300
3301 if (old_auto == intel_dp->color_range_auto &&
3302 old_range == intel_dp->color_range)
3303 return 0;
3304
e953fd7b
CW		 3305 goto done;
3306 }
3307
53b41837
YN		 3308 if (is_edp(intel_dp) &&
3309 property == connector->dev->mode_config.scaling_mode_property) {
3310 if (val == DRM_MODE_SCALE_NONE) {
3311 DRM_DEBUG_KMS("no scaling not supported\n");
3312 return -EINVAL;
3313 }
3314
3315 if (intel_connector->panel.fitting_mode == val) {
3316 /* the eDP scaling property is not changed */
3317 return 0;
3318 }
3319 intel_connector->panel.fitting_mode = val;
3320
3321 goto done;
3322 }
3323
f684960e
CW		 3324 return -EINVAL;
3325
3326done:
c0c36b94
CW		 3327 if (intel_encoder->base.crtc)
3328 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3329
3330 return 0;
3331}
3332
a4fc5ed6 3333static void
73845adf 3334intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3335{
1d508706 3336 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3337
9cd300e0
JN		 3338 if (!IS_ERR_OR_NULL(intel_connector->edid))
3339 kfree(intel_connector->edid);
3340
acd8db10
PZ		 3341 /* Can't call is_edp() since the encoder may have been destroyed
3342 * already. */
3343 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3344 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3345
a4fc5ed6 3346 drm_connector_cleanup(connector);
55f78c43 3347 kfree(connector);
a4fc5ed6
KP		 3348}
3349
00c09d70 3350void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3351{
da63a9f2
PZ		 3352 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3353 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3354 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3355
0b99836f 3356 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3357 drm_encoder_cleanup(encoder);
bd943159
KP		 3358 if (is_edp(intel_dp)) {
3359 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3360 mutex_lock(&dev->mode_config.mutex);
4be73780 3361 edp_panel_vdd_off_sync(intel_dp);
bd173813 3362 mutex_unlock(&dev->mode_config.mutex);
bd943159 3363 }
da63a9f2 3364 kfree(intel_dig_port);
24d05927
DV		 3365}
3366
a4fc5ed6 3367static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3368 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3369 .detect = intel_dp_detect,
3370 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3371 .set_property = intel_dp_set_property,
73845adf 3372 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3373};
3374
3375static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3376 .get_modes = intel_dp_get_modes,
3377 .mode_valid = intel_dp_mode_valid,
df0e9248 3378 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3379};
3380
a4fc5ed6 3381static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3382 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3383};
3384
995b6762 3385static void
21d40d37 3386intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3387{
fa90ecef 3388 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3389
885a5014 3390 intel_dp_check_link_status(intel_dp);
c8110e52 3391}
6207937d 3392
e3421a18
ZW		 3393/* Return which DP Port should be selected for Transcoder DP control */
3394int
0206e353 3395intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3396{
3397 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3398 struct intel_encoder *intel_encoder;
3399 struct intel_dp *intel_dp;
e3421a18 3400
fa90ecef
PZ		 3401 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3402 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3403
fa90ecef
PZ		 3404 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3405 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3406 return intel_dp->output_reg;
e3421a18 3407 }
ea5b213a 3408
e3421a18
ZW		 3409 return -1;
3410}
3411
36e83a18 3412/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3413bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3414{
3415 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3416 union child_device_config *p_child;
36e83a18 3417 int i;
5d8a7752
VS		 3418 static const short port_mapping[] = {
3419 [PORT_B] = PORT_IDPB,
3420 [PORT_C] = PORT_IDPC,
3421 [PORT_D] = PORT_IDPD,
3422 };
36e83a18 3423
3b32a35b
VS		 3424 if (port == PORT_A)
3425 return true;
3426
41aa3448 3427 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3428 return false;
3429
41aa3448
RV		 3430 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3431 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3432
5d8a7752 3433 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3434 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3435 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3436 return true;
3437 }
3438 return false;
3439}
3440
f684960e
CW		 3441static void
3442intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3443{
53b41837
YN		 3444 struct intel_connector *intel_connector = to_intel_connector(connector);
3445
3f43c48d 3446 intel_attach_force_audio_property(connector);
e953fd7b 3447 intel_attach_broadcast_rgb_property(connector);
55bc60db 3448 intel_dp->color_range_auto = true;
53b41837
YN		 3449
3450 if (is_edp(intel_dp)) {
3451 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3452 drm_object_attach_property(
3453 &connector->base,
53b41837 3454 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3455 DRM_MODE_SCALE_ASPECT);
3456 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3457 }
f684960e
CW		 3458}
3459
dada1a9f
ID		 3460static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3461{
3462 intel_dp->last_power_cycle = jiffies;
3463 intel_dp->last_power_on = jiffies;
3464 intel_dp->last_backlight_off = jiffies;
3465}
3466
67a54566
DV		 3467static void
3468intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3469 struct intel_dp *intel_dp,
3470 struct edp_power_seq *out)
67a54566
DV		 3471{
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473 struct edp_power_seq cur, vbt, spec, final;
3474 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3475 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3476
3477 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3478 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3479 pp_on_reg = PCH_PP_ON_DELAYS;
3480 pp_off_reg = PCH_PP_OFF_DELAYS;
3481 pp_div_reg = PCH_PP_DIVISOR;
3482 } else {
bf13e81b
JN		 3483 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3484
3485 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3486 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3487 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3488 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3489 }
67a54566
DV		 3490
3491 /* Workaround: Need to write PP_CONTROL with the unlock key as
3492 * the very first thing. */
453c5420 3493 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3494 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3495
453c5420
JB		 3496 pp_on = I915_READ(pp_on_reg);
3497 pp_off = I915_READ(pp_off_reg);
3498 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3499
3500 /* Pull timing values out of registers */
3501 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3502 PANEL_POWER_UP_DELAY_SHIFT;
3503
3504 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3505 PANEL_LIGHT_ON_DELAY_SHIFT;
3506
3507 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3508 PANEL_LIGHT_OFF_DELAY_SHIFT;
3509
3510 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3511 PANEL_POWER_DOWN_DELAY_SHIFT;
3512
3513 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3514 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3515
3516 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3517 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3518
41aa3448 3519 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3520
3521 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3522 * our hw here, which are all in 100usec. */
3523 spec.t1_t3 = 210 * 10;
3524 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3525 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3526 spec.t10 = 500 * 10;
3527 /* This one is special and actually in units of 100ms, but zero
3528 * based in the hw (so we need to add 100 ms). But the sw vbt
3529 * table multiplies it with 1000 to make it in units of 100usec,
3530 * too. */
3531 spec.t11_t12 = (510 + 100) * 10;
3532
3533 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3534 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3535
3536 /* Use the max of the register settings and vbt. If both are
3537 * unset, fall back to the spec limits. */
3538#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3539 spec.field : \
3540 max(cur.field, vbt.field))
3541 assign_final(t1_t3);
3542 assign_final(t8);
3543 assign_final(t9);
3544 assign_final(t10);
3545 assign_final(t11_t12);
3546#undef assign_final
3547
3548#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3549 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3550 intel_dp->backlight_on_delay = get_delay(t8);
3551 intel_dp->backlight_off_delay = get_delay(t9);
3552 intel_dp->panel_power_down_delay = get_delay(t10);
3553 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3554#undef get_delay
3555
f30d26e4
JN		 3556 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3557 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3558 intel_dp->panel_power_cycle_delay);
3559
3560 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3561 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3562
3563 if (out)
3564 *out = final;
3565}
3566
3567static void
3568intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3569 struct intel_dp *intel_dp,
3570 struct edp_power_seq *seq)
3571{
3572 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3573 u32 pp_on, pp_off, pp_div, port_sel = 0;
3574 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3575 int pp_on_reg, pp_off_reg, pp_div_reg;
3576
3577 if (HAS_PCH_SPLIT(dev)) {
3578 pp_on_reg = PCH_PP_ON_DELAYS;
3579 pp_off_reg = PCH_PP_OFF_DELAYS;
3580 pp_div_reg = PCH_PP_DIVISOR;
3581 } else {
bf13e81b
JN		 3582 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3583
3584 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3585 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3586 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3587 }
3588
b2f19d1a
PZ		 3589 /*
3590 * And finally store the new values in the power sequencer. The
3591 * backlight delays are set to 1 because we do manual waits on them. For
3592 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3593 * we'll end up waiting for the backlight off delay twice: once when we
3594 * do the manual sleep, and once when we disable the panel and wait for
3595 * the PP_STATUS bit to become zero.
3596 */
f30d26e4 3597 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3598 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3599 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3600 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3601 /* Compute the divisor for the pp clock, simply match the Bspec
3602 * formula. */
453c5420 3603 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3604 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3605 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3606
3607 /* Haswell doesn't have any port selection bits for the panel
3608 * power sequencer any more. */
bc7d38a4 3609 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3610 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3611 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3612 else
3613 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3614 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3615 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3616 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3617 else
a24c144c 3618 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3619 }
3620
453c5420
JB		 3621 pp_on |= port_sel;
3622
3623 I915_WRITE(pp_on_reg, pp_on);
3624 I915_WRITE(pp_off_reg, pp_off);
3625 I915_WRITE(pp_div_reg, pp_div);
67a54566 3626
67a54566 3627 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3628 I915_READ(pp_on_reg),
3629 I915_READ(pp_off_reg),
3630 I915_READ(pp_div_reg));
f684960e
CW		 3631}
3632
ed92f0b2 3633static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3634 struct intel_connector *intel_connector,
3635 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3636{
3637 struct drm_connector *connector = &intel_connector->base;
3638 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 3639 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3640 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3643 bool has_dpcd;
3644 struct drm_display_mode *scan;
3645 struct edid *edid;
3646
3647 if (!is_edp(intel_dp))
3648 return true;
3649
63635217
PZ		 3650 /* The VDD bit needs a power domain reference, so if the bit is already
3651 * enabled when we boot, grab this reference. */
3652 if (edp_have_panel_vdd(intel_dp)) {
3653 enum intel_display_power_domain power_domain;
3654 power_domain = intel_display_port_power_domain(intel_encoder);
3655 intel_display_power_get(dev_priv, power_domain);
3656 }
3657
ed92f0b2 3658 /* Cache DPCD and EDID for edp. */
24f3e092 3659 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3660 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3661 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3662
3663 if (has_dpcd) {
3664 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3665 dev_priv->no_aux_handshake =
3666 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3667 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3668 } else {
3669 /* if this fails, presume the device is a ghost */
3670 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3671 return false;
3672 }
3673
3674 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3675 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3676
060c8778 3677 mutex_lock(&dev->mode_config.mutex);
0b99836f 3678 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3679 if (edid) {
3680 if (drm_add_edid_modes(connector, edid)) {
3681 drm_mode_connector_update_edid_property(connector,
3682 edid);
3683 drm_edid_to_eld(connector, edid);
3684 } else {
3685 kfree(edid);
3686 edid = ERR_PTR(-EINVAL);
3687 }
3688 } else {
3689 edid = ERR_PTR(-ENOENT);
3690 }
3691 intel_connector->edid = edid;
3692
3693 /* prefer fixed mode from EDID if available */
3694 list_for_each_entry(scan, &connector->probed_modes, head) {
3695 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3696 fixed_mode = drm_mode_duplicate(dev, scan);
3697 break;
3698 }
3699 }
3700
3701 /* fallback to VBT if available for eDP */
3702 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3703 fixed_mode = drm_mode_duplicate(dev,
3704 dev_priv->vbt.lfp_lvds_vbt_mode);
3705 if (fixed_mode)
3706 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3707 }
060c8778 3708 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3709
4b6ed685 3710 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3711 intel_panel_setup_backlight(connector);
3712
3713 return true;
3714}
3715
16c25533 3716bool
f0fec3f2
PZ		 3717intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3718 struct intel_connector *intel_connector)
a4fc5ed6 3719{
f0fec3f2
PZ		 3720 struct drm_connector *connector = &intel_connector->base;
3721 struct intel_dp *intel_dp = &intel_dig_port->dp;
3722 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3723 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3724 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3725 enum port port = intel_dig_port->port;
0095e6dc 3726 struct edp_power_seq power_seq = { 0 };
0b99836f 3727 int type;
a4fc5ed6 3728
ec5b01dd
DL		 3729 /* intel_dp vfuncs */
3730 if (IS_VALLEYVIEW(dev))
3731 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3732 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3733 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3734 else if (HAS_PCH_SPLIT(dev))
3735 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3736 else
3737 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3738
153b1100
DL		 3739 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3740
0767935e
DV		 3741 /* Preserve the current hw state. */
3742 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3743 intel_dp->attached_connector = intel_connector;
3d3dc149 3744
3b32a35b 3745 if (intel_dp_is_edp(dev, port))
b329530c 3746 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3747 else
3748 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3749
f7d24902
ID		 3750 /*
3751 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3752 * for DP the encoder type can be set by the caller to
3753 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3754 */
3755 if (type == DRM_MODE_CONNECTOR_eDP)
3756 intel_encoder->type = INTEL_OUTPUT_EDP;
3757
e7281eab
ID		 3758 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3759 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3760 port_name(port));
3761
b329530c 3762 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3763 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3764
a4fc5ed6
KP		 3765 connector->interlace_allowed = true;
3766 connector->doublescan_allowed = 0;
3767
f0fec3f2 3768 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3769 edp_panel_vdd_work);
a4fc5ed6 3770
df0e9248 3771 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3772 drm_sysfs_connector_add(connector);
3773
affa9354 3774 if (HAS_DDI(dev))
bcbc889b
PZ		 3775 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3776 else
3777 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3778 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3779
0b99836f 3780 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3781 switch (port) {
3782 case PORT_A:
1d843f9d 3783 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3784 break;
3785 case PORT_B:
1d843f9d 3786 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3787 break;
3788 case PORT_C:
1d843f9d 3789 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3790 break;
3791 case PORT_D:
1d843f9d 3792 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3793 break;
3794 default:
ad1c0b19 3795 BUG();
5eb08b69
ZW		 3796 }
3797
dada1a9f
ID		 3798 if (is_edp(intel_dp)) {
3799 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3800 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3801 }
0095e6dc 3802
9d1a1031 3803 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3804
2b28bb1b
RV		 3805 intel_dp->psr_setup_done = false;
3806
0095e6dc 3807 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3808 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3809 if (is_edp(intel_dp)) {
3810 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3811 mutex_lock(&dev->mode_config.mutex);
4be73780 3812 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3813 mutex_unlock(&dev->mode_config.mutex);
3814 }
b2f246a8
PZ		 3815 drm_sysfs_connector_remove(connector);
3816 drm_connector_cleanup(connector);
16c25533 3817 return false;
b2f246a8 3818 }
32f9d658 3819
f684960e
CW		 3820 intel_dp_add_properties(intel_dp, connector);
3821
a4fc5ed6
KP		 3822 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3823 * 0xd. Failure to do so will result in spurious interrupts being
3824 * generated on the port when a cable is not attached.
3825 */
3826 if (IS_G4X(dev) && !IS_GM45(dev)) {
3827 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3828 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3829 }
16c25533
PZ		 3830
3831 return true;
a4fc5ed6 3832}
f0fec3f2
PZ		 3833
3834void
3835intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3836{
3837 struct intel_digital_port *intel_dig_port;
3838 struct intel_encoder *intel_encoder;
3839 struct drm_encoder *encoder;
3840 struct intel_connector *intel_connector;
3841
b14c5679 3842 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3843 if (!intel_dig_port)
3844 return;
3845
b14c5679 3846 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3847 if (!intel_connector) {
3848 kfree(intel_dig_port);
3849 return;
3850 }
3851
3852 intel_encoder = &intel_dig_port->base;
3853 encoder = &intel_encoder->base;
3854
3855 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3856 DRM_MODE_ENCODER_TMDS);
3857
5bfe2ac0 3858 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3859 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3860 intel_encoder->disable = intel_disable_dp;
3861 intel_encoder->post_disable = intel_post_disable_dp;
3862 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3863 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3864 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3865 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3866 intel_encoder->pre_enable = vlv_pre_enable_dp;
3867 intel_encoder->enable = vlv_enable_dp;
3868 } else {
ecff4f3b
JN		 3869 intel_encoder->pre_enable = g4x_pre_enable_dp;
3870 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3871 }
f0fec3f2 3872
174edf1f 3873 intel_dig_port->port = port;
f0fec3f2
PZ		 3874 intel_dig_port->dp.output_reg = output_reg;
3875
00c09d70 3876 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 3877 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3878 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 3879 intel_encoder->hot_plug = intel_dp_hot_plug;
3880
15b1d171
PZ		 3881 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3882 drm_encoder_cleanup(encoder);
3883 kfree(intel_dig_port);
b2f246a8 3884 kfree(intel_connector);
15b1d171 3885 }
f0fec3f2 3886}
Linux kernel - Deliverables
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