Commit | Line | Data |
---|---|---|
a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
a4fc5ed6 | 40 | #include "i915_drv.h" |
a4fc5ed6 | 41 | |
a4fc5ed6 KP |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
43 | ||
559be30c TP |
44 | /* Compliance test status bits */ |
45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | ||
9dd4ffdf CML |
50 | struct dp_link_dpll { |
51 | int link_bw; | |
52 | struct dpll dpll; | |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll gen4_dpll[] = { | |
56 | { DP_LINK_BW_1_62, | |
57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, | |
58 | { DP_LINK_BW_2_7, | |
59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } | |
60 | }; | |
61 | ||
62 | static const struct dp_link_dpll pch_dpll[] = { | |
63 | { DP_LINK_BW_1_62, | |
64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, | |
65 | { DP_LINK_BW_2_7, | |
66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } | |
67 | }; | |
68 | ||
65ce4bf5 CML |
69 | static const struct dp_link_dpll vlv_dpll[] = { |
70 | { DP_LINK_BW_1_62, | |
58f6e632 | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
65ce4bf5 CML |
72 | { DP_LINK_BW_2_7, |
73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } | |
74 | }; | |
75 | ||
ef9348c8 CML |
76 | /* |
77 | * CHV supports eDP 1.4 that have more link rates. | |
78 | * Below only provides the fixed rate but exclude variable rate. | |
79 | */ | |
80 | static const struct dp_link_dpll chv_dpll[] = { | |
81 | /* | |
82 | * CHV requires to program fractional division for m2. | |
83 | * m2 is stored in fixed point format using formula below | |
84 | * (m2_int << 22) | m2_fraction | |
85 | */ | |
86 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ | |
87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, | |
88 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ | |
89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, | |
90 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ | |
91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } | |
92 | }; | |
637a9c63 | 93 | |
64987fc5 SJ |
94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
95 | 324000, 432000, 540000 }; | |
637a9c63 | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 | 97 | 324000, 432000, 540000 }; |
fe51bfb9 VS |
98 | static const int chv_rates[] = { 162000, 202500, 210000, 216000, |
99 | 243000, 270000, 324000, 405000, | |
100 | 420000, 432000, 540000 }; | |
f4896f15 | 101 | static const int default_rates[] = { 162000, 270000, 540000 }; |
ef9348c8 | 102 | |
cfcb0fc9 JB |
103 | /** |
104 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
105 | * @intel_dp: DP struct | |
106 | * | |
107 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
108 | * will return true, and false otherwise. | |
109 | */ | |
110 | static bool is_edp(struct intel_dp *intel_dp) | |
111 | { | |
da63a9f2 PZ |
112 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
113 | ||
114 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
115 | } |
116 | ||
68b4d824 | 117 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 118 | { |
68b4d824 ID |
119 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
120 | ||
121 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
122 | } |
123 | ||
df0e9248 CW |
124 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
125 | { | |
fa90ecef | 126 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
127 | } |
128 | ||
ea5b213a | 129 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 130 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 131 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 132 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
133 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
134 | enum pipe pipe); | |
a4fc5ed6 | 135 | |
ed4e9c1d VS |
136 | static int |
137 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 138 | { |
7183dc29 | 139 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
140 | |
141 | switch (max_link_bw) { | |
142 | case DP_LINK_BW_1_62: | |
143 | case DP_LINK_BW_2_7: | |
1db10e28 | 144 | case DP_LINK_BW_5_4: |
d4eead50 | 145 | break; |
a4fc5ed6 | 146 | default: |
d4eead50 ID |
147 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
148 | max_link_bw); | |
a4fc5ed6 KP |
149 | max_link_bw = DP_LINK_BW_1_62; |
150 | break; | |
151 | } | |
152 | return max_link_bw; | |
153 | } | |
154 | ||
eeb6324d PZ |
155 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
156 | { | |
157 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
158 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
159 | u8 source_max, sink_max; | |
160 | ||
161 | source_max = 4; | |
162 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && | |
163 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) | |
164 | source_max = 2; | |
165 | ||
166 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | |
167 | ||
168 | return min(source_max, sink_max); | |
169 | } | |
170 | ||
cd9dde44 AJ |
171 | /* |
172 | * The units on the numbers in the next two are... bizarre. Examples will | |
173 | * make it clearer; this one parallels an example in the eDP spec. | |
174 | * | |
175 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
176 | * | |
177 | * 270000 * 1 * 8 / 10 == 216000 | |
178 | * | |
179 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
180 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
181 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
182 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
183 | * | |
184 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
185 | * get the result in decakilobits instead of kilobits. | |
186 | */ | |
187 | ||
a4fc5ed6 | 188 | static int |
c898261c | 189 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 190 | { |
cd9dde44 | 191 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
192 | } |
193 | ||
fe27d53e DA |
194 | static int |
195 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
196 | { | |
197 | return (max_link_clock * max_lanes * 8) / 10; | |
198 | } | |
199 | ||
c19de8eb | 200 | static enum drm_mode_status |
a4fc5ed6 KP |
201 | intel_dp_mode_valid(struct drm_connector *connector, |
202 | struct drm_display_mode *mode) | |
203 | { | |
df0e9248 | 204 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
205 | struct intel_connector *intel_connector = to_intel_connector(connector); |
206 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
207 | int target_clock = mode->clock; |
208 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 209 | |
dd06f90e JN |
210 | if (is_edp(intel_dp) && fixed_mode) { |
211 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
212 | return MODE_PANEL; |
213 | ||
dd06f90e | 214 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 215 | return MODE_PANEL; |
03afc4a2 DV |
216 | |
217 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
218 | } |
219 | ||
50fec21a | 220 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 221 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
222 | |
223 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
224 | mode_rate = intel_dp_link_required(target_clock, 18); | |
225 | ||
226 | if (mode_rate > max_rate) | |
c4867936 | 227 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
228 | |
229 | if (mode->clock < 10000) | |
230 | return MODE_CLOCK_LOW; | |
231 | ||
0af78a2b DV |
232 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
233 | return MODE_H_ILLEGAL; | |
234 | ||
a4fc5ed6 KP |
235 | return MODE_OK; |
236 | } | |
237 | ||
a4f1289e | 238 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
239 | { |
240 | int i; | |
241 | uint32_t v = 0; | |
242 | ||
243 | if (src_bytes > 4) | |
244 | src_bytes = 4; | |
245 | for (i = 0; i < src_bytes; i++) | |
246 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
247 | return v; | |
248 | } | |
249 | ||
c2af70e2 | 250 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
251 | { |
252 | int i; | |
253 | if (dst_bytes > 4) | |
254 | dst_bytes = 4; | |
255 | for (i = 0; i < dst_bytes; i++) | |
256 | dst[i] = src >> ((3-i) * 8); | |
257 | } | |
258 | ||
fb0f8fbf KP |
259 | /* hrawclock is 1/4 the FSB frequency */ |
260 | static int | |
261 | intel_hrawclk(struct drm_device *dev) | |
262 | { | |
263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
264 | uint32_t clkcfg; | |
265 | ||
9473c8f4 VP |
266 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
267 | if (IS_VALLEYVIEW(dev)) | |
268 | return 200; | |
269 | ||
fb0f8fbf KP |
270 | clkcfg = I915_READ(CLKCFG); |
271 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
272 | case CLKCFG_FSB_400: | |
273 | return 100; | |
274 | case CLKCFG_FSB_533: | |
275 | return 133; | |
276 | case CLKCFG_FSB_667: | |
277 | return 166; | |
278 | case CLKCFG_FSB_800: | |
279 | return 200; | |
280 | case CLKCFG_FSB_1067: | |
281 | return 266; | |
282 | case CLKCFG_FSB_1333: | |
283 | return 333; | |
284 | /* these two are just a guess; one of them might be right */ | |
285 | case CLKCFG_FSB_1600: | |
286 | case CLKCFG_FSB_1600_ALT: | |
287 | return 400; | |
288 | default: | |
289 | return 133; | |
290 | } | |
291 | } | |
292 | ||
bf13e81b JN |
293 | static void |
294 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 295 | struct intel_dp *intel_dp); |
bf13e81b JN |
296 | static void |
297 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 298 | struct intel_dp *intel_dp); |
bf13e81b | 299 | |
773538e8 VS |
300 | static void pps_lock(struct intel_dp *intel_dp) |
301 | { | |
302 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
303 | struct intel_encoder *encoder = &intel_dig_port->base; | |
304 | struct drm_device *dev = encoder->base.dev; | |
305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
306 | enum intel_display_power_domain power_domain; | |
307 | ||
308 | /* | |
309 | * See vlv_power_sequencer_reset() why we need | |
310 | * a power domain reference here. | |
311 | */ | |
312 | power_domain = intel_display_port_power_domain(encoder); | |
313 | intel_display_power_get(dev_priv, power_domain); | |
314 | ||
315 | mutex_lock(&dev_priv->pps_mutex); | |
316 | } | |
317 | ||
318 | static void pps_unlock(struct intel_dp *intel_dp) | |
319 | { | |
320 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
321 | struct intel_encoder *encoder = &intel_dig_port->base; | |
322 | struct drm_device *dev = encoder->base.dev; | |
323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
324 | enum intel_display_power_domain power_domain; | |
325 | ||
326 | mutex_unlock(&dev_priv->pps_mutex); | |
327 | ||
328 | power_domain = intel_display_port_power_domain(encoder); | |
329 | intel_display_power_put(dev_priv, power_domain); | |
330 | } | |
331 | ||
961a0db0 VS |
332 | static void |
333 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
334 | { | |
335 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
336 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
338 | enum pipe pipe = intel_dp->pps_pipe; | |
d288f65f | 339 | bool pll_enabled; |
961a0db0 VS |
340 | uint32_t DP; |
341 | ||
342 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
343 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
344 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
345 | return; | |
346 | ||
347 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
348 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
349 | ||
350 | /* Preserve the BIOS-computed detected bit. This is | |
351 | * supposed to be read-only. | |
352 | */ | |
353 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
354 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
355 | DP |= DP_PORT_WIDTH(1); | |
356 | DP |= DP_LINK_TRAIN_PAT_1; | |
357 | ||
358 | if (IS_CHERRYVIEW(dev)) | |
359 | DP |= DP_PIPE_SELECT_CHV(pipe); | |
360 | else if (pipe == PIPE_B) | |
361 | DP |= DP_PIPEB_SELECT; | |
362 | ||
d288f65f VS |
363 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
364 | ||
365 | /* | |
366 | * The DPLL for the pipe must be enabled for this to work. | |
367 | * So enable temporarily it if it's not already enabled. | |
368 | */ | |
369 | if (!pll_enabled) | |
370 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? | |
371 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); | |
372 | ||
961a0db0 VS |
373 | /* |
374 | * Similar magic as in intel_dp_enable_port(). | |
375 | * We _must_ do this port enable + disable trick | |
376 | * to make this power seqeuencer lock onto the port. | |
377 | * Otherwise even VDD force bit won't work. | |
378 | */ | |
379 | I915_WRITE(intel_dp->output_reg, DP); | |
380 | POSTING_READ(intel_dp->output_reg); | |
381 | ||
382 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
383 | POSTING_READ(intel_dp->output_reg); | |
384 | ||
385 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
386 | POSTING_READ(intel_dp->output_reg); | |
d288f65f VS |
387 | |
388 | if (!pll_enabled) | |
389 | vlv_force_pll_off(dev, pipe); | |
961a0db0 VS |
390 | } |
391 | ||
bf13e81b JN |
392 | static enum pipe |
393 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
394 | { | |
395 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b JN |
396 | struct drm_device *dev = intel_dig_port->base.base.dev; |
397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
398 | struct intel_encoder *encoder; |
399 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 400 | enum pipe pipe; |
bf13e81b | 401 | |
e39b999a | 402 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 403 | |
a8c3344e VS |
404 | /* We should never land here with regular DP ports */ |
405 | WARN_ON(!is_edp(intel_dp)); | |
406 | ||
a4a5d2f8 VS |
407 | if (intel_dp->pps_pipe != INVALID_PIPE) |
408 | return intel_dp->pps_pipe; | |
409 | ||
410 | /* | |
411 | * We don't have power sequencer currently. | |
412 | * Pick one that's not used by other ports. | |
413 | */ | |
414 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
415 | base.head) { | |
416 | struct intel_dp *tmp; | |
417 | ||
418 | if (encoder->type != INTEL_OUTPUT_EDP) | |
419 | continue; | |
420 | ||
421 | tmp = enc_to_intel_dp(&encoder->base); | |
422 | ||
423 | if (tmp->pps_pipe != INVALID_PIPE) | |
424 | pipes &= ~(1 << tmp->pps_pipe); | |
425 | } | |
426 | ||
427 | /* | |
428 | * Didn't find one. This should not happen since there | |
429 | * are two power sequencers and up to two eDP ports. | |
430 | */ | |
431 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
432 | pipe = PIPE_A; |
433 | else | |
434 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 435 | |
a8c3344e VS |
436 | vlv_steal_power_sequencer(dev, pipe); |
437 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
438 | |
439 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
440 | pipe_name(intel_dp->pps_pipe), | |
441 | port_name(intel_dig_port->port)); | |
442 | ||
443 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
444 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
445 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 | 446 | |
961a0db0 VS |
447 | /* |
448 | * Even vdd force doesn't work until we've made | |
449 | * the power sequencer lock in on the port. | |
450 | */ | |
451 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
452 | |
453 | return intel_dp->pps_pipe; | |
454 | } | |
455 | ||
6491ab27 VS |
456 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
457 | enum pipe pipe); | |
458 | ||
459 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
460 | enum pipe pipe) | |
461 | { | |
462 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; | |
463 | } | |
464 | ||
465 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
466 | enum pipe pipe) | |
467 | { | |
468 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; | |
469 | } | |
470 | ||
471 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
472 | enum pipe pipe) | |
473 | { | |
474 | return true; | |
475 | } | |
bf13e81b | 476 | |
a4a5d2f8 | 477 | static enum pipe |
6491ab27 VS |
478 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
479 | enum port port, | |
480 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
481 | { |
482 | enum pipe pipe; | |
bf13e81b | 483 | |
bf13e81b JN |
484 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
485 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
486 | PANEL_PORT_SELECT_MASK; | |
a4a5d2f8 VS |
487 | |
488 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
489 | continue; | |
490 | ||
6491ab27 VS |
491 | if (!pipe_check(dev_priv, pipe)) |
492 | continue; | |
493 | ||
a4a5d2f8 | 494 | return pipe; |
bf13e81b JN |
495 | } |
496 | ||
a4a5d2f8 VS |
497 | return INVALID_PIPE; |
498 | } | |
499 | ||
500 | static void | |
501 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
502 | { | |
503 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
504 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
506 | enum port port = intel_dig_port->port; |
507 | ||
508 | lockdep_assert_held(&dev_priv->pps_mutex); | |
509 | ||
510 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
511 | /* first pick one where the panel is on */ |
512 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
513 | vlv_pipe_has_pp_on); | |
514 | /* didn't find one? pick one where vdd is on */ | |
515 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
516 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
517 | vlv_pipe_has_vdd_on); | |
518 | /* didn't find one? pick one with just the correct port */ | |
519 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
520 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
521 | vlv_pipe_any); | |
a4a5d2f8 VS |
522 | |
523 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
524 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
525 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
526 | port_name(port)); | |
527 | return; | |
bf13e81b JN |
528 | } |
529 | ||
a4a5d2f8 VS |
530 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
531 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
532 | ||
36b5f425 VS |
533 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
534 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
bf13e81b JN |
535 | } |
536 | ||
773538e8 VS |
537 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
538 | { | |
539 | struct drm_device *dev = dev_priv->dev; | |
540 | struct intel_encoder *encoder; | |
541 | ||
542 | if (WARN_ON(!IS_VALLEYVIEW(dev))) | |
543 | return; | |
544 | ||
545 | /* | |
546 | * We can't grab pps_mutex here due to deadlock with power_domain | |
547 | * mutex when power_domain functions are called while holding pps_mutex. | |
548 | * That also means that in order to use pps_pipe the code needs to | |
549 | * hold both a power domain reference and pps_mutex, and the power domain | |
550 | * reference get/put must be done while _not_ holding pps_mutex. | |
551 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
552 | * should use them always. | |
553 | */ | |
554 | ||
555 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
556 | struct intel_dp *intel_dp; | |
557 | ||
558 | if (encoder->type != INTEL_OUTPUT_EDP) | |
559 | continue; | |
560 | ||
561 | intel_dp = enc_to_intel_dp(&encoder->base); | |
562 | intel_dp->pps_pipe = INVALID_PIPE; | |
563 | } | |
bf13e81b JN |
564 | } |
565 | ||
566 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) | |
567 | { | |
568 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
569 | ||
b0a08bec VK |
570 | if (IS_BROXTON(dev)) |
571 | return BXT_PP_CONTROL(0); | |
572 | else if (HAS_PCH_SPLIT(dev)) | |
bf13e81b JN |
573 | return PCH_PP_CONTROL; |
574 | else | |
575 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
576 | } | |
577 | ||
578 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) | |
579 | { | |
580 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
581 | ||
b0a08bec VK |
582 | if (IS_BROXTON(dev)) |
583 | return BXT_PP_STATUS(0); | |
584 | else if (HAS_PCH_SPLIT(dev)) | |
bf13e81b JN |
585 | return PCH_PP_STATUS; |
586 | else | |
587 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
588 | } | |
589 | ||
01527b31 CT |
590 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
591 | This function only applicable when panel PM state is not to be tracked */ | |
592 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
593 | void *unused) | |
594 | { | |
595 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
596 | edp_notifier); | |
597 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
599 | u32 pp_div; | |
600 | u32 pp_ctrl_reg, pp_div_reg; | |
01527b31 CT |
601 | |
602 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
603 | return 0; | |
604 | ||
773538e8 | 605 | pps_lock(intel_dp); |
e39b999a | 606 | |
01527b31 | 607 | if (IS_VALLEYVIEW(dev)) { |
e39b999a VS |
608 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
609 | ||
01527b31 CT |
610 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
611 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
612 | pp_div = I915_READ(pp_div_reg); | |
613 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
614 | ||
615 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
616 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
617 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
618 | msleep(intel_dp->panel_power_cycle_delay); | |
619 | } | |
620 | ||
773538e8 | 621 | pps_unlock(intel_dp); |
e39b999a | 622 | |
01527b31 CT |
623 | return 0; |
624 | } | |
625 | ||
4be73780 | 626 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 627 | { |
30add22d | 628 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
629 | struct drm_i915_private *dev_priv = dev->dev_private; |
630 | ||
e39b999a VS |
631 | lockdep_assert_held(&dev_priv->pps_mutex); |
632 | ||
9a42356b VS |
633 | if (IS_VALLEYVIEW(dev) && |
634 | intel_dp->pps_pipe == INVALID_PIPE) | |
635 | return false; | |
636 | ||
bf13e81b | 637 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
638 | } |
639 | ||
4be73780 | 640 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 641 | { |
30add22d | 642 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
643 | struct drm_i915_private *dev_priv = dev->dev_private; |
644 | ||
e39b999a VS |
645 | lockdep_assert_held(&dev_priv->pps_mutex); |
646 | ||
9a42356b VS |
647 | if (IS_VALLEYVIEW(dev) && |
648 | intel_dp->pps_pipe == INVALID_PIPE) | |
649 | return false; | |
650 | ||
773538e8 | 651 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
652 | } |
653 | ||
9b984dae KP |
654 | static void |
655 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
656 | { | |
30add22d | 657 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 658 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 659 | |
9b984dae KP |
660 | if (!is_edp(intel_dp)) |
661 | return; | |
453c5420 | 662 | |
4be73780 | 663 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
664 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
665 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
666 | I915_READ(_pp_stat_reg(intel_dp)), |
667 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
668 | } |
669 | } | |
670 | ||
9ee32fea DV |
671 | static uint32_t |
672 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
673 | { | |
674 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
675 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 677 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
678 | uint32_t status; |
679 | bool done; | |
680 | ||
ef04f00d | 681 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 682 | if (has_aux_irq) |
b18ac466 | 683 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 684 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
685 | else |
686 | done = wait_for_atomic(C, 10) == 0; | |
687 | if (!done) | |
688 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
689 | has_aux_irq); | |
690 | #undef C | |
691 | ||
692 | return status; | |
693 | } | |
694 | ||
ec5b01dd | 695 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 696 | { |
174edf1f PZ |
697 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
698 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
9ee32fea | 699 | |
ec5b01dd DL |
700 | /* |
701 | * The clock divider is based off the hrawclk, and would like to run at | |
702 | * 2MHz. So, take the hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 703 | */ |
ec5b01dd DL |
704 | return index ? 0 : intel_hrawclk(dev) / 2; |
705 | } | |
706 | ||
707 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
708 | { | |
709 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
710 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
469d4b2a | 711 | struct drm_i915_private *dev_priv = dev->dev_private; |
ec5b01dd DL |
712 | |
713 | if (index) | |
714 | return 0; | |
715 | ||
716 | if (intel_dig_port->port == PORT_A) { | |
05024da3 VS |
717 | return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); |
718 | ||
ec5b01dd DL |
719 | } else { |
720 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); | |
721 | } | |
722 | } | |
723 | ||
724 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
725 | { | |
726 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
727 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
729 | ||
730 | if (intel_dig_port->port == PORT_A) { | |
731 | if (index) | |
732 | return 0; | |
05024da3 | 733 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
2c55c336 JN |
734 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
735 | /* Workaround for non-ULT HSW */ | |
bc86625a CW |
736 | switch (index) { |
737 | case 0: return 63; | |
738 | case 1: return 72; | |
739 | default: return 0; | |
740 | } | |
ec5b01dd | 741 | } else { |
bc86625a | 742 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 743 | } |
b84a1cf8 RV |
744 | } |
745 | ||
ec5b01dd DL |
746 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
747 | { | |
748 | return index ? 0 : 100; | |
749 | } | |
750 | ||
b6b5e383 DL |
751 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
752 | { | |
753 | /* | |
754 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
755 | * derive the clock from CDCLK automatically). We still implement the | |
756 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
757 | */ | |
758 | return index ? 0 : 1; | |
759 | } | |
760 | ||
5ed12a19 DL |
761 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
762 | bool has_aux_irq, | |
763 | int send_bytes, | |
764 | uint32_t aux_clock_divider) | |
765 | { | |
766 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
767 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
768 | uint32_t precharge, timeout; | |
769 | ||
770 | if (IS_GEN6(dev)) | |
771 | precharge = 3; | |
772 | else | |
773 | precharge = 5; | |
774 | ||
775 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) | |
776 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; | |
777 | else | |
778 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
779 | ||
780 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 781 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 782 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 783 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 784 | timeout | |
788d4433 | 785 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
786 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
787 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 788 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
789 | } |
790 | ||
b9ca5fad DL |
791 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
792 | bool has_aux_irq, | |
793 | int send_bytes, | |
794 | uint32_t unused) | |
795 | { | |
796 | return DP_AUX_CH_CTL_SEND_BUSY | | |
797 | DP_AUX_CH_CTL_DONE | | |
798 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
799 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
800 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
801 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
802 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
803 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); | |
804 | } | |
805 | ||
b84a1cf8 RV |
806 | static int |
807 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 808 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
809 | uint8_t *recv, int recv_size) |
810 | { | |
811 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
812 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
814 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; | |
815 | uint32_t ch_data = ch_ctl + 4; | |
bc86625a | 816 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
817 | int i, ret, recv_bytes; |
818 | uint32_t status; | |
5ed12a19 | 819 | int try, clock = 0; |
4e6b788c | 820 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
821 | bool vdd; |
822 | ||
773538e8 | 823 | pps_lock(intel_dp); |
e39b999a | 824 | |
72c3500a VS |
825 | /* |
826 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
827 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
828 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
829 | * ourselves. | |
830 | */ | |
1e0560e0 | 831 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
832 | |
833 | /* dp aux is extremely sensitive to irq latency, hence request the | |
834 | * lowest possible wakeup latency and so prevent the cpu from going into | |
835 | * deep sleep states. | |
836 | */ | |
837 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
838 | ||
839 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 840 | |
c67a470b PZ |
841 | intel_aux_display_runtime_get(dev_priv); |
842 | ||
11bee43e JB |
843 | /* Try to wait for any previous AUX channel activity */ |
844 | for (try = 0; try < 3; try++) { | |
ef04f00d | 845 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
846 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
847 | break; | |
848 | msleep(1); | |
849 | } | |
850 | ||
851 | if (try == 3) { | |
02196c77 MK |
852 | static u32 last_status = -1; |
853 | const u32 status = I915_READ(ch_ctl); | |
854 | ||
855 | if (status != last_status) { | |
856 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
857 | status); | |
858 | last_status = status; | |
859 | } | |
860 | ||
9ee32fea DV |
861 | ret = -EBUSY; |
862 | goto out; | |
4f7f7b7e CW |
863 | } |
864 | ||
46a5ae9f PZ |
865 | /* Only 5 data registers! */ |
866 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
867 | ret = -E2BIG; | |
868 | goto out; | |
869 | } | |
870 | ||
ec5b01dd | 871 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
872 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
873 | has_aux_irq, | |
874 | send_bytes, | |
875 | aux_clock_divider); | |
5ed12a19 | 876 | |
bc86625a CW |
877 | /* Must try at least 3 times according to DP spec */ |
878 | for (try = 0; try < 5; try++) { | |
879 | /* Load the send data into the aux channel data registers */ | |
880 | for (i = 0; i < send_bytes; i += 4) | |
881 | I915_WRITE(ch_data + i, | |
a4f1289e RV |
882 | intel_dp_pack_aux(send + i, |
883 | send_bytes - i)); | |
bc86625a CW |
884 | |
885 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 886 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
887 | |
888 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
889 | ||
890 | /* Clear done status and any errors */ | |
891 | I915_WRITE(ch_ctl, | |
892 | status | | |
893 | DP_AUX_CH_CTL_DONE | | |
894 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
895 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
896 | ||
74ebf294 | 897 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 898 | continue; |
74ebf294 TP |
899 | |
900 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
901 | * 400us delay required for errors and timeouts | |
902 | * Timeout errors from the HW already meet this | |
903 | * requirement so skip to next iteration | |
904 | */ | |
905 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
906 | usleep_range(400, 500); | |
bc86625a | 907 | continue; |
74ebf294 | 908 | } |
bc86625a | 909 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 910 | goto done; |
bc86625a | 911 | } |
a4fc5ed6 KP |
912 | } |
913 | ||
a4fc5ed6 | 914 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 915 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
916 | ret = -EBUSY; |
917 | goto out; | |
a4fc5ed6 KP |
918 | } |
919 | ||
e058c945 | 920 | done: |
a4fc5ed6 KP |
921 | /* Check for timeout or receive error. |
922 | * Timeouts occur when the sink is not connected | |
923 | */ | |
a5b3da54 | 924 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 925 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
926 | ret = -EIO; |
927 | goto out; | |
a5b3da54 | 928 | } |
1ae8c0a5 KP |
929 | |
930 | /* Timeouts occur when the device isn't connected, so they're | |
931 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 932 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 933 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
934 | ret = -ETIMEDOUT; |
935 | goto out; | |
a4fc5ed6 KP |
936 | } |
937 | ||
938 | /* Unload any bytes sent back from the other side */ | |
939 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
940 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
941 | if (recv_bytes > recv_size) |
942 | recv_bytes = recv_size; | |
0206e353 | 943 | |
4f7f7b7e | 944 | for (i = 0; i < recv_bytes; i += 4) |
a4f1289e RV |
945 | intel_dp_unpack_aux(I915_READ(ch_data + i), |
946 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 947 | |
9ee32fea DV |
948 | ret = recv_bytes; |
949 | out: | |
950 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
c67a470b | 951 | intel_aux_display_runtime_put(dev_priv); |
9ee32fea | 952 | |
884f19e9 JN |
953 | if (vdd) |
954 | edp_panel_vdd_off(intel_dp, false); | |
955 | ||
773538e8 | 956 | pps_unlock(intel_dp); |
e39b999a | 957 | |
9ee32fea | 958 | return ret; |
a4fc5ed6 KP |
959 | } |
960 | ||
a6c8aff0 JN |
961 | #define BARE_ADDRESS_SIZE 3 |
962 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
963 | static ssize_t |
964 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 965 | { |
9d1a1031 JN |
966 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
967 | uint8_t txbuf[20], rxbuf[20]; | |
968 | size_t txsize, rxsize; | |
a4fc5ed6 | 969 | int ret; |
a4fc5ed6 | 970 | |
d2d9cbbd VS |
971 | txbuf[0] = (msg->request << 4) | |
972 | ((msg->address >> 16) & 0xf); | |
973 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
974 | txbuf[2] = msg->address & 0xff; |
975 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 976 | |
9d1a1031 JN |
977 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
978 | case DP_AUX_NATIVE_WRITE: | |
979 | case DP_AUX_I2C_WRITE: | |
a6c8aff0 | 980 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 981 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 982 | |
9d1a1031 JN |
983 | if (WARN_ON(txsize > 20)) |
984 | return -E2BIG; | |
a4fc5ed6 | 985 | |
9d1a1031 | 986 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
a4fc5ed6 | 987 | |
9d1a1031 JN |
988 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
989 | if (ret > 0) { | |
990 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 991 | |
a1ddefd8 JN |
992 | if (ret > 1) { |
993 | /* Number of bytes written in a short write. */ | |
994 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
995 | } else { | |
996 | /* Return payload size. */ | |
997 | ret = msg->size; | |
998 | } | |
9d1a1031 JN |
999 | } |
1000 | break; | |
46a5ae9f | 1001 | |
9d1a1031 JN |
1002 | case DP_AUX_NATIVE_READ: |
1003 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1004 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1005 | rxsize = msg->size + 1; |
a4fc5ed6 | 1006 | |
9d1a1031 JN |
1007 | if (WARN_ON(rxsize > 20)) |
1008 | return -E2BIG; | |
a4fc5ed6 | 1009 | |
9d1a1031 JN |
1010 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1011 | if (ret > 0) { | |
1012 | msg->reply = rxbuf[0] >> 4; | |
1013 | /* | |
1014 | * Assume happy day, and copy the data. The caller is | |
1015 | * expected to check msg->reply before touching it. | |
1016 | * | |
1017 | * Return payload size. | |
1018 | */ | |
1019 | ret--; | |
1020 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1021 | } |
9d1a1031 JN |
1022 | break; |
1023 | ||
1024 | default: | |
1025 | ret = -EINVAL; | |
1026 | break; | |
a4fc5ed6 | 1027 | } |
f51a44b9 | 1028 | |
9d1a1031 | 1029 | return ret; |
a4fc5ed6 KP |
1030 | } |
1031 | ||
9d1a1031 JN |
1032 | static void |
1033 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) | |
1034 | { | |
1035 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
500ea70d | 1036 | struct drm_i915_private *dev_priv = dev->dev_private; |
33ad6626 JN |
1037 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1038 | enum port port = intel_dig_port->port; | |
500ea70d | 1039 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
0b99836f | 1040 | const char *name = NULL; |
500ea70d | 1041 | uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL; |
ab2c0672 DA |
1042 | int ret; |
1043 | ||
500ea70d RV |
1044 | /* On SKL we don't have Aux for port E so we rely on VBT to set |
1045 | * a proper alternate aux channel. | |
1046 | */ | |
1047 | if (IS_SKYLAKE(dev) && port == PORT_E) { | |
1048 | switch (info->alternate_aux_channel) { | |
1049 | case DP_AUX_B: | |
1050 | porte_aux_ctl_reg = DPB_AUX_CH_CTL; | |
1051 | break; | |
1052 | case DP_AUX_C: | |
1053 | porte_aux_ctl_reg = DPC_AUX_CH_CTL; | |
1054 | break; | |
1055 | case DP_AUX_D: | |
1056 | porte_aux_ctl_reg = DPD_AUX_CH_CTL; | |
1057 | break; | |
1058 | case DP_AUX_A: | |
1059 | default: | |
1060 | porte_aux_ctl_reg = DPA_AUX_CH_CTL; | |
1061 | } | |
1062 | } | |
1063 | ||
33ad6626 JN |
1064 | switch (port) { |
1065 | case PORT_A: | |
1066 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
0b99836f | 1067 | name = "DPDDC-A"; |
ab2c0672 | 1068 | break; |
33ad6626 JN |
1069 | case PORT_B: |
1070 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
0b99836f | 1071 | name = "DPDDC-B"; |
ab2c0672 | 1072 | break; |
33ad6626 JN |
1073 | case PORT_C: |
1074 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
0b99836f | 1075 | name = "DPDDC-C"; |
ab2c0672 | 1076 | break; |
33ad6626 JN |
1077 | case PORT_D: |
1078 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
0b99836f | 1079 | name = "DPDDC-D"; |
33ad6626 | 1080 | break; |
500ea70d RV |
1081 | case PORT_E: |
1082 | intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg; | |
1083 | name = "DPDDC-E"; | |
1084 | break; | |
33ad6626 JN |
1085 | default: |
1086 | BUG(); | |
ab2c0672 DA |
1087 | } |
1088 | ||
1b1aad75 DL |
1089 | /* |
1090 | * The AUX_CTL register is usually DP_CTL + 0x10. | |
1091 | * | |
1092 | * On Haswell and Broadwell though: | |
1093 | * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU | |
1094 | * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU | |
1095 | * | |
1096 | * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU. | |
1097 | */ | |
500ea70d | 1098 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E) |
33ad6626 | 1099 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
8316f337 | 1100 | |
0b99836f | 1101 | intel_dp->aux.name = name; |
9d1a1031 JN |
1102 | intel_dp->aux.dev = dev->dev; |
1103 | intel_dp->aux.transfer = intel_dp_aux_transfer; | |
8316f337 | 1104 | |
0b99836f JN |
1105 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
1106 | connector->base.kdev->kobj.name); | |
8316f337 | 1107 | |
4f71d0cb | 1108 | ret = drm_dp_aux_register(&intel_dp->aux); |
0b99836f | 1109 | if (ret < 0) { |
4f71d0cb | 1110 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
0b99836f JN |
1111 | name, ret); |
1112 | return; | |
ab2c0672 | 1113 | } |
8a5e6aeb | 1114 | |
0b99836f JN |
1115 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
1116 | &intel_dp->aux.ddc.dev.kobj, | |
1117 | intel_dp->aux.ddc.dev.kobj.name); | |
1118 | if (ret < 0) { | |
1119 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); | |
4f71d0cb | 1120 | drm_dp_aux_unregister(&intel_dp->aux); |
ab2c0672 | 1121 | } |
a4fc5ed6 KP |
1122 | } |
1123 | ||
80f65de3 ID |
1124 | static void |
1125 | intel_dp_connector_unregister(struct intel_connector *intel_connector) | |
1126 | { | |
1127 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); | |
1128 | ||
0e32b39c DA |
1129 | if (!intel_connector->mst_port) |
1130 | sysfs_remove_link(&intel_connector->base.kdev->kobj, | |
1131 | intel_dp->aux.ddc.dev.kobj.name); | |
80f65de3 ID |
1132 | intel_connector_unregister(intel_connector); |
1133 | } | |
1134 | ||
5416d871 | 1135 | static void |
c3346ef6 | 1136 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) |
5416d871 DL |
1137 | { |
1138 | u32 ctrl1; | |
1139 | ||
dd3cd74a ACO |
1140 | memset(&pipe_config->dpll_hw_state, 0, |
1141 | sizeof(pipe_config->dpll_hw_state)); | |
1142 | ||
5416d871 DL |
1143 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
1144 | pipe_config->dpll_hw_state.cfgcr1 = 0; | |
1145 | pipe_config->dpll_hw_state.cfgcr2 = 0; | |
1146 | ||
1147 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
c3346ef6 SJ |
1148 | switch (link_clock / 2) { |
1149 | case 81000: | |
71cd8423 | 1150 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
5416d871 DL |
1151 | SKL_DPLL0); |
1152 | break; | |
c3346ef6 | 1153 | case 135000: |
71cd8423 | 1154 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
5416d871 DL |
1155 | SKL_DPLL0); |
1156 | break; | |
c3346ef6 | 1157 | case 270000: |
71cd8423 | 1158 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
5416d871 DL |
1159 | SKL_DPLL0); |
1160 | break; | |
c3346ef6 | 1161 | case 162000: |
71cd8423 | 1162 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
c3346ef6 SJ |
1163 | SKL_DPLL0); |
1164 | break; | |
1165 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which | |
1166 | results in CDCLK change. Need to handle the change of CDCLK by | |
1167 | disabling pipes and re-enabling them */ | |
1168 | case 108000: | |
71cd8423 | 1169 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
c3346ef6 SJ |
1170 | SKL_DPLL0); |
1171 | break; | |
1172 | case 216000: | |
71cd8423 | 1173 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
c3346ef6 SJ |
1174 | SKL_DPLL0); |
1175 | break; | |
1176 | ||
5416d871 DL |
1177 | } |
1178 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; | |
1179 | } | |
1180 | ||
0e50338c | 1181 | static void |
5cec258b | 1182 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) |
0e50338c | 1183 | { |
ee46f3c7 ACO |
1184 | memset(&pipe_config->dpll_hw_state, 0, |
1185 | sizeof(pipe_config->dpll_hw_state)); | |
1186 | ||
0e50338c DV |
1187 | switch (link_bw) { |
1188 | case DP_LINK_BW_1_62: | |
1189 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
1190 | break; | |
1191 | case DP_LINK_BW_2_7: | |
1192 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
1193 | break; | |
1194 | case DP_LINK_BW_5_4: | |
1195 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
1196 | break; | |
1197 | } | |
1198 | } | |
1199 | ||
fc0f8e25 | 1200 | static int |
12f6a2e2 | 1201 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
fc0f8e25 | 1202 | { |
94ca719e VS |
1203 | if (intel_dp->num_sink_rates) { |
1204 | *sink_rates = intel_dp->sink_rates; | |
1205 | return intel_dp->num_sink_rates; | |
fc0f8e25 | 1206 | } |
12f6a2e2 VS |
1207 | |
1208 | *sink_rates = default_rates; | |
1209 | ||
1210 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; | |
fc0f8e25 SJ |
1211 | } |
1212 | ||
a8f3ef61 | 1213 | static int |
1db10e28 | 1214 | intel_dp_source_rates(struct drm_device *dev, const int **source_rates) |
a8f3ef61 | 1215 | { |
64987fc5 SJ |
1216 | if (IS_BROXTON(dev)) { |
1217 | *source_rates = bxt_rates; | |
1218 | return ARRAY_SIZE(bxt_rates); | |
1219 | } else if (IS_SKYLAKE(dev)) { | |
637a9c63 SJ |
1220 | *source_rates = skl_rates; |
1221 | return ARRAY_SIZE(skl_rates); | |
fe51bfb9 VS |
1222 | } else if (IS_CHERRYVIEW(dev)) { |
1223 | *source_rates = chv_rates; | |
1224 | return ARRAY_SIZE(chv_rates); | |
a8f3ef61 | 1225 | } |
636280ba VS |
1226 | |
1227 | *source_rates = default_rates; | |
1228 | ||
1db10e28 VS |
1229 | if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) |
1230 | /* WaDisableHBR2:skl */ | |
1231 | return (DP_LINK_BW_2_7 >> 3) + 1; | |
1232 | else if (INTEL_INFO(dev)->gen >= 8 || | |
1233 | (IS_HASWELL(dev) && !IS_HSW_ULX(dev))) | |
1234 | return (DP_LINK_BW_5_4 >> 3) + 1; | |
1235 | else | |
1236 | return (DP_LINK_BW_2_7 >> 3) + 1; | |
a8f3ef61 SJ |
1237 | } |
1238 | ||
c6bb3538 DV |
1239 | static void |
1240 | intel_dp_set_clock(struct intel_encoder *encoder, | |
5cec258b | 1241 | struct intel_crtc_state *pipe_config, int link_bw) |
c6bb3538 DV |
1242 | { |
1243 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
1244 | const struct dp_link_dpll *divisor = NULL; |
1245 | int i, count = 0; | |
c6bb3538 DV |
1246 | |
1247 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
1248 | divisor = gen4_dpll; |
1249 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 | 1250 | } else if (HAS_PCH_SPLIT(dev)) { |
9dd4ffdf CML |
1251 | divisor = pch_dpll; |
1252 | count = ARRAY_SIZE(pch_dpll); | |
ef9348c8 CML |
1253 | } else if (IS_CHERRYVIEW(dev)) { |
1254 | divisor = chv_dpll; | |
1255 | count = ARRAY_SIZE(chv_dpll); | |
c6bb3538 | 1256 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
1257 | divisor = vlv_dpll; |
1258 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1259 | } |
9dd4ffdf CML |
1260 | |
1261 | if (divisor && count) { | |
1262 | for (i = 0; i < count; i++) { | |
1263 | if (link_bw == divisor[i].link_bw) { | |
1264 | pipe_config->dpll = divisor[i].dpll; | |
1265 | pipe_config->clock_set = true; | |
1266 | break; | |
1267 | } | |
1268 | } | |
c6bb3538 DV |
1269 | } |
1270 | } | |
1271 | ||
2ecae76a VS |
1272 | static int intersect_rates(const int *source_rates, int source_len, |
1273 | const int *sink_rates, int sink_len, | |
94ca719e | 1274 | int *common_rates) |
a8f3ef61 SJ |
1275 | { |
1276 | int i = 0, j = 0, k = 0; | |
1277 | ||
a8f3ef61 SJ |
1278 | while (i < source_len && j < sink_len) { |
1279 | if (source_rates[i] == sink_rates[j]) { | |
e6bda3e4 VS |
1280 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1281 | return k; | |
94ca719e | 1282 | common_rates[k] = source_rates[i]; |
a8f3ef61 SJ |
1283 | ++k; |
1284 | ++i; | |
1285 | ++j; | |
1286 | } else if (source_rates[i] < sink_rates[j]) { | |
1287 | ++i; | |
1288 | } else { | |
1289 | ++j; | |
1290 | } | |
1291 | } | |
1292 | return k; | |
1293 | } | |
1294 | ||
94ca719e VS |
1295 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1296 | int *common_rates) | |
2ecae76a VS |
1297 | { |
1298 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1299 | const int *source_rates, *sink_rates; | |
1300 | int source_len, sink_len; | |
1301 | ||
1302 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1303 | source_len = intel_dp_source_rates(dev, &source_rates); | |
1304 | ||
1305 | return intersect_rates(source_rates, source_len, | |
1306 | sink_rates, sink_len, | |
94ca719e | 1307 | common_rates); |
2ecae76a VS |
1308 | } |
1309 | ||
0336400e VS |
1310 | static void snprintf_int_array(char *str, size_t len, |
1311 | const int *array, int nelem) | |
1312 | { | |
1313 | int i; | |
1314 | ||
1315 | str[0] = '\0'; | |
1316 | ||
1317 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1318 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1319 | if (r >= len) |
1320 | return; | |
1321 | str += r; | |
1322 | len -= r; | |
1323 | } | |
1324 | } | |
1325 | ||
1326 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1327 | { | |
1328 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1329 | const int *source_rates, *sink_rates; | |
94ca719e VS |
1330 | int source_len, sink_len, common_len; |
1331 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1332 | char str[128]; /* FIXME: too big for stack? */ |
1333 | ||
1334 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1335 | return; | |
1336 | ||
1337 | source_len = intel_dp_source_rates(dev, &source_rates); | |
1338 | snprintf_int_array(str, sizeof(str), source_rates, source_len); | |
1339 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1340 | ||
1341 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1342 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1343 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1344 | ||
94ca719e VS |
1345 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1346 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1347 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1348 | } |
1349 | ||
f4896f15 | 1350 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1351 | { |
1352 | int i = 0; | |
1353 | ||
1354 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1355 | if (find == rates[i]) | |
1356 | break; | |
1357 | ||
1358 | return i; | |
1359 | } | |
1360 | ||
50fec21a VS |
1361 | int |
1362 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1363 | { | |
1364 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1365 | int len; | |
1366 | ||
94ca719e | 1367 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1368 | if (WARN_ON(len <= 0)) |
1369 | return 162000; | |
1370 | ||
1371 | return rates[rate_to_index(0, rates) - 1]; | |
1372 | } | |
1373 | ||
ed4e9c1d VS |
1374 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1375 | { | |
94ca719e | 1376 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1377 | } |
1378 | ||
00c09d70 | 1379 | bool |
5bfe2ac0 | 1380 | intel_dp_compute_config(struct intel_encoder *encoder, |
5cec258b | 1381 | struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 1382 | { |
5bfe2ac0 | 1383 | struct drm_device *dev = encoder->base.dev; |
36008365 | 1384 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 1385 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1386 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1387 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1388 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1389 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1390 | int lane_count, clock; |
56071a20 | 1391 | int min_lane_count = 1; |
eeb6324d | 1392 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1393 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1394 | int min_clock = 0; |
a8f3ef61 | 1395 | int max_clock; |
083f9560 | 1396 | int bpp, mode_rate; |
ff9a6750 | 1397 | int link_avail, link_clock; |
94ca719e VS |
1398 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1399 | int common_len; | |
a8f3ef61 | 1400 | |
94ca719e | 1401 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1402 | |
1403 | /* No common link rates between source and sink */ | |
94ca719e | 1404 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1405 | |
94ca719e | 1406 | max_clock = common_len - 1; |
a4fc5ed6 | 1407 | |
bc7d38a4 | 1408 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
1409 | pipe_config->has_pch_encoder = true; |
1410 | ||
03afc4a2 | 1411 | pipe_config->has_dp_encoder = true; |
f769cd24 | 1412 | pipe_config->has_drrs = false; |
9fcb1704 | 1413 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1414 | |
dd06f90e JN |
1415 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1416 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1417 | adjusted_mode); | |
a1b2278e CK |
1418 | |
1419 | if (INTEL_INFO(dev)->gen >= 9) { | |
1420 | int ret; | |
e435d6e5 | 1421 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1422 | if (ret) |
1423 | return ret; | |
1424 | } | |
1425 | ||
2dd24552 JB |
1426 | if (!HAS_PCH_SPLIT(dev)) |
1427 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
1428 | intel_connector->panel.fitting_mode); | |
1429 | else | |
b074cec8 JB |
1430 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1431 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1432 | } |
1433 | ||
cb1793ce | 1434 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1435 | return false; |
1436 | ||
083f9560 | 1437 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1438 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1439 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1440 | adjusted_mode->crtc_clock); |
083f9560 | 1441 | |
36008365 DV |
1442 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1443 | * bpc in between. */ | |
3e7ca985 | 1444 | bpp = pipe_config->pipe_bpp; |
56071a20 | 1445 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1446 | |
1447 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1448 | if (intel_connector->base.display_info.bpc == 0 && | |
1449 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { | |
56071a20 JN |
1450 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1451 | dev_priv->vbt.edp_bpp); | |
1452 | bpp = dev_priv->vbt.edp_bpp; | |
1453 | } | |
1454 | ||
344c5bbc JN |
1455 | /* |
1456 | * Use the maximum clock and number of lanes the eDP panel | |
1457 | * advertizes being capable of. The panels are generally | |
1458 | * designed to support only a single clock and lane | |
1459 | * configuration, and typically these values correspond to the | |
1460 | * native resolution of the panel. | |
1461 | */ | |
1462 | min_lane_count = max_lane_count; | |
1463 | min_clock = max_clock; | |
7984211e | 1464 | } |
657445fe | 1465 | |
36008365 | 1466 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1467 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1468 | bpp); | |
36008365 | 1469 | |
c6930992 | 1470 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1471 | for (lane_count = min_lane_count; |
1472 | lane_count <= max_lane_count; | |
1473 | lane_count <<= 1) { | |
1474 | ||
94ca719e | 1475 | link_clock = common_rates[clock]; |
36008365 DV |
1476 | link_avail = intel_dp_max_data_rate(link_clock, |
1477 | lane_count); | |
1478 | ||
1479 | if (mode_rate <= link_avail) { | |
1480 | goto found; | |
1481 | } | |
1482 | } | |
1483 | } | |
1484 | } | |
c4867936 | 1485 | |
36008365 | 1486 | return false; |
3685a8f3 | 1487 | |
36008365 | 1488 | found: |
55bc60db VS |
1489 | if (intel_dp->color_range_auto) { |
1490 | /* | |
1491 | * See: | |
1492 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1493 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1494 | */ | |
18316c8c | 1495 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
1496 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
1497 | else | |
1498 | intel_dp->color_range = 0; | |
1499 | } | |
1500 | ||
3685a8f3 | 1501 | if (intel_dp->color_range) |
50f3b016 | 1502 | pipe_config->limited_color_range = true; |
a4fc5ed6 | 1503 | |
36008365 | 1504 | intel_dp->lane_count = lane_count; |
a8f3ef61 | 1505 | |
94ca719e | 1506 | if (intel_dp->num_sink_rates) { |
bc27b7d3 | 1507 | intel_dp->link_bw = 0; |
a8f3ef61 | 1508 | intel_dp->rate_select = |
94ca719e | 1509 | intel_dp_rate_select(intel_dp, common_rates[clock]); |
bc27b7d3 VS |
1510 | } else { |
1511 | intel_dp->link_bw = | |
94ca719e | 1512 | drm_dp_link_rate_to_bw_code(common_rates[clock]); |
bc27b7d3 | 1513 | intel_dp->rate_select = 0; |
a8f3ef61 SJ |
1514 | } |
1515 | ||
657445fe | 1516 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1517 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1518 | |
36008365 DV |
1519 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
1520 | intel_dp->link_bw, intel_dp->lane_count, | |
ff9a6750 | 1521 | pipe_config->port_clock, bpp); |
36008365 DV |
1522 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1523 | mode_rate, link_avail); | |
a4fc5ed6 | 1524 | |
03afc4a2 | 1525 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1526 | adjusted_mode->crtc_clock, |
1527 | pipe_config->port_clock, | |
03afc4a2 | 1528 | &pipe_config->dp_m_n); |
9d1a455b | 1529 | |
439d7ac0 | 1530 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1531 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1532 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1533 | intel_link_compute_m_n(bpp, lane_count, |
1534 | intel_connector->panel.downclock_mode->clock, | |
1535 | pipe_config->port_clock, | |
1536 | &pipe_config->dp_m2_n2); | |
1537 | } | |
1538 | ||
5416d871 | 1539 | if (IS_SKYLAKE(dev) && is_edp(intel_dp)) |
94ca719e | 1540 | skl_edp_set_pll_config(pipe_config, common_rates[clock]); |
977bb38d S |
1541 | else if (IS_BROXTON(dev)) |
1542 | /* handled in ddi */; | |
5416d871 | 1543 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
0e50338c DV |
1544 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
1545 | else | |
1546 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); | |
c6bb3538 | 1547 | |
03afc4a2 | 1548 | return true; |
a4fc5ed6 KP |
1549 | } |
1550 | ||
7c62a164 | 1551 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
ea9b6006 | 1552 | { |
7c62a164 DV |
1553 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1554 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
1555 | struct drm_device *dev = crtc->base.dev; | |
ea9b6006 DV |
1556 | struct drm_i915_private *dev_priv = dev->dev_private; |
1557 | u32 dpa_ctl; | |
1558 | ||
6e3c9717 ACO |
1559 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", |
1560 | crtc->config->port_clock); | |
ea9b6006 DV |
1561 | dpa_ctl = I915_READ(DP_A); |
1562 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1563 | ||
6e3c9717 | 1564 | if (crtc->config->port_clock == 162000) { |
1ce17038 DV |
1565 | /* For a long time we've carried around a ILK-DevA w/a for the |
1566 | * 160MHz clock. If we're really unlucky, it's still required. | |
1567 | */ | |
1568 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 1569 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
7c62a164 | 1570 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
1571 | } else { |
1572 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
7c62a164 | 1573 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
ea9b6006 | 1574 | } |
1ce17038 | 1575 | |
ea9b6006 DV |
1576 | I915_WRITE(DP_A, dpa_ctl); |
1577 | ||
1578 | POSTING_READ(DP_A); | |
1579 | udelay(500); | |
1580 | } | |
1581 | ||
8ac33ed3 | 1582 | static void intel_dp_prepare(struct intel_encoder *encoder) |
a4fc5ed6 | 1583 | { |
b934223d | 1584 | struct drm_device *dev = encoder->base.dev; |
417e822d | 1585 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 1586 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1587 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1588 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
6e3c9717 | 1589 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
a4fc5ed6 | 1590 | |
417e822d | 1591 | /* |
1a2eb460 | 1592 | * There are four kinds of DP registers: |
417e822d KP |
1593 | * |
1594 | * IBX PCH | |
1a2eb460 KP |
1595 | * SNB CPU |
1596 | * IVB CPU | |
417e822d KP |
1597 | * CPT PCH |
1598 | * | |
1599 | * IBX PCH and CPU are the same for almost everything, | |
1600 | * except that the CPU DP PLL is configured in this | |
1601 | * register | |
1602 | * | |
1603 | * CPT PCH is quite different, having many bits moved | |
1604 | * to the TRANS_DP_CTL register instead. That | |
1605 | * configuration happens (oddly) in ironlake_pch_enable | |
1606 | */ | |
9c9e7927 | 1607 | |
417e822d KP |
1608 | /* Preserve the BIOS-computed detected bit. This is |
1609 | * supposed to be read-only. | |
1610 | */ | |
1611 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1612 | |
417e822d | 1613 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1614 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
17aa6be9 | 1615 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
a4fc5ed6 | 1616 | |
6e3c9717 | 1617 | if (crtc->config->has_audio) |
ea5b213a | 1618 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
247d89f6 | 1619 | |
417e822d | 1620 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1621 | |
39e5fa88 | 1622 | if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
1623 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1624 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1625 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1626 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1627 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1628 | ||
6aba5b6c | 1629 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1630 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1631 | ||
7c62a164 | 1632 | intel_dp->DP |= crtc->pipe << 29; |
39e5fa88 | 1633 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
e3ef4479 VS |
1634 | u32 trans_dp; |
1635 | ||
39e5fa88 | 1636 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1637 | |
1638 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1639 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1640 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1641 | else | |
1642 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1643 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1644 | } else { |
b2634017 | 1645 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 1646 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
1647 | |
1648 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1649 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1650 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1651 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1652 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1653 | ||
6aba5b6c | 1654 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1655 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1656 | ||
39e5fa88 | 1657 | if (IS_CHERRYVIEW(dev)) |
44f37d1f | 1658 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1659 | else if (crtc->pipe == PIPE_B) |
1660 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1661 | } |
a4fc5ed6 KP |
1662 | } |
1663 | ||
ffd6749d PZ |
1664 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1665 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1666 | |
1a5ef5b7 PZ |
1667 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1668 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1669 | |
ffd6749d PZ |
1670 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1671 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1672 | |
4be73780 | 1673 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1674 | u32 mask, |
1675 | u32 value) | |
bd943159 | 1676 | { |
30add22d | 1677 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1678 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
1679 | u32 pp_stat_reg, pp_ctrl_reg; |
1680 | ||
e39b999a VS |
1681 | lockdep_assert_held(&dev_priv->pps_mutex); |
1682 | ||
bf13e81b JN |
1683 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1684 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1685 | |
99ea7127 | 1686 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1687 | mask, value, |
1688 | I915_READ(pp_stat_reg), | |
1689 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1690 | |
453c5420 | 1691 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 1692 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1693 | I915_READ(pp_stat_reg), |
1694 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1695 | } |
54c136d4 CW |
1696 | |
1697 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1698 | } |
32ce697c | 1699 | |
4be73780 | 1700 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1701 | { |
1702 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1703 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1704 | } |
1705 | ||
4be73780 | 1706 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1707 | { |
1708 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1709 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1710 | } |
1711 | ||
4be73780 | 1712 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 KP |
1713 | { |
1714 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
dce56b3c PZ |
1715 | |
1716 | /* When we disable the VDD override bit last we have to do the manual | |
1717 | * wait. */ | |
1718 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, | |
1719 | intel_dp->panel_power_cycle_delay); | |
1720 | ||
4be73780 | 1721 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1722 | } |
1723 | ||
4be73780 | 1724 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1725 | { |
1726 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1727 | intel_dp->backlight_on_delay); | |
1728 | } | |
1729 | ||
4be73780 | 1730 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1731 | { |
1732 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1733 | intel_dp->backlight_off_delay); | |
1734 | } | |
99ea7127 | 1735 | |
832dd3c1 KP |
1736 | /* Read the current pp_control value, unlocking the register if it |
1737 | * is locked | |
1738 | */ | |
1739 | ||
453c5420 | 1740 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1741 | { |
453c5420 JB |
1742 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1744 | u32 control; | |
832dd3c1 | 1745 | |
e39b999a VS |
1746 | lockdep_assert_held(&dev_priv->pps_mutex); |
1747 | ||
bf13e81b | 1748 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
b0a08bec VK |
1749 | if (!IS_BROXTON(dev)) { |
1750 | control &= ~PANEL_UNLOCK_MASK; | |
1751 | control |= PANEL_UNLOCK_REGS; | |
1752 | } | |
832dd3c1 | 1753 | return control; |
bd943159 KP |
1754 | } |
1755 | ||
951468f3 VS |
1756 | /* |
1757 | * Must be paired with edp_panel_vdd_off(). | |
1758 | * Must hold pps_mutex around the whole on/off sequence. | |
1759 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1760 | */ | |
1e0560e0 | 1761 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1762 | { |
30add22d | 1763 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1764 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1765 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5d613501 | 1766 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1767 | enum intel_display_power_domain power_domain; |
5d613501 | 1768 | u32 pp; |
453c5420 | 1769 | u32 pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1770 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1771 | |
e39b999a VS |
1772 | lockdep_assert_held(&dev_priv->pps_mutex); |
1773 | ||
97af61f5 | 1774 | if (!is_edp(intel_dp)) |
adddaaf4 | 1775 | return false; |
bd943159 | 1776 | |
2c623c11 | 1777 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 1778 | intel_dp->want_panel_vdd = true; |
99ea7127 | 1779 | |
4be73780 | 1780 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1781 | return need_to_disable; |
b0665d57 | 1782 | |
4e6e1a54 ID |
1783 | power_domain = intel_display_port_power_domain(intel_encoder); |
1784 | intel_display_power_get(dev_priv, power_domain); | |
e9cb81a2 | 1785 | |
3936fcf4 VS |
1786 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1787 | port_name(intel_dig_port->port)); | |
bd943159 | 1788 | |
4be73780 DV |
1789 | if (!edp_have_panel_power(intel_dp)) |
1790 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1791 | |
453c5420 | 1792 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1793 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1794 | |
bf13e81b JN |
1795 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1796 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1797 | |
1798 | I915_WRITE(pp_ctrl_reg, pp); | |
1799 | POSTING_READ(pp_ctrl_reg); | |
1800 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1801 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1802 | /* |
1803 | * If the panel wasn't on, delay before accessing aux channel | |
1804 | */ | |
4be73780 | 1805 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1806 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1807 | port_name(intel_dig_port->port)); | |
f01eca2e | 1808 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1809 | } |
adddaaf4 JN |
1810 | |
1811 | return need_to_disable; | |
1812 | } | |
1813 | ||
951468f3 VS |
1814 | /* |
1815 | * Must be paired with intel_edp_panel_vdd_off() or | |
1816 | * intel_edp_panel_off(). | |
1817 | * Nested calls to these functions are not allowed since | |
1818 | * we drop the lock. Caller must use some higher level | |
1819 | * locking to prevent nested calls from other threads. | |
1820 | */ | |
b80d6c78 | 1821 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 1822 | { |
c695b6b6 | 1823 | bool vdd; |
adddaaf4 | 1824 | |
c695b6b6 VS |
1825 | if (!is_edp(intel_dp)) |
1826 | return; | |
1827 | ||
773538e8 | 1828 | pps_lock(intel_dp); |
c695b6b6 | 1829 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 1830 | pps_unlock(intel_dp); |
c695b6b6 | 1831 | |
e2c719b7 | 1832 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 1833 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
1834 | } |
1835 | ||
4be73780 | 1836 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1837 | { |
30add22d | 1838 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 | 1839 | struct drm_i915_private *dev_priv = dev->dev_private; |
be2c9196 VS |
1840 | struct intel_digital_port *intel_dig_port = |
1841 | dp_to_dig_port(intel_dp); | |
1842 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1843 | enum intel_display_power_domain power_domain; | |
5d613501 | 1844 | u32 pp; |
453c5420 | 1845 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1846 | |
e39b999a | 1847 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 1848 | |
15e899a0 | 1849 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 1850 | |
15e899a0 | 1851 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 1852 | return; |
b0665d57 | 1853 | |
3936fcf4 VS |
1854 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1855 | port_name(intel_dig_port->port)); | |
bd943159 | 1856 | |
be2c9196 VS |
1857 | pp = ironlake_get_pp_control(intel_dp); |
1858 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 1859 | |
be2c9196 VS |
1860 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1861 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 1862 | |
be2c9196 VS |
1863 | I915_WRITE(pp_ctrl_reg, pp); |
1864 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 1865 | |
be2c9196 VS |
1866 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1867 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1868 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 1869 | |
be2c9196 VS |
1870 | if ((pp & POWER_TARGET_ON) == 0) |
1871 | intel_dp->last_power_cycle = jiffies; | |
e9cb81a2 | 1872 | |
be2c9196 VS |
1873 | power_domain = intel_display_port_power_domain(intel_encoder); |
1874 | intel_display_power_put(dev_priv, power_domain); | |
bd943159 | 1875 | } |
5d613501 | 1876 | |
4be73780 | 1877 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1878 | { |
1879 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1880 | struct intel_dp, panel_vdd_work); | |
bd943159 | 1881 | |
773538e8 | 1882 | pps_lock(intel_dp); |
15e899a0 VS |
1883 | if (!intel_dp->want_panel_vdd) |
1884 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 1885 | pps_unlock(intel_dp); |
bd943159 KP |
1886 | } |
1887 | ||
aba86890 ID |
1888 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1889 | { | |
1890 | unsigned long delay; | |
1891 | ||
1892 | /* | |
1893 | * Queue the timer to fire a long time from now (relative to the power | |
1894 | * down delay) to keep the panel power up across a sequence of | |
1895 | * operations. | |
1896 | */ | |
1897 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
1898 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
1899 | } | |
1900 | ||
951468f3 VS |
1901 | /* |
1902 | * Must be paired with edp_panel_vdd_on(). | |
1903 | * Must hold pps_mutex around the whole on/off sequence. | |
1904 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1905 | */ | |
4be73780 | 1906 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1907 | { |
e39b999a VS |
1908 | struct drm_i915_private *dev_priv = |
1909 | intel_dp_to_dev(intel_dp)->dev_private; | |
1910 | ||
1911 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1912 | ||
97af61f5 KP |
1913 | if (!is_edp(intel_dp)) |
1914 | return; | |
5d613501 | 1915 | |
e2c719b7 | 1916 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 1917 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 1918 | |
bd943159 KP |
1919 | intel_dp->want_panel_vdd = false; |
1920 | ||
aba86890 | 1921 | if (sync) |
4be73780 | 1922 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
1923 | else |
1924 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
1925 | } |
1926 | ||
9f0fb5be | 1927 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1928 | { |
30add22d | 1929 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1930 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1931 | u32 pp; |
453c5420 | 1932 | u32 pp_ctrl_reg; |
9934c132 | 1933 | |
9f0fb5be VS |
1934 | lockdep_assert_held(&dev_priv->pps_mutex); |
1935 | ||
97af61f5 | 1936 | if (!is_edp(intel_dp)) |
bd943159 | 1937 | return; |
99ea7127 | 1938 | |
3936fcf4 VS |
1939 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
1940 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 1941 | |
e7a89ace VS |
1942 | if (WARN(edp_have_panel_power(intel_dp), |
1943 | "eDP port %c panel power already on\n", | |
1944 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 1945 | return; |
9934c132 | 1946 | |
4be73780 | 1947 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1948 | |
bf13e81b | 1949 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1950 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1951 | if (IS_GEN5(dev)) { |
1952 | /* ILK workaround: disable reset around power sequence */ | |
1953 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1954 | I915_WRITE(pp_ctrl_reg, pp); |
1955 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1956 | } |
37c6c9b0 | 1957 | |
1c0ae80a | 1958 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1959 | if (!IS_GEN5(dev)) |
1960 | pp |= PANEL_POWER_RESET; | |
1961 | ||
453c5420 JB |
1962 | I915_WRITE(pp_ctrl_reg, pp); |
1963 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1964 | |
4be73780 | 1965 | wait_panel_on(intel_dp); |
dce56b3c | 1966 | intel_dp->last_power_on = jiffies; |
9934c132 | 1967 | |
05ce1a49 KP |
1968 | if (IS_GEN5(dev)) { |
1969 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1970 | I915_WRITE(pp_ctrl_reg, pp); |
1971 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1972 | } |
9f0fb5be | 1973 | } |
e39b999a | 1974 | |
9f0fb5be VS |
1975 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1976 | { | |
1977 | if (!is_edp(intel_dp)) | |
1978 | return; | |
1979 | ||
1980 | pps_lock(intel_dp); | |
1981 | edp_panel_on(intel_dp); | |
773538e8 | 1982 | pps_unlock(intel_dp); |
9934c132 JB |
1983 | } |
1984 | ||
9f0fb5be VS |
1985 | |
1986 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 1987 | { |
4e6e1a54 ID |
1988 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1989 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 1990 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1991 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1992 | enum intel_display_power_domain power_domain; |
99ea7127 | 1993 | u32 pp; |
453c5420 | 1994 | u32 pp_ctrl_reg; |
9934c132 | 1995 | |
9f0fb5be VS |
1996 | lockdep_assert_held(&dev_priv->pps_mutex); |
1997 | ||
97af61f5 KP |
1998 | if (!is_edp(intel_dp)) |
1999 | return; | |
37c6c9b0 | 2000 | |
3936fcf4 VS |
2001 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2002 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2003 | |
3936fcf4 VS |
2004 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2005 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2006 | |
453c5420 | 2007 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2008 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2009 | * panels get very unhappy and cease to work. */ | |
b3064154 PJ |
2010 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2011 | EDP_BLC_ENABLE); | |
453c5420 | 2012 | |
bf13e81b | 2013 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2014 | |
849e39f5 PZ |
2015 | intel_dp->want_panel_vdd = false; |
2016 | ||
453c5420 JB |
2017 | I915_WRITE(pp_ctrl_reg, pp); |
2018 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2019 | |
dce56b3c | 2020 | intel_dp->last_power_cycle = jiffies; |
4be73780 | 2021 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2022 | |
2023 | /* We got a reference when we enabled the VDD. */ | |
4e6e1a54 ID |
2024 | power_domain = intel_display_port_power_domain(intel_encoder); |
2025 | intel_display_power_put(dev_priv, power_domain); | |
9f0fb5be | 2026 | } |
e39b999a | 2027 | |
9f0fb5be VS |
2028 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2029 | { | |
2030 | if (!is_edp(intel_dp)) | |
2031 | return; | |
e39b999a | 2032 | |
9f0fb5be VS |
2033 | pps_lock(intel_dp); |
2034 | edp_panel_off(intel_dp); | |
773538e8 | 2035 | pps_unlock(intel_dp); |
9934c132 JB |
2036 | } |
2037 | ||
1250d107 JN |
2038 | /* Enable backlight in the panel power control. */ |
2039 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2040 | { |
da63a9f2 PZ |
2041 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2042 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
2043 | struct drm_i915_private *dev_priv = dev->dev_private; |
2044 | u32 pp; | |
453c5420 | 2045 | u32 pp_ctrl_reg; |
32f9d658 | 2046 | |
01cb9ea6 JB |
2047 | /* |
2048 | * If we enable the backlight right away following a panel power | |
2049 | * on, we may see slight flicker as the panel syncs with the eDP | |
2050 | * link. So delay a bit to make sure the image is solid before | |
2051 | * allowing it to appear. | |
2052 | */ | |
4be73780 | 2053 | wait_backlight_on(intel_dp); |
e39b999a | 2054 | |
773538e8 | 2055 | pps_lock(intel_dp); |
e39b999a | 2056 | |
453c5420 | 2057 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2058 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2059 | |
bf13e81b | 2060 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2061 | |
2062 | I915_WRITE(pp_ctrl_reg, pp); | |
2063 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2064 | |
773538e8 | 2065 | pps_unlock(intel_dp); |
32f9d658 ZW |
2066 | } |
2067 | ||
1250d107 JN |
2068 | /* Enable backlight PWM and backlight PP control. */ |
2069 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2070 | { | |
2071 | if (!is_edp(intel_dp)) | |
2072 | return; | |
2073 | ||
2074 | DRM_DEBUG_KMS("\n"); | |
2075 | ||
2076 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2077 | _intel_edp_backlight_on(intel_dp); | |
2078 | } | |
2079 | ||
2080 | /* Disable backlight in the panel power control. */ | |
2081 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2082 | { |
30add22d | 2083 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
2084 | struct drm_i915_private *dev_priv = dev->dev_private; |
2085 | u32 pp; | |
453c5420 | 2086 | u32 pp_ctrl_reg; |
32f9d658 | 2087 | |
f01eca2e KP |
2088 | if (!is_edp(intel_dp)) |
2089 | return; | |
2090 | ||
773538e8 | 2091 | pps_lock(intel_dp); |
e39b999a | 2092 | |
453c5420 | 2093 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2094 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2095 | |
bf13e81b | 2096 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2097 | |
2098 | I915_WRITE(pp_ctrl_reg, pp); | |
2099 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2100 | |
773538e8 | 2101 | pps_unlock(intel_dp); |
e39b999a VS |
2102 | |
2103 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2104 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2105 | } |
f7d2323c | 2106 | |
1250d107 JN |
2107 | /* Disable backlight PP control and backlight PWM. */ |
2108 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2109 | { | |
2110 | if (!is_edp(intel_dp)) | |
2111 | return; | |
2112 | ||
2113 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2114 | |
1250d107 | 2115 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2116 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2117 | } |
a4fc5ed6 | 2118 | |
73580fb7 JN |
2119 | /* |
2120 | * Hook for controlling the panel power control backlight through the bl_power | |
2121 | * sysfs attribute. Take care to handle multiple calls. | |
2122 | */ | |
2123 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2124 | bool enable) | |
2125 | { | |
2126 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2127 | bool is_enabled; |
2128 | ||
773538e8 | 2129 | pps_lock(intel_dp); |
e39b999a | 2130 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2131 | pps_unlock(intel_dp); |
73580fb7 JN |
2132 | |
2133 | if (is_enabled == enable) | |
2134 | return; | |
2135 | ||
23ba9373 JN |
2136 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2137 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2138 | |
2139 | if (enable) | |
2140 | _intel_edp_backlight_on(intel_dp); | |
2141 | else | |
2142 | _intel_edp_backlight_off(intel_dp); | |
2143 | } | |
2144 | ||
2bd2ad64 | 2145 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 2146 | { |
da63a9f2 PZ |
2147 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2148 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
2149 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
2150 | struct drm_i915_private *dev_priv = dev->dev_private; |
2151 | u32 dpa_ctl; | |
2152 | ||
2bd2ad64 DV |
2153 | assert_pipe_disabled(dev_priv, |
2154 | to_intel_crtc(crtc)->pipe); | |
2155 | ||
d240f20f JB |
2156 | DRM_DEBUG_KMS("\n"); |
2157 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
2158 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
2159 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
2160 | ||
2161 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
2162 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
2163 | * enable bits here to ensure that we don't enable too much. */ | |
2164 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
2165 | intel_dp->DP |= DP_PLL_ENABLE; | |
2166 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
2167 | POSTING_READ(DP_A); |
2168 | udelay(200); | |
d240f20f JB |
2169 | } |
2170 | ||
2bd2ad64 | 2171 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2172 | { |
da63a9f2 PZ |
2173 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2174 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
2175 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
2176 | struct drm_i915_private *dev_priv = dev->dev_private; |
2177 | u32 dpa_ctl; | |
2178 | ||
2bd2ad64 DV |
2179 | assert_pipe_disabled(dev_priv, |
2180 | to_intel_crtc(crtc)->pipe); | |
2181 | ||
d240f20f | 2182 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
2183 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
2184 | "dp pll off, should be on\n"); | |
2185 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
2186 | ||
2187 | /* We can't rely on the value tracked for the DP register in | |
2188 | * intel_dp->DP because link_down must not change that (otherwise link | |
2189 | * re-training will fail. */ | |
298b0b39 | 2190 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 2191 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 2192 | POSTING_READ(DP_A); |
d240f20f JB |
2193 | udelay(200); |
2194 | } | |
2195 | ||
c7ad3810 | 2196 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2197 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2198 | { |
2199 | int ret, i; | |
2200 | ||
2201 | /* Should have a valid DPCD by this point */ | |
2202 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2203 | return; | |
2204 | ||
2205 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2206 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2207 | DP_SET_POWER_D3); | |
c7ad3810 JB |
2208 | } else { |
2209 | /* | |
2210 | * When turning on, we need to retry for 1ms to give the sink | |
2211 | * time to wake up. | |
2212 | */ | |
2213 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2214 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2215 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2216 | if (ret == 1) |
2217 | break; | |
2218 | msleep(1); | |
2219 | } | |
2220 | } | |
f9cac721 JN |
2221 | |
2222 | if (ret != 1) | |
2223 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2224 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2225 | } |
2226 | ||
19d8fe15 DV |
2227 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2228 | enum pipe *pipe) | |
d240f20f | 2229 | { |
19d8fe15 | 2230 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2231 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
2232 | struct drm_device *dev = encoder->base.dev; |
2233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d129bea ID |
2234 | enum intel_display_power_domain power_domain; |
2235 | u32 tmp; | |
2236 | ||
2237 | power_domain = intel_display_port_power_domain(encoder); | |
f458ebbc | 2238 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
2239 | return false; |
2240 | ||
2241 | tmp = I915_READ(intel_dp->output_reg); | |
19d8fe15 DV |
2242 | |
2243 | if (!(tmp & DP_PORT_EN)) | |
2244 | return false; | |
2245 | ||
39e5fa88 | 2246 | if (IS_GEN7(dev) && port == PORT_A) { |
19d8fe15 | 2247 | *pipe = PORT_TO_PIPE_CPT(tmp); |
39e5fa88 | 2248 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
adc289d7 | 2249 | enum pipe p; |
19d8fe15 | 2250 | |
adc289d7 VS |
2251 | for_each_pipe(dev_priv, p) { |
2252 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2253 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2254 | *pipe = p; | |
19d8fe15 DV |
2255 | return true; |
2256 | } | |
2257 | } | |
19d8fe15 | 2258 | |
4a0833ec DV |
2259 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
2260 | intel_dp->output_reg); | |
39e5fa88 VS |
2261 | } else if (IS_CHERRYVIEW(dev)) { |
2262 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); | |
2263 | } else { | |
2264 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2265 | } |
d240f20f | 2266 | |
19d8fe15 DV |
2267 | return true; |
2268 | } | |
d240f20f | 2269 | |
045ac3b5 | 2270 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2271 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2272 | { |
2273 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2274 | u32 tmp, flags = 0; |
63000ef6 XZ |
2275 | struct drm_device *dev = encoder->base.dev; |
2276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2277 | enum port port = dp_to_dig_port(intel_dp)->port; | |
2278 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
18442d08 | 2279 | int dotclock; |
045ac3b5 | 2280 | |
9ed109a7 | 2281 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2282 | |
2283 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2284 | |
39e5fa88 VS |
2285 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2286 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
2287 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2288 | flags |= DRM_MODE_FLAG_PHSYNC; |
2289 | else | |
2290 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2291 | |
39e5fa88 | 2292 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2293 | flags |= DRM_MODE_FLAG_PVSYNC; |
2294 | else | |
2295 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2296 | } else { | |
39e5fa88 | 2297 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2298 | flags |= DRM_MODE_FLAG_PHSYNC; |
2299 | else | |
2300 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2301 | |
39e5fa88 | 2302 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2303 | flags |= DRM_MODE_FLAG_PVSYNC; |
2304 | else | |
2305 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2306 | } | |
045ac3b5 | 2307 | |
2d112de7 | 2308 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2309 | |
8c875fca VS |
2310 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2311 | tmp & DP_COLOR_RANGE_16_235) | |
2312 | pipe_config->limited_color_range = true; | |
2313 | ||
eb14cb74 VS |
2314 | pipe_config->has_dp_encoder = true; |
2315 | ||
2316 | intel_dp_get_m_n(crtc, pipe_config); | |
2317 | ||
18442d08 | 2318 | if (port == PORT_A) { |
f1f644dc JB |
2319 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
2320 | pipe_config->port_clock = 162000; | |
2321 | else | |
2322 | pipe_config->port_clock = 270000; | |
2323 | } | |
18442d08 VS |
2324 | |
2325 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
2326 | &pipe_config->dp_m_n); | |
2327 | ||
2328 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) | |
2329 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
2330 | ||
2d112de7 | 2331 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
7f16e5c1 | 2332 | |
c6cd2ee2 JN |
2333 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2334 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
2335 | /* | |
2336 | * This is a big fat ugly hack. | |
2337 | * | |
2338 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2339 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2340 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2341 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2342 | * max, not what it tells us to use. | |
2343 | * | |
2344 | * Note: This will still be broken if the eDP panel is not lit | |
2345 | * up by the BIOS, and thus we can't get the mode at module | |
2346 | * load. | |
2347 | */ | |
2348 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
2349 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
2350 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
2351 | } | |
045ac3b5 JB |
2352 | } |
2353 | ||
e8cb4558 | 2354 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2355 | { |
e8cb4558 | 2356 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2357 | struct drm_device *dev = encoder->base.dev; |
495a5bb8 JN |
2358 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2359 | ||
6e3c9717 | 2360 | if (crtc->config->has_audio) |
495a5bb8 | 2361 | intel_audio_codec_disable(encoder); |
6cb49835 | 2362 | |
b32c6f48 RV |
2363 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2364 | intel_psr_disable(intel_dp); | |
2365 | ||
6cb49835 DV |
2366 | /* Make sure the panel is off before trying to change the mode. But also |
2367 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2368 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2369 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2370 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2371 | intel_edp_panel_off(intel_dp); |
3739850b | 2372 | |
08aff3fe VS |
2373 | /* disable the port before the pipe on g4x */ |
2374 | if (INTEL_INFO(dev)->gen < 5) | |
3739850b | 2375 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2376 | } |
2377 | ||
08aff3fe | 2378 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2379 | { |
2bd2ad64 | 2380 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2381 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2382 | |
49277c31 | 2383 | intel_dp_link_down(intel_dp); |
08aff3fe VS |
2384 | if (port == PORT_A) |
2385 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2386 | } |
2387 | ||
2388 | static void vlv_post_disable_dp(struct intel_encoder *encoder) | |
2389 | { | |
2390 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2391 | ||
2392 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2393 | } |
2394 | ||
580d3811 VS |
2395 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2396 | { | |
2397 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2398 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2399 | struct drm_device *dev = encoder->base.dev; | |
2400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2401 | struct intel_crtc *intel_crtc = | |
2402 | to_intel_crtc(encoder->base.crtc); | |
2403 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
2404 | enum pipe pipe = intel_crtc->pipe; | |
2405 | u32 val; | |
2406 | ||
2407 | intel_dp_link_down(intel_dp); | |
2408 | ||
a580516d | 2409 | mutex_lock(&dev_priv->sb_lock); |
580d3811 VS |
2410 | |
2411 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 2412 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 2413 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 2414 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 2415 | |
97fd4d5c VS |
2416 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2417 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
2418 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
2419 | ||
2420 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
2421 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
2422 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
2423 | ||
2424 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 2425 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 2426 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 | 2427 | |
a580516d | 2428 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2429 | } |
2430 | ||
7b13b58a VS |
2431 | static void |
2432 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2433 | uint32_t *DP, | |
2434 | uint8_t dp_train_pat) | |
2435 | { | |
2436 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2437 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2439 | enum port port = intel_dig_port->port; | |
2440 | ||
2441 | if (HAS_DDI(dev)) { | |
2442 | uint32_t temp = I915_READ(DP_TP_CTL(port)); | |
2443 | ||
2444 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2445 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2446 | else | |
2447 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2448 | ||
2449 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2450 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2451 | case DP_TRAINING_PATTERN_DISABLE: | |
2452 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2453 | ||
2454 | break; | |
2455 | case DP_TRAINING_PATTERN_1: | |
2456 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2457 | break; | |
2458 | case DP_TRAINING_PATTERN_2: | |
2459 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2460 | break; | |
2461 | case DP_TRAINING_PATTERN_3: | |
2462 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2463 | break; | |
2464 | } | |
2465 | I915_WRITE(DP_TP_CTL(port), temp); | |
2466 | ||
39e5fa88 VS |
2467 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2468 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
7b13b58a VS |
2469 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2470 | ||
2471 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2472 | case DP_TRAINING_PATTERN_DISABLE: | |
2473 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2474 | break; | |
2475 | case DP_TRAINING_PATTERN_1: | |
2476 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2477 | break; | |
2478 | case DP_TRAINING_PATTERN_2: | |
2479 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2480 | break; | |
2481 | case DP_TRAINING_PATTERN_3: | |
2482 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2483 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2484 | break; | |
2485 | } | |
2486 | ||
2487 | } else { | |
2488 | if (IS_CHERRYVIEW(dev)) | |
2489 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
2490 | else | |
2491 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2492 | ||
2493 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2494 | case DP_TRAINING_PATTERN_DISABLE: | |
2495 | *DP |= DP_LINK_TRAIN_OFF; | |
2496 | break; | |
2497 | case DP_TRAINING_PATTERN_1: | |
2498 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2499 | break; | |
2500 | case DP_TRAINING_PATTERN_2: | |
2501 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2502 | break; | |
2503 | case DP_TRAINING_PATTERN_3: | |
2504 | if (IS_CHERRYVIEW(dev)) { | |
2505 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; | |
2506 | } else { | |
2507 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2508 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2509 | } | |
2510 | break; | |
2511 | } | |
2512 | } | |
2513 | } | |
2514 | ||
2515 | static void intel_dp_enable_port(struct intel_dp *intel_dp) | |
2516 | { | |
2517 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2519 | ||
7b13b58a VS |
2520 | /* enable with pattern 1 (as per spec) */ |
2521 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, | |
2522 | DP_TRAINING_PATTERN_1); | |
2523 | ||
2524 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2525 | POSTING_READ(intel_dp->output_reg); | |
7b713f50 VS |
2526 | |
2527 | /* | |
2528 | * Magic for VLV/CHV. We _must_ first set up the register | |
2529 | * without actually enabling the port, and then do another | |
2530 | * write to enable the port. Otherwise link training will | |
2531 | * fail when the power sequencer is freshly used for this port. | |
2532 | */ | |
2533 | intel_dp->DP |= DP_PORT_EN; | |
2534 | ||
2535 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2536 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2537 | } |
2538 | ||
e8cb4558 | 2539 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 2540 | { |
e8cb4558 DV |
2541 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2542 | struct drm_device *dev = encoder->base.dev; | |
2543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1dec79a | 2544 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2545 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
9b6de0a1 | 2546 | unsigned int lane_mask = 0x0; |
5d613501 | 2547 | |
0c33d8d7 DV |
2548 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2549 | return; | |
5d613501 | 2550 | |
093e3f13 VS |
2551 | pps_lock(intel_dp); |
2552 | ||
2553 | if (IS_VALLEYVIEW(dev)) | |
2554 | vlv_init_panel_power_sequencer(intel_dp); | |
2555 | ||
7b13b58a | 2556 | intel_dp_enable_port(intel_dp); |
093e3f13 VS |
2557 | |
2558 | edp_panel_vdd_on(intel_dp); | |
2559 | edp_panel_on(intel_dp); | |
2560 | edp_panel_vdd_off(intel_dp, true); | |
2561 | ||
2562 | pps_unlock(intel_dp); | |
2563 | ||
61234fa5 | 2564 | if (IS_VALLEYVIEW(dev)) |
9b6de0a1 VS |
2565 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2566 | lane_mask); | |
61234fa5 | 2567 | |
f01eca2e | 2568 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2569 | intel_dp_start_link_train(intel_dp); |
33a34e4e | 2570 | intel_dp_complete_link_train(intel_dp); |
3ab9c637 | 2571 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2572 | |
6e3c9717 | 2573 | if (crtc->config->has_audio) { |
c1dec79a JN |
2574 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
2575 | pipe_name(crtc->pipe)); | |
2576 | intel_audio_codec_enable(encoder); | |
2577 | } | |
ab1f90f9 | 2578 | } |
89b667f8 | 2579 | |
ecff4f3b JN |
2580 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2581 | { | |
828f5c6e JN |
2582 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2583 | ||
ecff4f3b | 2584 | intel_enable_dp(encoder); |
4be73780 | 2585 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2586 | } |
89b667f8 | 2587 | |
ab1f90f9 JN |
2588 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2589 | { | |
828f5c6e JN |
2590 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2591 | ||
4be73780 | 2592 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2593 | intel_psr_enable(intel_dp); |
d240f20f JB |
2594 | } |
2595 | ||
ecff4f3b | 2596 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
2597 | { |
2598 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2599 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2600 | ||
8ac33ed3 DV |
2601 | intel_dp_prepare(encoder); |
2602 | ||
d41f1efb DV |
2603 | /* Only ilk+ has port A */ |
2604 | if (dport->port == PORT_A) { | |
2605 | ironlake_set_pll_cpu_edp(intel_dp); | |
ab1f90f9 | 2606 | ironlake_edp_pll_on(intel_dp); |
d41f1efb | 2607 | } |
ab1f90f9 JN |
2608 | } |
2609 | ||
83b84597 VS |
2610 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2611 | { | |
2612 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2613 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; | |
2614 | enum pipe pipe = intel_dp->pps_pipe; | |
2615 | int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
2616 | ||
2617 | edp_panel_vdd_off_sync(intel_dp); | |
2618 | ||
2619 | /* | |
2620 | * VLV seems to get confused when multiple power seqeuencers | |
2621 | * have the same port selected (even if only one has power/vdd | |
2622 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2623 | * CHV on the other hand doesn't seem to mind having the same port | |
2624 | * selected in multiple power seqeuencers, but let's clear the | |
2625 | * port select always when logically disconnecting a power sequencer | |
2626 | * from a port. | |
2627 | */ | |
2628 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2629 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2630 | I915_WRITE(pp_on_reg, 0); | |
2631 | POSTING_READ(pp_on_reg); | |
2632 | ||
2633 | intel_dp->pps_pipe = INVALID_PIPE; | |
2634 | } | |
2635 | ||
a4a5d2f8 VS |
2636 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2637 | enum pipe pipe) | |
2638 | { | |
2639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2640 | struct intel_encoder *encoder; | |
2641 | ||
2642 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2643 | ||
ac3c12e4 VS |
2644 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2645 | return; | |
2646 | ||
a4a5d2f8 VS |
2647 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
2648 | base.head) { | |
2649 | struct intel_dp *intel_dp; | |
773538e8 | 2650 | enum port port; |
a4a5d2f8 VS |
2651 | |
2652 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2653 | continue; | |
2654 | ||
2655 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2656 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2657 | |
2658 | if (intel_dp->pps_pipe != pipe) | |
2659 | continue; | |
2660 | ||
2661 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2662 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2663 | |
e02f9a06 | 2664 | WARN(encoder->base.crtc, |
034e43c6 VS |
2665 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2666 | pipe_name(pipe), port_name(port)); | |
a4a5d2f8 | 2667 | |
a4a5d2f8 | 2668 | /* make sure vdd is off before we steal it */ |
83b84597 | 2669 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2670 | } |
2671 | } | |
2672 | ||
2673 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2674 | { | |
2675 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2676 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2677 | struct drm_device *dev = encoder->base.dev; | |
2678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2679 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
a4a5d2f8 VS |
2680 | |
2681 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2682 | ||
093e3f13 VS |
2683 | if (!is_edp(intel_dp)) |
2684 | return; | |
2685 | ||
a4a5d2f8 VS |
2686 | if (intel_dp->pps_pipe == crtc->pipe) |
2687 | return; | |
2688 | ||
2689 | /* | |
2690 | * If another power sequencer was being used on this | |
2691 | * port previously make sure to turn off vdd there while | |
2692 | * we still have control of it. | |
2693 | */ | |
2694 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2695 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2696 | |
2697 | /* | |
2698 | * We may be stealing the power | |
2699 | * sequencer from another port. | |
2700 | */ | |
2701 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2702 | ||
2703 | /* now it's all ours */ | |
2704 | intel_dp->pps_pipe = crtc->pipe; | |
2705 | ||
2706 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2707 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2708 | ||
2709 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
2710 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2711 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 VS |
2712 | } |
2713 | ||
ab1f90f9 | 2714 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
a4fc5ed6 | 2715 | { |
2bd2ad64 | 2716 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2717 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 2718 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 2719 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 | 2720 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
e4607fcf | 2721 | enum dpio_channel port = vlv_dport_to_channel(dport); |
ab1f90f9 JN |
2722 | int pipe = intel_crtc->pipe; |
2723 | u32 val; | |
a4fc5ed6 | 2724 | |
a580516d | 2725 | mutex_lock(&dev_priv->sb_lock); |
89b667f8 | 2726 | |
ab3c759a | 2727 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
ab1f90f9 JN |
2728 | val = 0; |
2729 | if (pipe) | |
2730 | val |= (1<<21); | |
2731 | else | |
2732 | val &= ~(1<<21); | |
2733 | val |= 0x001000c4; | |
ab3c759a CML |
2734 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2735 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
2736 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
89b667f8 | 2737 | |
a580516d | 2738 | mutex_unlock(&dev_priv->sb_lock); |
ab1f90f9 JN |
2739 | |
2740 | intel_enable_dp(encoder); | |
89b667f8 JB |
2741 | } |
2742 | ||
ecff4f3b | 2743 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
2744 | { |
2745 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2746 | struct drm_device *dev = encoder->base.dev; | |
2747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
2748 | struct intel_crtc *intel_crtc = |
2749 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 2750 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2751 | int pipe = intel_crtc->pipe; |
89b667f8 | 2752 | |
8ac33ed3 DV |
2753 | intel_dp_prepare(encoder); |
2754 | ||
89b667f8 | 2755 | /* Program Tx lane resets to default */ |
a580516d | 2756 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 2757 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
2758 | DPIO_PCS_TX_LANE2_RESET | |
2759 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 2760 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
2761 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2762 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
2763 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
2764 | DPIO_PCS_CLK_SOFT_RESET); | |
2765 | ||
2766 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
2767 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2768 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
2769 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
a580516d | 2770 | mutex_unlock(&dev_priv->sb_lock); |
a4fc5ed6 KP |
2771 | } |
2772 | ||
e4a1d846 CML |
2773 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2774 | { | |
2775 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2776 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2777 | struct drm_device *dev = encoder->base.dev; | |
2778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e4a1d846 CML |
2779 | struct intel_crtc *intel_crtc = |
2780 | to_intel_crtc(encoder->base.crtc); | |
2781 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
2782 | int pipe = intel_crtc->pipe; | |
2e523e98 | 2783 | int data, i, stagger; |
949c1d43 | 2784 | u32 val; |
e4a1d846 | 2785 | |
a580516d | 2786 | mutex_lock(&dev_priv->sb_lock); |
949c1d43 | 2787 | |
570e2a74 VS |
2788 | /* allow hardware to manage TX FIFO reset source */ |
2789 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
2790 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
2791 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
2792 | ||
2793 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
2794 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
2795 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
2796 | ||
949c1d43 | 2797 | /* Deassert soft data lane reset*/ |
97fd4d5c | 2798 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 2799 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
2800 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2801 | ||
2802 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
2803 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
2804 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
2805 | ||
2806 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
2807 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
2808 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 2809 | |
97fd4d5c | 2810 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 2811 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 2812 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
2813 | |
2814 | /* Program Tx lane latency optimal setting*/ | |
e4a1d846 | 2815 | for (i = 0; i < 4; i++) { |
e4a1d846 CML |
2816 | /* Set the upar bit */ |
2817 | data = (i == 1) ? 0x0 : 0x1; | |
2818 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
2819 | data << DPIO_UPAR_SHIFT); | |
2820 | } | |
2821 | ||
2822 | /* Data lane stagger programming */ | |
2e523e98 VS |
2823 | if (intel_crtc->config->port_clock > 270000) |
2824 | stagger = 0x18; | |
2825 | else if (intel_crtc->config->port_clock > 135000) | |
2826 | stagger = 0xd; | |
2827 | else if (intel_crtc->config->port_clock > 67500) | |
2828 | stagger = 0x7; | |
2829 | else if (intel_crtc->config->port_clock > 33750) | |
2830 | stagger = 0x4; | |
2831 | else | |
2832 | stagger = 0x2; | |
2833 | ||
2834 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
2835 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
2836 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
2837 | ||
2838 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
2839 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
2840 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
2841 | ||
2842 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
2843 | DPIO_LANESTAGGER_STRAP(stagger) | | |
2844 | DPIO_LANESTAGGER_STRAP_OVRD | | |
2845 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
2846 | DPIO_TX1_STAGGER_MULT(6) | | |
2847 | DPIO_TX2_STAGGER_MULT(0)); | |
2848 | ||
2849 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
2850 | DPIO_LANESTAGGER_STRAP(stagger) | | |
2851 | DPIO_LANESTAGGER_STRAP_OVRD | | |
2852 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
2853 | DPIO_TX1_STAGGER_MULT(7) | | |
2854 | DPIO_TX2_STAGGER_MULT(5)); | |
e4a1d846 | 2855 | |
a580516d | 2856 | mutex_unlock(&dev_priv->sb_lock); |
e4a1d846 | 2857 | |
e4a1d846 | 2858 | intel_enable_dp(encoder); |
e4a1d846 CML |
2859 | } |
2860 | ||
9197c88b VS |
2861 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2862 | { | |
2863 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2864 | struct drm_device *dev = encoder->base.dev; | |
2865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2866 | struct intel_crtc *intel_crtc = | |
2867 | to_intel_crtc(encoder->base.crtc); | |
2868 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
2869 | enum pipe pipe = intel_crtc->pipe; | |
2870 | u32 val; | |
2871 | ||
625695f8 VS |
2872 | intel_dp_prepare(encoder); |
2873 | ||
a580516d | 2874 | mutex_lock(&dev_priv->sb_lock); |
9197c88b | 2875 | |
b9e5ac3c VS |
2876 | /* program left/right clock distribution */ |
2877 | if (pipe != PIPE_B) { | |
2878 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
2879 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
2880 | if (ch == DPIO_CH0) | |
2881 | val |= CHV_BUFLEFTENA1_FORCE; | |
2882 | if (ch == DPIO_CH1) | |
2883 | val |= CHV_BUFRIGHTENA1_FORCE; | |
2884 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
2885 | } else { | |
2886 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
2887 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
2888 | if (ch == DPIO_CH0) | |
2889 | val |= CHV_BUFLEFTENA2_FORCE; | |
2890 | if (ch == DPIO_CH1) | |
2891 | val |= CHV_BUFRIGHTENA2_FORCE; | |
2892 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
2893 | } | |
2894 | ||
9197c88b VS |
2895 | /* program clock channel usage */ |
2896 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
2897 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
2898 | if (pipe != PIPE_B) | |
2899 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
2900 | else | |
2901 | val |= CHV_PCS_USEDCLKCHANNEL; | |
2902 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
2903 | ||
2904 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
2905 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
2906 | if (pipe != PIPE_B) | |
2907 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
2908 | else | |
2909 | val |= CHV_PCS_USEDCLKCHANNEL; | |
2910 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
2911 | ||
2912 | /* | |
2913 | * This a a bit weird since generally CL | |
2914 | * matches the pipe, but here we need to | |
2915 | * pick the CL based on the port. | |
2916 | */ | |
2917 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
2918 | if (pipe != PIPE_B) | |
2919 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
2920 | else | |
2921 | val |= CHV_CMN_USEDCLKCHANNEL; | |
2922 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
2923 | ||
a580516d | 2924 | mutex_unlock(&dev_priv->sb_lock); |
9197c88b VS |
2925 | } |
2926 | ||
a4fc5ed6 | 2927 | /* |
df0c237d JB |
2928 | * Native read with retry for link status and receiver capability reads for |
2929 | * cases where the sink may still be asleep. | |
9d1a1031 JN |
2930 | * |
2931 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also | |
2932 | * supposed to retry 3 times per the spec. | |
a4fc5ed6 | 2933 | */ |
9d1a1031 JN |
2934 | static ssize_t |
2935 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, | |
2936 | void *buffer, size_t size) | |
a4fc5ed6 | 2937 | { |
9d1a1031 JN |
2938 | ssize_t ret; |
2939 | int i; | |
61da5fab | 2940 | |
f6a19066 VS |
2941 | /* |
2942 | * Sometime we just get the same incorrect byte repeated | |
2943 | * over the entire buffer. Doing just one throw away read | |
2944 | * initially seems to "solve" it. | |
2945 | */ | |
2946 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); | |
2947 | ||
61da5fab | 2948 | for (i = 0; i < 3; i++) { |
9d1a1031 JN |
2949 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
2950 | if (ret == size) | |
2951 | return ret; | |
61da5fab JB |
2952 | msleep(1); |
2953 | } | |
a4fc5ed6 | 2954 | |
9d1a1031 | 2955 | return ret; |
a4fc5ed6 KP |
2956 | } |
2957 | ||
2958 | /* | |
2959 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2960 | * link status information | |
2961 | */ | |
2962 | static bool | |
93f62dad | 2963 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2964 | { |
9d1a1031 JN |
2965 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
2966 | DP_LANE0_1_STATUS, | |
2967 | link_status, | |
2968 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
2969 | } |
2970 | ||
1100244e | 2971 | /* These are source-specific values. */ |
a4fc5ed6 | 2972 | static uint8_t |
1a2eb460 | 2973 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2974 | { |
30add22d | 2975 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
7ad14a29 | 2976 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc7d38a4 | 2977 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2978 | |
9314726b VK |
2979 | if (IS_BROXTON(dev)) |
2980 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; | |
2981 | else if (INTEL_INFO(dev)->gen >= 9) { | |
9e458034 | 2982 | if (dev_priv->edp_low_vswing && port == PORT_A) |
7ad14a29 | 2983 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 2984 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
7ad14a29 | 2985 | } else if (IS_VALLEYVIEW(dev)) |
bd60018a | 2986 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
bc7d38a4 | 2987 | else if (IS_GEN7(dev) && port == PORT_A) |
bd60018a | 2988 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
bc7d38a4 | 2989 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
bd60018a | 2990 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 2991 | else |
bd60018a | 2992 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
2993 | } |
2994 | ||
2995 | static uint8_t | |
2996 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
2997 | { | |
30add22d | 2998 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2999 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3000 | |
5a9d1f1a DL |
3001 | if (INTEL_INFO(dev)->gen >= 9) { |
3002 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
3003 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3004 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3005 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3006 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3007 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3008 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3009 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3010 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3011 | default: |
3012 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3013 | } | |
3014 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
d6c0d722 | 3015 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3016 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3017 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3018 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3019 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3020 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3021 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3022 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3023 | default: |
bd60018a | 3024 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3025 | } |
e2fa6fba P |
3026 | } else if (IS_VALLEYVIEW(dev)) { |
3027 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3028 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3029 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3030 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3031 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3032 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3033 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3034 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3035 | default: |
bd60018a | 3036 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3037 | } |
bc7d38a4 | 3038 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 | 3039 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3040 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3041 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3042 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3043 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3044 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3045 | default: |
bd60018a | 3046 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3047 | } |
3048 | } else { | |
3049 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3050 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3051 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3052 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3053 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3054 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3055 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3056 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3057 | default: |
bd60018a | 3058 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3059 | } |
a4fc5ed6 KP |
3060 | } |
3061 | } | |
3062 | ||
5829975c | 3063 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba P |
3064 | { |
3065 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3067 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
3068 | struct intel_crtc *intel_crtc = |
3069 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
3070 | unsigned long demph_reg_value, preemph_reg_value, |
3071 | uniqtranscale_reg_value; | |
3072 | uint8_t train_set = intel_dp->train_set[0]; | |
e4607fcf | 3073 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 3074 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
3075 | |
3076 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3077 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3078 | preemph_reg_value = 0x0004000; |
3079 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3080 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3081 | demph_reg_value = 0x2B405555; |
3082 | uniqtranscale_reg_value = 0x552AB83A; | |
3083 | break; | |
bd60018a | 3084 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3085 | demph_reg_value = 0x2B404040; |
3086 | uniqtranscale_reg_value = 0x5548B83A; | |
3087 | break; | |
bd60018a | 3088 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3089 | demph_reg_value = 0x2B245555; |
3090 | uniqtranscale_reg_value = 0x5560B83A; | |
3091 | break; | |
bd60018a | 3092 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3093 | demph_reg_value = 0x2B405555; |
3094 | uniqtranscale_reg_value = 0x5598DA3A; | |
3095 | break; | |
3096 | default: | |
3097 | return 0; | |
3098 | } | |
3099 | break; | |
bd60018a | 3100 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3101 | preemph_reg_value = 0x0002000; |
3102 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3103 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3104 | demph_reg_value = 0x2B404040; |
3105 | uniqtranscale_reg_value = 0x5552B83A; | |
3106 | break; | |
bd60018a | 3107 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3108 | demph_reg_value = 0x2B404848; |
3109 | uniqtranscale_reg_value = 0x5580B83A; | |
3110 | break; | |
bd60018a | 3111 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3112 | demph_reg_value = 0x2B404040; |
3113 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3114 | break; | |
3115 | default: | |
3116 | return 0; | |
3117 | } | |
3118 | break; | |
bd60018a | 3119 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3120 | preemph_reg_value = 0x0000000; |
3121 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3122 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3123 | demph_reg_value = 0x2B305555; |
3124 | uniqtranscale_reg_value = 0x5570B83A; | |
3125 | break; | |
bd60018a | 3126 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3127 | demph_reg_value = 0x2B2B4040; |
3128 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3129 | break; | |
3130 | default: | |
3131 | return 0; | |
3132 | } | |
3133 | break; | |
bd60018a | 3134 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3135 | preemph_reg_value = 0x0006000; |
3136 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3137 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3138 | demph_reg_value = 0x1B405555; |
3139 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3140 | break; | |
3141 | default: | |
3142 | return 0; | |
3143 | } | |
3144 | break; | |
3145 | default: | |
3146 | return 0; | |
3147 | } | |
3148 | ||
a580516d | 3149 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a CML |
3150 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3151 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
3152 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
e2fa6fba | 3153 | uniqtranscale_reg_value); |
ab3c759a CML |
3154 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3155 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
3156 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
3157 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); | |
a580516d | 3158 | mutex_unlock(&dev_priv->sb_lock); |
e2fa6fba P |
3159 | |
3160 | return 0; | |
3161 | } | |
3162 | ||
5829975c | 3163 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 CML |
3164 | { |
3165 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3167 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
3168 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); | |
f72df8db | 3169 | u32 deemph_reg_value, margin_reg_value, val; |
e4a1d846 CML |
3170 | uint8_t train_set = intel_dp->train_set[0]; |
3171 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
f72df8db VS |
3172 | enum pipe pipe = intel_crtc->pipe; |
3173 | int i; | |
e4a1d846 CML |
3174 | |
3175 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3176 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3177 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3178 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3179 | deemph_reg_value = 128; |
3180 | margin_reg_value = 52; | |
3181 | break; | |
bd60018a | 3182 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3183 | deemph_reg_value = 128; |
3184 | margin_reg_value = 77; | |
3185 | break; | |
bd60018a | 3186 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3187 | deemph_reg_value = 128; |
3188 | margin_reg_value = 102; | |
3189 | break; | |
bd60018a | 3190 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3191 | deemph_reg_value = 128; |
3192 | margin_reg_value = 154; | |
3193 | /* FIXME extra to set for 1200 */ | |
3194 | break; | |
3195 | default: | |
3196 | return 0; | |
3197 | } | |
3198 | break; | |
bd60018a | 3199 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3200 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3201 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3202 | deemph_reg_value = 85; |
3203 | margin_reg_value = 78; | |
3204 | break; | |
bd60018a | 3205 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3206 | deemph_reg_value = 85; |
3207 | margin_reg_value = 116; | |
3208 | break; | |
bd60018a | 3209 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3210 | deemph_reg_value = 85; |
3211 | margin_reg_value = 154; | |
3212 | break; | |
3213 | default: | |
3214 | return 0; | |
3215 | } | |
3216 | break; | |
bd60018a | 3217 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3218 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3219 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3220 | deemph_reg_value = 64; |
3221 | margin_reg_value = 104; | |
3222 | break; | |
bd60018a | 3223 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3224 | deemph_reg_value = 64; |
3225 | margin_reg_value = 154; | |
3226 | break; | |
3227 | default: | |
3228 | return 0; | |
3229 | } | |
3230 | break; | |
bd60018a | 3231 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3232 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3233 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3234 | deemph_reg_value = 43; |
3235 | margin_reg_value = 154; | |
3236 | break; | |
3237 | default: | |
3238 | return 0; | |
3239 | } | |
3240 | break; | |
3241 | default: | |
3242 | return 0; | |
3243 | } | |
3244 | ||
a580516d | 3245 | mutex_lock(&dev_priv->sb_lock); |
e4a1d846 CML |
3246 | |
3247 | /* Clear calc init */ | |
1966e59e VS |
3248 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3249 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
3250 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3251 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
3252 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3253 | ||
3254 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
3255 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
3256 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3257 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 3258 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 3259 | |
a02ef3c7 VS |
3260 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3261 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
3262 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
3263 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
3264 | ||
3265 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
3266 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
3267 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
3268 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
3269 | ||
e4a1d846 | 3270 | /* Program swing deemph */ |
f72df8db VS |
3271 | for (i = 0; i < 4; i++) { |
3272 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
3273 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
3274 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; | |
3275 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
3276 | } | |
e4a1d846 CML |
3277 | |
3278 | /* Program swing margin */ | |
f72df8db VS |
3279 | for (i = 0; i < 4; i++) { |
3280 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
3281 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3282 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
3283 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3284 | } | |
e4a1d846 CML |
3285 | |
3286 | /* Disable unique transition scale */ | |
f72df8db VS |
3287 | for (i = 0; i < 4; i++) { |
3288 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
3289 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
3290 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
3291 | } | |
e4a1d846 CML |
3292 | |
3293 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) | |
bd60018a | 3294 | == DP_TRAIN_PRE_EMPH_LEVEL_0) && |
e4a1d846 | 3295 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
bd60018a | 3296 | == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) { |
e4a1d846 CML |
3297 | |
3298 | /* | |
3299 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
3300 | * for ch1. Might be a typo in the doc. | |
3301 | * For now, for this unique transition scale selection, set bit | |
3302 | * 27 for ch0 and ch1. | |
3303 | */ | |
f72df8db VS |
3304 | for (i = 0; i < 4; i++) { |
3305 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
3306 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
3307 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
3308 | } | |
e4a1d846 | 3309 | |
f72df8db VS |
3310 | for (i = 0; i < 4; i++) { |
3311 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
3312 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
3313 | val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
3314 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
3315 | } | |
e4a1d846 CML |
3316 | } |
3317 | ||
3318 | /* Start swing calculation */ | |
1966e59e VS |
3319 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3320 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
3321 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
3322 | ||
3323 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
3324 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
3325 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
3326 | |
3327 | /* LRC Bypass */ | |
3328 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
3329 | val |= DPIO_LRC_BYPASS; | |
3330 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
3331 | ||
a580516d | 3332 | mutex_unlock(&dev_priv->sb_lock); |
e4a1d846 CML |
3333 | |
3334 | return 0; | |
3335 | } | |
3336 | ||
a4fc5ed6 | 3337 | static void |
0301b3ac JN |
3338 | intel_get_adjust_train(struct intel_dp *intel_dp, |
3339 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) | |
a4fc5ed6 KP |
3340 | { |
3341 | uint8_t v = 0; | |
3342 | uint8_t p = 0; | |
3343 | int lane; | |
1a2eb460 KP |
3344 | uint8_t voltage_max; |
3345 | uint8_t preemph_max; | |
a4fc5ed6 | 3346 | |
33a34e4e | 3347 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
3348 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
3349 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
3350 | |
3351 | if (this_v > v) | |
3352 | v = this_v; | |
3353 | if (this_p > p) | |
3354 | p = this_p; | |
3355 | } | |
3356 | ||
1a2eb460 | 3357 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
3358 | if (v >= voltage_max) |
3359 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 3360 | |
1a2eb460 KP |
3361 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
3362 | if (p >= preemph_max) | |
3363 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
3364 | |
3365 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 3366 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
3367 | } |
3368 | ||
3369 | static uint32_t | |
5829975c | 3370 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3371 | { |
3cf2efb1 | 3372 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3373 | |
3cf2efb1 | 3374 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3375 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3376 | default: |
3377 | signal_levels |= DP_VOLTAGE_0_4; | |
3378 | break; | |
bd60018a | 3379 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3380 | signal_levels |= DP_VOLTAGE_0_6; |
3381 | break; | |
bd60018a | 3382 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3383 | signal_levels |= DP_VOLTAGE_0_8; |
3384 | break; | |
bd60018a | 3385 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3386 | signal_levels |= DP_VOLTAGE_1_2; |
3387 | break; | |
3388 | } | |
3cf2efb1 | 3389 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3390 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3391 | default: |
3392 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3393 | break; | |
bd60018a | 3394 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3395 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3396 | break; | |
bd60018a | 3397 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3398 | signal_levels |= DP_PRE_EMPHASIS_6; |
3399 | break; | |
bd60018a | 3400 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3401 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3402 | break; | |
3403 | } | |
3404 | return signal_levels; | |
3405 | } | |
3406 | ||
e3421a18 ZW |
3407 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3408 | static uint32_t | |
5829975c | 3409 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3410 | { |
3c5a62b5 YL |
3411 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3412 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3413 | switch (signal_levels) { | |
bd60018a SJ |
3414 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3415 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3416 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3417 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3418 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3419 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3420 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3421 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3422 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3423 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3424 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3425 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3426 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3427 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3428 | default: |
3c5a62b5 YL |
3429 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3430 | "0x%x\n", signal_levels); | |
3431 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3432 | } |
3433 | } | |
3434 | ||
1a2eb460 KP |
3435 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3436 | static uint32_t | |
5829975c | 3437 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3438 | { |
3439 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3440 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3441 | switch (signal_levels) { | |
bd60018a | 3442 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3443 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3444 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3445 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3446 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3447 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3448 | ||
bd60018a | 3449 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3450 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3451 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3452 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3453 | ||
bd60018a | 3454 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3455 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3456 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3457 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3458 | ||
3459 | default: | |
3460 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3461 | "0x%x\n", signal_levels); | |
3462 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3463 | } | |
3464 | } | |
3465 | ||
f0a3424e PZ |
3466 | /* Properly updates "DP" with the correct signal levels. */ |
3467 | static void | |
3468 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
3469 | { | |
3470 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3471 | enum port port = intel_dig_port->port; |
f0a3424e | 3472 | struct drm_device *dev = intel_dig_port->base.base.dev; |
f8896f5d | 3473 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3474 | uint8_t train_set = intel_dp->train_set[0]; |
3475 | ||
f8896f5d DW |
3476 | if (HAS_DDI(dev)) { |
3477 | signal_levels = ddi_signal_levels(intel_dp); | |
3478 | ||
3479 | if (IS_BROXTON(dev)) | |
3480 | signal_levels = 0; | |
3481 | else | |
3482 | mask = DDI_BUF_EMP_MASK; | |
e4a1d846 | 3483 | } else if (IS_CHERRYVIEW(dev)) { |
5829975c | 3484 | signal_levels = chv_signal_levels(intel_dp); |
e2fa6fba | 3485 | } else if (IS_VALLEYVIEW(dev)) { |
5829975c | 3486 | signal_levels = vlv_signal_levels(intel_dp); |
bc7d38a4 | 3487 | } else if (IS_GEN7(dev) && port == PORT_A) { |
5829975c | 3488 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3489 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
bc7d38a4 | 3490 | } else if (IS_GEN6(dev) && port == PORT_A) { |
5829975c | 3491 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3492 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3493 | } else { | |
5829975c | 3494 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3495 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3496 | } | |
3497 | ||
96fb9f9b VK |
3498 | if (mask) |
3499 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3500 | ||
3501 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3502 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3503 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3504 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3505 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e PZ |
3506 | |
3507 | *DP = (*DP & ~mask) | signal_levels; | |
3508 | } | |
3509 | ||
a4fc5ed6 | 3510 | static bool |
ea5b213a | 3511 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
70aff66c | 3512 | uint32_t *DP, |
58e10eb9 | 3513 | uint8_t dp_train_pat) |
a4fc5ed6 | 3514 | { |
174edf1f PZ |
3515 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3516 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 3517 | struct drm_i915_private *dev_priv = dev->dev_private; |
2cdfe6c8 JN |
3518 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
3519 | int ret, len; | |
a4fc5ed6 | 3520 | |
7b13b58a | 3521 | _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
47ea7542 | 3522 | |
70aff66c | 3523 | I915_WRITE(intel_dp->output_reg, *DP); |
ea5b213a | 3524 | POSTING_READ(intel_dp->output_reg); |
a4fc5ed6 | 3525 | |
2cdfe6c8 JN |
3526 | buf[0] = dp_train_pat; |
3527 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == | |
47ea7542 | 3528 | DP_TRAINING_PATTERN_DISABLE) { |
2cdfe6c8 JN |
3529 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
3530 | len = 1; | |
3531 | } else { | |
3532 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ | |
3533 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); | |
3534 | len = intel_dp->lane_count + 1; | |
47ea7542 | 3535 | } |
a4fc5ed6 | 3536 | |
9d1a1031 JN |
3537 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
3538 | buf, len); | |
2cdfe6c8 JN |
3539 | |
3540 | return ret == len; | |
a4fc5ed6 KP |
3541 | } |
3542 | ||
70aff66c JN |
3543 | static bool |
3544 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
3545 | uint8_t dp_train_pat) | |
3546 | { | |
4e96c977 MK |
3547 | if (!intel_dp->train_set_valid) |
3548 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); | |
70aff66c JN |
3549 | intel_dp_set_signal_levels(intel_dp, DP); |
3550 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); | |
3551 | } | |
3552 | ||
3553 | static bool | |
3554 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
0301b3ac | 3555 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
70aff66c JN |
3556 | { |
3557 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3558 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3560 | int ret; | |
3561 | ||
3562 | intel_get_adjust_train(intel_dp, link_status); | |
3563 | intel_dp_set_signal_levels(intel_dp, DP); | |
3564 | ||
3565 | I915_WRITE(intel_dp->output_reg, *DP); | |
3566 | POSTING_READ(intel_dp->output_reg); | |
3567 | ||
9d1a1031 JN |
3568 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
3569 | intel_dp->train_set, intel_dp->lane_count); | |
70aff66c JN |
3570 | |
3571 | return ret == intel_dp->lane_count; | |
3572 | } | |
3573 | ||
3ab9c637 ID |
3574 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3575 | { | |
3576 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3577 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3579 | enum port port = intel_dig_port->port; | |
3580 | uint32_t val; | |
3581 | ||
3582 | if (!HAS_DDI(dev)) | |
3583 | return; | |
3584 | ||
3585 | val = I915_READ(DP_TP_CTL(port)); | |
3586 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3587 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3588 | I915_WRITE(DP_TP_CTL(port), val); | |
3589 | ||
3590 | /* | |
3591 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3592 | * we need to set idle transmission mode is to work around a HW issue | |
3593 | * where we enable the pipe while not in idle link-training mode. | |
3594 | * In this case there is requirement to wait for a minimum number of | |
3595 | * idle patterns to be sent. | |
3596 | */ | |
3597 | if (port == PORT_A) | |
3598 | return; | |
3599 | ||
3600 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
3601 | 1)) | |
3602 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
3603 | } | |
3604 | ||
33a34e4e | 3605 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 3606 | void |
33a34e4e | 3607 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 3608 | { |
da63a9f2 | 3609 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 3610 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
3611 | int i; |
3612 | uint8_t voltage; | |
cdb0e95b | 3613 | int voltage_tries, loop_tries; |
ea5b213a | 3614 | uint32_t DP = intel_dp->DP; |
6aba5b6c | 3615 | uint8_t link_config[2]; |
a4fc5ed6 | 3616 | |
affa9354 | 3617 | if (HAS_DDI(dev)) |
c19b0669 PZ |
3618 | intel_ddi_prepare_link_retrain(encoder); |
3619 | ||
3cf2efb1 | 3620 | /* Write the link configuration data */ |
6aba5b6c JN |
3621 | link_config[0] = intel_dp->link_bw; |
3622 | link_config[1] = intel_dp->lane_count; | |
3623 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
3624 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
9d1a1031 | 3625 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
94ca719e | 3626 | if (intel_dp->num_sink_rates) |
a8f3ef61 SJ |
3627 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, |
3628 | &intel_dp->rate_select, 1); | |
6aba5b6c JN |
3629 | |
3630 | link_config[0] = 0; | |
3631 | link_config[1] = DP_SET_ANSI_8B10B; | |
9d1a1031 | 3632 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
a4fc5ed6 KP |
3633 | |
3634 | DP |= DP_PORT_EN; | |
1a2eb460 | 3635 | |
70aff66c JN |
3636 | /* clock recovery */ |
3637 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
3638 | DP_TRAINING_PATTERN_1 | | |
3639 | DP_LINK_SCRAMBLING_DISABLE)) { | |
3640 | DRM_ERROR("failed to enable link training\n"); | |
3641 | return; | |
3642 | } | |
3643 | ||
a4fc5ed6 | 3644 | voltage = 0xff; |
cdb0e95b KP |
3645 | voltage_tries = 0; |
3646 | loop_tries = 0; | |
a4fc5ed6 | 3647 | for (;;) { |
70aff66c | 3648 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
a4fc5ed6 | 3649 | |
a7c9655f | 3650 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
3651 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3652 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 3653 | break; |
93f62dad | 3654 | } |
a4fc5ed6 | 3655 | |
01916270 | 3656 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 3657 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
3658 | break; |
3659 | } | |
3660 | ||
4e96c977 MK |
3661 | /* |
3662 | * if we used previously trained voltage and pre-emphasis values | |
3663 | * and we don't get clock recovery, reset link training values | |
3664 | */ | |
3665 | if (intel_dp->train_set_valid) { | |
3666 | DRM_DEBUG_KMS("clock recovery not ok, reset"); | |
3667 | /* clear the flag as we are not reusing train set */ | |
3668 | intel_dp->train_set_valid = false; | |
3669 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
3670 | DP_TRAINING_PATTERN_1 | | |
3671 | DP_LINK_SCRAMBLING_DISABLE)) { | |
3672 | DRM_ERROR("failed to enable link training\n"); | |
3673 | return; | |
3674 | } | |
3675 | continue; | |
3676 | } | |
3677 | ||
3cf2efb1 CW |
3678 | /* Check to see if we've tried the max voltage */ |
3679 | for (i = 0; i < intel_dp->lane_count; i++) | |
3680 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 3681 | break; |
3b4f819d | 3682 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
3683 | ++loop_tries; |
3684 | if (loop_tries == 5) { | |
3def84b3 | 3685 | DRM_ERROR("too many full retries, give up\n"); |
cdb0e95b KP |
3686 | break; |
3687 | } | |
70aff66c JN |
3688 | intel_dp_reset_link_train(intel_dp, &DP, |
3689 | DP_TRAINING_PATTERN_1 | | |
3690 | DP_LINK_SCRAMBLING_DISABLE); | |
cdb0e95b KP |
3691 | voltage_tries = 0; |
3692 | continue; | |
3693 | } | |
a4fc5ed6 | 3694 | |
3cf2efb1 | 3695 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 3696 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 3697 | ++voltage_tries; |
b06fbda3 | 3698 | if (voltage_tries == 5) { |
3def84b3 | 3699 | DRM_ERROR("too many voltage retries, give up\n"); |
b06fbda3 DV |
3700 | break; |
3701 | } | |
3702 | } else | |
3703 | voltage_tries = 0; | |
3704 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 3705 | |
70aff66c JN |
3706 | /* Update training set as requested by target */ |
3707 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
3708 | DRM_ERROR("failed to update link training\n"); | |
3709 | break; | |
3710 | } | |
a4fc5ed6 KP |
3711 | } |
3712 | ||
33a34e4e JB |
3713 | intel_dp->DP = DP; |
3714 | } | |
3715 | ||
c19b0669 | 3716 | void |
33a34e4e JB |
3717 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
3718 | { | |
33a34e4e | 3719 | bool channel_eq = false; |
37f80975 | 3720 | int tries, cr_tries; |
33a34e4e | 3721 | uint32_t DP = intel_dp->DP; |
06ea66b6 TP |
3722 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
3723 | ||
3724 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ | |
3725 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) | |
3726 | training_pattern = DP_TRAINING_PATTERN_3; | |
33a34e4e | 3727 | |
a4fc5ed6 | 3728 | /* channel equalization */ |
70aff66c | 3729 | if (!intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 3730 | training_pattern | |
70aff66c JN |
3731 | DP_LINK_SCRAMBLING_DISABLE)) { |
3732 | DRM_ERROR("failed to start channel equalization\n"); | |
3733 | return; | |
3734 | } | |
3735 | ||
a4fc5ed6 | 3736 | tries = 0; |
37f80975 | 3737 | cr_tries = 0; |
a4fc5ed6 KP |
3738 | channel_eq = false; |
3739 | for (;;) { | |
70aff66c | 3740 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 3741 | |
37f80975 JB |
3742 | if (cr_tries > 5) { |
3743 | DRM_ERROR("failed to train DP, aborting\n"); | |
37f80975 JB |
3744 | break; |
3745 | } | |
3746 | ||
a7c9655f | 3747 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
70aff66c JN |
3748 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3749 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 3750 | break; |
70aff66c | 3751 | } |
a4fc5ed6 | 3752 | |
37f80975 | 3753 | /* Make sure clock is still ok */ |
01916270 | 3754 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
4e96c977 | 3755 | intel_dp->train_set_valid = false; |
37f80975 | 3756 | intel_dp_start_link_train(intel_dp); |
70aff66c | 3757 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 3758 | training_pattern | |
70aff66c | 3759 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
3760 | cr_tries++; |
3761 | continue; | |
3762 | } | |
3763 | ||
1ffdff13 | 3764 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
3765 | channel_eq = true; |
3766 | break; | |
3767 | } | |
a4fc5ed6 | 3768 | |
37f80975 JB |
3769 | /* Try 5 times, then try clock recovery if that fails */ |
3770 | if (tries > 5) { | |
4e96c977 | 3771 | intel_dp->train_set_valid = false; |
37f80975 | 3772 | intel_dp_start_link_train(intel_dp); |
70aff66c | 3773 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 3774 | training_pattern | |
70aff66c | 3775 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
3776 | tries = 0; |
3777 | cr_tries++; | |
3778 | continue; | |
3779 | } | |
a4fc5ed6 | 3780 | |
70aff66c JN |
3781 | /* Update training set as requested by target */ |
3782 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
3783 | DRM_ERROR("failed to update link training\n"); | |
3784 | break; | |
3785 | } | |
3cf2efb1 | 3786 | ++tries; |
869184a6 | 3787 | } |
3cf2efb1 | 3788 | |
3ab9c637 ID |
3789 | intel_dp_set_idle_link_train(intel_dp); |
3790 | ||
3791 | intel_dp->DP = DP; | |
3792 | ||
4e96c977 | 3793 | if (channel_eq) { |
5fa836a9 | 3794 | intel_dp->train_set_valid = true; |
07f42258 | 3795 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
4e96c977 | 3796 | } |
3ab9c637 ID |
3797 | } |
3798 | ||
3799 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) | |
3800 | { | |
70aff66c | 3801 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3ab9c637 | 3802 | DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
3803 | } |
3804 | ||
3805 | static void | |
ea5b213a | 3806 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3807 | { |
da63a9f2 | 3808 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3809 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3810 | enum port port = intel_dig_port->port; |
da63a9f2 | 3811 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 3812 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 3813 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3814 | |
bc76e320 | 3815 | if (WARN_ON(HAS_DDI(dev))) |
c19b0669 PZ |
3816 | return; |
3817 | ||
0c33d8d7 | 3818 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3819 | return; |
3820 | ||
28c97730 | 3821 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3822 | |
39e5fa88 VS |
3823 | if ((IS_GEN7(dev) && port == PORT_A) || |
3824 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
e3421a18 | 3825 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3826 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3827 | } else { |
aad3d14d VS |
3828 | if (IS_CHERRYVIEW(dev)) |
3829 | DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
3830 | else | |
3831 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3832 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3833 | } |
1612c8bd | 3834 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3835 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3836 | |
1612c8bd VS |
3837 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3838 | I915_WRITE(intel_dp->output_reg, DP); | |
3839 | POSTING_READ(intel_dp->output_reg); | |
3840 | ||
3841 | /* | |
3842 | * HW workaround for IBX, we need to move the port | |
3843 | * to transcoder A after disabling it to allow the | |
3844 | * matching HDMI port to be enabled on transcoder A. | |
3845 | */ | |
3846 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { | |
3847 | /* always enable with pattern 1 (as per spec) */ | |
3848 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3849 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3850 | I915_WRITE(intel_dp->output_reg, DP); | |
3851 | POSTING_READ(intel_dp->output_reg); | |
3852 | ||
3853 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3854 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3855 | POSTING_READ(intel_dp->output_reg); |
5bddd17f EA |
3856 | } |
3857 | ||
f01eca2e | 3858 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
3859 | } |
3860 | ||
26d61aad KP |
3861 | static bool |
3862 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 3863 | { |
a031d709 RV |
3864 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3865 | struct drm_device *dev = dig_port->base.base.dev; | |
3866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc0f8e25 | 3867 | uint8_t rev; |
a031d709 | 3868 | |
9d1a1031 JN |
3869 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3870 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3871 | return false; /* aux transfer failed */ |
92fd8fd1 | 3872 | |
a8e98153 | 3873 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3874 | |
edb39244 AJ |
3875 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3876 | return false; /* DPCD not present */ | |
3877 | ||
2293bb5c SK |
3878 | /* Check if the panel supports PSR */ |
3879 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 | 3880 | if (is_edp(intel_dp)) { |
9d1a1031 JN |
3881 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3882 | intel_dp->psr_dpcd, | |
3883 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
3884 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3885 | dev_priv->psr.sink_support = true; | |
50003939 | 3886 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 3887 | } |
474d1ec4 SJ |
3888 | |
3889 | if (INTEL_INFO(dev)->gen >= 9 && | |
3890 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3891 | uint8_t frame_sync_cap; | |
3892 | ||
3893 | dev_priv->psr.sink_support = true; | |
3894 | intel_dp_dpcd_read_wake(&intel_dp->aux, | |
3895 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3896 | &frame_sync_cap, 1); | |
3897 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3898 | /* PSR2 needs frame sync as well */ | |
3899 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3900 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3901 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
3902 | } | |
50003939 JN |
3903 | } |
3904 | ||
7809a611 | 3905 | /* Training Pattern 3 support, both source and sink */ |
06ea66b6 | 3906 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
7809a611 JN |
3907 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && |
3908 | (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) { | |
06ea66b6 | 3909 | intel_dp->use_tps3 = true; |
f8d8a672 | 3910 | DRM_DEBUG_KMS("Displayport TPS3 supported\n"); |
06ea66b6 TP |
3911 | } else |
3912 | intel_dp->use_tps3 = false; | |
3913 | ||
fc0f8e25 SJ |
3914 | /* Intermediate frequency support */ |
3915 | if (is_edp(intel_dp) && | |
3916 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3917 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && | |
3918 | (rev >= 0x03)) { /* eDp v1.4 or higher */ | |
94ca719e | 3919 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3920 | int i; |
3921 | ||
fc0f8e25 SJ |
3922 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3923 | DP_SUPPORTED_LINK_RATES, | |
94ca719e VS |
3924 | sink_rates, |
3925 | sizeof(sink_rates)); | |
ea2d8a42 | 3926 | |
94ca719e VS |
3927 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3928 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3929 | |
3930 | if (val == 0) | |
3931 | break; | |
3932 | ||
af77b974 SJ |
3933 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3934 | intel_dp->sink_rates[i] = (val * 200) / 10; | |
ea2d8a42 | 3935 | } |
94ca719e | 3936 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3937 | } |
0336400e VS |
3938 | |
3939 | intel_dp_print_rates(intel_dp); | |
3940 | ||
edb39244 AJ |
3941 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3942 | DP_DWN_STRM_PORT_PRESENT)) | |
3943 | return true; /* native DP sink */ | |
3944 | ||
3945 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3946 | return true; /* no per-port downstream info */ | |
3947 | ||
9d1a1031 JN |
3948 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3949 | intel_dp->downstream_ports, | |
3950 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3951 | return false; /* downstream port status fetch failed */ |
3952 | ||
3953 | return true; | |
92fd8fd1 KP |
3954 | } |
3955 | ||
0d198328 AJ |
3956 | static void |
3957 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
3958 | { | |
3959 | u8 buf[3]; | |
3960 | ||
3961 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
3962 | return; | |
3963 | ||
9d1a1031 | 3964 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
3965 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3966 | buf[0], buf[1], buf[2]); | |
3967 | ||
9d1a1031 | 3968 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
3969 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3970 | buf[0], buf[1], buf[2]); | |
3971 | } | |
3972 | ||
0e32b39c DA |
3973 | static bool |
3974 | intel_dp_probe_mst(struct intel_dp *intel_dp) | |
3975 | { | |
3976 | u8 buf[1]; | |
3977 | ||
3978 | if (!intel_dp->can_mst) | |
3979 | return false; | |
3980 | ||
3981 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3982 | return false; | |
3983 | ||
0e32b39c DA |
3984 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3985 | if (buf[0] & DP_MST_CAP) { | |
3986 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3987 | intel_dp->is_mst = true; | |
3988 | } else { | |
3989 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3990 | intel_dp->is_mst = false; | |
3991 | } | |
3992 | } | |
0e32b39c DA |
3993 | |
3994 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3995 | return intel_dp->is_mst; | |
3996 | } | |
3997 | ||
e5a1cab5 | 3998 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3999 | { |
082dcc7c RV |
4000 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4001 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); | |
ad9dc91b | 4002 | u8 buf; |
e5a1cab5 | 4003 | int ret = 0; |
d2e216d0 | 4004 | |
082dcc7c RV |
4005 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
4006 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
4007 | ret = -EIO; |
4008 | goto out; | |
4373f0f2 PZ |
4009 | } |
4010 | ||
082dcc7c | 4011 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 4012 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 4013 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
4014 | ret = -EIO; |
4015 | goto out; | |
4016 | } | |
d2e216d0 | 4017 | |
e5a1cab5 RV |
4018 | intel_dp->sink_crc_started = false; |
4019 | out: | |
082dcc7c | 4020 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 4021 | return ret; |
082dcc7c RV |
4022 | } |
4023 | ||
4024 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
4025 | { | |
4026 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
4027 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); | |
4028 | u8 buf; | |
e5a1cab5 RV |
4029 | int ret; |
4030 | ||
4031 | if (intel_dp->sink_crc_started) { | |
4032 | ret = intel_dp_sink_crc_stop(intel_dp); | |
4033 | if (ret) | |
4034 | return ret; | |
4035 | } | |
082dcc7c RV |
4036 | |
4037 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) | |
4038 | return -EIO; | |
4039 | ||
4040 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
4041 | return -ENOTTY; | |
4042 | ||
4043 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
4044 | return -EIO; | |
4045 | ||
4046 | hsw_disable_ips(intel_crtc); | |
1dda5f93 | 4047 | |
9d1a1031 | 4048 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
4049 | buf | DP_TEST_SINK_START) < 0) { |
4050 | hsw_enable_ips(intel_crtc); | |
4051 | return -EIO; | |
4373f0f2 PZ |
4052 | } |
4053 | ||
e5a1cab5 | 4054 | intel_dp->sink_crc_started = true; |
082dcc7c RV |
4055 | return 0; |
4056 | } | |
4057 | ||
4058 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
4059 | { | |
4060 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
4061 | struct drm_device *dev = dig_port->base.base.dev; | |
4062 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); | |
4063 | u8 buf; | |
4064 | int test_crc_count; | |
4065 | int attempts = 6; | |
4066 | int ret; | |
4067 | ||
4068 | ret = intel_dp_sink_crc_start(intel_dp); | |
4069 | if (ret) | |
4070 | return ret; | |
4071 | ||
4373f0f2 PZ |
4072 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) { |
4073 | ret = -EIO; | |
afe0d67e | 4074 | goto stop; |
4373f0f2 | 4075 | } |
d2e216d0 | 4076 | |
ad9dc91b | 4077 | test_crc_count = buf & DP_TEST_COUNT_MASK; |
d2e216d0 | 4078 | |
ad9dc91b | 4079 | do { |
1dda5f93 | 4080 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
4081 | DP_TEST_SINK_MISC, &buf) < 0) { |
4082 | ret = -EIO; | |
afe0d67e | 4083 | goto stop; |
4373f0f2 | 4084 | } |
ad9dc91b RV |
4085 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4086 | } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count); | |
4087 | ||
4088 | if (attempts == 0) { | |
90bd1f46 | 4089 | DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n"); |
4373f0f2 | 4090 | ret = -ETIMEDOUT; |
afe0d67e | 4091 | goto stop; |
ad9dc91b | 4092 | } |
d2e216d0 | 4093 | |
082dcc7c | 4094 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
4373f0f2 | 4095 | ret = -EIO; |
afe0d67e | 4096 | stop: |
082dcc7c | 4097 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 4098 | return ret; |
d2e216d0 RV |
4099 | } |
4100 | ||
a60f0e38 JB |
4101 | static bool |
4102 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4103 | { | |
9d1a1031 JN |
4104 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4105 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4106 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
4107 | } |
4108 | ||
0e32b39c DA |
4109 | static bool |
4110 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4111 | { | |
4112 | int ret; | |
4113 | ||
4114 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, | |
4115 | DP_SINK_COUNT_ESI, | |
4116 | sink_irq_vector, 14); | |
4117 | if (ret != 14) | |
4118 | return false; | |
4119 | ||
4120 | return true; | |
4121 | } | |
4122 | ||
c5d5ab7a TP |
4123 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4124 | { | |
4125 | uint8_t test_result = DP_TEST_ACK; | |
4126 | return test_result; | |
4127 | } | |
4128 | ||
4129 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
4130 | { | |
4131 | uint8_t test_result = DP_TEST_NAK; | |
4132 | return test_result; | |
4133 | } | |
4134 | ||
4135 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 4136 | { |
c5d5ab7a | 4137 | uint8_t test_result = DP_TEST_NAK; |
559be30c TP |
4138 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4139 | struct drm_connector *connector = &intel_connector->base; | |
4140 | ||
4141 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4142 | connector->edid_corrupt || |
559be30c TP |
4143 | intel_dp->aux.i2c_defer_count > 6) { |
4144 | /* Check EDID read for NACKs, DEFERs and corruption | |
4145 | * (DP CTS 1.2 Core r1.1) | |
4146 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4147 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4148 | * 4.2.2.6 : EDID corruption detected | |
4149 | * Use failsafe mode for all cases | |
4150 | */ | |
4151 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4152 | intel_dp->aux.i2c_defer_count > 0) | |
4153 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
4154 | intel_dp->aux.i2c_nack_count, | |
4155 | intel_dp->aux.i2c_defer_count); | |
4156 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; | |
4157 | } else { | |
f79b468e TS |
4158 | struct edid *block = intel_connector->detect_edid; |
4159 | ||
4160 | /* We have to write the checksum | |
4161 | * of the last block read | |
4162 | */ | |
4163 | block += intel_connector->detect_edid->extensions; | |
4164 | ||
559be30c TP |
4165 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4166 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 4167 | &block->checksum, |
5a1cc655 | 4168 | 1)) |
559be30c TP |
4169 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4170 | ||
4171 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
4172 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; | |
4173 | } | |
4174 | ||
4175 | /* Set test active flag here so userspace doesn't interrupt things */ | |
4176 | intel_dp->compliance_test_active = 1; | |
4177 | ||
c5d5ab7a TP |
4178 | return test_result; |
4179 | } | |
4180 | ||
4181 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 4182 | { |
c5d5ab7a TP |
4183 | uint8_t test_result = DP_TEST_NAK; |
4184 | return test_result; | |
4185 | } | |
4186 | ||
4187 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4188 | { | |
4189 | uint8_t response = DP_TEST_NAK; | |
4190 | uint8_t rxdata = 0; | |
4191 | int status = 0; | |
4192 | ||
559be30c | 4193 | intel_dp->compliance_test_active = 0; |
c5d5ab7a | 4194 | intel_dp->compliance_test_type = 0; |
559be30c TP |
4195 | intel_dp->compliance_test_data = 0; |
4196 | ||
c5d5ab7a TP |
4197 | intel_dp->aux.i2c_nack_count = 0; |
4198 | intel_dp->aux.i2c_defer_count = 0; | |
4199 | ||
4200 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); | |
4201 | if (status <= 0) { | |
4202 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
4203 | goto update_status; | |
4204 | } | |
4205 | ||
4206 | switch (rxdata) { | |
4207 | case DP_TEST_LINK_TRAINING: | |
4208 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
4209 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; | |
4210 | response = intel_dp_autotest_link_training(intel_dp); | |
4211 | break; | |
4212 | case DP_TEST_LINK_VIDEO_PATTERN: | |
4213 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
4214 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; | |
4215 | response = intel_dp_autotest_video_pattern(intel_dp); | |
4216 | break; | |
4217 | case DP_TEST_LINK_EDID_READ: | |
4218 | DRM_DEBUG_KMS("EDID test requested\n"); | |
4219 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; | |
4220 | response = intel_dp_autotest_edid(intel_dp); | |
4221 | break; | |
4222 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
4223 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
4224 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; | |
4225 | response = intel_dp_autotest_phy_pattern(intel_dp); | |
4226 | break; | |
4227 | default: | |
4228 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); | |
4229 | break; | |
4230 | } | |
4231 | ||
4232 | update_status: | |
4233 | status = drm_dp_dpcd_write(&intel_dp->aux, | |
4234 | DP_TEST_RESPONSE, | |
4235 | &response, 1); | |
4236 | if (status <= 0) | |
4237 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
4238 | } |
4239 | ||
0e32b39c DA |
4240 | static int |
4241 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
4242 | { | |
4243 | bool bret; | |
4244 | ||
4245 | if (intel_dp->is_mst) { | |
4246 | u8 esi[16] = { 0 }; | |
4247 | int ret = 0; | |
4248 | int retry; | |
4249 | bool handled; | |
4250 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4251 | go_again: | |
4252 | if (bret == true) { | |
4253 | ||
4254 | /* check link status - esi[10] = 0x200c */ | |
4255 | if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { | |
4256 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); | |
4257 | intel_dp_start_link_train(intel_dp); | |
4258 | intel_dp_complete_link_train(intel_dp); | |
4259 | intel_dp_stop_link_train(intel_dp); | |
4260 | } | |
4261 | ||
6f34cc39 | 4262 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
4263 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4264 | ||
4265 | if (handled) { | |
4266 | for (retry = 0; retry < 3; retry++) { | |
4267 | int wret; | |
4268 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
4269 | DP_SINK_COUNT_ESI+1, | |
4270 | &esi[1], 3); | |
4271 | if (wret == 3) { | |
4272 | break; | |
4273 | } | |
4274 | } | |
4275 | ||
4276 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4277 | if (bret == true) { | |
6f34cc39 | 4278 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
4279 | goto go_again; |
4280 | } | |
4281 | } else | |
4282 | ret = 0; | |
4283 | ||
4284 | return ret; | |
4285 | } else { | |
4286 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4287 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4288 | intel_dp->is_mst = false; | |
4289 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4290 | /* send a hotplug event */ | |
4291 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4292 | } | |
4293 | } | |
4294 | return -EINVAL; | |
4295 | } | |
4296 | ||
a4fc5ed6 KP |
4297 | /* |
4298 | * According to DP spec | |
4299 | * 5.1.2: | |
4300 | * 1. Read DPCD | |
4301 | * 2. Configure link according to Receiver Capabilities | |
4302 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4303 | * 4. Check link status on receipt of hot-plug interrupt | |
4304 | */ | |
a5146200 | 4305 | static void |
ea5b213a | 4306 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 4307 | { |
5b215bcf | 4308 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
da63a9f2 | 4309 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 4310 | u8 sink_irq_vector; |
93f62dad | 4311 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 4312 | |
5b215bcf DA |
4313 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
4314 | ||
e02f9a06 | 4315 | if (!intel_encoder->base.crtc) |
a4fc5ed6 KP |
4316 | return; |
4317 | ||
1a125d8a ID |
4318 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4319 | return; | |
4320 | ||
92fd8fd1 | 4321 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 4322 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
a4fc5ed6 KP |
4323 | return; |
4324 | } | |
4325 | ||
92fd8fd1 | 4326 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 4327 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
4328 | return; |
4329 | } | |
4330 | ||
a60f0e38 JB |
4331 | /* Try to read the source of the interrupt */ |
4332 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
4333 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
4334 | /* Clear interrupt source */ | |
9d1a1031 JN |
4335 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4336 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4337 | sink_irq_vector); | |
a60f0e38 JB |
4338 | |
4339 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
09b1eb13 | 4340 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
a60f0e38 JB |
4341 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4342 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4343 | } | |
4344 | ||
1ffdff13 | 4345 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 4346 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
8e329a03 | 4347 | intel_encoder->base.name); |
33a34e4e JB |
4348 | intel_dp_start_link_train(intel_dp); |
4349 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 | 4350 | intel_dp_stop_link_train(intel_dp); |
33a34e4e | 4351 | } |
a4fc5ed6 | 4352 | } |
a4fc5ed6 | 4353 | |
caf9ab24 | 4354 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4355 | static enum drm_connector_status |
26d61aad | 4356 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4357 | { |
caf9ab24 | 4358 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4359 | uint8_t type; |
4360 | ||
4361 | if (!intel_dp_get_dpcd(intel_dp)) | |
4362 | return connector_status_disconnected; | |
4363 | ||
4364 | /* if there's no downstream port, we're done */ | |
4365 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 4366 | return connector_status_connected; |
caf9ab24 AJ |
4367 | |
4368 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4369 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4370 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
23235177 | 4371 | uint8_t reg; |
9d1a1031 JN |
4372 | |
4373 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, | |
4374 | ®, 1) < 0) | |
caf9ab24 | 4375 | return connector_status_unknown; |
9d1a1031 | 4376 | |
23235177 AJ |
4377 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4378 | : connector_status_disconnected; | |
caf9ab24 AJ |
4379 | } |
4380 | ||
4381 | /* If no HPD, poke DDC gently */ | |
0b99836f | 4382 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4383 | return connector_status_connected; |
caf9ab24 AJ |
4384 | |
4385 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4386 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4387 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4388 | if (type == DP_DS_PORT_TYPE_VGA || | |
4389 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4390 | return connector_status_unknown; | |
4391 | } else { | |
4392 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4393 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4394 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4395 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4396 | return connector_status_unknown; | |
4397 | } | |
caf9ab24 AJ |
4398 | |
4399 | /* Anything else is out of spec, warn and ignore */ | |
4400 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4401 | return connector_status_disconnected; |
71ba9000 AJ |
4402 | } |
4403 | ||
d410b56d CW |
4404 | static enum drm_connector_status |
4405 | edp_detect(struct intel_dp *intel_dp) | |
4406 | { | |
4407 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4408 | enum drm_connector_status status; | |
4409 | ||
4410 | status = intel_panel_detect(dev); | |
4411 | if (status == connector_status_unknown) | |
4412 | status = connector_status_connected; | |
4413 | ||
4414 | return status; | |
4415 | } | |
4416 | ||
5eb08b69 | 4417 | static enum drm_connector_status |
a9756bb5 | 4418 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 4419 | { |
30add22d | 4420 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
4421 | struct drm_i915_private *dev_priv = dev->dev_private; |
4422 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
01cb9ea6 | 4423 | |
1b469639 DL |
4424 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
4425 | return connector_status_disconnected; | |
4426 | ||
26d61aad | 4427 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
4428 | } |
4429 | ||
2a592bec DA |
4430 | static int g4x_digital_port_connected(struct drm_device *dev, |
4431 | struct intel_digital_port *intel_dig_port) | |
a4fc5ed6 | 4432 | { |
a4fc5ed6 | 4433 | struct drm_i915_private *dev_priv = dev->dev_private; |
10f76a38 | 4434 | uint32_t bit; |
5eb08b69 | 4435 | |
232a6ee9 TP |
4436 | if (IS_VALLEYVIEW(dev)) { |
4437 | switch (intel_dig_port->port) { | |
4438 | case PORT_B: | |
4439 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; | |
4440 | break; | |
4441 | case PORT_C: | |
4442 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; | |
4443 | break; | |
4444 | case PORT_D: | |
4445 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; | |
4446 | break; | |
4447 | default: | |
2a592bec | 4448 | return -EINVAL; |
232a6ee9 TP |
4449 | } |
4450 | } else { | |
4451 | switch (intel_dig_port->port) { | |
4452 | case PORT_B: | |
4453 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4454 | break; | |
4455 | case PORT_C: | |
4456 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4457 | break; | |
4458 | case PORT_D: | |
4459 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4460 | break; | |
4461 | default: | |
2a592bec | 4462 | return -EINVAL; |
232a6ee9 | 4463 | } |
a4fc5ed6 KP |
4464 | } |
4465 | ||
10f76a38 | 4466 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
2a592bec DA |
4467 | return 0; |
4468 | return 1; | |
4469 | } | |
4470 | ||
4471 | static enum drm_connector_status | |
4472 | g4x_dp_detect(struct intel_dp *intel_dp) | |
4473 | { | |
4474 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4475 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4476 | int ret; | |
4477 | ||
4478 | /* Can't disconnect eDP, but you can close the lid... */ | |
4479 | if (is_edp(intel_dp)) { | |
4480 | enum drm_connector_status status; | |
4481 | ||
4482 | status = intel_panel_detect(dev); | |
4483 | if (status == connector_status_unknown) | |
4484 | status = connector_status_connected; | |
4485 | return status; | |
4486 | } | |
4487 | ||
4488 | ret = g4x_digital_port_connected(dev, intel_dig_port); | |
4489 | if (ret == -EINVAL) | |
4490 | return connector_status_unknown; | |
4491 | else if (ret == 0) | |
a4fc5ed6 KP |
4492 | return connector_status_disconnected; |
4493 | ||
26d61aad | 4494 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
4495 | } |
4496 | ||
8c241fef | 4497 | static struct edid * |
beb60608 | 4498 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4499 | { |
beb60608 | 4500 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4501 | |
9cd300e0 JN |
4502 | /* use cached edid if we have one */ |
4503 | if (intel_connector->edid) { | |
9cd300e0 JN |
4504 | /* invalid edid */ |
4505 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4506 | return NULL; |
4507 | ||
55e9edeb | 4508 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4509 | } else |
4510 | return drm_get_edid(&intel_connector->base, | |
4511 | &intel_dp->aux.ddc); | |
4512 | } | |
8c241fef | 4513 | |
beb60608 CW |
4514 | static void |
4515 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4516 | { | |
4517 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4518 | struct edid *edid; | |
8c241fef | 4519 | |
beb60608 CW |
4520 | edid = intel_dp_get_edid(intel_dp); |
4521 | intel_connector->detect_edid = edid; | |
4522 | ||
4523 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4524 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4525 | else | |
4526 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4527 | } |
4528 | ||
beb60608 CW |
4529 | static void |
4530 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4531 | { |
beb60608 | 4532 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4533 | |
beb60608 CW |
4534 | kfree(intel_connector->detect_edid); |
4535 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4536 | |
beb60608 CW |
4537 | intel_dp->has_audio = false; |
4538 | } | |
d6f24d0f | 4539 | |
beb60608 CW |
4540 | static enum intel_display_power_domain |
4541 | intel_dp_power_get(struct intel_dp *dp) | |
4542 | { | |
4543 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; | |
4544 | enum intel_display_power_domain power_domain; | |
4545 | ||
4546 | power_domain = intel_display_port_power_domain(encoder); | |
4547 | intel_display_power_get(to_i915(encoder->base.dev), power_domain); | |
4548 | ||
4549 | return power_domain; | |
4550 | } | |
d6f24d0f | 4551 | |
beb60608 CW |
4552 | static void |
4553 | intel_dp_power_put(struct intel_dp *dp, | |
4554 | enum intel_display_power_domain power_domain) | |
4555 | { | |
4556 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; | |
4557 | intel_display_power_put(to_i915(encoder->base.dev), power_domain); | |
8c241fef KP |
4558 | } |
4559 | ||
a9756bb5 ZW |
4560 | static enum drm_connector_status |
4561 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4562 | { | |
4563 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
4564 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4565 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4566 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4567 | enum drm_connector_status status; |
671dedd2 | 4568 | enum intel_display_power_domain power_domain; |
0e32b39c | 4569 | bool ret; |
09b1eb13 | 4570 | u8 sink_irq_vector; |
a9756bb5 | 4571 | |
164c8598 | 4572 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 4573 | connector->base.id, connector->name); |
beb60608 | 4574 | intel_dp_unset_edid(intel_dp); |
164c8598 | 4575 | |
0e32b39c DA |
4576 | if (intel_dp->is_mst) { |
4577 | /* MST devices are disconnected from a monitor POV */ | |
4578 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4579 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
beb60608 | 4580 | return connector_status_disconnected; |
0e32b39c DA |
4581 | } |
4582 | ||
beb60608 | 4583 | power_domain = intel_dp_power_get(intel_dp); |
a9756bb5 | 4584 | |
d410b56d CW |
4585 | /* Can't disconnect eDP, but you can close the lid... */ |
4586 | if (is_edp(intel_dp)) | |
4587 | status = edp_detect(intel_dp); | |
4588 | else if (HAS_PCH_SPLIT(dev)) | |
a9756bb5 ZW |
4589 | status = ironlake_dp_detect(intel_dp); |
4590 | else | |
4591 | status = g4x_dp_detect(intel_dp); | |
4592 | if (status != connector_status_connected) | |
c8c8fb33 | 4593 | goto out; |
a9756bb5 | 4594 | |
0d198328 AJ |
4595 | intel_dp_probe_oui(intel_dp); |
4596 | ||
0e32b39c DA |
4597 | ret = intel_dp_probe_mst(intel_dp); |
4598 | if (ret) { | |
4599 | /* if we are in MST mode then this connector | |
4600 | won't appear connected or have anything with EDID on it */ | |
4601 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4602 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4603 | status = connector_status_disconnected; | |
4604 | goto out; | |
4605 | } | |
4606 | ||
beb60608 | 4607 | intel_dp_set_edid(intel_dp); |
a9756bb5 | 4608 | |
d63885da PZ |
4609 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4610 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
c8c8fb33 PZ |
4611 | status = connector_status_connected; |
4612 | ||
09b1eb13 TP |
4613 | /* Try to read the source of the interrupt */ |
4614 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
4615 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
4616 | /* Clear interrupt source */ | |
4617 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4618 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4619 | sink_irq_vector); | |
4620 | ||
4621 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4622 | intel_dp_handle_test_request(intel_dp); | |
4623 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4624 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4625 | } | |
4626 | ||
c8c8fb33 | 4627 | out: |
beb60608 | 4628 | intel_dp_power_put(intel_dp, power_domain); |
c8c8fb33 | 4629 | return status; |
a4fc5ed6 KP |
4630 | } |
4631 | ||
beb60608 CW |
4632 | static void |
4633 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4634 | { |
df0e9248 | 4635 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4636 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
671dedd2 | 4637 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4638 | |
beb60608 CW |
4639 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4640 | connector->base.id, connector->name); | |
4641 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4642 | |
beb60608 CW |
4643 | if (connector->status != connector_status_connected) |
4644 | return; | |
671dedd2 | 4645 | |
beb60608 CW |
4646 | power_domain = intel_dp_power_get(intel_dp); |
4647 | ||
4648 | intel_dp_set_edid(intel_dp); | |
4649 | ||
4650 | intel_dp_power_put(intel_dp, power_domain); | |
4651 | ||
4652 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4653 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4654 | } | |
4655 | ||
4656 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4657 | { | |
4658 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4659 | struct edid *edid; | |
4660 | ||
4661 | edid = intel_connector->detect_edid; | |
4662 | if (edid) { | |
4663 | int ret = intel_connector_update_modes(connector, edid); | |
4664 | if (ret) | |
4665 | return ret; | |
4666 | } | |
32f9d658 | 4667 | |
f8779fda | 4668 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4669 | if (is_edp(intel_attached_dp(connector)) && |
4670 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4671 | struct drm_display_mode *mode; |
beb60608 CW |
4672 | |
4673 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4674 | intel_connector->panel.fixed_mode); |
f8779fda | 4675 | if (mode) { |
32f9d658 ZW |
4676 | drm_mode_probed_add(connector, mode); |
4677 | return 1; | |
4678 | } | |
4679 | } | |
beb60608 | 4680 | |
32f9d658 | 4681 | return 0; |
a4fc5ed6 KP |
4682 | } |
4683 | ||
1aad7ac0 CW |
4684 | static bool |
4685 | intel_dp_detect_audio(struct drm_connector *connector) | |
4686 | { | |
1aad7ac0 | 4687 | bool has_audio = false; |
beb60608 | 4688 | struct edid *edid; |
1aad7ac0 | 4689 | |
beb60608 CW |
4690 | edid = to_intel_connector(connector)->detect_edid; |
4691 | if (edid) | |
1aad7ac0 | 4692 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4693 | |
1aad7ac0 CW |
4694 | return has_audio; |
4695 | } | |
4696 | ||
f684960e CW |
4697 | static int |
4698 | intel_dp_set_property(struct drm_connector *connector, | |
4699 | struct drm_property *property, | |
4700 | uint64_t val) | |
4701 | { | |
e953fd7b | 4702 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 4703 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4704 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4705 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4706 | int ret; |
4707 | ||
662595df | 4708 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4709 | if (ret) |
4710 | return ret; | |
4711 | ||
3f43c48d | 4712 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4713 | int i = val; |
4714 | bool has_audio; | |
4715 | ||
4716 | if (i == intel_dp->force_audio) | |
f684960e CW |
4717 | return 0; |
4718 | ||
1aad7ac0 | 4719 | intel_dp->force_audio = i; |
f684960e | 4720 | |
c3e5f67b | 4721 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4722 | has_audio = intel_dp_detect_audio(connector); |
4723 | else | |
c3e5f67b | 4724 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4725 | |
4726 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4727 | return 0; |
4728 | ||
1aad7ac0 | 4729 | intel_dp->has_audio = has_audio; |
f684960e CW |
4730 | goto done; |
4731 | } | |
4732 | ||
e953fd7b | 4733 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
4734 | bool old_auto = intel_dp->color_range_auto; |
4735 | uint32_t old_range = intel_dp->color_range; | |
4736 | ||
55bc60db VS |
4737 | switch (val) { |
4738 | case INTEL_BROADCAST_RGB_AUTO: | |
4739 | intel_dp->color_range_auto = true; | |
4740 | break; | |
4741 | case INTEL_BROADCAST_RGB_FULL: | |
4742 | intel_dp->color_range_auto = false; | |
4743 | intel_dp->color_range = 0; | |
4744 | break; | |
4745 | case INTEL_BROADCAST_RGB_LIMITED: | |
4746 | intel_dp->color_range_auto = false; | |
4747 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
4748 | break; | |
4749 | default: | |
4750 | return -EINVAL; | |
4751 | } | |
ae4edb80 DV |
4752 | |
4753 | if (old_auto == intel_dp->color_range_auto && | |
4754 | old_range == intel_dp->color_range) | |
4755 | return 0; | |
4756 | ||
e953fd7b CW |
4757 | goto done; |
4758 | } | |
4759 | ||
53b41837 YN |
4760 | if (is_edp(intel_dp) && |
4761 | property == connector->dev->mode_config.scaling_mode_property) { | |
4762 | if (val == DRM_MODE_SCALE_NONE) { | |
4763 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4764 | return -EINVAL; | |
4765 | } | |
4766 | ||
4767 | if (intel_connector->panel.fitting_mode == val) { | |
4768 | /* the eDP scaling property is not changed */ | |
4769 | return 0; | |
4770 | } | |
4771 | intel_connector->panel.fitting_mode = val; | |
4772 | ||
4773 | goto done; | |
4774 | } | |
4775 | ||
f684960e CW |
4776 | return -EINVAL; |
4777 | ||
4778 | done: | |
c0c36b94 CW |
4779 | if (intel_encoder->base.crtc) |
4780 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4781 | |
4782 | return 0; | |
4783 | } | |
4784 | ||
a4fc5ed6 | 4785 | static void |
73845adf | 4786 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4787 | { |
1d508706 | 4788 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4789 | |
10e972d3 | 4790 | kfree(intel_connector->detect_edid); |
beb60608 | 4791 | |
9cd300e0 JN |
4792 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4793 | kfree(intel_connector->edid); | |
4794 | ||
acd8db10 PZ |
4795 | /* Can't call is_edp() since the encoder may have been destroyed |
4796 | * already. */ | |
4797 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4798 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4799 | |
a4fc5ed6 | 4800 | drm_connector_cleanup(connector); |
55f78c43 | 4801 | kfree(connector); |
a4fc5ed6 KP |
4802 | } |
4803 | ||
00c09d70 | 4804 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4805 | { |
da63a9f2 PZ |
4806 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4807 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4808 | |
4f71d0cb | 4809 | drm_dp_aux_unregister(&intel_dp->aux); |
0e32b39c | 4810 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4811 | if (is_edp(intel_dp)) { |
4812 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4813 | /* |
4814 | * vdd might still be enabled do to the delayed vdd off. | |
4815 | * Make sure vdd is actually turned off here. | |
4816 | */ | |
773538e8 | 4817 | pps_lock(intel_dp); |
4be73780 | 4818 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4819 | pps_unlock(intel_dp); |
4820 | ||
01527b31 CT |
4821 | if (intel_dp->edp_notifier.notifier_call) { |
4822 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4823 | intel_dp->edp_notifier.notifier_call = NULL; | |
4824 | } | |
bd943159 | 4825 | } |
c8bd0e49 | 4826 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4827 | kfree(intel_dig_port); |
24d05927 DV |
4828 | } |
4829 | ||
07f9cd0b ID |
4830 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
4831 | { | |
4832 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4833 | ||
4834 | if (!is_edp(intel_dp)) | |
4835 | return; | |
4836 | ||
951468f3 VS |
4837 | /* |
4838 | * vdd might still be enabled do to the delayed vdd off. | |
4839 | * Make sure vdd is actually turned off here. | |
4840 | */ | |
afa4e53a | 4841 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4842 | pps_lock(intel_dp); |
07f9cd0b | 4843 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4844 | pps_unlock(intel_dp); |
07f9cd0b ID |
4845 | } |
4846 | ||
49e6bc51 VS |
4847 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4848 | { | |
4849 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4850 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
4851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4852 | enum intel_display_power_domain power_domain; | |
4853 | ||
4854 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4855 | ||
4856 | if (!edp_have_panel_vdd(intel_dp)) | |
4857 | return; | |
4858 | ||
4859 | /* | |
4860 | * The VDD bit needs a power domain reference, so if the bit is | |
4861 | * already enabled when we boot or resume, grab this reference and | |
4862 | * schedule a vdd off, so we don't hold on to the reference | |
4863 | * indefinitely. | |
4864 | */ | |
4865 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
4866 | power_domain = intel_display_port_power_domain(&intel_dig_port->base); | |
4867 | intel_display_power_get(dev_priv, power_domain); | |
4868 | ||
4869 | edp_panel_vdd_schedule_off(intel_dp); | |
4870 | } | |
4871 | ||
6d93c0c4 ID |
4872 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
4873 | { | |
49e6bc51 VS |
4874 | struct intel_dp *intel_dp; |
4875 | ||
4876 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) | |
4877 | return; | |
4878 | ||
4879 | intel_dp = enc_to_intel_dp(encoder); | |
4880 | ||
4881 | pps_lock(intel_dp); | |
4882 | ||
4883 | /* | |
4884 | * Read out the current power sequencer assignment, | |
4885 | * in case the BIOS did something with it. | |
4886 | */ | |
4887 | if (IS_VALLEYVIEW(encoder->dev)) | |
4888 | vlv_initial_power_sequencer_setup(intel_dp); | |
4889 | ||
4890 | intel_edp_panel_vdd_sanitize(intel_dp); | |
4891 | ||
4892 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4893 | } |
4894 | ||
a4fc5ed6 | 4895 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4896 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 4897 | .detect = intel_dp_detect, |
beb60608 | 4898 | .force = intel_dp_force, |
a4fc5ed6 | 4899 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4900 | .set_property = intel_dp_set_property, |
2545e4a6 | 4901 | .atomic_get_property = intel_connector_atomic_get_property, |
73845adf | 4902 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4903 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 4904 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
4905 | }; |
4906 | ||
4907 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4908 | .get_modes = intel_dp_get_modes, | |
4909 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 4910 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
4911 | }; |
4912 | ||
a4fc5ed6 | 4913 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4914 | .reset = intel_dp_encoder_reset, |
24d05927 | 4915 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4916 | }; |
4917 | ||
b2c5c181 | 4918 | enum irqreturn |
13cf5504 DA |
4919 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4920 | { | |
4921 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4922 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c DA |
4923 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c767b33 | 4925 | enum intel_display_power_domain power_domain; |
b2c5c181 | 4926 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 4927 | |
0e32b39c DA |
4928 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
4929 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; | |
13cf5504 | 4930 | |
7a7f84cc VS |
4931 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4932 | /* | |
4933 | * vdd off can generate a long pulse on eDP which | |
4934 | * would require vdd on to handle it, and thus we | |
4935 | * would end up in an endless cycle of | |
4936 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
4937 | */ | |
4938 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
4939 | port_name(intel_dig_port->port)); | |
a8b3d52f | 4940 | return IRQ_HANDLED; |
7a7f84cc VS |
4941 | } |
4942 | ||
26fbb774 VS |
4943 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4944 | port_name(intel_dig_port->port), | |
0e32b39c | 4945 | long_hpd ? "long" : "short"); |
13cf5504 | 4946 | |
1c767b33 ID |
4947 | power_domain = intel_display_port_power_domain(intel_encoder); |
4948 | intel_display_power_get(dev_priv, power_domain); | |
4949 | ||
0e32b39c | 4950 | if (long_hpd) { |
5fa836a9 MK |
4951 | /* indicate that we need to restart link training */ |
4952 | intel_dp->train_set_valid = false; | |
2a592bec DA |
4953 | |
4954 | if (HAS_PCH_SPLIT(dev)) { | |
4955 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) | |
4956 | goto mst_fail; | |
4957 | } else { | |
4958 | if (g4x_digital_port_connected(dev, intel_dig_port) != 1) | |
4959 | goto mst_fail; | |
4960 | } | |
0e32b39c DA |
4961 | |
4962 | if (!intel_dp_get_dpcd(intel_dp)) { | |
4963 | goto mst_fail; | |
4964 | } | |
4965 | ||
4966 | intel_dp_probe_oui(intel_dp); | |
4967 | ||
4968 | if (!intel_dp_probe_mst(intel_dp)) | |
4969 | goto mst_fail; | |
4970 | ||
4971 | } else { | |
4972 | if (intel_dp->is_mst) { | |
1c767b33 | 4973 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
0e32b39c DA |
4974 | goto mst_fail; |
4975 | } | |
4976 | ||
4977 | if (!intel_dp->is_mst) { | |
4978 | /* | |
4979 | * we'll check the link status via the normal hot plug path later - | |
4980 | * but for short hpds we should check it now | |
4981 | */ | |
5b215bcf | 4982 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
0e32b39c | 4983 | intel_dp_check_link_status(intel_dp); |
5b215bcf | 4984 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
0e32b39c DA |
4985 | } |
4986 | } | |
b2c5c181 DV |
4987 | |
4988 | ret = IRQ_HANDLED; | |
4989 | ||
1c767b33 | 4990 | goto put_power; |
0e32b39c DA |
4991 | mst_fail: |
4992 | /* if we were in MST mode, and device is not there get out of MST mode */ | |
4993 | if (intel_dp->is_mst) { | |
4994 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4995 | intel_dp->is_mst = false; | |
4996 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4997 | } | |
1c767b33 ID |
4998 | put_power: |
4999 | intel_display_power_put(dev_priv, power_domain); | |
5000 | ||
5001 | return ret; | |
13cf5504 DA |
5002 | } |
5003 | ||
e3421a18 ZW |
5004 | /* Return which DP Port should be selected for Transcoder DP control */ |
5005 | int | |
0206e353 | 5006 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
5007 | { |
5008 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
5009 | struct intel_encoder *intel_encoder; |
5010 | struct intel_dp *intel_dp; | |
e3421a18 | 5011 | |
fa90ecef PZ |
5012 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5013 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 5014 | |
fa90ecef PZ |
5015 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
5016 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 5017 | return intel_dp->output_reg; |
e3421a18 | 5018 | } |
ea5b213a | 5019 | |
e3421a18 ZW |
5020 | return -1; |
5021 | } | |
5022 | ||
36e83a18 | 5023 | /* check the VBT to see whether the eDP is on DP-D port */ |
5d8a7752 | 5024 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
5025 | { |
5026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768f69c9 | 5027 | union child_device_config *p_child; |
36e83a18 | 5028 | int i; |
5d8a7752 VS |
5029 | static const short port_mapping[] = { |
5030 | [PORT_B] = PORT_IDPB, | |
5031 | [PORT_C] = PORT_IDPC, | |
5032 | [PORT_D] = PORT_IDPD, | |
5033 | }; | |
36e83a18 | 5034 | |
3b32a35b VS |
5035 | if (port == PORT_A) |
5036 | return true; | |
5037 | ||
41aa3448 | 5038 | if (!dev_priv->vbt.child_dev_num) |
36e83a18 ZY |
5039 | return false; |
5040 | ||
41aa3448 RV |
5041 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
5042 | p_child = dev_priv->vbt.child_dev + i; | |
36e83a18 | 5043 | |
5d8a7752 | 5044 | if (p_child->common.dvo_port == port_mapping[port] && |
f02586df VS |
5045 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
5046 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) | |
36e83a18 ZY |
5047 | return true; |
5048 | } | |
5049 | return false; | |
5050 | } | |
5051 | ||
0e32b39c | 5052 | void |
f684960e CW |
5053 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5054 | { | |
53b41837 YN |
5055 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5056 | ||
3f43c48d | 5057 | intel_attach_force_audio_property(connector); |
e953fd7b | 5058 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 5059 | intel_dp->color_range_auto = true; |
53b41837 YN |
5060 | |
5061 | if (is_edp(intel_dp)) { | |
5062 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
5063 | drm_object_attach_property( |
5064 | &connector->base, | |
53b41837 | 5065 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
5066 | DRM_MODE_SCALE_ASPECT); |
5067 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 5068 | } |
f684960e CW |
5069 | } |
5070 | ||
dada1a9f ID |
5071 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5072 | { | |
5073 | intel_dp->last_power_cycle = jiffies; | |
5074 | intel_dp->last_power_on = jiffies; | |
5075 | intel_dp->last_backlight_off = jiffies; | |
5076 | } | |
5077 | ||
67a54566 DV |
5078 | static void |
5079 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 5080 | struct intel_dp *intel_dp) |
67a54566 DV |
5081 | { |
5082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
36b5f425 VS |
5083 | struct edp_power_seq cur, vbt, spec, |
5084 | *final = &intel_dp->pps_delays; | |
b0a08bec VK |
5085 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
5086 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0; | |
453c5420 | 5087 | |
e39b999a VS |
5088 | lockdep_assert_held(&dev_priv->pps_mutex); |
5089 | ||
81ddbc69 VS |
5090 | /* already initialized? */ |
5091 | if (final->t11_t12 != 0) | |
5092 | return; | |
5093 | ||
b0a08bec VK |
5094 | if (IS_BROXTON(dev)) { |
5095 | /* | |
5096 | * TODO: BXT has 2 sets of PPS registers. | |
5097 | * Correct Register for Broxton need to be identified | |
5098 | * using VBT. hardcoding for now | |
5099 | */ | |
5100 | pp_ctrl_reg = BXT_PP_CONTROL(0); | |
5101 | pp_on_reg = BXT_PP_ON_DELAYS(0); | |
5102 | pp_off_reg = BXT_PP_OFF_DELAYS(0); | |
5103 | } else if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 5104 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
5105 | pp_on_reg = PCH_PP_ON_DELAYS; |
5106 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
5107 | pp_div_reg = PCH_PP_DIVISOR; | |
5108 | } else { | |
bf13e81b JN |
5109 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5110 | ||
5111 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
5112 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
5113 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
5114 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 5115 | } |
67a54566 DV |
5116 | |
5117 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
5118 | * the very first thing. */ | |
b0a08bec | 5119 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 5120 | |
453c5420 JB |
5121 | pp_on = I915_READ(pp_on_reg); |
5122 | pp_off = I915_READ(pp_off_reg); | |
b0a08bec VK |
5123 | if (!IS_BROXTON(dev)) { |
5124 | I915_WRITE(pp_ctrl_reg, pp_ctl); | |
5125 | pp_div = I915_READ(pp_div_reg); | |
5126 | } | |
67a54566 DV |
5127 | |
5128 | /* Pull timing values out of registers */ | |
5129 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
5130 | PANEL_POWER_UP_DELAY_SHIFT; | |
5131 | ||
5132 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
5133 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
5134 | ||
5135 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
5136 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
5137 | ||
5138 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
5139 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
5140 | ||
b0a08bec VK |
5141 | if (IS_BROXTON(dev)) { |
5142 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> | |
5143 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
5144 | if (tmp > 0) | |
5145 | cur.t11_t12 = (tmp - 1) * 1000; | |
5146 | else | |
5147 | cur.t11_t12 = 0; | |
5148 | } else { | |
5149 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
67a54566 | 5150 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 5151 | } |
67a54566 DV |
5152 | |
5153 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5154 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
5155 | ||
41aa3448 | 5156 | vbt = dev_priv->vbt.edp_pps; |
67a54566 DV |
5157 | |
5158 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5159 | * our hw here, which are all in 100usec. */ | |
5160 | spec.t1_t3 = 210 * 10; | |
5161 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5162 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5163 | spec.t10 = 500 * 10; | |
5164 | /* This one is special and actually in units of 100ms, but zero | |
5165 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5166 | * table multiplies it with 1000 to make it in units of 100usec, | |
5167 | * too. */ | |
5168 | spec.t11_t12 = (510 + 100) * 10; | |
5169 | ||
5170 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5171 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
5172 | ||
5173 | /* Use the max of the register settings and vbt. If both are | |
5174 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5175 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5176 | spec.field : \ |
5177 | max(cur.field, vbt.field)) | |
5178 | assign_final(t1_t3); | |
5179 | assign_final(t8); | |
5180 | assign_final(t9); | |
5181 | assign_final(t10); | |
5182 | assign_final(t11_t12); | |
5183 | #undef assign_final | |
5184 | ||
36b5f425 | 5185 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5186 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5187 | intel_dp->backlight_on_delay = get_delay(t8); | |
5188 | intel_dp->backlight_off_delay = get_delay(t9); | |
5189 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5190 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5191 | #undef get_delay | |
5192 | ||
f30d26e4 JN |
5193 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5194 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5195 | intel_dp->panel_power_cycle_delay); | |
5196 | ||
5197 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5198 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
f30d26e4 JN |
5199 | } |
5200 | ||
5201 | static void | |
5202 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 5203 | struct intel_dp *intel_dp) |
f30d26e4 JN |
5204 | { |
5205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
5206 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5207 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
b0a08bec | 5208 | int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg; |
ad933b56 | 5209 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5210 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5211 | |
e39b999a | 5212 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5213 | |
b0a08bec VK |
5214 | if (IS_BROXTON(dev)) { |
5215 | /* | |
5216 | * TODO: BXT has 2 sets of PPS registers. | |
5217 | * Correct Register for Broxton need to be identified | |
5218 | * using VBT. hardcoding for now | |
5219 | */ | |
5220 | pp_ctrl_reg = BXT_PP_CONTROL(0); | |
5221 | pp_on_reg = BXT_PP_ON_DELAYS(0); | |
5222 | pp_off_reg = BXT_PP_OFF_DELAYS(0); | |
5223 | ||
5224 | } else if (HAS_PCH_SPLIT(dev)) { | |
453c5420 JB |
5225 | pp_on_reg = PCH_PP_ON_DELAYS; |
5226 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
5227 | pp_div_reg = PCH_PP_DIVISOR; | |
5228 | } else { | |
bf13e81b JN |
5229 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5230 | ||
5231 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
5232 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
5233 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
5234 | } |
5235 | ||
b2f19d1a PZ |
5236 | /* |
5237 | * And finally store the new values in the power sequencer. The | |
5238 | * backlight delays are set to 1 because we do manual waits on them. For | |
5239 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
5240 | * we'll end up waiting for the backlight off delay twice: once when we | |
5241 | * do the manual sleep, and once when we disable the panel and wait for | |
5242 | * the PP_STATUS bit to become zero. | |
5243 | */ | |
f30d26e4 | 5244 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
5245 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5246 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5247 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5248 | /* Compute the divisor for the pp clock, simply match the Bspec |
5249 | * formula. */ | |
b0a08bec VK |
5250 | if (IS_BROXTON(dev)) { |
5251 | pp_div = I915_READ(pp_ctrl_reg); | |
5252 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; | |
5253 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
5254 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
5255 | } else { | |
5256 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5257 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5258 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5259 | } | |
67a54566 DV |
5260 | |
5261 | /* Haswell doesn't have any port selection bits for the panel | |
5262 | * power sequencer any more. */ | |
bc7d38a4 | 5263 | if (IS_VALLEYVIEW(dev)) { |
ad933b56 | 5264 | port_sel = PANEL_PORT_SELECT_VLV(port); |
bc7d38a4 | 5265 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
ad933b56 | 5266 | if (port == PORT_A) |
a24c144c | 5267 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5268 | else |
a24c144c | 5269 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5270 | } |
5271 | ||
453c5420 JB |
5272 | pp_on |= port_sel; |
5273 | ||
5274 | I915_WRITE(pp_on_reg, pp_on); | |
5275 | I915_WRITE(pp_off_reg, pp_off); | |
b0a08bec VK |
5276 | if (IS_BROXTON(dev)) |
5277 | I915_WRITE(pp_ctrl_reg, pp_div); | |
5278 | else | |
5279 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 5280 | |
67a54566 | 5281 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
5282 | I915_READ(pp_on_reg), |
5283 | I915_READ(pp_off_reg), | |
b0a08bec VK |
5284 | IS_BROXTON(dev) ? |
5285 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : | |
453c5420 | 5286 | I915_READ(pp_div_reg)); |
f684960e CW |
5287 | } |
5288 | ||
b33a2815 VK |
5289 | /** |
5290 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5291 | * @dev: DRM device | |
5292 | * @refresh_rate: RR to be programmed | |
5293 | * | |
5294 | * This function gets called when refresh rate (RR) has to be changed from | |
5295 | * one frequency to another. Switches can be between high and low RR | |
5296 | * supported by the panel or to any other RR based on media playback (in | |
5297 | * this case, RR value needs to be passed from user space). | |
5298 | * | |
5299 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5300 | */ | |
96178eeb | 5301 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
439d7ac0 PB |
5302 | { |
5303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5304 | struct intel_encoder *encoder; | |
96178eeb VK |
5305 | struct intel_digital_port *dig_port = NULL; |
5306 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
5cec258b | 5307 | struct intel_crtc_state *config = NULL; |
439d7ac0 | 5308 | struct intel_crtc *intel_crtc = NULL; |
439d7ac0 | 5309 | u32 reg, val; |
96178eeb | 5310 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5311 | |
5312 | if (refresh_rate <= 0) { | |
5313 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5314 | return; | |
5315 | } | |
5316 | ||
96178eeb VK |
5317 | if (intel_dp == NULL) { |
5318 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5319 | return; |
5320 | } | |
5321 | ||
1fcc9d1c | 5322 | /* |
e4d59f6b RV |
5323 | * FIXME: This needs proper synchronization with psr state for some |
5324 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5325 | */ |
439d7ac0 | 5326 | |
96178eeb VK |
5327 | dig_port = dp_to_dig_port(intel_dp); |
5328 | encoder = &dig_port->base; | |
723f9aab | 5329 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5330 | |
5331 | if (!intel_crtc) { | |
5332 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5333 | return; | |
5334 | } | |
5335 | ||
6e3c9717 | 5336 | config = intel_crtc->config; |
439d7ac0 | 5337 | |
96178eeb | 5338 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5339 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5340 | return; | |
5341 | } | |
5342 | ||
96178eeb VK |
5343 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5344 | refresh_rate) | |
439d7ac0 PB |
5345 | index = DRRS_LOW_RR; |
5346 | ||
96178eeb | 5347 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5348 | DRM_DEBUG_KMS( |
5349 | "DRRS requested for previously set RR...ignoring\n"); | |
5350 | return; | |
5351 | } | |
5352 | ||
5353 | if (!intel_crtc->active) { | |
5354 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); | |
5355 | return; | |
5356 | } | |
5357 | ||
44395bfe | 5358 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
a4c30b1d VK |
5359 | switch (index) { |
5360 | case DRRS_HIGH_RR: | |
5361 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5362 | break; | |
5363 | case DRRS_LOW_RR: | |
5364 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5365 | break; | |
5366 | case DRRS_MAX_RR: | |
5367 | default: | |
5368 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5369 | } | |
5370 | } else if (INTEL_INFO(dev)->gen > 6) { | |
6e3c9717 | 5371 | reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
439d7ac0 | 5372 | val = I915_READ(reg); |
a4c30b1d | 5373 | |
439d7ac0 | 5374 | if (index > DRRS_HIGH_RR) { |
6fa7aec1 VK |
5375 | if (IS_VALLEYVIEW(dev)) |
5376 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; | |
5377 | else | |
5378 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5379 | } else { |
6fa7aec1 VK |
5380 | if (IS_VALLEYVIEW(dev)) |
5381 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; | |
5382 | else | |
5383 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5384 | } |
5385 | I915_WRITE(reg, val); | |
5386 | } | |
5387 | ||
4e9ac947 VK |
5388 | dev_priv->drrs.refresh_rate_type = index; |
5389 | ||
5390 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5391 | } | |
5392 | ||
b33a2815 VK |
5393 | /** |
5394 | * intel_edp_drrs_enable - init drrs struct if supported | |
5395 | * @intel_dp: DP struct | |
5396 | * | |
5397 | * Initializes frontbuffer_bits and drrs.dp | |
5398 | */ | |
c395578e VK |
5399 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5400 | { | |
5401 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
5402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5403 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
5404 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5405 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5406 | ||
5407 | if (!intel_crtc->config->has_drrs) { | |
5408 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); | |
5409 | return; | |
5410 | } | |
5411 | ||
5412 | mutex_lock(&dev_priv->drrs.mutex); | |
5413 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5414 | DRM_ERROR("DRRS already enabled\n"); | |
5415 | goto unlock; | |
5416 | } | |
5417 | ||
5418 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5419 | ||
5420 | dev_priv->drrs.dp = intel_dp; | |
5421 | ||
5422 | unlock: | |
5423 | mutex_unlock(&dev_priv->drrs.mutex); | |
5424 | } | |
5425 | ||
b33a2815 VK |
5426 | /** |
5427 | * intel_edp_drrs_disable - Disable DRRS | |
5428 | * @intel_dp: DP struct | |
5429 | * | |
5430 | */ | |
c395578e VK |
5431 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5432 | { | |
5433 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
5434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5435 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
5436 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5438 | ||
5439 | if (!intel_crtc->config->has_drrs) | |
5440 | return; | |
5441 | ||
5442 | mutex_lock(&dev_priv->drrs.mutex); | |
5443 | if (!dev_priv->drrs.dp) { | |
5444 | mutex_unlock(&dev_priv->drrs.mutex); | |
5445 | return; | |
5446 | } | |
5447 | ||
5448 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
5449 | intel_dp_set_drrs_state(dev_priv->dev, | |
5450 | intel_dp->attached_connector->panel. | |
5451 | fixed_mode->vrefresh); | |
5452 | ||
5453 | dev_priv->drrs.dp = NULL; | |
5454 | mutex_unlock(&dev_priv->drrs.mutex); | |
5455 | ||
5456 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5457 | } | |
5458 | ||
4e9ac947 VK |
5459 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5460 | { | |
5461 | struct drm_i915_private *dev_priv = | |
5462 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5463 | struct intel_dp *intel_dp; | |
5464 | ||
5465 | mutex_lock(&dev_priv->drrs.mutex); | |
5466 | ||
5467 | intel_dp = dev_priv->drrs.dp; | |
5468 | ||
5469 | if (!intel_dp) | |
5470 | goto unlock; | |
5471 | ||
439d7ac0 | 5472 | /* |
4e9ac947 VK |
5473 | * The delayed work can race with an invalidate hence we need to |
5474 | * recheck. | |
439d7ac0 PB |
5475 | */ |
5476 | ||
4e9ac947 VK |
5477 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5478 | goto unlock; | |
439d7ac0 | 5479 | |
4e9ac947 VK |
5480 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5481 | intel_dp_set_drrs_state(dev_priv->dev, | |
5482 | intel_dp->attached_connector->panel. | |
5483 | downclock_mode->vrefresh); | |
439d7ac0 | 5484 | |
4e9ac947 | 5485 | unlock: |
4e9ac947 | 5486 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5487 | } |
5488 | ||
b33a2815 | 5489 | /** |
0ddfd203 | 5490 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
b33a2815 VK |
5491 | * @dev: DRM device |
5492 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
5493 | * | |
0ddfd203 R |
5494 | * This function gets called everytime rendering on the given planes start. |
5495 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5496 | * |
5497 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5498 | */ | |
a93fad0f VK |
5499 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5500 | unsigned frontbuffer_bits) | |
5501 | { | |
5502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5503 | struct drm_crtc *crtc; | |
5504 | enum pipe pipe; | |
5505 | ||
9da7d693 | 5506 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5507 | return; |
5508 | ||
88f933a8 | 5509 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5510 | |
a93fad0f | 5511 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5512 | if (!dev_priv->drrs.dp) { |
5513 | mutex_unlock(&dev_priv->drrs.mutex); | |
5514 | return; | |
5515 | } | |
5516 | ||
a93fad0f VK |
5517 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5518 | pipe = to_intel_crtc(crtc)->pipe; | |
5519 | ||
c1d038c6 DV |
5520 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5521 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5522 | ||
0ddfd203 | 5523 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5524 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
a93fad0f VK |
5525 | intel_dp_set_drrs_state(dev_priv->dev, |
5526 | dev_priv->drrs.dp->attached_connector->panel. | |
5527 | fixed_mode->vrefresh); | |
a93fad0f | 5528 | |
a93fad0f VK |
5529 | mutex_unlock(&dev_priv->drrs.mutex); |
5530 | } | |
5531 | ||
b33a2815 | 5532 | /** |
0ddfd203 | 5533 | * intel_edp_drrs_flush - Restart Idleness DRRS |
b33a2815 VK |
5534 | * @dev: DRM device |
5535 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
5536 | * | |
0ddfd203 R |
5537 | * This function gets called every time rendering on the given planes has |
5538 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5539 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5540 | * if no other planes are dirty. | |
b33a2815 VK |
5541 | * |
5542 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5543 | */ | |
a93fad0f VK |
5544 | void intel_edp_drrs_flush(struct drm_device *dev, |
5545 | unsigned frontbuffer_bits) | |
5546 | { | |
5547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5548 | struct drm_crtc *crtc; | |
5549 | enum pipe pipe; | |
5550 | ||
9da7d693 | 5551 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5552 | return; |
5553 | ||
88f933a8 | 5554 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5555 | |
a93fad0f | 5556 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5557 | if (!dev_priv->drrs.dp) { |
5558 | mutex_unlock(&dev_priv->drrs.mutex); | |
5559 | return; | |
5560 | } | |
5561 | ||
a93fad0f VK |
5562 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5563 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5564 | |
5565 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5566 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5567 | ||
0ddfd203 | 5568 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5569 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
0ddfd203 R |
5570 | intel_dp_set_drrs_state(dev_priv->dev, |
5571 | dev_priv->drrs.dp->attached_connector->panel. | |
5572 | fixed_mode->vrefresh); | |
5573 | ||
5574 | /* | |
5575 | * flush also means no more activity hence schedule downclock, if all | |
5576 | * other fbs are quiescent too | |
5577 | */ | |
5578 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5579 | schedule_delayed_work(&dev_priv->drrs.work, |
5580 | msecs_to_jiffies(1000)); | |
5581 | mutex_unlock(&dev_priv->drrs.mutex); | |
5582 | } | |
5583 | ||
b33a2815 VK |
5584 | /** |
5585 | * DOC: Display Refresh Rate Switching (DRRS) | |
5586 | * | |
5587 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5588 | * which enables swtching between low and high refresh rates, | |
5589 | * dynamically, based on the usage scenario. This feature is applicable | |
5590 | * for internal panels. | |
5591 | * | |
5592 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5593 | * would list multiple refresh rates for one resolution. | |
5594 | * | |
5595 | * DRRS is of 2 types - static and seamless. | |
5596 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5597 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5598 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5599 | * and can be used during normal system usage. This is done by programming | |
5600 | * certain registers. | |
5601 | * | |
5602 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5603 | * inputs from the panel spec. | |
5604 | * | |
5605 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5606 | * | |
5607 | * eDP DRRS:- | |
5608 | * The implementation is based on frontbuffer tracking implementation. | |
5609 | * When there is a disturbance on the screen triggered by user activity or a | |
5610 | * periodic system activity, DRRS is disabled (RR is changed to high RR). | |
5611 | * When there is no movement on screen, after a timeout of 1 second, a switch | |
5612 | * to low RR is made. | |
5613 | * For integration with frontbuffer tracking code, | |
5614 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. | |
5615 | * | |
5616 | * DRRS can be further extended to support other internal panels and also | |
5617 | * the scenario of video playback wherein RR is set based on the rate | |
5618 | * requested by userspace. | |
5619 | */ | |
5620 | ||
5621 | /** | |
5622 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5623 | * @intel_connector: eDP connector | |
5624 | * @fixed_mode: preferred mode of panel | |
5625 | * | |
5626 | * This function is called only once at driver load to initialize basic | |
5627 | * DRRS stuff. | |
5628 | * | |
5629 | * Returns: | |
5630 | * Downclock mode if panel supports it, else return NULL. | |
5631 | * DRRS support is determined by the presence of downclock mode (apart | |
5632 | * from VBT setting). | |
5633 | */ | |
4f9db5b5 | 5634 | static struct drm_display_mode * |
96178eeb VK |
5635 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5636 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5637 | { |
5638 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5639 | struct drm_device *dev = connector->dev; |
4f9db5b5 PB |
5640 | struct drm_i915_private *dev_priv = dev->dev_private; |
5641 | struct drm_display_mode *downclock_mode = NULL; | |
5642 | ||
9da7d693 DV |
5643 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5644 | mutex_init(&dev_priv->drrs.mutex); | |
5645 | ||
4f9db5b5 PB |
5646 | if (INTEL_INFO(dev)->gen <= 6) { |
5647 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); | |
5648 | return NULL; | |
5649 | } | |
5650 | ||
5651 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5652 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5653 | return NULL; |
5654 | } | |
5655 | ||
5656 | downclock_mode = intel_find_panel_downclock | |
5657 | (dev, fixed_mode, connector); | |
5658 | ||
5659 | if (!downclock_mode) { | |
a1d26342 | 5660 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5661 | return NULL; |
5662 | } | |
5663 | ||
96178eeb | 5664 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5665 | |
96178eeb | 5666 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5667 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5668 | return downclock_mode; |
5669 | } | |
5670 | ||
ed92f0b2 | 5671 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5672 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5673 | { |
5674 | struct drm_connector *connector = &intel_connector->base; | |
5675 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5676 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5677 | struct drm_device *dev = intel_encoder->base.dev; | |
ed92f0b2 PZ |
5678 | struct drm_i915_private *dev_priv = dev->dev_private; |
5679 | struct drm_display_mode *fixed_mode = NULL; | |
4f9db5b5 | 5680 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5681 | bool has_dpcd; |
5682 | struct drm_display_mode *scan; | |
5683 | struct edid *edid; | |
6517d273 | 5684 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5685 | |
5686 | if (!is_edp(intel_dp)) | |
5687 | return true; | |
5688 | ||
49e6bc51 VS |
5689 | pps_lock(intel_dp); |
5690 | intel_edp_panel_vdd_sanitize(intel_dp); | |
5691 | pps_unlock(intel_dp); | |
63635217 | 5692 | |
ed92f0b2 | 5693 | /* Cache DPCD and EDID for edp. */ |
ed92f0b2 | 5694 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
ed92f0b2 PZ |
5695 | |
5696 | if (has_dpcd) { | |
5697 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
5698 | dev_priv->no_aux_handshake = | |
5699 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
5700 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
5701 | } else { | |
5702 | /* if this fails, presume the device is a ghost */ | |
5703 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
5704 | return false; |
5705 | } | |
5706 | ||
5707 | /* We now know it's not a ghost, init power sequence regs. */ | |
773538e8 | 5708 | pps_lock(intel_dp); |
36b5f425 | 5709 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
773538e8 | 5710 | pps_unlock(intel_dp); |
ed92f0b2 | 5711 | |
060c8778 | 5712 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5713 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5714 | if (edid) { |
5715 | if (drm_add_edid_modes(connector, edid)) { | |
5716 | drm_mode_connector_update_edid_property(connector, | |
5717 | edid); | |
5718 | drm_edid_to_eld(connector, edid); | |
5719 | } else { | |
5720 | kfree(edid); | |
5721 | edid = ERR_PTR(-EINVAL); | |
5722 | } | |
5723 | } else { | |
5724 | edid = ERR_PTR(-ENOENT); | |
5725 | } | |
5726 | intel_connector->edid = edid; | |
5727 | ||
5728 | /* prefer fixed mode from EDID if available */ | |
5729 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5730 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5731 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5732 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5733 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5734 | break; |
5735 | } | |
5736 | } | |
5737 | ||
5738 | /* fallback to VBT if available for eDP */ | |
5739 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5740 | fixed_mode = drm_mode_duplicate(dev, | |
5741 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
5742 | if (fixed_mode) | |
5743 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
5744 | } | |
060c8778 | 5745 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5746 | |
01527b31 CT |
5747 | if (IS_VALLEYVIEW(dev)) { |
5748 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; | |
5749 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5750 | |
5751 | /* | |
5752 | * Figure out the current pipe for the initial backlight setup. | |
5753 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5754 | * fails just assume pipe A. | |
5755 | */ | |
5756 | if (IS_CHERRYVIEW(dev)) | |
5757 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5758 | else | |
5759 | pipe = PORT_TO_PIPE(intel_dp->DP); | |
5760 | ||
5761 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5762 | pipe = intel_dp->pps_pipe; | |
5763 | ||
5764 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5765 | pipe = PIPE_A; | |
5766 | ||
5767 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5768 | pipe_name(pipe)); | |
01527b31 CT |
5769 | } |
5770 | ||
4f9db5b5 | 5771 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
73580fb7 | 5772 | intel_connector->panel.backlight_power = intel_edp_backlight_power; |
6517d273 | 5773 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5774 | |
5775 | return true; | |
5776 | } | |
5777 | ||
16c25533 | 5778 | bool |
f0fec3f2 PZ |
5779 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5780 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5781 | { |
f0fec3f2 PZ |
5782 | struct drm_connector *connector = &intel_connector->base; |
5783 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5784 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5785 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 5786 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 5787 | enum port port = intel_dig_port->port; |
0b99836f | 5788 | int type; |
a4fc5ed6 | 5789 | |
a4a5d2f8 VS |
5790 | intel_dp->pps_pipe = INVALID_PIPE; |
5791 | ||
ec5b01dd | 5792 | /* intel_dp vfuncs */ |
b6b5e383 DL |
5793 | if (INTEL_INFO(dev)->gen >= 9) |
5794 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
5795 | else if (IS_VALLEYVIEW(dev)) | |
ec5b01dd DL |
5796 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5797 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
5798 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
5799 | else if (HAS_PCH_SPLIT(dev)) | |
5800 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
5801 | else | |
5802 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; | |
5803 | ||
b9ca5fad DL |
5804 | if (INTEL_INFO(dev)->gen >= 9) |
5805 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
5806 | else | |
5807 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; | |
153b1100 | 5808 | |
0767935e DV |
5809 | /* Preserve the current hw state. */ |
5810 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5811 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5812 | |
3b32a35b | 5813 | if (intel_dp_is_edp(dev, port)) |
b329530c | 5814 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5815 | else |
5816 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5817 | |
f7d24902 ID |
5818 | /* |
5819 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5820 | * for DP the encoder type can be set by the caller to | |
5821 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5822 | */ | |
5823 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5824 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5825 | ||
c17ed5b5 VS |
5826 | /* eDP only on port B and/or C on vlv/chv */ |
5827 | if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && | |
5828 | port != PORT_B && port != PORT_C)) | |
5829 | return false; | |
5830 | ||
e7281eab ID |
5831 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5832 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5833 | port_name(port)); | |
5834 | ||
b329530c | 5835 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5836 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5837 | ||
a4fc5ed6 KP |
5838 | connector->interlace_allowed = true; |
5839 | connector->doublescan_allowed = 0; | |
5840 | ||
f0fec3f2 | 5841 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5842 | edp_panel_vdd_work); |
a4fc5ed6 | 5843 | |
df0e9248 | 5844 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
34ea3d38 | 5845 | drm_connector_register(connector); |
a4fc5ed6 | 5846 | |
affa9354 | 5847 | if (HAS_DDI(dev)) |
bcbc889b PZ |
5848 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5849 | else | |
5850 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
80f65de3 | 5851 | intel_connector->unregister = intel_dp_connector_unregister; |
bcbc889b | 5852 | |
0b99836f | 5853 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5854 | switch (port) { |
5855 | case PORT_A: | |
1d843f9d | 5856 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5857 | break; |
5858 | case PORT_B: | |
1d843f9d | 5859 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
5860 | break; |
5861 | case PORT_C: | |
1d843f9d | 5862 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5863 | break; |
5864 | case PORT_D: | |
1d843f9d | 5865 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
5866 | break; |
5867 | default: | |
ad1c0b19 | 5868 | BUG(); |
5eb08b69 ZW |
5869 | } |
5870 | ||
dada1a9f | 5871 | if (is_edp(intel_dp)) { |
773538e8 | 5872 | pps_lock(intel_dp); |
1e74a324 VS |
5873 | intel_dp_init_panel_power_timestamps(intel_dp); |
5874 | if (IS_VALLEYVIEW(dev)) | |
a4a5d2f8 | 5875 | vlv_initial_power_sequencer_setup(intel_dp); |
1e74a324 | 5876 | else |
36b5f425 | 5877 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
773538e8 | 5878 | pps_unlock(intel_dp); |
dada1a9f | 5879 | } |
0095e6dc | 5880 | |
9d1a1031 | 5881 | intel_dp_aux_init(intel_dp, intel_connector); |
c1f05264 | 5882 | |
0e32b39c | 5883 | /* init MST on ports that can support it */ |
0c9b3715 JN |
5884 | if (HAS_DP_MST(dev) && |
5885 | (port == PORT_B || port == PORT_C || port == PORT_D)) | |
5886 | intel_dp_mst_encoder_init(intel_dig_port, | |
5887 | intel_connector->base.base.id); | |
0e32b39c | 5888 | |
36b5f425 | 5889 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
4f71d0cb | 5890 | drm_dp_aux_unregister(&intel_dp->aux); |
15b1d171 PZ |
5891 | if (is_edp(intel_dp)) { |
5892 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
5893 | /* |
5894 | * vdd might still be enabled do to the delayed vdd off. | |
5895 | * Make sure vdd is actually turned off here. | |
5896 | */ | |
773538e8 | 5897 | pps_lock(intel_dp); |
4be73780 | 5898 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 5899 | pps_unlock(intel_dp); |
15b1d171 | 5900 | } |
34ea3d38 | 5901 | drm_connector_unregister(connector); |
b2f246a8 | 5902 | drm_connector_cleanup(connector); |
16c25533 | 5903 | return false; |
b2f246a8 | 5904 | } |
32f9d658 | 5905 | |
f684960e CW |
5906 | intel_dp_add_properties(intel_dp, connector); |
5907 | ||
a4fc5ed6 KP |
5908 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5909 | * 0xd. Failure to do so will result in spurious interrupts being | |
5910 | * generated on the port when a cable is not attached. | |
5911 | */ | |
5912 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
5913 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
5914 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5915 | } | |
16c25533 | 5916 | |
aa7471d2 JN |
5917 | i915_debugfs_connector_add(connector); |
5918 | ||
16c25533 | 5919 | return true; |
a4fc5ed6 | 5920 | } |
f0fec3f2 PZ |
5921 | |
5922 | void | |
5923 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
5924 | { | |
13cf5504 | 5925 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0fec3f2 PZ |
5926 | struct intel_digital_port *intel_dig_port; |
5927 | struct intel_encoder *intel_encoder; | |
5928 | struct drm_encoder *encoder; | |
5929 | struct intel_connector *intel_connector; | |
5930 | ||
b14c5679 | 5931 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
5932 | if (!intel_dig_port) |
5933 | return; | |
5934 | ||
08d9bc92 | 5935 | intel_connector = intel_connector_alloc(); |
f0fec3f2 PZ |
5936 | if (!intel_connector) { |
5937 | kfree(intel_dig_port); | |
5938 | return; | |
5939 | } | |
5940 | ||
5941 | intel_encoder = &intel_dig_port->base; | |
5942 | encoder = &intel_encoder->base; | |
5943 | ||
5944 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
5945 | DRM_MODE_ENCODER_TMDS); | |
5946 | ||
5bfe2ac0 | 5947 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5948 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5949 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5950 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5951 | intel_encoder->suspend = intel_dp_encoder_suspend; |
e4a1d846 | 5952 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 5953 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5954 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5955 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5956 | intel_encoder->post_disable = chv_post_disable_dp; |
e4a1d846 | 5957 | } else if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 5958 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5959 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5960 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5961 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5962 | } else { |
ecff4f3b JN |
5963 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5964 | intel_encoder->enable = g4x_enable_dp; | |
08aff3fe VS |
5965 | if (INTEL_INFO(dev)->gen >= 5) |
5966 | intel_encoder->post_disable = ilk_post_disable_dp; | |
ab1f90f9 | 5967 | } |
f0fec3f2 | 5968 | |
174edf1f | 5969 | intel_dig_port->port = port; |
f0fec3f2 PZ |
5970 | intel_dig_port->dp.output_reg = output_reg; |
5971 | ||
00c09d70 | 5972 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
882ec384 VS |
5973 | if (IS_CHERRYVIEW(dev)) { |
5974 | if (port == PORT_D) | |
5975 | intel_encoder->crtc_mask = 1 << 2; | |
5976 | else | |
5977 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5978 | } else { | |
5979 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5980 | } | |
bc079e8b | 5981 | intel_encoder->cloneable = 0; |
f0fec3f2 | 5982 | |
13cf5504 | 5983 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 5984 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 5985 | |
15b1d171 PZ |
5986 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
5987 | drm_encoder_cleanup(encoder); | |
5988 | kfree(intel_dig_port); | |
b2f246a8 | 5989 | kfree(intel_connector); |
15b1d171 | 5990 | } |
f0fec3f2 | 5991 | } |
0e32b39c DA |
5992 | |
5993 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5994 | { | |
5995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5996 | int i; | |
5997 | ||
5998 | /* disable MST */ | |
5999 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6000 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
0e32b39c DA |
6001 | if (!intel_dig_port) |
6002 | continue; | |
6003 | ||
6004 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
6005 | if (!intel_dig_port->dp.can_mst) | |
6006 | continue; | |
6007 | if (intel_dig_port->dp.is_mst) | |
6008 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
6009 | } | |
6010 | } | |
6011 | } | |
6012 | ||
6013 | void intel_dp_mst_resume(struct drm_device *dev) | |
6014 | { | |
6015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6016 | int i; | |
6017 | ||
6018 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6019 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
0e32b39c DA |
6020 | if (!intel_dig_port) |
6021 | continue; | |
6022 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
6023 | int ret; | |
6024 | ||
6025 | if (!intel_dig_port->dp.can_mst) | |
6026 | continue; | |
6027 | ||
6028 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); | |
6029 | if (ret != 0) { | |
6030 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
6031 | } | |
6032 | } | |
6033 | } | |
6034 | } |