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drm/i915: Create helper functions to determine eDP power state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
ea5b213a
CW		 45struct intel_dp {
46 struct intel_encoder base;
a4fc5ed6
KP		 47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 50 bool has_audio;
f684960e 51 int force_audio;
e953fd7b 52 uint32_t color_range;
d2b996ac 53 int dpms_mode;
a4fc5ed6
KP		 54 uint8_t link_bw;
55 uint8_t lane_count;
9de88e6e 56 uint8_t dpcd[8];
a4fc5ed6
KP		 57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
f0917379 59 bool is_pch_edp;
33a34e4e
JB		 60 uint8_t train_set[4];
61 uint8_t link_status[DP_LINK_STATUS_SIZE];
f01eca2e
KP		 62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
d15456de 67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
a4fc5ed6
KP		 68};
69
cfcb0fc9
JB		 70/**
71 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
72 * @intel_dp: DP struct
73 *
74 * If a CPU or PCH DP output is attached to an eDP panel, this function
75 * will return true, and false otherwise.
76 */
77static bool is_edp(struct intel_dp *intel_dp)
78{
79 return intel_dp->base.type == INTEL_OUTPUT_EDP;
80}
81
82/**
83 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
84 * @intel_dp: DP struct
85 *
86 * Returns true if the given DP struct corresponds to a PCH DP port attached
87 * to an eDP panel, false otherwise. Helpful for determining whether we
88 * may need FDI resources for a given DP output or not.
89 */
90static bool is_pch_edp(struct intel_dp *intel_dp)
91{
92 return intel_dp->is_pch_edp;
93}
94
ea5b213a
CW		 95static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
96{
4ef69c7a 97 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 98}
a4fc5ed6 99
df0e9248
CW		 100static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
101{
102 return container_of(intel_attached_encoder(connector),
103 struct intel_dp, base);
104}
105
814948ad
JB		 106/**
107 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
108 * @encoder: DRM encoder
109 *
110 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
111 * by intel_display.c.
112 */
113bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
114{
115 struct intel_dp *intel_dp;
116
117 if (!encoder)
118 return false;
119
120 intel_dp = enc_to_intel_dp(encoder);
121
122 return is_pch_edp(intel_dp);
123}
124
33a34e4e
JB		 125static void intel_dp_start_link_train(struct intel_dp *intel_dp);
126static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 127static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 128
32f9d658 129void
21d40d37 130intel_edp_link_config (struct intel_encoder *intel_encoder,
ea5b213a 131 int *lane_num, int *link_bw)
32f9d658 132{
ea5b213a 133 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 134
ea5b213a
CW		 135 *lane_num = intel_dp->lane_count;
136 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 137 *link_bw = 162000;
ea5b213a 138 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 139 *link_bw = 270000;
140}
141
a4fc5ed6 142static int
ea5b213a 143intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 144{
a4fc5ed6
KP		 145 int max_lane_count = 4;
146
7183dc29
JB		 147 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
148 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
a4fc5ed6
KP		 149 switch (max_lane_count) {
150 case 1: case 2: case 4:
151 break;
152 default:
153 max_lane_count = 4;
154 }
155 }
156 return max_lane_count;
157}
158
159static int
ea5b213a 160intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 161{
7183dc29 162 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 163
164 switch (max_link_bw) {
165 case DP_LINK_BW_1_62:
166 case DP_LINK_BW_2_7:
167 break;
168 default:
169 max_link_bw = DP_LINK_BW_1_62;
170 break;
171 }
172 return max_link_bw;
173}
174
175static int
176intel_dp_link_clock(uint8_t link_bw)
177{
178 if (link_bw == DP_LINK_BW_2_7)
179 return 270000;
180 else
181 return 162000;
182}
183
184/* I think this is a fiction */
185static int
ea5b213a 186intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
a4fc5ed6 187{
89c61432
JB		 188 struct drm_crtc *crtc = intel_dp->base.base.crtc;
189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
190 int bpp = 24;
885a5fb5 191
89c61432
JB		 192 if (intel_crtc)
193 bpp = intel_crtc->bpp;
194
195 return (pixel_clock * bpp + 7) / 8;
a4fc5ed6
KP		 196}
197
fe27d53e
DA		 198static int
199intel_dp_max_data_rate(int max_link_clock, int max_lanes)
200{
201 return (max_link_clock * max_lanes * 8) / 10;
202}
203
a4fc5ed6
KP		 204static int
205intel_dp_mode_valid(struct drm_connector *connector,
206 struct drm_display_mode *mode)
207{
df0e9248 208 struct intel_dp *intel_dp = intel_attached_dp(connector);
ea5b213a
CW		 209 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
210 int max_lanes = intel_dp_max_lane_count(intel_dp);
a4fc5ed6 211
d15456de
KP		 212 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
213 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 214 return MODE_PANEL;
215
d15456de 216 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 217 return MODE_PANEL;
218 }
219
25985edc 220 /* only refuse the mode on non eDP since we have seen some weird eDP panels
fe27d53e 221 which are outside spec tolerances but somehow work by magic */
cfcb0fc9 222 if (!is_edp(intel_dp) &&
ea5b213a 223 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
fe27d53e 224 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
a4fc5ed6
KP		 225 return MODE_CLOCK_HIGH;
226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
230 return MODE_OK;
231}
232
233static uint32_t
234pack_aux(uint8_t *src, int src_bytes)
235{
236 int i;
237 uint32_t v = 0;
238
239 if (src_bytes > 4)
240 src_bytes = 4;
241 for (i = 0; i < src_bytes; i++)
242 v |= ((uint32_t) src[i]) << ((3-i) * 8);
243 return v;
244}
245
246static void
247unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
248{
249 int i;
250 if (dst_bytes > 4)
251 dst_bytes = 4;
252 for (i = 0; i < dst_bytes; i++)
253 dst[i] = src >> ((3-i) * 8);
254}
255
fb0f8fbf
KP		 256/* hrawclock is 1/4 the FSB frequency */
257static int
258intel_hrawclk(struct drm_device *dev)
259{
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 uint32_t clkcfg;
262
263 clkcfg = I915_READ(CLKCFG);
264 switch (clkcfg & CLKCFG_FSB_MASK) {
265 case CLKCFG_FSB_400:
266 return 100;
267 case CLKCFG_FSB_533:
268 return 133;
269 case CLKCFG_FSB_667:
270 return 166;
271 case CLKCFG_FSB_800:
272 return 200;
273 case CLKCFG_FSB_1067:
274 return 266;
275 case CLKCFG_FSB_1333:
276 return 333;
277 /* these two are just a guess; one of them might be right */
278 case CLKCFG_FSB_1600:
279 case CLKCFG_FSB_1600_ALT:
280 return 400;
281 default:
282 return 133;
283 }
284}
285
ebf33b18
KP		 286static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
287{
288 struct drm_device *dev = intel_dp->base.base.dev;
289 struct drm_i915_private *dev_priv = dev->dev_private;
290
291 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
292}
293
294static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298
299 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
300}
301
9b984dae
KP		 302static void
303intel_dp_check_edp(struct intel_dp *intel_dp)
304{
305 struct drm_device *dev = intel_dp->base.base.dev;
306 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 307
9b984dae
KP		 308 if (!is_edp(intel_dp))
309 return;
ebf33b18 310 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 311 WARN(1, "eDP powered off while attempting aux channel communication.\n");
312 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 313 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 314 I915_READ(PCH_PP_CONTROL));
315 }
316}
317
a4fc5ed6 318static int
ea5b213a 319intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
322{
ea5b213a 323 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 324 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = output_reg + 0x10;
327 uint32_t ch_data = ch_ctl + 4;
328 int i;
329 int recv_bytes;
a4fc5ed6 330 uint32_t status;
fb0f8fbf 331 uint32_t aux_clock_divider;
e3421a18 332 int try, precharge;
a4fc5ed6 333
9b984dae 334 intel_dp_check_edp(intel_dp);
a4fc5ed6 335 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 336 * and would like to run at 2MHz. So, take the
337 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 338 *
339 * Note that PCH attached eDP panels should use a 125MHz input
340 * clock divider.
a4fc5ed6 341 */
cfcb0fc9 342 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
e3421a18
ZW		 343 if (IS_GEN6(dev))
344 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
345 else
346 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
347 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 348 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 349 else
350 aux_clock_divider = intel_hrawclk(dev) / 2;
351
e3421a18
ZW		 352 if (IS_GEN6(dev))
353 precharge = 3;
354 else
355 precharge = 5;
356
11bee43e
JB		 357 /* Try to wait for any previous AUX channel activity */
358 for (try = 0; try < 3; try++) {
359 status = I915_READ(ch_ctl);
360 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
361 break;
362 msleep(1);
363 }
364
365 if (try == 3) {
366 WARN(1, "dp_aux_ch not started status 0x%08x\n",
367 I915_READ(ch_ctl));
4f7f7b7e
CW		 368 return -EBUSY;
369 }
370
fb0f8fbf
KP		 371 /* Must try at least 3 times according to DP spec */
372 for (try = 0; try < 5; try++) {
373 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 374 for (i = 0; i < send_bytes; i += 4)
375 I915_WRITE(ch_data + i,
376 pack_aux(send + i, send_bytes - i));
fb0f8fbf
KP		 377
378 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 379 I915_WRITE(ch_ctl,
380 DP_AUX_CH_CTL_SEND_BUSY |
381 DP_AUX_CH_CTL_TIME_OUT_400us |
382 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
383 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
384 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
385 DP_AUX_CH_CTL_DONE |
386 DP_AUX_CH_CTL_TIME_OUT_ERROR |
387 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 388 for (;;) {
fb0f8fbf
KP		 389 status = I915_READ(ch_ctl);
390 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
391 break;
4f7f7b7e 392 udelay(100);
fb0f8fbf
KP		 393 }
394
395 /* Clear done status and any errors */
4f7f7b7e
CW		 396 I915_WRITE(ch_ctl,
397 status |
398 DP_AUX_CH_CTL_DONE |
399 DP_AUX_CH_CTL_TIME_OUT_ERROR |
400 DP_AUX_CH_CTL_RECEIVE_ERROR);
401 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 402 break;
403 }
404
a4fc5ed6 405 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 406 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 407 return -EBUSY;
a4fc5ed6
KP		 408 }
409
410 /* Check for timeout or receive error.
411 * Timeouts occur when the sink is not connected
412 */
a5b3da54 413 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 414 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 415 return -EIO;
416 }
1ae8c0a5
KP		 417
418 /* Timeouts occur when the device isn't connected, so they're
419 * "normal" -- don't fill the kernel log with these */
a5b3da54 420 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 421 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 422 return -ETIMEDOUT;
a4fc5ed6
KP		 423 }
424
425 /* Unload any bytes sent back from the other side */
426 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
427 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 428 if (recv_bytes > recv_size)
429 recv_bytes = recv_size;
430
4f7f7b7e
CW		 431 for (i = 0; i < recv_bytes; i += 4)
432 unpack_aux(I915_READ(ch_data + i),
433 recv + i, recv_bytes - i);
a4fc5ed6
KP		 434
435 return recv_bytes;
436}
437
438/* Write data to the aux channel in native mode */
439static int
ea5b213a 440intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 441 uint16_t address, uint8_t *send, int send_bytes)
442{
443 int ret;
444 uint8_t msg[20];
445 int msg_bytes;
446 uint8_t ack;
447
9b984dae 448 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 449 if (send_bytes > 16)
450 return -1;
451 msg[0] = AUX_NATIVE_WRITE << 4;
452 msg[1] = address >> 8;
eebc863e 453 msg[2] = address & 0xff;
a4fc5ed6
KP		 454 msg[3] = send_bytes - 1;
455 memcpy(&msg[4], send, send_bytes);
456 msg_bytes = send_bytes + 4;
457 for (;;) {
ea5b213a 458 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 459 if (ret < 0)
460 return ret;
461 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
462 break;
463 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
464 udelay(100);
465 else
a5b3da54 466 return -EIO;
a4fc5ed6
KP		 467 }
468 return send_bytes;
469}
470
471/* Write a single byte to the aux channel in native mode */
472static int
ea5b213a 473intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 474 uint16_t address, uint8_t byte)
475{
ea5b213a 476 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 477}
478
479/* read bytes from a native aux channel */
480static int
ea5b213a 481intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 482 uint16_t address, uint8_t *recv, int recv_bytes)
483{
484 uint8_t msg[4];
485 int msg_bytes;
486 uint8_t reply[20];
487 int reply_bytes;
488 uint8_t ack;
489 int ret;
490
9b984dae 491 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 492 msg[0] = AUX_NATIVE_READ << 4;
493 msg[1] = address >> 8;
494 msg[2] = address & 0xff;
495 msg[3] = recv_bytes - 1;
496
497 msg_bytes = 4;
498 reply_bytes = recv_bytes + 1;
499
500 for (;;) {
ea5b213a 501 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 502 reply, reply_bytes);
a5b3da54
KP		 503 if (ret == 0)
504 return -EPROTO;
505 if (ret < 0)
a4fc5ed6
KP		 506 return ret;
507 ack = reply[0];
508 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
509 memcpy(recv, reply + 1, ret - 1);
510 return ret - 1;
511 }
512 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
513 udelay(100);
514 else
a5b3da54 515 return -EIO;
a4fc5ed6
KP		 516 }
517}
518
519static int
ab2c0672
DA		 520intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
521 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 522{
ab2c0672 523 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 524 struct intel_dp *intel_dp = container_of(adapter,
525 struct intel_dp,
526 adapter);
ab2c0672
DA		 527 uint16_t address = algo_data->address;
528 uint8_t msg[5];
529 uint8_t reply[2];
8316f337 530 unsigned retry;
ab2c0672
DA		 531 int msg_bytes;
532 int reply_bytes;
533 int ret;
534
9b984dae 535 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 536 /* Set up the command byte */
537 if (mode & MODE_I2C_READ)
538 msg[0] = AUX_I2C_READ << 4;
539 else
540 msg[0] = AUX_I2C_WRITE << 4;
541
542 if (!(mode & MODE_I2C_STOP))
543 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 544
ab2c0672
DA		 545 msg[1] = address >> 8;
546 msg[2] = address;
547
548 switch (mode) {
549 case MODE_I2C_WRITE:
550 msg[3] = 0;
551 msg[4] = write_byte;
552 msg_bytes = 5;
553 reply_bytes = 1;
554 break;
555 case MODE_I2C_READ:
556 msg[3] = 0;
557 msg_bytes = 4;
558 reply_bytes = 2;
559 break;
560 default:
561 msg_bytes = 3;
562 reply_bytes = 1;
563 break;
564 }
565
8316f337
DF		 566 for (retry = 0; retry < 5; retry++) {
567 ret = intel_dp_aux_ch(intel_dp,
568 msg, msg_bytes,
569 reply, reply_bytes);
ab2c0672 570 if (ret < 0) {
3ff99164 571 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 572 return ret;
573 }
8316f337
DF		 574
575 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
576 case AUX_NATIVE_REPLY_ACK:
577 /* I2C-over-AUX Reply field is only valid
578 * when paired with AUX ACK.
579 */
580 break;
581 case AUX_NATIVE_REPLY_NACK:
582 DRM_DEBUG_KMS("aux_ch native nack\n");
583 return -EREMOTEIO;
584 case AUX_NATIVE_REPLY_DEFER:
585 udelay(100);
586 continue;
587 default:
588 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
589 reply[0]);
590 return -EREMOTEIO;
591 }
592
ab2c0672
DA		 593 switch (reply[0] & AUX_I2C_REPLY_MASK) {
594 case AUX_I2C_REPLY_ACK:
595 if (mode == MODE_I2C_READ) {
596 *read_byte = reply[1];
597 }
598 return reply_bytes - 1;
599 case AUX_I2C_REPLY_NACK:
8316f337 600 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 601 return -EREMOTEIO;
602 case AUX_I2C_REPLY_DEFER:
8316f337 603 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 604 udelay(100);
605 break;
606 default:
8316f337 607 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 608 return -EREMOTEIO;
609 }
610 }
8316f337
DF		 611
612 DRM_ERROR("too many retries, giving up\n");
613 return -EREMOTEIO;
a4fc5ed6
KP		 614}
615
0b5c541b
KP		 616static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
617static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp);
618
a4fc5ed6 619static int
ea5b213a 620intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 621 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 622{
0b5c541b
KP		 623 int ret;
624
d54e9d28 625 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 626 intel_dp->algo.running = false;
627 intel_dp->algo.address = 0;
628 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
629
630 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
631 intel_dp->adapter.owner = THIS_MODULE;
632 intel_dp->adapter.class = I2C_CLASS_DDC;
633 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
634 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
635 intel_dp->adapter.algo_data = &intel_dp->algo;
636 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
637
0b5c541b
KP		 638 ironlake_edp_panel_vdd_on(intel_dp);
639 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
640 ironlake_edp_panel_vdd_off(intel_dp);
641 return ret;
a4fc5ed6
KP		 642}
643
644static bool
645intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
646 struct drm_display_mode *adjusted_mode)
647{
0d3a1bee 648 struct drm_device *dev = encoder->dev;
ea5b213a 649 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 650 int lane_count, clock;
ea5b213a
CW		 651 int max_lane_count = intel_dp_max_lane_count(intel_dp);
652 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 653 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
654
d15456de
KP		 655 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
656 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 657 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
658 mode, adjusted_mode);
0d3a1bee
ZY		 659 /*
660 * the mode->clock is used to calculate the Data&Link M/N
661 * of the pipe. For the eDP the fixed clock should be used.
662 */
d15456de 663 mode->clock = intel_dp->panel_fixed_mode->clock;
0d3a1bee
ZY		 664 }
665
a4fc5ed6
KP		 666 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
667 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 668 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 669
ea5b213a 670 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
885a5fb5 671 <= link_avail) {
ea5b213a
CW		 672 intel_dp->link_bw = bws[clock];
673 intel_dp->lane_count = lane_count;
674 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
28c97730
ZY		 675 DRM_DEBUG_KMS("Display port link bw %02x lane "
676 "count %d clock %d\n",
ea5b213a 677 intel_dp->link_bw, intel_dp->lane_count,
a4fc5ed6
KP		 678 adjusted_mode->clock);
679 return true;
680 }
681 }
682 }
fe27d53e 683
3cf2efb1
CW		 684 if (is_edp(intel_dp)) {
685 /* okay we failed just pick the highest */
686 intel_dp->lane_count = max_lane_count;
687 intel_dp->link_bw = bws[max_clock];
688 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
689 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
690 "count %d clock %d\n",
691 intel_dp->link_bw, intel_dp->lane_count,
692 adjusted_mode->clock);
693
694 return true;
695 }
696
a4fc5ed6
KP		 697 return false;
698}
699
700struct intel_dp_m_n {
701 uint32_t tu;
702 uint32_t gmch_m;
703 uint32_t gmch_n;
704 uint32_t link_m;
705 uint32_t link_n;
706};
707
708static void
709intel_reduce_ratio(uint32_t *num, uint32_t *den)
710{
711 while (*num > 0xffffff || *den > 0xffffff) {
712 *num >>= 1;
713 *den >>= 1;
714 }
715}
716
717static void
36e83a18 718intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 719 int nlanes,
720 int pixel_clock,
721 int link_clock,
722 struct intel_dp_m_n *m_n)
723{
724 m_n->tu = 64;
36e83a18 725 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 726 m_n->gmch_n = link_clock * nlanes;
727 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
728 m_n->link_m = pixel_clock;
729 m_n->link_n = link_clock;
730 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
731}
732
733void
734intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
735 struct drm_display_mode *adjusted_mode)
736{
737 struct drm_device *dev = crtc->dev;
738 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 739 struct drm_encoder *encoder;
a4fc5ed6
KP		 740 struct drm_i915_private *dev_priv = dev->dev_private;
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 742 int lane_count = 4;
a4fc5ed6 743 struct intel_dp_m_n m_n;
9db4a9c7 744 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 745
746 /*
21d40d37 747 * Find the lane count in the intel_encoder private
a4fc5ed6 748 */
55f78c43 749 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 750 struct intel_dp *intel_dp;
a4fc5ed6 751
d8201ab6 752 if (encoder->crtc != crtc)
a4fc5ed6
KP		 753 continue;
754
ea5b213a
CW		 755 intel_dp = enc_to_intel_dp(encoder);
756 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
757 lane_count = intel_dp->lane_count;
51190667
JB		 758 break;
759 } else if (is_edp(intel_dp)) {
760 lane_count = dev_priv->edp.lanes;
a4fc5ed6
KP		 761 break;
762 }
763 }
764
765 /*
766 * Compute the GMCH and Link ratios. The '3' here is
767 * the number of bytes_per_pixel post-LUT, which we always
768 * set up for 8-bits of R/G/B, or 3 bytes total.
769 */
858fa035 770 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 771 mode->clock, adjusted_mode->clock, &m_n);
772
c619eed4 773 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 774 I915_WRITE(TRANSDATA_M1(pipe),
775 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
776 m_n.gmch_m);
777 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
778 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
779 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 780 } else {
9db4a9c7
JB		 781 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
782 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
783 m_n.gmch_m);
784 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
785 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
786 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 787 }
788}
789
f01eca2e
KP		 790static void ironlake_edp_pll_on(struct drm_encoder *encoder);
791static void ironlake_edp_pll_off(struct drm_encoder *encoder);
792
a4fc5ed6
KP		 793static void
794intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
795 struct drm_display_mode *adjusted_mode)
796{
e3421a18 797 struct drm_device *dev = encoder->dev;
ea5b213a 798 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 799 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
801
f01eca2e
KP		 802 /* Turn on the eDP PLL if needed */
803 if (is_edp(intel_dp)) {
804 if (!is_pch_edp(intel_dp))
805 ironlake_edp_pll_on(encoder);
806 else
807 ironlake_edp_pll_off(encoder);
808 }
809
e953fd7b
CW		 810 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
811 intel_dp->DP |= intel_dp->color_range;
9c9e7927
AJ		 812
813 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
ea5b213a 814 intel_dp->DP |= DP_SYNC_HS_HIGH;
9c9e7927 815 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
ea5b213a 816 intel_dp->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 817
cfcb0fc9 818 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
ea5b213a 819 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3421a18 820 else
ea5b213a 821 intel_dp->DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6 822
ea5b213a 823 switch (intel_dp->lane_count) {
a4fc5ed6 824 case 1:
ea5b213a 825 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 826 break;
827 case 2:
ea5b213a 828 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 829 break;
830 case 4:
ea5b213a 831 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 832 break;
833 }
ea5b213a
CW		 834 if (intel_dp->has_audio)
835 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
a4fc5ed6 836
ea5b213a
CW		 837 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
838 intel_dp->link_configuration[0] = intel_dp->link_bw;
839 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 840 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6
KP		 841
842 /*
9962c925 843 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 844 */
7183dc29
JB		 845 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
846 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a
CW		 847 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
848 intel_dp->DP |= DP_ENHANCED_FRAMING;
a4fc5ed6
KP		 849 }
850
e3421a18
ZW		 851 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
852 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
ea5b213a 853 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 854
895692be 855 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
32f9d658 856 /* don't miss out required setting for eDP */
ea5b213a 857 intel_dp->DP |= DP_PLL_ENABLE;
32f9d658 858 if (adjusted_mode->clock < 200000)
ea5b213a 859 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
32f9d658 860 else
ea5b213a 861 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
32f9d658 862 }
a4fc5ed6
KP		 863}
864
5d613501
JB		 865static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
866{
867 struct drm_device *dev = intel_dp->base.base.dev;
868 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 869 u32 pp;
5d613501 870
97af61f5
KP		 871 if (!is_edp(intel_dp))
872 return;
f01eca2e 873 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501
JB		 874
875 pp = I915_READ(PCH_PP_CONTROL);
1c0ae80a
KP		 876 pp &= ~PANEL_UNLOCK_MASK;
877 pp |= PANEL_UNLOCK_REGS;
5d613501
JB		 878 pp |= EDP_FORCE_VDD;
879 I915_WRITE(PCH_PP_CONTROL, pp);
880 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 881 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
882 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 883
884 /*
885 * If the panel wasn't on, delay before accessing aux channel
886 */
887 if (!ironlake_edp_have_panel_power(intel_dp)) {
f01eca2e
KP		 888 msleep(intel_dp->panel_power_up_delay);
889 DRM_DEBUG_KMS("eDP VDD was not on\n");
890 }
5d613501
JB		 891}
892
893static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
894{
895 struct drm_device *dev = intel_dp->base.base.dev;
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 u32 pp;
898
97af61f5
KP		 899 if (!is_edp(intel_dp))
900 return;
f01eca2e 901 DRM_DEBUG_KMS("Turn eDP VDD off\n");
5d613501 902 pp = I915_READ(PCH_PP_CONTROL);
1c0ae80a
KP		 903 pp &= ~PANEL_UNLOCK_MASK;
904 pp |= PANEL_UNLOCK_REGS;
5d613501
JB		 905 pp &= ~EDP_FORCE_VDD;
906 I915_WRITE(PCH_PP_CONTROL, pp);
907 POSTING_READ(PCH_PP_CONTROL);
908
909 /* Make sure sequencer is idle before allowing subsequent activity */
f01eca2e
KP		 910 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
911 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
912 msleep(intel_dp->panel_power_cycle_delay);
5d613501
JB		 913}
914
7eaf5547 915/* Returns true if the panel was already on when called */
7d639f35 916static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
9934c132 917{
01cb9ea6 918 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 919 struct drm_i915_private *dev_priv = dev->dev_private;
01cb9ea6 920 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
9934c132 921
97af61f5 922 if (!is_edp(intel_dp))
f01eca2e 923 return true;
ebf33b18 924 if (ironlake_edp_have_panel_power(intel_dp))
7d639f35 925 return;
9934c132
JB		 926
927 pp = I915_READ(PCH_PP_CONTROL);
1c0ae80a
KP		 928 pp &= ~PANEL_UNLOCK_MASK;
929 pp |= PANEL_UNLOCK_REGS;
37c6c9b0
JB		 930
931 /* ILK workaround: disable reset around power sequence */
932 pp &= ~PANEL_POWER_RESET;
933 I915_WRITE(PCH_PP_CONTROL, pp);
934 POSTING_READ(PCH_PP_CONTROL);
935
1c0ae80a 936 pp |= POWER_TARGET_ON;
9934c132 937 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 938 POSTING_READ(PCH_PP_CONTROL);
9934c132 939
01cb9ea6
JB		 940 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
941 5000))
913d8d11
CW		 942 DRM_ERROR("panel on wait timed out: 0x%08x\n",
943 I915_READ(PCH_PP_STATUS));
9934c132 944
37c6c9b0 945 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
9934c132 946 I915_WRITE(PCH_PP_CONTROL, pp);
37c6c9b0 947 POSTING_READ(PCH_PP_CONTROL);
9934c132
JB		 948}
949
f01eca2e 950static void ironlake_edp_panel_off(struct drm_encoder *encoder)
9934c132 951{
f01eca2e
KP		 952 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
953 struct drm_device *dev = encoder->dev;
9934c132 954 struct drm_i915_private *dev_priv = dev->dev_private;
01cb9ea6
JB		 955 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
956 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
9934c132 957
97af61f5
KP		 958 if (!is_edp(intel_dp))
959 return;
9934c132 960 pp = I915_READ(PCH_PP_CONTROL);
1c0ae80a
KP		 961 pp &= ~PANEL_UNLOCK_MASK;
962 pp |= PANEL_UNLOCK_REGS;
37c6c9b0
JB		 963
964 /* ILK workaround: disable reset around power sequence */
965 pp &= ~PANEL_POWER_RESET;
966 I915_WRITE(PCH_PP_CONTROL, pp);
967 POSTING_READ(PCH_PP_CONTROL);
968
9934c132
JB		 969 pp &= ~POWER_TARGET_ON;
970 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 971 POSTING_READ(PCH_PP_CONTROL);
f01eca2e 972 msleep(intel_dp->panel_power_cycle_delay);
9934c132 973
01cb9ea6 974 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
913d8d11
CW		 975 DRM_ERROR("panel off wait timed out: 0x%08x\n",
976 I915_READ(PCH_PP_STATUS));
9934c132 977
3969c9c9 978 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
9934c132 979 I915_WRITE(PCH_PP_CONTROL, pp);
37c6c9b0 980 POSTING_READ(PCH_PP_CONTROL);
9934c132
JB		 981}
982
f01eca2e 983static void ironlake_edp_backlight_on (struct intel_dp *intel_dp)
32f9d658 984{
f01eca2e 985 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 986 struct drm_i915_private *dev_priv = dev->dev_private;
987 u32 pp;
988
f01eca2e
KP		 989 if (!is_edp(intel_dp))
990 return;
991
28c97730 992 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 993 /*
994 * If we enable the backlight right away following a panel power
995 * on, we may see slight flicker as the panel syncs with the eDP
996 * link. So delay a bit to make sure the image is solid before
997 * allowing it to appear.
998 */
f01eca2e 999 msleep(intel_dp->backlight_on_delay);
32f9d658 1000 pp = I915_READ(PCH_PP_CONTROL);
1c0ae80a
KP		 1001 pp &= ~PANEL_UNLOCK_MASK;
1002 pp |= PANEL_UNLOCK_REGS;
32f9d658
ZW		 1003 pp |= EDP_BLC_ENABLE;
1004 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1005 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1006}
1007
f01eca2e 1008static void ironlake_edp_backlight_off (struct intel_dp *intel_dp)
32f9d658 1009{
f01eca2e 1010 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012 u32 pp;
1013
f01eca2e
KP		 1014 if (!is_edp(intel_dp))
1015 return;
1016
28c97730 1017 DRM_DEBUG_KMS("\n");
32f9d658 1018 pp = I915_READ(PCH_PP_CONTROL);
1c0ae80a
KP		 1019 pp &= ~PANEL_UNLOCK_MASK;
1020 pp |= PANEL_UNLOCK_REGS;
32f9d658
ZW		 1021 pp &= ~EDP_BLC_ENABLE;
1022 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1023 POSTING_READ(PCH_PP_CONTROL);
1024 msleep(intel_dp->backlight_off_delay);
32f9d658 1025}
a4fc5ed6 1026
d240f20f
JB		 1027static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1028{
1029 struct drm_device *dev = encoder->dev;
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 u32 dpa_ctl;
1032
1033 DRM_DEBUG_KMS("\n");
1034 dpa_ctl = I915_READ(DP_A);
298b0b39 1035 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1036 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1037 POSTING_READ(DP_A);
1038 udelay(200);
d240f20f
JB		 1039}
1040
1041static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1042{
1043 struct drm_device *dev = encoder->dev;
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 u32 dpa_ctl;
1046
1047 dpa_ctl = I915_READ(DP_A);
298b0b39 1048 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1049 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1050 POSTING_READ(DP_A);
d240f20f
JB		 1051 udelay(200);
1052}
1053
c7ad3810
JB		 1054/* If the sink supports it, try to set the power state appropriately */
1055static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1056{
1057 int ret, i;
1058
1059 /* Should have a valid DPCD by this point */
1060 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1061 return;
1062
1063 if (mode != DRM_MODE_DPMS_ON) {
1064 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1065 DP_SET_POWER_D3);
1066 if (ret != 1)
1067 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1068 } else {
1069 /*
1070 * When turning on, we need to retry for 1ms to give the sink
1071 * time to wake up.
1072 */
1073 for (i = 0; i < 3; i++) {
1074 ret = intel_dp_aux_native_write_1(intel_dp,
1075 DP_SET_POWER,
1076 DP_SET_POWER_D0);
1077 if (ret == 1)
1078 break;
1079 msleep(1);
1080 }
1081 }
1082}
1083
d240f20f
JB		 1084static void intel_dp_prepare(struct drm_encoder *encoder)
1085{
1086 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d240f20f 1087
c7ad3810 1088 /* Wake up the sink first */
f58ff854 1089 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1090 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
f58ff854 1091 ironlake_edp_panel_vdd_off(intel_dp);
c7ad3810 1092
f01eca2e
KP		 1093 /* Make sure the panel is off before trying to
1094 * change the mode
1095 */
1096 ironlake_edp_backlight_off(intel_dp);
736085bc 1097 intel_dp_link_down(intel_dp);
f01eca2e 1098 ironlake_edp_panel_off(encoder);
d240f20f
JB		 1099}
1100
1101static void intel_dp_commit(struct drm_encoder *encoder)
1102{
1103 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d240f20f 1104
97af61f5 1105 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1106 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1107 intel_dp_start_link_train(intel_dp);
97af61f5
KP		 1108 ironlake_edp_panel_on(intel_dp);
1109 ironlake_edp_panel_vdd_off(intel_dp);
33a34e4e 1110 intel_dp_complete_link_train(intel_dp);
f01eca2e 1111 ironlake_edp_backlight_on(intel_dp);
d2b996ac
KP		 1112
1113 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
d240f20f
JB		 1114}
1115
a4fc5ed6
KP		 1116static void
1117intel_dp_dpms(struct drm_encoder *encoder, int mode)
1118{
ea5b213a 1119 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 1120 struct drm_device *dev = encoder->dev;
a4fc5ed6 1121 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1122 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1123
1124 if (mode != DRM_MODE_DPMS_ON) {
245e2708 1125 ironlake_edp_panel_vdd_on(intel_dp);
01cb9ea6 1126 if (is_edp(intel_dp))
f01eca2e 1127 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1128 intel_dp_sink_dpms(intel_dp, mode);
736085bc 1129 intel_dp_link_down(intel_dp);
f01eca2e 1130 ironlake_edp_panel_off(encoder);
01cb9ea6 1131 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
d240f20f 1132 ironlake_edp_pll_off(encoder);
245e2708 1133 ironlake_edp_panel_vdd_off(intel_dp);
a4fc5ed6 1134 } else {
97af61f5 1135 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1136 intel_dp_sink_dpms(intel_dp, mode);
32f9d658 1137 if (!(dp_reg & DP_PORT_EN)) {
01cb9ea6 1138 intel_dp_start_link_train(intel_dp);
97af61f5
KP		 1139 ironlake_edp_panel_on(intel_dp);
1140 ironlake_edp_panel_vdd_off(intel_dp);
33a34e4e 1141 intel_dp_complete_link_train(intel_dp);
f01eca2e 1142 ironlake_edp_backlight_on(intel_dp);
bee7eb2d
KP		 1143 } else
1144 ironlake_edp_panel_vdd_off(intel_dp);
a4fc5ed6 1145 }
d2b996ac 1146 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 1147}
1148
1149/*
df0c237d
JB		 1150 * Native read with retry for link status and receiver capability reads for
1151 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1152 */
1153static bool
df0c237d
JB		 1154intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1155 uint8_t *recv, int recv_bytes)
a4fc5ed6 1156{
61da5fab
JB		 1157 int ret, i;
1158
df0c237d
JB		 1159 /*
1160 * Sinks are *supposed* to come up within 1ms from an off state,
1161 * but we're also supposed to retry 3 times per the spec.
1162 */
61da5fab 1163 for (i = 0; i < 3; i++) {
df0c237d
JB		 1164 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1165 recv_bytes);
1166 if (ret == recv_bytes)
61da5fab
JB		 1167 return true;
1168 msleep(1);
1169 }
a4fc5ed6 1170
61da5fab 1171 return false;
a4fc5ed6
KP		 1172}
1173
1174/*
1175 * Fetch AUX CH registers 0x202 - 0x207 which contain
1176 * link status information
1177 */
1178static bool
33a34e4e 1179intel_dp_get_link_status(struct intel_dp *intel_dp)
a4fc5ed6 1180{
df0c237d
JB		 1181 return intel_dp_aux_native_read_retry(intel_dp,
1182 DP_LANE0_1_STATUS,
1183 intel_dp->link_status,
1184 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1185}
1186
1187static uint8_t
1188intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1189 int r)
1190{
1191 return link_status[r - DP_LANE0_1_STATUS];
1192}
1193
a4fc5ed6
KP		 1194static uint8_t
1195intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1196 int lane)
1197{
1198 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1199 int s = ((lane & 1) ?
1200 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1201 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1202 uint8_t l = intel_dp_link_status(link_status, i);
1203
1204 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1205}
1206
1207static uint8_t
1208intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1209 int lane)
1210{
1211 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1212 int s = ((lane & 1) ?
1213 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1214 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1215 uint8_t l = intel_dp_link_status(link_status, i);
1216
1217 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1218}
1219
1220
1221#if 0
1222static char *voltage_names[] = {
1223 "0.4V", "0.6V", "0.8V", "1.2V"
1224};
1225static char *pre_emph_names[] = {
1226 "0dB", "3.5dB", "6dB", "9.5dB"
1227};
1228static char *link_train_names[] = {
1229 "pattern 1", "pattern 2", "idle", "off"
1230};
1231#endif
1232
1233/*
1234 * These are source-specific values; current Intel hardware supports
1235 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1236 */
1237#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1238
1239static uint8_t
1240intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1241{
1242 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1243 case DP_TRAIN_VOLTAGE_SWING_400:
1244 return DP_TRAIN_PRE_EMPHASIS_6;
1245 case DP_TRAIN_VOLTAGE_SWING_600:
1246 return DP_TRAIN_PRE_EMPHASIS_6;
1247 case DP_TRAIN_VOLTAGE_SWING_800:
1248 return DP_TRAIN_PRE_EMPHASIS_3_5;
1249 case DP_TRAIN_VOLTAGE_SWING_1200:
1250 default:
1251 return DP_TRAIN_PRE_EMPHASIS_0;
1252 }
1253}
1254
1255static void
33a34e4e 1256intel_get_adjust_train(struct intel_dp *intel_dp)
a4fc5ed6
KP		 1257{
1258 uint8_t v = 0;
1259 uint8_t p = 0;
1260 int lane;
1261
33a34e4e
JB		 1262 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1263 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1264 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
a4fc5ed6
KP		 1265
1266 if (this_v > v)
1267 v = this_v;
1268 if (this_p > p)
1269 p = this_p;
1270 }
1271
1272 if (v >= I830_DP_VOLTAGE_MAX)
1273 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1274
1275 if (p >= intel_dp_pre_emphasis_max(v))
1276 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1277
1278 for (lane = 0; lane < 4; lane++)
33a34e4e 1279 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1280}
1281
1282static uint32_t
3cf2efb1 1283intel_dp_signal_levels(uint8_t train_set, int lane_count)
a4fc5ed6 1284{
3cf2efb1 1285 uint32_t signal_levels = 0;
a4fc5ed6 1286
3cf2efb1 1287 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1288 case DP_TRAIN_VOLTAGE_SWING_400:
1289 default:
1290 signal_levels |= DP_VOLTAGE_0_4;
1291 break;
1292 case DP_TRAIN_VOLTAGE_SWING_600:
1293 signal_levels |= DP_VOLTAGE_0_6;
1294 break;
1295 case DP_TRAIN_VOLTAGE_SWING_800:
1296 signal_levels |= DP_VOLTAGE_0_8;
1297 break;
1298 case DP_TRAIN_VOLTAGE_SWING_1200:
1299 signal_levels |= DP_VOLTAGE_1_2;
1300 break;
1301 }
3cf2efb1 1302 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1303 case DP_TRAIN_PRE_EMPHASIS_0:
1304 default:
1305 signal_levels |= DP_PRE_EMPHASIS_0;
1306 break;
1307 case DP_TRAIN_PRE_EMPHASIS_3_5:
1308 signal_levels |= DP_PRE_EMPHASIS_3_5;
1309 break;
1310 case DP_TRAIN_PRE_EMPHASIS_6:
1311 signal_levels |= DP_PRE_EMPHASIS_6;
1312 break;
1313 case DP_TRAIN_PRE_EMPHASIS_9_5:
1314 signal_levels |= DP_PRE_EMPHASIS_9_5;
1315 break;
1316 }
1317 return signal_levels;
1318}
1319
e3421a18
ZW		 1320/* Gen6's DP voltage swing and pre-emphasis control */
1321static uint32_t
1322intel_gen6_edp_signal_levels(uint8_t train_set)
1323{
3c5a62b5
YL		 1324 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1325 DP_TRAIN_PRE_EMPHASIS_MASK);
1326 switch (signal_levels) {
e3421a18 1327 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1328 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1329 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1330 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1331 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1332 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1333 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1334 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1335 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1336 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1337 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1338 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1339 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1340 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1341 default:
3c5a62b5
YL		 1342 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1343 "0x%x\n", signal_levels);
1344 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1345 }
1346}
1347
a4fc5ed6
KP		 1348static uint8_t
1349intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1350 int lane)
1351{
1352 int i = DP_LANE0_1_STATUS + (lane >> 1);
1353 int s = (lane & 1) * 4;
1354 uint8_t l = intel_dp_link_status(link_status, i);
1355
1356 return (l >> s) & 0xf;
1357}
1358
1359/* Check for clock recovery is done on all channels */
1360static bool
1361intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1362{
1363 int lane;
1364 uint8_t lane_status;
1365
1366 for (lane = 0; lane < lane_count; lane++) {
1367 lane_status = intel_get_lane_status(link_status, lane);
1368 if ((lane_status & DP_LANE_CR_DONE) == 0)
1369 return false;
1370 }
1371 return true;
1372}
1373
1374/* Check to see if channel eq is done on all channels */
1375#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1376 DP_LANE_CHANNEL_EQ_DONE|\
1377 DP_LANE_SYMBOL_LOCKED)
1378static bool
33a34e4e 1379intel_channel_eq_ok(struct intel_dp *intel_dp)
a4fc5ed6
KP		 1380{
1381 uint8_t lane_align;
1382 uint8_t lane_status;
1383 int lane;
1384
33a34e4e 1385 lane_align = intel_dp_link_status(intel_dp->link_status,
a4fc5ed6
KP		 1386 DP_LANE_ALIGN_STATUS_UPDATED);
1387 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1388 return false;
33a34e4e
JB		 1389 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1390 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
a4fc5ed6
KP		 1391 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1392 return false;
1393 }
1394 return true;
1395}
1396
1397static bool
ea5b213a 1398intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1399 uint32_t dp_reg_value,
58e10eb9 1400 uint8_t dp_train_pat)
a4fc5ed6 1401{
4ef69c7a 1402 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1403 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1404 int ret;
1405
ea5b213a
CW		 1406 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1407 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1408
ea5b213a 1409 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1410 DP_TRAINING_PATTERN_SET,
1411 dp_train_pat);
1412
ea5b213a 1413 ret = intel_dp_aux_native_write(intel_dp,
58e10eb9
CW		 1414 DP_TRAINING_LANE0_SET,
1415 intel_dp->train_set, 4);
a4fc5ed6
KP		 1416 if (ret != 4)
1417 return false;
1418
1419 return true;
1420}
1421
33a34e4e 1422/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1423static void
33a34e4e 1424intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1425{
4ef69c7a 1426 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1427 struct drm_i915_private *dev_priv = dev->dev_private;
58e10eb9 1428 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
a4fc5ed6
KP		 1429 int i;
1430 uint8_t voltage;
1431 bool clock_recovery = false;
a4fc5ed6 1432 int tries;
e3421a18 1433 u32 reg;
ea5b213a 1434 uint32_t DP = intel_dp->DP;
a4fc5ed6 1435
e8519464
AJ		 1436 /*
1437 * On CPT we have to enable the port in training pattern 1, which
1438 * will happen below in intel_dp_set_link_train. Otherwise, enable
1439 * the port and wait for it to become active.
1440 */
1441 if (!HAS_PCH_CPT(dev)) {
1442 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1443 POSTING_READ(intel_dp->output_reg);
1444 intel_wait_for_vblank(dev, intel_crtc->pipe);
1445 }
a4fc5ed6 1446
3cf2efb1
CW		 1447 /* Write the link configuration data */
1448 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1449 intel_dp->link_configuration,
1450 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1451
1452 DP |= DP_PORT_EN;
cfcb0fc9 1453 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
e3421a18
ZW		 1454 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1455 else
1456 DP &= ~DP_LINK_TRAIN_MASK;
33a34e4e 1457 memset(intel_dp->train_set, 0, 4);
a4fc5ed6
KP		 1458 voltage = 0xff;
1459 tries = 0;
1460 clock_recovery = false;
1461 for (;;) {
33a34e4e 1462 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1463 uint32_t signal_levels;
cfcb0fc9 1464 if (IS_GEN6(dev) && is_edp(intel_dp)) {
33a34e4e 1465 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1466 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1467 } else {
3cf2efb1 1468 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1469 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1470 }
a4fc5ed6 1471
cfcb0fc9 1472 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
e3421a18
ZW		 1473 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1474 else
1475 reg = DP | DP_LINK_TRAIN_PAT_1;
1476
ea5b213a 1477 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1478 DP_TRAINING_PATTERN_1 |
1479 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1480 break;
a4fc5ed6
KP		 1481 /* Set training pattern 1 */
1482
3cf2efb1
CW		 1483 udelay(100);
1484 if (!intel_dp_get_link_status(intel_dp))
a4fc5ed6 1485 break;
a4fc5ed6 1486
3cf2efb1
CW		 1487 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1488 clock_recovery = true;
1489 break;
1490 }
1491
1492 /* Check to see if we've tried the max voltage */
1493 for (i = 0; i < intel_dp->lane_count; i++)
1494 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1495 break;
3cf2efb1
CW		 1496 if (i == intel_dp->lane_count)
1497 break;
a4fc5ed6 1498
3cf2efb1
CW		 1499 /* Check to see if we've tried the same voltage 5 times */
1500 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1501 ++tries;
1502 if (tries == 5)
a4fc5ed6 1503 break;
3cf2efb1
CW		 1504 } else
1505 tries = 0;
1506 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1507
3cf2efb1
CW		 1508 /* Compute new intel_dp->train_set as requested by target */
1509 intel_get_adjust_train(intel_dp);
a4fc5ed6
KP		 1510 }
1511
33a34e4e
JB		 1512 intel_dp->DP = DP;
1513}
1514
1515static void
1516intel_dp_complete_link_train(struct intel_dp *intel_dp)
1517{
4ef69c7a 1518 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e
JB		 1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 bool channel_eq = false;
37f80975 1521 int tries, cr_tries;
33a34e4e
JB		 1522 u32 reg;
1523 uint32_t DP = intel_dp->DP;
1524
a4fc5ed6
KP		 1525 /* channel equalization */
1526 tries = 0;
37f80975 1527 cr_tries = 0;
a4fc5ed6
KP		 1528 channel_eq = false;
1529 for (;;) {
33a34e4e 1530 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1531 uint32_t signal_levels;
1532
37f80975
JB		 1533 if (cr_tries > 5) {
1534 DRM_ERROR("failed to train DP, aborting\n");
1535 intel_dp_link_down(intel_dp);
1536 break;
1537 }
1538
cfcb0fc9 1539 if (IS_GEN6(dev) && is_edp(intel_dp)) {
33a34e4e 1540 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1541 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1542 } else {
3cf2efb1 1543 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1544 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1545 }
1546
cfcb0fc9 1547 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
e3421a18
ZW		 1548 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1549 else
1550 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1551
1552 /* channel eq pattern */
ea5b213a 1553 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1554 DP_TRAINING_PATTERN_2 |
1555 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1556 break;
1557
3cf2efb1
CW		 1558 udelay(400);
1559 if (!intel_dp_get_link_status(intel_dp))
a4fc5ed6 1560 break;
a4fc5ed6 1561
37f80975
JB		 1562 /* Make sure clock is still ok */
1563 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1564 intel_dp_start_link_train(intel_dp);
1565 cr_tries++;
1566 continue;
1567 }
1568
3cf2efb1
CW		 1569 if (intel_channel_eq_ok(intel_dp)) {
1570 channel_eq = true;
1571 break;
1572 }
a4fc5ed6 1573
37f80975
JB		 1574 /* Try 5 times, then try clock recovery if that fails */
1575 if (tries > 5) {
1576 intel_dp_link_down(intel_dp);
1577 intel_dp_start_link_train(intel_dp);
1578 tries = 0;
1579 cr_tries++;
1580 continue;
1581 }
a4fc5ed6 1582
3cf2efb1
CW		 1583 /* Compute new intel_dp->train_set as requested by target */
1584 intel_get_adjust_train(intel_dp);
1585 ++tries;
869184a6 1586 }
3cf2efb1 1587
cfcb0fc9 1588 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
e3421a18
ZW		 1589 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1590 else
1591 reg = DP | DP_LINK_TRAIN_OFF;
1592
ea5b213a
CW		 1593 I915_WRITE(intel_dp->output_reg, reg);
1594 POSTING_READ(intel_dp->output_reg);
1595 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1596 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1597}
1598
1599static void
ea5b213a 1600intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1601{
4ef69c7a 1602 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1603 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1604 uint32_t DP = intel_dp->DP;
a4fc5ed6 1605
1b39d6f3
CW		 1606 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1607 return;
1608
28c97730 1609 DRM_DEBUG_KMS("\n");
32f9d658 1610
cfcb0fc9 1611 if (is_edp(intel_dp)) {
32f9d658 1612 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1613 I915_WRITE(intel_dp->output_reg, DP);
1614 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1615 udelay(100);
1616 }
1617
cfcb0fc9 1618 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
e3421a18 1619 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1620 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1621 } else {
1622 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1623 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1624 }
fe255d00 1625 POSTING_READ(intel_dp->output_reg);
5eb08b69 1626
fe255d00 1627 msleep(17);
5eb08b69 1628
cfcb0fc9 1629 if (is_edp(intel_dp))
32f9d658 1630 DP |= DP_LINK_TRAIN_OFF;
5bddd17f 1631
1b39d6f3
CW		 1632 if (!HAS_PCH_CPT(dev) &&
1633 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1634 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1635
5bddd17f
EA		 1636 /* Hardware workaround: leaving our transcoder select
1637 * set to transcoder B while it's off will prevent the
1638 * corresponding HDMI output on transcoder A.
1639 *
1640 * Combine this with another hardware workaround:
1641 * transcoder select bit can only be cleared while the
1642 * port is enabled.
1643 */
1644 DP &= ~DP_PIPEB_SELECT;
1645 I915_WRITE(intel_dp->output_reg, DP);
1646
1647 /* Changes to enable or select take place the vblank
1648 * after being written.
1649 */
31acbcc4
CW		 1650 if (crtc == NULL) {
1651 /* We can arrive here never having been attached
1652 * to a CRTC, for instance, due to inheriting
1653 * random state from the BIOS.
1654 *
1655 * If the pipe is not running, play safe and
1656 * wait for the clocks to stabilise before
1657 * continuing.
1658 */
1659 POSTING_READ(intel_dp->output_reg);
1660 msleep(50);
1661 } else
1662 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1663 }
1664
ea5b213a
CW		 1665 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1666 POSTING_READ(intel_dp->output_reg);
f01eca2e 1667 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1668}
1669
26d61aad
KP		 1670static bool
1671intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1672{
92fd8fd1
KP		 1673 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1674 sizeof (intel_dp->dpcd)) &&
1675 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1676 return true;
92fd8fd1
KP		 1677 }
1678
26d61aad 1679 return false;
92fd8fd1
KP		 1680}
1681
a4fc5ed6
KP		 1682/*
1683 * According to DP spec
1684 * 5.1.2:
1685 * 1. Read DPCD
1686 * 2. Configure link according to Receiver Capabilities
1687 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1688 * 4. Check link status on receipt of hot-plug interrupt
1689 */
1690
1691static void
ea5b213a 1692intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 1693{
d2b996ac
KP		 1694 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1695 return;
59cd09e1 1696
4ef69c7a 1697 if (!intel_dp->base.base.crtc)
a4fc5ed6
KP		 1698 return;
1699
92fd8fd1 1700 /* Try to read receiver status if the link appears to be up */
33a34e4e 1701 if (!intel_dp_get_link_status(intel_dp)) {
ea5b213a 1702 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 1703 return;
1704 }
1705
92fd8fd1 1706 /* Now read the DPCD to see if it's actually running */
26d61aad 1707 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 1708 intel_dp_link_down(intel_dp);
1709 return;
1710 }
1711
33a34e4e 1712 if (!intel_channel_eq_ok(intel_dp)) {
92fd8fd1
KP		 1713 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1714 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 1715 intel_dp_start_link_train(intel_dp);
1716 intel_dp_complete_link_train(intel_dp);
1717 }
a4fc5ed6 1718}
a4fc5ed6 1719
71ba9000 1720static enum drm_connector_status
26d61aad 1721intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 1722{
26d61aad
KP		 1723 if (intel_dp_get_dpcd(intel_dp))
1724 return connector_status_connected;
1725 return connector_status_disconnected;
71ba9000
AJ		 1726}
1727
5eb08b69 1728static enum drm_connector_status
a9756bb5 1729ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 1730{
5eb08b69
ZW		 1731 enum drm_connector_status status;
1732
fe16d949
CW		 1733 /* Can't disconnect eDP, but you can close the lid... */
1734 if (is_edp(intel_dp)) {
1735 status = intel_panel_detect(intel_dp->base.base.dev);
1736 if (status == connector_status_unknown)
1737 status = connector_status_connected;
1738 return status;
1739 }
01cb9ea6 1740
26d61aad 1741 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 1742}
1743
a4fc5ed6 1744static enum drm_connector_status
a9756bb5 1745g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 1746{
4ef69c7a 1747 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1748 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 1749 uint32_t temp, bit;
5eb08b69 1750
ea5b213a 1751 switch (intel_dp->output_reg) {
a4fc5ed6
KP		 1752 case DP_B:
1753 bit = DPB_HOTPLUG_INT_STATUS;
1754 break;
1755 case DP_C:
1756 bit = DPC_HOTPLUG_INT_STATUS;
1757 break;
1758 case DP_D:
1759 bit = DPD_HOTPLUG_INT_STATUS;
1760 break;
1761 default:
1762 return connector_status_unknown;
1763 }
1764
1765 temp = I915_READ(PORT_HOTPLUG_STAT);
1766
1767 if ((temp & bit) == 0)
1768 return connector_status_disconnected;
1769
26d61aad 1770 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 1771}
1772
8c241fef
KP		 1773static struct edid *
1774intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1775{
1776 struct intel_dp *intel_dp = intel_attached_dp(connector);
1777 struct edid *edid;
1778
1779 ironlake_edp_panel_vdd_on(intel_dp);
1780 edid = drm_get_edid(connector, adapter);
1781 ironlake_edp_panel_vdd_off(intel_dp);
1782 return edid;
1783}
1784
1785static int
1786intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1787{
1788 struct intel_dp *intel_dp = intel_attached_dp(connector);
1789 int ret;
1790
1791 ironlake_edp_panel_vdd_on(intel_dp);
1792 ret = intel_ddc_get_modes(connector, adapter);
1793 ironlake_edp_panel_vdd_off(intel_dp);
1794 return ret;
1795}
1796
1797
a9756bb5
ZW		 1798/**
1799 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1800 *
1801 * \return true if DP port is connected.
1802 * \return false if DP port is disconnected.
1803 */
1804static enum drm_connector_status
1805intel_dp_detect(struct drm_connector *connector, bool force)
1806{
1807 struct intel_dp *intel_dp = intel_attached_dp(connector);
1808 struct drm_device *dev = intel_dp->base.base.dev;
1809 enum drm_connector_status status;
1810 struct edid *edid = NULL;
1811
1812 intel_dp->has_audio = false;
1813
1814 if (HAS_PCH_SPLIT(dev))
1815 status = ironlake_dp_detect(intel_dp);
1816 else
1817 status = g4x_dp_detect(intel_dp);
1b9be9d0 1818
ac66ae83
AJ		 1819 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1820 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1821 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1822 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 1823
a9756bb5
ZW		 1824 if (status != connector_status_connected)
1825 return status;
1826
f684960e
CW		 1827 if (intel_dp->force_audio) {
1828 intel_dp->has_audio = intel_dp->force_audio > 0;
1829 } else {
8c241fef 1830 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 1831 if (edid) {
1832 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1833 connector->display_info.raw_edid = NULL;
1834 kfree(edid);
1835 }
a9756bb5
ZW		 1836 }
1837
1838 return connector_status_connected;
a4fc5ed6
KP		 1839}
1840
1841static int intel_dp_get_modes(struct drm_connector *connector)
1842{
df0e9248 1843 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 1844 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 int ret;
a4fc5ed6
KP		 1847
1848 /* We should parse the EDID data and find out if it has an audio sink
1849 */
1850
8c241fef 1851 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 1852 if (ret) {
d15456de 1853 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 1854 struct drm_display_mode *newmode;
1855 list_for_each_entry(newmode, &connector->probed_modes,
1856 head) {
d15456de
KP		 1857 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
1858 intel_dp->panel_fixed_mode =
b9efc480
ZY		 1859 drm_mode_duplicate(dev, newmode);
1860 break;
1861 }
1862 }
1863 }
32f9d658 1864 return ret;
b9efc480 1865 }
32f9d658
ZW		 1866
1867 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 1868 if (is_edp(intel_dp)) {
47f0eb22 1869 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 1870 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1871 intel_dp->panel_fixed_mode =
47f0eb22 1872 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 1873 if (intel_dp->panel_fixed_mode) {
1874 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 1875 DRM_MODE_TYPE_PREFERRED;
1876 }
1877 }
d15456de 1878 if (intel_dp->panel_fixed_mode) {
32f9d658 1879 struct drm_display_mode *mode;
d15456de 1880 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 1881 drm_mode_probed_add(connector, mode);
1882 return 1;
1883 }
1884 }
1885 return 0;
a4fc5ed6
KP		 1886}
1887
1aad7ac0
CW		 1888static bool
1889intel_dp_detect_audio(struct drm_connector *connector)
1890{
1891 struct intel_dp *intel_dp = intel_attached_dp(connector);
1892 struct edid *edid;
1893 bool has_audio = false;
1894
8c241fef 1895 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 1896 if (edid) {
1897 has_audio = drm_detect_monitor_audio(edid);
1898
1899 connector->display_info.raw_edid = NULL;
1900 kfree(edid);
1901 }
1902
1903 return has_audio;
1904}
1905
f684960e
CW		 1906static int
1907intel_dp_set_property(struct drm_connector *connector,
1908 struct drm_property *property,
1909 uint64_t val)
1910{
e953fd7b 1911 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 1912 struct intel_dp *intel_dp = intel_attached_dp(connector);
1913 int ret;
1914
1915 ret = drm_connector_property_set_value(connector, property, val);
1916 if (ret)
1917 return ret;
1918
3f43c48d 1919 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1920 int i = val;
1921 bool has_audio;
1922
1923 if (i == intel_dp->force_audio)
f684960e
CW		 1924 return 0;
1925
1aad7ac0 1926 intel_dp->force_audio = i;
f684960e 1927
1aad7ac0
CW		 1928 if (i == 0)
1929 has_audio = intel_dp_detect_audio(connector);
1930 else
1931 has_audio = i > 0;
1932
1933 if (has_audio == intel_dp->has_audio)
f684960e
CW		 1934 return 0;
1935
1aad7ac0 1936 intel_dp->has_audio = has_audio;
f684960e
CW		 1937 goto done;
1938 }
1939
e953fd7b
CW		 1940 if (property == dev_priv->broadcast_rgb_property) {
1941 if (val == !!intel_dp->color_range)
1942 return 0;
1943
1944 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1945 goto done;
1946 }
1947
f684960e
CW		 1948 return -EINVAL;
1949
1950done:
1951 if (intel_dp->base.base.crtc) {
1952 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1953 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1954 crtc->x, crtc->y,
1955 crtc->fb);
1956 }
1957
1958 return 0;
1959}
1960
a4fc5ed6
KP		 1961static void
1962intel_dp_destroy (struct drm_connector *connector)
1963{
aaa6fd2a
MG		 1964 struct drm_device *dev = connector->dev;
1965
1966 if (intel_dpd_is_edp(dev))
1967 intel_panel_destroy_backlight(dev);
1968
a4fc5ed6
KP		 1969 drm_sysfs_connector_remove(connector);
1970 drm_connector_cleanup(connector);
55f78c43 1971 kfree(connector);
a4fc5ed6
KP		 1972}
1973
24d05927
DV		 1974static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1975{
1976 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1977
1978 i2c_del_adapter(&intel_dp->adapter);
1979 drm_encoder_cleanup(encoder);
1980 kfree(intel_dp);
1981}
1982
a4fc5ed6
KP		 1983static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1984 .dpms = intel_dp_dpms,
1985 .mode_fixup = intel_dp_mode_fixup,
d240f20f 1986 .prepare = intel_dp_prepare,
a4fc5ed6 1987 .mode_set = intel_dp_mode_set,
d240f20f 1988 .commit = intel_dp_commit,
a4fc5ed6
KP		 1989};
1990
1991static const struct drm_connector_funcs intel_dp_connector_funcs = {
1992 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1993 .detect = intel_dp_detect,
1994 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 1995 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 1996 .destroy = intel_dp_destroy,
1997};
1998
1999static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2000 .get_modes = intel_dp_get_modes,
2001 .mode_valid = intel_dp_mode_valid,
df0e9248 2002 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2003};
2004
a4fc5ed6 2005static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2006 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2007};
2008
995b6762 2009static void
21d40d37 2010intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2011{
ea5b213a 2012 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2013
885a5014 2014 intel_dp_check_link_status(intel_dp);
c8110e52 2015}
6207937d 2016
e3421a18
ZW		 2017/* Return which DP Port should be selected for Transcoder DP control */
2018int
2019intel_trans_dp_port_sel (struct drm_crtc *crtc)
2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_mode_config *mode_config = &dev->mode_config;
2023 struct drm_encoder *encoder;
e3421a18
ZW		 2024
2025 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 2026 struct intel_dp *intel_dp;
2027
d8201ab6 2028 if (encoder->crtc != crtc)
e3421a18
ZW		 2029 continue;
2030
ea5b213a
CW		 2031 intel_dp = enc_to_intel_dp(encoder);
2032 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2033 return intel_dp->output_reg;
e3421a18 2034 }
ea5b213a 2035
e3421a18
ZW		 2036 return -1;
2037}
2038
36e83a18 2039/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2040bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2041{
2042 struct drm_i915_private *dev_priv = dev->dev_private;
2043 struct child_device_config *p_child;
2044 int i;
2045
2046 if (!dev_priv->child_dev_num)
2047 return false;
2048
2049 for (i = 0; i < dev_priv->child_dev_num; i++) {
2050 p_child = dev_priv->child_dev + i;
2051
2052 if (p_child->dvo_port == PORT_IDPD &&
2053 p_child->device_type == DEVICE_TYPE_eDP)
2054 return true;
2055 }
2056 return false;
2057}
2058
f684960e
CW		 2059static void
2060intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2061{
3f43c48d 2062 intel_attach_force_audio_property(connector);
e953fd7b 2063 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2064}
2065
a4fc5ed6
KP		 2066void
2067intel_dp_init(struct drm_device *dev, int output_reg)
2068{
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 struct drm_connector *connector;
ea5b213a 2071 struct intel_dp *intel_dp;
21d40d37 2072 struct intel_encoder *intel_encoder;
55f78c43 2073 struct intel_connector *intel_connector;
5eb08b69 2074 const char *name = NULL;
b329530c 2075 int type;
a4fc5ed6 2076
ea5b213a
CW		 2077 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2078 if (!intel_dp)
a4fc5ed6
KP		 2079 return;
2080
3d3dc149 2081 intel_dp->output_reg = output_reg;
d2b996ac 2082 intel_dp->dpms_mode = -1;
3d3dc149 2083
55f78c43
ZW		 2084 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2085 if (!intel_connector) {
ea5b213a 2086 kfree(intel_dp);
55f78c43
ZW		 2087 return;
2088 }
ea5b213a 2089 intel_encoder = &intel_dp->base;
55f78c43 2090
ea5b213a 2091 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2092 if (intel_dpd_is_edp(dev))
ea5b213a 2093 intel_dp->is_pch_edp = true;
b329530c 2094
cfcb0fc9 2095 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2096 type = DRM_MODE_CONNECTOR_eDP;
2097 intel_encoder->type = INTEL_OUTPUT_EDP;
2098 } else {
2099 type = DRM_MODE_CONNECTOR_DisplayPort;
2100 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2101 }
2102
55f78c43 2103 connector = &intel_connector->base;
b329530c 2104 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2105 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2106
eb1f8e4f
DA		 2107 connector->polled = DRM_CONNECTOR_POLL_HPD;
2108
652af9d7 2109 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 2110 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 2111 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 2112 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 2113 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 2114 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 2115
cfcb0fc9 2116 if (is_edp(intel_dp))
21d40d37 2117 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 2118
21d40d37 2119 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 2120 connector->interlace_allowed = true;
2121 connector->doublescan_allowed = 0;
2122
4ef69c7a 2123 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2124 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2125 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2126
df0e9248 2127 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2128 drm_sysfs_connector_add(connector);
2129
2130 /* Set up the DDC bus. */
5eb08b69 2131 switch (output_reg) {
32f9d658
ZW		 2132 case DP_A:
2133 name = "DPDDC-A";
2134 break;
5eb08b69
ZW		 2135 case DP_B:
2136 case PCH_DP_B:
b01f2c3a
JB		 2137 dev_priv->hotplug_supported_mask |=
2138 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2139 name = "DPDDC-B";
2140 break;
2141 case DP_C:
2142 case PCH_DP_C:
b01f2c3a
JB		 2143 dev_priv->hotplug_supported_mask |=
2144 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2145 name = "DPDDC-C";
2146 break;
2147 case DP_D:
2148 case PCH_DP_D:
b01f2c3a
JB		 2149 dev_priv->hotplug_supported_mask |=
2150 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2151 name = "DPDDC-D";
2152 break;
2153 }
2154
89667383
JB		 2155 /* Cache some DPCD data in the eDP case */
2156 if (is_edp(intel_dp)) {
59f3e272 2157 bool ret;
f01eca2e
KP		 2158 struct edp_power_seq cur, vbt;
2159 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2160
2161 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2162 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2163 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2164
f01eca2e
KP		 2165 /* Pull timing values out of registers */
2166 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2167 PANEL_POWER_UP_DELAY_SHIFT;
2168
2169 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2170 PANEL_LIGHT_ON_DELAY_SHIFT;
2171
2172 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2173 PANEL_LIGHT_OFF_DELAY_SHIFT;
2174
2175 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2176 PANEL_POWER_DOWN_DELAY_SHIFT;
2177
2178 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2179 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2180
2181 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2182 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2183
2184 vbt = dev_priv->edp.pps;
2185
2186 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2187 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2188
2189#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2190
2191 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2192 intel_dp->backlight_on_delay = get_delay(t8);
2193 intel_dp->backlight_off_delay = get_delay(t9);
2194 intel_dp->panel_power_down_delay = get_delay(t10);
2195 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2196
2197 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2198 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2199 intel_dp->panel_power_cycle_delay);
2200
2201 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2202 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2203
2204 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2205 ret = intel_dp_get_dpcd(intel_dp);
3d3dc149 2206 ironlake_edp_panel_vdd_off(intel_dp);
59f3e272 2207 if (ret) {
7183dc29
JB		 2208 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2209 dev_priv->no_aux_handshake =
2210 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2211 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2212 } else {
3d3dc149 2213 /* if this fails, presume the device is a ghost */
48898b03 2214 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2215 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2216 intel_dp_destroy(&intel_connector->base);
3d3dc149 2217 return;
89667383 2218 }
89667383
JB		 2219 }
2220
552fb0b7
KP		 2221 intel_dp_i2c_init(intel_dp, intel_connector, name);
2222
21d40d37 2223 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2224
4d926461 2225 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2226 dev_priv->int_edp_connector = connector;
2227 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2228 }
2229
f684960e
CW		 2230 intel_dp_add_properties(intel_dp, connector);
2231
a4fc5ed6
KP		 2232 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2233 * 0xd. Failure to do so will result in spurious interrupts being
2234 * generated on the port when a cable is not attached.
2235 */
2236 if (IS_G4X(dev) && !IS_GM45(dev)) {
2237 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2238 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2239 }
2240}
Linux kernel - Deliverables
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