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drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
c4867936
DV		 180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
cb1793ce 183 bool adjust_mode)
c4867936 184{
9fa5f652
PZ		 185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
30add22d 295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
30add22d 303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
30add22d 312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
9ee32fea
DV		 325static uint32_t
326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
ef04f00d 354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea
DV		 355 if (has_aux_irq)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
357 else
358 done = wait_for_atomic(C, 10) == 0;
359 if (!done)
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 has_aux_irq);
362#undef C
363
364 return status;
365}
366
a4fc5ed6 367static int
ea5b213a 368intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
371{
ea5b213a 372 uint32_t output_reg = intel_dp->output_reg;
174edf1f
PZ		 373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
9ee32fea 378 int i, ret, recv_bytes;
a4fc5ed6 379 uint32_t status;
fb0f8fbf 380 uint32_t aux_clock_divider;
6b4e0a93 381 int try, precharge;
9ee32fea
DV		 382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
383
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
386 * deep sleep states.
387 */
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 389
750eb99e 390 if (IS_HASWELL(dev)) {
174edf1f 391 switch (intel_dig_port->port) {
750eb99e
PZ		 392 case PORT_A:
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
395 break;
396 case PORT_B:
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
399 break;
400 case PORT_C:
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
403 break;
404 case PORT_D:
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
407 break;
408 default:
409 BUG();
410 }
411 }
412
9b984dae 413 intel_dp_check_edp(intel_dp);
a4fc5ed6 414 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 417 *
418 * Note that PCH attached eDP panels should use a 125MHz input
419 * clock divider.
a4fc5ed6 420 */
1c95822a 421 if (is_cpu_edp(intel_dp)) {
affa9354 422 if (HAS_DDI(dev))
b8fc2f6a
PZ		 423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 428 else
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 432 else
433 aux_clock_divider = intel_hrawclk(dev) / 2;
434
6b4e0a93
DV		 435 if (IS_GEN6(dev))
436 precharge = 3;
437 else
438 precharge = 5;
439
11bee43e
JB		 440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
ef04f00d 442 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
444 break;
445 msleep(1);
446 }
447
448 if (try == 3) {
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
450 I915_READ(ch_ctl));
9ee32fea
DV		 451 ret = -EBUSY;
452 goto out;
4f7f7b7e
CW		 453 }
454
fb0f8fbf
KP		 455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
0206e353 461
fb0f8fbf 462 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 463 I915_WRITE(ch_ctl,
464 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 473
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 475
fb0f8fbf 476 /* Clear done status and any errors */
4f7f7b7e
CW		 477 I915_WRITE(ch_ctl,
478 status |
479 DP_AUX_CH_CTL_DONE |
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 482
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
485 continue;
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526
527 return ret;
a4fc5ed6
KP		 528}
529
530/* Write data to the aux channel in native mode */
531static int
ea5b213a 532intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 533 uint16_t address, uint8_t *send, int send_bytes)
534{
535 int ret;
536 uint8_t msg[20];
537 int msg_bytes;
538 uint8_t ack;
539
9b984dae 540 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 541 if (send_bytes > 16)
542 return -1;
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
eebc863e 545 msg[2] = address & 0xff;
a4fc5ed6
KP		 546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
549 for (;;) {
ea5b213a 550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 551 if (ret < 0)
552 return ret;
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
554 break;
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 udelay(100);
557 else
a5b3da54 558 return -EIO;
a4fc5ed6
KP		 559 }
560 return send_bytes;
561}
562
563/* Write a single byte to the aux channel in native mode */
564static int
ea5b213a 565intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 566 uint16_t address, uint8_t byte)
567{
ea5b213a 568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 569}
570
571/* read bytes from a native aux channel */
572static int
ea5b213a 573intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 574 uint16_t address, uint8_t *recv, int recv_bytes)
575{
576 uint8_t msg[4];
577 int msg_bytes;
578 uint8_t reply[20];
579 int reply_bytes;
580 uint8_t ack;
581 int ret;
582
9b984dae 583 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
588
589 msg_bytes = 4;
590 reply_bytes = recv_bytes + 1;
591
592 for (;;) {
ea5b213a 593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 594 reply, reply_bytes);
a5b3da54
KP		 595 if (ret == 0)
596 return -EPROTO;
597 if (ret < 0)
a4fc5ed6
KP		 598 return ret;
599 ack = reply[0];
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
602 return ret - 1;
603 }
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
605 udelay(100);
606 else
a5b3da54 607 return -EIO;
a4fc5ed6
KP		 608 }
609}
610
611static int
ab2c0672
DA		 612intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 614{
ab2c0672 615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 616 struct intel_dp *intel_dp = container_of(adapter,
617 struct intel_dp,
618 adapter);
ab2c0672
DA		 619 uint16_t address = algo_data->address;
620 uint8_t msg[5];
621 uint8_t reply[2];
8316f337 622 unsigned retry;
ab2c0672
DA		 623 int msg_bytes;
624 int reply_bytes;
625 int ret;
626
9b984dae 627 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
631 else
632 msg[0] = AUX_I2C_WRITE << 4;
633
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 636
ab2c0672
DA		 637 msg[1] = address >> 8;
638 msg[2] = address;
639
640 switch (mode) {
641 case MODE_I2C_WRITE:
642 msg[3] = 0;
643 msg[4] = write_byte;
644 msg_bytes = 5;
645 reply_bytes = 1;
646 break;
647 case MODE_I2C_READ:
648 msg[3] = 0;
649 msg_bytes = 4;
650 reply_bytes = 2;
651 break;
652 default:
653 msg_bytes = 3;
654 reply_bytes = 1;
655 break;
656 }
657
8316f337
DF		 658 for (retry = 0; retry < 5; retry++) {
659 ret = intel_dp_aux_ch(intel_dp,
660 msg, msg_bytes,
661 reply, reply_bytes);
ab2c0672 662 if (ret < 0) {
3ff99164 663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 664 return ret;
665 }
8316f337
DF		 666
667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
668 case AUX_NATIVE_REPLY_ACK:
669 /* I2C-over-AUX Reply field is only valid
670 * when paired with AUX ACK.
671 */
672 break;
673 case AUX_NATIVE_REPLY_NACK:
674 DRM_DEBUG_KMS("aux_ch native nack\n");
675 return -EREMOTEIO;
676 case AUX_NATIVE_REPLY_DEFER:
677 udelay(100);
678 continue;
679 default:
680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
681 reply[0]);
682 return -EREMOTEIO;
683 }
684
ab2c0672
DA		 685 switch (reply[0] & AUX_I2C_REPLY_MASK) {
686 case AUX_I2C_REPLY_ACK:
687 if (mode == MODE_I2C_READ) {
688 *read_byte = reply[1];
689 }
690 return reply_bytes - 1;
691 case AUX_I2C_REPLY_NACK:
8316f337 692 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 693 return -EREMOTEIO;
694 case AUX_I2C_REPLY_DEFER:
8316f337 695 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 696 udelay(100);
697 break;
698 default:
8316f337 699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 700 return -EREMOTEIO;
701 }
702 }
8316f337
DF		 703
704 DRM_ERROR("too many retries, giving up\n");
705 return -EREMOTEIO;
a4fc5ed6
KP		 706}
707
708static int
ea5b213a 709intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 710 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 711{
0b5c541b
KP		 712 int ret;
713
d54e9d28 714 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 715 intel_dp->algo.running = false;
716 intel_dp->algo.address = 0;
717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
718
0206e353 719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 720 intel_dp->adapter.owner = THIS_MODULE;
721 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
724 intel_dp->adapter.algo_data = &intel_dp->algo;
725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
726
0b5c541b
KP		 727 ironlake_edp_panel_vdd_on(intel_dp);
728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 729 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 730 return ret;
a4fc5ed6
KP		 731}
732
00c09d70 733bool
e811f5ae
LP		 734intel_dp_mode_fixup(struct drm_encoder *encoder,
735 const struct drm_display_mode *mode,
a4fc5ed6
KP		 736 struct drm_display_mode *adjusted_mode)
737{
0d3a1bee 738 struct drm_device *dev = encoder->dev;
ea5b213a 739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 740 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 741 int lane_count, clock;
397fe157 742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 744 int bpp, mode_rate;
a4fc5ed6
KP		 745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
746
dd06f90e
JN		 747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
749 adjusted_mode);
53b41837
YN		 750 intel_pch_panel_fitting(dev,
751 intel_connector->panel.fitting_mode,
1d8e1c75 752 mode, adjusted_mode);
0d3a1bee
ZY		 753 }
754
cb1793ce 755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 756 return false;
757
083f9560
DV		 758 DRM_DEBUG_KMS("DP link computation with max lane count %i "
759 "max bw %02x pixel clock %iKHz\n",
71244653 760 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 761
cb1793ce 762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 763 return false;
764
765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 766 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 767
2514bc51
JB		 768 for (clock = 0; clock <= max_clock; clock++) {
769 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
9fa5f652
PZ		 770 int link_bw_clock =
771 drm_dp_bw_code_to_link_rate(bws[clock]);
772 int link_avail = intel_dp_max_data_rate(link_bw_clock,
773 lane_count);
a4fc5ed6 774
083f9560 775 if (mode_rate <= link_avail) {
ea5b213a
CW		 776 intel_dp->link_bw = bws[clock];
777 intel_dp->lane_count = lane_count;
9fa5f652 778 adjusted_mode->clock = link_bw_clock;
083f9560
DV		 779 DRM_DEBUG_KMS("DP link bw %02x lane "
780 "count %d clock %d bpp %d\n",
ea5b213a 781 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 782 adjusted_mode->clock, bpp);
783 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
784 mode_rate, link_avail);
a4fc5ed6
KP		 785 return true;
786 }
787 }
788 }
fe27d53e 789
a4fc5ed6
KP		 790 return false;
791}
792
793struct intel_dp_m_n {
794 uint32_t tu;
795 uint32_t gmch_m;
796 uint32_t gmch_n;
797 uint32_t link_m;
798 uint32_t link_n;
799};
800
801static void
802intel_reduce_ratio(uint32_t *num, uint32_t *den)
803{
804 while (*num > 0xffffff || *den > 0xffffff) {
805 *num >>= 1;
806 *den >>= 1;
807 }
808}
809
810static void
36e83a18 811intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 812 int nlanes,
813 int pixel_clock,
814 int link_clock,
815 struct intel_dp_m_n *m_n)
816{
817 m_n->tu = 64;
36e83a18 818 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 819 m_n->gmch_n = link_clock * nlanes;
820 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
821 m_n->link_m = pixel_clock;
822 m_n->link_n = link_clock;
823 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
824}
825
826void
827intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
828 struct drm_display_mode *adjusted_mode)
829{
830 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 831 struct intel_encoder *intel_encoder;
832 struct intel_dp *intel_dp;
a4fc5ed6
KP		 833 struct drm_i915_private *dev_priv = dev->dev_private;
834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 835 int lane_count = 4;
a4fc5ed6 836 struct intel_dp_m_n m_n;
9db4a9c7 837 int pipe = intel_crtc->pipe;
afe2fcf5 838 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 839
840 /*
21d40d37 841 * Find the lane count in the intel_encoder private
a4fc5ed6 842 */
fa90ecef
PZ		 843 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
844 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 845
fa90ecef
PZ		 846 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
847 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 848 {
ea5b213a 849 lane_count = intel_dp->lane_count;
51190667 850 break;
a4fc5ed6
KP		 851 }
852 }
853
854 /*
855 * Compute the GMCH and Link ratios. The '3' here is
856 * the number of bytes_per_pixel post-LUT, which we always
857 * set up for 8-bits of R/G/B, or 3 bytes total.
858 */
858fa035 859 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 860 mode->clock, adjusted_mode->clock, &m_n);
861
1eb8dfec 862 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 863 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
864 TU_SIZE(m_n.tu) | m_n.gmch_m);
865 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
866 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
867 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 868 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 869 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 870 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
871 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
872 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 873 } else if (IS_VALLEYVIEW(dev)) {
874 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
875 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
876 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
877 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 878 } else {
9db4a9c7 879 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 880 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 881 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
882 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
883 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 884 }
885}
886
247d89f6
PZ		 887void intel_dp_init_link_config(struct intel_dp *intel_dp)
888{
889 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
890 intel_dp->link_configuration[0] = intel_dp->link_bw;
891 intel_dp->link_configuration[1] = intel_dp->lane_count;
892 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
893 /*
894 * Check for DPCD version > 1.1 and enhanced framing support
895 */
896 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
897 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
898 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
899 }
900}
901
a4fc5ed6
KP		 902static void
903intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
904 struct drm_display_mode *adjusted_mode)
905{
e3421a18 906 struct drm_device *dev = encoder->dev;
417e822d 907 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 908 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 909 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
911
417e822d 912 /*
1a2eb460 913 * There are four kinds of DP registers:
417e822d
KP		 914 *
915 * IBX PCH
1a2eb460
KP		 916 * SNB CPU
917 * IVB CPU
417e822d
KP		 918 * CPT PCH
919 *
920 * IBX PCH and CPU are the same for almost everything,
921 * except that the CPU DP PLL is configured in this
922 * register
923 *
924 * CPT PCH is quite different, having many bits moved
925 * to the TRANS_DP_CTL register instead. That
926 * configuration happens (oddly) in ironlake_pch_enable
927 */
9c9e7927 928
417e822d
KP		 929 /* Preserve the BIOS-computed detected bit. This is
930 * supposed to be read-only.
931 */
932 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 933
417e822d 934 /* Handle DP bits in common between all three register formats */
417e822d 935 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 936
ea5b213a 937 switch (intel_dp->lane_count) {
a4fc5ed6 938 case 1:
ea5b213a 939 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 940 break;
941 case 2:
ea5b213a 942 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 943 break;
944 case 4:
ea5b213a 945 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 946 break;
947 }
e0dac65e
WF		 948 if (intel_dp->has_audio) {
949 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
950 pipe_name(intel_crtc->pipe));
ea5b213a 951 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 952 intel_write_eld(encoder, adjusted_mode);
953 }
247d89f6
PZ		 954
955 intel_dp_init_link_config(intel_dp);
a4fc5ed6 956
417e822d 957 /* Split out the IBX/CPU vs CPT settings */
32f9d658 958
19c03924 959 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 960 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
961 intel_dp->DP |= DP_SYNC_HS_HIGH;
962 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
963 intel_dp->DP |= DP_SYNC_VS_HIGH;
964 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
965
966 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
967 intel_dp->DP |= DP_ENHANCED_FRAMING;
968
969 intel_dp->DP |= intel_crtc->pipe << 29;
970
971 /* don't miss out required setting for eDP */
1a2eb460
KP		 972 if (adjusted_mode->clock < 200000)
973 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
974 else
975 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
976 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 977 intel_dp->DP |= intel_dp->color_range;
978
979 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
980 intel_dp->DP |= DP_SYNC_HS_HIGH;
981 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
982 intel_dp->DP |= DP_SYNC_VS_HIGH;
983 intel_dp->DP |= DP_LINK_TRAIN_OFF;
984
985 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
986 intel_dp->DP |= DP_ENHANCED_FRAMING;
987
988 if (intel_crtc->pipe == 1)
989 intel_dp->DP |= DP_PIPEB_SELECT;
990
991 if (is_cpu_edp(intel_dp)) {
992 /* don't miss out required setting for eDP */
417e822d
KP		 993 if (adjusted_mode->clock < 200000)
994 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
995 else
996 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
997 }
998 } else {
999 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1000 }
a4fc5ed6
KP		 1001}
1002
99ea7127
KP		 1003#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1004#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1005
1006#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1007#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1008
1009#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1010#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1011
1012static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1013 u32 mask,
1014 u32 value)
bd943159 1015{
30add22d 1016 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1017 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 1018
99ea7127
KP		 1019 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1020 mask, value,
1021 I915_READ(PCH_PP_STATUS),
1022 I915_READ(PCH_PP_CONTROL));
32ce697c 1023
99ea7127
KP		 1024 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1025 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1026 I915_READ(PCH_PP_STATUS),
1027 I915_READ(PCH_PP_CONTROL));
32ce697c 1028 }
99ea7127 1029}
32ce697c 1030
99ea7127
KP		 1031static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1032{
1033 DRM_DEBUG_KMS("Wait for panel power on\n");
1034 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1035}
1036
99ea7127
KP		 1037static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1038{
1039 DRM_DEBUG_KMS("Wait for panel power off time\n");
1040 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1041}
1042
1043static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1044{
1045 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1046 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1047}
1048
1049
832dd3c1
KP		 1050/* Read the current pp_control value, unlocking the register if it
1051 * is locked
1052 */
1053
1054static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1055{
1056 u32 control = I915_READ(PCH_PP_CONTROL);
1057
1058 control &= ~PANEL_UNLOCK_MASK;
1059 control |= PANEL_UNLOCK_REGS;
1060 return control;
bd943159
KP		 1061}
1062
82a4d9c0 1063void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1064{
30add22d 1065 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 u32 pp;
1068
97af61f5
KP		 1069 if (!is_edp(intel_dp))
1070 return;
f01eca2e 1071 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1072
bd943159
KP		 1073 WARN(intel_dp->want_panel_vdd,
1074 "eDP VDD already requested on\n");
1075
1076 intel_dp->want_panel_vdd = true;
99ea7127 1077
bd943159
KP		 1078 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1079 DRM_DEBUG_KMS("eDP VDD already on\n");
1080 return;
1081 }
1082
99ea7127
KP		 1083 if (!ironlake_edp_have_panel_power(intel_dp))
1084 ironlake_wait_panel_power_cycle(intel_dp);
1085
832dd3c1 1086 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1087 pp |= EDP_FORCE_VDD;
1088 I915_WRITE(PCH_PP_CONTROL, pp);
1089 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1090 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1091 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1092
1093 /*
1094 * If the panel wasn't on, delay before accessing aux channel
1095 */
1096 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1097 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1098 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1099 }
5d613501
JB		 1100}
1101
bd943159 1102static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1103{
30add22d 1104 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1105 struct drm_i915_private *dev_priv = dev->dev_private;
1106 u32 pp;
1107
bd943159 1108 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1109 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1110 pp &= ~EDP_FORCE_VDD;
1111 I915_WRITE(PCH_PP_CONTROL, pp);
1112 POSTING_READ(PCH_PP_CONTROL);
1113
1114 /* Make sure sequencer is idle before allowing subsequent activity */
1115 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1116 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1117
1118 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1119 }
1120}
5d613501 1121
bd943159
KP		 1122static void ironlake_panel_vdd_work(struct work_struct *__work)
1123{
1124 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1125 struct intel_dp, panel_vdd_work);
30add22d 1126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1127
627f7675 1128 mutex_lock(&dev->mode_config.mutex);
bd943159 1129 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1130 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1131}
1132
82a4d9c0 1133void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1134{
97af61f5
KP		 1135 if (!is_edp(intel_dp))
1136 return;
5d613501 1137
bd943159
KP		 1138 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1139 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1140
bd943159
KP		 1141 intel_dp->want_panel_vdd = false;
1142
1143 if (sync) {
1144 ironlake_panel_vdd_off_sync(intel_dp);
1145 } else {
1146 /*
1147 * Queue the timer to fire a long
1148 * time from now (relative to the power down delay)
1149 * to keep the panel power up across a sequence of operations
1150 */
1151 schedule_delayed_work(&intel_dp->panel_vdd_work,
1152 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1153 }
5d613501
JB		 1154}
1155
82a4d9c0 1156void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1157{
30add22d 1158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1159 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1160 u32 pp;
9934c132 1161
97af61f5 1162 if (!is_edp(intel_dp))
bd943159 1163 return;
99ea7127
KP		 1164
1165 DRM_DEBUG_KMS("Turn eDP power on\n");
1166
1167 if (ironlake_edp_have_panel_power(intel_dp)) {
1168 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1169 return;
99ea7127 1170 }
9934c132 1171
99ea7127 1172 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1173
99ea7127 1174 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1175 if (IS_GEN5(dev)) {
1176 /* ILK workaround: disable reset around power sequence */
1177 pp &= ~PANEL_POWER_RESET;
1178 I915_WRITE(PCH_PP_CONTROL, pp);
1179 POSTING_READ(PCH_PP_CONTROL);
1180 }
37c6c9b0 1181
1c0ae80a 1182 pp |= POWER_TARGET_ON;
99ea7127
KP		 1183 if (!IS_GEN5(dev))
1184 pp |= PANEL_POWER_RESET;
1185
9934c132 1186 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1187 POSTING_READ(PCH_PP_CONTROL);
9934c132 1188
99ea7127 1189 ironlake_wait_panel_on(intel_dp);
9934c132 1190
05ce1a49
KP		 1191 if (IS_GEN5(dev)) {
1192 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1193 I915_WRITE(PCH_PP_CONTROL, pp);
1194 POSTING_READ(PCH_PP_CONTROL);
1195 }
9934c132
JB		 1196}
1197
82a4d9c0 1198void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1199{
30add22d 1200 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1201 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1202 u32 pp;
9934c132 1203
97af61f5
KP		 1204 if (!is_edp(intel_dp))
1205 return;
37c6c9b0 1206
99ea7127 1207 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1208
6cb49835 1209 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1210
99ea7127 1211 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1212 /* We need to switch off panel power _and_ force vdd, for otherwise some
1213 * panels get very unhappy and cease to work. */
1214 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1215 I915_WRITE(PCH_PP_CONTROL, pp);
1216 POSTING_READ(PCH_PP_CONTROL);
9934c132 1217
35a38556
DV		 1218 intel_dp->want_panel_vdd = false;
1219
99ea7127 1220 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1221}
1222
d6c50ff8 1223void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1224{
da63a9f2
PZ		 1225 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1226 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1227 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1228 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1229 u32 pp;
1230
f01eca2e
KP		 1231 if (!is_edp(intel_dp))
1232 return;
1233
28c97730 1234 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1235 /*
1236 * If we enable the backlight right away following a panel power
1237 * on, we may see slight flicker as the panel syncs with the eDP
1238 * link. So delay a bit to make sure the image is solid before
1239 * allowing it to appear.
1240 */
f01eca2e 1241 msleep(intel_dp->backlight_on_delay);
832dd3c1 1242 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1243 pp |= EDP_BLC_ENABLE;
1244 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1245 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1246
1247 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1248}
1249
d6c50ff8 1250void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1251{
30add22d 1252 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254 u32 pp;
1255
f01eca2e
KP		 1256 if (!is_edp(intel_dp))
1257 return;
1258
035aa3de
DV		 1259 intel_panel_disable_backlight(dev);
1260
28c97730 1261 DRM_DEBUG_KMS("\n");
832dd3c1 1262 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1263 pp &= ~EDP_BLC_ENABLE;
1264 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1265 POSTING_READ(PCH_PP_CONTROL);
1266 msleep(intel_dp->backlight_off_delay);
32f9d658 1267}
a4fc5ed6 1268
2bd2ad64 1269static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1270{
da63a9f2
PZ		 1271 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1272 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1273 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 u32 dpa_ctl;
1276
2bd2ad64
DV		 1277 assert_pipe_disabled(dev_priv,
1278 to_intel_crtc(crtc)->pipe);
1279
d240f20f
JB		 1280 DRM_DEBUG_KMS("\n");
1281 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1282 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1283 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1284
1285 /* We don't adjust intel_dp->DP while tearing down the link, to
1286 * facilitate link retraining (e.g. after hotplug). Hence clear all
1287 * enable bits here to ensure that we don't enable too much. */
1288 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1289 intel_dp->DP |= DP_PLL_ENABLE;
1290 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1291 POSTING_READ(DP_A);
1292 udelay(200);
d240f20f
JB		 1293}
1294
2bd2ad64 1295static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1296{
da63a9f2
PZ		 1297 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1298 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1299 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1300 struct drm_i915_private *dev_priv = dev->dev_private;
1301 u32 dpa_ctl;
1302
2bd2ad64
DV		 1303 assert_pipe_disabled(dev_priv,
1304 to_intel_crtc(crtc)->pipe);
1305
d240f20f 1306 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1307 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1308 "dp pll off, should be on\n");
1309 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1310
1311 /* We can't rely on the value tracked for the DP register in
1312 * intel_dp->DP because link_down must not change that (otherwise link
1313 * re-training will fail. */
298b0b39 1314 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1315 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1316 POSTING_READ(DP_A);
d240f20f
JB		 1317 udelay(200);
1318}
1319
c7ad3810 1320/* If the sink supports it, try to set the power state appropriately */
c19b0669 1321void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1322{
1323 int ret, i;
1324
1325 /* Should have a valid DPCD by this point */
1326 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1327 return;
1328
1329 if (mode != DRM_MODE_DPMS_ON) {
1330 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1331 DP_SET_POWER_D3);
1332 if (ret != 1)
1333 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1334 } else {
1335 /*
1336 * When turning on, we need to retry for 1ms to give the sink
1337 * time to wake up.
1338 */
1339 for (i = 0; i < 3; i++) {
1340 ret = intel_dp_aux_native_write_1(intel_dp,
1341 DP_SET_POWER,
1342 DP_SET_POWER_D0);
1343 if (ret == 1)
1344 break;
1345 msleep(1);
1346 }
1347 }
1348}
1349
19d8fe15
DV		 1350static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1351 enum pipe *pipe)
d240f20f 1352{
19d8fe15
DV		 1353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1354 struct drm_device *dev = encoder->base.dev;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 u32 tmp = I915_READ(intel_dp->output_reg);
1357
1358 if (!(tmp & DP_PORT_EN))
1359 return false;
1360
1361 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1362 *pipe = PORT_TO_PIPE_CPT(tmp);
1363 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1364 *pipe = PORT_TO_PIPE(tmp);
1365 } else {
1366 u32 trans_sel;
1367 u32 trans_dp;
1368 int i;
1369
1370 switch (intel_dp->output_reg) {
1371 case PCH_DP_B:
1372 trans_sel = TRANS_DP_PORT_SEL_B;
1373 break;
1374 case PCH_DP_C:
1375 trans_sel = TRANS_DP_PORT_SEL_C;
1376 break;
1377 case PCH_DP_D:
1378 trans_sel = TRANS_DP_PORT_SEL_D;
1379 break;
1380 default:
1381 return true;
1382 }
1383
1384 for_each_pipe(i) {
1385 trans_dp = I915_READ(TRANS_DP_CTL(i));
1386 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1387 *pipe = i;
1388 return true;
1389 }
1390 }
19d8fe15 1391
4a0833ec
DV		 1392 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1393 intel_dp->output_reg);
1394 }
d240f20f 1395
19d8fe15
DV		 1396 return true;
1397}
d240f20f 1398
e8cb4558 1399static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1400{
e8cb4558 1401 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1402
1403 /* Make sure the panel is off before trying to change the mode. But also
1404 * ensure that we have vdd while we switch off the panel. */
1405 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1406 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1407 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1408 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1409
1410 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1411 if (!is_cpu_edp(intel_dp))
1412 intel_dp_link_down(intel_dp);
d240f20f
JB		 1413}
1414
2bd2ad64 1415static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1416{
2bd2ad64
DV		 1417 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1418
3739850b
DV		 1419 if (is_cpu_edp(intel_dp)) {
1420 intel_dp_link_down(intel_dp);
2bd2ad64 1421 ironlake_edp_pll_off(intel_dp);
3739850b 1422 }
2bd2ad64
DV		 1423}
1424
e8cb4558 1425static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1426{
e8cb4558
DV		 1427 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1428 struct drm_device *dev = encoder->base.dev;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1431
0c33d8d7
DV		 1432 if (WARN_ON(dp_reg & DP_PORT_EN))
1433 return;
5d613501 1434
97af61f5 1435 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1436 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1437 intel_dp_start_link_train(intel_dp);
97af61f5 1438 ironlake_edp_panel_on(intel_dp);
bd943159 1439 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1440 intel_dp_complete_link_train(intel_dp);
f01eca2e 1441 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1442}
1443
2bd2ad64 1444static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1445{
2bd2ad64 1446 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 1447
2bd2ad64
DV		 1448 if (is_cpu_edp(intel_dp))
1449 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1450}
1451
1452/*
df0c237d
JB		 1453 * Native read with retry for link status and receiver capability reads for
1454 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1455 */
1456static bool
df0c237d
JB		 1457intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1458 uint8_t *recv, int recv_bytes)
a4fc5ed6 1459{
61da5fab
JB		 1460 int ret, i;
1461
df0c237d
JB		 1462 /*
1463 * Sinks are *supposed* to come up within 1ms from an off state,
1464 * but we're also supposed to retry 3 times per the spec.
1465 */
61da5fab 1466 for (i = 0; i < 3; i++) {
df0c237d
JB		 1467 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1468 recv_bytes);
1469 if (ret == recv_bytes)
61da5fab
JB		 1470 return true;
1471 msleep(1);
1472 }
a4fc5ed6 1473
61da5fab 1474 return false;
a4fc5ed6
KP		 1475}
1476
1477/*
1478 * Fetch AUX CH registers 0x202 - 0x207 which contain
1479 * link status information
1480 */
1481static bool
93f62dad 1482intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1483{
df0c237d
JB		 1484 return intel_dp_aux_native_read_retry(intel_dp,
1485 DP_LANE0_1_STATUS,
93f62dad 1486 link_status,
df0c237d 1487 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1488}
1489
a4fc5ed6
KP		 1490#if 0
1491static char *voltage_names[] = {
1492 "0.4V", "0.6V", "0.8V", "1.2V"
1493};
1494static char *pre_emph_names[] = {
1495 "0dB", "3.5dB", "6dB", "9.5dB"
1496};
1497static char *link_train_names[] = {
1498 "pattern 1", "pattern 2", "idle", "off"
1499};
1500#endif
1501
1502/*
1503 * These are source-specific values; current Intel hardware supports
1504 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1505 */
a4fc5ed6
KP		 1506
1507static uint8_t
1a2eb460 1508intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1509{
30add22d 1510 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1511
1512 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1513 return DP_TRAIN_VOLTAGE_SWING_800;
1514 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1515 return DP_TRAIN_VOLTAGE_SWING_1200;
1516 else
1517 return DP_TRAIN_VOLTAGE_SWING_800;
1518}
1519
1520static uint8_t
1521intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1522{
30add22d 1523 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1524
d6c0d722
PZ		 1525 if (IS_HASWELL(dev)) {
1526 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1527 case DP_TRAIN_VOLTAGE_SWING_400:
1528 return DP_TRAIN_PRE_EMPHASIS_9_5;
1529 case DP_TRAIN_VOLTAGE_SWING_600:
1530 return DP_TRAIN_PRE_EMPHASIS_6;
1531 case DP_TRAIN_VOLTAGE_SWING_800:
1532 return DP_TRAIN_PRE_EMPHASIS_3_5;
1533 case DP_TRAIN_VOLTAGE_SWING_1200:
1534 default:
1535 return DP_TRAIN_PRE_EMPHASIS_0;
1536 }
1537 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1538 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1539 case DP_TRAIN_VOLTAGE_SWING_400:
1540 return DP_TRAIN_PRE_EMPHASIS_6;
1541 case DP_TRAIN_VOLTAGE_SWING_600:
1542 case DP_TRAIN_VOLTAGE_SWING_800:
1543 return DP_TRAIN_PRE_EMPHASIS_3_5;
1544 default:
1545 return DP_TRAIN_PRE_EMPHASIS_0;
1546 }
1547 } else {
1548 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1549 case DP_TRAIN_VOLTAGE_SWING_400:
1550 return DP_TRAIN_PRE_EMPHASIS_6;
1551 case DP_TRAIN_VOLTAGE_SWING_600:
1552 return DP_TRAIN_PRE_EMPHASIS_6;
1553 case DP_TRAIN_VOLTAGE_SWING_800:
1554 return DP_TRAIN_PRE_EMPHASIS_3_5;
1555 case DP_TRAIN_VOLTAGE_SWING_1200:
1556 default:
1557 return DP_TRAIN_PRE_EMPHASIS_0;
1558 }
a4fc5ed6
KP		 1559 }
1560}
1561
1562static void
93f62dad 1563intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1564{
1565 uint8_t v = 0;
1566 uint8_t p = 0;
1567 int lane;
1a2eb460
KP		 1568 uint8_t voltage_max;
1569 uint8_t preemph_max;
a4fc5ed6 1570
33a34e4e 1571 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1572 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1573 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1574
1575 if (this_v > v)
1576 v = this_v;
1577 if (this_p > p)
1578 p = this_p;
1579 }
1580
1a2eb460 1581 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1582 if (v >= voltage_max)
1583 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1584
1a2eb460
KP		 1585 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1586 if (p >= preemph_max)
1587 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1588
1589 for (lane = 0; lane < 4; lane++)
33a34e4e 1590 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1591}
1592
1593static uint32_t
93f62dad 1594intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1595{
3cf2efb1 1596 uint32_t signal_levels = 0;
a4fc5ed6 1597
3cf2efb1 1598 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1599 case DP_TRAIN_VOLTAGE_SWING_400:
1600 default:
1601 signal_levels |= DP_VOLTAGE_0_4;
1602 break;
1603 case DP_TRAIN_VOLTAGE_SWING_600:
1604 signal_levels |= DP_VOLTAGE_0_6;
1605 break;
1606 case DP_TRAIN_VOLTAGE_SWING_800:
1607 signal_levels |= DP_VOLTAGE_0_8;
1608 break;
1609 case DP_TRAIN_VOLTAGE_SWING_1200:
1610 signal_levels |= DP_VOLTAGE_1_2;
1611 break;
1612 }
3cf2efb1 1613 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1614 case DP_TRAIN_PRE_EMPHASIS_0:
1615 default:
1616 signal_levels |= DP_PRE_EMPHASIS_0;
1617 break;
1618 case DP_TRAIN_PRE_EMPHASIS_3_5:
1619 signal_levels |= DP_PRE_EMPHASIS_3_5;
1620 break;
1621 case DP_TRAIN_PRE_EMPHASIS_6:
1622 signal_levels |= DP_PRE_EMPHASIS_6;
1623 break;
1624 case DP_TRAIN_PRE_EMPHASIS_9_5:
1625 signal_levels |= DP_PRE_EMPHASIS_9_5;
1626 break;
1627 }
1628 return signal_levels;
1629}
1630
e3421a18
ZW		 1631/* Gen6's DP voltage swing and pre-emphasis control */
1632static uint32_t
1633intel_gen6_edp_signal_levels(uint8_t train_set)
1634{
3c5a62b5
YL		 1635 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1636 DP_TRAIN_PRE_EMPHASIS_MASK);
1637 switch (signal_levels) {
e3421a18 1638 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1639 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1640 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1641 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1642 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1643 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1644 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1645 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1646 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1647 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1648 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1649 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1650 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1651 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1652 default:
3c5a62b5
YL		 1653 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1654 "0x%x\n", signal_levels);
1655 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1656 }
1657}
1658
1a2eb460
KP		 1659/* Gen7's DP voltage swing and pre-emphasis control */
1660static uint32_t
1661intel_gen7_edp_signal_levels(uint8_t train_set)
1662{
1663 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1664 DP_TRAIN_PRE_EMPHASIS_MASK);
1665 switch (signal_levels) {
1666 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1667 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1668 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1669 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1670 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1671 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1672
1673 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1674 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1675 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1676 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1677
1678 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1679 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1680 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1681 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1682
1683 default:
1684 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1685 "0x%x\n", signal_levels);
1686 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1687 }
1688}
1689
d6c0d722
PZ		 1690/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1691static uint32_t
1692intel_dp_signal_levels_hsw(uint8_t train_set)
a4fc5ed6 1693{
d6c0d722
PZ		 1694 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1695 DP_TRAIN_PRE_EMPHASIS_MASK);
1696 switch (signal_levels) {
1697 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1698 return DDI_BUF_EMP_400MV_0DB_HSW;
1699 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1700 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1701 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1702 return DDI_BUF_EMP_400MV_6DB_HSW;
1703 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1704 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1705
d6c0d722
PZ		 1706 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1707 return DDI_BUF_EMP_600MV_0DB_HSW;
1708 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1709 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1710 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1711 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1712
d6c0d722
PZ		 1713 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1714 return DDI_BUF_EMP_800MV_0DB_HSW;
1715 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1716 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1717 default:
1718 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1719 "0x%x\n", signal_levels);
1720 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1721 }
a4fc5ed6
KP		 1722}
1723
1724static bool
ea5b213a 1725intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1726 uint32_t dp_reg_value,
58e10eb9 1727 uint8_t dp_train_pat)
a4fc5ed6 1728{
174edf1f
PZ		 1729 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1730 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1731 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1732 enum port port = intel_dig_port->port;
a4fc5ed6 1733 int ret;
d6c0d722 1734 uint32_t temp;
a4fc5ed6 1735
d6c0d722 1736 if (IS_HASWELL(dev)) {
174edf1f 1737 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1738
1739 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1740 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1741 else
1742 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1743
1744 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1745 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1746 case DP_TRAINING_PATTERN_DISABLE:
1747 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
174edf1f 1748 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1749
174edf1f 1750 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
d6c0d722
PZ		 1751 DP_TP_STATUS_IDLE_DONE), 1))
1752 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1753
1754 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1755 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1756
1757 break;
1758 case DP_TRAINING_PATTERN_1:
1759 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1760 break;
1761 case DP_TRAINING_PATTERN_2:
1762 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1763 break;
1764 case DP_TRAINING_PATTERN_3:
1765 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1766 break;
1767 }
174edf1f 1768 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1769
1770 } else if (HAS_PCH_CPT(dev) &&
1771 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1772 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1773
1774 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1775 case DP_TRAINING_PATTERN_DISABLE:
1776 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1777 break;
1778 case DP_TRAINING_PATTERN_1:
1779 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1780 break;
1781 case DP_TRAINING_PATTERN_2:
1782 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1783 break;
1784 case DP_TRAINING_PATTERN_3:
1785 DRM_ERROR("DP training pattern 3 not supported\n");
1786 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1787 break;
1788 }
1789
1790 } else {
1791 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1792
1793 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1794 case DP_TRAINING_PATTERN_DISABLE:
1795 dp_reg_value |= DP_LINK_TRAIN_OFF;
1796 break;
1797 case DP_TRAINING_PATTERN_1:
1798 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1799 break;
1800 case DP_TRAINING_PATTERN_2:
1801 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1802 break;
1803 case DP_TRAINING_PATTERN_3:
1804 DRM_ERROR("DP training pattern 3 not supported\n");
1805 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1806 break;
1807 }
1808 }
1809
ea5b213a
CW		 1810 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1811 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1812
ea5b213a 1813 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1814 DP_TRAINING_PATTERN_SET,
1815 dp_train_pat);
1816
47ea7542
PZ		 1817 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1818 DP_TRAINING_PATTERN_DISABLE) {
1819 ret = intel_dp_aux_native_write(intel_dp,
1820 DP_TRAINING_LANE0_SET,
1821 intel_dp->train_set,
1822 intel_dp->lane_count);
1823 if (ret != intel_dp->lane_count)
1824 return false;
1825 }
a4fc5ed6
KP		 1826
1827 return true;
1828}
1829
33a34e4e 1830/* Enable corresponding port and start training pattern 1 */
c19b0669 1831void
33a34e4e 1832intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1833{
da63a9f2 1834 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1835 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1836 int i;
1837 uint8_t voltage;
1838 bool clock_recovery = false;
cdb0e95b 1839 int voltage_tries, loop_tries;
ea5b213a 1840 uint32_t DP = intel_dp->DP;
a4fc5ed6 1841
affa9354 1842 if (HAS_DDI(dev))
c19b0669
PZ		 1843 intel_ddi_prepare_link_retrain(encoder);
1844
3cf2efb1
CW		 1845 /* Write the link configuration data */
1846 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1847 intel_dp->link_configuration,
1848 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1849
1850 DP |= DP_PORT_EN;
1a2eb460 1851
33a34e4e 1852 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1853 voltage = 0xff;
cdb0e95b
KP		 1854 voltage_tries = 0;
1855 loop_tries = 0;
a4fc5ed6
KP		 1856 clock_recovery = false;
1857 for (;;) {
33a34e4e 1858 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1859 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1860 uint32_t signal_levels;
417e822d 1861
d6c0d722
PZ		 1862 if (IS_HASWELL(dev)) {
1863 signal_levels = intel_dp_signal_levels_hsw(
1864 intel_dp->train_set[0]);
1865 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1866 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1867 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1868 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1869 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1870 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1871 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1872 } else {
93f62dad 1873 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1874 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1875 }
d6c0d722
PZ		 1876 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1877 signal_levels);
a4fc5ed6 1878
a7c9655f 1879 /* Set training pattern 1 */
47ea7542 1880 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1881 DP_TRAINING_PATTERN_1 |
1882 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1883 break;
a4fc5ed6 1884
a7c9655f 1885 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1886 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1887 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1888 break;
93f62dad 1889 }
a4fc5ed6 1890
01916270 1891 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1892 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1893 clock_recovery = true;
1894 break;
1895 }
1896
1897 /* Check to see if we've tried the max voltage */
1898 for (i = 0; i < intel_dp->lane_count; i++)
1899 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1900 break;
0d710688 1901 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1902 ++loop_tries;
1903 if (loop_tries == 5) {
cdb0e95b
KP		 1904 DRM_DEBUG_KMS("too many full retries, give up\n");
1905 break;
1906 }
1907 memset(intel_dp->train_set, 0, 4);
1908 voltage_tries = 0;
1909 continue;
1910 }
a4fc5ed6 1911
3cf2efb1 1912 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1913 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1914 ++voltage_tries;
b06fbda3
DV		 1915 if (voltage_tries == 5) {
1916 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1917 break;
1918 }
1919 } else
1920 voltage_tries = 0;
1921 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1922
3cf2efb1 1923 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1924 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1925 }
1926
33a34e4e
JB		 1927 intel_dp->DP = DP;
1928}
1929
c19b0669 1930void
33a34e4e
JB		 1931intel_dp_complete_link_train(struct intel_dp *intel_dp)
1932{
30add22d 1933 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33a34e4e 1934 bool channel_eq = false;
37f80975 1935 int tries, cr_tries;
33a34e4e
JB		 1936 uint32_t DP = intel_dp->DP;
1937
a4fc5ed6
KP		 1938 /* channel equalization */
1939 tries = 0;
37f80975 1940 cr_tries = 0;
a4fc5ed6
KP		 1941 channel_eq = false;
1942 for (;;) {
33a34e4e 1943 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1944 uint32_t signal_levels;
93f62dad 1945 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1946
37f80975
JB		 1947 if (cr_tries > 5) {
1948 DRM_ERROR("failed to train DP, aborting\n");
1949 intel_dp_link_down(intel_dp);
1950 break;
1951 }
1952
d6c0d722
PZ		 1953 if (IS_HASWELL(dev)) {
1954 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1955 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1956 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1957 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1958 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1959 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1960 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1961 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1962 } else {
93f62dad 1963 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1964 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1965 }
1966
a4fc5ed6 1967 /* channel eq pattern */
47ea7542 1968 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1969 DP_TRAINING_PATTERN_2 |
1970 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1971 break;
1972
a7c9655f 1973 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1974 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1975 break;
a4fc5ed6 1976
37f80975 1977 /* Make sure clock is still ok */
01916270 1978 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1979 intel_dp_start_link_train(intel_dp);
1980 cr_tries++;
1981 continue;
1982 }
1983
1ffdff13 1984 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1985 channel_eq = true;
1986 break;
1987 }
a4fc5ed6 1988
37f80975
JB		 1989 /* Try 5 times, then try clock recovery if that fails */
1990 if (tries > 5) {
1991 intel_dp_link_down(intel_dp);
1992 intel_dp_start_link_train(intel_dp);
1993 tries = 0;
1994 cr_tries++;
1995 continue;
1996 }
a4fc5ed6 1997
3cf2efb1 1998 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1999 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2000 ++tries;
869184a6 2001 }
3cf2efb1 2002
d6c0d722
PZ		 2003 if (channel_eq)
2004 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2005
47ea7542 2006 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2007}
2008
2009static void
ea5b213a 2010intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2011{
da63a9f2
PZ		 2012 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2013 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2014 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 2015 uint32_t DP = intel_dp->DP;
a4fc5ed6 2016
c19b0669
PZ		 2017 /*
2018 * DDI code has a strict mode set sequence and we should try to respect
2019 * it, otherwise we might hang the machine in many different ways. So we
2020 * really should be disabling the port only on a complete crtc_disable
2021 * sequence. This function is just called under two conditions on DDI
2022 * code:
2023 * - Link train failed while doing crtc_enable, and on this case we
2024 * really should respect the mode set sequence and wait for a
2025 * crtc_disable.
2026 * - Someone turned the monitor off and intel_dp_check_link_status
2027 * called us. We don't need to disable the whole port on this case, so
2028 * when someone turns the monitor on again,
2029 * intel_ddi_prepare_link_retrain will take care of redoing the link
2030 * train.
2031 */
affa9354 2032 if (HAS_DDI(dev))
c19b0669
PZ		 2033 return;
2034
0c33d8d7 2035 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2036 return;
2037
28c97730 2038 DRM_DEBUG_KMS("\n");
32f9d658 2039
1a2eb460 2040 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2041 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2042 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2043 } else {
2044 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2045 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2046 }
fe255d00 2047 POSTING_READ(intel_dp->output_reg);
5eb08b69 2048
fe255d00 2049 msleep(17);
5eb08b69 2050
493a7081 2051 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2052 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2053 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2054
5bddd17f
EA		 2055 /* Hardware workaround: leaving our transcoder select
2056 * set to transcoder B while it's off will prevent the
2057 * corresponding HDMI output on transcoder A.
2058 *
2059 * Combine this with another hardware workaround:
2060 * transcoder select bit can only be cleared while the
2061 * port is enabled.
2062 */
2063 DP &= ~DP_PIPEB_SELECT;
2064 I915_WRITE(intel_dp->output_reg, DP);
2065
2066 /* Changes to enable or select take place the vblank
2067 * after being written.
2068 */
31acbcc4
CW		 2069 if (crtc == NULL) {
2070 /* We can arrive here never having been attached
2071 * to a CRTC, for instance, due to inheriting
2072 * random state from the BIOS.
2073 *
2074 * If the pipe is not running, play safe and
2075 * wait for the clocks to stabilise before
2076 * continuing.
2077 */
2078 POSTING_READ(intel_dp->output_reg);
2079 msleep(50);
2080 } else
2081 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2082 }
2083
832afda6 2084 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2085 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2086 POSTING_READ(intel_dp->output_reg);
f01eca2e 2087 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2088}
2089
26d61aad
KP		 2090static bool
2091intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2092{
92fd8fd1 2093 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2094 sizeof(intel_dp->dpcd)) == 0)
2095 return false; /* aux transfer failed */
92fd8fd1 2096
edb39244
AJ		 2097 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2098 return false; /* DPCD not present */
2099
2100 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2101 DP_DWN_STRM_PORT_PRESENT))
2102 return true; /* native DP sink */
2103
2104 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2105 return true; /* no per-port downstream info */
2106
2107 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2108 intel_dp->downstream_ports,
2109 DP_MAX_DOWNSTREAM_PORTS) == 0)
2110 return false; /* downstream port status fetch failed */
2111
2112 return true;
92fd8fd1
KP		 2113}
2114
0d198328
AJ		 2115static void
2116intel_dp_probe_oui(struct intel_dp *intel_dp)
2117{
2118 u8 buf[3];
2119
2120 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2121 return;
2122
351cfc34
DV		 2123 ironlake_edp_panel_vdd_on(intel_dp);
2124
0d198328
AJ		 2125 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2126 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2127 buf[0], buf[1], buf[2]);
2128
2129 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2130 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2131 buf[0], buf[1], buf[2]);
351cfc34
DV		 2132
2133 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2134}
2135
a60f0e38
JB		 2136static bool
2137intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2138{
2139 int ret;
2140
2141 ret = intel_dp_aux_native_read_retry(intel_dp,
2142 DP_DEVICE_SERVICE_IRQ_VECTOR,
2143 sink_irq_vector, 1);
2144 if (!ret)
2145 return false;
2146
2147 return true;
2148}
2149
2150static void
2151intel_dp_handle_test_request(struct intel_dp *intel_dp)
2152{
2153 /* NAK by default */
9324cf7f 2154 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2155}
2156
a4fc5ed6
KP		 2157/*
2158 * According to DP spec
2159 * 5.1.2:
2160 * 1. Read DPCD
2161 * 2. Configure link according to Receiver Capabilities
2162 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2163 * 4. Check link status on receipt of hot-plug interrupt
2164 */
2165
00c09d70 2166void
ea5b213a 2167intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2168{
da63a9f2 2169 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2170 u8 sink_irq_vector;
93f62dad 2171 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2172
da63a9f2 2173 if (!intel_encoder->connectors_active)
d2b996ac 2174 return;
59cd09e1 2175
da63a9f2 2176 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2177 return;
2178
92fd8fd1 2179 /* Try to read receiver status if the link appears to be up */
93f62dad 2180 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2181 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2182 return;
2183 }
2184
92fd8fd1 2185 /* Now read the DPCD to see if it's actually running */
26d61aad 2186 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2187 intel_dp_link_down(intel_dp);
2188 return;
2189 }
2190
a60f0e38
JB		 2191 /* Try to read the source of the interrupt */
2192 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2193 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2194 /* Clear interrupt source */
2195 intel_dp_aux_native_write_1(intel_dp,
2196 DP_DEVICE_SERVICE_IRQ_VECTOR,
2197 sink_irq_vector);
2198
2199 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2200 intel_dp_handle_test_request(intel_dp);
2201 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2202 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2203 }
2204
1ffdff13 2205 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2206 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2207 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2208 intel_dp_start_link_train(intel_dp);
2209 intel_dp_complete_link_train(intel_dp);
2210 }
a4fc5ed6 2211}
a4fc5ed6 2212
caf9ab24 2213/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2214static enum drm_connector_status
26d61aad 2215intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2216{
caf9ab24
AJ		 2217 uint8_t *dpcd = intel_dp->dpcd;
2218 bool hpd;
2219 uint8_t type;
2220
2221 if (!intel_dp_get_dpcd(intel_dp))
2222 return connector_status_disconnected;
2223
2224 /* if there's no downstream port, we're done */
2225 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2226 return connector_status_connected;
caf9ab24
AJ		 2227
2228 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2229 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2230 if (hpd) {
23235177 2231 uint8_t reg;
caf9ab24 2232 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2233 &reg, 1))
caf9ab24 2234 return connector_status_unknown;
23235177
AJ		 2235 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2236 : connector_status_disconnected;
caf9ab24
AJ		 2237 }
2238
2239 /* If no HPD, poke DDC gently */
2240 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2241 return connector_status_connected;
caf9ab24
AJ		 2242
2243 /* Well we tried, say unknown for unreliable port types */
2244 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2245 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2246 return connector_status_unknown;
2247
2248 /* Anything else is out of spec, warn and ignore */
2249 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2250 return connector_status_disconnected;
71ba9000
AJ		 2251}
2252
5eb08b69 2253static enum drm_connector_status
a9756bb5 2254ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2255{
30add22d 2256 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5eb08b69
ZW		 2257 enum drm_connector_status status;
2258
fe16d949
CW		 2259 /* Can't disconnect eDP, but you can close the lid... */
2260 if (is_edp(intel_dp)) {
30add22d 2261 status = intel_panel_detect(dev);
fe16d949
CW		 2262 if (status == connector_status_unknown)
2263 status = connector_status_connected;
2264 return status;
2265 }
01cb9ea6 2266
26d61aad 2267 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2268}
2269
a4fc5ed6 2270static enum drm_connector_status
a9756bb5 2271g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2272{
30add22d 2273 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2274 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2275 uint32_t bit;
5eb08b69 2276
ea5b213a 2277 switch (intel_dp->output_reg) {
a4fc5ed6 2278 case DP_B:
10f76a38 2279 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2280 break;
2281 case DP_C:
10f76a38 2282 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2283 break;
2284 case DP_D:
10f76a38 2285 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2286 break;
2287 default:
2288 return connector_status_unknown;
2289 }
2290
10f76a38 2291 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2292 return connector_status_disconnected;
2293
26d61aad 2294 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2295}
2296
8c241fef
KP		 2297static struct edid *
2298intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2299{
9cd300e0 2300 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2301
9cd300e0
JN		 2302 /* use cached edid if we have one */
2303 if (intel_connector->edid) {
2304 struct edid *edid;
2305 int size;
2306
2307 /* invalid edid */
2308 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2309 return NULL;
2310
9cd300e0 2311 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2312 edid = kmalloc(size, GFP_KERNEL);
2313 if (!edid)
2314 return NULL;
2315
9cd300e0 2316 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2317 return edid;
2318 }
8c241fef 2319
9cd300e0 2320 return drm_get_edid(connector, adapter);
8c241fef
KP		 2321}
2322
2323static int
2324intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2325{
9cd300e0 2326 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2327
9cd300e0
JN		 2328 /* use cached edid if we have one */
2329 if (intel_connector->edid) {
2330 /* invalid edid */
2331 if (IS_ERR(intel_connector->edid))
2332 return 0;
2333
2334 return intel_connector_update_modes(connector,
2335 intel_connector->edid);
d6f24d0f
JB		 2336 }
2337
9cd300e0 2338 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2339}
2340
2341
a9756bb5
ZW		 2342/**
2343 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2344 *
2345 * \return true if DP port is connected.
2346 * \return false if DP port is disconnected.
2347 */
2348static enum drm_connector_status
2349intel_dp_detect(struct drm_connector *connector, bool force)
2350{
2351 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2352 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2353 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2354 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2355 enum drm_connector_status status;
2356 struct edid *edid = NULL;
898076ed 2357 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
a9756bb5
ZW		 2358
2359 intel_dp->has_audio = false;
2360
2361 if (HAS_PCH_SPLIT(dev))
2362 status = ironlake_dp_detect(intel_dp);
2363 else
2364 status = g4x_dp_detect(intel_dp);
1b9be9d0 2365
898076ed
JN		 2366 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2367 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2368 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
1b9be9d0 2369
a9756bb5
ZW		 2370 if (status != connector_status_connected)
2371 return status;
2372
0d198328
AJ		 2373 intel_dp_probe_oui(intel_dp);
2374
c3e5f67b
DV		 2375 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2376 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2377 } else {
8c241fef 2378 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2379 if (edid) {
2380 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2381 kfree(edid);
2382 }
a9756bb5
ZW		 2383 }
2384
d63885da
PZ		 2385 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2386 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2387 return connector_status_connected;
a4fc5ed6
KP		 2388}
2389
2390static int intel_dp_get_modes(struct drm_connector *connector)
2391{
df0e9248 2392 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2393 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2394 struct drm_device *dev = connector->dev;
32f9d658 2395 int ret;
a4fc5ed6
KP		 2396
2397 /* We should parse the EDID data and find out if it has an audio sink
2398 */
2399
8c241fef 2400 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2401 if (ret)
32f9d658
ZW		 2402 return ret;
2403
f8779fda 2404 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2405 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2406 struct drm_display_mode *mode;
dd06f90e
JN		 2407 mode = drm_mode_duplicate(dev,
2408 intel_connector->panel.fixed_mode);
f8779fda 2409 if (mode) {
32f9d658
ZW		 2410 drm_mode_probed_add(connector, mode);
2411 return 1;
2412 }
2413 }
2414 return 0;
a4fc5ed6
KP		 2415}
2416
1aad7ac0
CW		 2417static bool
2418intel_dp_detect_audio(struct drm_connector *connector)
2419{
2420 struct intel_dp *intel_dp = intel_attached_dp(connector);
2421 struct edid *edid;
2422 bool has_audio = false;
2423
8c241fef 2424 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2425 if (edid) {
2426 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2427 kfree(edid);
2428 }
2429
2430 return has_audio;
2431}
2432
f684960e
CW		 2433static int
2434intel_dp_set_property(struct drm_connector *connector,
2435 struct drm_property *property,
2436 uint64_t val)
2437{
e953fd7b 2438 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2439 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2440 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2441 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2442 int ret;
2443
662595df 2444 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2445 if (ret)
2446 return ret;
2447
3f43c48d 2448 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2449 int i = val;
2450 bool has_audio;
2451
2452 if (i == intel_dp->force_audio)
f684960e
CW		 2453 return 0;
2454
1aad7ac0 2455 intel_dp->force_audio = i;
f684960e 2456
c3e5f67b 2457 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2458 has_audio = intel_dp_detect_audio(connector);
2459 else
c3e5f67b 2460 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2461
2462 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2463 return 0;
2464
1aad7ac0 2465 intel_dp->has_audio = has_audio;
f684960e
CW		 2466 goto done;
2467 }
2468
e953fd7b
CW		 2469 if (property == dev_priv->broadcast_rgb_property) {
2470 if (val == !!intel_dp->color_range)
2471 return 0;
2472
2473 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2474 goto done;
2475 }
2476
53b41837
YN		 2477 if (is_edp(intel_dp) &&
2478 property == connector->dev->mode_config.scaling_mode_property) {
2479 if (val == DRM_MODE_SCALE_NONE) {
2480 DRM_DEBUG_KMS("no scaling not supported\n");
2481 return -EINVAL;
2482 }
2483
2484 if (intel_connector->panel.fitting_mode == val) {
2485 /* the eDP scaling property is not changed */
2486 return 0;
2487 }
2488 intel_connector->panel.fitting_mode = val;
2489
2490 goto done;
2491 }
2492
f684960e
CW		 2493 return -EINVAL;
2494
2495done:
da63a9f2
PZ		 2496 if (intel_encoder->base.crtc) {
2497 struct drm_crtc *crtc = intel_encoder->base.crtc;
a6778b3c
DV		 2498 intel_set_mode(crtc, &crtc->mode,
2499 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2500 }
2501
2502 return 0;
2503}
2504
a4fc5ed6 2505static void
0206e353 2506intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2507{
aaa6fd2a 2508 struct drm_device *dev = connector->dev;
be3cd5e3 2509 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2510 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2511
9cd300e0
JN		 2512 if (!IS_ERR_OR_NULL(intel_connector->edid))
2513 kfree(intel_connector->edid);
2514
1d508706 2515 if (is_edp(intel_dp)) {
aaa6fd2a 2516 intel_panel_destroy_backlight(dev);
1d508706
JN		 2517 intel_panel_fini(&intel_connector->panel);
2518 }
aaa6fd2a 2519
a4fc5ed6
KP		 2520 drm_sysfs_connector_remove(connector);
2521 drm_connector_cleanup(connector);
55f78c43 2522 kfree(connector);
a4fc5ed6
KP		 2523}
2524
00c09d70 2525void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2526{
da63a9f2
PZ		 2527 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2528 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2529
2530 i2c_del_adapter(&intel_dp->adapter);
2531 drm_encoder_cleanup(encoder);
bd943159
KP		 2532 if (is_edp(intel_dp)) {
2533 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2534 ironlake_panel_vdd_off_sync(intel_dp);
2535 }
da63a9f2 2536 kfree(intel_dig_port);
24d05927
DV		 2537}
2538
a4fc5ed6 2539static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2540 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2541 .mode_set = intel_dp_mode_set,
1f703855 2542 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2543};
2544
2545static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2546 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2547 .detect = intel_dp_detect,
2548 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2549 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2550 .destroy = intel_dp_destroy,
2551};
2552
2553static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2554 .get_modes = intel_dp_get_modes,
2555 .mode_valid = intel_dp_mode_valid,
df0e9248 2556 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2557};
2558
a4fc5ed6 2559static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2560 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2561};
2562
995b6762 2563static void
21d40d37 2564intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2565{
fa90ecef 2566 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2567
885a5014 2568 intel_dp_check_link_status(intel_dp);
c8110e52 2569}
6207937d 2570
e3421a18
ZW		 2571/* Return which DP Port should be selected for Transcoder DP control */
2572int
0206e353 2573intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2574{
2575 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2576 struct intel_encoder *intel_encoder;
2577 struct intel_dp *intel_dp;
e3421a18 2578
fa90ecef
PZ		 2579 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2580 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2581
fa90ecef
PZ		 2582 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2583 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2584 return intel_dp->output_reg;
e3421a18 2585 }
ea5b213a 2586
e3421a18
ZW		 2587 return -1;
2588}
2589
36e83a18 2590/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2591bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2592{
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 struct child_device_config *p_child;
2595 int i;
2596
2597 if (!dev_priv->child_dev_num)
2598 return false;
2599
2600 for (i = 0; i < dev_priv->child_dev_num; i++) {
2601 p_child = dev_priv->child_dev + i;
2602
2603 if (p_child->dvo_port == PORT_IDPD &&
2604 p_child->device_type == DEVICE_TYPE_eDP)
2605 return true;
2606 }
2607 return false;
2608}
2609
f684960e
CW		 2610static void
2611intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2612{
53b41837
YN		 2613 struct intel_connector *intel_connector = to_intel_connector(connector);
2614
3f43c48d 2615 intel_attach_force_audio_property(connector);
e953fd7b 2616 intel_attach_broadcast_rgb_property(connector);
53b41837
YN		 2617
2618 if (is_edp(intel_dp)) {
2619 drm_mode_create_scaling_mode_property(connector->dev);
2620 drm_connector_attach_property(
2621 connector,
2622 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2623 DRM_MODE_SCALE_ASPECT);
2624 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2625 }
f684960e
CW		 2626}
2627
67a54566
DV		 2628static void
2629intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2630 struct intel_dp *intel_dp)
2631{
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 struct edp_power_seq cur, vbt, spec, final;
2634 u32 pp_on, pp_off, pp_div, pp;
2635
2636 /* Workaround: Need to write PP_CONTROL with the unlock key as
2637 * the very first thing. */
2638 pp = ironlake_get_pp_control(dev_priv);
2639 I915_WRITE(PCH_PP_CONTROL, pp);
2640
2641 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2642 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2643 pp_div = I915_READ(PCH_PP_DIVISOR);
2644
2645 /* Pull timing values out of registers */
2646 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2647 PANEL_POWER_UP_DELAY_SHIFT;
2648
2649 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2650 PANEL_LIGHT_ON_DELAY_SHIFT;
2651
2652 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2653 PANEL_LIGHT_OFF_DELAY_SHIFT;
2654
2655 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2656 PANEL_POWER_DOWN_DELAY_SHIFT;
2657
2658 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2659 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2660
2661 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2662 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2663
2664 vbt = dev_priv->edp.pps;
2665
2666 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2667 * our hw here, which are all in 100usec. */
2668 spec.t1_t3 = 210 * 10;
2669 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2670 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2671 spec.t10 = 500 * 10;
2672 /* This one is special and actually in units of 100ms, but zero
2673 * based in the hw (so we need to add 100 ms). But the sw vbt
2674 * table multiplies it with 1000 to make it in units of 100usec,
2675 * too. */
2676 spec.t11_t12 = (510 + 100) * 10;
2677
2678 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2679 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2680
2681 /* Use the max of the register settings and vbt. If both are
2682 * unset, fall back to the spec limits. */
2683#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2684 spec.field : \
2685 max(cur.field, vbt.field))
2686 assign_final(t1_t3);
2687 assign_final(t8);
2688 assign_final(t9);
2689 assign_final(t10);
2690 assign_final(t11_t12);
2691#undef assign_final
2692
2693#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2694 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2695 intel_dp->backlight_on_delay = get_delay(t8);
2696 intel_dp->backlight_off_delay = get_delay(t9);
2697 intel_dp->panel_power_down_delay = get_delay(t10);
2698 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2699#undef get_delay
2700
2701 /* And finally store the new values in the power sequencer. */
2702 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2703 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2704 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2705 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2706 /* Compute the divisor for the pp clock, simply match the Bspec
2707 * formula. */
2708 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2709 << PP_REFERENCE_DIVIDER_SHIFT;
2710 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2711 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2712
2713 /* Haswell doesn't have any port selection bits for the panel
2714 * power sequencer any more. */
2715 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2716 if (is_cpu_edp(intel_dp))
2717 pp_on |= PANEL_POWER_PORT_DP_A;
2718 else
2719 pp_on |= PANEL_POWER_PORT_DP_D;
2720 }
2721
2722 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2723 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2724 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2725
2726
2727 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2728 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2729 intel_dp->panel_power_cycle_delay);
2730
2731 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2732 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2733
2734 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2735 I915_READ(PCH_PP_ON_DELAYS),
2736 I915_READ(PCH_PP_OFF_DELAYS),
2737 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2738}
2739
a4fc5ed6 2740void
f0fec3f2
PZ		 2741intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2742 struct intel_connector *intel_connector)
a4fc5ed6 2743{
f0fec3f2
PZ		 2744 struct drm_connector *connector = &intel_connector->base;
2745 struct intel_dp *intel_dp = &intel_dig_port->dp;
2746 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2747 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2748 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2749 struct drm_display_mode *fixed_mode = NULL;
174edf1f 2750 enum port port = intel_dig_port->port;
5eb08b69 2751 const char *name = NULL;
b329530c 2752 int type;
a4fc5ed6 2753
0767935e
DV		 2754 /* Preserve the current hw state. */
2755 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2756 intel_dp->attached_connector = intel_connector;
3d3dc149 2757
f0fec3f2 2758 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2759 if (intel_dpd_is_edp(dev))
ea5b213a 2760 intel_dp->is_pch_edp = true;
b329530c 2761
19c03924
GB		 2762 /*
2763 * FIXME : We need to initialize built-in panels before external panels.
2764 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2765 */
f0fec3f2 2766 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2767 type = DRM_MODE_CONNECTOR_eDP;
2768 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2769 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2770 type = DRM_MODE_CONNECTOR_eDP;
2771 intel_encoder->type = INTEL_OUTPUT_EDP;
2772 } else {
00c09d70
PZ		 2773 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2774 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2775 * rewrite it.
2776 */
b329530c 2777 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2778 }
2779
b329530c 2780 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2781 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2782
eb1f8e4f 2783 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2784 connector->interlace_allowed = true;
2785 connector->doublescan_allowed = 0;
2786
f0fec3f2
PZ		 2787 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2788 ironlake_panel_vdd_work);
a4fc5ed6 2789
df0e9248 2790 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2791 drm_sysfs_connector_add(connector);
2792
affa9354 2793 if (HAS_DDI(dev))
bcbc889b
PZ		 2794 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2795 else
2796 intel_connector->get_hw_state = intel_connector_get_hw_state;
2797
e8cb4558 2798
a4fc5ed6 2799 /* Set up the DDC bus. */
ab9d7c30
PZ		 2800 switch (port) {
2801 case PORT_A:
2802 name = "DPDDC-A";
2803 break;
2804 case PORT_B:
2805 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2806 name = "DPDDC-B";
2807 break;
2808 case PORT_C:
2809 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2810 name = "DPDDC-C";
2811 break;
2812 case PORT_D:
2813 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2814 name = "DPDDC-D";
2815 break;
2816 default:
2817 WARN(1, "Invalid port %c\n", port_name(port));
2818 break;
5eb08b69
ZW		 2819 }
2820
67a54566
DV		 2821 if (is_edp(intel_dp))
2822 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2823
2824 intel_dp_i2c_init(intel_dp, intel_connector, name);
2825
67a54566 2826 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2827 if (is_edp(intel_dp)) {
2828 bool ret;
f8779fda 2829 struct drm_display_mode *scan;
c1f05264 2830 struct edid *edid;
5d613501
JB		 2831
2832 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2833 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2834 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2835
59f3e272 2836 if (ret) {
7183dc29
JB		 2837 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2838 dev_priv->no_aux_handshake =
2839 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2840 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2841 } else {
3d3dc149 2842 /* if this fails, presume the device is a ghost */
48898b03 2843 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2844 intel_dp_encoder_destroy(&intel_encoder->base);
2845 intel_dp_destroy(connector);
3d3dc149 2846 return;
89667383 2847 }
89667383 2848
d6f24d0f
JB		 2849 ironlake_edp_panel_vdd_on(intel_dp);
2850 edid = drm_get_edid(connector, &intel_dp->adapter);
2851 if (edid) {
9cd300e0
JN		 2852 if (drm_add_edid_modes(connector, edid)) {
2853 drm_mode_connector_update_edid_property(connector, edid);
2854 drm_edid_to_eld(connector, edid);
2855 } else {
2856 kfree(edid);
2857 edid = ERR_PTR(-EINVAL);
2858 }
2859 } else {
2860 edid = ERR_PTR(-ENOENT);
d6f24d0f 2861 }
9cd300e0 2862 intel_connector->edid = edid;
f8779fda
JN		 2863
2864 /* prefer fixed mode from EDID if available */
2865 list_for_each_entry(scan, &connector->probed_modes, head) {
2866 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2867 fixed_mode = drm_mode_duplicate(dev, scan);
2868 break;
2869 }
d6f24d0f 2870 }
f8779fda
JN		 2871
2872 /* fallback to VBT if available for eDP */
2873 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2874 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2875 if (fixed_mode)
2876 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2877 }
f8779fda 2878
d6f24d0f
JB		 2879 ironlake_edp_panel_vdd_off(intel_dp, false);
2880 }
552fb0b7 2881
4d926461 2882 if (is_edp(intel_dp)) {
dd06f90e 2883 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2884 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2885 }
2886
f684960e
CW		 2887 intel_dp_add_properties(intel_dp, connector);
2888
a4fc5ed6
KP		 2889 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2890 * 0xd. Failure to do so will result in spurious interrupts being
2891 * generated on the port when a cable is not attached.
2892 */
2893 if (IS_G4X(dev) && !IS_GM45(dev)) {
2894 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2895 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2896 }
2897}
f0fec3f2
PZ		 2898
2899void
2900intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2901{
2902 struct intel_digital_port *intel_dig_port;
2903 struct intel_encoder *intel_encoder;
2904 struct drm_encoder *encoder;
2905 struct intel_connector *intel_connector;
2906
2907 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2908 if (!intel_dig_port)
2909 return;
2910
2911 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2912 if (!intel_connector) {
2913 kfree(intel_dig_port);
2914 return;
2915 }
2916
2917 intel_encoder = &intel_dig_port->base;
2918 encoder = &intel_encoder->base;
2919
2920 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2921 DRM_MODE_ENCODER_TMDS);
00c09d70 2922 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2923
00c09d70
PZ		 2924 intel_encoder->enable = intel_enable_dp;
2925 intel_encoder->pre_enable = intel_pre_enable_dp;
2926 intel_encoder->disable = intel_disable_dp;
2927 intel_encoder->post_disable = intel_post_disable_dp;
2928 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2929
174edf1f 2930 intel_dig_port->port = port;
f0fec3f2
PZ		 2931 intel_dig_port->dp.output_reg = output_reg;
2932
00c09d70 2933 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2934 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2935 intel_encoder->cloneable = false;
2936 intel_encoder->hot_plug = intel_dp_hot_plug;
2937
2938 intel_dp_init_connector(intel_dig_port, intel_connector);
2939}
Linux kernel - Deliverables
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