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drm/i915: Correct the Sandybridge chipset info structs.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include "drmP.h"
30#include "drm.h"
31#include "drm_crtc.h"
32#include "drm_crtc_helper.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
ab2c0672 36#include "drm_dp_helper.h"
a4fc5ed6 37
ae266c98 38
a4fc5ed6
KP		 39#define DP_LINK_STATUS_SIZE 6
40#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41
42#define DP_LINK_CONFIGURATION_SIZE 9
43
32f9d658
ZW		 44#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
45
a4fc5ed6
KP		 46struct intel_dp_priv {
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 uint32_t save_DP;
51 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
52 bool has_audio;
c8110e52 53 int dpms_mode;
a4fc5ed6
KP		 54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[4];
57 struct intel_output *intel_output;
58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
60};
61
62static void
63intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
64 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
65
66static void
67intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
68
32f9d658
ZW		 69void
70intel_edp_link_config (struct intel_output *intel_output,
71 int *lane_num, int *link_bw)
72{
73 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
74
75 *lane_num = dp_priv->lane_count;
76 if (dp_priv->link_bw == DP_LINK_BW_1_62)
77 *link_bw = 162000;
78 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
79 *link_bw = 270000;
80}
81
a4fc5ed6
KP		 82static int
83intel_dp_max_lane_count(struct intel_output *intel_output)
84{
85 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
86 int max_lane_count = 4;
87
88 if (dp_priv->dpcd[0] >= 0x11) {
89 max_lane_count = dp_priv->dpcd[2] & 0x1f;
90 switch (max_lane_count) {
91 case 1: case 2: case 4:
92 break;
93 default:
94 max_lane_count = 4;
95 }
96 }
97 return max_lane_count;
98}
99
100static int
101intel_dp_max_link_bw(struct intel_output *intel_output)
102{
103 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
104 int max_link_bw = dp_priv->dpcd[1];
105
106 switch (max_link_bw) {
107 case DP_LINK_BW_1_62:
108 case DP_LINK_BW_2_7:
109 break;
110 default:
111 max_link_bw = DP_LINK_BW_1_62;
112 break;
113 }
114 return max_link_bw;
115}
116
117static int
118intel_dp_link_clock(uint8_t link_bw)
119{
120 if (link_bw == DP_LINK_BW_2_7)
121 return 270000;
122 else
123 return 162000;
124}
125
126/* I think this is a fiction */
127static int
885a5fb5
ZW		 128intel_dp_link_required(struct drm_device *dev,
129 struct intel_output *intel_output, int pixel_clock)
a4fc5ed6 130{
885a5fb5
ZW		 131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 if (IS_eDP(intel_output))
134 return (pixel_clock * dev_priv->edp_bpp) / 8;
135 else
136 return pixel_clock * 3;
a4fc5ed6
KP		 137}
138
139static int
140intel_dp_mode_valid(struct drm_connector *connector,
141 struct drm_display_mode *mode)
142{
143 struct intel_output *intel_output = to_intel_output(connector);
144 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
145 int max_lanes = intel_dp_max_lane_count(intel_output);
146
885a5fb5
ZW		 147 if (intel_dp_link_required(connector->dev, intel_output, mode->clock)
148 > max_link_clock * max_lanes)
a4fc5ed6
KP		 149 return MODE_CLOCK_HIGH;
150
151 if (mode->clock < 10000)
152 return MODE_CLOCK_LOW;
153
154 return MODE_OK;
155}
156
157static uint32_t
158pack_aux(uint8_t *src, int src_bytes)
159{
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168}
169
170static void
171unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172{
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178}
179
fb0f8fbf
KP		 180/* hrawclock is 1/4 the FSB frequency */
181static int
182intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 clkcfg = I915_READ(CLKCFG);
188 switch (clkcfg & CLKCFG_FSB_MASK) {
189 case CLKCFG_FSB_400:
190 return 100;
191 case CLKCFG_FSB_533:
192 return 133;
193 case CLKCFG_FSB_667:
194 return 166;
195 case CLKCFG_FSB_800:
196 return 200;
197 case CLKCFG_FSB_1067:
198 return 266;
199 case CLKCFG_FSB_1333:
200 return 333;
201 /* these two are just a guess; one of them might be right */
202 case CLKCFG_FSB_1600:
203 case CLKCFG_FSB_1600_ALT:
204 return 400;
205 default:
206 return 133;
207 }
208}
209
a4fc5ed6
KP		 210static int
211intel_dp_aux_ch(struct intel_output *intel_output,
212 uint8_t *send, int send_bytes,
213 uint8_t *recv, int recv_size)
214{
215 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
216 uint32_t output_reg = dp_priv->output_reg;
217 struct drm_device *dev = intel_output->base.dev;
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 uint32_t ch_ctl = output_reg + 0x10;
220 uint32_t ch_data = ch_ctl + 4;
221 int i;
222 int recv_bytes;
223 uint32_t ctl;
224 uint32_t status;
fb0f8fbf
KP		 225 uint32_t aux_clock_divider;
226 int try;
a4fc5ed6
KP		 227
228 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 229 * and would like to run at 2MHz. So, take the
230 * hrawclk value and divide by 2 and use that
a4fc5ed6 231 */
32f9d658
ZW		 232 if (IS_eDP(intel_output))
233 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
f2b115e6
AJ		 234 else if (IS_IRONLAKE(dev))
235 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 236 else
237 aux_clock_divider = intel_hrawclk(dev) / 2;
238
fb0f8fbf
KP		 239 /* Must try at least 3 times according to DP spec */
240 for (try = 0; try < 5; try++) {
241 /* Load the send data into the aux channel data registers */
242 for (i = 0; i < send_bytes; i += 4) {
a419aef8 243 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 244
245 I915_WRITE(ch_data + i, d);
246 }
247
248 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
249 DP_AUX_CH_CTL_TIME_OUT_400us |
250 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
251 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
252 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
253 DP_AUX_CH_CTL_DONE |
254 DP_AUX_CH_CTL_TIME_OUT_ERROR |
255 DP_AUX_CH_CTL_RECEIVE_ERROR);
256
257 /* Send the command and wait for it to complete */
258 I915_WRITE(ch_ctl, ctl);
259 (void) I915_READ(ch_ctl);
260 for (;;) {
261 udelay(100);
262 status = I915_READ(ch_ctl);
263 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
264 break;
265 }
266
267 /* Clear done status and any errors */
eebc863e 268 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 269 DP_AUX_CH_CTL_DONE |
270 DP_AUX_CH_CTL_TIME_OUT_ERROR |
271 DP_AUX_CH_CTL_RECEIVE_ERROR));
272 (void) I915_READ(ch_ctl);
273 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 274 break;
275 }
276
a4fc5ed6 277 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 278 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 279 return -EBUSY;
a4fc5ed6
KP		 280 }
281
282 /* Check for timeout or receive error.
283 * Timeouts occur when the sink is not connected
284 */
a5b3da54 285 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 286 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 287 return -EIO;
288 }
1ae8c0a5
KP		 289
290 /* Timeouts occur when the device isn't connected, so they're
291 * "normal" -- don't fill the kernel log with these */
a5b3da54 292 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 293 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 294 return -ETIMEDOUT;
a4fc5ed6
KP		 295 }
296
297 /* Unload any bytes sent back from the other side */
298 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
299 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
300
301 if (recv_bytes > recv_size)
302 recv_bytes = recv_size;
303
304 for (i = 0; i < recv_bytes; i += 4) {
305 uint32_t d = I915_READ(ch_data + i);
306
307 unpack_aux(d, recv + i, recv_bytes - i);
308 }
309
310 return recv_bytes;
311}
312
313/* Write data to the aux channel in native mode */
314static int
315intel_dp_aux_native_write(struct intel_output *intel_output,
316 uint16_t address, uint8_t *send, int send_bytes)
317{
318 int ret;
319 uint8_t msg[20];
320 int msg_bytes;
321 uint8_t ack;
322
323 if (send_bytes > 16)
324 return -1;
325 msg[0] = AUX_NATIVE_WRITE << 4;
326 msg[1] = address >> 8;
eebc863e 327 msg[2] = address & 0xff;
a4fc5ed6
KP		 328 msg[3] = send_bytes - 1;
329 memcpy(&msg[4], send, send_bytes);
330 msg_bytes = send_bytes + 4;
331 for (;;) {
332 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
333 if (ret < 0)
334 return ret;
335 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
336 break;
337 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
338 udelay(100);
339 else
a5b3da54 340 return -EIO;
a4fc5ed6
KP		 341 }
342 return send_bytes;
343}
344
345/* Write a single byte to the aux channel in native mode */
346static int
347intel_dp_aux_native_write_1(struct intel_output *intel_output,
348 uint16_t address, uint8_t byte)
349{
350 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
351}
352
353/* read bytes from a native aux channel */
354static int
355intel_dp_aux_native_read(struct intel_output *intel_output,
356 uint16_t address, uint8_t *recv, int recv_bytes)
357{
358 uint8_t msg[4];
359 int msg_bytes;
360 uint8_t reply[20];
361 int reply_bytes;
362 uint8_t ack;
363 int ret;
364
365 msg[0] = AUX_NATIVE_READ << 4;
366 msg[1] = address >> 8;
367 msg[2] = address & 0xff;
368 msg[3] = recv_bytes - 1;
369
370 msg_bytes = 4;
371 reply_bytes = recv_bytes + 1;
372
373 for (;;) {
374 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
375 reply, reply_bytes);
a5b3da54
KP		 376 if (ret == 0)
377 return -EPROTO;
378 if (ret < 0)
a4fc5ed6
KP		 379 return ret;
380 ack = reply[0];
381 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
382 memcpy(recv, reply + 1, ret - 1);
383 return ret - 1;
384 }
385 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
386 udelay(100);
387 else
a5b3da54 388 return -EIO;
a4fc5ed6
KP		 389 }
390}
391
392static int
ab2c0672
DA		 393intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
394 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 395{
ab2c0672 396 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 397 struct intel_dp_priv *dp_priv = container_of(adapter,
398 struct intel_dp_priv,
399 adapter);
400 struct intel_output *intel_output = dp_priv->intel_output;
ab2c0672
DA		 401 uint16_t address = algo_data->address;
402 uint8_t msg[5];
403 uint8_t reply[2];
404 int msg_bytes;
405 int reply_bytes;
406 int ret;
407
408 /* Set up the command byte */
409 if (mode & MODE_I2C_READ)
410 msg[0] = AUX_I2C_READ << 4;
411 else
412 msg[0] = AUX_I2C_WRITE << 4;
413
414 if (!(mode & MODE_I2C_STOP))
415 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 416
ab2c0672
DA		 417 msg[1] = address >> 8;
418 msg[2] = address;
419
420 switch (mode) {
421 case MODE_I2C_WRITE:
422 msg[3] = 0;
423 msg[4] = write_byte;
424 msg_bytes = 5;
425 reply_bytes = 1;
426 break;
427 case MODE_I2C_READ:
428 msg[3] = 0;
429 msg_bytes = 4;
430 reply_bytes = 2;
431 break;
432 default:
433 msg_bytes = 3;
434 reply_bytes = 1;
435 break;
436 }
437
438 for (;;) {
439 ret = intel_dp_aux_ch(intel_output,
440 msg, msg_bytes,
441 reply, reply_bytes);
442 if (ret < 0) {
3ff99164 443 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 444 return ret;
445 }
446 switch (reply[0] & AUX_I2C_REPLY_MASK) {
447 case AUX_I2C_REPLY_ACK:
448 if (mode == MODE_I2C_READ) {
449 *read_byte = reply[1];
450 }
451 return reply_bytes - 1;
452 case AUX_I2C_REPLY_NACK:
3ff99164 453 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 454 return -EREMOTEIO;
455 case AUX_I2C_REPLY_DEFER:
3ff99164 456 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 457 udelay(100);
458 break;
459 default:
460 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
461 return -EREMOTEIO;
462 }
463 }
a4fc5ed6
KP		 464}
465
466static int
467intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
468{
469 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
470
d54e9d28 471 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 472 dp_priv->algo.running = false;
473 dp_priv->algo.address = 0;
474 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
475
476 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
477 dp_priv->adapter.owner = THIS_MODULE;
478 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 479 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
480 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6
KP		 481 dp_priv->adapter.algo_data = &dp_priv->algo;
482 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
483
484 return i2c_dp_aux_add_bus(&dp_priv->adapter);
485}
486
487static bool
488intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
489 struct drm_display_mode *adjusted_mode)
490{
491 struct intel_output *intel_output = enc_to_intel_output(encoder);
492 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
493 int lane_count, clock;
494 int max_lane_count = intel_dp_max_lane_count(intel_output);
495 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
496 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
497
498 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
499 for (clock = 0; clock <= max_clock; clock++) {
500 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
501
885a5fb5
ZW		 502 if (intel_dp_link_required(encoder->dev, intel_output, mode->clock)
503 <= link_avail) {
a4fc5ed6
KP		 504 dp_priv->link_bw = bws[clock];
505 dp_priv->lane_count = lane_count;
506 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 507 DRM_DEBUG_KMS("Display port link bw %02x lane "
508 "count %d clock %d\n",
a4fc5ed6
KP		 509 dp_priv->link_bw, dp_priv->lane_count,
510 adjusted_mode->clock);
511 return true;
512 }
513 }
514 }
515 return false;
516}
517
518struct intel_dp_m_n {
519 uint32_t tu;
520 uint32_t gmch_m;
521 uint32_t gmch_n;
522 uint32_t link_m;
523 uint32_t link_n;
524};
525
526static void
527intel_reduce_ratio(uint32_t *num, uint32_t *den)
528{
529 while (*num > 0xffffff || *den > 0xffffff) {
530 *num >>= 1;
531 *den >>= 1;
532 }
533}
534
535static void
536intel_dp_compute_m_n(int bytes_per_pixel,
537 int nlanes,
538 int pixel_clock,
539 int link_clock,
540 struct intel_dp_m_n *m_n)
541{
542 m_n->tu = 64;
543 m_n->gmch_m = pixel_clock * bytes_per_pixel;
544 m_n->gmch_n = link_clock * nlanes;
545 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
546 m_n->link_m = pixel_clock;
547 m_n->link_n = link_clock;
548 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
549}
550
551void
552intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
553 struct drm_display_mode *adjusted_mode)
554{
555 struct drm_device *dev = crtc->dev;
556 struct drm_mode_config *mode_config = &dev->mode_config;
557 struct drm_connector *connector;
558 struct drm_i915_private *dev_priv = dev->dev_private;
559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
560 int lane_count = 4;
561 struct intel_dp_m_n m_n;
562
563 /*
564 * Find the lane count in the intel_output private
565 */
566 list_for_each_entry(connector, &mode_config->connector_list, head) {
567 struct intel_output *intel_output = to_intel_output(connector);
568 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
569
570 if (!connector->encoder || connector->encoder->crtc != crtc)
571 continue;
572
573 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
574 lane_count = dp_priv->lane_count;
575 break;
576 }
577 }
578
579 /*
580 * Compute the GMCH and Link ratios. The '3' here is
581 * the number of bytes_per_pixel post-LUT, which we always
582 * set up for 8-bits of R/G/B, or 3 bytes total.
583 */
584 intel_dp_compute_m_n(3, lane_count,
585 mode->clock, adjusted_mode->clock, &m_n);
586
f2b115e6 587 if (IS_IRONLAKE(dev)) {
5eb08b69
ZW		 588 if (intel_crtc->pipe == 0) {
589 I915_WRITE(TRANSA_DATA_M1,
590 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
591 m_n.gmch_m);
592 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
593 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
594 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
595 } else {
596 I915_WRITE(TRANSB_DATA_M1,
597 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
598 m_n.gmch_m);
599 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
600 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
601 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
602 }
a4fc5ed6 603 } else {
5eb08b69
ZW		 604 if (intel_crtc->pipe == 0) {
605 I915_WRITE(PIPEA_GMCH_DATA_M,
606 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
607 m_n.gmch_m);
608 I915_WRITE(PIPEA_GMCH_DATA_N,
609 m_n.gmch_n);
610 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
611 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
612 } else {
613 I915_WRITE(PIPEB_GMCH_DATA_M,
614 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
615 m_n.gmch_m);
616 I915_WRITE(PIPEB_GMCH_DATA_N,
617 m_n.gmch_n);
618 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
619 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
620 }
a4fc5ed6
KP		 621 }
622}
623
624static void
625intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
626 struct drm_display_mode *adjusted_mode)
627{
628 struct intel_output *intel_output = enc_to_intel_output(encoder);
629 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
630 struct drm_crtc *crtc = intel_output->enc.crtc;
631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
632
633 dp_priv->DP = (DP_LINK_TRAIN_OFF |
634 DP_VOLTAGE_0_4 |
635 DP_PRE_EMPHASIS_0 |
636 DP_SYNC_VS_HIGH |
637 DP_SYNC_HS_HIGH);
638
639 switch (dp_priv->lane_count) {
640 case 1:
641 dp_priv->DP |= DP_PORT_WIDTH_1;
642 break;
643 case 2:
644 dp_priv->DP |= DP_PORT_WIDTH_2;
645 break;
646 case 4:
647 dp_priv->DP |= DP_PORT_WIDTH_4;
648 break;
649 }
650 if (dp_priv->has_audio)
651 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
652
653 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
654 dp_priv->link_configuration[0] = dp_priv->link_bw;
655 dp_priv->link_configuration[1] = dp_priv->lane_count;
656
657 /*
658 * Check for DPCD version > 1.1,
659 * enable enahanced frame stuff in that case
660 */
661 if (dp_priv->dpcd[0] >= 0x11) {
662 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
663 dp_priv->DP |= DP_ENHANCED_FRAMING;
664 }
665
666 if (intel_crtc->pipe == 1)
667 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658
ZW		 668
669 if (IS_eDP(intel_output)) {
670 /* don't miss out required setting for eDP */
671 dp_priv->DP |= DP_PLL_ENABLE;
672 if (adjusted_mode->clock < 200000)
673 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
674 else
675 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
676 }
a4fc5ed6
KP		 677}
678
f2b115e6 679static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 680{
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 u32 pp;
683
28c97730 684 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 685 pp = I915_READ(PCH_PP_CONTROL);
686 pp |= EDP_BLC_ENABLE;
687 I915_WRITE(PCH_PP_CONTROL, pp);
688}
689
f2b115e6 690static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 691{
692 struct drm_i915_private *dev_priv = dev->dev_private;
693 u32 pp;
694
28c97730 695 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 696 pp = I915_READ(PCH_PP_CONTROL);
697 pp &= ~EDP_BLC_ENABLE;
698 I915_WRITE(PCH_PP_CONTROL, pp);
699}
a4fc5ed6
KP		 700
701static void
702intel_dp_dpms(struct drm_encoder *encoder, int mode)
703{
704 struct intel_output *intel_output = enc_to_intel_output(encoder);
705 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
706 struct drm_device *dev = intel_output->base.dev;
707 struct drm_i915_private *dev_priv = dev->dev_private;
708 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
709
710 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 711 if (dp_reg & DP_PORT_EN) {
a4fc5ed6 712 intel_dp_link_down(intel_output, dp_priv->DP);
32f9d658 713 if (IS_eDP(intel_output))
f2b115e6 714 ironlake_edp_backlight_off(dev);
32f9d658 715 }
a4fc5ed6 716 } else {
32f9d658 717 if (!(dp_reg & DP_PORT_EN)) {
a4fc5ed6 718 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
32f9d658 719 if (IS_eDP(intel_output))
f2b115e6 720 ironlake_edp_backlight_on(dev);
32f9d658 721 }
a4fc5ed6 722 }
c8110e52 723 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 724}
725
726/*
727 * Fetch AUX CH registers 0x202 - 0x207 which contain
728 * link status information
729 */
730static bool
731intel_dp_get_link_status(struct intel_output *intel_output,
732 uint8_t link_status[DP_LINK_STATUS_SIZE])
733{
734 int ret;
735
736 ret = intel_dp_aux_native_read(intel_output,
737 DP_LANE0_1_STATUS,
738 link_status, DP_LINK_STATUS_SIZE);
739 if (ret != DP_LINK_STATUS_SIZE)
740 return false;
741 return true;
742}
743
744static uint8_t
745intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
746 int r)
747{
748 return link_status[r - DP_LANE0_1_STATUS];
749}
750
751static void
752intel_dp_save(struct drm_connector *connector)
753{
754 struct intel_output *intel_output = to_intel_output(connector);
755 struct drm_device *dev = intel_output->base.dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
758
759 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
760 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
761 dp_priv->save_link_configuration,
762 sizeof (dp_priv->save_link_configuration));
763}
764
765static uint8_t
766intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
767 int lane)
768{
769 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
770 int s = ((lane & 1) ?
771 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
772 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
773 uint8_t l = intel_dp_link_status(link_status, i);
774
775 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
776}
777
778static uint8_t
779intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
780 int lane)
781{
782 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
783 int s = ((lane & 1) ?
784 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
785 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
786 uint8_t l = intel_dp_link_status(link_status, i);
787
788 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
789}
790
791
792#if 0
793static char *voltage_names[] = {
794 "0.4V", "0.6V", "0.8V", "1.2V"
795};
796static char *pre_emph_names[] = {
797 "0dB", "3.5dB", "6dB", "9.5dB"
798};
799static char *link_train_names[] = {
800 "pattern 1", "pattern 2", "idle", "off"
801};
802#endif
803
804/*
805 * These are source-specific values; current Intel hardware supports
806 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
807 */
808#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
809
810static uint8_t
811intel_dp_pre_emphasis_max(uint8_t voltage_swing)
812{
813 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
814 case DP_TRAIN_VOLTAGE_SWING_400:
815 return DP_TRAIN_PRE_EMPHASIS_6;
816 case DP_TRAIN_VOLTAGE_SWING_600:
817 return DP_TRAIN_PRE_EMPHASIS_6;
818 case DP_TRAIN_VOLTAGE_SWING_800:
819 return DP_TRAIN_PRE_EMPHASIS_3_5;
820 case DP_TRAIN_VOLTAGE_SWING_1200:
821 default:
822 return DP_TRAIN_PRE_EMPHASIS_0;
823 }
824}
825
826static void
827intel_get_adjust_train(struct intel_output *intel_output,
828 uint8_t link_status[DP_LINK_STATUS_SIZE],
829 int lane_count,
830 uint8_t train_set[4])
831{
832 uint8_t v = 0;
833 uint8_t p = 0;
834 int lane;
835
836 for (lane = 0; lane < lane_count; lane++) {
837 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
838 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
839
840 if (this_v > v)
841 v = this_v;
842 if (this_p > p)
843 p = this_p;
844 }
845
846 if (v >= I830_DP_VOLTAGE_MAX)
847 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
848
849 if (p >= intel_dp_pre_emphasis_max(v))
850 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
851
852 for (lane = 0; lane < 4; lane++)
853 train_set[lane] = v | p;
854}
855
856static uint32_t
857intel_dp_signal_levels(uint8_t train_set, int lane_count)
858{
859 uint32_t signal_levels = 0;
860
861 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
862 case DP_TRAIN_VOLTAGE_SWING_400:
863 default:
864 signal_levels |= DP_VOLTAGE_0_4;
865 break;
866 case DP_TRAIN_VOLTAGE_SWING_600:
867 signal_levels |= DP_VOLTAGE_0_6;
868 break;
869 case DP_TRAIN_VOLTAGE_SWING_800:
870 signal_levels |= DP_VOLTAGE_0_8;
871 break;
872 case DP_TRAIN_VOLTAGE_SWING_1200:
873 signal_levels |= DP_VOLTAGE_1_2;
874 break;
875 }
876 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
877 case DP_TRAIN_PRE_EMPHASIS_0:
878 default:
879 signal_levels |= DP_PRE_EMPHASIS_0;
880 break;
881 case DP_TRAIN_PRE_EMPHASIS_3_5:
882 signal_levels |= DP_PRE_EMPHASIS_3_5;
883 break;
884 case DP_TRAIN_PRE_EMPHASIS_6:
885 signal_levels |= DP_PRE_EMPHASIS_6;
886 break;
887 case DP_TRAIN_PRE_EMPHASIS_9_5:
888 signal_levels |= DP_PRE_EMPHASIS_9_5;
889 break;
890 }
891 return signal_levels;
892}
893
894static uint8_t
895intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
896 int lane)
897{
898 int i = DP_LANE0_1_STATUS + (lane >> 1);
899 int s = (lane & 1) * 4;
900 uint8_t l = intel_dp_link_status(link_status, i);
901
902 return (l >> s) & 0xf;
903}
904
905/* Check for clock recovery is done on all channels */
906static bool
907intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
908{
909 int lane;
910 uint8_t lane_status;
911
912 for (lane = 0; lane < lane_count; lane++) {
913 lane_status = intel_get_lane_status(link_status, lane);
914 if ((lane_status & DP_LANE_CR_DONE) == 0)
915 return false;
916 }
917 return true;
918}
919
920/* Check to see if channel eq is done on all channels */
921#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
922 DP_LANE_CHANNEL_EQ_DONE|\
923 DP_LANE_SYMBOL_LOCKED)
924static bool
925intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
926{
927 uint8_t lane_align;
928 uint8_t lane_status;
929 int lane;
930
931 lane_align = intel_dp_link_status(link_status,
932 DP_LANE_ALIGN_STATUS_UPDATED);
933 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
934 return false;
935 for (lane = 0; lane < lane_count; lane++) {
936 lane_status = intel_get_lane_status(link_status, lane);
937 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
938 return false;
939 }
940 return true;
941}
942
943static bool
944intel_dp_set_link_train(struct intel_output *intel_output,
945 uint32_t dp_reg_value,
946 uint8_t dp_train_pat,
947 uint8_t train_set[4],
948 bool first)
949{
950 struct drm_device *dev = intel_output->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
953 int ret;
954
955 I915_WRITE(dp_priv->output_reg, dp_reg_value);
956 POSTING_READ(dp_priv->output_reg);
957 if (first)
958 intel_wait_for_vblank(dev);
959
960 intel_dp_aux_native_write_1(intel_output,
961 DP_TRAINING_PATTERN_SET,
962 dp_train_pat);
963
964 ret = intel_dp_aux_native_write(intel_output,
965 DP_TRAINING_LANE0_SET, train_set, 4);
966 if (ret != 4)
967 return false;
968
969 return true;
970}
971
972static void
973intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
974 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
975{
976 struct drm_device *dev = intel_output->base.dev;
977 struct drm_i915_private *dev_priv = dev->dev_private;
978 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
979 uint8_t train_set[4];
980 uint8_t link_status[DP_LINK_STATUS_SIZE];
981 int i;
982 uint8_t voltage;
983 bool clock_recovery = false;
984 bool channel_eq = false;
985 bool first = true;
986 int tries;
987
988 /* Write the link configuration data */
989 intel_dp_aux_native_write(intel_output, 0x100,
990 link_configuration, DP_LINK_CONFIGURATION_SIZE);
991
992 DP |= DP_PORT_EN;
993 DP &= ~DP_LINK_TRAIN_MASK;
994 memset(train_set, 0, 4);
995 voltage = 0xff;
996 tries = 0;
997 clock_recovery = false;
998 for (;;) {
999 /* Use train_set[0] to set the voltage and pre emphasis values */
1000 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1001 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1002
1003 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
1004 DP_TRAINING_PATTERN_1, train_set, first))
1005 break;
1006 first = false;
1007 /* Set training pattern 1 */
1008
1009 udelay(100);
1010 if (!intel_dp_get_link_status(intel_output, link_status))
1011 break;
1012
1013 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1014 clock_recovery = true;
1015 break;
1016 }
1017
1018 /* Check to see if we've tried the max voltage */
1019 for (i = 0; i < dp_priv->lane_count; i++)
1020 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1021 break;
1022 if (i == dp_priv->lane_count)
1023 break;
1024
1025 /* Check to see if we've tried the same voltage 5 times */
1026 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1027 ++tries;
1028 if (tries == 5)
1029 break;
1030 } else
1031 tries = 0;
1032 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1033
1034 /* Compute new train_set as requested by target */
1035 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1036 }
1037
1038 /* channel equalization */
1039 tries = 0;
1040 channel_eq = false;
1041 for (;;) {
1042 /* Use train_set[0] to set the voltage and pre emphasis values */
1043 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1044 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1045
1046 /* channel eq pattern */
1047 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
1048 DP_TRAINING_PATTERN_2, train_set,
1049 false))
1050 break;
1051
1052 udelay(400);
1053 if (!intel_dp_get_link_status(intel_output, link_status))
1054 break;
1055
1056 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1057 channel_eq = true;
1058 break;
1059 }
1060
1061 /* Try 5 times */
1062 if (tries > 5)
1063 break;
1064
1065 /* Compute new train_set as requested by target */
1066 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1067 ++tries;
1068 }
1069
1070 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1071 POSTING_READ(dp_priv->output_reg);
1072 intel_dp_aux_native_write_1(intel_output,
1073 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1074}
1075
1076static void
1077intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1078{
1079 struct drm_device *dev = intel_output->base.dev;
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1082
28c97730 1083 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 1084
1085 if (IS_eDP(intel_output)) {
1086 DP &= ~DP_PLL_ENABLE;
1087 I915_WRITE(dp_priv->output_reg, DP);
1088 POSTING_READ(dp_priv->output_reg);
1089 udelay(100);
1090 }
1091
5eb08b69
ZW		 1092 DP &= ~DP_LINK_TRAIN_MASK;
1093 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1094 POSTING_READ(dp_priv->output_reg);
1095
1096 udelay(17000);
1097
32f9d658
ZW		 1098 if (IS_eDP(intel_output))
1099 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1100 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1101 POSTING_READ(dp_priv->output_reg);
1102}
1103
1104static void
1105intel_dp_restore(struct drm_connector *connector)
1106{
1107 struct intel_output *intel_output = to_intel_output(connector);
1108 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1109
1110 if (dp_priv->save_DP & DP_PORT_EN)
1111 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
1112 else
1113 intel_dp_link_down(intel_output, dp_priv->save_DP);
1114}
1115
a4fc5ed6
KP		 1116/*
1117 * According to DP spec
1118 * 5.1.2:
1119 * 1. Read DPCD
1120 * 2. Configure link according to Receiver Capabilities
1121 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1122 * 4. Check link status on receipt of hot-plug interrupt
1123 */
1124
1125static void
1126intel_dp_check_link_status(struct intel_output *intel_output)
1127{
1128 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1129 uint8_t link_status[DP_LINK_STATUS_SIZE];
1130
1131 if (!intel_output->enc.crtc)
1132 return;
1133
1134 if (!intel_dp_get_link_status(intel_output, link_status)) {
1135 intel_dp_link_down(intel_output, dp_priv->DP);
1136 return;
1137 }
1138
1139 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1140 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
1141}
a4fc5ed6 1142
5eb08b69 1143static enum drm_connector_status
f2b115e6 1144ironlake_dp_detect(struct drm_connector *connector)
5eb08b69
ZW		 1145{
1146 struct intel_output *intel_output = to_intel_output(connector);
1147 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1148 enum drm_connector_status status;
1149
1150 status = connector_status_disconnected;
1151 if (intel_dp_aux_native_read(intel_output,
1152 0x000, dp_priv->dpcd,
1153 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1154 {
1155 if (dp_priv->dpcd[0] != 0)
1156 status = connector_status_connected;
1157 }
1158 return status;
1159}
1160
a4fc5ed6
KP		 1161/**
1162 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1163 *
1164 * \return true if DP port is connected.
1165 * \return false if DP port is disconnected.
1166 */
1167static enum drm_connector_status
1168intel_dp_detect(struct drm_connector *connector)
1169{
1170 struct intel_output *intel_output = to_intel_output(connector);
1171 struct drm_device *dev = intel_output->base.dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1174 uint32_t temp, bit;
1175 enum drm_connector_status status;
1176
1177 dp_priv->has_audio = false;
1178
f2b115e6
AJ		 1179 if (IS_IRONLAKE(dev))
1180 return ironlake_dp_detect(connector);
5eb08b69 1181
a4fc5ed6
KP		 1182 temp = I915_READ(PORT_HOTPLUG_EN);
1183
1184 I915_WRITE(PORT_HOTPLUG_EN,
1185 temp |
1186 DPB_HOTPLUG_INT_EN |
1187 DPC_HOTPLUG_INT_EN |
1188 DPD_HOTPLUG_INT_EN);
1189
1190 POSTING_READ(PORT_HOTPLUG_EN);
1191
1192 switch (dp_priv->output_reg) {
1193 case DP_B:
1194 bit = DPB_HOTPLUG_INT_STATUS;
1195 break;
1196 case DP_C:
1197 bit = DPC_HOTPLUG_INT_STATUS;
1198 break;
1199 case DP_D:
1200 bit = DPD_HOTPLUG_INT_STATUS;
1201 break;
1202 default:
1203 return connector_status_unknown;
1204 }
1205
1206 temp = I915_READ(PORT_HOTPLUG_STAT);
1207
1208 if ((temp & bit) == 0)
1209 return connector_status_disconnected;
1210
1211 status = connector_status_disconnected;
1212 if (intel_dp_aux_native_read(intel_output,
1213 0x000, dp_priv->dpcd,
1214 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1215 {
1216 if (dp_priv->dpcd[0] != 0)
1217 status = connector_status_connected;
1218 }
1219 return status;
1220}
1221
1222static int intel_dp_get_modes(struct drm_connector *connector)
1223{
1224 struct intel_output *intel_output = to_intel_output(connector);
32f9d658
ZW		 1225 struct drm_device *dev = intel_output->base.dev;
1226 struct drm_i915_private *dev_priv = dev->dev_private;
1227 int ret;
a4fc5ed6
KP		 1228
1229 /* We should parse the EDID data and find out if it has an audio sink
1230 */
1231
32f9d658
ZW		 1232 ret = intel_ddc_get_modes(intel_output);
1233 if (ret)
1234 return ret;
1235
1236 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1237 if (IS_eDP(intel_output)) {
1238 if (dev_priv->panel_fixed_mode != NULL) {
1239 struct drm_display_mode *mode;
1240 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1241 drm_mode_probed_add(connector, mode);
1242 return 1;
1243 }
1244 }
1245 return 0;
a4fc5ed6
KP		 1246}
1247
1248static void
1249intel_dp_destroy (struct drm_connector *connector)
1250{
1251 struct intel_output *intel_output = to_intel_output(connector);
1252
1253 if (intel_output->i2c_bus)
1254 intel_i2c_destroy(intel_output->i2c_bus);
1255 drm_sysfs_connector_remove(connector);
1256 drm_connector_cleanup(connector);
1257 kfree(intel_output);
1258}
1259
1260static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1261 .dpms = intel_dp_dpms,
1262 .mode_fixup = intel_dp_mode_fixup,
1263 .prepare = intel_encoder_prepare,
1264 .mode_set = intel_dp_mode_set,
1265 .commit = intel_encoder_commit,
1266};
1267
1268static const struct drm_connector_funcs intel_dp_connector_funcs = {
1269 .dpms = drm_helper_connector_dpms,
1270 .save = intel_dp_save,
1271 .restore = intel_dp_restore,
1272 .detect = intel_dp_detect,
1273 .fill_modes = drm_helper_probe_single_connector_modes,
1274 .destroy = intel_dp_destroy,
1275};
1276
1277static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1278 .get_modes = intel_dp_get_modes,
1279 .mode_valid = intel_dp_mode_valid,
1280 .best_encoder = intel_best_encoder,
1281};
1282
1283static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1284{
1285 drm_encoder_cleanup(encoder);
1286}
1287
1288static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1289 .destroy = intel_dp_enc_destroy,
1290};
1291
c8110e52
KP		 1292void
1293intel_dp_hot_plug(struct intel_output *intel_output)
1294{
1295 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1296
1297 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1298 intel_dp_check_link_status(intel_output);
1299}
6207937d 1300
a4fc5ed6
KP		 1301void
1302intel_dp_init(struct drm_device *dev, int output_reg)
1303{
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct drm_connector *connector;
1306 struct intel_output *intel_output;
1307 struct intel_dp_priv *dp_priv;
5eb08b69 1308 const char *name = NULL;
a4fc5ed6
KP		 1309
1310 intel_output = kcalloc(sizeof(struct intel_output) +
1311 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1312 if (!intel_output)
1313 return;
1314
1315 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1316
1317 connector = &intel_output->base;
1318 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1319 DRM_MODE_CONNECTOR_DisplayPort);
1320 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1321
32f9d658
ZW		 1322 if (output_reg == DP_A)
1323 intel_output->type = INTEL_OUTPUT_EDP;
1324 else
1325 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1326
652af9d7 1327 if (output_reg == DP_B || output_reg == PCH_DP_B)
f8aed700 1328 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1329 else if (output_reg == DP_C || output_reg == PCH_DP_C)
f8aed700 1330 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1331 else if (output_reg == DP_D || output_reg == PCH_DP_D)
f8aed700
ML		 1332 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1333
6251ec0a 1334 if (IS_eDP(intel_output))
7c8460db 1335 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a
ZW		 1336
1337 intel_output->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1338 connector->interlace_allowed = true;
1339 connector->doublescan_allowed = 0;
1340
1341 dp_priv->intel_output = intel_output;
1342 dp_priv->output_reg = output_reg;
1343 dp_priv->has_audio = false;
c8110e52 1344 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6
KP		 1345 intel_output->dev_priv = dp_priv;
1346
1347 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1348 DRM_MODE_ENCODER_TMDS);
1349 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1350
1351 drm_mode_connector_attach_encoder(&intel_output->base,
1352 &intel_output->enc);
1353 drm_sysfs_connector_add(connector);
1354
1355 /* Set up the DDC bus. */
5eb08b69 1356 switch (output_reg) {
32f9d658
ZW		 1357 case DP_A:
1358 name = "DPDDC-A";
1359 break;
5eb08b69
ZW		 1360 case DP_B:
1361 case PCH_DP_B:
b01f2c3a
JB		 1362 dev_priv->hotplug_supported_mask |=
1363 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1364 name = "DPDDC-B";
1365 break;
1366 case DP_C:
1367 case PCH_DP_C:
b01f2c3a
JB		 1368 dev_priv->hotplug_supported_mask |=
1369 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1370 name = "DPDDC-C";
1371 break;
1372 case DP_D:
1373 case PCH_DP_D:
b01f2c3a
JB		 1374 dev_priv->hotplug_supported_mask |=
1375 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1376 name = "DPDDC-D";
1377 break;
1378 }
1379
1380 intel_dp_i2c_init(intel_output, name);
32f9d658 1381
a4fc5ed6 1382 intel_output->ddc_bus = &dp_priv->adapter;
c8110e52 1383 intel_output->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1384
32f9d658
ZW		 1385 if (output_reg == DP_A) {
1386 /* initialize panel mode from VBT if available for eDP */
1387 if (dev_priv->lfp_lvds_vbt_mode) {
1388 dev_priv->panel_fixed_mode =
1389 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1390 if (dev_priv->panel_fixed_mode) {
1391 dev_priv->panel_fixed_mode->type |=
1392 DRM_MODE_TYPE_PREFERRED;
1393 }
1394 }
1395 }
1396
a4fc5ed6
KP		 1397 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1398 * 0xd. Failure to do so will result in spurious interrupts being
1399 * generated on the port when a cable is not attached.
1400 */
1401 if (IS_G4X(dev) && !IS_GM45(dev)) {
1402 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1403 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1404 }
1405}
Linux kernel - Deliverables
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