Commit | Line | Data |
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0e32b39c DA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * 2014 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include "i915_drv.h" | |
28 | #include "intel_drv.h" | |
c6f95f27 | 29 | #include <drm/drm_atomic_helper.h> |
0e32b39c DA |
30 | #include <drm/drm_crtc_helper.h> |
31 | #include <drm/drm_edid.h> | |
32 | ||
33 | static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |
5cec258b | 34 | struct intel_crtc_state *pipe_config) |
0e32b39c DA |
35 | { |
36 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
37 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
38 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
e75f4771 ACO |
39 | struct drm_atomic_state *state; |
40 | int bpp, i; | |
04a60f9f | 41 | int lane_count, slots; |
7c5f93b0 | 42 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
da3ced29 ACO |
43 | struct drm_connector *drm_connector; |
44 | struct intel_connector *connector, *found = NULL; | |
45 | struct drm_connector_state *connector_state; | |
0e32b39c DA |
46 | int mst_pbn; |
47 | ||
48 | pipe_config->dp_encoder_is_mst = true; | |
49 | pipe_config->has_pch_encoder = false; | |
50 | pipe_config->has_dp_encoder = true; | |
51 | bpp = 24; | |
52 | /* | |
53 | * for MST we always configure max link bw - the spec doesn't | |
54 | * seem to suggest we should do otherwise. | |
55 | */ | |
56 | lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | |
ed4e9c1d | 57 | |
ed4e9c1d | 58 | |
90a6b7b0 | 59 | pipe_config->lane_count = lane_count; |
0e32b39c DA |
60 | |
61 | pipe_config->pipe_bpp = 24; | |
04a60f9f | 62 | pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); |
0e32b39c | 63 | |
e75f4771 ACO |
64 | state = pipe_config->base.state; |
65 | ||
da3ced29 ACO |
66 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
67 | connector = to_intel_connector(drm_connector); | |
e75f4771 | 68 | |
da3ced29 ACO |
69 | if (connector_state->best_encoder == &encoder->base) { |
70 | found = connector; | |
0e32b39c DA |
71 | break; |
72 | } | |
73 | } | |
74 | ||
75 | if (!found) { | |
76 | DRM_ERROR("can't find connector\n"); | |
77 | return false; | |
78 | } | |
79 | ||
3d52ccf5 LY |
80 | if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, found->port)) |
81 | pipe_config->has_audio = true; | |
aad941d5 | 82 | mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp); |
0e32b39c DA |
83 | |
84 | pipe_config->pbn = mst_pbn; | |
85 | slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn); | |
86 | ||
87 | intel_link_compute_m_n(bpp, lane_count, | |
88 | adjusted_mode->crtc_clock, | |
89 | pipe_config->port_clock, | |
90 | &pipe_config->dp_m_n); | |
91 | ||
92 | pipe_config->dp_m_n.tu = slots; | |
6fa2d197 | 93 | |
0e32b39c DA |
94 | return true; |
95 | ||
96 | } | |
97 | ||
98 | static void intel_mst_disable_dp(struct intel_encoder *encoder) | |
99 | { | |
100 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
101 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
102 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3d52ccf5 LY |
103 | struct drm_device *dev = encoder->base.dev; |
104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
105 | struct drm_crtc *crtc = encoder->base.crtc; | |
106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
107 | ||
0e32b39c DA |
108 | int ret; |
109 | ||
110 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
111 | ||
112 | drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, intel_mst->port); | |
113 | ||
114 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
115 | if (ret) { | |
116 | DRM_ERROR("failed to update payload %d\n", ret); | |
117 | } | |
3d52ccf5 LY |
118 | if (intel_crtc->config->has_audio) { |
119 | intel_audio_codec_disable(encoder); | |
120 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | |
121 | } | |
0e32b39c DA |
122 | } |
123 | ||
124 | static void intel_mst_post_disable_dp(struct intel_encoder *encoder) | |
125 | { | |
126 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
127 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
128 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
129 | ||
130 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
131 | ||
132 | /* this can fail */ | |
133 | drm_dp_check_act_status(&intel_dp->mst_mgr); | |
134 | /* and this can also fail */ | |
135 | drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
136 | ||
137 | drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, intel_mst->port); | |
138 | ||
139 | intel_dp->active_mst_links--; | |
140 | intel_mst->port = NULL; | |
141 | if (intel_dp->active_mst_links == 0) { | |
142 | intel_dig_port->base.post_disable(&intel_dig_port->base); | |
143 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); | |
144 | } | |
145 | } | |
146 | ||
147 | static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) | |
148 | { | |
149 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
150 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
151 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
152 | struct drm_device *dev = encoder->base.dev; | |
153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
154 | enum port port = intel_dig_port->port; | |
155 | int ret; | |
156 | uint32_t temp; | |
9b4fd8f2 | 157 | struct intel_connector *found = NULL, *connector; |
0e32b39c DA |
158 | int slots; |
159 | struct drm_crtc *crtc = encoder->base.crtc; | |
160 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
161 | ||
9b4fd8f2 ACO |
162 | for_each_intel_connector(dev, connector) { |
163 | if (connector->base.state->best_encoder == &encoder->base) { | |
164 | found = connector; | |
0e32b39c DA |
165 | break; |
166 | } | |
167 | } | |
168 | ||
169 | if (!found) { | |
170 | DRM_ERROR("can't find connector\n"); | |
171 | return; | |
172 | } | |
173 | ||
e85376cb ML |
174 | /* MST encoders are bound to a crtc, not to a connector, |
175 | * force the mapping here for get_hw_state. | |
176 | */ | |
177 | found->encoder = encoder; | |
178 | ||
0e32b39c DA |
179 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
180 | intel_mst->port = found->port; | |
181 | ||
182 | if (intel_dp->active_mst_links == 0) { | |
6a7e4f99 VS |
183 | intel_prepare_ddi_buffer(&intel_dig_port->base); |
184 | ||
d919161b | 185 | intel_ddi_clk_select(&intel_dig_port->base, intel_crtc->config); |
0e32b39c | 186 | |
901c2daf VS |
187 | intel_dp_set_link_params(intel_dp, intel_crtc->config); |
188 | ||
0e32b39c DA |
189 | intel_ddi_init_dp_buf_reg(&intel_dig_port->base); |
190 | ||
191 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
192 | ||
0e32b39c | 193 | intel_dp_start_link_train(intel_dp); |
0e32b39c DA |
194 | intel_dp_stop_link_train(intel_dp); |
195 | } | |
196 | ||
197 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | |
6e3c9717 ACO |
198 | intel_mst->port, |
199 | intel_crtc->config->pbn, &slots); | |
0e32b39c DA |
200 | if (ret == false) { |
201 | DRM_ERROR("failed to allocate vcpi\n"); | |
202 | return; | |
203 | } | |
204 | ||
205 | ||
206 | intel_dp->active_mst_links++; | |
207 | temp = I915_READ(DP_TP_STATUS(port)); | |
208 | I915_WRITE(DP_TP_STATUS(port), temp); | |
209 | ||
210 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
211 | } | |
212 | ||
213 | static void intel_mst_enable_dp(struct intel_encoder *encoder) | |
214 | { | |
215 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
216 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
217 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
218 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3d52ccf5 | 220 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
0e32b39c DA |
221 | enum port port = intel_dig_port->port; |
222 | int ret; | |
223 | ||
224 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
225 | ||
226 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_ACT_SENT), | |
227 | 1)) | |
228 | DRM_ERROR("Timed out waiting for ACT sent\n"); | |
229 | ||
230 | ret = drm_dp_check_act_status(&intel_dp->mst_mgr); | |
231 | ||
232 | ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
3d52ccf5 LY |
233 | |
234 | if (crtc->config->has_audio) { | |
235 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
236 | pipe_name(crtc->pipe)); | |
237 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); | |
238 | intel_audio_codec_enable(encoder); | |
239 | } | |
0e32b39c DA |
240 | } |
241 | ||
242 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, | |
243 | enum pipe *pipe) | |
244 | { | |
245 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
246 | *pipe = intel_mst->pipe; | |
247 | if (intel_mst->port) | |
248 | return true; | |
249 | return false; | |
250 | } | |
251 | ||
252 | static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, | |
5cec258b | 253 | struct intel_crtc_state *pipe_config) |
0e32b39c DA |
254 | { |
255 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
256 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
257 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
258 | struct drm_device *dev = encoder->base.dev; | |
259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0cb09a97 | 260 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
0e32b39c DA |
261 | u32 temp, flags = 0; |
262 | ||
263 | pipe_config->has_dp_encoder = true; | |
264 | ||
3d52ccf5 LY |
265 | pipe_config->has_audio = |
266 | intel_ddi_is_audio_enabled(dev_priv, crtc); | |
267 | ||
0e32b39c DA |
268 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
269 | if (temp & TRANS_DDI_PHSYNC) | |
270 | flags |= DRM_MODE_FLAG_PHSYNC; | |
271 | else | |
272 | flags |= DRM_MODE_FLAG_NHSYNC; | |
273 | if (temp & TRANS_DDI_PVSYNC) | |
274 | flags |= DRM_MODE_FLAG_PVSYNC; | |
275 | else | |
276 | flags |= DRM_MODE_FLAG_NVSYNC; | |
277 | ||
278 | switch (temp & TRANS_DDI_BPC_MASK) { | |
279 | case TRANS_DDI_BPC_6: | |
280 | pipe_config->pipe_bpp = 18; | |
281 | break; | |
282 | case TRANS_DDI_BPC_8: | |
283 | pipe_config->pipe_bpp = 24; | |
284 | break; | |
285 | case TRANS_DDI_BPC_10: | |
286 | pipe_config->pipe_bpp = 30; | |
287 | break; | |
288 | case TRANS_DDI_BPC_12: | |
289 | pipe_config->pipe_bpp = 36; | |
290 | break; | |
291 | default: | |
292 | break; | |
293 | } | |
2d112de7 | 294 | pipe_config->base.adjusted_mode.flags |= flags; |
90a6b7b0 VS |
295 | |
296 | pipe_config->lane_count = | |
297 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
298 | ||
0e32b39c DA |
299 | intel_dp_get_m_n(crtc, pipe_config); |
300 | ||
301 | intel_ddi_clock_get(&intel_dig_port->base, pipe_config); | |
302 | } | |
303 | ||
304 | static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) | |
305 | { | |
306 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
307 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
308 | struct edid *edid; | |
309 | int ret; | |
310 | ||
311 | edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); | |
312 | if (!edid) | |
313 | return 0; | |
314 | ||
315 | ret = intel_connector_update_modes(connector, edid); | |
316 | kfree(edid); | |
317 | ||
318 | return ret; | |
319 | } | |
320 | ||
321 | static enum drm_connector_status | |
f7f3d48a | 322 | intel_dp_mst_detect(struct drm_connector *connector, bool force) |
0e32b39c DA |
323 | { |
324 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
325 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
326 | ||
c6a0aed4 | 327 | return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
328 | } |
329 | ||
0e32b39c DA |
330 | static int |
331 | intel_dp_mst_set_property(struct drm_connector *connector, | |
332 | struct drm_property *property, | |
333 | uint64_t val) | |
334 | { | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static void | |
339 | intel_dp_mst_connector_destroy(struct drm_connector *connector) | |
340 | { | |
341 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
342 | ||
343 | if (!IS_ERR_OR_NULL(intel_connector->edid)) | |
344 | kfree(intel_connector->edid); | |
345 | ||
346 | drm_connector_cleanup(connector); | |
347 | kfree(connector); | |
348 | } | |
349 | ||
350 | static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { | |
4d688a2a | 351 | .dpms = drm_atomic_helper_connector_dpms, |
0e32b39c DA |
352 | .detect = intel_dp_mst_detect, |
353 | .fill_modes = drm_helper_probe_single_connector_modes, | |
354 | .set_property = intel_dp_mst_set_property, | |
2545e4a6 | 355 | .atomic_get_property = intel_connector_atomic_get_property, |
0e32b39c | 356 | .destroy = intel_dp_mst_connector_destroy, |
c6f95f27 | 357 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 358 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
0e32b39c DA |
359 | }; |
360 | ||
361 | static int intel_dp_mst_get_modes(struct drm_connector *connector) | |
362 | { | |
363 | return intel_dp_mst_get_ddc_modes(connector); | |
364 | } | |
365 | ||
366 | static enum drm_mode_status | |
367 | intel_dp_mst_mode_valid(struct drm_connector *connector, | |
368 | struct drm_display_mode *mode) | |
369 | { | |
832d5bfd MK |
370 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
371 | ||
0e32b39c DA |
372 | /* TODO - validate mode against available PBN for link */ |
373 | if (mode->clock < 10000) | |
374 | return MODE_CLOCK_LOW; | |
375 | ||
376 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
377 | return MODE_H_ILLEGAL; | |
378 | ||
832d5bfd MK |
379 | if (mode->clock > max_dotclk) |
380 | return MODE_CLOCK_HIGH; | |
381 | ||
0e32b39c DA |
382 | return MODE_OK; |
383 | } | |
384 | ||
459485ad DV |
385 | static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, |
386 | struct drm_connector_state *state) | |
387 | { | |
388 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
389 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
390 | struct intel_crtc *crtc = to_intel_crtc(state->crtc); | |
391 | ||
392 | return &intel_dp->mst_encoders[crtc->pipe]->base.base; | |
393 | } | |
394 | ||
0e32b39c DA |
395 | static struct drm_encoder *intel_mst_best_encoder(struct drm_connector *connector) |
396 | { | |
397 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
398 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
399 | return &intel_dp->mst_encoders[0]->base.base; | |
400 | } | |
401 | ||
402 | static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { | |
403 | .get_modes = intel_dp_mst_get_modes, | |
404 | .mode_valid = intel_dp_mst_mode_valid, | |
459485ad | 405 | .atomic_best_encoder = intel_mst_atomic_best_encoder, |
0e32b39c DA |
406 | .best_encoder = intel_mst_best_encoder, |
407 | }; | |
408 | ||
409 | static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) | |
410 | { | |
411 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
412 | ||
413 | drm_encoder_cleanup(encoder); | |
414 | kfree(intel_mst); | |
415 | } | |
416 | ||
417 | static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { | |
418 | .destroy = intel_dp_mst_encoder_destroy, | |
419 | }; | |
420 | ||
421 | static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) | |
422 | { | |
e85376cb | 423 | if (connector->encoder && connector->base.state->crtc) { |
0e32b39c DA |
424 | enum pipe pipe; |
425 | if (!connector->encoder->get_hw_state(connector->encoder, &pipe)) | |
426 | return false; | |
427 | return true; | |
428 | } | |
429 | return false; | |
430 | } | |
431 | ||
7296c849 CW |
432 | static void intel_connector_add_to_fbdev(struct intel_connector *connector) |
433 | { | |
0695726e | 434 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 435 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
436 | |
437 | if (dev_priv->fbdev) | |
438 | drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, | |
439 | &connector->base); | |
7296c849 CW |
440 | #endif |
441 | } | |
442 | ||
443 | static void intel_connector_remove_from_fbdev(struct intel_connector *connector) | |
444 | { | |
0695726e | 445 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 446 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
447 | |
448 | if (dev_priv->fbdev) | |
449 | drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, | |
450 | &connector->base); | |
7296c849 CW |
451 | #endif |
452 | } | |
453 | ||
12e6cecd | 454 | static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) |
0e32b39c DA |
455 | { |
456 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
457 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
458 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
0e32b39c DA |
459 | struct intel_connector *intel_connector; |
460 | struct drm_connector *connector; | |
461 | int i; | |
462 | ||
9bdbd0b9 | 463 | intel_connector = intel_connector_alloc(); |
0e32b39c DA |
464 | if (!intel_connector) |
465 | return NULL; | |
466 | ||
467 | connector = &intel_connector->base; | |
468 | drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); | |
469 | drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); | |
470 | ||
471 | intel_connector->unregister = intel_connector_unregister; | |
472 | intel_connector->get_hw_state = intel_dp_mst_get_hw_state; | |
473 | intel_connector->mst_port = intel_dp; | |
474 | intel_connector->port = port; | |
475 | ||
476 | for (i = PIPE_A; i <= PIPE_C; i++) { | |
477 | drm_mode_connector_attach_encoder(&intel_connector->base, | |
478 | &intel_dp->mst_encoders[i]->base.base); | |
479 | } | |
480 | intel_dp_add_properties(intel_dp, connector); | |
481 | ||
482 | drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); | |
6f134d7b DA |
483 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
484 | ||
0e32b39c | 485 | drm_mode_connector_set_path_property(connector, pathprop); |
d9515c5e DA |
486 | return connector; |
487 | } | |
488 | ||
489 | static void intel_dp_register_mst_connector(struct drm_connector *connector) | |
490 | { | |
491 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
492 | struct drm_device *dev = connector->dev; | |
8bb4da1d | 493 | drm_modeset_lock_all(dev); |
7296c849 | 494 | intel_connector_add_to_fbdev(intel_connector); |
8bb4da1d | 495 | drm_modeset_unlock_all(dev); |
0e32b39c | 496 | drm_connector_register(&intel_connector->base); |
0e32b39c DA |
497 | } |
498 | ||
499 | static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, | |
500 | struct drm_connector *connector) | |
501 | { | |
502 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
503 | struct drm_device *dev = connector->dev; | |
20fae983 | 504 | |
1f771755 L |
505 | intel_connector->unregister(intel_connector); |
506 | ||
0e32b39c | 507 | /* need to nuke the connector */ |
8bb4da1d | 508 | drm_modeset_lock_all(dev); |
20fae983 ML |
509 | if (connector->state->crtc) { |
510 | struct drm_mode_set set; | |
511 | int ret; | |
512 | ||
513 | memset(&set, 0, sizeof(set)); | |
514 | set.crtc = connector->state->crtc, | |
515 | ||
516 | ret = drm_atomic_helper_set_config(&set); | |
517 | ||
518 | WARN(ret, "Disabling mst crtc failed with %i\n", ret); | |
519 | } | |
0e32b39c | 520 | |
7296c849 | 521 | intel_connector_remove_from_fbdev(intel_connector); |
0e32b39c | 522 | drm_connector_cleanup(connector); |
8bb4da1d | 523 | drm_modeset_unlock_all(dev); |
0e32b39c | 524 | |
0e32b39c DA |
525 | kfree(intel_connector); |
526 | DRM_DEBUG_KMS("\n"); | |
527 | } | |
528 | ||
529 | static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) | |
530 | { | |
531 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
532 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
533 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
534 | ||
535 | drm_kms_helper_hotplug_event(dev); | |
536 | } | |
537 | ||
69a0f89c | 538 | static const struct drm_dp_mst_topology_cbs mst_cbs = { |
0e32b39c | 539 | .add_connector = intel_dp_add_mst_connector, |
d9515c5e | 540 | .register_connector = intel_dp_register_mst_connector, |
0e32b39c DA |
541 | .destroy_connector = intel_dp_destroy_mst_connector, |
542 | .hotplug = intel_dp_mst_hotplug, | |
543 | }; | |
544 | ||
545 | static struct intel_dp_mst_encoder * | |
546 | intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) | |
547 | { | |
548 | struct intel_dp_mst_encoder *intel_mst; | |
549 | struct intel_encoder *intel_encoder; | |
550 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
551 | ||
552 | intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); | |
553 | ||
554 | if (!intel_mst) | |
555 | return NULL; | |
556 | ||
557 | intel_mst->pipe = pipe; | |
558 | intel_encoder = &intel_mst->base; | |
559 | intel_mst->primary = intel_dig_port; | |
560 | ||
561 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, | |
13a3d91f | 562 | DRM_MODE_ENCODER_DPMST, NULL); |
0e32b39c DA |
563 | |
564 | intel_encoder->type = INTEL_OUTPUT_DP_MST; | |
565 | intel_encoder->crtc_mask = 0x7; | |
566 | intel_encoder->cloneable = 0; | |
567 | ||
568 | intel_encoder->compute_config = intel_dp_mst_compute_config; | |
569 | intel_encoder->disable = intel_mst_disable_dp; | |
570 | intel_encoder->post_disable = intel_mst_post_disable_dp; | |
571 | intel_encoder->pre_enable = intel_mst_pre_enable_dp; | |
572 | intel_encoder->enable = intel_mst_enable_dp; | |
573 | intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; | |
574 | intel_encoder->get_config = intel_dp_mst_enc_get_config; | |
575 | ||
576 | return intel_mst; | |
577 | ||
578 | } | |
579 | ||
580 | static bool | |
581 | intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) | |
582 | { | |
583 | int i; | |
584 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
585 | ||
586 | for (i = PIPE_A; i <= PIPE_C; i++) | |
587 | intel_dp->mst_encoders[i] = intel_dp_create_fake_mst_encoder(intel_dig_port, i); | |
588 | return true; | |
589 | } | |
590 | ||
591 | int | |
592 | intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) | |
593 | { | |
594 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
595 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
596 | int ret; | |
597 | ||
598 | intel_dp->can_mst = true; | |
599 | intel_dp->mst_mgr.cbs = &mst_cbs; | |
600 | ||
601 | /* create encoders */ | |
602 | intel_dp_create_fake_mst_encoders(intel_dig_port); | |
603 | ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, dev->dev, &intel_dp->aux, 16, 3, conn_base_id); | |
604 | if (ret) { | |
605 | intel_dp->can_mst = false; | |
606 | return ret; | |
607 | } | |
608 | return 0; | |
609 | } | |
610 | ||
611 | void | |
612 | intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) | |
613 | { | |
614 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
615 | ||
616 | if (!intel_dp->can_mst) | |
617 | return; | |
618 | ||
619 | drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); | |
620 | /* encoders will get killed by normal cleanup */ | |
621 | } |