Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
80824003 | 29 | #include "i915_drv.h" |
79e53945 | 30 | #include "drm_crtc.h" |
79e53945 | 31 | #include "drm_crtc_helper.h" |
37811fcc | 32 | #include "drm_fb_helper.h" |
913d8d11 | 33 | |
481b6af3 | 34 | #define _wait_for(COND, MS, W) ({ \ |
913d8d11 CW |
35 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ |
36 | int ret__ = 0; \ | |
0206e353 | 37 | while (!(COND)) { \ |
913d8d11 CW |
38 | if (time_after(jiffies, timeout__)) { \ |
39 | ret__ = -ETIMEDOUT; \ | |
40 | break; \ | |
41 | } \ | |
9f01b250 | 42 | if (W && !(in_atomic() || in_dbg_master())) msleep(W); \ |
913d8d11 CW |
43 | } \ |
44 | ret__; \ | |
45 | }) | |
46 | ||
481b6af3 CW |
47 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
48 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
49 | ||
ec5da01e CW |
50 | #define MSLEEP(x) do { \ |
51 | if (in_dbg_master()) \ | |
0206e353 | 52 | mdelay(x); \ |
ec5da01e CW |
53 | else \ |
54 | msleep(x); \ | |
0206e353 | 55 | } while (0) |
ec5da01e | 56 | |
021357ac CW |
57 | #define KHz(x) (1000*x) |
58 | #define MHz(x) KHz(1000*x) | |
59 | ||
79e53945 JB |
60 | /* |
61 | * Display related stuff | |
62 | */ | |
63 | ||
64 | /* store information about an Ixxx DVO */ | |
65 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
66 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
67 | #define MAX_OUTPUTS 6 | |
68 | /* maximum connectors per crtcs in the mode set */ | |
69 | #define INTELFB_CONN_LIMIT 4 | |
70 | ||
71 | #define INTEL_I2C_BUS_DVO 1 | |
72 | #define INTEL_I2C_BUS_SDVO 2 | |
73 | ||
74 | /* these are outputs from the chip - integrated only | |
75 | external chips are via DVO or SDVO output */ | |
76 | #define INTEL_OUTPUT_UNUSED 0 | |
77 | #define INTEL_OUTPUT_ANALOG 1 | |
78 | #define INTEL_OUTPUT_DVO 2 | |
79 | #define INTEL_OUTPUT_SDVO 3 | |
80 | #define INTEL_OUTPUT_LVDS 4 | |
81 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 82 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 83 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 84 | #define INTEL_OUTPUT_EDP 8 |
79e53945 | 85 | |
f8aed700 ML |
86 | /* Intel Pipe Clone Bit */ |
87 | #define INTEL_HDMIB_CLONE_BIT 1 | |
88 | #define INTEL_HDMIC_CLONE_BIT 2 | |
89 | #define INTEL_HDMID_CLONE_BIT 3 | |
90 | #define INTEL_HDMIE_CLONE_BIT 4 | |
91 | #define INTEL_HDMIF_CLONE_BIT 5 | |
92 | #define INTEL_SDVO_NON_TV_CLONE_BIT 6 | |
93 | #define INTEL_SDVO_TV_CLONE_BIT 7 | |
94 | #define INTEL_SDVO_LVDS_CLONE_BIT 8 | |
95 | #define INTEL_ANALOG_CLONE_BIT 9 | |
96 | #define INTEL_TV_CLONE_BIT 10 | |
97 | #define INTEL_DP_B_CLONE_BIT 11 | |
98 | #define INTEL_DP_C_CLONE_BIT 12 | |
99 | #define INTEL_DP_D_CLONE_BIT 13 | |
100 | #define INTEL_LVDS_CLONE_BIT 14 | |
101 | #define INTEL_DVO_TMDS_CLONE_BIT 15 | |
102 | #define INTEL_DVO_LVDS_CLONE_BIT 16 | |
7c8460db | 103 | #define INTEL_EDP_CLONE_BIT 17 |
f8aed700 | 104 | |
79e53945 JB |
105 | #define INTEL_DVO_CHIP_NONE 0 |
106 | #define INTEL_DVO_CHIP_LVDS 1 | |
107 | #define INTEL_DVO_CHIP_TMDS 2 | |
108 | #define INTEL_DVO_CHIP_TVOUT 4 | |
109 | ||
6c9547ff CW |
110 | /* drm_display_mode->private_flags */ |
111 | #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) | |
112 | #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) | |
113 | ||
114 | static inline void | |
115 | intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, | |
116 | int multiplier) | |
117 | { | |
118 | mode->clock *= multiplier; | |
119 | mode->private_flags |= multiplier; | |
120 | } | |
121 | ||
122 | static inline int | |
123 | intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) | |
124 | { | |
125 | return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; | |
126 | } | |
127 | ||
79e53945 JB |
128 | struct intel_framebuffer { |
129 | struct drm_framebuffer base; | |
05394f39 | 130 | struct drm_i915_gem_object *obj; |
79e53945 JB |
131 | }; |
132 | ||
37811fcc CW |
133 | struct intel_fbdev { |
134 | struct drm_fb_helper helper; | |
135 | struct intel_framebuffer ifb; | |
136 | struct list_head fbdev_list; | |
137 | struct drm_display_mode *our_mode; | |
138 | }; | |
79e53945 | 139 | |
21d40d37 | 140 | struct intel_encoder { |
4ef69c7a | 141 | struct drm_encoder base; |
79e53945 | 142 | int type; |
e2f0ba97 | 143 | bool needs_tv_clock; |
21d40d37 | 144 | void (*hot_plug)(struct intel_encoder *); |
f8aed700 ML |
145 | int crtc_mask; |
146 | int clone_mask; | |
79e53945 JB |
147 | }; |
148 | ||
5daa55eb ZW |
149 | struct intel_connector { |
150 | struct drm_connector base; | |
df0e9248 | 151 | struct intel_encoder *encoder; |
5daa55eb ZW |
152 | }; |
153 | ||
79e53945 JB |
154 | struct intel_crtc { |
155 | struct drm_crtc base; | |
80824003 JB |
156 | enum pipe pipe; |
157 | enum plane plane; | |
79e53945 JB |
158 | u8 lut_r[256], lut_g[256], lut_b[256]; |
159 | int dpms_mode; | |
f7abfe8b | 160 | bool active; /* is the crtc on? independent of the dpms mode */ |
652c393a JB |
161 | bool busy; /* is scanout buffer being updated frequently? */ |
162 | struct timer_list idle_timer; | |
163 | bool lowfreq_avail; | |
02e792fb | 164 | struct intel_overlay *overlay; |
6b95a207 | 165 | struct intel_unpin_work *unpin_work; |
77ffb597 | 166 | int fdi_lanes; |
cda4b7d3 | 167 | |
05394f39 | 168 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
169 | uint32_t cursor_addr; |
170 | int16_t cursor_x, cursor_y; | |
171 | int16_t cursor_width, cursor_height; | |
6b383a7f | 172 | bool cursor_visible; |
5a354204 | 173 | unsigned int bpp; |
4b645f14 JB |
174 | |
175 | bool no_pll; /* tertiary pipe for IVB */ | |
176 | bool use_pll_a; | |
79e53945 JB |
177 | }; |
178 | ||
179 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) | |
5daa55eb | 180 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 181 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 JB |
182 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
183 | ||
45187ace JB |
184 | #define DIP_HEADER_SIZE 5 |
185 | ||
3c17fe4b DH |
186 | #define DIP_TYPE_AVI 0x82 |
187 | #define DIP_VERSION_AVI 0x2 | |
188 | #define DIP_LEN_AVI 13 | |
189 | ||
26005210 | 190 | #define DIP_TYPE_SPD 0x83 |
c0864cb3 JB |
191 | #define DIP_VERSION_SPD 0x1 |
192 | #define DIP_LEN_SPD 25 | |
193 | #define DIP_SPD_UNKNOWN 0 | |
194 | #define DIP_SPD_DSTB 0x1 | |
195 | #define DIP_SPD_DVDP 0x2 | |
196 | #define DIP_SPD_DVHS 0x3 | |
197 | #define DIP_SPD_HDDVR 0x4 | |
198 | #define DIP_SPD_DVC 0x5 | |
199 | #define DIP_SPD_DSC 0x6 | |
200 | #define DIP_SPD_VCD 0x7 | |
201 | #define DIP_SPD_GAME 0x8 | |
202 | #define DIP_SPD_PC 0x9 | |
203 | #define DIP_SPD_BD 0xa | |
204 | #define DIP_SPD_SCD 0xb | |
205 | ||
3c17fe4b DH |
206 | struct dip_infoframe { |
207 | uint8_t type; /* HB0 */ | |
208 | uint8_t ver; /* HB1 */ | |
209 | uint8_t len; /* HB2 - body len, not including checksum */ | |
210 | uint8_t ecc; /* Header ECC */ | |
211 | uint8_t checksum; /* PB0 */ | |
212 | union { | |
213 | struct { | |
214 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ | |
215 | uint8_t Y_A_B_S; | |
216 | /* PB2 - C 7:6, M 5:4, R 3:0 */ | |
217 | uint8_t C_M_R; | |
218 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ | |
219 | uint8_t ITC_EC_Q_SC; | |
220 | /* PB4 - VIC 6:0 */ | |
221 | uint8_t VIC; | |
222 | /* PB5 - PR 3:0 */ | |
223 | uint8_t PR; | |
224 | /* PB6 to PB13 */ | |
225 | uint16_t top_bar_end; | |
226 | uint16_t bottom_bar_start; | |
227 | uint16_t left_bar_end; | |
228 | uint16_t right_bar_start; | |
229 | } avi; | |
c0864cb3 JB |
230 | struct { |
231 | uint8_t vn[8]; | |
232 | uint8_t pd[16]; | |
233 | uint8_t sdi; | |
234 | } spd; | |
3c17fe4b DH |
235 | uint8_t payload[27]; |
236 | } __attribute__ ((packed)) body; | |
237 | } __attribute__((packed)); | |
238 | ||
f875c15a CW |
239 | static inline struct drm_crtc * |
240 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
241 | { | |
242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
243 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
244 | } | |
245 | ||
417ae147 CW |
246 | static inline struct drm_crtc * |
247 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
248 | { | |
249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
250 | return dev_priv->plane_to_crtc_mapping[plane]; | |
251 | } | |
252 | ||
4e5359cd SF |
253 | struct intel_unpin_work { |
254 | struct work_struct work; | |
255 | struct drm_device *dev; | |
05394f39 CW |
256 | struct drm_i915_gem_object *old_fb_obj; |
257 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd SF |
258 | struct drm_pending_vblank_event *event; |
259 | int pending; | |
260 | bool enable_stall_check; | |
261 | }; | |
262 | ||
1630fe75 CW |
263 | struct intel_fbc_work { |
264 | struct delayed_work work; | |
265 | struct drm_crtc *crtc; | |
266 | struct drm_framebuffer *fb; | |
267 | int interval; | |
268 | }; | |
269 | ||
335af9a2 | 270 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f899fc64 | 271 | extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus); |
f0217c42 | 272 | |
3f43c48d | 273 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
e953fd7b CW |
274 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
275 | ||
79e53945 | 276 | extern void intel_crt_init(struct drm_device *dev); |
7d57382e | 277 | extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); |
3c17fe4b | 278 | void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
7d57382e | 279 | extern bool intel_sdvo_init(struct drm_device *dev, int output_device); |
79e53945 JB |
280 | extern void intel_dvo_init(struct drm_device *dev); |
281 | extern void intel_tv_init(struct drm_device *dev); | |
05394f39 CW |
282 | extern void intel_mark_busy(struct drm_device *dev, |
283 | struct drm_i915_gem_object *obj); | |
c5d1b51d | 284 | extern bool intel_lvds_init(struct drm_device *dev); |
a4fc5ed6 KP |
285 | extern void intel_dp_init(struct drm_device *dev, int dp_reg); |
286 | void | |
287 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
288 | struct drm_display_mode *adjusted_mode); | |
cb0953d7 | 289 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
0206e353 | 290 | extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
814948ad | 291 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
32f9d658 | 292 | |
a9573556 | 293 | /* intel_panel.c */ |
1d8e1c75 CW |
294 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
295 | struct drm_display_mode *adjusted_mode); | |
296 | extern void intel_pch_panel_fitting(struct drm_device *dev, | |
297 | int fitting_mode, | |
298 | struct drm_display_mode *mode, | |
299 | struct drm_display_mode *adjusted_mode); | |
a9573556 CW |
300 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
301 | extern u32 intel_panel_get_backlight(struct drm_device *dev); | |
302 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); | |
aaa6fd2a | 303 | extern int intel_panel_setup_backlight(struct drm_device *dev); |
47356eb6 CW |
304 | extern void intel_panel_enable_backlight(struct drm_device *dev); |
305 | extern void intel_panel_disable_backlight(struct drm_device *dev); | |
aaa6fd2a | 306 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
fe16d949 | 307 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
1d8e1c75 | 308 | |
79e53945 | 309 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
0206e353 AJ |
310 | extern void intel_encoder_prepare(struct drm_encoder *encoder); |
311 | extern void intel_encoder_commit(struct drm_encoder *encoder); | |
ea5b213a | 312 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
79e53945 | 313 | |
df0e9248 CW |
314 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
315 | { | |
316 | return to_intel_connector(connector)->encoder; | |
317 | } | |
318 | ||
319 | extern void intel_connector_attach_encoder(struct intel_connector *connector, | |
320 | struct intel_encoder *encoder); | |
321 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
322 | |
323 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
324 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
325 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
326 | struct drm_file *file_priv); | |
9d0498a2 | 327 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
58e10eb9 | 328 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
8261b191 CW |
329 | |
330 | struct intel_load_detect_pipe { | |
d2dff872 | 331 | struct drm_framebuffer *release_fb; |
8261b191 CW |
332 | bool load_detect_temp; |
333 | int dpms_mode; | |
334 | }; | |
7173188d CW |
335 | extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
336 | struct drm_connector *connector, | |
337 | struct drm_display_mode *mode, | |
8261b191 | 338 | struct intel_load_detect_pipe *old); |
21d40d37 | 339 | extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 340 | struct drm_connector *connector, |
8261b191 | 341 | struct intel_load_detect_pipe *old); |
79e53945 | 342 | |
79e53945 JB |
343 | extern void intelfb_restore(void); |
344 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
345 | u16 blue, int regno); | |
b8c00ac5 DA |
346 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
347 | u16 *blue, int regno); | |
0cdab21f | 348 | extern void intel_enable_clock_gating(struct drm_device *dev); |
f97108d1 JB |
349 | extern void ironlake_enable_drps(struct drm_device *dev); |
350 | extern void ironlake_disable_drps(struct drm_device *dev); | |
3b8d8d91 | 351 | extern void gen6_enable_rps(struct drm_i915_private *dev_priv); |
23b2f8bb | 352 | extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv); |
3b8d8d91 | 353 | extern void gen6_disable_rps(struct drm_device *dev); |
48fcfc88 | 354 | extern void intel_init_emon(struct drm_device *dev); |
79e53945 | 355 | |
127bd2ac | 356 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 357 | struct drm_i915_gem_object *obj, |
919926ae | 358 | struct intel_ring_buffer *pipelined); |
127bd2ac | 359 | |
38651674 DA |
360 | extern int intel_framebuffer_init(struct drm_device *dev, |
361 | struct intel_framebuffer *ifb, | |
308e5bcb | 362 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 363 | struct drm_i915_gem_object *obj); |
38651674 DA |
364 | extern int intel_fbdev_init(struct drm_device *dev); |
365 | extern void intel_fbdev_fini(struct drm_device *dev); | |
28d52043 | 366 | |
6b95a207 KH |
367 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
368 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 369 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 370 | |
02e792fb DV |
371 | extern void intel_setup_overlay(struct drm_device *dev); |
372 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
ce453d81 | 373 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
02e792fb DV |
374 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
375 | struct drm_file *file_priv); | |
376 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
377 | struct drm_file *file_priv); | |
4abe3520 | 378 | |
eb1f8e4f | 379 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
e8e7a2b8 | 380 | extern void intel_fb_restore_mode(struct drm_device *dev); |
645c62a5 JB |
381 | |
382 | extern void intel_init_clock_gating(struct drm_device *dev); | |
e0dac65e WF |
383 | extern void intel_write_eld(struct drm_encoder *encoder, |
384 | struct drm_display_mode *mode); | |
d4270e57 JB |
385 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
386 | ||
79e53945 | 387 | #endif /* __INTEL_DRV_H__ */ |