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drm/i915: wait_event_timeout's timeout is in jiffies
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
57f350b6 53#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
57f350b6
JB		 64})
65
481b6af3
CW		 66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68
021357ac
CW		 69#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x)
71
79e53945
JB		 72/*
73 * Display related stuff
74 */
75
76/* store information about an Ixxx DVO */
77/* The i830->i865 use multiple DVOs with multiple i2cs */
78/* the i915, i945 have a single sDVO i2c bus - which is different */
79#define MAX_OUTPUTS 6
80/* maximum connectors per crtcs in the mode set */
81#define INTELFB_CONN_LIMIT 4
82
83#define INTEL_I2C_BUS_DVO 1
84#define INTEL_I2C_BUS_SDVO 2
85
86/* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88#define INTEL_OUTPUT_UNUSED 0
89#define INTEL_OUTPUT_ANALOG 1
90#define INTEL_OUTPUT_DVO 2
91#define INTEL_OUTPUT_SDVO 3
92#define INTEL_OUTPUT_LVDS 4
93#define INTEL_OUTPUT_TVOUT 5
7d57382e 94#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 95#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 96#define INTEL_OUTPUT_EDP 8
00c09d70 97#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 98
99#define INTEL_DVO_CHIP_NONE 0
100#define INTEL_DVO_CHIP_LVDS 1
101#define INTEL_DVO_CHIP_TMDS 2
102#define INTEL_DVO_CHIP_TVOUT 4
103
6c9547ff
CW		 104/* drm_display_mode->private_flags */
105#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
106#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 107#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 108/* This flag must be set by the encoder's mode_fixup if it changes the crtc
109 * timings in the mode to prevent the crtc fixup from overwriting them.
110 * Currently only lvds needs that. */
111#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
3685a8f3
VS		 112/*
113 * Set when limited 16-235 (as opposed to full 0-255) RGB color range is
114 * to be used.
115 */
116#define INTEL_MODE_LIMITED_COLOR_RANGE (0x40)
6c9547ff
CW		 117
118static inline void
119intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
120 int multiplier)
121{
122 mode->clock *= multiplier;
123 mode->private_flags |= multiplier;
124}
125
126static inline int
127intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
128{
129 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
130}
131
79e53945
JB		 132struct intel_framebuffer {
133 struct drm_framebuffer base;
05394f39 134 struct drm_i915_gem_object *obj;
79e53945
JB		 135};
136
37811fcc
CW		 137struct intel_fbdev {
138 struct drm_fb_helper helper;
139 struct intel_framebuffer ifb;
140 struct list_head fbdev_list;
141 struct drm_display_mode *our_mode;
142};
79e53945 143
21d40d37 144struct intel_encoder {
4ef69c7a 145 struct drm_encoder base;
9a935856
DV		 146 /*
147 * The new crtc this encoder will be driven from. Only differs from
148 * base->crtc while a modeset is in progress.
149 */
150 struct intel_crtc *new_crtc;
151
79e53945 152 int type;
e2f0ba97 153 bool needs_tv_clock;
66a9278e
DV		 154 /*
155 * Intel hw has only one MUX where encoders could be clone, hence a
156 * simple flag is enough to compute the possible_clones mask.
157 */
158 bool cloneable;
5ab432ef 159 bool connectors_active;
21d40d37 160 void (*hot_plug)(struct intel_encoder *);
dafd226c 161 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 162 void (*pre_enable)(struct intel_encoder *);
ef9c3aee
DV		 163 void (*enable)(struct intel_encoder *);
164 void (*disable)(struct intel_encoder *);
bf49ec8c 165 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 166 /* Read out the current hw state of this connector, returning true if
167 * the encoder is active. If the encoder is enabled it also set the pipe
168 * it is connected to in the pipe parameter. */
169 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 170 int crtc_mask;
79e53945
JB		 171};
172
1d508706 173struct intel_panel {
dd06f90e 174 struct drm_display_mode *fixed_mode;
4d891523 175 int fitting_mode;
1d508706
JN		 176};
177
5daa55eb
ZW		 178struct intel_connector {
179 struct drm_connector base;
9a935856
DV		 180 /*
181 * The fixed encoder this connector is connected to.
182 */
df0e9248 183 struct intel_encoder *encoder;
9a935856
DV		 184
185 /*
186 * The new encoder this connector will be driven. Only differs from
187 * encoder while a modeset is in progress.
188 */
189 struct intel_encoder *new_encoder;
190
f0947c37
DV		 191 /* Reads out the current hw, returning true if the connector is enabled
192 * and active (i.e. dpms ON state). */
193 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 194
195 /* Panel info for eDP and LVDS */
196 struct intel_panel panel;
9cd300e0
JN		 197
198 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
199 struct edid *edid;
5daa55eb
ZW		 200};
201
79e53945
JB		 202struct intel_crtc {
203 struct drm_crtc base;
80824003
JB		 204 enum pipe pipe;
205 enum plane plane;
a5c961d1 206 enum transcoder cpu_transcoder;
79e53945 207 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 208 /*
209 * Whether the crtc and the connected output pipeline is active. Implies
210 * that crtc->enabled is set, i.e. the current mode configuration has
211 * some outputs connected to this crtc.
08a48469
DV		 212 */
213 bool active;
7b9f35a6 214 bool eld_vld;
93314b5b 215 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 216 bool lowfreq_avail;
02e792fb 217 struct intel_overlay *overlay;
6b95a207 218 struct intel_unpin_work *unpin_work;
77ffb597 219 int fdi_lanes;
cda4b7d3 220
b4a98e57
CW		 221 atomic_t unpin_work_count;
222
e506a0c6
DV		 223 /* Display surface base address adjustement for pageflips. Note that on
224 * gen4+ this only adjusts up to a tile, offsets within a tile are
225 * handled in the hw itself (with the TILEOFF register). */
226 unsigned long dspaddr_offset;
227
05394f39 228 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 229 uint32_t cursor_addr;
230 int16_t cursor_x, cursor_y;
231 int16_t cursor_width, cursor_height;
6b383a7f 232 bool cursor_visible;
5a354204 233 unsigned int bpp;
4b645f14 234
ee7b9f93
JB		 235 /* We can share PLLs across outputs if the timings match */
236 struct intel_pch_pll *pch_pll;
6441ab5f 237 uint32_t ddi_pll_sel;
10d83730
VS		 238
239 /* reset counter value when the last flip was submitted */
240 unsigned int reset_counter;
79e53945
JB		 241};
242
b840d907
JB		 243struct intel_plane {
244 struct drm_plane base;
245 enum pipe pipe;
246 struct drm_i915_gem_object *obj;
2d354c34 247 bool can_scale;
b840d907
JB		 248 int max_downscale;
249 u32 lut_r[1024], lut_g[1024], lut_b[1024];
250 void (*update_plane)(struct drm_plane *plane,
251 struct drm_framebuffer *fb,
252 struct drm_i915_gem_object *obj,
253 int crtc_x, int crtc_y,
254 unsigned int crtc_w, unsigned int crtc_h,
255 uint32_t x, uint32_t y,
256 uint32_t src_w, uint32_t src_h);
257 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 258 int (*update_colorkey)(struct drm_plane *plane,
259 struct drm_intel_sprite_colorkey *key);
260 void (*get_colorkey)(struct drm_plane *plane,
261 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 262};
263
b445e3b0
ED		 264struct intel_watermark_params {
265 unsigned long fifo_size;
266 unsigned long max_wm;
267 unsigned long default_wm;
268 unsigned long guard_size;
269 unsigned long cacheline_size;
270};
271
272struct cxsr_latency {
273 int is_desktop;
274 int is_ddr3;
275 unsigned long fsb_freq;
276 unsigned long mem_freq;
277 unsigned long display_sr;
278 unsigned long display_hpll_disable;
279 unsigned long cursor_sr;
280 unsigned long cursor_hpll_disable;
281};
282
79e53945 283#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 284#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 285#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 286#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 287#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 288
45187ace
JB		 289#define DIP_HEADER_SIZE 5
290
3c17fe4b
DH		 291#define DIP_TYPE_AVI 0x82
292#define DIP_VERSION_AVI 0x2
293#define DIP_LEN_AVI 13
c846b619
PZ		 294#define DIP_AVI_PR_1 0
295#define DIP_AVI_PR_2 1
abedc077
VS		 296#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
297#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
298#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
3c17fe4b 299
26005210 300#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 301#define DIP_VERSION_SPD 0x1
302#define DIP_LEN_SPD 25
303#define DIP_SPD_UNKNOWN 0
304#define DIP_SPD_DSTB 0x1
305#define DIP_SPD_DVDP 0x2
306#define DIP_SPD_DVHS 0x3
307#define DIP_SPD_HDDVR 0x4
308#define DIP_SPD_DVC 0x5
309#define DIP_SPD_DSC 0x6
310#define DIP_SPD_VCD 0x7
311#define DIP_SPD_GAME 0x8
312#define DIP_SPD_PC 0x9
313#define DIP_SPD_BD 0xa
314#define DIP_SPD_SCD 0xb
315
3c17fe4b
DH		 316struct dip_infoframe {
317 uint8_t type; /* HB0 */
318 uint8_t ver; /* HB1 */
319 uint8_t len; /* HB2 - body len, not including checksum */
320 uint8_t ecc; /* Header ECC */
321 uint8_t checksum; /* PB0 */
322 union {
323 struct {
324 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
325 uint8_t Y_A_B_S;
326 /* PB2 - C 7:6, M 5:4, R 3:0 */
327 uint8_t C_M_R;
328 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
329 uint8_t ITC_EC_Q_SC;
330 /* PB4 - VIC 6:0 */
331 uint8_t VIC;
0aa534df
PZ		 332 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
333 uint8_t YQ_CN_PR;
3c17fe4b
DH		 334 /* PB6 to PB13 */
335 uint16_t top_bar_end;
336 uint16_t bottom_bar_start;
337 uint16_t left_bar_end;
338 uint16_t right_bar_start;
81014b9d 339 } __attribute__ ((packed)) avi;
c0864cb3
JB		 340 struct {
341 uint8_t vn[8];
342 uint8_t pd[16];
343 uint8_t sdi;
81014b9d 344 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 345 uint8_t payload[27];
346 } __attribute__ ((packed)) body;
347} __attribute__((packed));
348
f5bbfca3 349struct intel_hdmi {
f5bbfca3
ED		 350 u32 sdvox_reg;
351 int ddc_bus;
f5bbfca3 352 uint32_t color_range;
55bc60db 353 bool color_range_auto;
f5bbfca3
ED		 354 bool has_hdmi_sink;
355 bool has_audio;
356 enum hdmi_force_audio force_audio;
abedc077 357 bool rgb_quant_range_selectable;
f5bbfca3
ED		 358 void (*write_infoframe)(struct drm_encoder *encoder,
359 struct dip_infoframe *frame);
687f4d06
PZ		 360 void (*set_infoframes)(struct drm_encoder *encoder,
361 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 362};
363
b091cd92 364#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 365#define DP_LINK_CONFIGURATION_SIZE 9
366
367struct intel_dp {
54d63ca6
SK		 368 uint32_t output_reg;
369 uint32_t DP;
370 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
371 bool has_audio;
372 enum hdmi_force_audio force_audio;
373 uint32_t color_range;
55bc60db 374 bool color_range_auto;
54d63ca6
SK		 375 uint8_t link_bw;
376 uint8_t lane_count;
377 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 378 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 379 struct i2c_adapter adapter;
380 struct i2c_algo_dp_aux_data algo;
381 bool is_pch_edp;
382 uint8_t train_set[4];
383 int panel_power_up_delay;
384 int panel_power_down_delay;
385 int panel_power_cycle_delay;
386 int backlight_on_delay;
387 int backlight_off_delay;
54d63ca6
SK		 388 struct delayed_work panel_vdd_work;
389 bool want_panel_vdd;
dd06f90e 390 struct intel_connector *attached_connector;
54d63ca6
SK		 391};
392
da63a9f2
PZ		 393struct intel_digital_port {
394 struct intel_encoder base;
174edf1f 395 enum port port;
876a8cdf 396 u32 port_reversal;
da63a9f2
PZ		 397 struct intel_dp dp;
398 struct intel_hdmi hdmi;
399};
400
f875c15a
CW		 401static inline struct drm_crtc *
402intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
403{
404 struct drm_i915_private *dev_priv = dev->dev_private;
405 return dev_priv->pipe_to_crtc_mapping[pipe];
406}
407
417ae147
CW		 408static inline struct drm_crtc *
409intel_get_crtc_for_plane(struct drm_device *dev, int plane)
410{
411 struct drm_i915_private *dev_priv = dev->dev_private;
412 return dev_priv->plane_to_crtc_mapping[plane];
413}
414
4e5359cd
SF		 415struct intel_unpin_work {
416 struct work_struct work;
b4a98e57 417 struct drm_crtc *crtc;
05394f39
CW		 418 struct drm_i915_gem_object *old_fb_obj;
419 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 420 struct drm_pending_vblank_event *event;
e7d841ca
CW		 421 atomic_t pending;
422#define INTEL_FLIP_INACTIVE 0
423#define INTEL_FLIP_PENDING 1
424#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF		 425 bool enable_stall_check;
426};
427
1630fe75
CW		 428struct intel_fbc_work {
429 struct delayed_work work;
430 struct drm_crtc *crtc;
431 struct drm_framebuffer *fb;
432 int interval;
433};
434
d2acd215
DV		 435int intel_pch_rawclk(struct drm_device *dev);
436
4eab8136
JN		 437int intel_connector_update_modes(struct drm_connector *connector,
438 struct edid *edid);
335af9a2 439int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 440
3f43c48d 441extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 442extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
443
79e53945 444extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 445extern void intel_hdmi_init(struct drm_device *dev,
446 int sdvox_reg, enum port port);
00c09d70
PZ		 447extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
448 struct intel_connector *intel_connector);
f5bbfca3 449extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
00c09d70
PZ		 450extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
451 const struct drm_display_mode *mode,
452 struct drm_display_mode *adjusted_mode);
f5bbfca3 453extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 454extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
455 bool is_sdvob);
79e53945
JB		 456extern void intel_dvo_init(struct drm_device *dev);
457extern void intel_tv_init(struct drm_device *dev);
f047e395 458extern void intel_mark_busy(struct drm_device *dev);
f047e395 459extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
725a5b54 460extern void intel_mark_idle(struct drm_device *dev);
c5d1b51d 461extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 462extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 463extern void intel_dp_init(struct drm_device *dev, int output_reg,
464 enum port port);
00c09d70
PZ		 465extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
466 struct intel_connector *intel_connector);
a4fc5ed6
KP		 467void
468intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
469 struct drm_display_mode *adjusted_mode);
247d89f6 470extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 471extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
472extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
473extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 474extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
475extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
476extern bool intel_dp_mode_fixup(struct drm_encoder *encoder,
477 const struct drm_display_mode *mode,
478 struct drm_display_mode *adjusted_mode);
cb0953d7 479extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 480extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
481extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 482extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
483extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
484extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
485extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0206e353 486extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 487extern int intel_edp_target_clock(struct intel_encoder *,
488 struct drm_display_mode *mode);
814948ad 489extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 490extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 491extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
492 enum plane plane);
32f9d658 493
a9573556 494/* intel_panel.c */
dd06f90e
JN		 495extern int intel_panel_init(struct intel_panel *panel,
496 struct drm_display_mode *fixed_mode);
1d508706
JN		 497extern void intel_panel_fini(struct intel_panel *panel);
498
1d8e1c75
CW		 499extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
500 struct drm_display_mode *adjusted_mode);
501extern void intel_pch_panel_fitting(struct drm_device *dev,
502 int fitting_mode,
cb1793ce 503 const struct drm_display_mode *mode,
1d8e1c75 504 struct drm_display_mode *adjusted_mode);
a9573556 505extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 506extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 507extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 508extern void intel_panel_enable_backlight(struct drm_device *dev,
509 enum pipe pipe);
47356eb6 510extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 511extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 512extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 513
d9e55608 514struct intel_set_config {
1aa4b628
DV		 515 struct drm_encoder **save_connector_encoders;
516 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 517
518 bool fb_changed;
519 bool mode_changed;
d9e55608
DV		 520};
521
c0c36b94
CW		 522extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
523 int x, int y, struct drm_framebuffer *old_fb);
a261b246 524extern void intel_modeset_disable(struct drm_device *dev);
c0c36b94 525extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
79e53945 526extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 527extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
1f703855 528extern void intel_encoder_noop(struct drm_encoder *encoder);
ea5b213a 529extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 530extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 531extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 532extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 533extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c
DV		 534extern void intel_modeset_check_state(struct drm_device *dev);
535
79e53945 536
df0e9248
CW		 537static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
538{
539 return to_intel_connector(connector)->encoder;
540}
541
7739c33b
PZ		 542static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
543{
da63a9f2
PZ		 544 struct intel_digital_port *intel_dig_port =
545 container_of(encoder, struct intel_digital_port, base.base);
546 return &intel_dig_port->dp;
547}
548
549static inline struct intel_digital_port *
550enc_to_dig_port(struct drm_encoder *encoder)
551{
552 return container_of(encoder, struct intel_digital_port, base.base);
553}
554
555static inline struct intel_digital_port *
556dp_to_dig_port(struct intel_dp *intel_dp)
557{
558 return container_of(intel_dp, struct intel_digital_port, dp);
559}
560
561static inline struct intel_digital_port *
562hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
563{
564 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 565}
566
b0ea7d37
DL		 567bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
568 struct intel_digital_port *port);
569
df0e9248
CW		 570extern void intel_connector_attach_encoder(struct intel_connector *connector,
571 struct intel_encoder *encoder);
572extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 573
574extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
575 struct drm_crtc *crtc);
08d7b3d1
CW		 576int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
577 struct drm_file *file_priv);
a5c961d1
PZ		 578extern enum transcoder
579intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
580 enum pipe pipe);
9d0498a2 581extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 582extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
d4b1931c 583extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
8261b191
CW		 584
585struct intel_load_detect_pipe {
d2dff872 586 struct drm_framebuffer *release_fb;
8261b191
CW		 587 bool load_detect_temp;
588 int dpms_mode;
589};
d2434ab7 590extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 591 struct drm_display_mode *mode,
8261b191 592 struct intel_load_detect_pipe *old);
d2434ab7 593extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 594 struct intel_load_detect_pipe *old);
79e53945 595
79e53945
JB		 596extern void intelfb_restore(void);
597extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
598 u16 blue, int regno);
b8c00ac5
DA		 599extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
600 u16 *blue, int regno);
0cdab21f 601extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 602
127bd2ac 603extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 604 struct drm_i915_gem_object *obj,
919926ae 605 struct intel_ring_buffer *pipelined);
1690e1eb 606extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 607
38651674
DA		 608extern int intel_framebuffer_init(struct drm_device *dev,
609 struct intel_framebuffer *ifb,
308e5bcb 610 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 611 struct drm_i915_gem_object *obj);
38651674 612extern int intel_fbdev_init(struct drm_device *dev);
20afbda2 613extern void intel_fbdev_initial_config(struct drm_device *dev);
38651674 614extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 615extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 616extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
617extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 618extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 619
02e792fb
DV		 620extern void intel_setup_overlay(struct drm_device *dev);
621extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 622extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 623extern int intel_overlay_put_image(struct drm_device *dev, void *data,
624 struct drm_file *file_priv);
625extern int intel_overlay_attrs(struct drm_device *dev, void *data,
626 struct drm_file *file_priv);
4abe3520 627
eb1f8e4f 628extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 629extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 630
b840d907
JB		 631extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
632 bool state);
633#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
634#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
635
645c62a5 636extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 637extern void intel_write_eld(struct drm_encoder *encoder,
638 struct drm_display_mode *mode);
d4270e57 639extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 640extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 641extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 642extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 643
b840d907 644/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 645extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 646extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
647 uint32_t sprite_width,
648 int pixel_size);
1f8eeabf
ED		 649extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
650 struct drm_display_mode *mode);
8ea30864 651
5a35e99e
DL		 652extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
653 unsigned int bpp,
654 unsigned int pitch);
655
8ea30864
JB		 656extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
657 struct drm_file *file_priv);
658extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
659 struct drm_file *file_priv);
660
57f350b6
JB		 661extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
662
85208be0 663/* Power-related functions, located in intel_pm.c */
1fa61106 664extern void intel_init_pm(struct drm_device *dev);
85208be0 665/* FBC */
85208be0
ED		 666extern bool intel_fbc_enabled(struct drm_device *dev);
667extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
668extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 669/* IPS */
670extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
671extern void intel_gpu_ips_teardown(void);
85208be0 672
fa42e23c 673extern void intel_init_power_well(struct drm_device *dev);
cb10799c 674extern void intel_set_power_well(struct drm_device *dev, bool enable);
8090c6b9
DV		 675extern void intel_enable_gt_powersave(struct drm_device *dev);
676extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 677extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 678extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 679
85234cdc
DV		 680extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
681 enum pipe *pipe);
b8fc2f6a 682extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 683extern void intel_ddi_pll_init(struct drm_device *dev);
8d9ddbcb 684extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
ad80a810
PZ		 685extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
686 enum transcoder cpu_transcoder);
fc914639
PZ		 687extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
688extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 689extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
690extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 691extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 692extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 693extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 694extern bool
695intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
696extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 697
96a02917
VS		 698extern void intel_display_handle_reset(struct drm_device *dev);
699
79e53945 700#endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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