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drm/i915: add haswell_set_pipeconf
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
8ea30864 29#include "i915_drm.h"
80824003 30#include "i915_drv.h"
79e53945 31#include "drm_crtc.h"
79e53945 32#include "drm_crtc_helper.h"
37811fcc 33#include "drm_fb_helper.h"
54d63ca6 34#include "drm_dp_helper.h"
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
57f350b6 53#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
57f350b6
JB		 64})
65
481b6af3
CW		 66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68
021357ac
CW		 69#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x)
71
79e53945
JB		 72/*
73 * Display related stuff
74 */
75
76/* store information about an Ixxx DVO */
77/* The i830->i865 use multiple DVOs with multiple i2cs */
78/* the i915, i945 have a single sDVO i2c bus - which is different */
79#define MAX_OUTPUTS 6
80/* maximum connectors per crtcs in the mode set */
81#define INTELFB_CONN_LIMIT 4
82
83#define INTEL_I2C_BUS_DVO 1
84#define INTEL_I2C_BUS_SDVO 2
85
86/* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88#define INTEL_OUTPUT_UNUSED 0
89#define INTEL_OUTPUT_ANALOG 1
90#define INTEL_OUTPUT_DVO 2
91#define INTEL_OUTPUT_SDVO 3
92#define INTEL_OUTPUT_LVDS 4
93#define INTEL_OUTPUT_TVOUT 5
7d57382e 94#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 95#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 96#define INTEL_OUTPUT_EDP 8
79e53945
JB		 97
98#define INTEL_DVO_CHIP_NONE 0
99#define INTEL_DVO_CHIP_LVDS 1
100#define INTEL_DVO_CHIP_TMDS 2
101#define INTEL_DVO_CHIP_TVOUT 4
102
6c9547ff
CW		 103/* drm_display_mode->private_flags */
104#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
105#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 106#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 107/* This flag must be set by the encoder's mode_fixup if it changes the crtc
108 * timings in the mode to prevent the crtc fixup from overwriting them.
109 * Currently only lvds needs that. */
110#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 111
112static inline void
113intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
114 int multiplier)
115{
116 mode->clock *= multiplier;
117 mode->private_flags |= multiplier;
118}
119
120static inline int
121intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
122{
123 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
124}
125
79e53945
JB		 126struct intel_framebuffer {
127 struct drm_framebuffer base;
05394f39 128 struct drm_i915_gem_object *obj;
79e53945
JB		 129};
130
37811fcc
CW		 131struct intel_fbdev {
132 struct drm_fb_helper helper;
133 struct intel_framebuffer ifb;
134 struct list_head fbdev_list;
135 struct drm_display_mode *our_mode;
136};
79e53945 137
21d40d37 138struct intel_encoder {
4ef69c7a 139 struct drm_encoder base;
9a935856
DV		 140 /*
141 * The new crtc this encoder will be driven from. Only differs from
142 * base->crtc while a modeset is in progress.
143 */
144 struct intel_crtc *new_crtc;
145
79e53945 146 int type;
e2f0ba97 147 bool needs_tv_clock;
66a9278e
DV		 148 /*
149 * Intel hw has only one MUX where encoders could be clone, hence a
150 * simple flag is enough to compute the possible_clones mask.
151 */
152 bool cloneable;
5ab432ef 153 bool connectors_active;
21d40d37 154 void (*hot_plug)(struct intel_encoder *);
bf49ec8c 155 void (*pre_enable)(struct intel_encoder *);
ef9c3aee
DV		 156 void (*enable)(struct intel_encoder *);
157 void (*disable)(struct intel_encoder *);
bf49ec8c 158 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 159 /* Read out the current hw state of this connector, returning true if
160 * the encoder is active. If the encoder is enabled it also set the pipe
161 * it is connected to in the pipe parameter. */
162 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 163 int crtc_mask;
79e53945
JB		 164};
165
5daa55eb
ZW		 166struct intel_connector {
167 struct drm_connector base;
9a935856
DV		 168 /*
169 * The fixed encoder this connector is connected to.
170 */
df0e9248 171 struct intel_encoder *encoder;
9a935856
DV		 172
173 /*
174 * The new encoder this connector will be driven. Only differs from
175 * encoder while a modeset is in progress.
176 */
177 struct intel_encoder *new_encoder;
178
f0947c37
DV		 179 /* Reads out the current hw, returning true if the connector is enabled
180 * and active (i.e. dpms ON state). */
181 bool (*get_hw_state)(struct intel_connector *);
5daa55eb
ZW		 182};
183
79e53945
JB		 184struct intel_crtc {
185 struct drm_crtc base;
80824003
JB		 186 enum pipe pipe;
187 enum plane plane;
79e53945 188 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 189 /*
190 * Whether the crtc and the connected output pipeline is active. Implies
191 * that crtc->enabled is set, i.e. the current mode configuration has
192 * some outputs connected to this crtc.
08a48469
DV		 193 */
194 bool active;
93314b5b 195 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 196 bool lowfreq_avail;
02e792fb 197 struct intel_overlay *overlay;
6b95a207 198 struct intel_unpin_work *unpin_work;
77ffb597 199 int fdi_lanes;
cda4b7d3 200
e506a0c6
DV		 201 /* Display surface base address adjustement for pageflips. Note that on
202 * gen4+ this only adjusts up to a tile, offsets within a tile are
203 * handled in the hw itself (with the TILEOFF register). */
204 unsigned long dspaddr_offset;
205
05394f39 206 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 207 uint32_t cursor_addr;
208 int16_t cursor_x, cursor_y;
209 int16_t cursor_width, cursor_height;
6b383a7f 210 bool cursor_visible;
5a354204 211 unsigned int bpp;
4b645f14 212
ee7b9f93
JB		 213 /* We can share PLLs across outputs if the timings match */
214 struct intel_pch_pll *pch_pll;
79e53945
JB		 215};
216
b840d907
JB		 217struct intel_plane {
218 struct drm_plane base;
219 enum pipe pipe;
220 struct drm_i915_gem_object *obj;
221 int max_downscale;
222 u32 lut_r[1024], lut_g[1024], lut_b[1024];
223 void (*update_plane)(struct drm_plane *plane,
224 struct drm_framebuffer *fb,
225 struct drm_i915_gem_object *obj,
226 int crtc_x, int crtc_y,
227 unsigned int crtc_w, unsigned int crtc_h,
228 uint32_t x, uint32_t y,
229 uint32_t src_w, uint32_t src_h);
230 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 231 int (*update_colorkey)(struct drm_plane *plane,
232 struct drm_intel_sprite_colorkey *key);
233 void (*get_colorkey)(struct drm_plane *plane,
234 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 235};
236
b445e3b0
ED		 237struct intel_watermark_params {
238 unsigned long fifo_size;
239 unsigned long max_wm;
240 unsigned long default_wm;
241 unsigned long guard_size;
242 unsigned long cacheline_size;
243};
244
245struct cxsr_latency {
246 int is_desktop;
247 int is_ddr3;
248 unsigned long fsb_freq;
249 unsigned long mem_freq;
250 unsigned long display_sr;
251 unsigned long display_hpll_disable;
252 unsigned long cursor_sr;
253 unsigned long cursor_hpll_disable;
254};
255
79e53945 256#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 257#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 258#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 259#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 260#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 261
45187ace
JB		 262#define DIP_HEADER_SIZE 5
263
3c17fe4b
DH		 264#define DIP_TYPE_AVI 0x82
265#define DIP_VERSION_AVI 0x2
266#define DIP_LEN_AVI 13
c846b619
PZ		 267#define DIP_AVI_PR_1 0
268#define DIP_AVI_PR_2 1
3c17fe4b 269
26005210 270#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 271#define DIP_VERSION_SPD 0x1
272#define DIP_LEN_SPD 25
273#define DIP_SPD_UNKNOWN 0
274#define DIP_SPD_DSTB 0x1
275#define DIP_SPD_DVDP 0x2
276#define DIP_SPD_DVHS 0x3
277#define DIP_SPD_HDDVR 0x4
278#define DIP_SPD_DVC 0x5
279#define DIP_SPD_DSC 0x6
280#define DIP_SPD_VCD 0x7
281#define DIP_SPD_GAME 0x8
282#define DIP_SPD_PC 0x9
283#define DIP_SPD_BD 0xa
284#define DIP_SPD_SCD 0xb
285
3c17fe4b
DH		 286struct dip_infoframe {
287 uint8_t type; /* HB0 */
288 uint8_t ver; /* HB1 */
289 uint8_t len; /* HB2 - body len, not including checksum */
290 uint8_t ecc; /* Header ECC */
291 uint8_t checksum; /* PB0 */
292 union {
293 struct {
294 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
295 uint8_t Y_A_B_S;
296 /* PB2 - C 7:6, M 5:4, R 3:0 */
297 uint8_t C_M_R;
298 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
299 uint8_t ITC_EC_Q_SC;
300 /* PB4 - VIC 6:0 */
301 uint8_t VIC;
0aa534df
PZ		 302 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
303 uint8_t YQ_CN_PR;
3c17fe4b
DH		 304 /* PB6 to PB13 */
305 uint16_t top_bar_end;
306 uint16_t bottom_bar_start;
307 uint16_t left_bar_end;
308 uint16_t right_bar_start;
81014b9d 309 } __attribute__ ((packed)) avi;
c0864cb3
JB		 310 struct {
311 uint8_t vn[8];
312 uint8_t pd[16];
313 uint8_t sdi;
81014b9d 314 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 315 uint8_t payload[27];
316 } __attribute__ ((packed)) body;
317} __attribute__((packed));
318
f5bbfca3
ED		 319struct intel_hdmi {
320 struct intel_encoder base;
321 u32 sdvox_reg;
322 int ddc_bus;
323 int ddi_port;
324 uint32_t color_range;
325 bool has_hdmi_sink;
326 bool has_audio;
327 enum hdmi_force_audio force_audio;
328 void (*write_infoframe)(struct drm_encoder *encoder,
329 struct dip_infoframe *frame);
687f4d06
PZ		 330 void (*set_infoframes)(struct drm_encoder *encoder,
331 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 332};
333
54d63ca6 334#define DP_RECEIVER_CAP_SIZE 0xf
b091cd92 335#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 336#define DP_LINK_CONFIGURATION_SIZE 9
337
338struct intel_dp {
339 struct intel_encoder base;
340 uint32_t output_reg;
341 uint32_t DP;
342 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
343 bool has_audio;
344 enum hdmi_force_audio force_audio;
ab9d7c30 345 enum port port;
54d63ca6 346 uint32_t color_range;
54d63ca6
SK		 347 uint8_t link_bw;
348 uint8_t lane_count;
349 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 350 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 351 struct i2c_adapter adapter;
352 struct i2c_algo_dp_aux_data algo;
353 bool is_pch_edp;
354 uint8_t train_set[4];
355 int panel_power_up_delay;
356 int panel_power_down_delay;
357 int panel_power_cycle_delay;
358 int backlight_on_delay;
359 int backlight_off_delay;
360 struct drm_display_mode *panel_fixed_mode; /* for eDP */
361 struct delayed_work panel_vdd_work;
362 bool want_panel_vdd;
363 struct edid *edid; /* cached EDID for eDP */
364 int edid_mode_count;
365};
366
f875c15a
CW		 367static inline struct drm_crtc *
368intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
369{
370 struct drm_i915_private *dev_priv = dev->dev_private;
371 return dev_priv->pipe_to_crtc_mapping[pipe];
372}
373
417ae147
CW		 374static inline struct drm_crtc *
375intel_get_crtc_for_plane(struct drm_device *dev, int plane)
376{
377 struct drm_i915_private *dev_priv = dev->dev_private;
378 return dev_priv->plane_to_crtc_mapping[plane];
379}
380
4e5359cd
SF		 381struct intel_unpin_work {
382 struct work_struct work;
383 struct drm_device *dev;
05394f39
CW		 384 struct drm_i915_gem_object *old_fb_obj;
385 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 386 struct drm_pending_vblank_event *event;
387 int pending;
388 bool enable_stall_check;
389};
390
1630fe75
CW		 391struct intel_fbc_work {
392 struct delayed_work work;
393 struct drm_crtc *crtc;
394 struct drm_framebuffer *fb;
395 int interval;
396};
397
4eab8136
JN		 398int intel_connector_update_modes(struct drm_connector *connector,
399 struct edid *edid);
335af9a2 400int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 401
3f43c48d 402extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 403extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
404
79e53945 405extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 406extern void intel_hdmi_init(struct drm_device *dev,
407 int sdvox_reg, enum port port);
f5bbfca3 408extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
f5bbfca3 409extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 410extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
411 bool is_sdvob);
79e53945
JB		 412extern void intel_dvo_init(struct drm_device *dev);
413extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 414extern void intel_mark_busy(struct drm_device *dev);
415extern void intel_mark_idle(struct drm_device *dev);
416extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
417extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 418extern bool intel_lvds_init(struct drm_device *dev);
ab9d7c30
PZ		 419extern void intel_dp_init(struct drm_device *dev, int output_reg,
420 enum port port);
a4fc5ed6
KP		 421void
422intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
423 struct drm_display_mode *adjusted_mode);
cb0953d7 424extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353 425extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 426extern int intel_edp_target_clock(struct intel_encoder *,
427 struct drm_display_mode *mode);
814948ad 428extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 429extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 430extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
431 enum plane plane);
32f9d658 432
a9573556 433/* intel_panel.c */
1d8e1c75
CW		 434extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
435 struct drm_display_mode *adjusted_mode);
436extern void intel_pch_panel_fitting(struct drm_device *dev,
437 int fitting_mode,
cb1793ce 438 const struct drm_display_mode *mode,
1d8e1c75 439 struct drm_display_mode *adjusted_mode);
a9573556 440extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 441extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
aaa6fd2a 442extern int intel_panel_setup_backlight(struct drm_device *dev);
24ded204
DV		 443extern void intel_panel_enable_backlight(struct drm_device *dev,
444 enum pipe pipe);
47356eb6 445extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 446extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 447extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 448
d9e55608 449struct intel_set_config {
1aa4b628
DV		 450 struct drm_encoder **save_connector_encoders;
451 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 452
453 bool fb_changed;
454 bool mode_changed;
d9e55608
DV		 455};
456
a6778b3c
DV		 457extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
458 int x, int y, struct drm_framebuffer *old_fb);
a261b246 459extern void intel_modeset_disable(struct drm_device *dev);
79e53945 460extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 461extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
1f703855 462extern void intel_encoder_noop(struct drm_encoder *encoder);
ea5b213a 463extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 464extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 465extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 466extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 467extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c
DV		 468extern void intel_modeset_check_state(struct drm_device *dev);
469
79e53945 470
df0e9248
CW		 471static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
472{
473 return to_intel_connector(connector)->encoder;
474}
475
476extern void intel_connector_attach_encoder(struct intel_connector *connector,
477 struct intel_encoder *encoder);
478extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 479
480extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
481 struct drm_crtc *crtc);
08d7b3d1
CW		 482int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
483 struct drm_file *file_priv);
9d0498a2 484extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 485extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 486
487struct intel_load_detect_pipe {
d2dff872 488 struct drm_framebuffer *release_fb;
8261b191
CW		 489 bool load_detect_temp;
490 int dpms_mode;
491};
d2434ab7 492extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 493 struct drm_display_mode *mode,
8261b191 494 struct intel_load_detect_pipe *old);
d2434ab7 495extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 496 struct intel_load_detect_pipe *old);
79e53945 497
79e53945
JB		 498extern void intelfb_restore(void);
499extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
500 u16 blue, int regno);
b8c00ac5
DA		 501extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
502 u16 *blue, int regno);
0cdab21f 503extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 504
127bd2ac 505extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 506 struct drm_i915_gem_object *obj,
919926ae 507 struct intel_ring_buffer *pipelined);
1690e1eb 508extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 509
38651674
DA		 510extern int intel_framebuffer_init(struct drm_device *dev,
511 struct intel_framebuffer *ifb,
308e5bcb 512 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 513 struct drm_i915_gem_object *obj);
38651674
DA		 514extern int intel_fbdev_init(struct drm_device *dev);
515extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 516extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 517extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
518extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 519extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 520
02e792fb
DV		 521extern void intel_setup_overlay(struct drm_device *dev);
522extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 523extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 524extern int intel_overlay_put_image(struct drm_device *dev, void *data,
525 struct drm_file *file_priv);
526extern int intel_overlay_attrs(struct drm_device *dev, void *data,
527 struct drm_file *file_priv);
4abe3520 528
eb1f8e4f 529extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 530extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 531
b840d907
JB		 532extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
533 bool state);
534#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
535#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
536
645c62a5 537extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 538extern void intel_write_eld(struct drm_encoder *encoder,
539 struct drm_display_mode *mode);
d4270e57 540extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 541extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 542extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 543extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 544
b840d907 545/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 546extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 547extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
548 uint32_t sprite_width,
549 int pixel_size);
1f8eeabf
ED		 550extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
551 struct drm_display_mode *mode);
8ea30864
JB		 552
553extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
554 struct drm_file *file_priv);
555extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
556 struct drm_file *file_priv);
557
57f350b6
JB		 558extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
559
85208be0 560/* Power-related functions, located in intel_pm.c */
1fa61106 561extern void intel_init_pm(struct drm_device *dev);
85208be0 562/* FBC */
85208be0
ED		 563extern bool intel_fbc_enabled(struct drm_device *dev);
564extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
565extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 566/* IPS */
567extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
568extern void intel_gpu_ips_teardown(void);
85208be0 569
0232e927 570extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 571extern void intel_enable_gt_powersave(struct drm_device *dev);
572extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 573extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 574extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 575
5ab432ef
DV		 576extern void intel_enable_ddi(struct intel_encoder *encoder);
577extern void intel_disable_ddi(struct intel_encoder *encoder);
85234cdc
DV		 578extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
579 enum pipe *pipe);
72662e10
ED		 580extern void intel_ddi_mode_set(struct drm_encoder *encoder,
581 struct drm_display_mode *mode,
582 struct drm_display_mode *adjusted_mode);
79f689aa 583extern void intel_ddi_pll_init(struct drm_device *dev);
8d9ddbcb
PZ		 584extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
585extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
586 enum pipe pipe);
fc914639
PZ		 587extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
588extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
72662e10 589
79e53945 590#endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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