Commit | Line | Data |
---|---|---|
4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
7f6a6a4a | 49 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
50 | { |
51 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
52 | struct drm_device *dev = encoder->dev; | |
53 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
54 | u32 mask; |
55 | ||
56 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
57 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
58 | ||
59 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
60 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
61 | } | |
62 | ||
f0f59a00 VS |
63 | static void write_data(struct drm_i915_private *dev_priv, |
64 | i915_reg_t reg, | |
7e9804fd JN |
65 | const u8 *data, u32 len) |
66 | { | |
67 | u32 i, j; | |
68 | ||
69 | for (i = 0; i < len; i += 4) { | |
70 | u32 val = 0; | |
71 | ||
72 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
73 | val |= *data++ << 8 * j; | |
74 | ||
75 | I915_WRITE(reg, val); | |
76 | } | |
77 | } | |
78 | ||
f0f59a00 VS |
79 | static void read_data(struct drm_i915_private *dev_priv, |
80 | i915_reg_t reg, | |
7e9804fd JN |
81 | u8 *data, u32 len) |
82 | { | |
83 | u32 i, j; | |
84 | ||
85 | for (i = 0; i < len; i += 4) { | |
86 | u32 val = I915_READ(reg); | |
87 | ||
88 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
89 | *data++ = val >> 8 * j; | |
90 | } | |
91 | } | |
92 | ||
93 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
94 | const struct mipi_dsi_msg *msg) | |
95 | { | |
96 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
97 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
98 | struct drm_i915_private *dev_priv = dev->dev_private; | |
99 | enum port port = intel_dsi_host->port; | |
100 | struct mipi_dsi_packet packet; | |
101 | ssize_t ret; | |
102 | const u8 *header, *data; | |
f0f59a00 VS |
103 | i915_reg_t data_reg, ctrl_reg; |
104 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
105 | |
106 | ret = mipi_dsi_create_packet(&packet, msg); | |
107 | if (ret < 0) | |
108 | return ret; | |
109 | ||
110 | header = packet.header; | |
111 | data = packet.payload; | |
112 | ||
113 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
114 | data_reg = MIPI_LP_GEN_DATA(port); | |
115 | data_mask = LP_DATA_FIFO_FULL; | |
116 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
117 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
118 | } else { | |
119 | data_reg = MIPI_HS_GEN_DATA(port); | |
120 | data_mask = HS_DATA_FIFO_FULL; | |
121 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
122 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
123 | } | |
124 | ||
125 | /* note: this is never true for reads */ | |
126 | if (packet.payload_length) { | |
127 | ||
128 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) | |
129 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); | |
130 | ||
131 | write_data(dev_priv, data_reg, packet.payload, | |
132 | packet.payload_length); | |
133 | } | |
134 | ||
135 | if (msg->rx_len) { | |
136 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
137 | } | |
138 | ||
139 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { | |
140 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); | |
141 | } | |
142 | ||
143 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
144 | ||
145 | /* ->rx_len is set only for reads */ | |
146 | if (msg->rx_len) { | |
147 | data_mask = GEN_READ_DATA_AVAIL; | |
148 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) | |
149 | DRM_ERROR("Timeout waiting for read data.\n"); | |
150 | ||
151 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
152 | } | |
153 | ||
154 | /* XXX: fix for reads and writes */ | |
155 | return 4 + packet.payload_length; | |
156 | } | |
157 | ||
158 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
159 | struct mipi_dsi_device *dsi) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | ||
164 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
165 | struct mipi_dsi_device *dsi) | |
166 | { | |
167 | return 0; | |
168 | } | |
169 | ||
170 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
171 | .attach = intel_dsi_host_attach, | |
172 | .detach = intel_dsi_host_detach, | |
173 | .transfer = intel_dsi_host_transfer, | |
174 | }; | |
175 | ||
176 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
177 | enum port port) | |
178 | { | |
179 | struct intel_dsi_host *host; | |
180 | struct mipi_dsi_device *device; | |
181 | ||
182 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
183 | if (!host) | |
184 | return NULL; | |
185 | ||
186 | host->base.ops = &intel_dsi_host_ops; | |
187 | host->intel_dsi = intel_dsi; | |
188 | host->port = port; | |
189 | ||
190 | /* | |
191 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
192 | * have a host->dev, and we don't have OF stuff either. So just use the | |
193 | * dsi framework as a library and hope for the best. Create the dsi | |
194 | * devices by ourselves here too. Need to be careful though, because we | |
195 | * don't initialize any of the driver model devices here. | |
196 | */ | |
197 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
198 | if (!device) { | |
199 | kfree(host); | |
200 | return NULL; | |
201 | } | |
202 | ||
203 | device->host = &host->base; | |
204 | host->device = device; | |
205 | ||
206 | return host; | |
207 | } | |
208 | ||
a2581a9e JN |
209 | /* |
210 | * send a video mode command | |
211 | * | |
212 | * XXX: commands with data in MIPI_DPI_DATA? | |
213 | */ | |
214 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
215 | enum port port) | |
216 | { | |
217 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
218 | struct drm_device *dev = encoder->dev; | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | u32 mask; | |
221 | ||
222 | /* XXX: pipe, hs */ | |
223 | if (hs) | |
224 | cmd &= ~DPI_LP_MODE; | |
225 | else | |
226 | cmd |= DPI_LP_MODE; | |
227 | ||
228 | /* clear bit */ | |
229 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
230 | ||
231 | /* XXX: old code skips write if control unchanged */ | |
232 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
233 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
234 | ||
235 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
236 | ||
237 | mask = SPL_PKT_SENT_INTERRUPT; | |
238 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) | |
239 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
e9fe51c6 | 244 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 245 | { |
a580516d | 246 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 247 | |
e9fe51c6 SK |
248 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
249 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
250 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
251 | udelay(150); | |
252 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
253 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 254 | |
a580516d | 255 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
256 | } |
257 | ||
4e646495 JN |
258 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
259 | { | |
dfba2e2d | 260 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
261 | } |
262 | ||
263 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
264 | { | |
dfba2e2d | 265 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
266 | } |
267 | ||
4e646495 | 268 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
a65347ba | 269 | struct intel_crtc_state *pipe_config) |
4e646495 | 270 | { |
4d1de975 | 271 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
4e646495 JN |
272 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
273 | base); | |
274 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
275 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 276 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
4e646495 JN |
277 | |
278 | DRM_DEBUG_KMS("\n"); | |
279 | ||
a65347ba JN |
280 | pipe_config->has_dsi_encoder = true; |
281 | ||
4e646495 JN |
282 | if (fixed_mode) |
283 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
284 | ||
f573de5a SK |
285 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
286 | adjusted_mode->flags = 0; | |
287 | ||
4d1de975 JN |
288 | if (IS_BROXTON(dev_priv)) { |
289 | /* Dual link goes to DSI transcoder A. */ | |
290 | if (intel_dsi->ports == BIT(PORT_C)) | |
291 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
292 | else | |
293 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
294 | } | |
295 | ||
4e646495 JN |
296 | return true; |
297 | } | |
298 | ||
37ab0810 | 299 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 300 | { |
37ab0810 | 301 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
5505a244 | 302 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 303 | enum port port; |
37ab0810 | 304 | u32 val; |
5505a244 | 305 | |
37ab0810 | 306 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 307 | |
37ab0810 | 308 | /* Exit Low power state in 4 steps*/ |
369602d3 | 309 | for_each_dsi_port(port, intel_dsi->ports) { |
5505a244 | 310 | |
37ab0810 SS |
311 | /* 1. Enable MIPI PHY transparent latch */ |
312 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
313 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
314 | usleep_range(2000, 2500); | |
315 | ||
316 | /* 2. Enter ULPS */ | |
317 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
318 | val &= ~ULPS_STATE_MASK; | |
319 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
320 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
321 | usleep_range(2, 3); | |
322 | ||
323 | /* 3. Exit ULPS */ | |
324 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
325 | val &= ~ULPS_STATE_MASK; | |
326 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
327 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
328 | usleep_range(1000, 1500); | |
5505a244 | 329 | |
37ab0810 SS |
330 | /* Clear ULPS and set device ready */ |
331 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
332 | val &= ~ULPS_STATE_MASK; | |
333 | val |= DEVICE_READY; | |
334 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 335 | } |
5505a244 GS |
336 | } |
337 | ||
37ab0810 | 338 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 339 | { |
1dbd7cb2 | 340 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
341 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
342 | enum port port; | |
1dbd7cb2 SK |
343 | u32 val; |
344 | ||
4e646495 | 345 | DRM_DEBUG_KMS("\n"); |
4e646495 | 346 | |
a580516d | 347 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
348 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
349 | * needed everytime after power gate */ | |
350 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 351 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
352 | |
353 | /* bandgap reset is needed after everytime we do power gate */ | |
354 | band_gap_reset(dev_priv); | |
355 | ||
24ee0e64 | 356 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 357 | |
24ee0e64 GS |
358 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
359 | usleep_range(2500, 3000); | |
aceb365c | 360 | |
bf344e80 GS |
361 | /* Enable MIPI PHY transparent latch |
362 | * Common bit for both MIPI Port A & MIPI Port C | |
363 | * No similar bit in MIPI Port C reg | |
364 | */ | |
4ba7d93a | 365 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 366 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 367 | usleep_range(1000, 1500); |
aceb365c | 368 | |
24ee0e64 GS |
369 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
370 | usleep_range(2500, 3000); | |
371 | ||
372 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
373 | usleep_range(2500, 3000); | |
374 | } | |
1dbd7cb2 | 375 | } |
1dbd7cb2 | 376 | |
37ab0810 SS |
377 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
378 | { | |
379 | struct drm_device *dev = encoder->base.dev; | |
380 | ||
666a4537 | 381 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
37ab0810 SS |
382 | vlv_dsi_device_ready(encoder); |
383 | else if (IS_BROXTON(dev)) | |
384 | bxt_dsi_device_ready(encoder); | |
385 | } | |
386 | ||
387 | static void intel_dsi_port_enable(struct intel_encoder *encoder) | |
388 | { | |
389 | struct drm_device *dev = encoder->base.dev; | |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
391 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
392 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
393 | enum port port; | |
37ab0810 SS |
394 | |
395 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 VS |
396 | u32 temp; |
397 | ||
37ab0810 SS |
398 | temp = I915_READ(VLV_CHICKEN_3); |
399 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
400 | intel_dsi->pixel_overlap << | |
401 | PIXEL_OVERLAP_CNT_SHIFT; | |
402 | I915_WRITE(VLV_CHICKEN_3, temp); | |
403 | } | |
404 | ||
405 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
406 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
407 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
408 | u32 temp; | |
37ab0810 SS |
409 | |
410 | temp = I915_READ(port_ctrl); | |
411 | ||
412 | temp &= ~LANE_CONFIGURATION_MASK; | |
413 | temp &= ~DUAL_LINK_MODE_MASK; | |
414 | ||
701d25b4 | 415 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
416 | temp |= (intel_dsi->dual_link - 1) |
417 | << DUAL_LINK_MODE_SHIFT; | |
418 | temp |= intel_crtc->pipe ? | |
419 | LANE_CONFIGURATION_DUAL_LINK_B : | |
420 | LANE_CONFIGURATION_DUAL_LINK_A; | |
421 | } | |
422 | /* assert ip_tg_enable signal */ | |
423 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
424 | POSTING_READ(port_ctrl); | |
425 | } | |
426 | } | |
427 | ||
428 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
429 | { | |
430 | struct drm_device *dev = encoder->base.dev; | |
431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
432 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
433 | enum port port; | |
37ab0810 SS |
434 | |
435 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
436 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
437 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
438 | u32 temp; | |
439 | ||
37ab0810 | 440 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
441 | temp = I915_READ(port_ctrl); |
442 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
443 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
444 | } |
445 | } | |
446 | ||
1dbd7cb2 SK |
447 | static void intel_dsi_enable(struct intel_encoder *encoder) |
448 | { | |
449 | struct drm_device *dev = encoder->base.dev; | |
450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 451 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 452 | enum port port; |
1dbd7cb2 SK |
453 | |
454 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 455 | |
4934b656 JN |
456 | if (is_cmd_mode(intel_dsi)) { |
457 | for_each_dsi_port(port, intel_dsi->ports) | |
458 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
459 | } else { | |
4e646495 | 460 | msleep(20); /* XXX */ |
f03e4179 | 461 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 462 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
463 | msleep(100); |
464 | ||
593e0622 | 465 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 466 | |
7f6a6a4a JN |
467 | for_each_dsi_port(port, intel_dsi->ports) |
468 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 469 | |
5505a244 | 470 | intel_dsi_port_enable(encoder); |
4e646495 | 471 | } |
b029e66f SK |
472 | |
473 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
474 | } |
475 | ||
e3488e75 JN |
476 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder); |
477 | ||
2634fd7f SK |
478 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
479 | { | |
20e5bf66 SK |
480 | struct drm_device *dev = encoder->base.dev; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 482 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
483 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
484 | enum pipe pipe = intel_crtc->pipe; | |
7f6a6a4a | 485 | enum port port; |
20e5bf66 | 486 | u32 tmp; |
2634fd7f SK |
487 | |
488 | DRM_DEBUG_KMS("\n"); | |
489 | ||
e3488e75 | 490 | intel_enable_dsi_pll(encoder); |
58d4d32f | 491 | intel_dsi_prepare(encoder); |
e3488e75 | 492 | |
fc45e821 SK |
493 | /* Panel Enable over CRC PMIC */ |
494 | if (intel_dsi->gpio_panel) | |
495 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
496 | ||
497 | msleep(intel_dsi->panel_on_delay); | |
498 | ||
666a4537 | 499 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
37ab0810 SS |
500 | /* |
501 | * Disable DPOunit clock gating, can stall pipe | |
502 | * and we need DPLL REFA always enabled | |
503 | */ | |
504 | tmp = I915_READ(DPLL(pipe)); | |
505 | tmp |= DPLL_REF_CLK_ENABLE_VLV; | |
506 | I915_WRITE(DPLL(pipe), tmp); | |
507 | ||
508 | /* update the hw state for DPLL */ | |
509 | intel_crtc->config->dpll_hw_state.dpll = | |
510 | DPLL_INTEGRATED_REF_CLK_VLV | | |
511 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
512 | ||
513 | tmp = I915_READ(DSPCLK_GATE_D); | |
514 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
515 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
516 | } | |
2634fd7f SK |
517 | |
518 | /* put device in ready state */ | |
519 | intel_dsi_device_ready(encoder); | |
4e646495 | 520 | |
593e0622 | 521 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 522 | |
7f6a6a4a JN |
523 | for_each_dsi_port(port, intel_dsi->ports) |
524 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 525 | |
2634fd7f SK |
526 | /* Enable port in pre-enable phase itself because as per hw team |
527 | * recommendation, port should be enabled befor plane & pipe */ | |
528 | intel_dsi_enable(encoder); | |
529 | } | |
530 | ||
531 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
532 | { | |
533 | DRM_DEBUG_KMS("\n"); | |
534 | ||
535 | /* for DSI port enable has to be done before pipe | |
536 | * and plane enable, so port enable is done in | |
537 | * pre_enable phase itself unlike other encoders | |
538 | */ | |
4e646495 JN |
539 | } |
540 | ||
c315faf8 ID |
541 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
542 | { | |
543 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 544 | enum port port; |
c315faf8 ID |
545 | |
546 | DRM_DEBUG_KMS("\n"); | |
547 | ||
b029e66f SK |
548 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
549 | ||
c315faf8 ID |
550 | if (is_vid_mode(intel_dsi)) { |
551 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 552 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 553 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
554 | msleep(10); |
555 | } | |
556 | } | |
557 | ||
4e646495 JN |
558 | static void intel_dsi_disable(struct intel_encoder *encoder) |
559 | { | |
1dbd7cb2 SK |
560 | struct drm_device *dev = encoder->base.dev; |
561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 562 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 563 | enum port port; |
4e646495 JN |
564 | u32 temp; |
565 | ||
566 | DRM_DEBUG_KMS("\n"); | |
567 | ||
4e646495 | 568 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
569 | for_each_dsi_port(port, intel_dsi->ports) |
570 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 571 | |
5505a244 | 572 | intel_dsi_port_disable(encoder); |
4e646495 JN |
573 | msleep(2); |
574 | } | |
575 | ||
384f02a2 GS |
576 | for_each_dsi_port(port, intel_dsi->ports) { |
577 | /* Panel commands can be sent when clock is in LP11 */ | |
578 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 579 | |
b389a45c | 580 | intel_dsi_reset_clocks(encoder, port); |
384f02a2 | 581 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 582 | |
384f02a2 GS |
583 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
584 | temp &= ~VID_MODE_FORMAT_MASK; | |
585 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 586 | |
384f02a2 GS |
587 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
588 | } | |
1dbd7cb2 SK |
589 | /* if disable packets are sent before sending shutdown packet then in |
590 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 591 | drm_panel_disable(intel_dsi->panel); |
1381308b | 592 | |
7f6a6a4a JN |
593 | for_each_dsi_port(port, intel_dsi->ports) |
594 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
595 | } |
596 | ||
1dbd7cb2 | 597 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 598 | { |
b389a45c | 599 | struct drm_device *dev = encoder->base.dev; |
1dbd7cb2 | 600 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
601 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
602 | enum port port; | |
1dbd7cb2 | 603 | |
4e646495 | 604 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 605 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
606 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
607 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? | |
608 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
609 | u32 val; | |
be4fc046 | 610 | |
384f02a2 GS |
611 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
612 | ULPS_STATE_ENTER); | |
613 | usleep_range(2000, 2500); | |
614 | ||
615 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
616 | ULPS_STATE_EXIT); | |
617 | usleep_range(2000, 2500); | |
618 | ||
619 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
620 | ULPS_STATE_ENTER); | |
621 | usleep_range(2000, 2500); | |
622 | ||
623 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
624 | * only. MIPI Port C has no similar bit for checking | |
625 | */ | |
b389a45c SS |
626 | if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) |
627 | == 0x00000), 30)) | |
384f02a2 GS |
628 | DRM_ERROR("DSI LP not going Low\n"); |
629 | ||
b389a45c SS |
630 | /* Disable MIPI PHY transparent latch */ |
631 | val = I915_READ(port_ctrl); | |
632 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
384f02a2 GS |
633 | usleep_range(1000, 1500); |
634 | ||
635 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
636 | usleep_range(2000, 2500); | |
637 | } | |
1dbd7cb2 | 638 | |
fe88fc68 | 639 | intel_disable_dsi_pll(encoder); |
4e646495 | 640 | } |
20e5bf66 | 641 | |
1dbd7cb2 SK |
642 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
643 | { | |
20e5bf66 | 644 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 SK |
645 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
646 | ||
647 | DRM_DEBUG_KMS("\n"); | |
648 | ||
c315faf8 ID |
649 | intel_dsi_disable(encoder); |
650 | ||
1dbd7cb2 SK |
651 | intel_dsi_clear_device_ready(encoder); |
652 | ||
d6e3af54 US |
653 | if (!IS_BROXTON(dev_priv)) { |
654 | u32 val; | |
655 | ||
656 | val = I915_READ(DSPCLK_GATE_D); | |
657 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
658 | I915_WRITE(DSPCLK_GATE_D, val); | |
659 | } | |
20e5bf66 | 660 | |
593e0622 | 661 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
662 | |
663 | msleep(intel_dsi->panel_off_delay); | |
664 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
fc45e821 SK |
665 | |
666 | /* Panel Disable over CRC PMIC */ | |
667 | if (intel_dsi->gpio_panel) | |
668 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1dbd7cb2 | 669 | } |
4e646495 JN |
670 | |
671 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
672 | enum pipe *pipe) | |
673 | { | |
674 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
675 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
676 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 677 | enum intel_display_power_domain power_domain; |
e7d7cad0 | 678 | enum port port; |
1dcec2f3 | 679 | bool active = false; |
4e646495 JN |
680 | |
681 | DRM_DEBUG_KMS("\n"); | |
682 | ||
6d129bea | 683 | power_domain = intel_display_port_power_domain(encoder); |
3f3f42b8 | 684 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
685 | return false; |
686 | ||
db18b6a6 ID |
687 | /* |
688 | * On Broxton the PLL needs to be enabled with a valid divider | |
689 | * configuration, otherwise accessing DSI registers will hang the | |
690 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
691 | */ | |
692 | if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) | |
693 | goto out_put_power; | |
694 | ||
4e646495 | 695 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 696 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
697 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
698 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
1dcec2f3 | 699 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 GS |
700 | |
701 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
702 | * Enable bit does not get set. To check whether DSI Port C | |
703 | * was enabled in BIOS, check the Pipe B enable bit | |
704 | */ | |
666a4537 | 705 | if (IS_VALLEYVIEW(dev) && port == PORT_C) |
1dcec2f3 | 706 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 707 | |
1dcec2f3 JN |
708 | /* Try command mode if video mode not enabled */ |
709 | if (!enabled) { | |
710 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
711 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 712 | } |
1dcec2f3 JN |
713 | |
714 | if (!enabled) | |
715 | continue; | |
716 | ||
717 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
718 | continue; | |
719 | ||
6b93e9c8 JN |
720 | if (IS_BROXTON(dev_priv)) { |
721 | u32 tmp = I915_READ(MIPI_CTRL(port)); | |
722 | tmp &= BXT_PIPE_SELECT_MASK; | |
723 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
724 | ||
725 | if (WARN_ON(tmp > PIPE_C)) | |
726 | continue; | |
727 | ||
728 | *pipe = tmp; | |
729 | } else { | |
730 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
731 | } | |
732 | ||
1dcec2f3 JN |
733 | active = true; |
734 | break; | |
4e646495 | 735 | } |
1dcec2f3 | 736 | |
db18b6a6 | 737 | out_put_power: |
3f3f42b8 | 738 | intel_display_power_put(dev_priv, power_domain); |
4e646495 | 739 | |
1dcec2f3 | 740 | return active; |
4e646495 JN |
741 | } |
742 | ||
743 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
5cec258b | 744 | struct intel_crtc_state *pipe_config) |
4e646495 | 745 | { |
d7d85d85 | 746 | u32 pclk; |
4e646495 JN |
747 | DRM_DEBUG_KMS("\n"); |
748 | ||
a65347ba JN |
749 | pipe_config->has_dsi_encoder = true; |
750 | ||
f573de5a SK |
751 | /* |
752 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
753 | * set dpll_md = 0 | |
754 | */ | |
755 | pipe_config->dpll_hw_state.dpll_md = 0; | |
756 | ||
d7d85d85 | 757 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp); |
f573de5a SK |
758 | if (!pclk) |
759 | return; | |
760 | ||
2d112de7 | 761 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 762 | pipe_config->port_clock = pclk; |
4e646495 JN |
763 | } |
764 | ||
c19de8eb DL |
765 | static enum drm_mode_status |
766 | intel_dsi_mode_valid(struct drm_connector *connector, | |
767 | struct drm_display_mode *mode) | |
4e646495 JN |
768 | { |
769 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
770 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
759a1e98 | 771 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
772 | |
773 | DRM_DEBUG_KMS("\n"); | |
774 | ||
775 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
776 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
777 | return MODE_NO_DBLESCAN; | |
778 | } | |
779 | ||
780 | if (fixed_mode) { | |
781 | if (mode->hdisplay > fixed_mode->hdisplay) | |
782 | return MODE_PANEL; | |
783 | if (mode->vdisplay > fixed_mode->vdisplay) | |
784 | return MODE_PANEL; | |
759a1e98 MK |
785 | if (fixed_mode->clock > max_dotclk) |
786 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
787 | } |
788 | ||
36d21f4c | 789 | return MODE_OK; |
4e646495 JN |
790 | } |
791 | ||
792 | /* return txclkesc cycles in terms of divider and duration in us */ | |
793 | static u16 txclkesc(u32 divider, unsigned int us) | |
794 | { | |
795 | switch (divider) { | |
796 | case ESCAPE_CLOCK_DIVIDER_1: | |
797 | default: | |
798 | return 20 * us; | |
799 | case ESCAPE_CLOCK_DIVIDER_2: | |
800 | return 10 * us; | |
801 | case ESCAPE_CLOCK_DIVIDER_4: | |
802 | return 5 * us; | |
803 | } | |
804 | } | |
805 | ||
806 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
807 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
808 | u16 burst_mode_ratio) | |
4e646495 | 809 | { |
7f0c8605 | 810 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 811 | 8 * 100), lane_count); |
4e646495 JN |
812 | } |
813 | ||
814 | static void set_dsi_timings(struct drm_encoder *encoder, | |
5e7234c9 | 815 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
816 | { |
817 | struct drm_device *dev = encoder->dev; | |
818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 819 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 820 | enum port port; |
1e78aa01 | 821 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
822 | unsigned int lane_count = intel_dsi->lane_count; |
823 | ||
824 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
825 | ||
aad941d5 VS |
826 | hactive = adjusted_mode->crtc_hdisplay; |
827 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
828 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
829 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 830 | |
aa102d28 GS |
831 | if (intel_dsi->dual_link) { |
832 | hactive /= 2; | |
833 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
834 | hactive += intel_dsi->pixel_overlap; | |
835 | hfp /= 2; | |
836 | hsync /= 2; | |
837 | hbp /= 2; | |
838 | } | |
839 | ||
aad941d5 VS |
840 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
841 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
842 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
843 | |
844 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 845 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 846 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
847 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
848 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 849 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 850 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 851 | |
aa102d28 | 852 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
853 | if (IS_BROXTON(dev)) { |
854 | /* | |
855 | * Program hdisplay and vdisplay on MIPI transcoder. | |
856 | * This is different from calculated hactive and | |
857 | * vactive, as they are calculated per channel basis, | |
858 | * whereas these values should be based on resolution. | |
859 | */ | |
860 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 861 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 862 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 863 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 864 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 865 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
866 | } |
867 | ||
aa102d28 GS |
868 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
869 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
870 | ||
871 | /* meaningful for video mode non-burst sync pulse mode only, | |
872 | * can be zero for non-burst sync events and burst modes */ | |
873 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
874 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
875 | ||
876 | /* vertical values are in terms of lines */ | |
877 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
878 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
879 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
880 | } | |
4e646495 JN |
881 | } |
882 | ||
1e78aa01 JN |
883 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
884 | { | |
885 | switch (fmt) { | |
886 | case MIPI_DSI_FMT_RGB888: | |
887 | return VID_MODE_FORMAT_RGB888; | |
888 | case MIPI_DSI_FMT_RGB666: | |
889 | return VID_MODE_FORMAT_RGB666; | |
890 | case MIPI_DSI_FMT_RGB666_PACKED: | |
891 | return VID_MODE_FORMAT_RGB666_PACKED; | |
892 | case MIPI_DSI_FMT_RGB565: | |
893 | return VID_MODE_FORMAT_RGB565; | |
894 | default: | |
895 | MISSING_CASE(fmt); | |
896 | return VID_MODE_FORMAT_RGB666; | |
897 | } | |
898 | } | |
899 | ||
07e4fb9e | 900 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
901 | { |
902 | struct drm_encoder *encoder = &intel_encoder->base; | |
903 | struct drm_device *dev = encoder->dev; | |
904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
905 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
906 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
7c5f93b0 | 907 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 908 | enum port port; |
1e78aa01 | 909 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 910 | u32 val, tmp; |
24ee0e64 | 911 | u16 mode_hdisplay; |
4e646495 | 912 | |
e7d7cad0 | 913 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 914 | |
aad941d5 | 915 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 916 | |
24ee0e64 GS |
917 | if (intel_dsi->dual_link) { |
918 | mode_hdisplay /= 2; | |
919 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
920 | mode_hdisplay += intel_dsi->pixel_overlap; | |
921 | } | |
4e646495 | 922 | |
24ee0e64 | 923 | for_each_dsi_port(port, intel_dsi->ports) { |
666a4537 | 924 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
d2e08c0f SS |
925 | /* |
926 | * escape clock divider, 20MHz, shared for A and C. | |
927 | * device ready must be off when doing this! txclkesc? | |
928 | */ | |
929 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
930 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
931 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
932 | ESCAPE_CLOCK_DIVIDER_1); | |
933 | ||
934 | /* read request priority is per pipe */ | |
935 | tmp = I915_READ(MIPI_CTRL(port)); | |
936 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
937 | I915_WRITE(MIPI_CTRL(port), tmp | | |
938 | READ_REQUEST_PRIORITY_HIGH); | |
939 | } else if (IS_BROXTON(dev)) { | |
56c48978 D |
940 | enum pipe pipe = intel_crtc->pipe; |
941 | ||
d2e08c0f SS |
942 | tmp = I915_READ(MIPI_CTRL(port)); |
943 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
944 | ||
56c48978 | 945 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
946 | I915_WRITE(MIPI_CTRL(port), tmp); |
947 | } | |
24ee0e64 GS |
948 | |
949 | /* XXX: why here, why like this? handling in irq handler?! */ | |
950 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
951 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
952 | ||
953 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
954 | ||
955 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 956 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
957 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
958 | } | |
4e646495 JN |
959 | |
960 | set_dsi_timings(encoder, adjusted_mode); | |
961 | ||
962 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
963 | if (is_cmd_mode(intel_dsi)) { | |
964 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
965 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
966 | } else { | |
967 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 968 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 969 | } |
4e646495 | 970 | |
24ee0e64 GS |
971 | tmp = 0; |
972 | if (intel_dsi->eotp_pkt == 0) | |
973 | tmp |= EOT_DISABLE; | |
974 | if (intel_dsi->clock_stop) | |
975 | tmp |= CLOCKSTOP; | |
4e646495 | 976 | |
24ee0e64 GS |
977 | for_each_dsi_port(port, intel_dsi->ports) { |
978 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
979 | ||
980 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
981 | * EOT and stop state. */ | |
982 | ||
983 | /* | |
984 | * In burst mode, value greater than one DPI line Time in byte | |
985 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
986 | * said value is recommended. | |
987 | * | |
988 | * In non-burst mode, Value greater than one DPI frame time in | |
989 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
990 | * said value is recommended. | |
991 | * | |
992 | * In DBI only mode, value greater than one DBI frame time in | |
993 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
994 | * said value is recommended. | |
995 | */ | |
4e646495 | 996 | |
24ee0e64 GS |
997 | if (is_vid_mode(intel_dsi) && |
998 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
999 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1000 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1001 | intel_dsi->lane_count, |
1002 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1003 | } else { |
1004 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1005 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1006 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1007 | bpp, intel_dsi->lane_count, |
1008 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1009 | } |
1010 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1011 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1012 | intel_dsi->turn_arnd_val); | |
1013 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1014 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1015 | |
24ee0e64 | 1016 | /* dphy stuff */ |
f1c79f16 | 1017 | |
24ee0e64 GS |
1018 | /* in terms of low power clock */ |
1019 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1020 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1021 | |
d2e08c0f SS |
1022 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
1023 | /* | |
1024 | * BXT spec says write MIPI_INIT_COUNT for | |
1025 | * both the ports, even if only one is | |
1026 | * getting used. So write the other port | |
1027 | * if not in dual link mode. | |
1028 | */ | |
1029 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1030 | PORT_A ? PORT_C : PORT_A), | |
1031 | intel_dsi->init_count); | |
1032 | } | |
4e646495 | 1033 | |
24ee0e64 | 1034 | /* recovery disables */ |
87c54d0e | 1035 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1036 | |
24ee0e64 GS |
1037 | /* in terms of low power clock */ |
1038 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1039 | |
24ee0e64 GS |
1040 | /* in terms of txbyteclkhs. actual high to low switch + |
1041 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1042 | * | |
1043 | * XXX: write MIPI_STOP_STATE_STALL? | |
1044 | */ | |
1045 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1046 | intel_dsi->hs_to_lp_count); | |
1047 | ||
1048 | /* XXX: low power clock equivalence in terms of byte clock. | |
1049 | * the number of byte clocks occupied in one low power clock. | |
1050 | * based on txbyteclkhs and txclkesc. | |
1051 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1052 | * ) / 105.??? | |
1053 | */ | |
1054 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1055 | ||
1056 | /* the bw essential for transmitting 16 long packets containing | |
1057 | * 252 bytes meant for dcs write memory command is programmed in | |
1058 | * this register in terms of byte clocks. based on dsi transfer | |
1059 | * rate and the number of lanes configured the time taken to | |
1060 | * transmit 16 long packets in a dsi stream varies. */ | |
1061 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1062 | ||
1063 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1064 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1065 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1066 | ||
1067 | if (is_vid_mode(intel_dsi)) | |
1068 | /* Some panels might have resolution which is not a | |
1069 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1070 | * resolution support for such panels by default */ | |
1071 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1072 | intel_dsi->video_frmt_cfg_bits | | |
1073 | intel_dsi->video_mode_format | | |
1074 | IP_TG_CONFIG | | |
1075 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1076 | } | |
4e646495 JN |
1077 | } |
1078 | ||
1079 | static enum drm_connector_status | |
1080 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
1081 | { | |
36d21f4c | 1082 | return connector_status_connected; |
4e646495 JN |
1083 | } |
1084 | ||
1085 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
1086 | { | |
1087 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1088 | struct drm_display_mode *mode; | |
1089 | ||
1090 | DRM_DEBUG_KMS("\n"); | |
1091 | ||
1092 | if (!intel_connector->panel.fixed_mode) { | |
1093 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | mode = drm_mode_duplicate(connector->dev, | |
1098 | intel_connector->panel.fixed_mode); | |
1099 | if (!mode) { | |
1100 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | drm_mode_probed_add(connector, mode); | |
1105 | return 1; | |
1106 | } | |
1107 | ||
593e0622 | 1108 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1109 | { |
1110 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1111 | ||
1112 | DRM_DEBUG_KMS("\n"); | |
1113 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1114 | drm_connector_cleanup(connector); |
1115 | kfree(connector); | |
1116 | } | |
1117 | ||
593e0622 JN |
1118 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1119 | { | |
1120 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1121 | ||
1122 | if (intel_dsi->panel) { | |
1123 | drm_panel_detach(intel_dsi->panel); | |
1124 | /* XXX: Logically this call belongs in the panel driver. */ | |
1125 | drm_panel_remove(intel_dsi->panel); | |
1126 | } | |
fc45e821 SK |
1127 | |
1128 | /* dispose of the gpios */ | |
1129 | if (intel_dsi->gpio_panel) | |
1130 | gpiod_put(intel_dsi->gpio_panel); | |
1131 | ||
593e0622 JN |
1132 | intel_encoder_destroy(encoder); |
1133 | } | |
1134 | ||
4e646495 | 1135 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1136 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1137 | }; |
1138 | ||
1139 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1140 | .get_modes = intel_dsi_get_modes, | |
1141 | .mode_valid = intel_dsi_mode_valid, | |
1142 | .best_encoder = intel_best_encoder, | |
1143 | }; | |
1144 | ||
1145 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1146 | .dpms = drm_atomic_helper_connector_dpms, |
4e646495 | 1147 | .detect = intel_dsi_detect, |
593e0622 | 1148 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1149 | .fill_modes = drm_helper_probe_single_connector_modes, |
2545e4a6 | 1150 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1151 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1152 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1153 | }; |
1154 | ||
4328633d | 1155 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
1156 | { |
1157 | struct intel_dsi *intel_dsi; | |
1158 | struct intel_encoder *intel_encoder; | |
1159 | struct drm_encoder *encoder; | |
1160 | struct intel_connector *intel_connector; | |
1161 | struct drm_connector *connector; | |
593e0622 | 1162 | struct drm_display_mode *scan, *fixed_mode = NULL; |
b6fdd0f2 | 1163 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e9804fd | 1164 | enum port port; |
4e646495 JN |
1165 | unsigned int i; |
1166 | ||
1167 | DRM_DEBUG_KMS("\n"); | |
1168 | ||
3e6bd011 | 1169 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1170 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1171 | return; |
3e6bd011 | 1172 | |
666a4537 | 1173 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
868d665b | 1174 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
c6c794a2 SS |
1175 | } else if (IS_BROXTON(dev)) { |
1176 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; | |
868d665b CJ |
1177 | } else { |
1178 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1179 | return; | |
1180 | } | |
3e6bd011 | 1181 | |
4e646495 JN |
1182 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1183 | if (!intel_dsi) | |
4328633d | 1184 | return; |
4e646495 | 1185 | |
08d9bc92 | 1186 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1187 | if (!intel_connector) { |
1188 | kfree(intel_dsi); | |
4328633d | 1189 | return; |
4e646495 JN |
1190 | } |
1191 | ||
1192 | intel_encoder = &intel_dsi->base; | |
1193 | encoder = &intel_encoder->base; | |
1194 | intel_dsi->attached_connector = intel_connector; | |
1195 | ||
1196 | connector = &intel_connector->base; | |
1197 | ||
13a3d91f VS |
1198 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
1199 | NULL); | |
4e646495 | 1200 | |
4e646495 | 1201 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1202 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1203 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1204 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1205 | intel_encoder->post_disable = intel_dsi_post_disable; |
1206 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1207 | intel_encoder->get_config = intel_dsi_get_config; | |
1208 | ||
1209 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1210 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 1211 | |
2e85ab4f JN |
1212 | /* |
1213 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1214 | * port C. BXT isn't limited like this. | |
1215 | */ | |
1216 | if (IS_BROXTON(dev_priv)) | |
1217 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); | |
1218 | else if (port == PORT_A) | |
701d25b4 | 1219 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1220 | else |
701d25b4 | 1221 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1222 | |
82425785 | 1223 | if (dev_priv->vbt.dsi.config->dual_link) |
701d25b4 | 1224 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
7137aec1 | 1225 | else |
701d25b4 | 1226 | intel_dsi->ports = BIT(port); |
82425785 | 1227 | |
7e9804fd JN |
1228 | /* Create a DSI host (and a device) for each port. */ |
1229 | for_each_dsi_port(port, intel_dsi->ports) { | |
1230 | struct intel_dsi_host *host; | |
1231 | ||
1232 | host = intel_dsi_host_init(intel_dsi, port); | |
1233 | if (!host) | |
1234 | goto err; | |
1235 | ||
1236 | intel_dsi->dsi_hosts[port] = host; | |
1237 | } | |
1238 | ||
593e0622 JN |
1239 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1240 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1241 | intel_dsi_drivers[i].panel_id); | |
1242 | if (intel_dsi->panel) | |
4e646495 JN |
1243 | break; |
1244 | } | |
1245 | ||
593e0622 | 1246 | if (!intel_dsi->panel) { |
4e646495 JN |
1247 | DRM_DEBUG_KMS("no device found\n"); |
1248 | goto err; | |
1249 | } | |
1250 | ||
fc45e821 SK |
1251 | /* |
1252 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1253 | * Panel control. | |
1254 | */ | |
1255 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1256 | intel_dsi->gpio_panel = | |
1257 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1258 | ||
1259 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1260 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1261 | intel_dsi->gpio_panel = NULL; | |
1262 | } | |
1263 | } | |
1264 | ||
4e646495 | 1265 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1266 | intel_encoder->cloneable = 0; |
4e646495 JN |
1267 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1268 | DRM_MODE_CONNECTOR_DSI); | |
1269 | ||
1270 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1271 | ||
1272 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1273 | connector->interlace_allowed = false; | |
1274 | connector->doublescan_allowed = false; | |
1275 | ||
1276 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1277 | ||
34ea3d38 | 1278 | drm_connector_register(connector); |
4e646495 | 1279 | |
593e0622 JN |
1280 | drm_panel_attach(intel_dsi->panel, connector); |
1281 | ||
1282 | mutex_lock(&dev->mode_config.mutex); | |
1283 | drm_panel_get_modes(intel_dsi->panel); | |
1284 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1285 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1286 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1287 | break; | |
1288 | } | |
1289 | } | |
1290 | mutex_unlock(&dev->mode_config.mutex); | |
1291 | ||
4e646495 JN |
1292 | if (!fixed_mode) { |
1293 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1294 | goto err; | |
1295 | } | |
1296 | ||
4b6ed685 | 1297 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
b029e66f | 1298 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
4e646495 | 1299 | |
4328633d | 1300 | return; |
4e646495 JN |
1301 | |
1302 | err: | |
1303 | drm_encoder_cleanup(&intel_encoder->base); | |
1304 | kfree(intel_dsi); | |
1305 | kfree(intel_connector); | |
4e646495 | 1306 | } |