Commit | Line | Data |
---|---|---|
4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
042ab0c3 R |
49 | /* return pixels in terms of txbyteclkhs */ |
50 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, | |
51 | u16 burst_mode_ratio) | |
52 | { | |
53 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, | |
54 | 8 * 100), lane_count); | |
55 | } | |
56 | ||
cefc4e18 R |
57 | /* return pixels equvalent to txbyteclkhs */ |
58 | static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, | |
59 | u16 burst_mode_ratio) | |
60 | { | |
61 | return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), | |
62 | (bpp * burst_mode_ratio)); | |
63 | } | |
64 | ||
43367ec9 R |
65 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
66 | { | |
67 | /* It just so happens the VBT matches register contents. */ | |
68 | switch (fmt) { | |
69 | case VID_MODE_FORMAT_RGB888: | |
70 | return MIPI_DSI_FMT_RGB888; | |
71 | case VID_MODE_FORMAT_RGB666: | |
72 | return MIPI_DSI_FMT_RGB666; | |
73 | case VID_MODE_FORMAT_RGB666_PACKED: | |
74 | return MIPI_DSI_FMT_RGB666_PACKED; | |
75 | case VID_MODE_FORMAT_RGB565: | |
76 | return MIPI_DSI_FMT_RGB565; | |
77 | default: | |
78 | MISSING_CASE(fmt); | |
79 | return MIPI_DSI_FMT_RGB666; | |
80 | } | |
81 | } | |
82 | ||
7f6a6a4a | 83 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
84 | { |
85 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
86 | struct drm_device *dev = encoder->dev; | |
87 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
88 | u32 mask; |
89 | ||
90 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
91 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
92 | ||
93 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
94 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
95 | } | |
96 | ||
f0f59a00 VS |
97 | static void write_data(struct drm_i915_private *dev_priv, |
98 | i915_reg_t reg, | |
7e9804fd JN |
99 | const u8 *data, u32 len) |
100 | { | |
101 | u32 i, j; | |
102 | ||
103 | for (i = 0; i < len; i += 4) { | |
104 | u32 val = 0; | |
105 | ||
106 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
107 | val |= *data++ << 8 * j; | |
108 | ||
109 | I915_WRITE(reg, val); | |
110 | } | |
111 | } | |
112 | ||
f0f59a00 VS |
113 | static void read_data(struct drm_i915_private *dev_priv, |
114 | i915_reg_t reg, | |
7e9804fd JN |
115 | u8 *data, u32 len) |
116 | { | |
117 | u32 i, j; | |
118 | ||
119 | for (i = 0; i < len; i += 4) { | |
120 | u32 val = I915_READ(reg); | |
121 | ||
122 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
123 | *data++ = val >> 8 * j; | |
124 | } | |
125 | } | |
126 | ||
127 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
128 | const struct mipi_dsi_msg *msg) | |
129 | { | |
130 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
131 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
133 | enum port port = intel_dsi_host->port; | |
134 | struct mipi_dsi_packet packet; | |
135 | ssize_t ret; | |
136 | const u8 *header, *data; | |
f0f59a00 VS |
137 | i915_reg_t data_reg, ctrl_reg; |
138 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
139 | |
140 | ret = mipi_dsi_create_packet(&packet, msg); | |
141 | if (ret < 0) | |
142 | return ret; | |
143 | ||
144 | header = packet.header; | |
145 | data = packet.payload; | |
146 | ||
147 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
148 | data_reg = MIPI_LP_GEN_DATA(port); | |
149 | data_mask = LP_DATA_FIFO_FULL; | |
150 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
151 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
152 | } else { | |
153 | data_reg = MIPI_HS_GEN_DATA(port); | |
154 | data_mask = HS_DATA_FIFO_FULL; | |
155 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
156 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
157 | } | |
158 | ||
159 | /* note: this is never true for reads */ | |
160 | if (packet.payload_length) { | |
161 | ||
162 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) | |
163 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); | |
164 | ||
165 | write_data(dev_priv, data_reg, packet.payload, | |
166 | packet.payload_length); | |
167 | } | |
168 | ||
169 | if (msg->rx_len) { | |
170 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
171 | } | |
172 | ||
173 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { | |
174 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); | |
175 | } | |
176 | ||
177 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
178 | ||
179 | /* ->rx_len is set only for reads */ | |
180 | if (msg->rx_len) { | |
181 | data_mask = GEN_READ_DATA_AVAIL; | |
182 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) | |
183 | DRM_ERROR("Timeout waiting for read data.\n"); | |
184 | ||
185 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
186 | } | |
187 | ||
188 | /* XXX: fix for reads and writes */ | |
189 | return 4 + packet.payload_length; | |
190 | } | |
191 | ||
192 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
193 | struct mipi_dsi_device *dsi) | |
194 | { | |
195 | return 0; | |
196 | } | |
197 | ||
198 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
199 | struct mipi_dsi_device *dsi) | |
200 | { | |
201 | return 0; | |
202 | } | |
203 | ||
204 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
205 | .attach = intel_dsi_host_attach, | |
206 | .detach = intel_dsi_host_detach, | |
207 | .transfer = intel_dsi_host_transfer, | |
208 | }; | |
209 | ||
210 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
211 | enum port port) | |
212 | { | |
213 | struct intel_dsi_host *host; | |
214 | struct mipi_dsi_device *device; | |
215 | ||
216 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
217 | if (!host) | |
218 | return NULL; | |
219 | ||
220 | host->base.ops = &intel_dsi_host_ops; | |
221 | host->intel_dsi = intel_dsi; | |
222 | host->port = port; | |
223 | ||
224 | /* | |
225 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
226 | * have a host->dev, and we don't have OF stuff either. So just use the | |
227 | * dsi framework as a library and hope for the best. Create the dsi | |
228 | * devices by ourselves here too. Need to be careful though, because we | |
229 | * don't initialize any of the driver model devices here. | |
230 | */ | |
231 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
232 | if (!device) { | |
233 | kfree(host); | |
234 | return NULL; | |
235 | } | |
236 | ||
237 | device->host = &host->base; | |
238 | host->device = device; | |
239 | ||
240 | return host; | |
241 | } | |
242 | ||
a2581a9e JN |
243 | /* |
244 | * send a video mode command | |
245 | * | |
246 | * XXX: commands with data in MIPI_DPI_DATA? | |
247 | */ | |
248 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
249 | enum port port) | |
250 | { | |
251 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
252 | struct drm_device *dev = encoder->dev; | |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
254 | u32 mask; | |
255 | ||
256 | /* XXX: pipe, hs */ | |
257 | if (hs) | |
258 | cmd &= ~DPI_LP_MODE; | |
259 | else | |
260 | cmd |= DPI_LP_MODE; | |
261 | ||
262 | /* clear bit */ | |
263 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
264 | ||
265 | /* XXX: old code skips write if control unchanged */ | |
266 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
267 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
268 | ||
269 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
270 | ||
271 | mask = SPL_PKT_SENT_INTERRUPT; | |
272 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) | |
273 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
e9fe51c6 | 278 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 279 | { |
a580516d | 280 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 281 | |
e9fe51c6 SK |
282 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
283 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
284 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
285 | udelay(150); | |
286 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
287 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 288 | |
a580516d | 289 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
290 | } |
291 | ||
4e646495 JN |
292 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
293 | { | |
dfba2e2d | 294 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
295 | } |
296 | ||
297 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
298 | { | |
dfba2e2d | 299 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
300 | } |
301 | ||
4e646495 | 302 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
a65347ba | 303 | struct intel_crtc_state *pipe_config) |
4e646495 | 304 | { |
4d1de975 | 305 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
4e646495 JN |
306 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
307 | base); | |
308 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
f4ee265f VS |
309 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
310 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 311 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
47eacbab | 312 | int ret; |
4e646495 JN |
313 | |
314 | DRM_DEBUG_KMS("\n"); | |
315 | ||
a65347ba JN |
316 | pipe_config->has_dsi_encoder = true; |
317 | ||
f4ee265f | 318 | if (fixed_mode) { |
4e646495 JN |
319 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
320 | ||
f4ee265f VS |
321 | if (HAS_GMCH_DISPLAY(dev_priv)) |
322 | intel_gmch_panel_fitting(crtc, pipe_config, | |
323 | intel_connector->panel.fitting_mode); | |
324 | else | |
325 | intel_pch_panel_fitting(crtc, pipe_config, | |
326 | intel_connector->panel.fitting_mode); | |
327 | } | |
328 | ||
f573de5a SK |
329 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
330 | adjusted_mode->flags = 0; | |
331 | ||
4d1de975 JN |
332 | if (IS_BROXTON(dev_priv)) { |
333 | /* Dual link goes to DSI transcoder A. */ | |
334 | if (intel_dsi->ports == BIT(PORT_C)) | |
335 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
336 | else | |
337 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
338 | } | |
339 | ||
47eacbab VS |
340 | ret = intel_compute_dsi_pll(encoder, pipe_config); |
341 | if (ret) | |
342 | return false; | |
343 | ||
cd2d34d9 VS |
344 | pipe_config->clock_set = true; |
345 | ||
4e646495 JN |
346 | return true; |
347 | } | |
348 | ||
37ab0810 | 349 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 350 | { |
37ab0810 | 351 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
5505a244 | 352 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 353 | enum port port; |
37ab0810 | 354 | u32 val; |
5505a244 | 355 | |
37ab0810 | 356 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 357 | |
37ab0810 | 358 | /* Exit Low power state in 4 steps*/ |
369602d3 | 359 | for_each_dsi_port(port, intel_dsi->ports) { |
5505a244 | 360 | |
37ab0810 SS |
361 | /* 1. Enable MIPI PHY transparent latch */ |
362 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
363 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
364 | usleep_range(2000, 2500); | |
365 | ||
366 | /* 2. Enter ULPS */ | |
367 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
368 | val &= ~ULPS_STATE_MASK; | |
369 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
370 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
371 | usleep_range(2, 3); | |
372 | ||
373 | /* 3. Exit ULPS */ | |
374 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
375 | val &= ~ULPS_STATE_MASK; | |
376 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
377 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
378 | usleep_range(1000, 1500); | |
5505a244 | 379 | |
37ab0810 SS |
380 | /* Clear ULPS and set device ready */ |
381 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
382 | val &= ~ULPS_STATE_MASK; | |
383 | val |= DEVICE_READY; | |
384 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 385 | } |
5505a244 GS |
386 | } |
387 | ||
37ab0810 | 388 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 389 | { |
1dbd7cb2 | 390 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
391 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
392 | enum port port; | |
1dbd7cb2 SK |
393 | u32 val; |
394 | ||
4e646495 | 395 | DRM_DEBUG_KMS("\n"); |
4e646495 | 396 | |
a580516d | 397 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
398 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
399 | * needed everytime after power gate */ | |
400 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 401 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
402 | |
403 | /* bandgap reset is needed after everytime we do power gate */ | |
404 | band_gap_reset(dev_priv); | |
405 | ||
24ee0e64 | 406 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 407 | |
24ee0e64 GS |
408 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
409 | usleep_range(2500, 3000); | |
aceb365c | 410 | |
bf344e80 GS |
411 | /* Enable MIPI PHY transparent latch |
412 | * Common bit for both MIPI Port A & MIPI Port C | |
413 | * No similar bit in MIPI Port C reg | |
414 | */ | |
4ba7d93a | 415 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 416 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 417 | usleep_range(1000, 1500); |
aceb365c | 418 | |
24ee0e64 GS |
419 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
420 | usleep_range(2500, 3000); | |
421 | ||
422 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
423 | usleep_range(2500, 3000); | |
424 | } | |
1dbd7cb2 | 425 | } |
1dbd7cb2 | 426 | |
37ab0810 SS |
427 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
428 | { | |
429 | struct drm_device *dev = encoder->base.dev; | |
430 | ||
666a4537 | 431 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
37ab0810 SS |
432 | vlv_dsi_device_ready(encoder); |
433 | else if (IS_BROXTON(dev)) | |
434 | bxt_dsi_device_ready(encoder); | |
435 | } | |
436 | ||
437 | static void intel_dsi_port_enable(struct intel_encoder *encoder) | |
438 | { | |
439 | struct drm_device *dev = encoder->base.dev; | |
440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
441 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
442 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
443 | enum port port; | |
37ab0810 SS |
444 | |
445 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 VS |
446 | u32 temp; |
447 | ||
37ab0810 SS |
448 | temp = I915_READ(VLV_CHICKEN_3); |
449 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
450 | intel_dsi->pixel_overlap << | |
451 | PIXEL_OVERLAP_CNT_SHIFT; | |
452 | I915_WRITE(VLV_CHICKEN_3, temp); | |
453 | } | |
454 | ||
455 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
456 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
457 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
458 | u32 temp; | |
37ab0810 SS |
459 | |
460 | temp = I915_READ(port_ctrl); | |
461 | ||
462 | temp &= ~LANE_CONFIGURATION_MASK; | |
463 | temp &= ~DUAL_LINK_MODE_MASK; | |
464 | ||
701d25b4 | 465 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
466 | temp |= (intel_dsi->dual_link - 1) |
467 | << DUAL_LINK_MODE_SHIFT; | |
468 | temp |= intel_crtc->pipe ? | |
469 | LANE_CONFIGURATION_DUAL_LINK_B : | |
470 | LANE_CONFIGURATION_DUAL_LINK_A; | |
471 | } | |
472 | /* assert ip_tg_enable signal */ | |
473 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
474 | POSTING_READ(port_ctrl); | |
475 | } | |
476 | } | |
477 | ||
478 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
479 | { | |
480 | struct drm_device *dev = encoder->base.dev; | |
481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
482 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
483 | enum port port; | |
37ab0810 SS |
484 | |
485 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
486 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
487 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
488 | u32 temp; | |
489 | ||
37ab0810 | 490 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
491 | temp = I915_READ(port_ctrl); |
492 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
493 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
494 | } |
495 | } | |
496 | ||
1dbd7cb2 SK |
497 | static void intel_dsi_enable(struct intel_encoder *encoder) |
498 | { | |
499 | struct drm_device *dev = encoder->base.dev; | |
500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 501 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 502 | enum port port; |
1dbd7cb2 SK |
503 | |
504 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 505 | |
4934b656 JN |
506 | if (is_cmd_mode(intel_dsi)) { |
507 | for_each_dsi_port(port, intel_dsi->ports) | |
508 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
509 | } else { | |
4e646495 | 510 | msleep(20); /* XXX */ |
f03e4179 | 511 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 512 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
513 | msleep(100); |
514 | ||
593e0622 | 515 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 516 | |
7f6a6a4a JN |
517 | for_each_dsi_port(port, intel_dsi->ports) |
518 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 519 | |
5505a244 | 520 | intel_dsi_port_enable(encoder); |
4e646495 | 521 | } |
b029e66f SK |
522 | |
523 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
524 | } |
525 | ||
e3488e75 JN |
526 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder); |
527 | ||
2634fd7f SK |
528 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
529 | { | |
20e5bf66 SK |
530 | struct drm_device *dev = encoder->base.dev; |
531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 532 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
47eacbab | 533 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7f6a6a4a | 534 | enum port port; |
2634fd7f SK |
535 | |
536 | DRM_DEBUG_KMS("\n"); | |
537 | ||
f00b5689 VS |
538 | /* |
539 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
540 | * lock. It needs to be fully powered down to fix it. | |
541 | */ | |
542 | intel_disable_dsi_pll(encoder); | |
47eacbab | 543 | intel_enable_dsi_pll(encoder, crtc->config); |
f00b5689 | 544 | |
58d4d32f | 545 | intel_dsi_prepare(encoder); |
e3488e75 | 546 | |
fc45e821 SK |
547 | /* Panel Enable over CRC PMIC */ |
548 | if (intel_dsi->gpio_panel) | |
549 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
550 | ||
551 | msleep(intel_dsi->panel_on_delay); | |
552 | ||
d1877c0f VS |
553 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
554 | u32 val; | |
555 | ||
cd2d34d9 | 556 | /* Disable DPOunit clock gating, can stall pipe */ |
d1877c0f VS |
557 | val = I915_READ(DSPCLK_GATE_D); |
558 | val |= DPOUNIT_CLOCK_GATE_DISABLE; | |
559 | I915_WRITE(DSPCLK_GATE_D, val); | |
37ab0810 | 560 | } |
2634fd7f SK |
561 | |
562 | /* put device in ready state */ | |
563 | intel_dsi_device_ready(encoder); | |
4e646495 | 564 | |
593e0622 | 565 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 566 | |
7f6a6a4a JN |
567 | for_each_dsi_port(port, intel_dsi->ports) |
568 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 569 | |
2634fd7f SK |
570 | /* Enable port in pre-enable phase itself because as per hw team |
571 | * recommendation, port should be enabled befor plane & pipe */ | |
572 | intel_dsi_enable(encoder); | |
573 | } | |
574 | ||
575 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
576 | { | |
577 | DRM_DEBUG_KMS("\n"); | |
578 | ||
579 | /* for DSI port enable has to be done before pipe | |
580 | * and plane enable, so port enable is done in | |
581 | * pre_enable phase itself unlike other encoders | |
582 | */ | |
4e646495 JN |
583 | } |
584 | ||
c315faf8 ID |
585 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
586 | { | |
587 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 588 | enum port port; |
c315faf8 ID |
589 | |
590 | DRM_DEBUG_KMS("\n"); | |
591 | ||
b029e66f SK |
592 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
593 | ||
c315faf8 ID |
594 | if (is_vid_mode(intel_dsi)) { |
595 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 596 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 597 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
598 | msleep(10); |
599 | } | |
600 | } | |
601 | ||
4e646495 JN |
602 | static void intel_dsi_disable(struct intel_encoder *encoder) |
603 | { | |
1dbd7cb2 SK |
604 | struct drm_device *dev = encoder->base.dev; |
605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 606 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 607 | enum port port; |
4e646495 JN |
608 | u32 temp; |
609 | ||
610 | DRM_DEBUG_KMS("\n"); | |
611 | ||
4e646495 | 612 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
613 | for_each_dsi_port(port, intel_dsi->ports) |
614 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 615 | |
5505a244 | 616 | intel_dsi_port_disable(encoder); |
4e646495 JN |
617 | msleep(2); |
618 | } | |
619 | ||
384f02a2 GS |
620 | for_each_dsi_port(port, intel_dsi->ports) { |
621 | /* Panel commands can be sent when clock is in LP11 */ | |
622 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 623 | |
b389a45c | 624 | intel_dsi_reset_clocks(encoder, port); |
384f02a2 | 625 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 626 | |
384f02a2 GS |
627 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
628 | temp &= ~VID_MODE_FORMAT_MASK; | |
629 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 630 | |
384f02a2 GS |
631 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
632 | } | |
1dbd7cb2 SK |
633 | /* if disable packets are sent before sending shutdown packet then in |
634 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 635 | drm_panel_disable(intel_dsi->panel); |
1381308b | 636 | |
7f6a6a4a JN |
637 | for_each_dsi_port(port, intel_dsi->ports) |
638 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
639 | } |
640 | ||
1dbd7cb2 | 641 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 642 | { |
b389a45c | 643 | struct drm_device *dev = encoder->base.dev; |
1dbd7cb2 | 644 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
645 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
646 | enum port port; | |
1dbd7cb2 | 647 | |
4e646495 | 648 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 649 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
650 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
651 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? | |
652 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
653 | u32 val; | |
be4fc046 | 654 | |
384f02a2 GS |
655 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
656 | ULPS_STATE_ENTER); | |
657 | usleep_range(2000, 2500); | |
658 | ||
659 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
660 | ULPS_STATE_EXIT); | |
661 | usleep_range(2000, 2500); | |
662 | ||
663 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
664 | ULPS_STATE_ENTER); | |
665 | usleep_range(2000, 2500); | |
666 | ||
667 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
668 | * only. MIPI Port C has no similar bit for checking | |
669 | */ | |
b389a45c SS |
670 | if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) |
671 | == 0x00000), 30)) | |
384f02a2 GS |
672 | DRM_ERROR("DSI LP not going Low\n"); |
673 | ||
b389a45c SS |
674 | /* Disable MIPI PHY transparent latch */ |
675 | val = I915_READ(port_ctrl); | |
676 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
384f02a2 GS |
677 | usleep_range(1000, 1500); |
678 | ||
679 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
680 | usleep_range(2000, 2500); | |
681 | } | |
1dbd7cb2 | 682 | |
fe88fc68 | 683 | intel_disable_dsi_pll(encoder); |
4e646495 | 684 | } |
20e5bf66 | 685 | |
1dbd7cb2 SK |
686 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
687 | { | |
20e5bf66 | 688 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 SK |
689 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
690 | ||
691 | DRM_DEBUG_KMS("\n"); | |
692 | ||
c315faf8 ID |
693 | intel_dsi_disable(encoder); |
694 | ||
1dbd7cb2 SK |
695 | intel_dsi_clear_device_ready(encoder); |
696 | ||
d1877c0f | 697 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d6e3af54 US |
698 | u32 val; |
699 | ||
700 | val = I915_READ(DSPCLK_GATE_D); | |
701 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
702 | I915_WRITE(DSPCLK_GATE_D, val); | |
703 | } | |
20e5bf66 | 704 | |
593e0622 | 705 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
706 | |
707 | msleep(intel_dsi->panel_off_delay); | |
fc45e821 SK |
708 | |
709 | /* Panel Disable over CRC PMIC */ | |
710 | if (intel_dsi->gpio_panel) | |
711 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1d5c65ed VS |
712 | |
713 | /* | |
714 | * FIXME As we do with eDP, just make a note of the time here | |
715 | * and perform the wait before the next panel power on. | |
716 | */ | |
717 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 718 | } |
4e646495 JN |
719 | |
720 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
721 | enum pipe *pipe) | |
722 | { | |
723 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
724 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
725 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 726 | enum intel_display_power_domain power_domain; |
e7d7cad0 | 727 | enum port port; |
1dcec2f3 | 728 | bool active = false; |
4e646495 JN |
729 | |
730 | DRM_DEBUG_KMS("\n"); | |
731 | ||
6d129bea | 732 | power_domain = intel_display_port_power_domain(encoder); |
3f3f42b8 | 733 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
734 | return false; |
735 | ||
db18b6a6 ID |
736 | /* |
737 | * On Broxton the PLL needs to be enabled with a valid divider | |
738 | * configuration, otherwise accessing DSI registers will hang the | |
739 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
740 | */ | |
741 | if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) | |
742 | goto out_put_power; | |
743 | ||
4e646495 | 744 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 745 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
746 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
747 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
1dcec2f3 | 748 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 | 749 | |
e6f57789 JN |
750 | /* |
751 | * Due to some hardware limitations on VLV/CHV, the DPI enable | |
752 | * bit in port C control register does not get set. As a | |
753 | * workaround, check pipe B conf instead. | |
c0beefd2 | 754 | */ |
e6f57789 | 755 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C) |
1dcec2f3 | 756 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 757 | |
1dcec2f3 JN |
758 | /* Try command mode if video mode not enabled */ |
759 | if (!enabled) { | |
760 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
761 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 762 | } |
1dcec2f3 JN |
763 | |
764 | if (!enabled) | |
765 | continue; | |
766 | ||
767 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
768 | continue; | |
769 | ||
6b93e9c8 JN |
770 | if (IS_BROXTON(dev_priv)) { |
771 | u32 tmp = I915_READ(MIPI_CTRL(port)); | |
772 | tmp &= BXT_PIPE_SELECT_MASK; | |
773 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
774 | ||
775 | if (WARN_ON(tmp > PIPE_C)) | |
776 | continue; | |
777 | ||
778 | *pipe = tmp; | |
779 | } else { | |
780 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
781 | } | |
782 | ||
1dcec2f3 JN |
783 | active = true; |
784 | break; | |
4e646495 | 785 | } |
1dcec2f3 | 786 | |
db18b6a6 | 787 | out_put_power: |
3f3f42b8 | 788 | intel_display_power_put(dev_priv, power_domain); |
4e646495 | 789 | |
1dcec2f3 | 790 | return active; |
4e646495 JN |
791 | } |
792 | ||
6f0e7535 R |
793 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
794 | struct intel_crtc_state *pipe_config) | |
795 | { | |
796 | struct drm_device *dev = encoder->base.dev; | |
797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
798 | struct drm_display_mode *adjusted_mode = | |
799 | &pipe_config->base.adjusted_mode; | |
042ab0c3 R |
800 | struct drm_display_mode *adjusted_mode_sw; |
801 | struct intel_crtc *intel_crtc; | |
6f0e7535 | 802 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
cefc4e18 | 803 | unsigned int lane_count = intel_dsi->lane_count; |
6f0e7535 R |
804 | unsigned int bpp, fmt; |
805 | enum port port; | |
cefc4e18 | 806 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
042ab0c3 R |
807 | u16 hfp_sw, hsync_sw, hbp_sw; |
808 | u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, | |
809 | crtc_hblank_start_sw, crtc_hblank_end_sw; | |
810 | ||
811 | intel_crtc = to_intel_crtc(encoder->base.crtc); | |
812 | adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode; | |
6f0e7535 R |
813 | |
814 | /* | |
815 | * Atleast one port is active as encoder->get_config called only if | |
816 | * encoder->get_hw_state() returns true. | |
817 | */ | |
818 | for_each_dsi_port(port, intel_dsi->ports) { | |
819 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
820 | break; | |
821 | } | |
822 | ||
823 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
824 | pipe_config->pipe_bpp = | |
825 | mipi_dsi_pixel_format_to_bpp( | |
826 | pixel_format_from_register_bits(fmt)); | |
827 | bpp = pipe_config->pipe_bpp; | |
828 | ||
829 | /* In terms of pixels */ | |
830 | adjusted_mode->crtc_hdisplay = | |
831 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
832 | adjusted_mode->crtc_vdisplay = | |
833 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
834 | adjusted_mode->crtc_vtotal = | |
835 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
836 | ||
cefc4e18 R |
837 | hactive = adjusted_mode->crtc_hdisplay; |
838 | hfp = I915_READ(MIPI_HFP_COUNT(port)); | |
839 | ||
6f0e7535 | 840 | /* |
cefc4e18 R |
841 | * Meaningful for video mode non-burst sync pulse mode only, |
842 | * can be zero for non-burst sync events and burst modes | |
6f0e7535 | 843 | */ |
cefc4e18 R |
844 | hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); |
845 | hbp = I915_READ(MIPI_HBP_COUNT(port)); | |
846 | ||
847 | /* harizontal values are in terms of high speed byte clock */ | |
848 | hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, | |
849 | intel_dsi->burst_mode_ratio); | |
850 | hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, | |
851 | intel_dsi->burst_mode_ratio); | |
852 | hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, | |
853 | intel_dsi->burst_mode_ratio); | |
854 | ||
855 | if (intel_dsi->dual_link) { | |
856 | hfp *= 2; | |
857 | hsync *= 2; | |
858 | hbp *= 2; | |
859 | } | |
6f0e7535 R |
860 | |
861 | /* vertical values are in terms of lines */ | |
862 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
863 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
864 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
865 | ||
cefc4e18 R |
866 | adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; |
867 | adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; | |
868 | adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; | |
6f0e7535 | 869 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; |
cefc4e18 | 870 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; |
6f0e7535 | 871 | |
cefc4e18 R |
872 | adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; |
873 | adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; | |
6f0e7535 R |
874 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; |
875 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
6f0e7535 | 876 | |
042ab0c3 R |
877 | /* |
878 | * In BXT DSI there is no regs programmed with few horizontal timings | |
879 | * in Pixels but txbyteclkhs.. So retrieval process adds some | |
880 | * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. | |
881 | * Actually here for the given adjusted_mode, we are calculating the | |
882 | * value programmed to the port and then back to the horizontal timing | |
883 | * param in pixels. This is the expected value, including roundup errors | |
884 | * And if that is same as retrieved value from port, then | |
885 | * (HW state) adjusted_mode's horizontal timings are corrected to | |
886 | * match with SW state to nullify the errors. | |
887 | */ | |
888 | /* Calculating the value programmed to the Port register */ | |
889 | hfp_sw = adjusted_mode_sw->crtc_hsync_start - | |
890 | adjusted_mode_sw->crtc_hdisplay; | |
891 | hsync_sw = adjusted_mode_sw->crtc_hsync_end - | |
892 | adjusted_mode_sw->crtc_hsync_start; | |
893 | hbp_sw = adjusted_mode_sw->crtc_htotal - | |
894 | adjusted_mode_sw->crtc_hsync_end; | |
895 | ||
896 | if (intel_dsi->dual_link) { | |
897 | hfp_sw /= 2; | |
898 | hsync_sw /= 2; | |
899 | hbp_sw /= 2; | |
900 | } | |
901 | ||
902 | hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, | |
903 | intel_dsi->burst_mode_ratio); | |
904 | hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, | |
905 | intel_dsi->burst_mode_ratio); | |
906 | hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, | |
907 | intel_dsi->burst_mode_ratio); | |
908 | ||
909 | /* Reverse calculating the adjusted mode parameters from port reg vals*/ | |
910 | hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, | |
911 | intel_dsi->burst_mode_ratio); | |
912 | hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, | |
913 | intel_dsi->burst_mode_ratio); | |
914 | hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, | |
915 | intel_dsi->burst_mode_ratio); | |
916 | ||
917 | if (intel_dsi->dual_link) { | |
918 | hfp_sw *= 2; | |
919 | hsync_sw *= 2; | |
920 | hbp_sw *= 2; | |
921 | } | |
922 | ||
923 | crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + | |
924 | hsync_sw + hbp_sw; | |
925 | crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; | |
926 | crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; | |
927 | crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; | |
928 | crtc_hblank_end_sw = crtc_htotal_sw; | |
929 | ||
930 | if (adjusted_mode->crtc_htotal == crtc_htotal_sw) | |
931 | adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; | |
932 | ||
933 | if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) | |
934 | adjusted_mode->crtc_hsync_start = | |
935 | adjusted_mode_sw->crtc_hsync_start; | |
936 | ||
937 | if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) | |
938 | adjusted_mode->crtc_hsync_end = | |
939 | adjusted_mode_sw->crtc_hsync_end; | |
940 | ||
941 | if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) | |
942 | adjusted_mode->crtc_hblank_start = | |
943 | adjusted_mode_sw->crtc_hblank_start; | |
944 | ||
945 | if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) | |
946 | adjusted_mode->crtc_hblank_end = | |
947 | adjusted_mode_sw->crtc_hblank_end; | |
948 | } | |
6f0e7535 | 949 | |
4e646495 | 950 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 951 | struct intel_crtc_state *pipe_config) |
4e646495 | 952 | { |
6f0e7535 | 953 | struct drm_device *dev = encoder->base.dev; |
d7d85d85 | 954 | u32 pclk; |
4e646495 JN |
955 | DRM_DEBUG_KMS("\n"); |
956 | ||
a65347ba JN |
957 | pipe_config->has_dsi_encoder = true; |
958 | ||
6f0e7535 R |
959 | if (IS_BROXTON(dev)) |
960 | bxt_dsi_get_pipe_config(encoder, pipe_config); | |
961 | ||
47eacbab VS |
962 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, |
963 | pipe_config); | |
f573de5a SK |
964 | if (!pclk) |
965 | return; | |
966 | ||
2d112de7 | 967 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 968 | pipe_config->port_clock = pclk; |
4e646495 JN |
969 | } |
970 | ||
c19de8eb DL |
971 | static enum drm_mode_status |
972 | intel_dsi_mode_valid(struct drm_connector *connector, | |
973 | struct drm_display_mode *mode) | |
4e646495 JN |
974 | { |
975 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
f4ee265f | 976 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
759a1e98 | 977 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
978 | |
979 | DRM_DEBUG_KMS("\n"); | |
980 | ||
981 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
982 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
983 | return MODE_NO_DBLESCAN; | |
984 | } | |
985 | ||
986 | if (fixed_mode) { | |
987 | if (mode->hdisplay > fixed_mode->hdisplay) | |
988 | return MODE_PANEL; | |
989 | if (mode->vdisplay > fixed_mode->vdisplay) | |
990 | return MODE_PANEL; | |
759a1e98 MK |
991 | if (fixed_mode->clock > max_dotclk) |
992 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
993 | } |
994 | ||
36d21f4c | 995 | return MODE_OK; |
4e646495 JN |
996 | } |
997 | ||
998 | /* return txclkesc cycles in terms of divider and duration in us */ | |
999 | static u16 txclkesc(u32 divider, unsigned int us) | |
1000 | { | |
1001 | switch (divider) { | |
1002 | case ESCAPE_CLOCK_DIVIDER_1: | |
1003 | default: | |
1004 | return 20 * us; | |
1005 | case ESCAPE_CLOCK_DIVIDER_2: | |
1006 | return 10 * us; | |
1007 | case ESCAPE_CLOCK_DIVIDER_4: | |
1008 | return 5 * us; | |
1009 | } | |
1010 | } | |
1011 | ||
4e646495 | 1012 | static void set_dsi_timings(struct drm_encoder *encoder, |
5e7234c9 | 1013 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
1014 | { |
1015 | struct drm_device *dev = encoder->dev; | |
1016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 1017 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 1018 | enum port port; |
1e78aa01 | 1019 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
1020 | unsigned int lane_count = intel_dsi->lane_count; |
1021 | ||
1022 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
1023 | ||
aad941d5 VS |
1024 | hactive = adjusted_mode->crtc_hdisplay; |
1025 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
1026 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
1027 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 1028 | |
aa102d28 GS |
1029 | if (intel_dsi->dual_link) { |
1030 | hactive /= 2; | |
1031 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1032 | hactive += intel_dsi->pixel_overlap; | |
1033 | hfp /= 2; | |
1034 | hsync /= 2; | |
1035 | hbp /= 2; | |
1036 | } | |
1037 | ||
aad941d5 VS |
1038 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
1039 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
1040 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
1041 | |
1042 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 1043 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 1044 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
1045 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
1046 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 1047 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 1048 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 1049 | |
aa102d28 | 1050 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
1051 | if (IS_BROXTON(dev)) { |
1052 | /* | |
1053 | * Program hdisplay and vdisplay on MIPI transcoder. | |
1054 | * This is different from calculated hactive and | |
1055 | * vactive, as they are calculated per channel basis, | |
1056 | * whereas these values should be based on resolution. | |
1057 | */ | |
1058 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 1059 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 1060 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 1061 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 1062 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 1063 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
1064 | } |
1065 | ||
aa102d28 GS |
1066 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
1067 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
1068 | ||
1069 | /* meaningful for video mode non-burst sync pulse mode only, | |
1070 | * can be zero for non-burst sync events and burst modes */ | |
1071 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
1072 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
1073 | ||
1074 | /* vertical values are in terms of lines */ | |
1075 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
1076 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
1077 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
1078 | } | |
4e646495 JN |
1079 | } |
1080 | ||
1e78aa01 JN |
1081 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
1082 | { | |
1083 | switch (fmt) { | |
1084 | case MIPI_DSI_FMT_RGB888: | |
1085 | return VID_MODE_FORMAT_RGB888; | |
1086 | case MIPI_DSI_FMT_RGB666: | |
1087 | return VID_MODE_FORMAT_RGB666; | |
1088 | case MIPI_DSI_FMT_RGB666_PACKED: | |
1089 | return VID_MODE_FORMAT_RGB666_PACKED; | |
1090 | case MIPI_DSI_FMT_RGB565: | |
1091 | return VID_MODE_FORMAT_RGB565; | |
1092 | default: | |
1093 | MISSING_CASE(fmt); | |
1094 | return VID_MODE_FORMAT_RGB666; | |
1095 | } | |
1096 | } | |
1097 | ||
07e4fb9e | 1098 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
1099 | { |
1100 | struct drm_encoder *encoder = &intel_encoder->base; | |
1101 | struct drm_device *dev = encoder->dev; | |
1102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1103 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
1104 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
7c5f93b0 | 1105 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 1106 | enum port port; |
1e78aa01 | 1107 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 1108 | u32 val, tmp; |
24ee0e64 | 1109 | u16 mode_hdisplay; |
4e646495 | 1110 | |
e7d7cad0 | 1111 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 1112 | |
aad941d5 | 1113 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 1114 | |
24ee0e64 GS |
1115 | if (intel_dsi->dual_link) { |
1116 | mode_hdisplay /= 2; | |
1117 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1118 | mode_hdisplay += intel_dsi->pixel_overlap; | |
1119 | } | |
4e646495 | 1120 | |
24ee0e64 | 1121 | for_each_dsi_port(port, intel_dsi->ports) { |
666a4537 | 1122 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
d2e08c0f SS |
1123 | /* |
1124 | * escape clock divider, 20MHz, shared for A and C. | |
1125 | * device ready must be off when doing this! txclkesc? | |
1126 | */ | |
1127 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1128 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1129 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1130 | ESCAPE_CLOCK_DIVIDER_1); | |
1131 | ||
1132 | /* read request priority is per pipe */ | |
1133 | tmp = I915_READ(MIPI_CTRL(port)); | |
1134 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1135 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1136 | READ_REQUEST_PRIORITY_HIGH); | |
1137 | } else if (IS_BROXTON(dev)) { | |
56c48978 D |
1138 | enum pipe pipe = intel_crtc->pipe; |
1139 | ||
d2e08c0f SS |
1140 | tmp = I915_READ(MIPI_CTRL(port)); |
1141 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1142 | ||
56c48978 | 1143 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1144 | I915_WRITE(MIPI_CTRL(port), tmp); |
1145 | } | |
24ee0e64 GS |
1146 | |
1147 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1148 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1149 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1150 | ||
1151 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1152 | ||
1153 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1154 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1155 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1156 | } | |
4e646495 JN |
1157 | |
1158 | set_dsi_timings(encoder, adjusted_mode); | |
1159 | ||
1160 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1161 | if (is_cmd_mode(intel_dsi)) { | |
1162 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1163 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1164 | } else { | |
1165 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1166 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1167 | } |
4e646495 | 1168 | |
24ee0e64 GS |
1169 | tmp = 0; |
1170 | if (intel_dsi->eotp_pkt == 0) | |
1171 | tmp |= EOT_DISABLE; | |
1172 | if (intel_dsi->clock_stop) | |
1173 | tmp |= CLOCKSTOP; | |
4e646495 | 1174 | |
24ee0e64 GS |
1175 | for_each_dsi_port(port, intel_dsi->ports) { |
1176 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1177 | ||
1178 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1179 | * EOT and stop state. */ | |
1180 | ||
1181 | /* | |
1182 | * In burst mode, value greater than one DPI line Time in byte | |
1183 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1184 | * said value is recommended. | |
1185 | * | |
1186 | * In non-burst mode, Value greater than one DPI frame time in | |
1187 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1188 | * said value is recommended. | |
1189 | * | |
1190 | * In DBI only mode, value greater than one DBI frame time in | |
1191 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1192 | * said value is recommended. | |
1193 | */ | |
4e646495 | 1194 | |
24ee0e64 GS |
1195 | if (is_vid_mode(intel_dsi) && |
1196 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1197 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1198 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1199 | intel_dsi->lane_count, |
1200 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1201 | } else { |
1202 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1203 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1204 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1205 | bpp, intel_dsi->lane_count, |
1206 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1207 | } |
1208 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1209 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1210 | intel_dsi->turn_arnd_val); | |
1211 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1212 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1213 | |
24ee0e64 | 1214 | /* dphy stuff */ |
f1c79f16 | 1215 | |
24ee0e64 GS |
1216 | /* in terms of low power clock */ |
1217 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1218 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1219 | |
d2e08c0f SS |
1220 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
1221 | /* | |
1222 | * BXT spec says write MIPI_INIT_COUNT for | |
1223 | * both the ports, even if only one is | |
1224 | * getting used. So write the other port | |
1225 | * if not in dual link mode. | |
1226 | */ | |
1227 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1228 | PORT_A ? PORT_C : PORT_A), | |
1229 | intel_dsi->init_count); | |
1230 | } | |
4e646495 | 1231 | |
24ee0e64 | 1232 | /* recovery disables */ |
87c54d0e | 1233 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1234 | |
24ee0e64 GS |
1235 | /* in terms of low power clock */ |
1236 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1237 | |
24ee0e64 GS |
1238 | /* in terms of txbyteclkhs. actual high to low switch + |
1239 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1240 | * | |
1241 | * XXX: write MIPI_STOP_STATE_STALL? | |
1242 | */ | |
1243 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1244 | intel_dsi->hs_to_lp_count); | |
1245 | ||
1246 | /* XXX: low power clock equivalence in terms of byte clock. | |
1247 | * the number of byte clocks occupied in one low power clock. | |
1248 | * based on txbyteclkhs and txclkesc. | |
1249 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1250 | * ) / 105.??? | |
1251 | */ | |
1252 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1253 | ||
1254 | /* the bw essential for transmitting 16 long packets containing | |
1255 | * 252 bytes meant for dcs write memory command is programmed in | |
1256 | * this register in terms of byte clocks. based on dsi transfer | |
1257 | * rate and the number of lanes configured the time taken to | |
1258 | * transmit 16 long packets in a dsi stream varies. */ | |
1259 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1260 | ||
1261 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1262 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1263 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1264 | ||
1265 | if (is_vid_mode(intel_dsi)) | |
1266 | /* Some panels might have resolution which is not a | |
1267 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1268 | * resolution support for such panels by default */ | |
1269 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1270 | intel_dsi->video_frmt_cfg_bits | | |
1271 | intel_dsi->video_mode_format | | |
1272 | IP_TG_CONFIG | | |
1273 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1274 | } | |
4e646495 JN |
1275 | } |
1276 | ||
1277 | static enum drm_connector_status | |
1278 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
1279 | { | |
36d21f4c | 1280 | return connector_status_connected; |
4e646495 JN |
1281 | } |
1282 | ||
1283 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
1284 | { | |
1285 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1286 | struct drm_display_mode *mode; | |
1287 | ||
1288 | DRM_DEBUG_KMS("\n"); | |
1289 | ||
1290 | if (!intel_connector->panel.fixed_mode) { | |
1291 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1292 | return 0; | |
1293 | } | |
1294 | ||
1295 | mode = drm_mode_duplicate(connector->dev, | |
1296 | intel_connector->panel.fixed_mode); | |
1297 | if (!mode) { | |
1298 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | drm_mode_probed_add(connector, mode); | |
1303 | return 1; | |
1304 | } | |
1305 | ||
f4ee265f VS |
1306 | static int intel_dsi_set_property(struct drm_connector *connector, |
1307 | struct drm_property *property, | |
1308 | uint64_t val) | |
1309 | { | |
1310 | struct drm_device *dev = connector->dev; | |
1311 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1312 | struct drm_crtc *crtc; | |
1313 | int ret; | |
1314 | ||
1315 | ret = drm_object_property_set_value(&connector->base, property, val); | |
1316 | if (ret) | |
1317 | return ret; | |
1318 | ||
1319 | if (property == dev->mode_config.scaling_mode_property) { | |
1320 | if (val == DRM_MODE_SCALE_NONE) { | |
1321 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
1322 | return -EINVAL; | |
1323 | } | |
234126c6 VS |
1324 | if (HAS_GMCH_DISPLAY(dev) && |
1325 | val == DRM_MODE_SCALE_CENTER) { | |
1326 | DRM_DEBUG_KMS("centering not supported\n"); | |
1327 | return -EINVAL; | |
1328 | } | |
f4ee265f VS |
1329 | |
1330 | if (intel_connector->panel.fitting_mode == val) | |
1331 | return 0; | |
1332 | ||
1333 | intel_connector->panel.fitting_mode = val; | |
1334 | } | |
1335 | ||
1336 | crtc = intel_attached_encoder(connector)->base.crtc; | |
1337 | if (crtc && crtc->state->enable) { | |
1338 | /* | |
1339 | * If the CRTC is enabled, the display will be changed | |
1340 | * according to the new panel fitting mode. | |
1341 | */ | |
1342 | intel_crtc_restore_mode(crtc); | |
1343 | } | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
593e0622 | 1348 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1349 | { |
1350 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1351 | ||
1352 | DRM_DEBUG_KMS("\n"); | |
1353 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1354 | drm_connector_cleanup(connector); |
1355 | kfree(connector); | |
1356 | } | |
1357 | ||
593e0622 JN |
1358 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1359 | { | |
1360 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1361 | ||
1362 | if (intel_dsi->panel) { | |
1363 | drm_panel_detach(intel_dsi->panel); | |
1364 | /* XXX: Logically this call belongs in the panel driver. */ | |
1365 | drm_panel_remove(intel_dsi->panel); | |
1366 | } | |
fc45e821 SK |
1367 | |
1368 | /* dispose of the gpios */ | |
1369 | if (intel_dsi->gpio_panel) | |
1370 | gpiod_put(intel_dsi->gpio_panel); | |
1371 | ||
593e0622 JN |
1372 | intel_encoder_destroy(encoder); |
1373 | } | |
1374 | ||
4e646495 | 1375 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1376 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1377 | }; |
1378 | ||
1379 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1380 | .get_modes = intel_dsi_get_modes, | |
1381 | .mode_valid = intel_dsi_mode_valid, | |
1382 | .best_encoder = intel_best_encoder, | |
1383 | }; | |
1384 | ||
1385 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1386 | .dpms = drm_atomic_helper_connector_dpms, |
4e646495 | 1387 | .detect = intel_dsi_detect, |
593e0622 | 1388 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1389 | .fill_modes = drm_helper_probe_single_connector_modes, |
f4ee265f | 1390 | .set_property = intel_dsi_set_property, |
2545e4a6 | 1391 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1392 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1393 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1394 | }; |
1395 | ||
f4ee265f VS |
1396 | static void intel_dsi_add_properties(struct intel_connector *connector) |
1397 | { | |
1398 | struct drm_device *dev = connector->base.dev; | |
1399 | ||
1400 | if (connector->panel.fixed_mode) { | |
1401 | drm_mode_create_scaling_mode_property(dev); | |
1402 | drm_object_attach_property(&connector->base.base, | |
1403 | dev->mode_config.scaling_mode_property, | |
1404 | DRM_MODE_SCALE_ASPECT); | |
1405 | connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
1406 | } | |
1407 | } | |
1408 | ||
4328633d | 1409 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
1410 | { |
1411 | struct intel_dsi *intel_dsi; | |
1412 | struct intel_encoder *intel_encoder; | |
1413 | struct drm_encoder *encoder; | |
1414 | struct intel_connector *intel_connector; | |
1415 | struct drm_connector *connector; | |
593e0622 | 1416 | struct drm_display_mode *scan, *fixed_mode = NULL; |
b6fdd0f2 | 1417 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e9804fd | 1418 | enum port port; |
4e646495 JN |
1419 | unsigned int i; |
1420 | ||
1421 | DRM_DEBUG_KMS("\n"); | |
1422 | ||
3e6bd011 | 1423 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1424 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1425 | return; |
3e6bd011 | 1426 | |
666a4537 | 1427 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
868d665b | 1428 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
c6c794a2 SS |
1429 | } else if (IS_BROXTON(dev)) { |
1430 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; | |
868d665b CJ |
1431 | } else { |
1432 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1433 | return; | |
1434 | } | |
3e6bd011 | 1435 | |
4e646495 JN |
1436 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1437 | if (!intel_dsi) | |
4328633d | 1438 | return; |
4e646495 | 1439 | |
08d9bc92 | 1440 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1441 | if (!intel_connector) { |
1442 | kfree(intel_dsi); | |
4328633d | 1443 | return; |
4e646495 JN |
1444 | } |
1445 | ||
1446 | intel_encoder = &intel_dsi->base; | |
1447 | encoder = &intel_encoder->base; | |
1448 | intel_dsi->attached_connector = intel_connector; | |
1449 | ||
1450 | connector = &intel_connector->base; | |
1451 | ||
13a3d91f | 1452 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
580d8ed5 | 1453 | "DSI %c", port_name(port)); |
4e646495 | 1454 | |
4e646495 | 1455 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1456 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1457 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1458 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1459 | intel_encoder->post_disable = intel_dsi_post_disable; |
1460 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1461 | intel_encoder->get_config = intel_dsi_get_config; | |
1462 | ||
1463 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1464 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 1465 | |
2e85ab4f JN |
1466 | /* |
1467 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1468 | * port C. BXT isn't limited like this. | |
1469 | */ | |
1470 | if (IS_BROXTON(dev_priv)) | |
1471 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); | |
1472 | else if (port == PORT_A) | |
701d25b4 | 1473 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1474 | else |
701d25b4 | 1475 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1476 | |
90198355 | 1477 | if (dev_priv->vbt.dsi.config->dual_link) { |
701d25b4 | 1478 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
90198355 JN |
1479 | |
1480 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
1481 | case DL_DCS_PORT_A: | |
1482 | intel_dsi->dcs_backlight_ports = BIT(PORT_A); | |
1483 | break; | |
1484 | case DL_DCS_PORT_C: | |
1485 | intel_dsi->dcs_backlight_ports = BIT(PORT_C); | |
1486 | break; | |
1487 | default: | |
1488 | case DL_DCS_PORT_A_AND_C: | |
1489 | intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C); | |
1490 | break; | |
1491 | } | |
1ecc1c6c D |
1492 | |
1493 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
1494 | case DL_DCS_PORT_A: | |
1495 | intel_dsi->dcs_cabc_ports = BIT(PORT_A); | |
1496 | break; | |
1497 | case DL_DCS_PORT_C: | |
1498 | intel_dsi->dcs_cabc_ports = BIT(PORT_C); | |
1499 | break; | |
1500 | default: | |
1501 | case DL_DCS_PORT_A_AND_C: | |
1502 | intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C); | |
1503 | break; | |
1504 | } | |
90198355 | 1505 | } else { |
701d25b4 | 1506 | intel_dsi->ports = BIT(port); |
90198355 | 1507 | intel_dsi->dcs_backlight_ports = BIT(port); |
1ecc1c6c | 1508 | intel_dsi->dcs_cabc_ports = BIT(port); |
90198355 | 1509 | } |
82425785 | 1510 | |
1ecc1c6c D |
1511 | if (!dev_priv->vbt.dsi.config->cabc_supported) |
1512 | intel_dsi->dcs_cabc_ports = 0; | |
1513 | ||
7e9804fd JN |
1514 | /* Create a DSI host (and a device) for each port. */ |
1515 | for_each_dsi_port(port, intel_dsi->ports) { | |
1516 | struct intel_dsi_host *host; | |
1517 | ||
1518 | host = intel_dsi_host_init(intel_dsi, port); | |
1519 | if (!host) | |
1520 | goto err; | |
1521 | ||
1522 | intel_dsi->dsi_hosts[port] = host; | |
1523 | } | |
1524 | ||
593e0622 JN |
1525 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1526 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1527 | intel_dsi_drivers[i].panel_id); | |
1528 | if (intel_dsi->panel) | |
4e646495 JN |
1529 | break; |
1530 | } | |
1531 | ||
593e0622 | 1532 | if (!intel_dsi->panel) { |
4e646495 JN |
1533 | DRM_DEBUG_KMS("no device found\n"); |
1534 | goto err; | |
1535 | } | |
1536 | ||
fc45e821 SK |
1537 | /* |
1538 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1539 | * Panel control. | |
1540 | */ | |
1541 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1542 | intel_dsi->gpio_panel = | |
1543 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1544 | ||
1545 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1546 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1547 | intel_dsi->gpio_panel = NULL; | |
1548 | } | |
1549 | } | |
1550 | ||
4e646495 | 1551 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1552 | intel_encoder->cloneable = 0; |
4e646495 JN |
1553 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1554 | DRM_MODE_CONNECTOR_DSI); | |
1555 | ||
1556 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1557 | ||
1558 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1559 | connector->interlace_allowed = false; | |
1560 | connector->doublescan_allowed = false; | |
1561 | ||
1562 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1563 | ||
593e0622 JN |
1564 | drm_panel_attach(intel_dsi->panel, connector); |
1565 | ||
1566 | mutex_lock(&dev->mode_config.mutex); | |
1567 | drm_panel_get_modes(intel_dsi->panel); | |
1568 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1569 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1570 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1571 | break; | |
1572 | } | |
1573 | } | |
1574 | mutex_unlock(&dev->mode_config.mutex); | |
1575 | ||
4e646495 JN |
1576 | if (!fixed_mode) { |
1577 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1578 | goto err; | |
1579 | } | |
1580 | ||
4b6ed685 | 1581 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
f4ee265f VS |
1582 | |
1583 | intel_dsi_add_properties(intel_connector); | |
1584 | ||
1585 | drm_connector_register(connector); | |
1586 | ||
b029e66f | 1587 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
4e646495 | 1588 | |
4328633d | 1589 | return; |
4e646495 JN |
1590 | |
1591 | err: | |
1592 | drm_encoder_cleanup(&intel_encoder->base); | |
1593 | kfree(intel_dsi); | |
1594 | kfree(intel_connector); | |
4e646495 | 1595 | } |