Commit | Line | Data |
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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
9f218336 PZ |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { | |
0e631adc | 46 | return dev_priv->fbc.activate != NULL; |
9f218336 PZ |
47 | } |
48 | ||
57105022 PZ |
49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
50 | { | |
51 | return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; | |
52 | } | |
53 | ||
2db3366b PZ |
54 | /* |
55 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
56 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
57 | * origin so the x and y offsets can actually fit the registers. As a | |
58 | * consequence, the fence doesn't really start exactly at the display plane | |
59 | * address we program because it starts at the real start of the buffer, so we | |
60 | * have to take this into consideration here. | |
61 | */ | |
62 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
63 | { | |
64 | return crtc->base.y - crtc->adjusted_y; | |
65 | } | |
66 | ||
c5ecd469 PZ |
67 | /* |
68 | * For SKL+, the plane source size used by the hardware is based on the value we | |
69 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value | |
70 | * we wrote to PIPESRC. | |
71 | */ | |
72 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, | |
73 | int *width, int *height) | |
74 | { | |
75 | struct intel_plane_state *plane_state = | |
76 | to_intel_plane_state(crtc->base.primary->state); | |
77 | int w, h; | |
78 | ||
79 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { | |
80 | w = drm_rect_height(&plane_state->src) >> 16; | |
81 | h = drm_rect_width(&plane_state->src) >> 16; | |
82 | } else { | |
83 | w = drm_rect_width(&plane_state->src) >> 16; | |
84 | h = drm_rect_height(&plane_state->src) >> 16; | |
85 | } | |
86 | ||
87 | if (width) | |
88 | *width = w; | |
89 | if (height) | |
90 | *height = h; | |
91 | } | |
92 | ||
93 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc, | |
94 | struct drm_framebuffer *fb) | |
95 | { | |
96 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
97 | int lines; | |
98 | ||
99 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); | |
100 | if (INTEL_INFO(dev_priv)->gen >= 7) | |
101 | lines = min(lines, 2048); | |
102 | ||
103 | /* Hardware needs the full buffer stride, not just the active area. */ | |
104 | return lines * fb->pitches[0]; | |
105 | } | |
106 | ||
0e631adc | 107 | static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 108 | { |
7ff0ebcc RV |
109 | u32 fbc_ctl; |
110 | ||
0e631adc | 111 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
112 | |
113 | /* Disable compression */ | |
114 | fbc_ctl = I915_READ(FBC_CONTROL); | |
115 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
116 | return; | |
117 | ||
118 | fbc_ctl &= ~FBC_CTL_EN; | |
119 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
120 | ||
121 | /* Wait for compressing bit to clear */ | |
122 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
123 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
124 | return; | |
125 | } | |
126 | ||
0e631adc | 127 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
128 | } |
129 | ||
0e631adc | 130 | static void i8xx_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 131 | { |
220285f2 PZ |
132 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
133 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 134 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
135 | int cfb_pitch; |
136 | int i; | |
137 | u32 fbc_ctl; | |
138 | ||
0e631adc | 139 | dev_priv->fbc.active = true; |
7ff0ebcc | 140 | |
60ee5cd2 JN |
141 | /* Note: fbc.threshold == 1 for i8xx */ |
142 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
143 | if (fb->pitches[0] < cfb_pitch) |
144 | cfb_pitch = fb->pitches[0]; | |
145 | ||
146 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 147 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
148 | cfb_pitch = (cfb_pitch / 32) - 1; |
149 | else | |
150 | cfb_pitch = (cfb_pitch / 64) - 1; | |
151 | ||
152 | /* Clear old tags */ | |
153 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 154 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 155 | |
7733b49b | 156 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
157 | u32 fbc_ctl2; |
158 | ||
159 | /* Set it up... */ | |
160 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
220285f2 | 161 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 162 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
2db3366b | 163 | I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
164 | } |
165 | ||
166 | /* enable it... */ | |
167 | fbc_ctl = I915_READ(FBC_CONTROL); | |
168 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
169 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 170 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
171 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
172 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
173 | fbc_ctl |= obj->fence_reg; | |
174 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
175 | ||
0e631adc | 176 | DRM_DEBUG_KMS("activated FBC, pitch %d, yoff %d, plane %c\n", |
220285f2 | 177 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
7ff0ebcc RV |
178 | } |
179 | ||
0e631adc | 180 | static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 181 | { |
7ff0ebcc RV |
182 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
183 | } | |
184 | ||
0e631adc | 185 | static void g4x_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 186 | { |
220285f2 PZ |
187 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
188 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 189 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
190 | u32 dpfc_ctl; |
191 | ||
0e631adc | 192 | dev_priv->fbc.active = true; |
7ff0ebcc | 193 | |
220285f2 | 194 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
7ff0ebcc RV |
195 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
196 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
197 | else | |
198 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
199 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
200 | ||
2db3366b | 201 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
202 | |
203 | /* enable it... */ | |
204 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
205 | ||
0e631adc | 206 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
207 | } |
208 | ||
0e631adc | 209 | static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 210 | { |
7ff0ebcc RV |
211 | u32 dpfc_ctl; |
212 | ||
0e631adc | 213 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
214 | |
215 | /* Disable compression */ | |
216 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
217 | if (dpfc_ctl & DPFC_CTL_EN) { | |
218 | dpfc_ctl &= ~DPFC_CTL_EN; | |
219 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
220 | ||
0e631adc | 221 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
222 | } |
223 | } | |
224 | ||
0e631adc | 225 | static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 226 | { |
7ff0ebcc RV |
227 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
228 | } | |
229 | ||
d5ce4164 PZ |
230 | /* This function forces a CFB recompression through the nuke operation. */ |
231 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) | |
7ff0ebcc | 232 | { |
dbef0f15 PZ |
233 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
234 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
235 | } |
236 | ||
0e631adc | 237 | static void ilk_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 238 | { |
220285f2 PZ |
239 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
240 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 241 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 242 | u32 dpfc_ctl; |
ce65e47b | 243 | int threshold = dev_priv->fbc.threshold; |
2db3366b | 244 | unsigned int y_offset; |
7ff0ebcc | 245 | |
0e631adc | 246 | dev_priv->fbc.active = true; |
7ff0ebcc | 247 | |
220285f2 | 248 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 249 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 250 | threshold++; |
7ff0ebcc | 251 | |
ce65e47b | 252 | switch (threshold) { |
7ff0ebcc RV |
253 | case 4: |
254 | case 3: | |
255 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
256 | break; | |
257 | case 2: | |
258 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
259 | break; | |
260 | case 1: | |
261 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
262 | break; | |
263 | } | |
264 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 265 | if (IS_GEN5(dev_priv)) |
7ff0ebcc RV |
266 | dpfc_ctl |= obj->fence_reg; |
267 | ||
2db3366b PZ |
268 | y_offset = get_crtc_fence_y_offset(crtc); |
269 | I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); | |
7ff0ebcc RV |
270 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
271 | /* enable it... */ | |
272 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
273 | ||
7733b49b | 274 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc RV |
275 | I915_WRITE(SNB_DPFC_CTL_SA, |
276 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 277 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
7ff0ebcc RV |
278 | } |
279 | ||
d5ce4164 | 280 | intel_fbc_recompress(dev_priv); |
dbef0f15 | 281 | |
0e631adc | 282 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
283 | } |
284 | ||
0e631adc | 285 | static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 286 | { |
7ff0ebcc RV |
287 | u32 dpfc_ctl; |
288 | ||
0e631adc | 289 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
290 | |
291 | /* Disable compression */ | |
292 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
293 | if (dpfc_ctl & DPFC_CTL_EN) { | |
294 | dpfc_ctl &= ~DPFC_CTL_EN; | |
295 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
296 | ||
0e631adc | 297 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
298 | } |
299 | } | |
300 | ||
0e631adc | 301 | static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 302 | { |
7ff0ebcc RV |
303 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
304 | } | |
305 | ||
0e631adc | 306 | static void gen7_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 307 | { |
220285f2 PZ |
308 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
309 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 310 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 311 | u32 dpfc_ctl; |
ce65e47b | 312 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc | 313 | |
0e631adc | 314 | dev_priv->fbc.active = true; |
7ff0ebcc | 315 | |
d8514d63 | 316 | dpfc_ctl = 0; |
7733b49b | 317 | if (IS_IVYBRIDGE(dev_priv)) |
220285f2 | 318 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
d8514d63 | 319 | |
7ff0ebcc | 320 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 321 | threshold++; |
7ff0ebcc | 322 | |
ce65e47b | 323 | switch (threshold) { |
7ff0ebcc RV |
324 | case 4: |
325 | case 3: | |
326 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
327 | break; | |
328 | case 2: | |
329 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
330 | break; | |
331 | case 1: | |
332 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
333 | break; | |
334 | } | |
335 | ||
336 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
337 | ||
338 | if (dev_priv->fbc.false_color) | |
339 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
340 | ||
7733b49b | 341 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
342 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
343 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
344 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
345 | ILK_FBCQ_DIS); | |
40f4022e | 346 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 347 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
220285f2 PZ |
348 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
349 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | | |
7ff0ebcc RV |
350 | HSW_FBCQ_DIS); |
351 | } | |
352 | ||
57012be9 PZ |
353 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
354 | ||
7ff0ebcc RV |
355 | I915_WRITE(SNB_DPFC_CTL_SA, |
356 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 357 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc | 358 | |
d5ce4164 | 359 | intel_fbc_recompress(dev_priv); |
7ff0ebcc | 360 | |
0e631adc | 361 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
362 | } |
363 | ||
94b83957 | 364 | /** |
0e631adc | 365 | * intel_fbc_is_active - Is FBC active? |
7733b49b | 366 | * @dev_priv: i915 device instance |
94b83957 RV |
367 | * |
368 | * This function is used to verify the current state of FBC. | |
369 | * FIXME: This should be tracked in the plane config eventually | |
370 | * instead of queried at runtime for most callers. | |
371 | */ | |
0e631adc | 372 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 373 | { |
0e631adc | 374 | return dev_priv->fbc.active; |
7ff0ebcc RV |
375 | } |
376 | ||
0e631adc | 377 | static void intel_fbc_activate(const struct drm_framebuffer *fb) |
e8cb8d69 | 378 | { |
e9c5fd26 PZ |
379 | struct drm_i915_private *dev_priv = fb->dev->dev_private; |
380 | struct intel_crtc *crtc = dev_priv->fbc.crtc; | |
e8cb8d69 | 381 | |
0e631adc | 382 | dev_priv->fbc.activate(crtc); |
e8cb8d69 | 383 | |
e8cb8d69 PZ |
384 | dev_priv->fbc.fb_id = fb->base.id; |
385 | dev_priv->fbc.y = crtc->base.y; | |
386 | } | |
387 | ||
7ff0ebcc RV |
388 | static void intel_fbc_work_fn(struct work_struct *__work) |
389 | { | |
390 | struct intel_fbc_work *work = | |
391 | container_of(to_delayed_work(__work), | |
392 | struct intel_fbc_work, work); | |
e9c5fd26 PZ |
393 | struct drm_i915_private *dev_priv = work->fb->dev->dev_private; |
394 | struct drm_framebuffer *crtc_fb = dev_priv->fbc.crtc->base.primary->fb; | |
7ff0ebcc | 395 | |
25ad93fd | 396 | mutex_lock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
397 | if (work == dev_priv->fbc.fbc_work) { |
398 | /* Double check that we haven't switched fb without cancelling | |
399 | * the prior work. | |
400 | */ | |
e8cb8d69 | 401 | if (crtc_fb == work->fb) |
0e631adc | 402 | intel_fbc_activate(work->fb); |
7ff0ebcc RV |
403 | |
404 | dev_priv->fbc.fbc_work = NULL; | |
405 | } | |
25ad93fd | 406 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
407 | |
408 | kfree(work); | |
409 | } | |
410 | ||
411 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
412 | { | |
25ad93fd PZ |
413 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
414 | ||
7ff0ebcc RV |
415 | if (dev_priv->fbc.fbc_work == NULL) |
416 | return; | |
417 | ||
7ff0ebcc RV |
418 | /* Synchronisation is provided by struct_mutex and checking of |
419 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
420 | * entirely asynchronously. | |
421 | */ | |
422 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
423 | /* tasklet was killed before being run, clean up */ | |
424 | kfree(dev_priv->fbc.fbc_work); | |
425 | ||
426 | /* Mark the work as no longer wanted so that if it does | |
427 | * wake-up (because the work was already running and waiting | |
428 | * for our mutex), it will discover that is no longer | |
429 | * necessary to run. | |
430 | */ | |
431 | dev_priv->fbc.fbc_work = NULL; | |
432 | } | |
433 | ||
0e631adc | 434 | static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
7ff0ebcc RV |
435 | { |
436 | struct intel_fbc_work *work; | |
220285f2 | 437 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 438 | |
25ad93fd PZ |
439 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
440 | ||
7ff0ebcc RV |
441 | intel_fbc_cancel_work(dev_priv); |
442 | ||
443 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
444 | if (work == NULL) { | |
445 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
0e631adc | 446 | intel_fbc_activate(crtc->base.primary->fb); |
7ff0ebcc RV |
447 | return; |
448 | } | |
449 | ||
220285f2 | 450 | work->fb = crtc->base.primary->fb; |
7ff0ebcc RV |
451 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
452 | ||
453 | dev_priv->fbc.fbc_work = work; | |
454 | ||
455 | /* Delay the actual enabling to let pageflipping cease and the | |
456 | * display to settle before starting the compression. Note that | |
457 | * this delay also serves a second purpose: it allows for a | |
458 | * vblank to pass after disabling the FBC before we attempt | |
459 | * to modify the control registers. | |
460 | * | |
461 | * A more complicated solution would involve tracking vblanks | |
462 | * following the termination of the page-flipping sequence | |
463 | * and indeed performing the enable as a co-routine and not | |
464 | * waiting synchronously upon the vblank. | |
465 | * | |
466 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
467 | */ | |
468 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
469 | } | |
470 | ||
d029bcad | 471 | static void __intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
25ad93fd | 472 | { |
25ad93fd PZ |
473 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
474 | ||
475 | intel_fbc_cancel_work(dev_priv); | |
476 | ||
0e631adc PZ |
477 | if (dev_priv->fbc.active) |
478 | dev_priv->fbc.deactivate(dev_priv); | |
754d1133 PZ |
479 | } |
480 | ||
25ad93fd | 481 | /* |
d029bcad | 482 | * intel_fbc_deactivate - deactivate FBC if it's associated with crtc |
25ad93fd PZ |
483 | * @crtc: the CRTC |
484 | * | |
d029bcad | 485 | * This function deactivates FBC if it's associated with the provided CRTC. |
25ad93fd | 486 | */ |
d029bcad | 487 | void intel_fbc_deactivate(struct intel_crtc *crtc) |
25ad93fd | 488 | { |
7733b49b | 489 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 490 | |
9f218336 | 491 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
492 | return; |
493 | ||
25ad93fd PZ |
494 | mutex_lock(&dev_priv->fbc.lock); |
495 | if (dev_priv->fbc.crtc == crtc) | |
d029bcad | 496 | __intel_fbc_deactivate(dev_priv); |
25ad93fd | 497 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
498 | } |
499 | ||
2e8144a5 | 500 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
bf6189c6 | 501 | const char *reason) |
7ff0ebcc RV |
502 | { |
503 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 504 | return; |
7ff0ebcc RV |
505 | |
506 | dev_priv->fbc.no_fbc_reason = reason; | |
bf6189c6 | 507 | DRM_DEBUG_KMS("Disabling FBC: %s\n", reason); |
7ff0ebcc RV |
508 | } |
509 | ||
d029bcad | 510 | static bool crtc_can_fbc(struct intel_crtc *crtc) |
30c58d58 PZ |
511 | { |
512 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
513 | ||
514 | if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) | |
515 | return false; | |
516 | ||
d029bcad PZ |
517 | return true; |
518 | } | |
519 | ||
520 | static bool crtc_is_valid(struct intel_crtc *crtc) | |
521 | { | |
30c58d58 PZ |
522 | if (!intel_crtc_active(&crtc->base)) |
523 | return false; | |
524 | ||
525 | if (!to_intel_plane_state(crtc->base.primary->state)->visible) | |
526 | return false; | |
527 | ||
528 | return true; | |
529 | } | |
530 | ||
232fd934 PZ |
531 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
532 | { | |
533 | enum pipe pipe; | |
534 | int n_pipes = 0; | |
535 | struct drm_crtc *crtc; | |
536 | ||
537 | if (INTEL_INFO(dev_priv)->gen > 4) | |
538 | return true; | |
539 | ||
540 | for_each_pipe(dev_priv, pipe) { | |
541 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
542 | ||
543 | if (intel_crtc_active(crtc) && | |
544 | to_intel_plane_state(crtc->primary->state)->visible) | |
545 | n_pipes++; | |
546 | } | |
547 | ||
548 | return (n_pipes < 2); | |
549 | } | |
550 | ||
7733b49b | 551 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
552 | struct drm_mm_node *node, |
553 | int size, | |
554 | int fb_cpp) | |
555 | { | |
fc786728 PZ |
556 | int compression_threshold = 1; |
557 | int ret; | |
a9da512b PZ |
558 | u64 end; |
559 | ||
560 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
561 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
562 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
563 | * underruns, even if that range is not reserved by the BIOS. */ | |
ef11bdb3 RV |
564 | if (IS_BROADWELL(dev_priv) || |
565 | IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
a9da512b PZ |
566 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
567 | else | |
568 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
569 | |
570 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
571 | * code changes, this code needs to change as well. | |
572 | * | |
573 | * The enable_fbc code will attempt to use one of our 2 compression | |
574 | * thresholds, therefore, in that case, we only have 1 resort. | |
575 | */ | |
576 | ||
577 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
578 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
579 | 4096, 0, end); | |
fc786728 PZ |
580 | if (ret == 0) |
581 | return compression_threshold; | |
582 | ||
583 | again: | |
584 | /* HW's ability to limit the CFB is 1:4 */ | |
585 | if (compression_threshold > 4 || | |
586 | (fb_cpp == 2 && compression_threshold == 2)) | |
587 | return 0; | |
588 | ||
a9da512b PZ |
589 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
590 | 4096, 0, end); | |
7733b49b | 591 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
592 | return 0; |
593 | } else if (ret) { | |
594 | compression_threshold <<= 1; | |
595 | goto again; | |
596 | } else { | |
597 | return compression_threshold; | |
598 | } | |
599 | } | |
600 | ||
c5ecd469 | 601 | static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) |
fc786728 | 602 | { |
c5ecd469 PZ |
603 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
604 | struct drm_framebuffer *fb = crtc->base.primary->state->fb; | |
fc786728 | 605 | struct drm_mm_node *uninitialized_var(compressed_llb); |
c5ecd469 PZ |
606 | int size, fb_cpp, ret; |
607 | ||
608 | WARN_ON(drm_mm_node_allocated(&dev_priv->fbc.compressed_fb)); | |
609 | ||
610 | size = intel_fbc_calculate_cfb_size(crtc, fb); | |
611 | fb_cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
fc786728 | 612 | |
7733b49b | 613 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
fc786728 PZ |
614 | size, fb_cpp); |
615 | if (!ret) | |
616 | goto err_llb; | |
617 | else if (ret > 1) { | |
618 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
619 | ||
620 | } | |
621 | ||
622 | dev_priv->fbc.threshold = ret; | |
623 | ||
624 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
625 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
7733b49b | 626 | else if (IS_GM45(dev_priv)) { |
fc786728 PZ |
627 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
628 | } else { | |
629 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
630 | if (!compressed_llb) | |
631 | goto err_fb; | |
632 | ||
633 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
634 | 4096, 4096); | |
635 | if (ret) | |
636 | goto err_fb; | |
637 | ||
638 | dev_priv->fbc.compressed_llb = compressed_llb; | |
639 | ||
640 | I915_WRITE(FBC_CFB_BASE, | |
641 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
642 | I915_WRITE(FBC_LL_BASE, | |
643 | dev_priv->mm.stolen_base + compressed_llb->start); | |
644 | } | |
645 | ||
646 | dev_priv->fbc.uncompressed_size = size; | |
647 | ||
b8bf5d7f PZ |
648 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
649 | dev_priv->fbc.compressed_fb.size, | |
650 | dev_priv->fbc.threshold); | |
fc786728 PZ |
651 | |
652 | return 0; | |
653 | ||
654 | err_fb: | |
655 | kfree(compressed_llb); | |
656 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
657 | err_llb: | |
658 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
659 | return -ENOSPC; | |
660 | } | |
661 | ||
7733b49b | 662 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 663 | { |
fc786728 PZ |
664 | if (dev_priv->fbc.uncompressed_size == 0) |
665 | return; | |
666 | ||
667 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
668 | ||
669 | if (dev_priv->fbc.compressed_llb) { | |
670 | i915_gem_stolen_remove_node(dev_priv, | |
671 | dev_priv->fbc.compressed_llb); | |
672 | kfree(dev_priv->fbc.compressed_llb); | |
673 | } | |
674 | ||
675 | dev_priv->fbc.uncompressed_size = 0; | |
676 | } | |
677 | ||
7733b49b | 678 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 679 | { |
9f218336 | 680 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
681 | return; |
682 | ||
25ad93fd | 683 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 684 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
685 | mutex_unlock(&dev_priv->fbc.lock); |
686 | } | |
687 | ||
adf70c65 PZ |
688 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
689 | unsigned int stride) | |
690 | { | |
691 | /* These should have been caught earlier. */ | |
692 | WARN_ON(stride < 512); | |
693 | WARN_ON((stride & (64 - 1)) != 0); | |
694 | ||
695 | /* Below are the additional FBC restrictions. */ | |
696 | ||
697 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
698 | return stride == 4096 || stride == 8192; | |
699 | ||
700 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
701 | return false; | |
702 | ||
703 | if (stride > 16384) | |
704 | return false; | |
705 | ||
706 | return true; | |
707 | } | |
708 | ||
b9e831dc PZ |
709 | static bool pixel_format_is_valid(struct drm_framebuffer *fb) |
710 | { | |
711 | struct drm_device *dev = fb->dev; | |
712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
713 | ||
714 | switch (fb->pixel_format) { | |
715 | case DRM_FORMAT_XRGB8888: | |
716 | case DRM_FORMAT_XBGR8888: | |
717 | return true; | |
718 | case DRM_FORMAT_XRGB1555: | |
719 | case DRM_FORMAT_RGB565: | |
720 | /* 16bpp not supported on gen2 */ | |
721 | if (IS_GEN2(dev)) | |
722 | return false; | |
723 | /* WaFbcOnly1to1Ratio:ctg */ | |
724 | if (IS_G4X(dev_priv)) | |
725 | return false; | |
726 | return true; | |
727 | default: | |
728 | return false; | |
729 | } | |
730 | } | |
731 | ||
856312ae PZ |
732 | /* |
733 | * For some reason, the hardware tracking starts looking at whatever we | |
734 | * programmed as the display plane base address register. It does not look at | |
735 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} | |
736 | * variables instead of just looking at the pipe/plane size. | |
737 | */ | |
738 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) | |
3c5f174e PZ |
739 | { |
740 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
856312ae | 741 | unsigned int effective_w, effective_h, max_w, max_h; |
3c5f174e PZ |
742 | |
743 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { | |
744 | max_w = 4096; | |
745 | max_h = 4096; | |
746 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { | |
747 | max_w = 4096; | |
748 | max_h = 2048; | |
749 | } else { | |
750 | max_w = 2048; | |
751 | max_h = 1536; | |
752 | } | |
753 | ||
856312ae PZ |
754 | intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h); |
755 | effective_w += crtc->adjusted_x; | |
756 | effective_h += crtc->adjusted_y; | |
757 | ||
758 | return effective_w <= max_w && effective_h <= max_h; | |
3c5f174e PZ |
759 | } |
760 | ||
7ff0ebcc | 761 | /** |
d029bcad | 762 | * __intel_fbc_update - activate/deactivate FBC as needed, unlocked |
754d1133 | 763 | * @crtc: the CRTC that triggered the update |
7ff0ebcc | 764 | * |
d029bcad PZ |
765 | * This function completely reevaluates the status of FBC, then activates, |
766 | * deactivates or maintains it on the same state. | |
7ff0ebcc | 767 | */ |
754d1133 | 768 | static void __intel_fbc_update(struct intel_crtc *crtc) |
7ff0ebcc | 769 | { |
754d1133 | 770 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc RV |
771 | struct drm_framebuffer *fb; |
772 | struct drm_i915_gem_object *obj; | |
773 | const struct drm_display_mode *adjusted_mode; | |
7ff0ebcc | 774 | |
25ad93fd PZ |
775 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
776 | ||
754d1133 PZ |
777 | if (!multiple_pipes_ok(dev_priv)) { |
778 | set_no_fbc_reason(dev_priv, "more than one pipe active"); | |
779 | goto out_disable; | |
780 | } | |
781 | ||
d029bcad | 782 | if (!dev_priv->fbc.enabled || dev_priv->fbc.crtc != crtc) |
754d1133 PZ |
783 | return; |
784 | ||
754d1133 | 785 | if (!crtc_is_valid(crtc)) { |
bf6189c6 | 786 | set_no_fbc_reason(dev_priv, "no output"); |
7ff0ebcc | 787 | goto out_disable; |
8df5dd57 | 788 | } |
7ff0ebcc | 789 | |
45b32a29 | 790 | fb = crtc->base.primary->fb; |
7ff0ebcc | 791 | obj = intel_fb_obj(fb); |
45b32a29 | 792 | adjusted_mode = &crtc->config->base.adjusted_mode; |
7ff0ebcc | 793 | |
7ff0ebcc RV |
794 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
795 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
bf6189c6 | 796 | set_no_fbc_reason(dev_priv, "incompatible mode"); |
7ff0ebcc RV |
797 | goto out_disable; |
798 | } | |
799 | ||
45b32a29 | 800 | if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
bf6189c6 | 801 | set_no_fbc_reason(dev_priv, "mode too large for compression"); |
7ff0ebcc RV |
802 | goto out_disable; |
803 | } | |
3c5f174e | 804 | |
7733b49b | 805 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
45b32a29 | 806 | crtc->plane != PLANE_A) { |
bf6189c6 | 807 | set_no_fbc_reason(dev_priv, "FBC unsupported on plane"); |
7ff0ebcc RV |
808 | goto out_disable; |
809 | } | |
810 | ||
811 | /* The use of a CPU fence is mandatory in order to detect writes | |
812 | * by the CPU to the scanout and trigger updates to the FBC. | |
813 | */ | |
814 | if (obj->tiling_mode != I915_TILING_X || | |
815 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
bf6189c6 | 816 | set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
7ff0ebcc RV |
817 | goto out_disable; |
818 | } | |
7733b49b | 819 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
45b32a29 | 820 | crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) { |
bf6189c6 | 821 | set_no_fbc_reason(dev_priv, "rotation unsupported"); |
7ff0ebcc RV |
822 | goto out_disable; |
823 | } | |
824 | ||
adf70c65 | 825 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
bf6189c6 | 826 | set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
adf70c65 PZ |
827 | goto out_disable; |
828 | } | |
829 | ||
b9e831dc | 830 | if (!pixel_format_is_valid(fb)) { |
bf6189c6 | 831 | set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
b9e831dc PZ |
832 | goto out_disable; |
833 | } | |
834 | ||
7b24c9a6 PZ |
835 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
836 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
45b32a29 | 837 | ilk_pipe_pixel_rate(crtc->config) >= |
7b24c9a6 | 838 | dev_priv->cdclk_freq * 95 / 100) { |
bf6189c6 | 839 | set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
7b24c9a6 PZ |
840 | goto out_disable; |
841 | } | |
842 | ||
c5ecd469 PZ |
843 | /* It is possible for the required CFB size change without a |
844 | * crtc->disable + crtc->enable since it is possible to change the | |
845 | * stride without triggering a full modeset. Since we try to | |
846 | * over-allocate the CFB, there's a chance we may keep FBC enabled even | |
847 | * if this happens, but if we exceed the current CFB size we'll have to | |
848 | * disable FBC. Notice that it would be possible to disable FBC, wait | |
849 | * for a frame, free the stolen node, then try to reenable FBC in case | |
850 | * we didn't get any invalidate/deactivate calls, but this would require | |
851 | * a lot of tracking just for a specific case. If we conclude it's an | |
852 | * important case, we can implement it later. */ | |
853 | if (intel_fbc_calculate_cfb_size(crtc, fb) > | |
854 | dev_priv->fbc.compressed_fb.size * dev_priv->fbc.threshold) { | |
855 | set_no_fbc_reason(dev_priv, "CFB requirements changed"); | |
7ff0ebcc RV |
856 | goto out_disable; |
857 | } | |
858 | ||
859 | /* If the scanout has not changed, don't modify the FBC settings. | |
860 | * Note that we make the fundamental assumption that the fb->obj | |
861 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
862 | * without first being decoupled from the scanout and FBC disabled. | |
863 | */ | |
45b32a29 | 864 | if (dev_priv->fbc.crtc == crtc && |
7ff0ebcc | 865 | dev_priv->fbc.fb_id == fb->base.id && |
754d1133 | 866 | dev_priv->fbc.y == crtc->base.y && |
0e631adc | 867 | dev_priv->fbc.active) |
7ff0ebcc RV |
868 | return; |
869 | ||
0e631adc | 870 | if (intel_fbc_is_active(dev_priv)) { |
7ff0ebcc RV |
871 | /* We update FBC along two paths, after changing fb/crtc |
872 | * configuration (modeswitching) and after page-flipping | |
873 | * finishes. For the latter, we know that not only did | |
874 | * we disable the FBC at the start of the page-flip | |
875 | * sequence, but also more than one vblank has passed. | |
876 | * | |
877 | * For the former case of modeswitching, it is possible | |
878 | * to switch between two FBC valid configurations | |
879 | * instantaneously so we do need to disable the FBC | |
880 | * before we can modify its control registers. We also | |
881 | * have to wait for the next vblank for that to take | |
882 | * effect. However, since we delay enabling FBC we can | |
883 | * assume that a vblank has passed since disabling and | |
884 | * that we can safely alter the registers in the deferred | |
885 | * callback. | |
886 | * | |
887 | * In the scenario that we go from a valid to invalid | |
888 | * and then back to valid FBC configuration we have | |
889 | * no strict enforcement that a vblank occurred since | |
890 | * disabling the FBC. However, along all current pipe | |
891 | * disabling paths we do need to wait for a vblank at | |
892 | * some point. And we wait before enabling FBC anyway. | |
893 | */ | |
d029bcad PZ |
894 | DRM_DEBUG_KMS("deactivating FBC for update\n"); |
895 | __intel_fbc_deactivate(dev_priv); | |
7ff0ebcc RV |
896 | } |
897 | ||
0e631adc | 898 | intel_fbc_schedule_activation(crtc); |
793af070 | 899 | dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)"; |
7ff0ebcc RV |
900 | return; |
901 | ||
902 | out_disable: | |
903 | /* Multiple disables should be harmless */ | |
0e631adc | 904 | if (intel_fbc_is_active(dev_priv)) { |
d029bcad PZ |
905 | DRM_DEBUG_KMS("unsupported config, deactivating FBC\n"); |
906 | __intel_fbc_deactivate(dev_priv); | |
7ff0ebcc | 907 | } |
25ad93fd PZ |
908 | } |
909 | ||
910 | /* | |
d029bcad | 911 | * intel_fbc_update - activate/deactivate FBC as needed |
754d1133 | 912 | * @crtc: the CRTC that triggered the update |
25ad93fd | 913 | * |
d029bcad | 914 | * This function reevaluates the overall state and activates or deactivates FBC. |
25ad93fd | 915 | */ |
754d1133 | 916 | void intel_fbc_update(struct intel_crtc *crtc) |
25ad93fd | 917 | { |
754d1133 PZ |
918 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
919 | ||
9f218336 | 920 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
921 | return; |
922 | ||
25ad93fd | 923 | mutex_lock(&dev_priv->fbc.lock); |
754d1133 | 924 | __intel_fbc_update(crtc); |
25ad93fd | 925 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
926 | } |
927 | ||
dbef0f15 PZ |
928 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
929 | unsigned int frontbuffer_bits, | |
930 | enum fb_op_origin origin) | |
931 | { | |
dbef0f15 PZ |
932 | unsigned int fbc_bits; |
933 | ||
9f218336 | 934 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
935 | return; |
936 | ||
dbef0f15 PZ |
937 | if (origin == ORIGIN_GTT) |
938 | return; | |
939 | ||
25ad93fd PZ |
940 | mutex_lock(&dev_priv->fbc.lock); |
941 | ||
d029bcad | 942 | if (dev_priv->fbc.enabled) |
dbef0f15 | 943 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
dbef0f15 PZ |
944 | else |
945 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
946 | ||
947 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
948 | ||
949 | if (dev_priv->fbc.busy_bits) | |
d029bcad | 950 | __intel_fbc_deactivate(dev_priv); |
25ad93fd PZ |
951 | |
952 | mutex_unlock(&dev_priv->fbc.lock); | |
dbef0f15 PZ |
953 | } |
954 | ||
955 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 956 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 957 | { |
9f218336 | 958 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
959 | return; |
960 | ||
6f4551fe PZ |
961 | if (origin == ORIGIN_GTT) |
962 | return; | |
25ad93fd | 963 | |
6f4551fe | 964 | mutex_lock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
965 | |
966 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
967 | ||
d029bcad PZ |
968 | if (!dev_priv->fbc.busy_bits && dev_priv->fbc.enabled) { |
969 | __intel_fbc_deactivate(dev_priv); | |
754d1133 | 970 | __intel_fbc_update(dev_priv->fbc.crtc); |
6f4551fe | 971 | } |
25ad93fd | 972 | |
25ad93fd | 973 | mutex_unlock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
974 | } |
975 | ||
d029bcad PZ |
976 | /** |
977 | * intel_fbc_enable: tries to enable FBC on the CRTC | |
978 | * @crtc: the CRTC | |
979 | * | |
980 | * This function checks if it's possible to enable FBC on the following CRTC, | |
981 | * then enables it. Notice that it doesn't activate FBC. | |
982 | */ | |
983 | void intel_fbc_enable(struct intel_crtc *crtc) | |
984 | { | |
985 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
986 | ||
987 | if (!fbc_supported(dev_priv)) | |
988 | return; | |
989 | ||
990 | mutex_lock(&dev_priv->fbc.lock); | |
991 | ||
992 | if (dev_priv->fbc.enabled) { | |
993 | WARN_ON(dev_priv->fbc.crtc == crtc); | |
994 | goto out; | |
995 | } | |
996 | ||
997 | WARN_ON(dev_priv->fbc.active); | |
998 | WARN_ON(dev_priv->fbc.crtc != NULL); | |
999 | ||
1000 | if (intel_vgpu_active(dev_priv->dev)) { | |
1001 | set_no_fbc_reason(dev_priv, "VGPU is active"); | |
1002 | goto out; | |
1003 | } | |
1004 | ||
1005 | if (i915.enable_fbc < 0) { | |
1006 | set_no_fbc_reason(dev_priv, "disabled per chip default"); | |
1007 | goto out; | |
1008 | } | |
1009 | ||
1010 | if (!i915.enable_fbc) { | |
1011 | set_no_fbc_reason(dev_priv, "disabled per module param"); | |
1012 | goto out; | |
1013 | } | |
1014 | ||
1015 | if (!crtc_can_fbc(crtc)) { | |
1016 | set_no_fbc_reason(dev_priv, "no enabled pipes can have FBC"); | |
1017 | goto out; | |
1018 | } | |
1019 | ||
c5ecd469 PZ |
1020 | if (intel_fbc_alloc_cfb(crtc)) { |
1021 | set_no_fbc_reason(dev_priv, "not enough stolen memory"); | |
1022 | goto out; | |
1023 | } | |
1024 | ||
d029bcad PZ |
1025 | DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
1026 | dev_priv->fbc.no_fbc_reason = "FBC enabled but not active yet\n"; | |
1027 | ||
1028 | dev_priv->fbc.enabled = true; | |
1029 | dev_priv->fbc.crtc = crtc; | |
1030 | out: | |
1031 | mutex_unlock(&dev_priv->fbc.lock); | |
1032 | } | |
1033 | ||
1034 | /** | |
1035 | * __intel_fbc_disable - disable FBC | |
1036 | * @dev_priv: i915 device instance | |
1037 | * | |
1038 | * This is the low level function that actually disables FBC. Callers should | |
1039 | * grab the FBC lock. | |
1040 | */ | |
1041 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1042 | { | |
1043 | struct intel_crtc *crtc = dev_priv->fbc.crtc; | |
1044 | ||
1045 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); | |
1046 | WARN_ON(!dev_priv->fbc.enabled); | |
1047 | WARN_ON(dev_priv->fbc.active); | |
1048 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1049 | ||
1050 | DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); | |
1051 | ||
c5ecd469 PZ |
1052 | __intel_fbc_cleanup_cfb(dev_priv); |
1053 | ||
d029bcad PZ |
1054 | dev_priv->fbc.enabled = false; |
1055 | dev_priv->fbc.crtc = NULL; | |
1056 | } | |
1057 | ||
1058 | /** | |
1059 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
1060 | * @crtc: the CRTC | |
1061 | * | |
1062 | * This function disables FBC if it's associated with the provided CRTC. | |
1063 | */ | |
1064 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
1065 | { | |
1066 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1067 | ||
1068 | if (!fbc_supported(dev_priv)) | |
1069 | return; | |
1070 | ||
1071 | mutex_lock(&dev_priv->fbc.lock); | |
1072 | if (dev_priv->fbc.crtc == crtc) { | |
1073 | WARN_ON(!dev_priv->fbc.enabled); | |
1074 | WARN_ON(dev_priv->fbc.active); | |
1075 | __intel_fbc_disable(dev_priv); | |
1076 | } | |
1077 | mutex_unlock(&dev_priv->fbc.lock); | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * intel_fbc_disable - globally disable FBC | |
1082 | * @dev_priv: i915 device instance | |
1083 | * | |
1084 | * This function disables FBC regardless of which CRTC is associated with it. | |
1085 | */ | |
1086 | void intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1087 | { | |
1088 | if (!fbc_supported(dev_priv)) | |
1089 | return; | |
1090 | ||
1091 | mutex_lock(&dev_priv->fbc.lock); | |
1092 | if (dev_priv->fbc.enabled) | |
1093 | __intel_fbc_disable(dev_priv); | |
1094 | mutex_unlock(&dev_priv->fbc.lock); | |
1095 | } | |
1096 | ||
94b83957 RV |
1097 | /** |
1098 | * intel_fbc_init - Initialize FBC | |
1099 | * @dev_priv: the i915 device | |
1100 | * | |
1101 | * This function might be called during PM init process. | |
1102 | */ | |
7ff0ebcc RV |
1103 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1104 | { | |
dbef0f15 PZ |
1105 | enum pipe pipe; |
1106 | ||
25ad93fd | 1107 | mutex_init(&dev_priv->fbc.lock); |
d029bcad | 1108 | dev_priv->fbc.enabled = false; |
0e631adc | 1109 | dev_priv->fbc.active = false; |
25ad93fd | 1110 | |
7ff0ebcc | 1111 | if (!HAS_FBC(dev_priv)) { |
bf6189c6 | 1112 | dev_priv->fbc.no_fbc_reason = "unsupported by this chipset"; |
7ff0ebcc RV |
1113 | return; |
1114 | } | |
1115 | ||
dbef0f15 PZ |
1116 | for_each_pipe(dev_priv, pipe) { |
1117 | dev_priv->fbc.possible_framebuffer_bits |= | |
1118 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
1119 | ||
57105022 | 1120 | if (fbc_on_pipe_a_only(dev_priv)) |
dbef0f15 PZ |
1121 | break; |
1122 | } | |
1123 | ||
7ff0ebcc | 1124 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
0e631adc PZ |
1125 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1126 | dev_priv->fbc.activate = gen7_fbc_activate; | |
1127 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1128 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
0e631adc PZ |
1129 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1130 | dev_priv->fbc.activate = ilk_fbc_activate; | |
1131 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1132 | } else if (IS_GM45(dev_priv)) { |
0e631adc PZ |
1133 | dev_priv->fbc.is_active = g4x_fbc_is_active; |
1134 | dev_priv->fbc.activate = g4x_fbc_activate; | |
1135 | dev_priv->fbc.deactivate = g4x_fbc_deactivate; | |
7ff0ebcc | 1136 | } else { |
0e631adc PZ |
1137 | dev_priv->fbc.is_active = i8xx_fbc_is_active; |
1138 | dev_priv->fbc.activate = i8xx_fbc_activate; | |
1139 | dev_priv->fbc.deactivate = i8xx_fbc_deactivate; | |
7ff0ebcc RV |
1140 | |
1141 | /* This value was pulled out of someone's hat */ | |
1142 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1143 | } | |
1144 | ||
b07ea0fa | 1145 | /* We still don't have any sort of hardware state readout for FBC, so |
0e631adc PZ |
1146 | * deactivate it in case the BIOS activated it to make sure software |
1147 | * matches the hardware state. */ | |
1148 | if (dev_priv->fbc.is_active(dev_priv)) | |
1149 | dev_priv->fbc.deactivate(dev_priv); | |
7ff0ebcc | 1150 | } |