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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
7ff0ebcc RV |
44 | static void i8xx_fbc_disable(struct drm_device *dev) |
45 | { | |
46 | struct drm_i915_private *dev_priv = dev->dev_private; | |
47 | u32 fbc_ctl; | |
48 | ||
49 | dev_priv->fbc.enabled = false; | |
50 | ||
51 | /* Disable compression */ | |
52 | fbc_ctl = I915_READ(FBC_CONTROL); | |
53 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
54 | return; | |
55 | ||
56 | fbc_ctl &= ~FBC_CTL_EN; | |
57 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
58 | ||
59 | /* Wait for compressing bit to clear */ | |
60 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
61 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
62 | return; | |
63 | } | |
64 | ||
65 | DRM_DEBUG_KMS("disabled FBC\n"); | |
66 | } | |
67 | ||
68 | static void i8xx_fbc_enable(struct drm_crtc *crtc) | |
69 | { | |
70 | struct drm_device *dev = crtc->dev; | |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
72 | struct drm_framebuffer *fb = crtc->primary->fb; | |
73 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
74 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
75 | int cfb_pitch; | |
76 | int i; | |
77 | u32 fbc_ctl; | |
78 | ||
79 | dev_priv->fbc.enabled = true; | |
80 | ||
60ee5cd2 JN |
81 | /* Note: fbc.threshold == 1 for i8xx */ |
82 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
83 | if (fb->pitches[0] < cfb_pitch) |
84 | cfb_pitch = fb->pitches[0]; | |
85 | ||
86 | /* FBC_CTL wants 32B or 64B units */ | |
87 | if (IS_GEN2(dev)) | |
88 | cfb_pitch = (cfb_pitch / 32) - 1; | |
89 | else | |
90 | cfb_pitch = (cfb_pitch / 64) - 1; | |
91 | ||
92 | /* Clear old tags */ | |
93 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
94 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
95 | ||
96 | if (IS_GEN4(dev)) { | |
97 | u32 fbc_ctl2; | |
98 | ||
99 | /* Set it up... */ | |
100 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
101 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); | |
102 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
103 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
104 | } | |
105 | ||
106 | /* enable it... */ | |
107 | fbc_ctl = I915_READ(FBC_CONTROL); | |
108 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
109 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
110 | if (IS_I945GM(dev)) | |
111 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
112 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
113 | fbc_ctl |= obj->fence_reg; | |
114 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
115 | ||
116 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", | |
117 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); | |
118 | } | |
119 | ||
120 | static bool i8xx_fbc_enabled(struct drm_device *dev) | |
121 | { | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | ||
124 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
125 | } | |
126 | ||
127 | static void g4x_fbc_enable(struct drm_crtc *crtc) | |
128 | { | |
129 | struct drm_device *dev = crtc->dev; | |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | struct drm_framebuffer *fb = crtc->primary->fb; | |
132 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
134 | u32 dpfc_ctl; | |
135 | ||
136 | dev_priv->fbc.enabled = true; | |
137 | ||
138 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; | |
139 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
140 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
141 | else | |
142 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
143 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
144 | ||
145 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
146 | ||
147 | /* enable it... */ | |
148 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
149 | ||
150 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); | |
151 | } | |
152 | ||
153 | static void g4x_fbc_disable(struct drm_device *dev) | |
154 | { | |
155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
156 | u32 dpfc_ctl; | |
157 | ||
158 | dev_priv->fbc.enabled = false; | |
159 | ||
160 | /* Disable compression */ | |
161 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
162 | if (dpfc_ctl & DPFC_CTL_EN) { | |
163 | dpfc_ctl &= ~DPFC_CTL_EN; | |
164 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
165 | ||
166 | DRM_DEBUG_KMS("disabled FBC\n"); | |
167 | } | |
168 | } | |
169 | ||
170 | static bool g4x_fbc_enabled(struct drm_device *dev) | |
171 | { | |
172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
173 | ||
174 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
175 | } | |
176 | ||
dbef0f15 | 177 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
7ff0ebcc | 178 | { |
dbef0f15 PZ |
179 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
180 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
181 | } |
182 | ||
183 | static void ilk_fbc_enable(struct drm_crtc *crtc) | |
184 | { | |
185 | struct drm_device *dev = crtc->dev; | |
186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
187 | struct drm_framebuffer *fb = crtc->primary->fb; | |
188 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
190 | u32 dpfc_ctl; | |
191 | ||
192 | dev_priv->fbc.enabled = true; | |
193 | ||
194 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); | |
195 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
196 | dev_priv->fbc.threshold++; | |
197 | ||
198 | switch (dev_priv->fbc.threshold) { | |
199 | case 4: | |
200 | case 3: | |
201 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
202 | break; | |
203 | case 2: | |
204 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
205 | break; | |
206 | case 1: | |
207 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
208 | break; | |
209 | } | |
210 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
211 | if (IS_GEN5(dev)) | |
212 | dpfc_ctl |= obj->fence_reg; | |
213 | ||
214 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
215 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); | |
216 | /* enable it... */ | |
217 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
218 | ||
219 | if (IS_GEN6(dev)) { | |
220 | I915_WRITE(SNB_DPFC_CTL_SA, | |
221 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
222 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
7ff0ebcc RV |
223 | } |
224 | ||
dbef0f15 PZ |
225 | intel_fbc_nuke(dev_priv); |
226 | ||
7ff0ebcc RV |
227 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
228 | } | |
229 | ||
230 | static void ilk_fbc_disable(struct drm_device *dev) | |
231 | { | |
232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
233 | u32 dpfc_ctl; | |
234 | ||
235 | dev_priv->fbc.enabled = false; | |
236 | ||
237 | /* Disable compression */ | |
238 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
239 | if (dpfc_ctl & DPFC_CTL_EN) { | |
240 | dpfc_ctl &= ~DPFC_CTL_EN; | |
241 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
242 | ||
243 | DRM_DEBUG_KMS("disabled FBC\n"); | |
244 | } | |
245 | } | |
246 | ||
247 | static bool ilk_fbc_enabled(struct drm_device *dev) | |
248 | { | |
249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
250 | ||
251 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
252 | } | |
253 | ||
254 | static void gen7_fbc_enable(struct drm_crtc *crtc) | |
255 | { | |
256 | struct drm_device *dev = crtc->dev; | |
257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
258 | struct drm_framebuffer *fb = crtc->primary->fb; | |
259 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
261 | u32 dpfc_ctl; | |
262 | ||
263 | dev_priv->fbc.enabled = true; | |
264 | ||
265 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); | |
266 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
267 | dev_priv->fbc.threshold++; | |
268 | ||
269 | switch (dev_priv->fbc.threshold) { | |
270 | case 4: | |
271 | case 3: | |
272 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
273 | break; | |
274 | case 2: | |
275 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
276 | break; | |
277 | case 1: | |
278 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
279 | break; | |
280 | } | |
281 | ||
282 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
283 | ||
284 | if (dev_priv->fbc.false_color) | |
285 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
286 | ||
287 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
288 | ||
289 | if (IS_IVYBRIDGE(dev)) { | |
290 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ | |
291 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
292 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
293 | ILK_FBCQ_DIS); | |
294 | } else { | |
295 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ | |
296 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), | |
297 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | | |
298 | HSW_FBCQ_DIS); | |
299 | } | |
300 | ||
301 | I915_WRITE(SNB_DPFC_CTL_SA, | |
302 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
303 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
304 | ||
dbef0f15 | 305 | intel_fbc_nuke(dev_priv); |
7ff0ebcc RV |
306 | |
307 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); | |
308 | } | |
309 | ||
94b83957 RV |
310 | /** |
311 | * intel_fbc_enabled - Is FBC enabled? | |
312 | * @dev: the drm_device | |
313 | * | |
314 | * This function is used to verify the current state of FBC. | |
315 | * FIXME: This should be tracked in the plane config eventually | |
316 | * instead of queried at runtime for most callers. | |
317 | */ | |
7ff0ebcc RV |
318 | bool intel_fbc_enabled(struct drm_device *dev) |
319 | { | |
320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
321 | ||
322 | return dev_priv->fbc.enabled; | |
323 | } | |
324 | ||
7ff0ebcc RV |
325 | static void intel_fbc_work_fn(struct work_struct *__work) |
326 | { | |
327 | struct intel_fbc_work *work = | |
328 | container_of(to_delayed_work(__work), | |
329 | struct intel_fbc_work, work); | |
330 | struct drm_device *dev = work->crtc->dev; | |
331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
332 | ||
333 | mutex_lock(&dev->struct_mutex); | |
334 | if (work == dev_priv->fbc.fbc_work) { | |
335 | /* Double check that we haven't switched fb without cancelling | |
336 | * the prior work. | |
337 | */ | |
338 | if (work->crtc->primary->fb == work->fb) { | |
339 | dev_priv->display.enable_fbc(work->crtc); | |
340 | ||
e35fef21 | 341 | dev_priv->fbc.crtc = to_intel_crtc(work->crtc); |
7ff0ebcc RV |
342 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
343 | dev_priv->fbc.y = work->crtc->y; | |
344 | } | |
345 | ||
346 | dev_priv->fbc.fbc_work = NULL; | |
347 | } | |
348 | mutex_unlock(&dev->struct_mutex); | |
349 | ||
350 | kfree(work); | |
351 | } | |
352 | ||
353 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
354 | { | |
355 | if (dev_priv->fbc.fbc_work == NULL) | |
356 | return; | |
357 | ||
358 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
359 | ||
360 | /* Synchronisation is provided by struct_mutex and checking of | |
361 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
362 | * entirely asynchronously. | |
363 | */ | |
364 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
365 | /* tasklet was killed before being run, clean up */ | |
366 | kfree(dev_priv->fbc.fbc_work); | |
367 | ||
368 | /* Mark the work as no longer wanted so that if it does | |
369 | * wake-up (because the work was already running and waiting | |
370 | * for our mutex), it will discover that is no longer | |
371 | * necessary to run. | |
372 | */ | |
373 | dev_priv->fbc.fbc_work = NULL; | |
374 | } | |
375 | ||
376 | static void intel_fbc_enable(struct drm_crtc *crtc) | |
377 | { | |
378 | struct intel_fbc_work *work; | |
379 | struct drm_device *dev = crtc->dev; | |
380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
381 | ||
382 | if (!dev_priv->display.enable_fbc) | |
383 | return; | |
384 | ||
385 | intel_fbc_cancel_work(dev_priv); | |
386 | ||
387 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
388 | if (work == NULL) { | |
389 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
390 | dev_priv->display.enable_fbc(crtc); | |
391 | return; | |
392 | } | |
393 | ||
394 | work->crtc = crtc; | |
395 | work->fb = crtc->primary->fb; | |
396 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
397 | ||
398 | dev_priv->fbc.fbc_work = work; | |
399 | ||
400 | /* Delay the actual enabling to let pageflipping cease and the | |
401 | * display to settle before starting the compression. Note that | |
402 | * this delay also serves a second purpose: it allows for a | |
403 | * vblank to pass after disabling the FBC before we attempt | |
404 | * to modify the control registers. | |
405 | * | |
406 | * A more complicated solution would involve tracking vblanks | |
407 | * following the termination of the page-flipping sequence | |
408 | * and indeed performing the enable as a co-routine and not | |
409 | * waiting synchronously upon the vblank. | |
410 | * | |
411 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
412 | */ | |
413 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
414 | } | |
415 | ||
94b83957 RV |
416 | /** |
417 | * intel_fbc_disable - disable FBC | |
418 | * @dev: the drm_device | |
419 | * | |
420 | * This function disables FBC. | |
421 | */ | |
7ff0ebcc RV |
422 | void intel_fbc_disable(struct drm_device *dev) |
423 | { | |
424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425 | ||
426 | intel_fbc_cancel_work(dev_priv); | |
427 | ||
428 | if (!dev_priv->display.disable_fbc) | |
429 | return; | |
430 | ||
431 | dev_priv->display.disable_fbc(dev); | |
e35fef21 | 432 | dev_priv->fbc.crtc = NULL; |
7ff0ebcc RV |
433 | } |
434 | ||
435 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, | |
436 | enum no_fbc_reason reason) | |
437 | { | |
438 | if (dev_priv->fbc.no_fbc_reason == reason) | |
439 | return false; | |
440 | ||
441 | dev_priv->fbc.no_fbc_reason = reason; | |
442 | return true; | |
443 | } | |
444 | ||
95106753 PZ |
445 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
446 | { | |
95106753 | 447 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
68b92147 | 448 | enum pipe pipe; |
e489e38e | 449 | bool pipe_a_only = false, one_pipe_only = false; |
68b92147 PZ |
450 | |
451 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
452 | pipe_a_only = true; | |
e489e38e PZ |
453 | else if (INTEL_INFO(dev_priv)->gen <= 4) |
454 | one_pipe_only = true; | |
68b92147 PZ |
455 | |
456 | for_each_pipe(dev_priv, pipe) { | |
457 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
95106753 | 458 | |
95106753 | 459 | if (intel_crtc_active(tmp_crtc) && |
b70709a6 | 460 | to_intel_plane_state(tmp_crtc->primary->state)->visible) { |
e489e38e | 461 | if (one_pipe_only && crtc) { |
95106753 PZ |
462 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
463 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
464 | return NULL; | |
465 | } | |
466 | crtc = tmp_crtc; | |
467 | } | |
68b92147 PZ |
468 | |
469 | if (pipe_a_only) | |
470 | break; | |
95106753 PZ |
471 | } |
472 | ||
473 | if (!crtc || crtc->primary->fb == NULL) { | |
474 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) | |
475 | DRM_DEBUG_KMS("no output, disabling\n"); | |
476 | return NULL; | |
477 | } | |
478 | ||
479 | return crtc; | |
480 | } | |
481 | ||
7ff0ebcc RV |
482 | /** |
483 | * intel_fbc_update - enable/disable FBC as needed | |
484 | * @dev: the drm_device | |
485 | * | |
486 | * Set up the framebuffer compression hardware at mode set time. We | |
487 | * enable it if possible: | |
488 | * - plane A only (on pre-965) | |
489 | * - no pixel mulitply/line duplication | |
490 | * - no alpha buffer discard | |
491 | * - no dual wide | |
492 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height | |
493 | * | |
494 | * We can't assume that any compression will take place (worst case), | |
495 | * so the compressed buffer has to be the same size as the uncompressed | |
496 | * one. It also must reside (along with the line length buffer) in | |
497 | * stolen memory. | |
498 | * | |
499 | * We need to enable/disable FBC on a global basis. | |
500 | */ | |
501 | void intel_fbc_update(struct drm_device *dev) | |
502 | { | |
503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
95106753 | 504 | struct drm_crtc *crtc = NULL; |
7ff0ebcc RV |
505 | struct intel_crtc *intel_crtc; |
506 | struct drm_framebuffer *fb; | |
507 | struct drm_i915_gem_object *obj; | |
508 | const struct drm_display_mode *adjusted_mode; | |
509 | unsigned int max_width, max_height; | |
510 | ||
104618b3 | 511 | if (!HAS_FBC(dev)) |
7ff0ebcc | 512 | return; |
7ff0ebcc | 513 | |
bd49234b YZ |
514 | /* disable framebuffer compression in vGPU */ |
515 | if (intel_vgpu_active(dev)) | |
516 | i915.enable_fbc = 0; | |
517 | ||
7cc65746 PZ |
518 | if (i915.enable_fbc < 0) { |
519 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) | |
520 | DRM_DEBUG_KMS("disabled per chip default\n"); | |
521 | goto out_disable; | |
522 | } | |
523 | ||
ab585dea | 524 | if (!i915.enable_fbc) { |
7ff0ebcc RV |
525 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
526 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
7cc65746 | 527 | goto out_disable; |
7ff0ebcc RV |
528 | } |
529 | ||
530 | /* | |
531 | * If FBC is already on, we just have to verify that we can | |
532 | * keep it that way... | |
533 | * Need to disable if: | |
534 | * - more than one pipe is active | |
535 | * - changing FBC params (stride, fence, mode) | |
536 | * - new fb is too large to fit in compressed buffer | |
537 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
538 | */ | |
95106753 PZ |
539 | crtc = intel_fbc_find_crtc(dev_priv); |
540 | if (!crtc) | |
7ff0ebcc | 541 | goto out_disable; |
7ff0ebcc RV |
542 | |
543 | intel_crtc = to_intel_crtc(crtc); | |
544 | fb = crtc->primary->fb; | |
545 | obj = intel_fb_obj(fb); | |
6e3c9717 | 546 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
7ff0ebcc | 547 | |
7ff0ebcc RV |
548 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
549 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
550 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) | |
551 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
552 | "disabling\n"); | |
553 | goto out_disable; | |
554 | } | |
555 | ||
556 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { | |
557 | max_width = 4096; | |
558 | max_height = 4096; | |
559 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
560 | max_width = 4096; | |
561 | max_height = 2048; | |
562 | } else { | |
563 | max_width = 2048; | |
564 | max_height = 1536; | |
565 | } | |
6e3c9717 ACO |
566 | if (intel_crtc->config->pipe_src_w > max_width || |
567 | intel_crtc->config->pipe_src_h > max_height) { | |
7ff0ebcc RV |
568 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
569 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
570 | goto out_disable; | |
571 | } | |
572 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && | |
573 | intel_crtc->plane != PLANE_A) { | |
574 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) | |
575 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); | |
576 | goto out_disable; | |
577 | } | |
578 | ||
579 | /* The use of a CPU fence is mandatory in order to detect writes | |
580 | * by the CPU to the scanout and trigger updates to the FBC. | |
581 | */ | |
582 | if (obj->tiling_mode != I915_TILING_X || | |
583 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
584 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) | |
585 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
586 | goto out_disable; | |
587 | } | |
588 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
8e7d688b | 589 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
7ff0ebcc RV |
590 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
591 | DRM_DEBUG_KMS("Rotation unsupported, disabling\n"); | |
592 | goto out_disable; | |
593 | } | |
594 | ||
595 | /* If the kernel debugger is active, always disable compression */ | |
596 | if (in_dbg_master()) | |
597 | goto out_disable; | |
598 | ||
599 | if (i915_gem_stolen_setup_compression(dev, obj->base.size, | |
600 | drm_format_plane_cpp(fb->pixel_format, 0))) { | |
601 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) | |
602 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); | |
603 | goto out_disable; | |
604 | } | |
605 | ||
606 | /* If the scanout has not changed, don't modify the FBC settings. | |
607 | * Note that we make the fundamental assumption that the fb->obj | |
608 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
609 | * without first being decoupled from the scanout and FBC disabled. | |
610 | */ | |
e35fef21 | 611 | if (dev_priv->fbc.crtc == intel_crtc && |
7ff0ebcc RV |
612 | dev_priv->fbc.fb_id == fb->base.id && |
613 | dev_priv->fbc.y == crtc->y) | |
614 | return; | |
615 | ||
616 | if (intel_fbc_enabled(dev)) { | |
617 | /* We update FBC along two paths, after changing fb/crtc | |
618 | * configuration (modeswitching) and after page-flipping | |
619 | * finishes. For the latter, we know that not only did | |
620 | * we disable the FBC at the start of the page-flip | |
621 | * sequence, but also more than one vblank has passed. | |
622 | * | |
623 | * For the former case of modeswitching, it is possible | |
624 | * to switch between two FBC valid configurations | |
625 | * instantaneously so we do need to disable the FBC | |
626 | * before we can modify its control registers. We also | |
627 | * have to wait for the next vblank for that to take | |
628 | * effect. However, since we delay enabling FBC we can | |
629 | * assume that a vblank has passed since disabling and | |
630 | * that we can safely alter the registers in the deferred | |
631 | * callback. | |
632 | * | |
633 | * In the scenario that we go from a valid to invalid | |
634 | * and then back to valid FBC configuration we have | |
635 | * no strict enforcement that a vblank occurred since | |
636 | * disabling the FBC. However, along all current pipe | |
637 | * disabling paths we do need to wait for a vblank at | |
638 | * some point. And we wait before enabling FBC anyway. | |
639 | */ | |
640 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
641 | intel_fbc_disable(dev); | |
642 | } | |
643 | ||
644 | intel_fbc_enable(crtc); | |
645 | dev_priv->fbc.no_fbc_reason = FBC_OK; | |
646 | return; | |
647 | ||
648 | out_disable: | |
649 | /* Multiple disables should be harmless */ | |
650 | if (intel_fbc_enabled(dev)) { | |
651 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
652 | intel_fbc_disable(dev); | |
653 | } | |
654 | i915_gem_stolen_cleanup_compression(dev); | |
655 | } | |
656 | ||
dbef0f15 PZ |
657 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
658 | unsigned int frontbuffer_bits, | |
659 | enum fb_op_origin origin) | |
660 | { | |
661 | struct drm_device *dev = dev_priv->dev; | |
662 | unsigned int fbc_bits; | |
663 | ||
664 | if (origin == ORIGIN_GTT) | |
665 | return; | |
666 | ||
667 | if (dev_priv->fbc.enabled) | |
668 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); | |
669 | else if (dev_priv->fbc.fbc_work) | |
670 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( | |
671 | to_intel_crtc(dev_priv->fbc.fbc_work->crtc)->pipe); | |
672 | else | |
673 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
674 | ||
675 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
676 | ||
677 | if (dev_priv->fbc.busy_bits) | |
678 | intel_fbc_disable(dev); | |
679 | } | |
680 | ||
681 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
682 | unsigned int frontbuffer_bits) | |
683 | { | |
684 | struct drm_device *dev = dev_priv->dev; | |
685 | ||
686 | if (!dev_priv->fbc.busy_bits) | |
687 | return; | |
688 | ||
689 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
690 | ||
691 | if (!dev_priv->fbc.busy_bits) | |
692 | intel_fbc_update(dev); | |
693 | } | |
694 | ||
94b83957 RV |
695 | /** |
696 | * intel_fbc_init - Initialize FBC | |
697 | * @dev_priv: the i915 device | |
698 | * | |
699 | * This function might be called during PM init process. | |
700 | */ | |
7ff0ebcc RV |
701 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
702 | { | |
dbef0f15 PZ |
703 | enum pipe pipe; |
704 | ||
7ff0ebcc RV |
705 | if (!HAS_FBC(dev_priv)) { |
706 | dev_priv->fbc.enabled = false; | |
104618b3 | 707 | dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
7ff0ebcc RV |
708 | return; |
709 | } | |
710 | ||
dbef0f15 PZ |
711 | for_each_pipe(dev_priv, pipe) { |
712 | dev_priv->fbc.possible_framebuffer_bits |= | |
713 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
714 | ||
715 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
716 | break; | |
717 | } | |
718 | ||
7ff0ebcc RV |
719 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
720 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; | |
721 | dev_priv->display.enable_fbc = gen7_fbc_enable; | |
722 | dev_priv->display.disable_fbc = ilk_fbc_disable; | |
723 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { | |
724 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; | |
725 | dev_priv->display.enable_fbc = ilk_fbc_enable; | |
726 | dev_priv->display.disable_fbc = ilk_fbc_disable; | |
727 | } else if (IS_GM45(dev_priv)) { | |
728 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
729 | dev_priv->display.enable_fbc = g4x_fbc_enable; | |
730 | dev_priv->display.disable_fbc = g4x_fbc_disable; | |
731 | } else { | |
732 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; | |
733 | dev_priv->display.enable_fbc = i8xx_fbc_enable; | |
734 | dev_priv->display.disable_fbc = i8xx_fbc_disable; | |
735 | ||
736 | /* This value was pulled out of someone's hat */ | |
737 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
738 | } | |
739 | ||
740 | dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev); | |
741 | } |