Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
f5bbfca3 | 40 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 41 | { |
4ef69c7a | 42 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
43 | } |
44 | ||
df0e9248 CW |
45 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
46 | { | |
47 | return container_of(intel_attached_encoder(connector), | |
48 | struct intel_hdmi, base); | |
49 | } | |
50 | ||
45187ace | 51 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 52 | { |
45187ace | 53 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
54 | uint8_t sum = 0; |
55 | unsigned i; | |
56 | ||
45187ace JB |
57 | frame->checksum = 0; |
58 | frame->ecc = 0; | |
3c17fe4b | 59 | |
64a8fc01 | 60 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
61 | sum += data[i]; |
62 | ||
45187ace | 63 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
64 | } |
65 | ||
bc2481f3 | 66 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 67 | { |
45187ace JB |
68 | switch (frame->type) { |
69 | case DIP_TYPE_AVI: | |
ed517fbb | 70 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 71 | case DIP_TYPE_SPD: |
ed517fbb | 72 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
73 | default: |
74 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 75 | return 0; |
45187ace | 76 | } |
45187ace JB |
77 | } |
78 | ||
bc2481f3 | 79 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 80 | { |
45187ace JB |
81 | switch (frame->type) { |
82 | case DIP_TYPE_AVI: | |
ed517fbb | 83 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 84 | case DIP_TYPE_SPD: |
ed517fbb | 85 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
86 | default: |
87 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 88 | return 0; |
fa193ff7 | 89 | } |
fa193ff7 PZ |
90 | } |
91 | ||
2da8af54 PZ |
92 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
93 | { | |
94 | switch (frame->type) { | |
95 | case DIP_TYPE_AVI: | |
96 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
97 | case DIP_TYPE_SPD: | |
98 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
99 | default: | |
100 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
101 | return 0; | |
102 | } | |
103 | } | |
104 | ||
105 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
106 | { | |
107 | switch (frame->type) { | |
108 | case DIP_TYPE_AVI: | |
109 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
110 | case DIP_TYPE_SPD: | |
111 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
112 | default: | |
113 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
114 | return 0; | |
115 | } | |
116 | } | |
117 | ||
a3da1df7 DV |
118 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
119 | struct dip_infoframe *frame) | |
45187ace JB |
120 | { |
121 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
122 | struct drm_device *dev = encoder->dev; |
123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 124 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 125 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 126 | |
822974ae PZ |
127 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
128 | ||
1d4f85ac | 129 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 130 | val |= g4x_infoframe_index(frame); |
22509ec8 | 131 | |
bc2481f3 | 132 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 133 | |
22509ec8 | 134 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 135 | |
45187ace | 136 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
137 | I915_WRITE(VIDEO_DIP_DATA, *data); |
138 | data++; | |
139 | } | |
140 | ||
bc2481f3 | 141 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 142 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 143 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 144 | |
22509ec8 | 145 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
146 | } |
147 | ||
fdf1250a PZ |
148 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
149 | struct dip_infoframe *frame) | |
150 | { | |
151 | uint32_t *data = (uint32_t *)frame; | |
152 | struct drm_device *dev = encoder->dev; | |
153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 154 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
155 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
156 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
157 | u32 val = I915_READ(reg); | |
158 | ||
822974ae PZ |
159 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
160 | ||
fdf1250a | 161 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 162 | val |= g4x_infoframe_index(frame); |
fdf1250a | 163 | |
bc2481f3 | 164 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
165 | |
166 | I915_WRITE(reg, val); | |
167 | ||
168 | for (i = 0; i < len; i += 4) { | |
169 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
170 | data++; | |
171 | } | |
172 | ||
bc2481f3 | 173 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 174 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 175 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
176 | |
177 | I915_WRITE(reg, val); | |
178 | } | |
179 | ||
180 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
181 | struct dip_infoframe *frame) | |
b055c8f3 | 182 | { |
45187ace | 183 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
184 | struct drm_device *dev = encoder->dev; |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 186 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 187 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 188 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 189 | u32 val = I915_READ(reg); |
b055c8f3 | 190 | |
822974ae PZ |
191 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
192 | ||
64a8fc01 | 193 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 194 | val |= g4x_infoframe_index(frame); |
45187ace | 195 | |
ecb97851 PZ |
196 | /* The DIP control register spec says that we need to update the AVI |
197 | * infoframe without clearing its enable bit */ | |
822974ae | 198 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 199 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 200 | |
22509ec8 | 201 | I915_WRITE(reg, val); |
45187ace JB |
202 | |
203 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
204 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
205 | data++; | |
206 | } | |
207 | ||
bc2481f3 | 208 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 209 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 210 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 211 | |
22509ec8 | 212 | I915_WRITE(reg, val); |
45187ace | 213 | } |
90b107c8 SK |
214 | |
215 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
216 | struct dip_infoframe *frame) | |
217 | { | |
218 | uint32_t *data = (uint32_t *)frame; | |
219 | struct drm_device *dev = encoder->dev; | |
220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 221 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
222 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
223 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 224 | u32 val = I915_READ(reg); |
90b107c8 | 225 | |
822974ae PZ |
226 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
227 | ||
90b107c8 | 228 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 229 | val |= g4x_infoframe_index(frame); |
22509ec8 | 230 | |
bc2481f3 | 231 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 232 | |
22509ec8 | 233 | I915_WRITE(reg, val); |
90b107c8 SK |
234 | |
235 | for (i = 0; i < len; i += 4) { | |
236 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
237 | data++; | |
238 | } | |
239 | ||
bc2481f3 | 240 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 243 | |
22509ec8 | 244 | I915_WRITE(reg, val); |
90b107c8 SK |
245 | } |
246 | ||
8c5f5f7c | 247 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 248 | struct dip_infoframe *frame) |
8c5f5f7c | 249 | { |
2da8af54 PZ |
250 | uint32_t *data = (uint32_t *)frame; |
251 | struct drm_device *dev = encoder->dev; | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
254 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
255 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
256 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
257 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 258 | |
2da8af54 PZ |
259 | if (data_reg == 0) |
260 | return; | |
261 | ||
2da8af54 PZ |
262 | val &= ~hsw_infoframe_enable(frame); |
263 | I915_WRITE(ctl_reg, val); | |
264 | ||
265 | for (i = 0; i < len; i += 4) { | |
266 | I915_WRITE(data_reg + i, *data); | |
267 | data++; | |
268 | } | |
8c5f5f7c | 269 | |
2da8af54 PZ |
270 | val |= hsw_infoframe_enable(frame); |
271 | I915_WRITE(ctl_reg, val); | |
8c5f5f7c ED |
272 | } |
273 | ||
45187ace JB |
274 | static void intel_set_infoframe(struct drm_encoder *encoder, |
275 | struct dip_infoframe *frame) | |
276 | { | |
277 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
278 | ||
45187ace JB |
279 | intel_dip_infoframe_csum(frame); |
280 | intel_hdmi->write_infoframe(encoder, frame); | |
281 | } | |
282 | ||
687f4d06 | 283 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 284 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
285 | { |
286 | struct dip_infoframe avi_if = { | |
287 | .type = DIP_TYPE_AVI, | |
288 | .ver = DIP_VERSION_AVI, | |
289 | .len = DIP_LEN_AVI, | |
290 | }; | |
291 | ||
c846b619 PZ |
292 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
293 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
294 | ||
45187ace | 295 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
296 | } |
297 | ||
687f4d06 | 298 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
299 | { |
300 | struct dip_infoframe spd_if; | |
301 | ||
302 | memset(&spd_if, 0, sizeof(spd_if)); | |
303 | spd_if.type = DIP_TYPE_SPD; | |
304 | spd_if.ver = DIP_VERSION_SPD; | |
305 | spd_if.len = DIP_LEN_SPD; | |
306 | strcpy(spd_if.body.spd.vn, "Intel"); | |
307 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
308 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
309 | ||
310 | intel_set_infoframe(encoder, &spd_if); | |
311 | } | |
312 | ||
687f4d06 PZ |
313 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
314 | struct drm_display_mode *adjusted_mode) | |
315 | { | |
0c14c7f9 PZ |
316 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
317 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
318 | u32 reg = VIDEO_DIP_CTL; | |
319 | u32 val = I915_READ(reg); | |
320 | ||
321 | /* If the registers were not initialized yet, they might be zeroes, | |
322 | * which means we're selecting the AVI DIP and we're setting its | |
323 | * frequency to once. This seems to really confuse the HW and make | |
324 | * things stop working (the register spec says the AVI always needs to | |
325 | * be sent every VSync). So here we avoid writing to the register more | |
326 | * than we need and also explicitly select the AVI DIP and explicitly | |
327 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
328 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
329 | * either. */ | |
330 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
331 | ||
332 | if (!intel_hdmi->has_hdmi_sink) { | |
333 | if (!(val & VIDEO_DIP_ENABLE)) | |
334 | return; | |
335 | val &= ~VIDEO_DIP_ENABLE; | |
336 | I915_WRITE(reg, val); | |
337 | return; | |
338 | } | |
339 | ||
f278d972 PZ |
340 | val &= ~VIDEO_DIP_PORT_MASK; |
341 | switch (intel_hdmi->sdvox_reg) { | |
342 | case SDVOB: | |
343 | val |= VIDEO_DIP_PORT_B; | |
344 | break; | |
345 | case SDVOC: | |
346 | val |= VIDEO_DIP_PORT_C; | |
347 | break; | |
348 | default: | |
349 | return; | |
350 | } | |
351 | ||
822974ae | 352 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 353 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 354 | |
f278d972 PZ |
355 | I915_WRITE(reg, val); |
356 | ||
687f4d06 PZ |
357 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
358 | intel_hdmi_set_spd_infoframe(encoder); | |
359 | } | |
360 | ||
361 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
362 | struct drm_display_mode *adjusted_mode) | |
363 | { | |
0c14c7f9 PZ |
364 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
365 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
366 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
367 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
368 | u32 val = I915_READ(reg); | |
369 | ||
370 | /* See the big comment in g4x_set_infoframes() */ | |
371 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
372 | ||
373 | if (!intel_hdmi->has_hdmi_sink) { | |
374 | if (!(val & VIDEO_DIP_ENABLE)) | |
375 | return; | |
376 | val &= ~VIDEO_DIP_ENABLE; | |
377 | I915_WRITE(reg, val); | |
378 | return; | |
379 | } | |
380 | ||
f278d972 PZ |
381 | val &= ~VIDEO_DIP_PORT_MASK; |
382 | switch (intel_hdmi->sdvox_reg) { | |
383 | case HDMIB: | |
384 | val |= VIDEO_DIP_PORT_B; | |
385 | break; | |
386 | case HDMIC: | |
387 | val |= VIDEO_DIP_PORT_C; | |
388 | break; | |
389 | case HDMID: | |
390 | val |= VIDEO_DIP_PORT_D; | |
391 | break; | |
392 | default: | |
393 | return; | |
394 | } | |
395 | ||
822974ae | 396 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
397 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
398 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 399 | |
f278d972 PZ |
400 | I915_WRITE(reg, val); |
401 | ||
687f4d06 PZ |
402 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
403 | intel_hdmi_set_spd_infoframe(encoder); | |
404 | } | |
405 | ||
406 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
407 | struct drm_display_mode *adjusted_mode) | |
408 | { | |
0c14c7f9 PZ |
409 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
410 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
411 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
412 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
413 | u32 val = I915_READ(reg); | |
414 | ||
415 | /* See the big comment in g4x_set_infoframes() */ | |
416 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
417 | ||
418 | if (!intel_hdmi->has_hdmi_sink) { | |
419 | if (!(val & VIDEO_DIP_ENABLE)) | |
420 | return; | |
421 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
422 | I915_WRITE(reg, val); | |
423 | return; | |
424 | } | |
425 | ||
822974ae PZ |
426 | /* Set both together, unset both together: see the spec. */ |
427 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
428 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
429 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
430 | |
431 | I915_WRITE(reg, val); | |
432 | ||
687f4d06 PZ |
433 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
434 | intel_hdmi_set_spd_infoframe(encoder); | |
435 | } | |
436 | ||
437 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
438 | struct drm_display_mode *adjusted_mode) | |
439 | { | |
0c14c7f9 PZ |
440 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
441 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
442 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
443 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
444 | u32 val = I915_READ(reg); | |
445 | ||
446 | /* See the big comment in g4x_set_infoframes() */ | |
447 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
448 | ||
449 | if (!intel_hdmi->has_hdmi_sink) { | |
450 | if (!(val & VIDEO_DIP_ENABLE)) | |
451 | return; | |
452 | val &= ~VIDEO_DIP_ENABLE; | |
453 | I915_WRITE(reg, val); | |
454 | return; | |
455 | } | |
456 | ||
822974ae | 457 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
458 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
459 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
460 | |
461 | I915_WRITE(reg, val); | |
462 | ||
687f4d06 PZ |
463 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
464 | intel_hdmi_set_spd_infoframe(encoder); | |
465 | } | |
466 | ||
467 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
468 | struct drm_display_mode *adjusted_mode) | |
469 | { | |
0c14c7f9 PZ |
470 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
471 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
472 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
473 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
0dd87d20 | 474 | u32 val = I915_READ(reg); |
0c14c7f9 PZ |
475 | |
476 | if (!intel_hdmi->has_hdmi_sink) { | |
477 | I915_WRITE(reg, 0); | |
478 | return; | |
479 | } | |
480 | ||
0dd87d20 PZ |
481 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
482 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
483 | ||
484 | I915_WRITE(reg, val); | |
485 | ||
687f4d06 PZ |
486 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
487 | intel_hdmi_set_spd_infoframe(encoder); | |
488 | } | |
489 | ||
7d57382e EA |
490 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
491 | struct drm_display_mode *mode, | |
492 | struct drm_display_mode *adjusted_mode) | |
493 | { | |
494 | struct drm_device *dev = encoder->dev; | |
495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 496 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 497 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
498 | u32 sdvox; |
499 | ||
b599c0bc | 500 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
501 | if (!HAS_PCH_SPLIT(dev)) |
502 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
503 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
504 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
505 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
506 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 507 | |
020f6704 JB |
508 | if (intel_crtc->bpp > 24) |
509 | sdvox |= COLOR_FORMAT_12bpc; | |
510 | else | |
511 | sdvox |= COLOR_FORMAT_8bpc; | |
512 | ||
2e3d6006 ZW |
513 | /* Required on CPT */ |
514 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
515 | sdvox |= HDMI_MODE_SELECT; | |
516 | ||
3c17fe4b | 517 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
518 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
519 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 520 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 521 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 522 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 523 | } |
7d57382e | 524 | |
75770564 JB |
525 | if (HAS_PCH_CPT(dev)) |
526 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
527 | else if (intel_crtc->pipe == 1) | |
528 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 529 | |
ea5b213a CW |
530 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
531 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 532 | |
687f4d06 | 533 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
534 | } |
535 | ||
536 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
537 | { | |
538 | struct drm_device *dev = encoder->dev; | |
539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 540 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 541 | u32 temp; |
2deed761 WF |
542 | u32 enable_bits = SDVO_ENABLE; |
543 | ||
544 | if (intel_hdmi->has_audio) | |
545 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 546 | |
ea5b213a | 547 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
548 | |
549 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
550 | * we do this anyway which shows more stable in testing. | |
551 | */ | |
c619eed4 | 552 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
553 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
554 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
555 | } |
556 | ||
557 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 558 | temp &= ~enable_bits; |
7d57382e | 559 | } else { |
2deed761 | 560 | temp |= enable_bits; |
7d57382e | 561 | } |
d8a2d0e0 | 562 | |
ea5b213a CW |
563 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
564 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
565 | |
566 | /* HW workaround, need to write this twice for issue that may result | |
567 | * in first write getting masked. | |
568 | */ | |
c619eed4 | 569 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
570 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
571 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 572 | } |
7d57382e EA |
573 | } |
574 | ||
7d57382e EA |
575 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
576 | struct drm_display_mode *mode) | |
577 | { | |
578 | if (mode->clock > 165000) | |
579 | return MODE_CLOCK_HIGH; | |
580 | if (mode->clock < 20000) | |
5cbba41d | 581 | return MODE_CLOCK_LOW; |
7d57382e EA |
582 | |
583 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
584 | return MODE_NO_DBLESCAN; | |
585 | ||
586 | return MODE_OK; | |
587 | } | |
588 | ||
589 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
590 | struct drm_display_mode *mode, | |
591 | struct drm_display_mode *adjusted_mode) | |
592 | { | |
593 | return true; | |
594 | } | |
595 | ||
8ec22b21 CW |
596 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
597 | { | |
598 | struct drm_device *dev = intel_hdmi->base.base.dev; | |
599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
600 | uint32_t bit; | |
601 | ||
602 | switch (intel_hdmi->sdvox_reg) { | |
eeafaaca | 603 | case SDVOB: |
8ec22b21 CW |
604 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
605 | break; | |
eeafaaca | 606 | case SDVOC: |
8ec22b21 CW |
607 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
608 | break; | |
8ec22b21 CW |
609 | default: |
610 | bit = 0; | |
611 | break; | |
612 | } | |
613 | ||
614 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
615 | } | |
616 | ||
aa93d632 | 617 | static enum drm_connector_status |
930a9e28 | 618 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 619 | { |
df0e9248 | 620 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
621 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
622 | struct edid *edid; | |
aa93d632 | 623 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 624 | |
8ec22b21 CW |
625 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
626 | return status; | |
627 | ||
ea5b213a | 628 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 629 | intel_hdmi->has_audio = false; |
f899fc64 | 630 | edid = drm_get_edid(connector, |
3bd7d909 DK |
631 | intel_gmbus_get_adapter(dev_priv, |
632 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 633 | |
aa93d632 | 634 | if (edid) { |
be9f1c4f | 635 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 636 | status = connector_status_connected; |
b1d7e4b4 WF |
637 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
638 | intel_hdmi->has_hdmi_sink = | |
639 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 640 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 641 | } |
674e2d08 | 642 | connector->display_info.raw_edid = NULL; |
aa93d632 | 643 | kfree(edid); |
9dff6af8 | 644 | } |
30ad48b7 | 645 | |
55b7d6e8 | 646 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
647 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
648 | intel_hdmi->has_audio = | |
649 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
650 | } |
651 | ||
2ded9e27 | 652 | return status; |
7d57382e EA |
653 | } |
654 | ||
655 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
656 | { | |
df0e9248 | 657 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 658 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
659 | |
660 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
661 | * we can send audio to it. | |
662 | */ | |
663 | ||
f899fc64 | 664 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
665 | intel_gmbus_get_adapter(dev_priv, |
666 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
667 | } |
668 | ||
1aad7ac0 CW |
669 | static bool |
670 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
671 | { | |
672 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
673 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
674 | struct edid *edid; | |
675 | bool has_audio = false; | |
676 | ||
677 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
678 | intel_gmbus_get_adapter(dev_priv, |
679 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
680 | if (edid) { |
681 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
682 | has_audio = drm_detect_monitor_audio(edid); | |
683 | ||
684 | connector->display_info.raw_edid = NULL; | |
685 | kfree(edid); | |
686 | } | |
687 | ||
688 | return has_audio; | |
689 | } | |
690 | ||
55b7d6e8 CW |
691 | static int |
692 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
693 | struct drm_property *property, |
694 | uint64_t val) | |
55b7d6e8 CW |
695 | { |
696 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 697 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
698 | int ret; |
699 | ||
700 | ret = drm_connector_property_set_value(connector, property, val); | |
701 | if (ret) | |
702 | return ret; | |
703 | ||
3f43c48d | 704 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 705 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
706 | bool has_audio; |
707 | ||
708 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
709 | return 0; |
710 | ||
1aad7ac0 | 711 | intel_hdmi->force_audio = i; |
55b7d6e8 | 712 | |
b1d7e4b4 | 713 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
714 | has_audio = intel_hdmi_detect_audio(connector); |
715 | else | |
b1d7e4b4 | 716 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 717 | |
b1d7e4b4 WF |
718 | if (i == HDMI_AUDIO_OFF_DVI) |
719 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 720 | |
1aad7ac0 | 721 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
722 | goto done; |
723 | } | |
724 | ||
e953fd7b CW |
725 | if (property == dev_priv->broadcast_rgb_property) { |
726 | if (val == !!intel_hdmi->color_range) | |
727 | return 0; | |
728 | ||
729 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
730 | goto done; | |
731 | } | |
732 | ||
55b7d6e8 CW |
733 | return -EINVAL; |
734 | ||
735 | done: | |
736 | if (intel_hdmi->base.base.crtc) { | |
737 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
738 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
739 | crtc->x, crtc->y, | |
740 | crtc->fb); | |
741 | } | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
7d57382e EA |
746 | static void intel_hdmi_destroy(struct drm_connector *connector) |
747 | { | |
7d57382e EA |
748 | drm_sysfs_connector_remove(connector); |
749 | drm_connector_cleanup(connector); | |
674e2d08 | 750 | kfree(connector); |
7d57382e EA |
751 | } |
752 | ||
72662e10 ED |
753 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
754 | .dpms = intel_ddi_dpms, | |
755 | .mode_fixup = intel_hdmi_mode_fixup, | |
756 | .prepare = intel_encoder_prepare, | |
757 | .mode_set = intel_ddi_mode_set, | |
758 | .commit = intel_encoder_commit, | |
759 | }; | |
760 | ||
7d57382e EA |
761 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
762 | .dpms = intel_hdmi_dpms, | |
763 | .mode_fixup = intel_hdmi_mode_fixup, | |
764 | .prepare = intel_encoder_prepare, | |
765 | .mode_set = intel_hdmi_mode_set, | |
766 | .commit = intel_encoder_commit, | |
767 | }; | |
768 | ||
769 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 770 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
771 | .detect = intel_hdmi_detect, |
772 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 773 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
774 | .destroy = intel_hdmi_destroy, |
775 | }; | |
776 | ||
777 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
778 | .get_modes = intel_hdmi_get_modes, | |
779 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 780 | .best_encoder = intel_best_encoder, |
7d57382e EA |
781 | }; |
782 | ||
7d57382e | 783 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 784 | .destroy = intel_encoder_destroy, |
7d57382e EA |
785 | }; |
786 | ||
55b7d6e8 CW |
787 | static void |
788 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
789 | { | |
3f43c48d | 790 | intel_attach_force_audio_property(connector); |
e953fd7b | 791 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
792 | } |
793 | ||
7d57382e EA |
794 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
795 | { | |
796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
797 | struct drm_connector *connector; | |
21d40d37 | 798 | struct intel_encoder *intel_encoder; |
674e2d08 | 799 | struct intel_connector *intel_connector; |
ea5b213a | 800 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 801 | int i; |
7d57382e | 802 | |
ea5b213a CW |
803 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
804 | if (!intel_hdmi) | |
7d57382e | 805 | return; |
674e2d08 ZW |
806 | |
807 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
808 | if (!intel_connector) { | |
ea5b213a | 809 | kfree(intel_hdmi); |
674e2d08 ZW |
810 | return; |
811 | } | |
812 | ||
ea5b213a | 813 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
814 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
815 | DRM_MODE_ENCODER_TMDS); | |
816 | ||
674e2d08 | 817 | connector = &intel_connector->base; |
7d57382e | 818 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 819 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
820 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
821 | ||
21d40d37 | 822 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 823 | |
eb1f8e4f | 824 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 825 | connector->interlace_allowed = 1; |
7d57382e | 826 | connector->doublescan_allowed = 0; |
27f8227b | 827 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
828 | |
829 | /* Set up the DDC bus. */ | |
f8aed700 | 830 | if (sdvox_reg == SDVOB) { |
21d40d37 | 831 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 832 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 833 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 834 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 835 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 836 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 837 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 838 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 839 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 840 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 841 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 842 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 843 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 844 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 845 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 846 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 847 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 848 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 849 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
7ceae0a5 ED |
850 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
851 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); | |
852 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); | |
853 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; | |
854 | intel_hdmi->ddi_port = PORT_B; | |
855 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | |
856 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { | |
857 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); | |
858 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); | |
859 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; | |
860 | intel_hdmi->ddi_port = PORT_C; | |
861 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | |
862 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { | |
863 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); | |
864 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); | |
865 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
866 | intel_hdmi->ddi_port = PORT_D; | |
867 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | |
6e4c1677 ED |
868 | } else { |
869 | /* If we got an unknown sdvox_reg, things are pretty much broken | |
870 | * in a way that we should let the kernel know about it */ | |
871 | BUG(); | |
f8aed700 | 872 | } |
7d57382e | 873 | |
ea5b213a | 874 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 875 | |
64a8fc01 | 876 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 877 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 878 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
64a8fc01 | 879 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
880 | } else if (IS_VALLEYVIEW(dev)) { |
881 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 882 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
90b107c8 SK |
883 | for_each_pipe(i) |
884 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
8c5f5f7c ED |
885 | } else if (IS_HASWELL(dev)) { |
886 | /* FIXME: Haswell has a new set of DIP frame registers, but we are | |
887 | * just doing the minimal required for HDMI to work at this stage. | |
888 | */ | |
889 | intel_hdmi->write_infoframe = hsw_write_infoframe; | |
687f4d06 | 890 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
8c5f5f7c ED |
891 | for_each_pipe(i) |
892 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); | |
fdf1250a PZ |
893 | } else if (HAS_PCH_IBX(dev)) { |
894 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 895 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
896 | for_each_pipe(i) |
897 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
898 | } else { | |
899 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 900 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 JB |
901 | for_each_pipe(i) |
902 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
903 | } | |
45187ace | 904 | |
72662e10 ED |
905 | if (IS_HASWELL(dev)) |
906 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw); | |
907 | else | |
908 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); | |
7d57382e | 909 | |
55b7d6e8 CW |
910 | intel_hdmi_add_properties(intel_hdmi, connector); |
911 | ||
df0e9248 | 912 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
913 | drm_sysfs_connector_add(connector); |
914 | ||
915 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
916 | * 0xd. Failure to do so will result in spurious interrupts being | |
917 | * generated on the port when a cable is not attached. | |
918 | */ | |
919 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
920 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
921 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
922 | } | |
7d57382e | 923 | } |