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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
f899fc64 | 3 | * Copyright © 2006-2008,2010 Intel Corporation |
79e53945 JB |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
f899fc64 | 27 | * Chris Wilson <chris@chris-wilson.co.uk> |
79e53945 JB |
28 | */ |
29 | #include <linux/i2c.h> | |
79e53945 | 30 | #include <linux/i2c-algo-bit.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
79e53945 | 33 | #include "intel_drv.h" |
760285e7 | 34 | #include <drm/i915_drm.h> |
79e53945 JB |
35 | #include "i915_drv.h" |
36 | ||
24eb2d59 CML |
37 | enum disp_clk { |
38 | CDCLK, | |
39 | CZCLK | |
40 | }; | |
41 | ||
2ed06c93 DK |
42 | struct gmbus_port { |
43 | const char *name; | |
44 | int reg; | |
45 | }; | |
46 | ||
47 | static const struct gmbus_port gmbus_ports[] = { | |
48 | { "ssc", GPIOB }, | |
49 | { "vga", GPIOA }, | |
50 | { "panel", GPIOC }, | |
51 | { "dpc", GPIOD }, | |
52 | { "dpb", GPIOE }, | |
53 | { "dpd", GPIOF }, | |
54 | }; | |
55 | ||
f899fc64 CW |
56 | /* Intel GPIO access functions */ |
57 | ||
1849ecb2 | 58 | #define I2C_RISEFALL_TIME 10 |
f899fc64 | 59 | |
e957d772 CW |
60 | static inline struct intel_gmbus * |
61 | to_intel_gmbus(struct i2c_adapter *i2c) | |
62 | { | |
63 | return container_of(i2c, struct intel_gmbus, adapter); | |
64 | } | |
65 | ||
24eb2d59 CML |
66 | static int get_disp_clk_div(struct drm_i915_private *dev_priv, |
67 | enum disp_clk clk) | |
68 | { | |
69 | u32 reg_val; | |
70 | int clk_ratio; | |
71 | ||
72 | reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO); | |
73 | ||
74 | if (clk == CDCLK) | |
75 | clk_ratio = | |
76 | ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1; | |
77 | else | |
78 | clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1; | |
79 | ||
80 | return clk_ratio; | |
81 | } | |
82 | ||
83 | static void gmbus_set_freq(struct drm_i915_private *dev_priv) | |
84 | { | |
85 | int vco_freq[] = { 800, 1600, 2000, 2400 }; | |
86 | int gmbus_freq = 0, cdclk_div, hpll_freq; | |
87 | ||
88 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
89 | ||
90 | /* Skip setting the gmbus freq if BIOS has already programmed it */ | |
91 | if (I915_READ(GMBUSFREQ_VLV) != 0xA0) | |
92 | return; | |
93 | ||
94 | /* Obtain SKU information */ | |
95 | mutex_lock(&dev_priv->dpio_lock); | |
96 | hpll_freq = | |
97 | vlv_cck_read(dev_priv, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK; | |
98 | mutex_unlock(&dev_priv->dpio_lock); | |
99 | ||
100 | /* Get the CDCLK divide ratio */ | |
101 | cdclk_div = get_disp_clk_div(dev_priv, CDCLK); | |
102 | ||
103 | /* | |
104 | * Program the gmbus_freq based on the cdclk frequency. | |
105 | * BSpec erroneously claims we should aim for 4MHz, but | |
106 | * in fact 1MHz is the correct frequency. | |
107 | */ | |
108 | if (cdclk_div) | |
109 | gmbus_freq = (vco_freq[hpll_freq] << 1) / cdclk_div; | |
110 | ||
111 | if (WARN_ON(gmbus_freq == 0)) | |
112 | return; | |
113 | ||
114 | I915_WRITE(GMBUSFREQ_VLV, gmbus_freq); | |
115 | } | |
116 | ||
f899fc64 CW |
117 | void |
118 | intel_i2c_reset(struct drm_device *dev) | |
0ba0e9e1 SL |
119 | { |
120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
24eb2d59 CML |
121 | |
122 | /* | |
123 | * In BIOS-less system, program the correct gmbus frequency | |
124 | * before reading edid. | |
125 | */ | |
126 | if (IS_VALLEYVIEW(dev)) | |
127 | gmbus_set_freq(dev_priv); | |
128 | ||
110447fc | 129 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); |
28c70f16 | 130 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); |
f899fc64 CW |
131 | } |
132 | ||
133 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) | |
134 | { | |
b222f267 | 135 | u32 val; |
0ba0e9e1 SL |
136 | |
137 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ | |
f899fc64 | 138 | if (!IS_PINEVIEW(dev_priv->dev)) |
0ba0e9e1 | 139 | return; |
b222f267 CW |
140 | |
141 | val = I915_READ(DSPCLK_GATE_D); | |
0ba0e9e1 | 142 | if (enable) |
b222f267 | 143 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
0ba0e9e1 | 144 | else |
b222f267 CW |
145 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
146 | I915_WRITE(DSPCLK_GATE_D, val); | |
0ba0e9e1 SL |
147 | } |
148 | ||
36c785f0 | 149 | static u32 get_reserved(struct intel_gmbus *bus) |
e957d772 | 150 | { |
36c785f0 | 151 | struct drm_i915_private *dev_priv = bus->dev_priv; |
e957d772 CW |
152 | struct drm_device *dev = dev_priv->dev; |
153 | u32 reserved = 0; | |
154 | ||
155 | /* On most chips, these bits must be preserved in software. */ | |
156 | if (!IS_I830(dev) && !IS_845G(dev)) | |
36c785f0 | 157 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
db5e4172 YL |
158 | (GPIO_DATA_PULLUP_DISABLE | |
159 | GPIO_CLOCK_PULLUP_DISABLE); | |
e957d772 CW |
160 | |
161 | return reserved; | |
162 | } | |
163 | ||
79e53945 JB |
164 | static int get_clock(void *data) |
165 | { | |
36c785f0 DV |
166 | struct intel_gmbus *bus = data; |
167 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
168 | u32 reserved = get_reserved(bus); | |
169 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); | |
170 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
171 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; | |
79e53945 JB |
172 | } |
173 | ||
174 | static int get_data(void *data) | |
175 | { | |
36c785f0 DV |
176 | struct intel_gmbus *bus = data; |
177 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
178 | u32 reserved = get_reserved(bus); | |
179 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); | |
180 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
181 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; | |
79e53945 JB |
182 | } |
183 | ||
184 | static void set_clock(void *data, int state_high) | |
185 | { | |
36c785f0 DV |
186 | struct intel_gmbus *bus = data; |
187 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
188 | u32 reserved = get_reserved(bus); | |
e957d772 | 189 | u32 clock_bits; |
79e53945 JB |
190 | |
191 | if (state_high) | |
192 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; | |
193 | else | |
194 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | | |
195 | GPIO_CLOCK_VAL_MASK; | |
f899fc64 | 196 | |
36c785f0 DV |
197 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
198 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
199 | } |
200 | ||
201 | static void set_data(void *data, int state_high) | |
202 | { | |
36c785f0 DV |
203 | struct intel_gmbus *bus = data; |
204 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
205 | u32 reserved = get_reserved(bus); | |
e957d772 | 206 | u32 data_bits; |
79e53945 JB |
207 | |
208 | if (state_high) | |
209 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; | |
210 | else | |
211 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | | |
212 | GPIO_DATA_VAL_MASK; | |
213 | ||
36c785f0 DV |
214 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
215 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
216 | } |
217 | ||
489fbc10 DK |
218 | static int |
219 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) | |
220 | { | |
221 | struct intel_gmbus *bus = container_of(adapter, | |
222 | struct intel_gmbus, | |
223 | adapter); | |
224 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
225 | ||
226 | intel_i2c_reset(dev_priv->dev); | |
227 | intel_i2c_quirk_set(dev_priv, true); | |
228 | set_data(bus, 1); | |
229 | set_clock(bus, 1); | |
230 | udelay(I2C_RISEFALL_TIME); | |
231 | return 0; | |
232 | } | |
233 | ||
234 | static void | |
235 | intel_gpio_post_xfer(struct i2c_adapter *adapter) | |
236 | { | |
237 | struct intel_gmbus *bus = container_of(adapter, | |
238 | struct intel_gmbus, | |
239 | adapter); | |
240 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
241 | ||
242 | set_data(bus, 1); | |
243 | set_clock(bus, 1); | |
244 | intel_i2c_quirk_set(dev_priv, false); | |
245 | } | |
246 | ||
2ed06c93 | 247 | static void |
f6f808c8 | 248 | intel_gpio_setup(struct intel_gmbus *bus, u32 pin) |
f0217c42 | 249 | { |
36c785f0 | 250 | struct drm_i915_private *dev_priv = bus->dev_priv; |
36c785f0 | 251 | struct i2c_algo_bit_data *algo; |
f0217c42 | 252 | |
c167a6fc | 253 | algo = &bus->bit_algo; |
36c785f0 | 254 | |
2ed06c93 DK |
255 | /* -1 to map pin pair to gmbus index */ |
256 | bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; | |
79e53945 | 257 | |
c167a6fc | 258 | bus->adapter.algo_data = algo; |
36c785f0 DV |
259 | algo->setsda = set_data; |
260 | algo->setscl = set_clock; | |
261 | algo->getsda = get_data; | |
262 | algo->getscl = get_clock; | |
489fbc10 DK |
263 | algo->pre_xfer = intel_gpio_pre_xfer; |
264 | algo->post_xfer = intel_gpio_post_xfer; | |
36c785f0 DV |
265 | algo->udelay = I2C_RISEFALL_TIME; |
266 | algo->timeout = usecs_to_jiffies(2200); | |
267 | algo->data = bus; | |
79e53945 JB |
268 | } |
269 | ||
c12aba5a JK |
270 | /* |
271 | * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI | |
272 | * mode. This results in spurious interrupt warnings if the legacy irq no. is | |
273 | * shared with another device. The kernel then disables that interrupt source | |
274 | * and so prevents the other device from working properly. | |
275 | */ | |
276 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
61168c53 DV |
277 | static int |
278 | gmbus_wait_hw_status(struct drm_i915_private *dev_priv, | |
28c70f16 DV |
279 | u32 gmbus2_status, |
280 | u32 gmbus4_irq_en) | |
61168c53 | 281 | { |
28c70f16 | 282 | int i; |
61168c53 | 283 | int reg_offset = dev_priv->gpio_mmio_base; |
28c70f16 DV |
284 | u32 gmbus2 = 0; |
285 | DEFINE_WAIT(wait); | |
286 | ||
c12aba5a JK |
287 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
288 | gmbus4_irq_en = 0; | |
289 | ||
28c70f16 DV |
290 | /* Important: The hw handles only the first bit, so set only one! Since |
291 | * we also need to check for NAKs besides the hw ready/idle signal, we | |
292 | * need to wake up periodically and check that ourselves. */ | |
293 | I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); | |
294 | ||
2554fc1f | 295 | for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { |
28c70f16 DV |
296 | prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
297 | TASK_UNINTERRUPTIBLE); | |
298 | ||
ef04f00d | 299 | gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); |
28c70f16 DV |
300 | if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) |
301 | break; | |
61168c53 | 302 | |
28c70f16 DV |
303 | schedule_timeout(1); |
304 | } | |
305 | finish_wait(&dev_priv->gmbus_wait_queue, &wait); | |
306 | ||
307 | I915_WRITE(GMBUS4 + reg_offset, 0); | |
61168c53 DV |
308 | |
309 | if (gmbus2 & GMBUS_SATOER) | |
310 | return -ENXIO; | |
28c70f16 DV |
311 | if (gmbus2 & gmbus2_status) |
312 | return 0; | |
313 | return -ETIMEDOUT; | |
61168c53 DV |
314 | } |
315 | ||
2c438c02 DV |
316 | static int |
317 | gmbus_wait_idle(struct drm_i915_private *dev_priv) | |
318 | { | |
319 | int ret; | |
320 | int reg_offset = dev_priv->gpio_mmio_base; | |
321 | ||
ef04f00d | 322 | #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) |
2c438c02 DV |
323 | |
324 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) | |
325 | return wait_for(C, 10); | |
326 | ||
327 | /* Important: The hw handles only the first bit, so set only one! */ | |
328 | I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); | |
329 | ||
3598706b ID |
330 | ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
331 | msecs_to_jiffies_timeout(10)); | |
2c438c02 DV |
332 | |
333 | I915_WRITE(GMBUS4 + reg_offset, 0); | |
334 | ||
335 | if (ret) | |
336 | return 0; | |
337 | else | |
338 | return -ETIMEDOUT; | |
339 | #undef C | |
340 | } | |
341 | ||
924a93ed | 342 | static int |
56f9eac0 DK |
343 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
344 | u32 gmbus1_index) | |
924a93ed DK |
345 | { |
346 | int reg_offset = dev_priv->gpio_mmio_base; | |
347 | u16 len = msg->len; | |
348 | u8 *buf = msg->buf; | |
349 | ||
350 | I915_WRITE(GMBUS1 + reg_offset, | |
56f9eac0 | 351 | gmbus1_index | |
924a93ed | 352 | GMBUS_CYCLE_WAIT | |
924a93ed DK |
353 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
354 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
355 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); | |
79985eee | 356 | while (len) { |
90e6b26d | 357 | int ret; |
924a93ed DK |
358 | u32 val, loop = 0; |
359 | ||
28c70f16 DV |
360 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
361 | GMBUS_HW_RDY_EN); | |
90e6b26d | 362 | if (ret) |
61168c53 | 363 | return ret; |
924a93ed DK |
364 | |
365 | val = I915_READ(GMBUS3 + reg_offset); | |
366 | do { | |
367 | *buf++ = val & 0xff; | |
368 | val >>= 8; | |
369 | } while (--len && ++loop < 4); | |
79985eee | 370 | } |
924a93ed DK |
371 | |
372 | return 0; | |
373 | } | |
374 | ||
375 | static int | |
72d66afd | 376 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) |
924a93ed DK |
377 | { |
378 | int reg_offset = dev_priv->gpio_mmio_base; | |
379 | u16 len = msg->len; | |
380 | u8 *buf = msg->buf; | |
381 | u32 val, loop; | |
382 | ||
383 | val = loop = 0; | |
26883c31 DK |
384 | while (len && loop < 4) { |
385 | val |= *buf++ << (8 * loop++); | |
386 | len -= 1; | |
387 | } | |
924a93ed DK |
388 | |
389 | I915_WRITE(GMBUS3 + reg_offset, val); | |
390 | I915_WRITE(GMBUS1 + reg_offset, | |
391 | GMBUS_CYCLE_WAIT | | |
924a93ed DK |
392 | (msg->len << GMBUS_BYTE_COUNT_SHIFT) | |
393 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
394 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); | |
924a93ed | 395 | while (len) { |
90e6b26d | 396 | int ret; |
90e6b26d | 397 | |
924a93ed DK |
398 | val = loop = 0; |
399 | do { | |
400 | val |= *buf++ << (8 * loop); | |
401 | } while (--len && ++loop < 4); | |
402 | ||
403 | I915_WRITE(GMBUS3 + reg_offset, val); | |
7a39a9d4 | 404 | |
28c70f16 DV |
405 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
406 | GMBUS_HW_RDY_EN); | |
90e6b26d | 407 | if (ret) |
61168c53 | 408 | return ret; |
924a93ed DK |
409 | } |
410 | return 0; | |
411 | } | |
412 | ||
56f9eac0 DK |
413 | /* |
414 | * The gmbus controller can combine a 1 or 2 byte write with a read that | |
415 | * immediately follows it by using an "INDEX" cycle. | |
416 | */ | |
417 | static bool | |
418 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) | |
419 | { | |
420 | return (i + 1 < num && | |
421 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && | |
422 | (msgs[i + 1].flags & I2C_M_RD)); | |
423 | } | |
424 | ||
425 | static int | |
426 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) | |
427 | { | |
428 | int reg_offset = dev_priv->gpio_mmio_base; | |
429 | u32 gmbus1_index = 0; | |
430 | u32 gmbus5 = 0; | |
431 | int ret; | |
432 | ||
433 | if (msgs[0].len == 2) | |
434 | gmbus5 = GMBUS_2BYTE_INDEX_EN | | |
435 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); | |
436 | if (msgs[0].len == 1) | |
437 | gmbus1_index = GMBUS_CYCLE_INDEX | | |
438 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); | |
439 | ||
440 | /* GMBUS5 holds 16-bit index */ | |
441 | if (gmbus5) | |
442 | I915_WRITE(GMBUS5 + reg_offset, gmbus5); | |
443 | ||
444 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); | |
445 | ||
446 | /* Clear GMBUS5 after each index transfer */ | |
447 | if (gmbus5) | |
448 | I915_WRITE(GMBUS5 + reg_offset, 0); | |
449 | ||
450 | return ret; | |
451 | } | |
452 | ||
f899fc64 CW |
453 | static int |
454 | gmbus_xfer(struct i2c_adapter *adapter, | |
455 | struct i2c_msg *msgs, | |
456 | int num) | |
457 | { | |
458 | struct intel_gmbus *bus = container_of(adapter, | |
459 | struct intel_gmbus, | |
460 | adapter); | |
c2b9152f | 461 | struct drm_i915_private *dev_priv = bus->dev_priv; |
72d66afd DK |
462 | int i, reg_offset; |
463 | int ret = 0; | |
f899fc64 | 464 | |
c67a470b | 465 | intel_aux_display_runtime_get(dev_priv); |
8a8ed1f5 YS |
466 | mutex_lock(&dev_priv->gmbus_mutex); |
467 | ||
468 | if (bus->force_bit) { | |
489fbc10 | 469 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
8a8ed1f5 YS |
470 | goto out; |
471 | } | |
f899fc64 | 472 | |
110447fc | 473 | reg_offset = dev_priv->gpio_mmio_base; |
f899fc64 | 474 | |
e957d772 | 475 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
f899fc64 CW |
476 | |
477 | for (i = 0; i < num; i++) { | |
56f9eac0 DK |
478 | if (gmbus_is_index_read(msgs, i, num)) { |
479 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); | |
480 | i += 1; /* set i to the index of the read xfer */ | |
481 | } else if (msgs[i].flags & I2C_M_RD) { | |
482 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); | |
483 | } else { | |
72d66afd | 484 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
56f9eac0 | 485 | } |
924a93ed DK |
486 | |
487 | if (ret == -ETIMEDOUT) | |
488 | goto timeout; | |
489 | if (ret == -ENXIO) | |
490 | goto clear_err; | |
491 | ||
28c70f16 DV |
492 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, |
493 | GMBUS_HW_WAIT_EN); | |
61168c53 DV |
494 | if (ret == -ENXIO) |
495 | goto clear_err; | |
90e6b26d | 496 | if (ret) |
f899fc64 | 497 | goto timeout; |
f899fc64 CW |
498 | } |
499 | ||
72d66afd DK |
500 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
501 | * a STOP on the very first cycle. To simplify the code we | |
502 | * unconditionally generate the STOP condition with an additional gmbus | |
503 | * cycle. */ | |
504 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); | |
505 | ||
e646d577 DK |
506 | /* Mark the GMBUS interface as disabled after waiting for idle. |
507 | * We will re-enable it at the start of the next xfer, | |
508 | * till then let it sleep. | |
509 | */ | |
2c438c02 | 510 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f | 511 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
e646d577 | 512 | adapter->name); |
72d66afd DK |
513 | ret = -ETIMEDOUT; |
514 | } | |
e646d577 | 515 | I915_WRITE(GMBUS0 + reg_offset, 0); |
72d66afd | 516 | ret = ret ?: i; |
e646d577 | 517 | goto out; |
7f58aabc CW |
518 | |
519 | clear_err: | |
e646d577 DK |
520 | /* |
521 | * Wait for bus to IDLE before clearing NAK. | |
522 | * If we clear the NAK while bus is still active, then it will stay | |
523 | * active and the next transaction may fail. | |
65e81866 DV |
524 | * |
525 | * If no ACK is received during the address phase of a transaction, the | |
526 | * adapter must report -ENXIO. It is not clear what to return if no ACK | |
527 | * is received at other times. But we have to be careful to not return | |
528 | * spurious -ENXIO because that will prevent i2c and drm edid functions | |
529 | * from retrying. So return -ENXIO only when gmbus properly quiescents - | |
530 | * timing out seems to happen when there _is_ a ddc chip present, but | |
531 | * it's slow responding and only answers on the 2nd retry. | |
e646d577 | 532 | */ |
65e81866 | 533 | ret = -ENXIO; |
2c438c02 | 534 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f DK |
535 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
536 | adapter->name); | |
65e81866 DV |
537 | ret = -ETIMEDOUT; |
538 | } | |
e646d577 | 539 | |
7f58aabc CW |
540 | /* Toggle the Software Clear Interrupt bit. This has the effect |
541 | * of resetting the GMBUS controller and so clearing the | |
542 | * BUS_ERROR raised by the slave's NAK. | |
543 | */ | |
544 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); | |
545 | I915_WRITE(GMBUS1 + reg_offset, 0); | |
e646d577 | 546 | I915_WRITE(GMBUS0 + reg_offset, 0); |
7f58aabc | 547 | |
56fa6d6f | 548 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
e646d577 DK |
549 | adapter->name, msgs[i].addr, |
550 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); | |
551 | ||
8a8ed1f5 | 552 | goto out; |
f899fc64 CW |
553 | |
554 | timeout: | |
874e3cc9 DK |
555 | DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
556 | bus->adapter.name, bus->reg0 & 0xff); | |
7f58aabc CW |
557 | I915_WRITE(GMBUS0 + reg_offset, 0); |
558 | ||
2ed06c93 | 559 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
f2ce9faf | 560 | bus->force_bit = 1; |
2ed06c93 | 561 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
489fbc10 | 562 | |
8a8ed1f5 YS |
563 | out: |
564 | mutex_unlock(&dev_priv->gmbus_mutex); | |
c67a470b | 565 | intel_aux_display_runtime_put(dev_priv); |
8a8ed1f5 | 566 | return ret; |
f899fc64 CW |
567 | } |
568 | ||
569 | static u32 gmbus_func(struct i2c_adapter *adapter) | |
570 | { | |
f6f808c8 DV |
571 | return i2c_bit_algo.functionality(adapter) & |
572 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
f899fc64 CW |
573 | /* I2C_FUNC_10BIT_ADDR | */ |
574 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
575 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); | |
576 | } | |
577 | ||
578 | static const struct i2c_algorithm gmbus_algorithm = { | |
579 | .master_xfer = gmbus_xfer, | |
580 | .functionality = gmbus_func | |
581 | }; | |
582 | ||
79e53945 | 583 | /** |
f899fc64 CW |
584 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
585 | * @dev: DRM device | |
79e53945 | 586 | */ |
f899fc64 CW |
587 | int intel_setup_gmbus(struct drm_device *dev) |
588 | { | |
f899fc64 CW |
589 | struct drm_i915_private *dev_priv = dev->dev_private; |
590 | int ret, i; | |
591 | ||
ab5c608b BW |
592 | if (HAS_PCH_NOP(dev)) |
593 | return 0; | |
594 | else if (HAS_PCH_SPLIT(dev)) | |
110447fc | 595 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
d8112150 VS |
596 | else if (IS_VALLEYVIEW(dev)) |
597 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; | |
110447fc DV |
598 | else |
599 | dev_priv->gpio_mmio_base = 0; | |
600 | ||
8a8ed1f5 | 601 | mutex_init(&dev_priv->gmbus_mutex); |
28c70f16 | 602 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
8a8ed1f5 | 603 | |
f899fc64 CW |
604 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
605 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; | |
2ed06c93 | 606 | u32 port = i + 1; /* +1 to map gmbus index to pin pair */ |
f899fc64 CW |
607 | |
608 | bus->adapter.owner = THIS_MODULE; | |
609 | bus->adapter.class = I2C_CLASS_DDC; | |
610 | snprintf(bus->adapter.name, | |
69669455 JD |
611 | sizeof(bus->adapter.name), |
612 | "i915 gmbus %s", | |
2ed06c93 | 613 | gmbus_ports[i].name); |
f899fc64 CW |
614 | |
615 | bus->adapter.dev.parent = &dev->pdev->dev; | |
c2b9152f | 616 | bus->dev_priv = dev_priv; |
f899fc64 CW |
617 | |
618 | bus->adapter.algo = &gmbus_algorithm; | |
f899fc64 | 619 | |
e957d772 | 620 | /* By default use a conservative clock rate */ |
2ed06c93 | 621 | bus->reg0 = port | GMBUS_RATE_100KHZ; |
cb8ea752 | 622 | |
83ee9e64 DV |
623 | /* gmbus seems to be broken on i830 */ |
624 | if (IS_I830(dev)) | |
f2ce9faf | 625 | bus->force_bit = 1; |
83ee9e64 | 626 | |
2ed06c93 | 627 | intel_gpio_setup(bus, port); |
cee25168 JN |
628 | |
629 | ret = i2c_add_adapter(&bus->adapter); | |
630 | if (ret) | |
631 | goto err; | |
f899fc64 CW |
632 | } |
633 | ||
634 | intel_i2c_reset(dev_priv->dev); | |
635 | ||
636 | return 0; | |
637 | ||
638 | err: | |
639 | while (--i) { | |
640 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; | |
641 | i2c_del_adapter(&bus->adapter); | |
642 | } | |
f899fc64 CW |
643 | return ret; |
644 | } | |
645 | ||
3bd7d909 DK |
646 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
647 | unsigned port) | |
648 | { | |
649 | WARN_ON(!intel_gmbus_is_port_valid(port)); | |
2ed06c93 | 650 | /* -1 to map pin pair to gmbus index */ |
3bd7d909 | 651 | return (intel_gmbus_is_port_valid(port)) ? |
2ed06c93 | 652 | &dev_priv->gmbus[port - 1].adapter : NULL; |
3bd7d909 DK |
653 | } |
654 | ||
e957d772 CW |
655 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
656 | { | |
657 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
658 | ||
d5090b96 | 659 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
e957d772 CW |
660 | } |
661 | ||
662 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) | |
663 | { | |
664 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
665 | ||
f2ce9faf CW |
666 | bus->force_bit += force_bit ? 1 : -1; |
667 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", | |
668 | force_bit ? "en" : "dis", adapter->name, | |
669 | bus->force_bit); | |
e957d772 CW |
670 | } |
671 | ||
f899fc64 | 672 | void intel_teardown_gmbus(struct drm_device *dev) |
79e53945 | 673 | { |
f899fc64 CW |
674 | struct drm_i915_private *dev_priv = dev->dev_private; |
675 | int i; | |
f9c10a9b | 676 | |
f899fc64 CW |
677 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
678 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; | |
f899fc64 CW |
679 | i2c_del_adapter(&bus->adapter); |
680 | } | |
79e53945 | 681 | } |