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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
158 | |
159 | #define CTX_LRI_HEADER_0 0x01 | |
160 | #define CTX_CONTEXT_CONTROL 0x02 | |
161 | #define CTX_RING_HEAD 0x04 | |
162 | #define CTX_RING_TAIL 0x06 | |
163 | #define CTX_RING_BUFFER_START 0x08 | |
164 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
165 | #define CTX_BB_HEAD_U 0x0c | |
166 | #define CTX_BB_HEAD_L 0x0e | |
167 | #define CTX_BB_STATE 0x10 | |
168 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
169 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
170 | #define CTX_SECOND_BB_STATE 0x16 | |
171 | #define CTX_BB_PER_CTX_PTR 0x18 | |
172 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
173 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
174 | #define CTX_LRI_HEADER_1 0x21 | |
175 | #define CTX_CTX_TIMESTAMP 0x22 | |
176 | #define CTX_PDP3_UDW 0x24 | |
177 | #define CTX_PDP3_LDW 0x26 | |
178 | #define CTX_PDP2_UDW 0x28 | |
179 | #define CTX_PDP2_LDW 0x2a | |
180 | #define CTX_PDP1_UDW 0x2c | |
181 | #define CTX_PDP1_LDW 0x2e | |
182 | #define CTX_PDP0_UDW 0x30 | |
183 | #define CTX_PDP0_LDW 0x32 | |
184 | #define CTX_LRI_HEADER_2 0x41 | |
185 | #define CTX_R_PWR_CLK_STATE 0x42 | |
186 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
187 | ||
84b790f8 BW |
188 | #define GEN8_CTX_VALID (1<<0) |
189 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
190 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
191 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
192 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 193 | |
0d925ea0 | 194 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 195 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
196 | (reg_state)[(pos)+1] = (val); \ |
197 | } while (0) | |
198 | ||
199 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 200 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
201 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
202 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 203 | } while (0) |
e5815a2e | 204 | |
9244a817 | 205 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
206 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
207 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 208 | } while (0) |
2dba3239 | 209 | |
84b790f8 BW |
210 | enum { |
211 | ADVANCED_CONTEXT = 0, | |
2dba3239 | 212 | LEGACY_32B_CONTEXT, |
84b790f8 BW |
213 | ADVANCED_AD_CONTEXT, |
214 | LEGACY_64B_CONTEXT | |
215 | }; | |
2dba3239 MT |
216 | #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
217 | #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ | |
218 | LEGACY_64B_CONTEXT :\ | |
219 | LEGACY_32B_CONTEXT) | |
84b790f8 BW |
220 | enum { |
221 | FAULT_AND_HANG = 0, | |
222 | FAULT_AND_HALT, /* Debug only */ | |
223 | FAULT_AND_STREAM, | |
224 | FAULT_AND_CONTINUE /* Unsupported */ | |
225 | }; | |
226 | #define GEN8_CTX_ID_SHIFT 32 | |
7069b144 | 227 | #define GEN8_CTX_ID_WIDTH 21 |
71562919 MT |
228 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
229 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 230 | |
e5292823 TU |
231 | static int intel_lr_context_pin(struct intel_context *ctx, |
232 | struct intel_engine_cs *engine); | |
7ba717cf | 233 | |
73e4d07f OM |
234 | /** |
235 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
236 | * @dev: DRM device. | |
237 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
238 | * | |
239 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 240 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
241 | * |
242 | * Return: 1 if Execlists is supported and has to be enabled. | |
243 | */ | |
127f1003 OM |
244 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
245 | { | |
bd84b1e9 DV |
246 | WARN_ON(i915.enable_ppgtt == -1); |
247 | ||
a0bd6c31 ZL |
248 | /* On platforms with execlist available, vGPU will only |
249 | * support execlist mode, no ring buffer mode. | |
250 | */ | |
251 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev)) | |
252 | return 1; | |
253 | ||
70ee45e1 DL |
254 | if (INTEL_INFO(dev)->gen >= 9) |
255 | return 1; | |
256 | ||
127f1003 OM |
257 | if (enable_execlists == 0) |
258 | return 0; | |
259 | ||
14bf993e OM |
260 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
261 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
262 | return 1; |
263 | ||
264 | return 0; | |
265 | } | |
ede7d42b | 266 | |
ca82580c | 267 | static void |
0bc40be8 | 268 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 269 | { |
0bc40be8 | 270 | struct drm_device *dev = engine->dev; |
ca82580c | 271 | |
c6a2ac71 | 272 | if (IS_GEN8(dev) || IS_GEN9(dev)) |
0bc40be8 | 273 | engine->idle_lite_restore_wa = ~0; |
c6a2ac71 | 274 | |
0bc40be8 | 275 | engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
ca82580c | 276 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) && |
0bc40be8 | 277 | (engine->id == VCS || engine->id == VCS2); |
ca82580c | 278 | |
0bc40be8 TU |
279 | engine->ctx_desc_template = GEN8_CTX_VALID; |
280 | engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) << | |
ca82580c TU |
281 | GEN8_CTX_ADDRESSING_MODE_SHIFT; |
282 | if (IS_GEN8(dev)) | |
0bc40be8 TU |
283 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
284 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
285 | |
286 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
287 | * signalling between Command Streamers */ | |
288 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
289 | ||
290 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
291 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
292 | if (engine->disable_lite_restore_wa) |
293 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
294 | } |
295 | ||
73e4d07f | 296 | /** |
ca82580c TU |
297 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
298 | * descriptor for a pinned context | |
73e4d07f | 299 | * |
ca82580c TU |
300 | * @ctx: Context to work on |
301 | * @ring: Engine the descriptor will be used with | |
73e4d07f | 302 | * |
ca82580c TU |
303 | * The context descriptor encodes various attributes of a context, |
304 | * including its GTT address and some flags. Because it's fairly | |
305 | * expensive to calculate, we'll just do it once and cache the result, | |
306 | * which remains valid until the context is unpinned. | |
307 | * | |
308 | * This is what a descriptor looks like, from LSB to MSB: | |
ef87bba8 | 309 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) |
ca82580c | 310 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
7069b144 | 311 | * bits 32-52: ctx ID, a globally unique tag |
ef87bba8 CW |
312 | * bits 53-54: mbz, reserved for use by hardware |
313 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 314 | */ |
ca82580c TU |
315 | static void |
316 | intel_lr_context_descriptor_update(struct intel_context *ctx, | |
0bc40be8 | 317 | struct intel_engine_cs *engine) |
84b790f8 | 318 | { |
7069b144 | 319 | u64 desc; |
84b790f8 | 320 | |
7069b144 | 321 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 322 | |
7069b144 CW |
323 | desc = engine->ctx_desc_template; /* bits 0-11 */ |
324 | desc |= ctx->engine[engine->id].lrc_vma->node.start + /* bits 12-31 */ | |
325 | LRC_PPHWSP_PN * PAGE_SIZE; | |
326 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ | |
5af05fef | 327 | |
0bc40be8 | 328 | ctx->engine[engine->id].lrc_desc = desc; |
5af05fef MT |
329 | } |
330 | ||
919f1f55 | 331 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
0bc40be8 | 332 | struct intel_engine_cs *engine) |
84b790f8 | 333 | { |
0bc40be8 | 334 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 335 | } |
203a571b | 336 | |
cc3c4253 MK |
337 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
338 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 339 | { |
cc3c4253 | 340 | |
4a570db5 | 341 | struct intel_engine_cs *engine = rq0->engine; |
e2f80391 | 342 | struct drm_device *dev = engine->dev; |
6e7cc470 | 343 | struct drm_i915_private *dev_priv = dev->dev_private; |
1cff8cc3 | 344 | uint64_t desc[2]; |
84b790f8 | 345 | |
1cff8cc3 | 346 | if (rq1) { |
4a570db5 | 347 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine); |
1cff8cc3 MK |
348 | rq1->elsp_submitted++; |
349 | } else { | |
350 | desc[1] = 0; | |
351 | } | |
84b790f8 | 352 | |
4a570db5 | 353 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine); |
1cff8cc3 | 354 | rq0->elsp_submitted++; |
84b790f8 | 355 | |
1cff8cc3 | 356 | /* You must always write both descriptors in the order below. */ |
e2f80391 TU |
357 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1])); |
358 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1])); | |
6daccb0b | 359 | |
e2f80391 | 360 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0])); |
84b790f8 | 361 | /* The context is automatically loaded after the following */ |
e2f80391 | 362 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0])); |
84b790f8 | 363 | |
1cff8cc3 | 364 | /* ELSP is a wo register, use another nearby reg for posting */ |
e2f80391 | 365 | POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine)); |
84b790f8 BW |
366 | } |
367 | ||
c6a2ac71 TU |
368 | static void |
369 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
370 | { | |
371 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
372 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
373 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
374 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
375 | } | |
376 | ||
377 | static void execlists_update_context(struct drm_i915_gem_request *rq) | |
ae1250b9 | 378 | { |
4a570db5 | 379 | struct intel_engine_cs *engine = rq->engine; |
05d9824b | 380 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
e2f80391 | 381 | uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state; |
ae1250b9 | 382 | |
05d9824b | 383 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 384 | |
c6a2ac71 TU |
385 | /* True 32b PPGTT with dynamic page allocation: update PDP |
386 | * registers and point the unallocated PDPs to scratch page. | |
387 | * PML4 is allocated during ppgtt init, so this is not needed | |
388 | * in 48-bit mode. | |
389 | */ | |
390 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
391 | execlists_update_context_pdps(ppgtt, reg_state); | |
ae1250b9 OM |
392 | } |
393 | ||
d8cb8875 MK |
394 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
395 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 396 | { |
26720ab9 | 397 | struct drm_i915_private *dev_priv = rq0->i915; |
3756685a | 398 | unsigned int fw_domains = rq0->engine->fw_domains; |
26720ab9 | 399 | |
05d9824b | 400 | execlists_update_context(rq0); |
d8cb8875 | 401 | |
cc3c4253 | 402 | if (rq1) |
05d9824b | 403 | execlists_update_context(rq1); |
84b790f8 | 404 | |
27af5eea | 405 | spin_lock_irq(&dev_priv->uncore.lock); |
3756685a | 406 | intel_uncore_forcewake_get__locked(dev_priv, fw_domains); |
26720ab9 | 407 | |
cc3c4253 | 408 | execlists_elsp_write(rq0, rq1); |
26720ab9 | 409 | |
3756685a | 410 | intel_uncore_forcewake_put__locked(dev_priv, fw_domains); |
27af5eea | 411 | spin_unlock_irq(&dev_priv->uncore.lock); |
84b790f8 BW |
412 | } |
413 | ||
26720ab9 | 414 | static void execlists_context_unqueue(struct intel_engine_cs *engine) |
acdd884a | 415 | { |
6d3d8274 | 416 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
c6a2ac71 | 417 | struct drm_i915_gem_request *cursor, *tmp; |
e981e7b1 | 418 | |
0bc40be8 | 419 | assert_spin_locked(&engine->execlist_lock); |
acdd884a | 420 | |
779949f4 PA |
421 | /* |
422 | * If irqs are not active generate a warning as batches that finish | |
423 | * without the irqs may get lost and a GPU Hang may occur. | |
424 | */ | |
0bc40be8 | 425 | WARN_ON(!intel_irqs_enabled(engine->dev->dev_private)); |
779949f4 | 426 | |
acdd884a | 427 | /* Try to read in pairs */ |
0bc40be8 | 428 | list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue, |
acdd884a MT |
429 | execlist_link) { |
430 | if (!req0) { | |
431 | req0 = cursor; | |
6d3d8274 | 432 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
433 | /* Same ctx: ignore first request, as second request |
434 | * will update tail past first request's workload */ | |
e1fee72c | 435 | cursor->elsp_submitted = req0->elsp_submitted; |
7eb08a25 | 436 | list_move_tail(&req0->execlist_link, |
0bc40be8 | 437 | &engine->execlist_retired_req_list); |
acdd884a MT |
438 | req0 = cursor; |
439 | } else { | |
440 | req1 = cursor; | |
c6a2ac71 | 441 | WARN_ON(req1->elsp_submitted); |
acdd884a MT |
442 | break; |
443 | } | |
444 | } | |
445 | ||
c6a2ac71 TU |
446 | if (unlikely(!req0)) |
447 | return; | |
448 | ||
0bc40be8 | 449 | if (req0->elsp_submitted & engine->idle_lite_restore_wa) { |
53292cdb | 450 | /* |
c6a2ac71 TU |
451 | * WaIdleLiteRestore: make sure we never cause a lite restore |
452 | * with HEAD==TAIL. | |
453 | * | |
454 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we | |
455 | * resubmit the request. See gen8_emit_request() for where we | |
456 | * prepare the padding after the end of the request. | |
53292cdb | 457 | */ |
c6a2ac71 | 458 | struct intel_ringbuffer *ringbuf; |
53292cdb | 459 | |
0bc40be8 | 460 | ringbuf = req0->ctx->engine[engine->id].ringbuf; |
c6a2ac71 TU |
461 | req0->tail += 8; |
462 | req0->tail &= ringbuf->size - 1; | |
53292cdb MT |
463 | } |
464 | ||
d8cb8875 | 465 | execlists_submit_requests(req0, req1); |
acdd884a MT |
466 | } |
467 | ||
c6a2ac71 | 468 | static unsigned int |
0bc40be8 | 469 | execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id) |
e981e7b1 | 470 | { |
6d3d8274 | 471 | struct drm_i915_gem_request *head_req; |
e981e7b1 | 472 | |
0bc40be8 | 473 | assert_spin_locked(&engine->execlist_lock); |
e981e7b1 | 474 | |
0bc40be8 | 475 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
6d3d8274 | 476 | struct drm_i915_gem_request, |
e981e7b1 TD |
477 | execlist_link); |
478 | ||
c6a2ac71 TU |
479 | if (!head_req) |
480 | return 0; | |
e1fee72c | 481 | |
7069b144 | 482 | if (unlikely(head_req->ctx->hw_id != request_id)) |
c6a2ac71 TU |
483 | return 0; |
484 | ||
485 | WARN(head_req->elsp_submitted == 0, "Never submitted head request\n"); | |
486 | ||
487 | if (--head_req->elsp_submitted > 0) | |
488 | return 0; | |
489 | ||
490 | list_move_tail(&head_req->execlist_link, | |
0bc40be8 | 491 | &engine->execlist_retired_req_list); |
e981e7b1 | 492 | |
c6a2ac71 | 493 | return 1; |
e981e7b1 TD |
494 | } |
495 | ||
c6a2ac71 | 496 | static u32 |
0bc40be8 | 497 | get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer, |
c6a2ac71 | 498 | u32 *context_id) |
91a41032 | 499 | { |
0bc40be8 | 500 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
c6a2ac71 | 501 | u32 status; |
91a41032 | 502 | |
c6a2ac71 TU |
503 | read_pointer %= GEN8_CSB_ENTRIES; |
504 | ||
0bc40be8 | 505 | status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer)); |
c6a2ac71 TU |
506 | |
507 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) | |
508 | return 0; | |
91a41032 | 509 | |
0bc40be8 | 510 | *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine, |
c6a2ac71 TU |
511 | read_pointer)); |
512 | ||
513 | return status; | |
91a41032 BW |
514 | } |
515 | ||
73e4d07f | 516 | /** |
3f7531c3 | 517 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
27af5eea | 518 | * @engine: Engine Command Streamer to handle. |
73e4d07f OM |
519 | * |
520 | * Check the unread Context Status Buffers and manage the submission of new | |
521 | * contexts to the ELSP accordingly. | |
522 | */ | |
27af5eea | 523 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 524 | { |
27af5eea | 525 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
0bc40be8 | 526 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
e981e7b1 | 527 | u32 status_pointer; |
c6a2ac71 | 528 | unsigned int read_pointer, write_pointer; |
26720ab9 TU |
529 | u32 csb[GEN8_CSB_ENTRIES][2]; |
530 | unsigned int csb_read = 0, i; | |
c6a2ac71 TU |
531 | unsigned int submit_contexts = 0; |
532 | ||
3756685a | 533 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 534 | |
0bc40be8 | 535 | status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine)); |
e981e7b1 | 536 | |
0bc40be8 | 537 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 538 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
e981e7b1 | 539 | if (read_pointer > write_pointer) |
dfc53c5e | 540 | write_pointer += GEN8_CSB_ENTRIES; |
e981e7b1 | 541 | |
e981e7b1 | 542 | while (read_pointer < write_pointer) { |
26720ab9 TU |
543 | if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES)) |
544 | break; | |
545 | csb[csb_read][0] = get_context_status(engine, ++read_pointer, | |
546 | &csb[csb_read][1]); | |
547 | csb_read++; | |
548 | } | |
91a41032 | 549 | |
26720ab9 TU |
550 | engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; |
551 | ||
552 | /* Update the read pointer to the old write pointer. Manual ringbuffer | |
553 | * management ftw </sarcasm> */ | |
554 | I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine), | |
555 | _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, | |
556 | engine->next_context_status_buffer << 8)); | |
557 | ||
3756685a | 558 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
26720ab9 TU |
559 | |
560 | spin_lock(&engine->execlist_lock); | |
561 | ||
562 | for (i = 0; i < csb_read; i++) { | |
563 | if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) { | |
564 | if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) { | |
565 | if (execlists_check_remove_request(engine, csb[i][1])) | |
e1fee72c OM |
566 | WARN(1, "Lite Restored request removed from queue\n"); |
567 | } else | |
568 | WARN(1, "Preemption without Lite Restore\n"); | |
569 | } | |
570 | ||
26720ab9 | 571 | if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE | |
c6a2ac71 TU |
572 | GEN8_CTX_STATUS_ELEMENT_SWITCH)) |
573 | submit_contexts += | |
26720ab9 | 574 | execlists_check_remove_request(engine, csb[i][1]); |
e981e7b1 TD |
575 | } |
576 | ||
c6a2ac71 | 577 | if (submit_contexts) { |
0bc40be8 | 578 | if (!engine->disable_lite_restore_wa || |
26720ab9 TU |
579 | (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE)) |
580 | execlists_context_unqueue(engine); | |
5af05fef | 581 | } |
e981e7b1 | 582 | |
0bc40be8 | 583 | spin_unlock(&engine->execlist_lock); |
c6a2ac71 TU |
584 | |
585 | if (unlikely(submit_contexts > 2)) | |
586 | DRM_ERROR("More than two context complete events?\n"); | |
e981e7b1 TD |
587 | } |
588 | ||
c6a2ac71 | 589 | static void execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 590 | { |
4a570db5 | 591 | struct intel_engine_cs *engine = request->engine; |
6d3d8274 | 592 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 593 | int num_elements = 0; |
acdd884a | 594 | |
24f1d3cc | 595 | intel_lr_context_pin(request->ctx, request->engine); |
9bb1af44 JH |
596 | i915_gem_request_reference(request); |
597 | ||
27af5eea | 598 | spin_lock_bh(&engine->execlist_lock); |
acdd884a | 599 | |
e2f80391 | 600 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) |
f1ad5a1f OM |
601 | if (++num_elements > 2) |
602 | break; | |
603 | ||
604 | if (num_elements > 2) { | |
6d3d8274 | 605 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f | 606 | |
e2f80391 | 607 | tail_req = list_last_entry(&engine->execlist_queue, |
6d3d8274 | 608 | struct drm_i915_gem_request, |
f1ad5a1f OM |
609 | execlist_link); |
610 | ||
ae70797d | 611 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 612 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 613 | "More than 2 already-submitted reqs queued\n"); |
7eb08a25 | 614 | list_move_tail(&tail_req->execlist_link, |
e2f80391 | 615 | &engine->execlist_retired_req_list); |
f1ad5a1f OM |
616 | } |
617 | } | |
618 | ||
e2f80391 | 619 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
f1ad5a1f | 620 | if (num_elements == 0) |
e2f80391 | 621 | execlists_context_unqueue(engine); |
acdd884a | 622 | |
27af5eea | 623 | spin_unlock_bh(&engine->execlist_lock); |
acdd884a MT |
624 | } |
625 | ||
2f20055d | 626 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 627 | { |
4a570db5 | 628 | struct intel_engine_cs *engine = req->engine; |
ba8b7ccb OM |
629 | uint32_t flush_domains; |
630 | int ret; | |
631 | ||
632 | flush_domains = 0; | |
e2f80391 | 633 | if (engine->gpu_caches_dirty) |
ba8b7ccb OM |
634 | flush_domains = I915_GEM_GPU_DOMAINS; |
635 | ||
e2f80391 | 636 | ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
637 | if (ret) |
638 | return ret; | |
639 | ||
e2f80391 | 640 | engine->gpu_caches_dirty = false; |
ba8b7ccb OM |
641 | return 0; |
642 | } | |
643 | ||
535fbe82 | 644 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
645 | struct list_head *vmas) |
646 | { | |
666796da | 647 | const unsigned other_rings = ~intel_engine_flag(req->engine); |
ba8b7ccb OM |
648 | struct i915_vma *vma; |
649 | uint32_t flush_domains = 0; | |
650 | bool flush_chipset = false; | |
651 | int ret; | |
652 | ||
653 | list_for_each_entry(vma, vmas, exec_list) { | |
654 | struct drm_i915_gem_object *obj = vma->obj; | |
655 | ||
03ade511 | 656 | if (obj->active & other_rings) { |
4a570db5 | 657 | ret = i915_gem_object_sync(obj, req->engine, &req); |
03ade511 CW |
658 | if (ret) |
659 | return ret; | |
660 | } | |
ba8b7ccb OM |
661 | |
662 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
663 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
664 | ||
665 | flush_domains |= obj->base.write_domain; | |
666 | } | |
667 | ||
668 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
669 | wmb(); | |
670 | ||
671 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
672 | * any residual writes from the previous batch. | |
673 | */ | |
2f20055d | 674 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
675 | } |
676 | ||
40e895ce | 677 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 678 | { |
24f1d3cc | 679 | struct intel_engine_cs *engine = request->engine; |
bfa01200 | 680 | int ret; |
bc0dce3f | 681 | |
6310346e CW |
682 | /* Flush enough space to reduce the likelihood of waiting after |
683 | * we start building the request - in which case we will just | |
684 | * have to repeat work. | |
685 | */ | |
686 | request->reserved_space += MIN_SPACE_FOR_ADD_REQUEST; | |
687 | ||
24f1d3cc | 688 | request->ringbuf = request->ctx->engine[engine->id].ringbuf; |
f3cc01f0 | 689 | |
a7e02199 AD |
690 | if (i915.enable_guc_submission) { |
691 | /* | |
692 | * Check that the GuC has space for the request before | |
693 | * going any further, as the i915_add_request() call | |
694 | * later on mustn't fail ... | |
695 | */ | |
696 | struct intel_guc *guc = &request->i915->guc; | |
697 | ||
698 | ret = i915_guc_wq_check_space(guc->execbuf_client); | |
699 | if (ret) | |
700 | return ret; | |
701 | } | |
702 | ||
24f1d3cc CW |
703 | ret = intel_lr_context_pin(request->ctx, engine); |
704 | if (ret) | |
705 | return ret; | |
e28e404c | 706 | |
bfa01200 CW |
707 | ret = intel_ring_begin(request, 0); |
708 | if (ret) | |
709 | goto err_unpin; | |
710 | ||
24f1d3cc CW |
711 | if (!request->ctx->engine[engine->id].initialised) { |
712 | ret = engine->init_context(request); | |
713 | if (ret) | |
714 | goto err_unpin; | |
715 | ||
716 | request->ctx->engine[engine->id].initialised = true; | |
717 | } | |
718 | ||
719 | /* Note that after this point, we have committed to using | |
720 | * this request as it is being used to both track the | |
721 | * state of engine initialisation and liveness of the | |
722 | * golden renderstate above. Think twice before you try | |
723 | * to cancel/unwind this request now. | |
724 | */ | |
725 | ||
6310346e | 726 | request->reserved_space -= MIN_SPACE_FOR_ADD_REQUEST; |
bfa01200 CW |
727 | return 0; |
728 | ||
729 | err_unpin: | |
24f1d3cc | 730 | intel_lr_context_unpin(request->ctx, engine); |
e28e404c | 731 | return ret; |
bc0dce3f JH |
732 | } |
733 | ||
bc0dce3f JH |
734 | /* |
735 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 736 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
737 | * |
738 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
739 | * really happens during submission is that the context and current tail will be placed | |
740 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
741 | * point, the tail *inside* the context is updated and the ELSP written to. | |
742 | */ | |
7c17d377 | 743 | static int |
ae70797d | 744 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 745 | { |
7c17d377 | 746 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
d1675198 | 747 | struct drm_i915_private *dev_priv = request->i915; |
4a570db5 | 748 | struct intel_engine_cs *engine = request->engine; |
bc0dce3f | 749 | |
7c17d377 CW |
750 | intel_logical_ring_advance(ringbuf); |
751 | request->tail = ringbuf->tail; | |
bc0dce3f | 752 | |
7c17d377 CW |
753 | /* |
754 | * Here we add two extra NOOPs as padding to avoid | |
755 | * lite restore of a context with HEAD==TAIL. | |
756 | * | |
757 | * Caller must reserve WA_TAIL_DWORDS for us! | |
758 | */ | |
759 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
760 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
761 | intel_logical_ring_advance(ringbuf); | |
d1675198 | 762 | |
117897f4 | 763 | if (intel_engine_stopped(engine)) |
7c17d377 | 764 | return 0; |
bc0dce3f | 765 | |
f4e2dece TU |
766 | if (engine->last_context != request->ctx) { |
767 | if (engine->last_context) | |
768 | intel_lr_context_unpin(engine->last_context, engine); | |
24f1d3cc CW |
769 | intel_lr_context_pin(request->ctx, engine); |
770 | engine->last_context = request->ctx; | |
f4e2dece TU |
771 | } |
772 | ||
d1675198 AD |
773 | if (dev_priv->guc.execbuf_client) |
774 | i915_guc_submit(dev_priv->guc.execbuf_client, request); | |
775 | else | |
776 | execlists_context_queue(request); | |
7c17d377 CW |
777 | |
778 | return 0; | |
bc0dce3f JH |
779 | } |
780 | ||
73e4d07f OM |
781 | /** |
782 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
783 | * @dev: DRM device. | |
784 | * @file: DRM file. | |
785 | * @ring: Engine Command Streamer to submit to. | |
786 | * @ctx: Context to employ for this submission. | |
787 | * @args: execbuffer call arguments. | |
788 | * @vmas: list of vmas. | |
789 | * @batch_obj: the batchbuffer to submit. | |
790 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 791 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
792 | * |
793 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
794 | * away the submission details of the execbuffer ioctl call. | |
795 | * | |
796 | * Return: non-zero if the submission fails. | |
797 | */ | |
5f19e2bf | 798 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 799 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 800 | struct list_head *vmas) |
454afebd | 801 | { |
5f19e2bf | 802 | struct drm_device *dev = params->dev; |
4a570db5 | 803 | struct intel_engine_cs *engine = params->engine; |
ba8b7ccb | 804 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 805 | struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf; |
5f19e2bf | 806 | u64 exec_start; |
ba8b7ccb OM |
807 | int instp_mode; |
808 | u32 instp_mask; | |
809 | int ret; | |
810 | ||
811 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
812 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
813 | switch (instp_mode) { | |
814 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
815 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
816 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
4a570db5 | 817 | if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) { |
ba8b7ccb OM |
818 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
819 | return -EINVAL; | |
820 | } | |
821 | ||
822 | if (instp_mode != dev_priv->relative_constants_mode) { | |
823 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
824 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
825 | return -EINVAL; | |
826 | } | |
827 | ||
828 | /* The HW changed the meaning on this bit on gen6 */ | |
829 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
830 | } | |
831 | break; | |
832 | default: | |
833 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
834 | return -EINVAL; | |
835 | } | |
836 | ||
ba8b7ccb OM |
837 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
838 | DRM_DEBUG("sol reset is gen7 only\n"); | |
839 | return -EINVAL; | |
840 | } | |
841 | ||
535fbe82 | 842 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
843 | if (ret) |
844 | return ret; | |
845 | ||
4a570db5 | 846 | if (engine == &dev_priv->engine[RCS] && |
ba8b7ccb | 847 | instp_mode != dev_priv->relative_constants_mode) { |
987046ad | 848 | ret = intel_ring_begin(params->request, 4); |
ba8b7ccb OM |
849 | if (ret) |
850 | return ret; | |
851 | ||
852 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
853 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 854 | intel_logical_ring_emit_reg(ringbuf, INSTPM); |
ba8b7ccb OM |
855 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); |
856 | intel_logical_ring_advance(ringbuf); | |
857 | ||
858 | dev_priv->relative_constants_mode = instp_mode; | |
859 | } | |
860 | ||
5f19e2bf JH |
861 | exec_start = params->batch_obj_vm_offset + |
862 | args->batch_start_offset; | |
863 | ||
e2f80391 | 864 | ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
865 | if (ret) |
866 | return ret; | |
867 | ||
95c24161 | 868 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 869 | |
8a8edb59 | 870 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
ba8b7ccb | 871 | |
454afebd OM |
872 | return 0; |
873 | } | |
874 | ||
0bc40be8 | 875 | void intel_execlists_retire_requests(struct intel_engine_cs *engine) |
c86ee3a9 | 876 | { |
6d3d8274 | 877 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
878 | struct list_head retired_list; |
879 | ||
0bc40be8 TU |
880 | WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); |
881 | if (list_empty(&engine->execlist_retired_req_list)) | |
c86ee3a9 TD |
882 | return; |
883 | ||
884 | INIT_LIST_HEAD(&retired_list); | |
27af5eea | 885 | spin_lock_bh(&engine->execlist_lock); |
0bc40be8 | 886 | list_replace_init(&engine->execlist_retired_req_list, &retired_list); |
27af5eea | 887 | spin_unlock_bh(&engine->execlist_lock); |
c86ee3a9 TD |
888 | |
889 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
24f1d3cc | 890 | intel_lr_context_unpin(req->ctx, engine); |
e5292823 | 891 | |
c86ee3a9 | 892 | list_del(&req->execlist_link); |
f8210795 | 893 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
894 | } |
895 | } | |
896 | ||
0bc40be8 | 897 | void intel_logical_ring_stop(struct intel_engine_cs *engine) |
454afebd | 898 | { |
0bc40be8 | 899 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
9832b9da OM |
900 | int ret; |
901 | ||
117897f4 | 902 | if (!intel_engine_initialized(engine)) |
9832b9da OM |
903 | return; |
904 | ||
666796da | 905 | ret = intel_engine_idle(engine); |
f4457ae7 | 906 | if (ret) |
9832b9da | 907 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 908 | engine->name, ret); |
9832b9da OM |
909 | |
910 | /* TODO: Is this correct with Execlists enabled? */ | |
0bc40be8 TU |
911 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
912 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
913 | DRM_ERROR("%s :timed out trying to stop ring\n", engine->name); | |
9832b9da OM |
914 | return; |
915 | } | |
0bc40be8 | 916 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); |
454afebd OM |
917 | } |
918 | ||
4866d729 | 919 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 920 | { |
4a570db5 | 921 | struct intel_engine_cs *engine = req->engine; |
48e29f55 OM |
922 | int ret; |
923 | ||
e2f80391 | 924 | if (!engine->gpu_caches_dirty) |
48e29f55 OM |
925 | return 0; |
926 | ||
e2f80391 | 927 | ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
928 | if (ret) |
929 | return ret; | |
930 | ||
e2f80391 | 931 | engine->gpu_caches_dirty = false; |
48e29f55 OM |
932 | return 0; |
933 | } | |
934 | ||
24f1d3cc CW |
935 | static int intel_lr_context_pin(struct intel_context *ctx, |
936 | struct intel_engine_cs *engine) | |
dcb4c12a | 937 | { |
24f1d3cc CW |
938 | struct drm_i915_private *dev_priv = ctx->i915; |
939 | struct drm_i915_gem_object *ctx_obj; | |
940 | struct intel_ringbuffer *ringbuf; | |
7d774cac TU |
941 | void *vaddr; |
942 | u32 *lrc_reg_state; | |
ca82580c | 943 | int ret; |
dcb4c12a | 944 | |
24f1d3cc | 945 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); |
ca82580c | 946 | |
24f1d3cc CW |
947 | if (ctx->engine[engine->id].pin_count++) |
948 | return 0; | |
949 | ||
950 | ctx_obj = ctx->engine[engine->id].state; | |
e84fe803 NH |
951 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
952 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
953 | if (ret) | |
24f1d3cc | 954 | goto err; |
7ba717cf | 955 | |
7d774cac TU |
956 | vaddr = i915_gem_object_pin_map(ctx_obj); |
957 | if (IS_ERR(vaddr)) { | |
958 | ret = PTR_ERR(vaddr); | |
82352e90 TU |
959 | goto unpin_ctx_obj; |
960 | } | |
961 | ||
7d774cac TU |
962 | lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
963 | ||
24f1d3cc | 964 | ringbuf = ctx->engine[engine->id].ringbuf; |
0bc40be8 | 965 | ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf); |
e84fe803 | 966 | if (ret) |
7d774cac | 967 | goto unpin_map; |
d1675198 | 968 | |
24f1d3cc | 969 | i915_gem_context_reference(ctx); |
0bc40be8 TU |
970 | ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj); |
971 | intel_lr_context_descriptor_update(ctx, engine); | |
77b04a04 | 972 | lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start; |
0bc40be8 | 973 | ctx->engine[engine->id].lrc_reg_state = lrc_reg_state; |
e84fe803 | 974 | ctx_obj->dirty = true; |
e93c28f3 | 975 | |
e84fe803 NH |
976 | /* Invalidate GuC TLB. */ |
977 | if (i915.enable_guc_submission) | |
978 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
dcb4c12a | 979 | |
24f1d3cc | 980 | return 0; |
7ba717cf | 981 | |
7d774cac TU |
982 | unpin_map: |
983 | i915_gem_object_unpin_map(ctx_obj); | |
7ba717cf TD |
984 | unpin_ctx_obj: |
985 | i915_gem_object_ggtt_unpin(ctx_obj); | |
24f1d3cc CW |
986 | err: |
987 | ctx->engine[engine->id].pin_count = 0; | |
e84fe803 NH |
988 | return ret; |
989 | } | |
990 | ||
24f1d3cc CW |
991 | void intel_lr_context_unpin(struct intel_context *ctx, |
992 | struct intel_engine_cs *engine) | |
e84fe803 | 993 | { |
24f1d3cc | 994 | struct drm_i915_gem_object *ctx_obj; |
e84fe803 | 995 | |
24f1d3cc CW |
996 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); |
997 | GEM_BUG_ON(ctx->engine[engine->id].pin_count == 0); | |
321fe304 | 998 | |
24f1d3cc CW |
999 | if (--ctx->engine[engine->id].pin_count) |
1000 | return; | |
e84fe803 | 1001 | |
24f1d3cc | 1002 | intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf); |
dcb4c12a | 1003 | |
24f1d3cc CW |
1004 | ctx_obj = ctx->engine[engine->id].state; |
1005 | i915_gem_object_unpin_map(ctx_obj); | |
1006 | i915_gem_object_ggtt_unpin(ctx_obj); | |
af3302b9 | 1007 | |
24f1d3cc CW |
1008 | ctx->engine[engine->id].lrc_vma = NULL; |
1009 | ctx->engine[engine->id].lrc_desc = 0; | |
1010 | ctx->engine[engine->id].lrc_reg_state = NULL; | |
321fe304 | 1011 | |
24f1d3cc | 1012 | i915_gem_context_unreference(ctx); |
dcb4c12a OM |
1013 | } |
1014 | ||
e2be4faf | 1015 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1016 | { |
1017 | int ret, i; | |
4a570db5 | 1018 | struct intel_engine_cs *engine = req->engine; |
e2be4faf | 1019 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
e2f80391 | 1020 | struct drm_device *dev = engine->dev; |
771b9a53 MT |
1021 | struct drm_i915_private *dev_priv = dev->dev_private; |
1022 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1023 | ||
cd7feaaa | 1024 | if (w->count == 0) |
771b9a53 MT |
1025 | return 0; |
1026 | ||
e2f80391 | 1027 | engine->gpu_caches_dirty = true; |
4866d729 | 1028 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1029 | if (ret) |
1030 | return ret; | |
1031 | ||
987046ad | 1032 | ret = intel_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1033 | if (ret) |
1034 | return ret; | |
1035 | ||
1036 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1037 | for (i = 0; i < w->count; i++) { | |
f92a9162 | 1038 | intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr); |
771b9a53 MT |
1039 | intel_logical_ring_emit(ringbuf, w->reg[i].value); |
1040 | } | |
1041 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1042 | ||
1043 | intel_logical_ring_advance(ringbuf); | |
1044 | ||
e2f80391 | 1045 | engine->gpu_caches_dirty = true; |
4866d729 | 1046 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1047 | if (ret) |
1048 | return ret; | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
83b8a982 | 1053 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 1054 | do { \ |
83b8a982 AS |
1055 | int __index = (index)++; \ |
1056 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
1057 | return -ENOSPC; \ |
1058 | } \ | |
83b8a982 | 1059 | batch[__index] = (cmd); \ |
17ee950d AS |
1060 | } while (0) |
1061 | ||
8f40db77 | 1062 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 1063 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
1064 | |
1065 | /* | |
1066 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1067 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1068 | * but there is a slight complication as this is applied in WA batch where the | |
1069 | * values are only initialized once so we cannot take register value at the | |
1070 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1071 | * constant value with bit21 set and then we restore it back with the saved value. | |
1072 | * To simplify the WA, a constant value is formed by using the default value | |
1073 | * of this register. This shouldn't be a problem because we are only modifying | |
1074 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1075 | * use additional instructions that read the actual value of the register | |
1076 | * at that time and set our bit of interest but it makes the WA complicated. | |
1077 | * | |
1078 | * This WA is also required for Gen9 so extracting as a function avoids | |
1079 | * code duplication. | |
1080 | */ | |
0bc40be8 | 1081 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
9e000847 AS |
1082 | uint32_t *const batch, |
1083 | uint32_t index) | |
1084 | { | |
1085 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1086 | ||
a4106a78 AS |
1087 | /* |
1088 | * WaDisableLSQCROPERFforOCL:skl | |
1089 | * This WA is implemented in skl_init_clock_gating() but since | |
1090 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
1091 | * set this bit here to retain the WA during flush. | |
1092 | */ | |
0bc40be8 | 1093 | if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0)) |
a4106a78 AS |
1094 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
1095 | ||
f1afe24f | 1096 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 1097 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1098 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1099 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 AS |
1100 | wa_ctx_emit(batch, index, 0); |
1101 | ||
1102 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 1103 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
1104 | wa_ctx_emit(batch, index, l3sqc4_flush); |
1105 | ||
1106 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1107 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
1108 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1109 | wa_ctx_emit(batch, index, 0); | |
1110 | wa_ctx_emit(batch, index, 0); | |
1111 | wa_ctx_emit(batch, index, 0); | |
1112 | wa_ctx_emit(batch, index, 0); | |
1113 | ||
f1afe24f | 1114 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 1115 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1116 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1117 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 | 1118 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
1119 | |
1120 | return index; | |
1121 | } | |
1122 | ||
17ee950d AS |
1123 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1124 | uint32_t offset, | |
1125 | uint32_t start_alignment) | |
1126 | { | |
1127 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1128 | } | |
1129 | ||
1130 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1131 | uint32_t offset, | |
1132 | uint32_t size_alignment) | |
1133 | { | |
1134 | wa_ctx->size = offset - wa_ctx->offset; | |
1135 | ||
1136 | WARN(wa_ctx->size % size_alignment, | |
1137 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1138 | wa_ctx->size, size_alignment); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | /** | |
1143 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1144 | * | |
1145 | * @ring: only applicable for RCS | |
1146 | * @wa_ctx: structure representing wa_ctx | |
1147 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1148 | * with the offset value received as input. | |
1149 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1150 | * @batch: page in which WA are loaded | |
1151 | * @offset: This field specifies the start of the batch, it should be | |
1152 | * cache-aligned otherwise it is adjusted accordingly. | |
1153 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1154 | * initialized at the beginning and shared across all contexts but this field | |
1155 | * helps us to have multiple batches at different offsets and select them based | |
1156 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1157 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1158 | * | |
1159 | * The number of WA applied are not known at the beginning; we use this field | |
1160 | * to return the no of DWORDS written. | |
4d78c8dc | 1161 | * |
17ee950d AS |
1162 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1163 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1164 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1165 | * makes a complete batch buffer. | |
1166 | * | |
1167 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1168 | */ | |
1169 | ||
0bc40be8 | 1170 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1171 | struct i915_wa_ctx_bb *wa_ctx, |
1172 | uint32_t *const batch, | |
1173 | uint32_t *offset) | |
1174 | { | |
0160f055 | 1175 | uint32_t scratch_addr; |
17ee950d AS |
1176 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1177 | ||
7ad00d1a | 1178 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1179 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1180 | |
c82435bb | 1181 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
0bc40be8 TU |
1182 | if (IS_BROADWELL(engine->dev)) { |
1183 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); | |
604ef734 AH |
1184 | if (rc < 0) |
1185 | return rc; | |
1186 | index = rc; | |
c82435bb AS |
1187 | } |
1188 | ||
0160f055 AS |
1189 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1190 | /* Actual scratch location is at 128 bytes offset */ | |
0bc40be8 | 1191 | scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES; |
0160f055 | 1192 | |
83b8a982 AS |
1193 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1194 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1195 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1196 | PIPE_CONTROL_CS_STALL | | |
1197 | PIPE_CONTROL_QW_WRITE)); | |
1198 | wa_ctx_emit(batch, index, scratch_addr); | |
1199 | wa_ctx_emit(batch, index, 0); | |
1200 | wa_ctx_emit(batch, index, 0); | |
1201 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1202 | |
17ee950d AS |
1203 | /* Pad to end of cacheline */ |
1204 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1205 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1206 | |
1207 | /* | |
1208 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1209 | * execution depends on the length specified in terms of cache lines | |
1210 | * in the register CTX_RCS_INDIRECT_CTX | |
1211 | */ | |
1212 | ||
1213 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1214 | } | |
1215 | ||
1216 | /** | |
1217 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1218 | * | |
1219 | * @ring: only applicable for RCS | |
1220 | * @wa_ctx: structure representing wa_ctx | |
1221 | * offset: specifies start of the batch, should be cache-aligned. | |
1222 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1223 | * @batch: page in which WA are loaded |
17ee950d AS |
1224 | * @offset: This field specifies the start of this batch. |
1225 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1226 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1227 | * | |
1228 | * The number of DWORDS written are returned using this field. | |
1229 | * | |
1230 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1231 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1232 | */ | |
0bc40be8 | 1233 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1234 | struct i915_wa_ctx_bb *wa_ctx, |
1235 | uint32_t *const batch, | |
1236 | uint32_t *offset) | |
1237 | { | |
1238 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1239 | ||
7ad00d1a | 1240 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1241 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1242 | |
83b8a982 | 1243 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1244 | |
1245 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1246 | } | |
1247 | ||
0bc40be8 | 1248 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1249 | struct i915_wa_ctx_bb *wa_ctx, |
1250 | uint32_t *const batch, | |
1251 | uint32_t *offset) | |
1252 | { | |
a4106a78 | 1253 | int ret; |
0bc40be8 | 1254 | struct drm_device *dev = engine->dev; |
0504cffc AS |
1255 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1256 | ||
0907c8f7 | 1257 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
e87a005d | 1258 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
cbdc12a9 | 1259 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
0907c8f7 | 1260 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 1261 | |
a4106a78 | 1262 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 1263 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1264 | if (ret < 0) |
1265 | return ret; | |
1266 | index = ret; | |
1267 | ||
0504cffc AS |
1268 | /* Pad to end of cacheline */ |
1269 | while (index % CACHELINE_DWORDS) | |
1270 | wa_ctx_emit(batch, index, MI_NOOP); | |
1271 | ||
1272 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1273 | } | |
1274 | ||
0bc40be8 | 1275 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1276 | struct i915_wa_ctx_bb *wa_ctx, |
1277 | uint32_t *const batch, | |
1278 | uint32_t *offset) | |
1279 | { | |
0bc40be8 | 1280 | struct drm_device *dev = engine->dev; |
0504cffc AS |
1281 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1282 | ||
9b01435d | 1283 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
e87a005d | 1284 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
cbdc12a9 | 1285 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9b01435d | 1286 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1287 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1288 | wa_ctx_emit(batch, index, |
1289 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1290 | wa_ctx_emit(batch, index, MI_NOOP); | |
1291 | } | |
1292 | ||
b1e429fe TG |
1293 | /* WaClearTdlStateAckDirtyBits:bxt */ |
1294 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { | |
1295 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); | |
1296 | ||
1297 | wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); | |
1298 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1299 | ||
1300 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); | |
1301 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1302 | ||
1303 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); | |
1304 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1305 | ||
1306 | wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); | |
1307 | /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ | |
1308 | wa_ctx_emit(batch, index, 0x0); | |
1309 | wa_ctx_emit(batch, index, MI_NOOP); | |
1310 | } | |
1311 | ||
0907c8f7 | 1312 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
e87a005d | 1313 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
cbdc12a9 | 1314 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
0907c8f7 AS |
1315 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1316 | ||
0504cffc AS |
1317 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1318 | ||
1319 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1320 | } | |
1321 | ||
0bc40be8 | 1322 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d AS |
1323 | { |
1324 | int ret; | |
1325 | ||
d37cd8a8 | 1326 | engine->wa_ctx.obj = i915_gem_object_create(engine->dev, |
0bc40be8 | 1327 | PAGE_ALIGN(size)); |
fe3db79b | 1328 | if (IS_ERR(engine->wa_ctx.obj)) { |
17ee950d | 1329 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); |
fe3db79b CW |
1330 | ret = PTR_ERR(engine->wa_ctx.obj); |
1331 | engine->wa_ctx.obj = NULL; | |
1332 | return ret; | |
17ee950d AS |
1333 | } |
1334 | ||
0bc40be8 | 1335 | ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0); |
17ee950d AS |
1336 | if (ret) { |
1337 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1338 | ret); | |
0bc40be8 | 1339 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); |
17ee950d AS |
1340 | return ret; |
1341 | } | |
1342 | ||
1343 | return 0; | |
1344 | } | |
1345 | ||
0bc40be8 | 1346 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1347 | { |
0bc40be8 TU |
1348 | if (engine->wa_ctx.obj) { |
1349 | i915_gem_object_ggtt_unpin(engine->wa_ctx.obj); | |
1350 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); | |
1351 | engine->wa_ctx.obj = NULL; | |
17ee950d AS |
1352 | } |
1353 | } | |
1354 | ||
0bc40be8 | 1355 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d AS |
1356 | { |
1357 | int ret; | |
1358 | uint32_t *batch; | |
1359 | uint32_t offset; | |
1360 | struct page *page; | |
0bc40be8 | 1361 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d | 1362 | |
0bc40be8 | 1363 | WARN_ON(engine->id != RCS); |
17ee950d | 1364 | |
5e60d790 | 1365 | /* update this when WA for higher Gen are added */ |
0bc40be8 | 1366 | if (INTEL_INFO(engine->dev)->gen > 9) { |
0504cffc | 1367 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
0bc40be8 | 1368 | INTEL_INFO(engine->dev)->gen); |
5e60d790 | 1369 | return 0; |
0504cffc | 1370 | } |
5e60d790 | 1371 | |
c4db7599 | 1372 | /* some WA perform writes to scratch page, ensure it is valid */ |
0bc40be8 TU |
1373 | if (engine->scratch.obj == NULL) { |
1374 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); | |
c4db7599 AS |
1375 | return -EINVAL; |
1376 | } | |
1377 | ||
0bc40be8 | 1378 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1379 | if (ret) { |
1380 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1381 | return ret; | |
1382 | } | |
1383 | ||
033908ae | 1384 | page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0); |
17ee950d AS |
1385 | batch = kmap_atomic(page); |
1386 | offset = 0; | |
1387 | ||
0bc40be8 TU |
1388 | if (INTEL_INFO(engine->dev)->gen == 8) { |
1389 | ret = gen8_init_indirectctx_bb(engine, | |
17ee950d AS |
1390 | &wa_ctx->indirect_ctx, |
1391 | batch, | |
1392 | &offset); | |
1393 | if (ret) | |
1394 | goto out; | |
1395 | ||
0bc40be8 | 1396 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1397 | &wa_ctx->per_ctx, |
1398 | batch, | |
1399 | &offset); | |
1400 | if (ret) | |
1401 | goto out; | |
0bc40be8 TU |
1402 | } else if (INTEL_INFO(engine->dev)->gen == 9) { |
1403 | ret = gen9_init_indirectctx_bb(engine, | |
0504cffc AS |
1404 | &wa_ctx->indirect_ctx, |
1405 | batch, | |
1406 | &offset); | |
1407 | if (ret) | |
1408 | goto out; | |
1409 | ||
0bc40be8 | 1410 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1411 | &wa_ctx->per_ctx, |
1412 | batch, | |
1413 | &offset); | |
1414 | if (ret) | |
1415 | goto out; | |
17ee950d AS |
1416 | } |
1417 | ||
1418 | out: | |
1419 | kunmap_atomic(batch); | |
1420 | if (ret) | |
0bc40be8 | 1421 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1422 | |
1423 | return ret; | |
1424 | } | |
1425 | ||
04794adb TU |
1426 | static void lrc_init_hws(struct intel_engine_cs *engine) |
1427 | { | |
1428 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
1429 | ||
1430 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), | |
1431 | (u32)engine->status_page.gfx_addr); | |
1432 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
1433 | } | |
1434 | ||
0bc40be8 | 1435 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1436 | { |
0bc40be8 | 1437 | struct drm_device *dev = engine->dev; |
9b1136d5 | 1438 | struct drm_i915_private *dev_priv = dev->dev_private; |
c6a2ac71 | 1439 | unsigned int next_context_status_buffer_hw; |
9b1136d5 | 1440 | |
04794adb | 1441 | lrc_init_hws(engine); |
e84fe803 | 1442 | |
0bc40be8 TU |
1443 | I915_WRITE_IMR(engine, |
1444 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1445 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
73d477f6 | 1446 | |
0bc40be8 | 1447 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1448 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1449 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
0bc40be8 | 1450 | POSTING_READ(RING_MODE_GEN7(engine)); |
dfc53c5e MT |
1451 | |
1452 | /* | |
1453 | * Instead of resetting the Context Status Buffer (CSB) read pointer to | |
1454 | * zero, we need to read the write pointer from hardware and use its | |
1455 | * value because "this register is power context save restored". | |
1456 | * Effectively, these states have been observed: | |
1457 | * | |
1458 | * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | | |
1459 | * BDW | CSB regs not reset | CSB regs reset | | |
1460 | * CHT | CSB regs not reset | CSB regs not reset | | |
5590a5f0 BW |
1461 | * SKL | ? | ? | |
1462 | * BXT | ? | ? | | |
dfc53c5e | 1463 | */ |
5590a5f0 | 1464 | next_context_status_buffer_hw = |
0bc40be8 | 1465 | GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))); |
dfc53c5e MT |
1466 | |
1467 | /* | |
1468 | * When the CSB registers are reset (also after power-up / gpu reset), | |
1469 | * CSB write pointer is set to all 1's, which is not valid, use '5' in | |
1470 | * this special case, so the first element read is CSB[0]. | |
1471 | */ | |
1472 | if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) | |
1473 | next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); | |
1474 | ||
0bc40be8 TU |
1475 | engine->next_context_status_buffer = next_context_status_buffer_hw; |
1476 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); | |
9b1136d5 | 1477 | |
fc0768ce | 1478 | intel_engine_init_hangcheck(engine); |
9b1136d5 | 1479 | |
0ccdacf6 | 1480 | return intel_mocs_init_engine(engine); |
9b1136d5 OM |
1481 | } |
1482 | ||
0bc40be8 | 1483 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1484 | { |
0bc40be8 | 1485 | struct drm_device *dev = engine->dev; |
9b1136d5 OM |
1486 | struct drm_i915_private *dev_priv = dev->dev_private; |
1487 | int ret; | |
1488 | ||
0bc40be8 | 1489 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1490 | if (ret) |
1491 | return ret; | |
1492 | ||
1493 | /* We need to disable the AsyncFlip performance optimisations in order | |
1494 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1495 | * programmed to '1' on all products. | |
1496 | * | |
1497 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1498 | */ | |
1499 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1500 | ||
9b1136d5 OM |
1501 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1502 | ||
0bc40be8 | 1503 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1504 | } |
1505 | ||
0bc40be8 | 1506 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1507 | { |
1508 | int ret; | |
1509 | ||
0bc40be8 | 1510 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1511 | if (ret) |
1512 | return ret; | |
1513 | ||
0bc40be8 | 1514 | return init_workarounds_ring(engine); |
82ef822e DL |
1515 | } |
1516 | ||
7a01a0a2 MT |
1517 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1518 | { | |
1519 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1520 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1521 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
1522 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1523 | int i, ret; | |
1524 | ||
987046ad | 1525 | ret = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
7a01a0a2 MT |
1526 | if (ret) |
1527 | return ret; | |
1528 | ||
1529 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1530 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1531 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1532 | ||
e2f80391 TU |
1533 | intel_logical_ring_emit_reg(ringbuf, |
1534 | GEN8_RING_PDP_UDW(engine, i)); | |
7a01a0a2 | 1535 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); |
e2f80391 TU |
1536 | intel_logical_ring_emit_reg(ringbuf, |
1537 | GEN8_RING_PDP_LDW(engine, i)); | |
7a01a0a2 MT |
1538 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); |
1539 | } | |
1540 | ||
1541 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1542 | intel_logical_ring_advance(ringbuf); | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
be795fc1 | 1547 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1548 | u64 offset, unsigned dispatch_flags) |
15648585 | 1549 | { |
be795fc1 | 1550 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1551 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1552 | int ret; |
1553 | ||
7a01a0a2 MT |
1554 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1555 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1556 | * but we can't. Force Restore would be a second option, but | |
1557 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1558 | * not idle). PML4 is allocated during ppgtt init so this is |
1559 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1560 | if (req->ctx->ppgtt && |
666796da | 1561 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 ZL |
1562 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
1563 | !intel_vgpu_active(req->i915->dev)) { | |
2dba3239 MT |
1564 | ret = intel_logical_ring_emit_pdps(req); |
1565 | if (ret) | |
1566 | return ret; | |
1567 | } | |
7a01a0a2 | 1568 | |
666796da | 1569 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1570 | } |
1571 | ||
987046ad | 1572 | ret = intel_ring_begin(req, 4); |
15648585 OM |
1573 | if (ret) |
1574 | return ret; | |
1575 | ||
1576 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1577 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1578 | (ppgtt<<8) | | |
1579 | (dispatch_flags & I915_DISPATCH_RS ? | |
1580 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1581 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1582 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1583 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1584 | intel_logical_ring_advance(ringbuf); | |
1585 | ||
1586 | return 0; | |
1587 | } | |
1588 | ||
0bc40be8 | 1589 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine) |
73d477f6 | 1590 | { |
0bc40be8 | 1591 | struct drm_device *dev = engine->dev; |
73d477f6 OM |
1592 | struct drm_i915_private *dev_priv = dev->dev_private; |
1593 | unsigned long flags; | |
1594 | ||
7cd512f1 | 1595 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1596 | return false; |
1597 | ||
1598 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1599 | if (engine->irq_refcount++ == 0) { |
1600 | I915_WRITE_IMR(engine, | |
1601 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1602 | POSTING_READ(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1603 | } |
1604 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1605 | ||
1606 | return true; | |
1607 | } | |
1608 | ||
0bc40be8 | 1609 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine) |
73d477f6 | 1610 | { |
0bc40be8 | 1611 | struct drm_device *dev = engine->dev; |
73d477f6 OM |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; |
1613 | unsigned long flags; | |
1614 | ||
1615 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1616 | if (--engine->irq_refcount == 0) { |
1617 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
1618 | POSTING_READ(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1619 | } |
1620 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1621 | } | |
1622 | ||
7deb4d39 | 1623 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1624 | u32 invalidate_domains, |
1625 | u32 unused) | |
1626 | { | |
7deb4d39 | 1627 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1628 | struct intel_engine_cs *engine = ringbuf->engine; |
e2f80391 | 1629 | struct drm_device *dev = engine->dev; |
4712274c OM |
1630 | struct drm_i915_private *dev_priv = dev->dev_private; |
1631 | uint32_t cmd; | |
1632 | int ret; | |
1633 | ||
987046ad | 1634 | ret = intel_ring_begin(request, 4); |
4712274c OM |
1635 | if (ret) |
1636 | return ret; | |
1637 | ||
1638 | cmd = MI_FLUSH_DW + 1; | |
1639 | ||
f0a1fb10 CW |
1640 | /* We always require a command barrier so that subsequent |
1641 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1642 | * wrt the contents of the write cache being flushed to memory | |
1643 | * (and thus being coherent from the CPU). | |
1644 | */ | |
1645 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1646 | ||
1647 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1648 | cmd |= MI_INVALIDATE_TLB; | |
4a570db5 | 1649 | if (engine == &dev_priv->engine[VCS]) |
f0a1fb10 | 1650 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1651 | } |
1652 | ||
1653 | intel_logical_ring_emit(ringbuf, cmd); | |
1654 | intel_logical_ring_emit(ringbuf, | |
1655 | I915_GEM_HWS_SCRATCH_ADDR | | |
1656 | MI_FLUSH_DW_USE_GTT); | |
1657 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1658 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1659 | intel_logical_ring_advance(ringbuf); | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
7deb4d39 | 1664 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1665 | u32 invalidate_domains, |
1666 | u32 flush_domains) | |
1667 | { | |
7deb4d39 | 1668 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1669 | struct intel_engine_cs *engine = ringbuf->engine; |
e2f80391 | 1670 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
1a5a9ce7 | 1671 | bool vf_flush_wa = false; |
4712274c OM |
1672 | u32 flags = 0; |
1673 | int ret; | |
1674 | ||
1675 | flags |= PIPE_CONTROL_CS_STALL; | |
1676 | ||
1677 | if (flush_domains) { | |
1678 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1679 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1680 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1681 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1682 | } |
1683 | ||
1684 | if (invalidate_domains) { | |
1685 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1686 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1687 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1688 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1689 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1690 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1691 | flags |= PIPE_CONTROL_QW_WRITE; | |
1692 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1693 | |
1a5a9ce7 BW |
1694 | /* |
1695 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1696 | * pipe control. | |
1697 | */ | |
e2f80391 | 1698 | if (IS_GEN9(engine->dev)) |
1a5a9ce7 BW |
1699 | vf_flush_wa = true; |
1700 | } | |
9647ff36 | 1701 | |
987046ad | 1702 | ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1703 | if (ret) |
1704 | return ret; | |
1705 | ||
9647ff36 ID |
1706 | if (vf_flush_wa) { |
1707 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1708 | intel_logical_ring_emit(ringbuf, 0); | |
1709 | intel_logical_ring_emit(ringbuf, 0); | |
1710 | intel_logical_ring_emit(ringbuf, 0); | |
1711 | intel_logical_ring_emit(ringbuf, 0); | |
1712 | intel_logical_ring_emit(ringbuf, 0); | |
1713 | } | |
1714 | ||
4712274c OM |
1715 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1716 | intel_logical_ring_emit(ringbuf, flags); | |
1717 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1718 | intel_logical_ring_emit(ringbuf, 0); | |
1719 | intel_logical_ring_emit(ringbuf, 0); | |
1720 | intel_logical_ring_emit(ringbuf, 0); | |
1721 | intel_logical_ring_advance(ringbuf); | |
1722 | ||
1723 | return 0; | |
1724 | } | |
1725 | ||
c04e0f3b | 1726 | static u32 gen8_get_seqno(struct intel_engine_cs *engine) |
e94e37ad | 1727 | { |
0bc40be8 | 1728 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
e94e37ad OM |
1729 | } |
1730 | ||
0bc40be8 | 1731 | static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
e94e37ad | 1732 | { |
0bc40be8 | 1733 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
e94e37ad OM |
1734 | } |
1735 | ||
c04e0f3b | 1736 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
319404df | 1737 | { |
319404df ID |
1738 | /* |
1739 | * On BXT A steppings there is a HW coherency issue whereby the | |
1740 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1741 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1742 | * clflushing the corresponding cacheline whenever the caller wants | |
1743 | * the coherency to be guaranteed. Note that this cacheline is known | |
1744 | * to be clean at this point, since we only write it in | |
1745 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1746 | * this clflush in practice becomes an invalidate operation. | |
1747 | */ | |
c04e0f3b | 1748 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1749 | } |
1750 | ||
0bc40be8 | 1751 | static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
319404df | 1752 | { |
0bc40be8 | 1753 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
319404df ID |
1754 | |
1755 | /* See bxt_a_get_seqno() explaining the reason for the clflush. */ | |
0bc40be8 | 1756 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1757 | } |
1758 | ||
7c17d377 CW |
1759 | /* |
1760 | * Reserve space for 2 NOOPs at the end of each request to be | |
1761 | * used as a workaround for not being allowed to do lite | |
1762 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1763 | */ | |
1764 | #define WA_TAIL_DWORDS 2 | |
1765 | ||
1766 | static inline u32 hws_seqno_address(struct intel_engine_cs *engine) | |
1767 | { | |
1768 | return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR; | |
1769 | } | |
1770 | ||
c4e76638 | 1771 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1772 | { |
c4e76638 | 1773 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1774 | int ret; |
1775 | ||
987046ad | 1776 | ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS); |
4da46e1e OM |
1777 | if (ret) |
1778 | return ret; | |
1779 | ||
7c17d377 CW |
1780 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1781 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1782 | |
4da46e1e | 1783 | intel_logical_ring_emit(ringbuf, |
7c17d377 CW |
1784 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
1785 | intel_logical_ring_emit(ringbuf, | |
4a570db5 | 1786 | hws_seqno_address(request->engine) | |
7c17d377 | 1787 | MI_FLUSH_DW_USE_GTT); |
4da46e1e | 1788 | intel_logical_ring_emit(ringbuf, 0); |
c4e76638 | 1789 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1790 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1791 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
7c17d377 CW |
1792 | return intel_logical_ring_advance_and_submit(request); |
1793 | } | |
4da46e1e | 1794 | |
7c17d377 CW |
1795 | static int gen8_emit_request_render(struct drm_i915_gem_request *request) |
1796 | { | |
1797 | struct intel_ringbuffer *ringbuf = request->ringbuf; | |
1798 | int ret; | |
53292cdb | 1799 | |
987046ad | 1800 | ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS); |
7c17d377 CW |
1801 | if (ret) |
1802 | return ret; | |
1803 | ||
ce81a65c MW |
1804 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1805 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1806 | ||
7c17d377 CW |
1807 | /* w/a for post sync ops following a GPGPU operation we |
1808 | * need a prior CS_STALL, which is emitted by the flush | |
1809 | * following the batch. | |
1810 | */ | |
ce81a65c | 1811 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
7c17d377 CW |
1812 | intel_logical_ring_emit(ringbuf, |
1813 | (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1814 | PIPE_CONTROL_CS_STALL | | |
1815 | PIPE_CONTROL_QW_WRITE)); | |
4a570db5 | 1816 | intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine)); |
7c17d377 CW |
1817 | intel_logical_ring_emit(ringbuf, 0); |
1818 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); | |
ce81a65c MW |
1819 | /* We're thrashing one dword of HWS. */ |
1820 | intel_logical_ring_emit(ringbuf, 0); | |
7c17d377 | 1821 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
ce81a65c | 1822 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
7c17d377 | 1823 | return intel_logical_ring_advance_and_submit(request); |
4da46e1e OM |
1824 | } |
1825 | ||
be01363f | 1826 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1827 | { |
cef437ad | 1828 | struct render_state so; |
cef437ad DL |
1829 | int ret; |
1830 | ||
4a570db5 | 1831 | ret = i915_gem_render_state_prepare(req->engine, &so); |
cef437ad DL |
1832 | if (ret) |
1833 | return ret; | |
1834 | ||
1835 | if (so.rodata == NULL) | |
1836 | return 0; | |
1837 | ||
4a570db5 | 1838 | ret = req->engine->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1839 | I915_DISPATCH_SECURE); |
cef437ad DL |
1840 | if (ret) |
1841 | goto out; | |
1842 | ||
4a570db5 | 1843 | ret = req->engine->emit_bb_start(req, |
84e81020 AS |
1844 | (so.ggtt_offset + so.aux_batch_offset), |
1845 | I915_DISPATCH_SECURE); | |
1846 | if (ret) | |
1847 | goto out; | |
1848 | ||
b2af0376 | 1849 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1850 | |
cef437ad DL |
1851 | out: |
1852 | i915_gem_render_state_fini(&so); | |
1853 | return ret; | |
1854 | } | |
1855 | ||
8753181e | 1856 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1857 | { |
1858 | int ret; | |
1859 | ||
e2be4faf | 1860 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1861 | if (ret) |
1862 | return ret; | |
1863 | ||
3bbaba0c PA |
1864 | ret = intel_rcs_context_init_mocs(req); |
1865 | /* | |
1866 | * Failing to program the MOCS is non-fatal.The system will not | |
1867 | * run at peak performance. So generate an error and carry on. | |
1868 | */ | |
1869 | if (ret) | |
1870 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1871 | ||
be01363f | 1872 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1873 | } |
1874 | ||
73e4d07f OM |
1875 | /** |
1876 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1877 | * | |
1878 | * @ring: Engine Command Streamer. | |
1879 | * | |
1880 | */ | |
0bc40be8 | 1881 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1882 | { |
6402c330 | 1883 | struct drm_i915_private *dev_priv; |
9832b9da | 1884 | |
117897f4 | 1885 | if (!intel_engine_initialized(engine)) |
48d82387 OM |
1886 | return; |
1887 | ||
27af5eea TU |
1888 | /* |
1889 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1890 | * so this is just for documentation. | |
1891 | */ | |
1892 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1893 | tasklet_kill(&engine->irq_tasklet); | |
1894 | ||
0bc40be8 | 1895 | dev_priv = engine->dev->dev_private; |
6402c330 | 1896 | |
0bc40be8 TU |
1897 | if (engine->buffer) { |
1898 | intel_logical_ring_stop(engine); | |
1899 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
b0366a54 | 1900 | } |
48d82387 | 1901 | |
0bc40be8 TU |
1902 | if (engine->cleanup) |
1903 | engine->cleanup(engine); | |
48d82387 | 1904 | |
0bc40be8 TU |
1905 | i915_cmd_parser_fini_ring(engine); |
1906 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
48d82387 | 1907 | |
0bc40be8 | 1908 | if (engine->status_page.obj) { |
7d774cac | 1909 | i915_gem_object_unpin_map(engine->status_page.obj); |
0bc40be8 | 1910 | engine->status_page.obj = NULL; |
48d82387 | 1911 | } |
24f1d3cc | 1912 | intel_lr_context_unpin(dev_priv->kernel_context, engine); |
17ee950d | 1913 | |
0bc40be8 TU |
1914 | engine->idle_lite_restore_wa = 0; |
1915 | engine->disable_lite_restore_wa = false; | |
1916 | engine->ctx_desc_template = 0; | |
ca82580c | 1917 | |
0bc40be8 TU |
1918 | lrc_destroy_wa_ctx_obj(engine); |
1919 | engine->dev = NULL; | |
454afebd OM |
1920 | } |
1921 | ||
c9cacf93 TU |
1922 | static void |
1923 | logical_ring_default_vfuncs(struct drm_device *dev, | |
0bc40be8 | 1924 | struct intel_engine_cs *engine) |
c9cacf93 TU |
1925 | { |
1926 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 TU |
1927 | engine->init_hw = gen8_init_common_ring; |
1928 | engine->emit_request = gen8_emit_request; | |
1929 | engine->emit_flush = gen8_emit_flush; | |
1930 | engine->irq_get = gen8_logical_ring_get_irq; | |
1931 | engine->irq_put = gen8_logical_ring_put_irq; | |
1932 | engine->emit_bb_start = gen8_emit_bb_start; | |
c04e0f3b CW |
1933 | engine->get_seqno = gen8_get_seqno; |
1934 | engine->set_seqno = gen8_set_seqno; | |
c9cacf93 | 1935 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
c04e0f3b | 1936 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
0bc40be8 | 1937 | engine->set_seqno = bxt_a_set_seqno; |
c9cacf93 TU |
1938 | } |
1939 | } | |
1940 | ||
d9f3af96 | 1941 | static inline void |
0bc40be8 | 1942 | logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) |
d9f3af96 | 1943 | { |
0bc40be8 TU |
1944 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1945 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1946 | } |
1947 | ||
7d774cac | 1948 | static int |
04794adb TU |
1949 | lrc_setup_hws(struct intel_engine_cs *engine, |
1950 | struct drm_i915_gem_object *dctx_obj) | |
1951 | { | |
7d774cac | 1952 | void *hws; |
04794adb TU |
1953 | |
1954 | /* The HWSP is part of the default context object in LRC mode. */ | |
1955 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) + | |
1956 | LRC_PPHWSP_PN * PAGE_SIZE; | |
7d774cac TU |
1957 | hws = i915_gem_object_pin_map(dctx_obj); |
1958 | if (IS_ERR(hws)) | |
1959 | return PTR_ERR(hws); | |
1960 | engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE; | |
04794adb | 1961 | engine->status_page.obj = dctx_obj; |
7d774cac TU |
1962 | |
1963 | return 0; | |
04794adb TU |
1964 | } |
1965 | ||
c9cacf93 | 1966 | static int |
0bc40be8 | 1967 | logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) |
454afebd | 1968 | { |
3756685a TU |
1969 | struct drm_i915_private *dev_priv = to_i915(dev); |
1970 | struct intel_context *dctx = dev_priv->kernel_context; | |
1971 | enum forcewake_domains fw_domains; | |
48d82387 | 1972 | int ret; |
48d82387 OM |
1973 | |
1974 | /* Intentionally left blank. */ | |
0bc40be8 | 1975 | engine->buffer = NULL; |
48d82387 | 1976 | |
0bc40be8 TU |
1977 | engine->dev = dev; |
1978 | INIT_LIST_HEAD(&engine->active_list); | |
1979 | INIT_LIST_HEAD(&engine->request_list); | |
1980 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
1981 | init_waitqueue_head(&engine->irq_queue); | |
48d82387 | 1982 | |
0bc40be8 TU |
1983 | INIT_LIST_HEAD(&engine->buffers); |
1984 | INIT_LIST_HEAD(&engine->execlist_queue); | |
1985 | INIT_LIST_HEAD(&engine->execlist_retired_req_list); | |
1986 | spin_lock_init(&engine->execlist_lock); | |
acdd884a | 1987 | |
27af5eea TU |
1988 | tasklet_init(&engine->irq_tasklet, |
1989 | intel_lrc_irq_handler, (unsigned long)engine); | |
1990 | ||
0bc40be8 | 1991 | logical_ring_init_platform_invariants(engine); |
ca82580c | 1992 | |
3756685a TU |
1993 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, |
1994 | RING_ELSP(engine), | |
1995 | FW_REG_WRITE); | |
1996 | ||
1997 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1998 | RING_CONTEXT_STATUS_PTR(engine), | |
1999 | FW_REG_READ | FW_REG_WRITE); | |
2000 | ||
2001 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
2002 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
2003 | FW_REG_READ); | |
2004 | ||
2005 | engine->fw_domains = fw_domains; | |
2006 | ||
0bc40be8 | 2007 | ret = i915_cmd_parser_init_ring(engine); |
48d82387 | 2008 | if (ret) |
b0366a54 | 2009 | goto error; |
48d82387 | 2010 | |
0bc40be8 | 2011 | ret = intel_lr_context_deferred_alloc(dctx, engine); |
e84fe803 | 2012 | if (ret) |
b0366a54 | 2013 | goto error; |
e84fe803 NH |
2014 | |
2015 | /* As this is the default context, always pin it */ | |
24f1d3cc | 2016 | ret = intel_lr_context_pin(dctx, engine); |
e84fe803 | 2017 | if (ret) { |
24f1d3cc CW |
2018 | DRM_ERROR("Failed to pin context for %s: %d\n", |
2019 | engine->name, ret); | |
b0366a54 | 2020 | goto error; |
e84fe803 | 2021 | } |
564ddb2f | 2022 | |
04794adb | 2023 | /* And setup the hardware status page. */ |
7d774cac TU |
2024 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); |
2025 | if (ret) { | |
2026 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
2027 | goto error; | |
2028 | } | |
04794adb | 2029 | |
b0366a54 DG |
2030 | return 0; |
2031 | ||
2032 | error: | |
0bc40be8 | 2033 | intel_logical_ring_cleanup(engine); |
564ddb2f | 2034 | return ret; |
454afebd OM |
2035 | } |
2036 | ||
2037 | static int logical_render_ring_init(struct drm_device *dev) | |
2038 | { | |
2039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2040 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
99be1dfe | 2041 | int ret; |
454afebd | 2042 | |
e2f80391 TU |
2043 | engine->name = "render ring"; |
2044 | engine->id = RCS; | |
2045 | engine->exec_id = I915_EXEC_RENDER; | |
2046 | engine->guc_id = GUC_RENDER_ENGINE; | |
2047 | engine->mmio_base = RENDER_RING_BASE; | |
d9f3af96 | 2048 | |
e2f80391 | 2049 | logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT); |
73d477f6 | 2050 | if (HAS_L3_DPF(dev)) |
e2f80391 | 2051 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
454afebd | 2052 | |
e2f80391 | 2053 | logical_ring_default_vfuncs(dev, engine); |
c9cacf93 TU |
2054 | |
2055 | /* Override some for render ring. */ | |
82ef822e | 2056 | if (INTEL_INFO(dev)->gen >= 9) |
e2f80391 | 2057 | engine->init_hw = gen9_init_render_ring; |
82ef822e | 2058 | else |
e2f80391 TU |
2059 | engine->init_hw = gen8_init_render_ring; |
2060 | engine->init_context = gen8_init_rcs_context; | |
2061 | engine->cleanup = intel_fini_pipe_control; | |
2062 | engine->emit_flush = gen8_emit_flush_render; | |
2063 | engine->emit_request = gen8_emit_request_render; | |
9b1136d5 | 2064 | |
e2f80391 | 2065 | engine->dev = dev; |
c4db7599 | 2066 | |
e2f80391 | 2067 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2068 | if (ret) |
2069 | return ret; | |
2070 | ||
e2f80391 | 2071 | ret = intel_init_workaround_bb(engine); |
17ee950d AS |
2072 | if (ret) { |
2073 | /* | |
2074 | * We continue even if we fail to initialize WA batch | |
2075 | * because we only expect rare glitches but nothing | |
2076 | * critical to prevent us from using GPU | |
2077 | */ | |
2078 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
2079 | ret); | |
2080 | } | |
2081 | ||
e2f80391 | 2082 | ret = logical_ring_init(dev, engine); |
c4db7599 | 2083 | if (ret) { |
e2f80391 | 2084 | lrc_destroy_wa_ctx_obj(engine); |
c4db7599 | 2085 | } |
17ee950d AS |
2086 | |
2087 | return ret; | |
454afebd OM |
2088 | } |
2089 | ||
2090 | static int logical_bsd_ring_init(struct drm_device *dev) | |
2091 | { | |
2092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2093 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
454afebd | 2094 | |
e2f80391 TU |
2095 | engine->name = "bsd ring"; |
2096 | engine->id = VCS; | |
2097 | engine->exec_id = I915_EXEC_BSD; | |
2098 | engine->guc_id = GUC_VIDEO_ENGINE; | |
2099 | engine->mmio_base = GEN6_BSD_RING_BASE; | |
454afebd | 2100 | |
e2f80391 TU |
2101 | logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT); |
2102 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2103 | |
e2f80391 | 2104 | return logical_ring_init(dev, engine); |
454afebd OM |
2105 | } |
2106 | ||
2107 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
2108 | { | |
2109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2110 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
454afebd | 2111 | |
e2f80391 TU |
2112 | engine->name = "bsd2 ring"; |
2113 | engine->id = VCS2; | |
2114 | engine->exec_id = I915_EXEC_BSD; | |
2115 | engine->guc_id = GUC_VIDEO_ENGINE2; | |
2116 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
454afebd | 2117 | |
e2f80391 TU |
2118 | logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT); |
2119 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2120 | |
e2f80391 | 2121 | return logical_ring_init(dev, engine); |
454afebd OM |
2122 | } |
2123 | ||
2124 | static int logical_blt_ring_init(struct drm_device *dev) | |
2125 | { | |
2126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2127 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
454afebd | 2128 | |
e2f80391 TU |
2129 | engine->name = "blitter ring"; |
2130 | engine->id = BCS; | |
2131 | engine->exec_id = I915_EXEC_BLT; | |
2132 | engine->guc_id = GUC_BLITTER_ENGINE; | |
2133 | engine->mmio_base = BLT_RING_BASE; | |
454afebd | 2134 | |
e2f80391 TU |
2135 | logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT); |
2136 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2137 | |
e2f80391 | 2138 | return logical_ring_init(dev, engine); |
454afebd OM |
2139 | } |
2140 | ||
2141 | static int logical_vebox_ring_init(struct drm_device *dev) | |
2142 | { | |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2144 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
454afebd | 2145 | |
e2f80391 TU |
2146 | engine->name = "video enhancement ring"; |
2147 | engine->id = VECS; | |
2148 | engine->exec_id = I915_EXEC_VEBOX; | |
2149 | engine->guc_id = GUC_VIDEOENHANCE_ENGINE; | |
2150 | engine->mmio_base = VEBOX_RING_BASE; | |
454afebd | 2151 | |
e2f80391 TU |
2152 | logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT); |
2153 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2154 | |
e2f80391 | 2155 | return logical_ring_init(dev, engine); |
454afebd OM |
2156 | } |
2157 | ||
73e4d07f OM |
2158 | /** |
2159 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
2160 | * @dev: DRM device. | |
2161 | * | |
2162 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
117897f4 | 2163 | * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for |
73e4d07f OM |
2164 | * those engines that are present in the hardware. |
2165 | * | |
2166 | * Return: non-zero if the initialization failed. | |
2167 | */ | |
454afebd OM |
2168 | int intel_logical_rings_init(struct drm_device *dev) |
2169 | { | |
2170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2171 | int ret; | |
2172 | ||
2173 | ret = logical_render_ring_init(dev); | |
2174 | if (ret) | |
2175 | return ret; | |
2176 | ||
2177 | if (HAS_BSD(dev)) { | |
2178 | ret = logical_bsd_ring_init(dev); | |
2179 | if (ret) | |
2180 | goto cleanup_render_ring; | |
2181 | } | |
2182 | ||
2183 | if (HAS_BLT(dev)) { | |
2184 | ret = logical_blt_ring_init(dev); | |
2185 | if (ret) | |
2186 | goto cleanup_bsd_ring; | |
2187 | } | |
2188 | ||
2189 | if (HAS_VEBOX(dev)) { | |
2190 | ret = logical_vebox_ring_init(dev); | |
2191 | if (ret) | |
2192 | goto cleanup_blt_ring; | |
2193 | } | |
2194 | ||
2195 | if (HAS_BSD2(dev)) { | |
2196 | ret = logical_bsd2_ring_init(dev); | |
2197 | if (ret) | |
2198 | goto cleanup_vebox_ring; | |
2199 | } | |
2200 | ||
454afebd OM |
2201 | return 0; |
2202 | ||
454afebd | 2203 | cleanup_vebox_ring: |
4a570db5 | 2204 | intel_logical_ring_cleanup(&dev_priv->engine[VECS]); |
454afebd | 2205 | cleanup_blt_ring: |
4a570db5 | 2206 | intel_logical_ring_cleanup(&dev_priv->engine[BCS]); |
454afebd | 2207 | cleanup_bsd_ring: |
4a570db5 | 2208 | intel_logical_ring_cleanup(&dev_priv->engine[VCS]); |
454afebd | 2209 | cleanup_render_ring: |
4a570db5 | 2210 | intel_logical_ring_cleanup(&dev_priv->engine[RCS]); |
454afebd OM |
2211 | |
2212 | return ret; | |
2213 | } | |
2214 | ||
0cea6502 JM |
2215 | static u32 |
2216 | make_rpcs(struct drm_device *dev) | |
2217 | { | |
2218 | u32 rpcs = 0; | |
2219 | ||
2220 | /* | |
2221 | * No explicit RPCS request is needed to ensure full | |
2222 | * slice/subslice/EU enablement prior to Gen9. | |
2223 | */ | |
2224 | if (INTEL_INFO(dev)->gen < 9) | |
2225 | return 0; | |
2226 | ||
2227 | /* | |
2228 | * Starting in Gen9, render power gating can leave | |
2229 | * slice/subslice/EU in a partially enabled state. We | |
2230 | * must make an explicit request through RPCS for full | |
2231 | * enablement. | |
2232 | */ | |
2233 | if (INTEL_INFO(dev)->has_slice_pg) { | |
2234 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
2235 | rpcs |= INTEL_INFO(dev)->slice_total << | |
2236 | GEN8_RPCS_S_CNT_SHIFT; | |
2237 | rpcs |= GEN8_RPCS_ENABLE; | |
2238 | } | |
2239 | ||
2240 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
2241 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
2242 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
2243 | GEN8_RPCS_SS_CNT_SHIFT; | |
2244 | rpcs |= GEN8_RPCS_ENABLE; | |
2245 | } | |
2246 | ||
2247 | if (INTEL_INFO(dev)->has_eu_pg) { | |
2248 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2249 | GEN8_RPCS_EU_MIN_SHIFT; | |
2250 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2251 | GEN8_RPCS_EU_MAX_SHIFT; | |
2252 | rpcs |= GEN8_RPCS_ENABLE; | |
2253 | } | |
2254 | ||
2255 | return rpcs; | |
2256 | } | |
2257 | ||
0bc40be8 | 2258 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2259 | { |
2260 | u32 indirect_ctx_offset; | |
2261 | ||
0bc40be8 | 2262 | switch (INTEL_INFO(engine->dev)->gen) { |
71562919 | 2263 | default: |
0bc40be8 | 2264 | MISSING_CASE(INTEL_INFO(engine->dev)->gen); |
71562919 MT |
2265 | /* fall through */ |
2266 | case 9: | |
2267 | indirect_ctx_offset = | |
2268 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2269 | break; | |
2270 | case 8: | |
2271 | indirect_ctx_offset = | |
2272 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2273 | break; | |
2274 | } | |
2275 | ||
2276 | return indirect_ctx_offset; | |
2277 | } | |
2278 | ||
8670d6f9 | 2279 | static int |
7d774cac TU |
2280 | populate_lr_context(struct intel_context *ctx, |
2281 | struct drm_i915_gem_object *ctx_obj, | |
0bc40be8 TU |
2282 | struct intel_engine_cs *engine, |
2283 | struct intel_ringbuffer *ringbuf) | |
8670d6f9 | 2284 | { |
0bc40be8 | 2285 | struct drm_device *dev = engine->dev; |
2d965536 | 2286 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae6c4806 | 2287 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
7d774cac TU |
2288 | void *vaddr; |
2289 | u32 *reg_state; | |
8670d6f9 OM |
2290 | int ret; |
2291 | ||
2d965536 TD |
2292 | if (!ppgtt) |
2293 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2294 | ||
8670d6f9 OM |
2295 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2296 | if (ret) { | |
2297 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2298 | return ret; | |
2299 | } | |
2300 | ||
7d774cac TU |
2301 | vaddr = i915_gem_object_pin_map(ctx_obj); |
2302 | if (IS_ERR(vaddr)) { | |
2303 | ret = PTR_ERR(vaddr); | |
2304 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
8670d6f9 OM |
2305 | return ret; |
2306 | } | |
7d774cac | 2307 | ctx_obj->dirty = true; |
8670d6f9 OM |
2308 | |
2309 | /* The second page of the context object contains some fields which must | |
2310 | * be set up prior to the first execution. */ | |
7d774cac | 2311 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
8670d6f9 OM |
2312 | |
2313 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2314 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2315 | * only for the first context restore: on a subsequent save, the GPU will | |
2316 | * recreate this batchbuffer with new values (including all the missing | |
2317 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 2318 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
2319 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
2320 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
2321 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
2322 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
2323 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
99cf8ea1 MT |
2324 | (HAS_RESOURCE_STREAMER(dev) ? |
2325 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
0bc40be8 TU |
2326 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
2327 | 0); | |
2328 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
2329 | 0); | |
7ba717cf TD |
2330 | /* Ring buffer start address is not known until the buffer is pinned. |
2331 | * It is written to the context image in execlists_update_context() | |
2332 | */ | |
0bc40be8 TU |
2333 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
2334 | RING_START(engine->mmio_base), 0); | |
2335 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
2336 | RING_CTL(engine->mmio_base), | |
0d925ea0 | 2337 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); |
0bc40be8 TU |
2338 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
2339 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
2340 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
2341 | RING_BBADDR(engine->mmio_base), 0); | |
2342 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
2343 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 2344 | RING_BB_PPGTT); |
0bc40be8 TU |
2345 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
2346 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
2347 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
2348 | RING_SBBADDR(engine->mmio_base), 0); | |
2349 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
2350 | RING_SBBSTATE(engine->mmio_base), 0); | |
2351 | if (engine->id == RCS) { | |
2352 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
2353 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
2354 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
2355 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
2356 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2357 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
2358 | if (engine->wa_ctx.obj) { | |
2359 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; | |
17ee950d AS |
2360 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); |
2361 | ||
2362 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2363 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2364 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2365 | ||
2366 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 2367 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
2368 | |
2369 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2370 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2371 | 0x01; | |
2372 | } | |
8670d6f9 | 2373 | } |
0d925ea0 | 2374 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
2375 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
2376 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 2377 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
2378 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
2379 | 0); | |
2380 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
2381 | 0); | |
2382 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
2383 | 0); | |
2384 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2385 | 0); | |
2386 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2387 | 0); | |
2388 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2389 | 0); | |
2390 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2391 | 0); | |
2392 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2393 | 0); | |
d7b2633d | 2394 | |
2dba3239 MT |
2395 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2396 | /* 64b PPGTT (48bit canonical) | |
2397 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2398 | * other PDP Descriptors are ignored. | |
2399 | */ | |
2400 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2401 | } else { | |
2402 | /* 32b PPGTT | |
2403 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2404 | * With dynamic page allocation, PDPs may not be allocated at | |
2405 | * this point. Point the unallocated PDPs to the scratch page | |
2406 | */ | |
c6a2ac71 | 2407 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2408 | } |
2409 | ||
0bc40be8 | 2410 | if (engine->id == RCS) { |
8670d6f9 | 2411 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 VS |
2412 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
2413 | make_rpcs(dev)); | |
8670d6f9 OM |
2414 | } |
2415 | ||
7d774cac | 2416 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2417 | |
2418 | return 0; | |
2419 | } | |
2420 | ||
73e4d07f OM |
2421 | /** |
2422 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2423 | * @ctx: the LR context to free. | |
2424 | * | |
2425 | * The real context freeing is done in i915_gem_context_free: this only | |
2426 | * takes care of the bits that are LRC related: the per-engine backing | |
2427 | * objects and the logical ringbuffer. | |
2428 | */ | |
ede7d42b OM |
2429 | void intel_lr_context_free(struct intel_context *ctx) |
2430 | { | |
8c857917 OM |
2431 | int i; |
2432 | ||
666796da | 2433 | for (i = I915_NUM_ENGINES; --i >= 0; ) { |
e28e404c | 2434 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
8c857917 | 2435 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
84c2377f | 2436 | |
e28e404c DG |
2437 | if (!ctx_obj) |
2438 | continue; | |
dcb4c12a | 2439 | |
e28e404c DG |
2440 | WARN_ON(ctx->engine[i].pin_count); |
2441 | intel_ringbuffer_free(ringbuf); | |
2442 | drm_gem_object_unreference(&ctx_obj->base); | |
8c857917 OM |
2443 | } |
2444 | } | |
2445 | ||
c5d46ee2 DG |
2446 | /** |
2447 | * intel_lr_context_size() - return the size of the context for an engine | |
2448 | * @ring: which engine to find the context size for | |
2449 | * | |
2450 | * Each engine may require a different amount of space for a context image, | |
2451 | * so when allocating (or copying) an image, this function can be used to | |
2452 | * find the right size for the specific engine. | |
2453 | * | |
2454 | * Return: size (in bytes) of an engine-specific context image | |
2455 | * | |
2456 | * Note: this size includes the HWSP, which is part of the context image | |
2457 | * in LRC mode, but does not include the "shared data page" used with | |
2458 | * GuC submission. The caller should account for this if using the GuC. | |
2459 | */ | |
0bc40be8 | 2460 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2461 | { |
2462 | int ret = 0; | |
2463 | ||
0bc40be8 | 2464 | WARN_ON(INTEL_INFO(engine->dev)->gen < 8); |
8c857917 | 2465 | |
0bc40be8 | 2466 | switch (engine->id) { |
8c857917 | 2467 | case RCS: |
0bc40be8 | 2468 | if (INTEL_INFO(engine->dev)->gen >= 9) |
468c6816 MN |
2469 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2470 | else | |
2471 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2472 | break; |
2473 | case VCS: | |
2474 | case BCS: | |
2475 | case VECS: | |
2476 | case VCS2: | |
2477 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2478 | break; | |
2479 | } | |
2480 | ||
2481 | return ret; | |
ede7d42b OM |
2482 | } |
2483 | ||
73e4d07f | 2484 | /** |
e84fe803 | 2485 | * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context |
73e4d07f OM |
2486 | * @ctx: LR context to create. |
2487 | * @ring: engine to be used with the context. | |
2488 | * | |
2489 | * This function can be called more than once, with different engines, if we plan | |
2490 | * to use the context with them. The context backing objects and the ringbuffers | |
2491 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2492 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2493 | * a given ring with the context. | |
2494 | * | |
32197aab | 2495 | * Return: non-zero on error. |
73e4d07f | 2496 | */ |
e84fe803 NH |
2497 | |
2498 | int intel_lr_context_deferred_alloc(struct intel_context *ctx, | |
0bc40be8 | 2499 | struct intel_engine_cs *engine) |
ede7d42b | 2500 | { |
0bc40be8 | 2501 | struct drm_device *dev = engine->dev; |
8c857917 OM |
2502 | struct drm_i915_gem_object *ctx_obj; |
2503 | uint32_t context_size; | |
84c2377f | 2504 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2505 | int ret; |
2506 | ||
ede7d42b | 2507 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
0bc40be8 | 2508 | WARN_ON(ctx->engine[engine->id].state); |
ede7d42b | 2509 | |
0bc40be8 | 2510 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2511 | |
d1675198 AD |
2512 | /* One extra page as the sharing data between driver and GuC */ |
2513 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2514 | ||
d37cd8a8 | 2515 | ctx_obj = i915_gem_object_create(dev, context_size); |
fe3db79b | 2516 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2517 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2518 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2519 | } |
2520 | ||
0bc40be8 | 2521 | ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE); |
01101fa7 CW |
2522 | if (IS_ERR(ringbuf)) { |
2523 | ret = PTR_ERR(ringbuf); | |
e84fe803 | 2524 | goto error_deref_obj; |
8670d6f9 OM |
2525 | } |
2526 | ||
0bc40be8 | 2527 | ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf); |
8670d6f9 OM |
2528 | if (ret) { |
2529 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
e84fe803 | 2530 | goto error_ringbuf; |
84c2377f OM |
2531 | } |
2532 | ||
0bc40be8 TU |
2533 | ctx->engine[engine->id].ringbuf = ringbuf; |
2534 | ctx->engine[engine->id].state = ctx_obj; | |
24f1d3cc | 2535 | ctx->engine[engine->id].initialised = engine->init_context == NULL; |
ede7d42b OM |
2536 | |
2537 | return 0; | |
8670d6f9 | 2538 | |
01101fa7 CW |
2539 | error_ringbuf: |
2540 | intel_ringbuffer_free(ringbuf); | |
e84fe803 | 2541 | error_deref_obj: |
8670d6f9 | 2542 | drm_gem_object_unreference(&ctx_obj->base); |
0bc40be8 TU |
2543 | ctx->engine[engine->id].ringbuf = NULL; |
2544 | ctx->engine[engine->id].state = NULL; | |
8670d6f9 | 2545 | return ret; |
ede7d42b | 2546 | } |
3e5b6f05 | 2547 | |
7d774cac TU |
2548 | void intel_lr_context_reset(struct drm_i915_private *dev_priv, |
2549 | struct intel_context *ctx) | |
3e5b6f05 | 2550 | { |
e2f80391 | 2551 | struct intel_engine_cs *engine; |
3e5b6f05 | 2552 | |
b4ac5afc | 2553 | for_each_engine(engine, dev_priv) { |
3e5b6f05 | 2554 | struct drm_i915_gem_object *ctx_obj = |
e2f80391 | 2555 | ctx->engine[engine->id].state; |
3e5b6f05 | 2556 | struct intel_ringbuffer *ringbuf = |
e2f80391 | 2557 | ctx->engine[engine->id].ringbuf; |
7d774cac | 2558 | void *vaddr; |
3e5b6f05 | 2559 | uint32_t *reg_state; |
3e5b6f05 TD |
2560 | |
2561 | if (!ctx_obj) | |
2562 | continue; | |
2563 | ||
7d774cac TU |
2564 | vaddr = i915_gem_object_pin_map(ctx_obj); |
2565 | if (WARN_ON(IS_ERR(vaddr))) | |
3e5b6f05 | 2566 | continue; |
7d774cac TU |
2567 | |
2568 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; | |
2569 | ctx_obj->dirty = true; | |
3e5b6f05 TD |
2570 | |
2571 | reg_state[CTX_RING_HEAD+1] = 0; | |
2572 | reg_state[CTX_RING_TAIL+1] = 0; | |
2573 | ||
7d774cac | 2574 | i915_gem_object_unpin_map(ctx_obj); |
3e5b6f05 TD |
2575 | |
2576 | ringbuf->head = 0; | |
2577 | ringbuf->tail = 0; | |
2578 | } | |
2579 | } |