Commit | Line | Data |
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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
31 | /* | |
32 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". | |
33 | * These expanded contexts enable a number of new abilities, especially | |
34 | * "Execlists" (also implemented in this file). | |
35 | * | |
36 | * Execlists are the new method by which, on gen8+ hardware, workloads are | |
37 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
38 | */ | |
39 | ||
40 | #include <drm/drmP.h> | |
41 | #include <drm/i915_drm.h> | |
42 | #include "i915_drv.h" | |
127f1003 | 43 | |
8c857917 OM |
44 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
45 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
46 | ||
47 | #define GEN8_LR_CONTEXT_ALIGN 4096 | |
48 | ||
8670d6f9 OM |
49 | #define RING_ELSP(ring) ((ring)->mmio_base+0x230) |
50 | #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) | |
51 | ||
52 | #define CTX_LRI_HEADER_0 0x01 | |
53 | #define CTX_CONTEXT_CONTROL 0x02 | |
54 | #define CTX_RING_HEAD 0x04 | |
55 | #define CTX_RING_TAIL 0x06 | |
56 | #define CTX_RING_BUFFER_START 0x08 | |
57 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
58 | #define CTX_BB_HEAD_U 0x0c | |
59 | #define CTX_BB_HEAD_L 0x0e | |
60 | #define CTX_BB_STATE 0x10 | |
61 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
62 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
63 | #define CTX_SECOND_BB_STATE 0x16 | |
64 | #define CTX_BB_PER_CTX_PTR 0x18 | |
65 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
66 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
67 | #define CTX_LRI_HEADER_1 0x21 | |
68 | #define CTX_CTX_TIMESTAMP 0x22 | |
69 | #define CTX_PDP3_UDW 0x24 | |
70 | #define CTX_PDP3_LDW 0x26 | |
71 | #define CTX_PDP2_UDW 0x28 | |
72 | #define CTX_PDP2_LDW 0x2a | |
73 | #define CTX_PDP1_UDW 0x2c | |
74 | #define CTX_PDP1_LDW 0x2e | |
75 | #define CTX_PDP0_UDW 0x30 | |
76 | #define CTX_PDP0_LDW 0x32 | |
77 | #define CTX_LRI_HEADER_2 0x41 | |
78 | #define CTX_R_PWR_CLK_STATE 0x42 | |
79 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
80 | ||
127f1003 OM |
81 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
82 | { | |
bd84b1e9 DV |
83 | WARN_ON(i915.enable_ppgtt == -1); |
84 | ||
127f1003 OM |
85 | if (enable_execlists == 0) |
86 | return 0; | |
87 | ||
88 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev)) | |
89 | return 1; | |
90 | ||
91 | return 0; | |
92 | } | |
ede7d42b | 93 | |
454afebd OM |
94 | int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
95 | struct intel_engine_cs *ring, | |
96 | struct intel_context *ctx, | |
97 | struct drm_i915_gem_execbuffer2 *args, | |
98 | struct list_head *vmas, | |
99 | struct drm_i915_gem_object *batch_obj, | |
100 | u64 exec_start, u32 flags) | |
101 | { | |
102 | /* TODO */ | |
103 | return 0; | |
104 | } | |
105 | ||
106 | void intel_logical_ring_stop(struct intel_engine_cs *ring) | |
107 | { | |
108 | /* TODO */ | |
109 | } | |
110 | ||
9b1136d5 OM |
111 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
112 | { | |
113 | struct drm_device *dev = ring->dev; | |
114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
115 | ||
116 | I915_WRITE(RING_MODE_GEN7(ring), | |
117 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
118 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
119 | POSTING_READ(RING_MODE_GEN7(ring)); | |
120 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); | |
121 | ||
122 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
128 | { | |
129 | struct drm_device *dev = ring->dev; | |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | int ret; | |
132 | ||
133 | ret = gen8_init_common_ring(ring); | |
134 | if (ret) | |
135 | return ret; | |
136 | ||
137 | /* We need to disable the AsyncFlip performance optimisations in order | |
138 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
139 | * programmed to '1' on all products. | |
140 | * | |
141 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
142 | */ | |
143 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
144 | ||
145 | ret = intel_init_pipe_control(ring); | |
146 | if (ret) | |
147 | return ret; | |
148 | ||
149 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
150 | ||
151 | return ret; | |
152 | } | |
153 | ||
454afebd OM |
154 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
155 | { | |
48d82387 OM |
156 | if (!intel_ring_initialized(ring)) |
157 | return; | |
158 | ||
159 | /* TODO: make sure the ring is stopped */ | |
160 | ring->preallocated_lazy_request = NULL; | |
161 | ring->outstanding_lazy_seqno = 0; | |
162 | ||
163 | if (ring->cleanup) | |
164 | ring->cleanup(ring); | |
165 | ||
166 | i915_cmd_parser_fini_ring(ring); | |
167 | ||
168 | if (ring->status_page.obj) { | |
169 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
170 | ring->status_page.obj = NULL; | |
171 | } | |
454afebd OM |
172 | } |
173 | ||
174 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
175 | { | |
48d82387 OM |
176 | int ret; |
177 | struct intel_context *dctx = ring->default_context; | |
178 | struct drm_i915_gem_object *dctx_obj; | |
179 | ||
180 | /* Intentionally left blank. */ | |
181 | ring->buffer = NULL; | |
182 | ||
183 | ring->dev = dev; | |
184 | INIT_LIST_HEAD(&ring->active_list); | |
185 | INIT_LIST_HEAD(&ring->request_list); | |
186 | init_waitqueue_head(&ring->irq_queue); | |
187 | ||
188 | ret = intel_lr_context_deferred_create(dctx, ring); | |
189 | if (ret) | |
190 | return ret; | |
191 | ||
192 | /* The status page is offset 0 from the context object in LRCs. */ | |
193 | dctx_obj = dctx->engine[ring->id].state; | |
194 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj); | |
195 | ring->status_page.page_addr = kmap(sg_page(dctx_obj->pages->sgl)); | |
196 | if (ring->status_page.page_addr == NULL) | |
197 | return -ENOMEM; | |
198 | ring->status_page.obj = dctx_obj; | |
199 | ||
200 | ret = i915_cmd_parser_init_ring(ring); | |
201 | if (ret) | |
202 | return ret; | |
203 | ||
204 | if (ring->init) { | |
205 | ret = ring->init(ring); | |
206 | if (ret) | |
207 | return ret; | |
208 | } | |
209 | ||
454afebd OM |
210 | return 0; |
211 | } | |
212 | ||
213 | static int logical_render_ring_init(struct drm_device *dev) | |
214 | { | |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
216 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
217 | ||
218 | ring->name = "render ring"; | |
219 | ring->id = RCS; | |
220 | ring->mmio_base = RENDER_RING_BASE; | |
221 | ring->irq_enable_mask = | |
222 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
223 | ||
9b1136d5 OM |
224 | ring->init = gen8_init_render_ring; |
225 | ring->cleanup = intel_fini_pipe_control; | |
226 | ||
454afebd OM |
227 | return logical_ring_init(dev, ring); |
228 | } | |
229 | ||
230 | static int logical_bsd_ring_init(struct drm_device *dev) | |
231 | { | |
232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
233 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
234 | ||
235 | ring->name = "bsd ring"; | |
236 | ring->id = VCS; | |
237 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
238 | ring->irq_enable_mask = | |
239 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
240 | ||
9b1136d5 OM |
241 | ring->init = gen8_init_common_ring; |
242 | ||
454afebd OM |
243 | return logical_ring_init(dev, ring); |
244 | } | |
245 | ||
246 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
247 | { | |
248 | struct drm_i915_private *dev_priv = dev->dev_private; | |
249 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
250 | ||
251 | ring->name = "bds2 ring"; | |
252 | ring->id = VCS2; | |
253 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
254 | ring->irq_enable_mask = | |
255 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
256 | ||
9b1136d5 OM |
257 | ring->init = gen8_init_common_ring; |
258 | ||
454afebd OM |
259 | return logical_ring_init(dev, ring); |
260 | } | |
261 | ||
262 | static int logical_blt_ring_init(struct drm_device *dev) | |
263 | { | |
264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
265 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
266 | ||
267 | ring->name = "blitter ring"; | |
268 | ring->id = BCS; | |
269 | ring->mmio_base = BLT_RING_BASE; | |
270 | ring->irq_enable_mask = | |
271 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
272 | ||
9b1136d5 OM |
273 | ring->init = gen8_init_common_ring; |
274 | ||
454afebd OM |
275 | return logical_ring_init(dev, ring); |
276 | } | |
277 | ||
278 | static int logical_vebox_ring_init(struct drm_device *dev) | |
279 | { | |
280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
281 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
282 | ||
283 | ring->name = "video enhancement ring"; | |
284 | ring->id = VECS; | |
285 | ring->mmio_base = VEBOX_RING_BASE; | |
286 | ring->irq_enable_mask = | |
287 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
288 | ||
9b1136d5 OM |
289 | ring->init = gen8_init_common_ring; |
290 | ||
454afebd OM |
291 | return logical_ring_init(dev, ring); |
292 | } | |
293 | ||
294 | int intel_logical_rings_init(struct drm_device *dev) | |
295 | { | |
296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
297 | int ret; | |
298 | ||
299 | ret = logical_render_ring_init(dev); | |
300 | if (ret) | |
301 | return ret; | |
302 | ||
303 | if (HAS_BSD(dev)) { | |
304 | ret = logical_bsd_ring_init(dev); | |
305 | if (ret) | |
306 | goto cleanup_render_ring; | |
307 | } | |
308 | ||
309 | if (HAS_BLT(dev)) { | |
310 | ret = logical_blt_ring_init(dev); | |
311 | if (ret) | |
312 | goto cleanup_bsd_ring; | |
313 | } | |
314 | ||
315 | if (HAS_VEBOX(dev)) { | |
316 | ret = logical_vebox_ring_init(dev); | |
317 | if (ret) | |
318 | goto cleanup_blt_ring; | |
319 | } | |
320 | ||
321 | if (HAS_BSD2(dev)) { | |
322 | ret = logical_bsd2_ring_init(dev); | |
323 | if (ret) | |
324 | goto cleanup_vebox_ring; | |
325 | } | |
326 | ||
327 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
328 | if (ret) | |
329 | goto cleanup_bsd2_ring; | |
330 | ||
331 | return 0; | |
332 | ||
333 | cleanup_bsd2_ring: | |
334 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
335 | cleanup_vebox_ring: | |
336 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
337 | cleanup_blt_ring: | |
338 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
339 | cleanup_bsd_ring: | |
340 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
341 | cleanup_render_ring: | |
342 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
343 | ||
344 | return ret; | |
345 | } | |
346 | ||
8670d6f9 OM |
347 | static int |
348 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
349 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
350 | { | |
351 | struct drm_i915_gem_object *ring_obj = ringbuf->obj; | |
352 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); | |
353 | struct page *page; | |
354 | uint32_t *reg_state; | |
355 | int ret; | |
356 | ||
357 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
358 | if (ret) { | |
359 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
360 | return ret; | |
361 | } | |
362 | ||
363 | ret = i915_gem_object_get_pages(ctx_obj); | |
364 | if (ret) { | |
365 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
366 | return ret; | |
367 | } | |
368 | ||
369 | i915_gem_object_pin_pages(ctx_obj); | |
370 | ||
371 | /* The second page of the context object contains some fields which must | |
372 | * be set up prior to the first execution. */ | |
373 | page = i915_gem_object_get_page(ctx_obj, 1); | |
374 | reg_state = kmap_atomic(page); | |
375 | ||
376 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
377 | * commands followed by (reg, value) pairs. The values we are setting here are | |
378 | * only for the first context restore: on a subsequent save, the GPU will | |
379 | * recreate this batchbuffer with new values (including all the missing | |
380 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
381 | if (ring->id == RCS) | |
382 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
383 | else | |
384 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
385 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
386 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
387 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
388 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); | |
389 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); | |
390 | reg_state[CTX_RING_HEAD+1] = 0; | |
391 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
392 | reg_state[CTX_RING_TAIL+1] = 0; | |
393 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
394 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); | |
395 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); | |
396 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
397 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
398 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
399 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
400 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
401 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
402 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
403 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
404 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
405 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
406 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
407 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
408 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
409 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
410 | if (ring->id == RCS) { | |
411 | /* TODO: according to BSpec, the register state context | |
412 | * for CHV does not have these. OTOH, these registers do | |
413 | * exist in CHV. I'm waiting for a clarification */ | |
414 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; | |
415 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
416 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
417 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
418 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
419 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
420 | } | |
421 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
422 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
423 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
424 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
425 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
426 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
427 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
428 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
429 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
430 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
431 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
432 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
433 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); | |
434 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); | |
435 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); | |
436 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); | |
437 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); | |
438 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); | |
439 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); | |
440 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); | |
441 | if (ring->id == RCS) { | |
442 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
443 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; | |
444 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; | |
445 | } | |
446 | ||
447 | kunmap_atomic(reg_state); | |
448 | ||
449 | ctx_obj->dirty = 1; | |
450 | set_page_dirty(page); | |
451 | i915_gem_object_unpin_pages(ctx_obj); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
ede7d42b OM |
456 | void intel_lr_context_free(struct intel_context *ctx) |
457 | { | |
8c857917 OM |
458 | int i; |
459 | ||
460 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
461 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f OM |
462 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
463 | ||
8c857917 | 464 | if (ctx_obj) { |
84c2377f OM |
465 | intel_destroy_ringbuffer_obj(ringbuf); |
466 | kfree(ringbuf); | |
8c857917 OM |
467 | i915_gem_object_ggtt_unpin(ctx_obj); |
468 | drm_gem_object_unreference(&ctx_obj->base); | |
469 | } | |
470 | } | |
471 | } | |
472 | ||
473 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
474 | { | |
475 | int ret = 0; | |
476 | ||
477 | WARN_ON(INTEL_INFO(ring->dev)->gen != 8); | |
478 | ||
479 | switch (ring->id) { | |
480 | case RCS: | |
481 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
482 | break; | |
483 | case VCS: | |
484 | case BCS: | |
485 | case VECS: | |
486 | case VCS2: | |
487 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
488 | break; | |
489 | } | |
490 | ||
491 | return ret; | |
ede7d42b OM |
492 | } |
493 | ||
494 | int intel_lr_context_deferred_create(struct intel_context *ctx, | |
495 | struct intel_engine_cs *ring) | |
496 | { | |
8c857917 OM |
497 | struct drm_device *dev = ring->dev; |
498 | struct drm_i915_gem_object *ctx_obj; | |
499 | uint32_t context_size; | |
84c2377f | 500 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
501 | int ret; |
502 | ||
ede7d42b | 503 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
48d82387 OM |
504 | if (ctx->engine[ring->id].state) |
505 | return 0; | |
ede7d42b | 506 | |
8c857917 OM |
507 | context_size = round_up(get_lr_context_size(ring), 4096); |
508 | ||
509 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); | |
510 | if (IS_ERR(ctx_obj)) { | |
511 | ret = PTR_ERR(ctx_obj); | |
512 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); | |
513 | return ret; | |
514 | } | |
515 | ||
516 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
517 | if (ret) { | |
518 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); | |
519 | drm_gem_object_unreference(&ctx_obj->base); | |
520 | return ret; | |
521 | } | |
522 | ||
84c2377f OM |
523 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
524 | if (!ringbuf) { | |
525 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
526 | ring->name); | |
527 | i915_gem_object_ggtt_unpin(ctx_obj); | |
528 | drm_gem_object_unreference(&ctx_obj->base); | |
529 | ret = -ENOMEM; | |
530 | return ret; | |
531 | } | |
532 | ||
0c7dd53b | 533 | ringbuf->ring = ring; |
84c2377f OM |
534 | ringbuf->size = 32 * PAGE_SIZE; |
535 | ringbuf->effective_size = ringbuf->size; | |
536 | ringbuf->head = 0; | |
537 | ringbuf->tail = 0; | |
538 | ringbuf->space = ringbuf->size; | |
539 | ringbuf->last_retired_head = -1; | |
540 | ||
541 | /* TODO: For now we put this in the mappable region so that we can reuse | |
542 | * the existing ringbuffer code which ioremaps it. When we start | |
543 | * creating many contexts, this will no longer work and we must switch | |
544 | * to a kmapish interface. | |
545 | */ | |
546 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
547 | if (ret) { | |
548 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", | |
549 | ring->name, ret); | |
8670d6f9 OM |
550 | goto error; |
551 | } | |
552 | ||
553 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
554 | if (ret) { | |
555 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
556 | intel_destroy_ringbuffer_obj(ringbuf); | |
557 | goto error; | |
84c2377f OM |
558 | } |
559 | ||
560 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 561 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b OM |
562 | |
563 | return 0; | |
8670d6f9 OM |
564 | |
565 | error: | |
566 | kfree(ringbuf); | |
567 | i915_gem_object_ggtt_unpin(ctx_obj); | |
568 | drm_gem_object_unreference(&ctx_obj->base); | |
569 | return ret; | |
ede7d42b | 570 | } |