Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 | 34 | #include <drm/drmP.h> |
c6f95f27 | 35 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
36 | #include <drm/drm_crtc.h> |
37 | #include <drm/drm_edid.h> | |
79e53945 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
79e53945 | 40 | #include "i915_drv.h" |
e99da35f | 41 | #include <linux/acpi.h> |
79e53945 | 42 | |
3fbe18d6 | 43 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
44 | struct intel_lvds_connector { |
45 | struct intel_connector base; | |
788319d4 | 46 | |
db1740a0 | 47 | struct notifier_block lid_notifier; |
c7362c4d JN |
48 | }; |
49 | ||
29b99b48 | 50 | struct intel_lvds_encoder { |
ea5b213a | 51 | struct intel_encoder base; |
788319d4 | 52 | |
13c7d870 | 53 | bool is_dual_link; |
7dec0606 | 54 | u32 reg; |
1f835a77 | 55 | u32 a3_power; |
788319d4 | 56 | |
62165e0d | 57 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
58 | }; |
59 | ||
29b99b48 | 60 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 61 | { |
29b99b48 | 62 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
63 | } |
64 | ||
c7362c4d | 65 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 66 | { |
c7362c4d | 67 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
68 | } |
69 | ||
b1dc332c DV |
70 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
71 | enum pipe *pipe) | |
72 | { | |
73 | struct drm_device *dev = encoder->base.dev; | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 | 75 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
34a6c70f | 76 | enum intel_display_power_domain power_domain; |
7dec0606 | 77 | u32 tmp; |
b1dc332c | 78 | |
34a6c70f | 79 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 80 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
34a6c70f PZ |
81 | return false; |
82 | ||
7dec0606 | 83 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
84 | |
85 | if (!(tmp & LVDS_PORT_EN)) | |
86 | return false; | |
87 | ||
88 | if (HAS_PCH_CPT(dev)) | |
89 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
90 | else | |
91 | *pipe = PORT_TO_PIPE(tmp); | |
92 | ||
93 | return true; | |
94 | } | |
95 | ||
045ac3b5 | 96 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
5cec258b | 97 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
98 | { |
99 | struct drm_device *dev = encoder->base.dev; | |
100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
101 | u32 lvds_reg, tmp, flags = 0; | |
18442d08 | 102 | int dotclock; |
045ac3b5 JB |
103 | |
104 | if (HAS_PCH_SPLIT(dev)) | |
105 | lvds_reg = PCH_LVDS; | |
106 | else | |
107 | lvds_reg = LVDS; | |
108 | ||
109 | tmp = I915_READ(lvds_reg); | |
110 | if (tmp & LVDS_HSYNC_POLARITY) | |
111 | flags |= DRM_MODE_FLAG_NHSYNC; | |
112 | else | |
113 | flags |= DRM_MODE_FLAG_PHSYNC; | |
114 | if (tmp & LVDS_VSYNC_POLARITY) | |
115 | flags |= DRM_MODE_FLAG_NVSYNC; | |
116 | else | |
117 | flags |= DRM_MODE_FLAG_PVSYNC; | |
118 | ||
2d112de7 | 119 | pipe_config->base.adjusted_mode.flags |= flags; |
06922821 | 120 | |
6b89cdde DV |
121 | /* gen2/3 store dither state in pfit control, needs to match */ |
122 | if (INTEL_INFO(dev)->gen < 4) { | |
123 | tmp = I915_READ(PFIT_CONTROL); | |
124 | ||
125 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
126 | } | |
127 | ||
18442d08 VS |
128 | dotclock = pipe_config->port_clock; |
129 | ||
130 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
131 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
132 | ||
2d112de7 | 133 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
134 | } |
135 | ||
f6736a1a | 136 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
fc683091 DV |
137 | { |
138 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
139 | struct drm_device *dev = encoder->base.dev; | |
140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55607e8a | 141 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
4c6df4b4 | 142 | const struct drm_display_mode *adjusted_mode = |
6e3c9717 | 143 | &crtc->config->base.adjusted_mode; |
55607e8a | 144 | int pipe = crtc->pipe; |
fc683091 DV |
145 | u32 temp; |
146 | ||
55607e8a DV |
147 | if (HAS_PCH_SPLIT(dev)) { |
148 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
149 | assert_shared_dpll_disabled(dev_priv, | |
150 | intel_crtc_to_shared_dpll(crtc)); | |
151 | } else { | |
152 | assert_pll_disabled(dev_priv, pipe); | |
153 | } | |
154 | ||
fc683091 DV |
155 | temp = I915_READ(lvds_encoder->reg); |
156 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
157 | |
158 | if (HAS_PCH_CPT(dev)) { | |
159 | temp &= ~PORT_TRANS_SEL_MASK; | |
160 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 161 | } else { |
62810e5a DV |
162 | if (pipe == 1) { |
163 | temp |= LVDS_PIPEB_SELECT; | |
164 | } else { | |
165 | temp &= ~LVDS_PIPEB_SELECT; | |
166 | } | |
fc683091 | 167 | } |
62810e5a | 168 | |
fc683091 | 169 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 170 | temp &= ~LVDS_BORDER_ENABLE; |
6e3c9717 | 171 | temp |= crtc->config->gmch_pfit.lvds_border_bits; |
fc683091 DV |
172 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
173 | * set the DPLLs for dual-channel mode or not. | |
174 | */ | |
175 | if (lvds_encoder->is_dual_link) | |
176 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
177 | else | |
178 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
179 | ||
180 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
181 | * appropriately here, but we need to look more thoroughly into how | |
1f835a77 PZ |
182 | * panels behave in the two modes. For now, let's just maintain the |
183 | * value we got from the BIOS. | |
fc683091 | 184 | */ |
1f835a77 PZ |
185 | temp &= ~LVDS_A3_POWER_MASK; |
186 | temp |= lvds_encoder->a3_power; | |
62810e5a DV |
187 | |
188 | /* Set the dithering flag on LVDS as needed, note that there is no | |
189 | * special lvds dither control bit on pch-split platforms, dithering is | |
190 | * only controlled through the PIPECONF reg. */ | |
191 | if (INTEL_INFO(dev)->gen == 4) { | |
d8b32247 DV |
192 | /* Bspec wording suggests that LVDS port dithering only exists |
193 | * for 18bpp panels. */ | |
6e3c9717 | 194 | if (crtc->config->dither && crtc->config->pipe_bpp == 18) |
fc683091 DV |
195 | temp |= LVDS_ENABLE_DITHER; |
196 | else | |
197 | temp &= ~LVDS_ENABLE_DITHER; | |
198 | } | |
199 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 200 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 201 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 202 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
203 | temp |= LVDS_VSYNC_POLARITY; |
204 | ||
205 | I915_WRITE(lvds_encoder->reg, temp); | |
206 | } | |
207 | ||
79e53945 JB |
208 | /** |
209 | * Sets the power state for the panel. | |
210 | */ | |
c22834ec | 211 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 212 | { |
c22834ec | 213 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 214 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
215 | struct intel_connector *intel_connector = |
216 | &lvds_encoder->attached_connector->base; | |
79e53945 | 217 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 218 | u32 ctl_reg, stat_reg; |
541998a1 | 219 | |
c619eed4 | 220 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 221 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 222 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
223 | } else { |
224 | ctl_reg = PP_CONTROL; | |
de842eff | 225 | stat_reg = PP_STATUS; |
541998a1 | 226 | } |
79e53945 | 227 | |
7dec0606 | 228 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 229 | |
2a1292fd | 230 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 231 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
232 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
233 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 234 | |
752aa88a | 235 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
236 | } |
237 | ||
c22834ec | 238 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 239 | { |
c22834ec | 240 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 241 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
242 | struct intel_connector *intel_connector = |
243 | &lvds_encoder->attached_connector->base; | |
2a1292fd | 244 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 245 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
246 | |
247 | if (HAS_PCH_SPLIT(dev)) { | |
248 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 249 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
250 | } else { |
251 | ctl_reg = PP_CONTROL; | |
de842eff | 252 | stat_reg = PP_STATUS; |
2a1292fd CW |
253 | } |
254 | ||
752aa88a | 255 | intel_panel_disable_backlight(intel_connector); |
2a1292fd CW |
256 | |
257 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
258 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
259 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 260 | |
7dec0606 DV |
261 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
262 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
263 | } |
264 | ||
c19de8eb DL |
265 | static enum drm_mode_status |
266 | intel_lvds_mode_valid(struct drm_connector *connector, | |
267 | struct drm_display_mode *mode) | |
79e53945 | 268 | { |
dd06f90e JN |
269 | struct intel_connector *intel_connector = to_intel_connector(connector); |
270 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 271 | |
788319d4 CW |
272 | if (mode->hdisplay > fixed_mode->hdisplay) |
273 | return MODE_PANEL; | |
274 | if (mode->vdisplay > fixed_mode->vdisplay) | |
275 | return MODE_PANEL; | |
79e53945 JB |
276 | |
277 | return MODE_OK; | |
278 | } | |
279 | ||
7ae89233 | 280 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
5cec258b | 281 | struct intel_crtc_state *pipe_config) |
79e53945 | 282 | { |
7ae89233 | 283 | struct drm_device *dev = intel_encoder->base.dev; |
7ae89233 DV |
284 | struct intel_lvds_encoder *lvds_encoder = |
285 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
286 | struct intel_connector *intel_connector = |
287 | &lvds_encoder->attached_connector->base; | |
2d112de7 | 288 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d21bd67b | 289 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e53c2e0 | 290 | unsigned int lvds_bpp; |
79e53945 JB |
291 | |
292 | /* Should never happen!! */ | |
a6c45cf0 | 293 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 294 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
295 | return false; |
296 | } | |
297 | ||
1f835a77 | 298 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
4e53c2e0 DV |
299 | lvds_bpp = 8*3; |
300 | else | |
301 | lvds_bpp = 6*3; | |
302 | ||
e29c22c0 | 303 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
304 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
305 | pipe_config->pipe_bpp, lvds_bpp); | |
306 | pipe_config->pipe_bpp = lvds_bpp; | |
307 | } | |
d8b32247 | 308 | |
79e53945 | 309 | /* |
71677043 | 310 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
311 | * to the adjusted mode. The CRTC will be set up for this mode, |
312 | * with the panel scaling set up to source from the H/VDisplay | |
313 | * of the original mode. | |
314 | */ | |
4d891523 | 315 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 316 | adjusted_mode); |
1d8e1c75 CW |
317 | |
318 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
319 | pipe_config->has_pch_encoder = true; |
320 | ||
b074cec8 JB |
321 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
322 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
323 | } else { |
324 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
325 | intel_connector->panel.fitting_mode); | |
79e53945 | 326 | |
21d8a475 | 327 | } |
f9bef081 | 328 | |
79e53945 JB |
329 | /* |
330 | * XXX: It would be nice to support lower refresh rates on the | |
331 | * panels to reduce power consumption, and perhaps match the | |
332 | * user's requested refresh rate. | |
333 | */ | |
334 | ||
335 | return true; | |
336 | } | |
337 | ||
79e53945 JB |
338 | /** |
339 | * Detect the LVDS connection. | |
340 | * | |
b42d4c5c JB |
341 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
342 | * connected and closed means disconnected. We also send hotplug events as | |
343 | * needed, using lid status notification from the input layer. | |
79e53945 | 344 | */ |
7b334fcb | 345 | static enum drm_connector_status |
930a9e28 | 346 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 347 | { |
7b9c5abe | 348 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 349 | enum drm_connector_status status; |
b42d4c5c | 350 | |
164c8598 | 351 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 352 | connector->base.id, connector->name); |
164c8598 | 353 | |
fe16d949 CW |
354 | status = intel_panel_detect(dev); |
355 | if (status != connector_status_unknown) | |
356 | return status; | |
01fe9dbd | 357 | |
6ee3b5a1 | 358 | return connector_status_connected; |
79e53945 JB |
359 | } |
360 | ||
361 | /** | |
362 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
363 | */ | |
364 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
365 | { | |
62165e0d | 366 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 367 | struct drm_device *dev = connector->dev; |
788319d4 | 368 | struct drm_display_mode *mode; |
79e53945 | 369 | |
9cd300e0 | 370 | /* use cached edid if we have one */ |
2aa4f099 | 371 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 372 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 373 | |
dd06f90e | 374 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 375 | if (mode == NULL) |
788319d4 | 376 | return 0; |
79e53945 | 377 | |
788319d4 CW |
378 | drm_mode_probed_add(connector, mode); |
379 | return 1; | |
79e53945 JB |
380 | } |
381 | ||
0544edfd TB |
382 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
383 | { | |
bc0daf48 | 384 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
385 | return 1; |
386 | } | |
387 | ||
388 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
389 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
390 | { | |
391 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
392 | .ident = "Toshiba Tecra A11", | |
393 | .matches = { | |
394 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
395 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
396 | }, | |
397 | }, | |
398 | ||
399 | { } /* terminating entry */ | |
400 | }; | |
401 | ||
c9354c85 | 402 | /* |
b8efb17b ZR |
403 | * Lid events. Note the use of 'modeset': |
404 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
405 | * and set it to MODESET_DONE on open | |
c9354c85 | 406 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
407 | * duplicate events where it was already properly set) |
408 | * - the suspend/resume paths will set it to | |
409 | * MODESET_SUSPENDED and ignore the lid open event, | |
410 | * because they restore the mode ("lid open"). | |
c9354c85 | 411 | */ |
c1c7af60 JB |
412 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
413 | void *unused) | |
414 | { | |
db1740a0 JN |
415 | struct intel_lvds_connector *lvds_connector = |
416 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
417 | struct drm_connector *connector = &lvds_connector->base.base; | |
418 | struct drm_device *dev = connector->dev; | |
419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 420 | |
2fb4e61d AW |
421 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
422 | return NOTIFY_OK; | |
423 | ||
b8efb17b ZR |
424 | mutex_lock(&dev_priv->modeset_restore_lock); |
425 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
426 | goto exit; | |
a2565377 ZY |
427 | /* |
428 | * check and update the status of LVDS connector after receiving | |
429 | * the LID nofication event. | |
430 | */ | |
db1740a0 | 431 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 432 | |
0544edfd TB |
433 | /* Don't force modeset on machines where it causes a GPU lockup */ |
434 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 435 | goto exit; |
c9354c85 | 436 | if (!acpi_lid_open()) { |
b8efb17b ZR |
437 | /* do modeset on next lid open event */ |
438 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
439 | goto exit; | |
06891e27 | 440 | } |
c1c7af60 | 441 | |
b8efb17b ZR |
442 | if (dev_priv->modeset_restore == MODESET_DONE) |
443 | goto exit; | |
c9354c85 | 444 | |
5be19d91 DV |
445 | /* |
446 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
447 | * We try to detect this here and undo any damage. The split for PCH | |
448 | * platforms is rather conservative and a bit arbitrary expect that on | |
449 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
450 | * and as part of the cleanup in the hw state restore we also redisable | |
451 | * the vga plane. | |
452 | */ | |
453 | if (!HAS_PCH_SPLIT(dev)) { | |
454 | drm_modeset_lock_all(dev); | |
455 | intel_modeset_setup_hw_state(dev, true); | |
456 | drm_modeset_unlock_all(dev); | |
457 | } | |
06324194 | 458 | |
b8efb17b ZR |
459 | dev_priv->modeset_restore = MODESET_DONE; |
460 | ||
461 | exit: | |
462 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
463 | return NOTIFY_OK; |
464 | } | |
465 | ||
79e53945 JB |
466 | /** |
467 | * intel_lvds_destroy - unregister and free LVDS structures | |
468 | * @connector: connector to free | |
469 | * | |
470 | * Unregister the DDC bus for this connector then free the driver private | |
471 | * structure. | |
472 | */ | |
473 | static void intel_lvds_destroy(struct drm_connector *connector) | |
474 | { | |
db1740a0 JN |
475 | struct intel_lvds_connector *lvds_connector = |
476 | to_lvds_connector(connector); | |
79e53945 | 477 | |
db1740a0 JN |
478 | if (lvds_connector->lid_notifier.notifier_call) |
479 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 480 | |
9cd300e0 JN |
481 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
482 | kfree(lvds_connector->base.edid); | |
483 | ||
1d508706 | 484 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 485 | |
79e53945 JB |
486 | drm_connector_cleanup(connector); |
487 | kfree(connector); | |
488 | } | |
489 | ||
335041ed JB |
490 | static int intel_lvds_set_property(struct drm_connector *connector, |
491 | struct drm_property *property, | |
492 | uint64_t value) | |
493 | { | |
4d891523 | 494 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 495 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 496 | |
788319d4 | 497 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 498 | struct drm_crtc *crtc; |
bb8a3560 | 499 | |
53bd8389 JB |
500 | if (value == DRM_MODE_SCALE_NONE) { |
501 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 502 | return -EINVAL; |
3fbe18d6 | 503 | } |
788319d4 | 504 | |
4d891523 | 505 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
506 | /* the LVDS scaling property is not changed */ |
507 | return 0; | |
508 | } | |
4d891523 | 509 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
510 | |
511 | crtc = intel_attached_encoder(connector)->base.crtc; | |
83d65738 | 512 | if (crtc && crtc->state->enable) { |
3fbe18d6 ZY |
513 | /* |
514 | * If the CRTC is enabled, the display will be changed | |
515 | * according to the new panel fitting mode. | |
516 | */ | |
c0c36b94 | 517 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
518 | } |
519 | } | |
520 | ||
335041ed JB |
521 | return 0; |
522 | } | |
523 | ||
79e53945 JB |
524 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
525 | .get_modes = intel_lvds_get_modes, | |
526 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 527 | .best_encoder = intel_best_encoder, |
79e53945 JB |
528 | }; |
529 | ||
530 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 531 | .dpms = intel_connector_dpms, |
79e53945 JB |
532 | .detect = intel_lvds_detect, |
533 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 534 | .set_property = intel_lvds_set_property, |
2545e4a6 | 535 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 | 536 | .destroy = intel_lvds_destroy, |
c6f95f27 | 537 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 538 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
539 | }; |
540 | ||
79e53945 | 541 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 542 | .destroy = intel_encoder_destroy, |
79e53945 JB |
543 | }; |
544 | ||
bbe1c274 | 545 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
425d244c | 546 | { |
bc0daf48 | 547 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
548 | return 1; |
549 | } | |
79e53945 | 550 | |
425d244c | 551 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 552 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
553 | { |
554 | .callback = intel_no_lvds_dmi_callback, | |
555 | .ident = "Apple Mac Mini (Core series)", | |
556 | .matches = { | |
98acd46f | 557 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
558 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
559 | }, | |
560 | }, | |
561 | { | |
562 | .callback = intel_no_lvds_dmi_callback, | |
563 | .ident = "Apple Mac Mini (Core 2 series)", | |
564 | .matches = { | |
98acd46f | 565 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
566 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
567 | }, | |
568 | }, | |
569 | { | |
570 | .callback = intel_no_lvds_dmi_callback, | |
571 | .ident = "MSI IM-945GSE-A", | |
572 | .matches = { | |
573 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
574 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
575 | }, | |
576 | }, | |
577 | { | |
578 | .callback = intel_no_lvds_dmi_callback, | |
579 | .ident = "Dell Studio Hybrid", | |
580 | .matches = { | |
581 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
582 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
583 | }, | |
584 | }, | |
70aa96ca JW |
585 | { |
586 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
587 | .ident = "Dell OptiPlex FX170", |
588 | .matches = { | |
589 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
590 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
591 | }, | |
592 | }, | |
593 | { | |
594 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
595 | .ident = "AOpen Mini PC", |
596 | .matches = { | |
597 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
598 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
599 | }, | |
600 | }, | |
ed8c754b TV |
601 | { |
602 | .callback = intel_no_lvds_dmi_callback, | |
603 | .ident = "AOpen Mini PC MP915", | |
604 | .matches = { | |
605 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
606 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
607 | }, | |
608 | }, | |
22ab70d3 KP |
609 | { |
610 | .callback = intel_no_lvds_dmi_callback, | |
611 | .ident = "AOpen i915GMm-HFS", | |
612 | .matches = { | |
613 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
614 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
615 | }, | |
616 | }, | |
e57b6886 DV |
617 | { |
618 | .callback = intel_no_lvds_dmi_callback, | |
619 | .ident = "AOpen i45GMx-I", | |
620 | .matches = { | |
621 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
622 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
623 | }, | |
624 | }, | |
fa0864b2 MC |
625 | { |
626 | .callback = intel_no_lvds_dmi_callback, | |
627 | .ident = "Aopen i945GTt-VFA", | |
628 | .matches = { | |
629 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
630 | }, | |
631 | }, | |
9875557e SB |
632 | { |
633 | .callback = intel_no_lvds_dmi_callback, | |
634 | .ident = "Clientron U800", | |
635 | .matches = { | |
636 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
637 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
638 | }, | |
639 | }, | |
6a574b5b | 640 | { |
44306ab3 JS |
641 | .callback = intel_no_lvds_dmi_callback, |
642 | .ident = "Clientron E830", | |
643 | .matches = { | |
644 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
645 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
646 | }, | |
647 | }, | |
648 | { | |
6a574b5b HG |
649 | .callback = intel_no_lvds_dmi_callback, |
650 | .ident = "Asus EeeBox PC EB1007", | |
651 | .matches = { | |
652 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
653 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
654 | }, | |
655 | }, | |
0999bbe0 AJ |
656 | { |
657 | .callback = intel_no_lvds_dmi_callback, | |
658 | .ident = "Asus AT5NM10T-I", | |
659 | .matches = { | |
660 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
661 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
662 | }, | |
663 | }, | |
33471119 JBG |
664 | { |
665 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 666 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
667 | .matches = { |
668 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 669 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
670 | }, |
671 | }, | |
f5b8a7ed MG |
672 | { |
673 | .callback = intel_no_lvds_dmi_callback, | |
674 | .ident = "Hewlett-Packard t5745", | |
675 | .matches = { | |
676 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 677 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
678 | }, |
679 | }, | |
680 | { | |
681 | .callback = intel_no_lvds_dmi_callback, | |
682 | .ident = "Hewlett-Packard st5747", | |
683 | .matches = { | |
684 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 685 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
686 | }, |
687 | }, | |
97effadb AA |
688 | { |
689 | .callback = intel_no_lvds_dmi_callback, | |
690 | .ident = "MSI Wind Box DC500", | |
691 | .matches = { | |
692 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
693 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
694 | }, | |
695 | }, | |
a51d4ed0 CW |
696 | { |
697 | .callback = intel_no_lvds_dmi_callback, | |
698 | .ident = "Gigabyte GA-D525TUD", | |
699 | .matches = { | |
700 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
701 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
702 | }, | |
703 | }, | |
c31407a3 CW |
704 | { |
705 | .callback = intel_no_lvds_dmi_callback, | |
706 | .ident = "Supermicro X7SPA-H", | |
707 | .matches = { | |
708 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
709 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
710 | }, | |
711 | }, | |
9e9dd0e8 CL |
712 | { |
713 | .callback = intel_no_lvds_dmi_callback, | |
714 | .ident = "Fujitsu Esprimo Q900", | |
715 | .matches = { | |
716 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
717 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
718 | }, | |
719 | }, | |
645378d8 RP |
720 | { |
721 | .callback = intel_no_lvds_dmi_callback, | |
722 | .ident = "Intel D410PT", | |
723 | .matches = { | |
724 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
725 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
726 | }, | |
727 | }, | |
728 | { | |
729 | .callback = intel_no_lvds_dmi_callback, | |
730 | .ident = "Intel D425KT", | |
731 | .matches = { | |
732 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
733 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
734 | }, | |
735 | }, | |
e5614f0c CW |
736 | { |
737 | .callback = intel_no_lvds_dmi_callback, | |
738 | .ident = "Intel D510MO", | |
739 | .matches = { | |
740 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
741 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
742 | }, | |
743 | }, | |
dcf6d294 JN |
744 | { |
745 | .callback = intel_no_lvds_dmi_callback, | |
746 | .ident = "Intel D525MW", | |
747 | .matches = { | |
748 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
749 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
750 | }, | |
751 | }, | |
425d244c JW |
752 | |
753 | { } /* terminating entry */ | |
754 | }; | |
79e53945 | 755 | |
7cf4f69d ZY |
756 | /* |
757 | * Enumerate the child dev array parsed from VBT to check whether | |
758 | * the LVDS is present. | |
759 | * If it is present, return 1. | |
760 | * If it is not present, return false. | |
761 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 762 | */ |
270eea0f CW |
763 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
764 | u8 *i2c_pin) | |
7cf4f69d ZY |
765 | { |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 767 | int i; |
7cf4f69d | 768 | |
41aa3448 | 769 | if (!dev_priv->vbt.child_dev_num) |
425904dd | 770 | return true; |
7cf4f69d | 771 | |
41aa3448 | 772 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
768f69c9 PZ |
773 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
774 | struct old_child_dev_config *child = &uchild->old; | |
425904dd CW |
775 | |
776 | /* If the device type is not LFP, continue. | |
777 | * We have to check both the new identifiers as well as the | |
778 | * old for compatibility with some BIOSes. | |
7cf4f69d | 779 | */ |
425904dd CW |
780 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
781 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
782 | continue; |
783 | ||
88ac7939 | 784 | if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) |
3bd7d909 | 785 | *i2c_pin = child->i2c_pin; |
270eea0f | 786 | |
425904dd CW |
787 | /* However, we cannot trust the BIOS writers to populate |
788 | * the VBT correctly. Since LVDS requires additional | |
789 | * information from AIM blocks, a non-zero addin offset is | |
790 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 791 | */ |
425904dd CW |
792 | if (child->addin_offset) |
793 | return true; | |
794 | ||
795 | /* But even then some BIOS writers perform some black magic | |
796 | * and instantiate the device without reference to any | |
797 | * additional data. Trust that if the VBT was written into | |
798 | * the OpRegion then they have validated the LVDS's existence. | |
799 | */ | |
800 | if (dev_priv->opregion.vbt) | |
801 | return true; | |
7cf4f69d | 802 | } |
425904dd CW |
803 | |
804 | return false; | |
7cf4f69d ZY |
805 | } |
806 | ||
1974cad0 DV |
807 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
808 | { | |
809 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
810 | return 1; | |
811 | } | |
812 | ||
813 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
814 | { | |
815 | .callback = intel_dual_link_lvds_callback, | |
3916e3fd LW |
816 | .ident = "Apple MacBook Pro 15\" (2010)", |
817 | .matches = { | |
818 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
819 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), | |
820 | }, | |
821 | }, | |
822 | { | |
823 | .callback = intel_dual_link_lvds_callback, | |
824 | .ident = "Apple MacBook Pro 15\" (2011)", | |
1974cad0 DV |
825 | .matches = { |
826 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
827 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
828 | }, | |
829 | }, | |
3916e3fd LW |
830 | { |
831 | .callback = intel_dual_link_lvds_callback, | |
832 | .ident = "Apple MacBook Pro 15\" (2012)", | |
833 | .matches = { | |
834 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
835 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), | |
836 | }, | |
837 | }, | |
1974cad0 DV |
838 | { } /* terminating entry */ |
839 | }; | |
840 | ||
841 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
842 | { |
843 | struct intel_encoder *encoder; | |
844 | struct intel_lvds_encoder *lvds_encoder; | |
845 | ||
b2784e15 | 846 | for_each_intel_encoder(dev, encoder) { |
13c7d870 DV |
847 | if (encoder->type == INTEL_OUTPUT_LVDS) { |
848 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
849 | ||
850 | return lvds_encoder->is_dual_link; | |
851 | } | |
852 | } | |
853 | ||
854 | return false; | |
855 | } | |
856 | ||
7dec0606 | 857 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 858 | { |
7dec0606 | 859 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
860 | unsigned int val; |
861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
862 | |
863 | /* use the module option value if specified */ | |
d330a953 JN |
864 | if (i915.lvds_channel_mode > 0) |
865 | return i915.lvds_channel_mode == 2; | |
1974cad0 | 866 | |
6f317cfe LW |
867 | /* single channel LVDS is limited to 112 MHz */ |
868 | if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock | |
869 | > 112999) | |
870 | return true; | |
871 | ||
1974cad0 DV |
872 | if (dmi_check_system(intel_dual_link_lvds)) |
873 | return true; | |
874 | ||
13c7d870 DV |
875 | /* BIOS should set the proper LVDS register value at boot, but |
876 | * in reality, it doesn't set the value when the lid is closed; | |
877 | * we need to check "the value to be set" in VBT when LVDS | |
878 | * register is uninitialized. | |
879 | */ | |
7dec0606 | 880 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 881 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 882 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 883 | |
1974cad0 DV |
884 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
885 | } | |
886 | ||
f3cfcba6 CW |
887 | static bool intel_lvds_supported(struct drm_device *dev) |
888 | { | |
889 | /* With the introduction of the PCH we gained a dedicated | |
890 | * LVDS presence pin, use it. */ | |
311e359c | 891 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
892 | return true; |
893 | ||
894 | /* Otherwise LVDS was only attached to mobile products, | |
895 | * except for the inglorious 830gm */ | |
311e359c PZ |
896 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
897 | return true; | |
898 | ||
899 | return false; | |
f3cfcba6 CW |
900 | } |
901 | ||
79e53945 JB |
902 | /** |
903 | * intel_lvds_init - setup LVDS connectors on this device | |
904 | * @dev: drm device | |
905 | * | |
906 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
907 | * modes we can display on the LVDS panel (if present). | |
908 | */ | |
c9093354 | 909 | void intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
910 | { |
911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 912 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 913 | struct intel_encoder *intel_encoder; |
c7362c4d | 914 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 915 | struct intel_connector *intel_connector; |
79e53945 JB |
916 | struct drm_connector *connector; |
917 | struct drm_encoder *encoder; | |
918 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 919 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 920 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 921 | struct edid *edid; |
79e53945 JB |
922 | struct drm_crtc *crtc; |
923 | u32 lvds; | |
270eea0f CW |
924 | int pipe; |
925 | u8 pin; | |
79e53945 | 926 | |
b0616c53 DV |
927 | /* |
928 | * Unlock registers and just leave them unlocked. Do this before | |
929 | * checking quirk lists to avoid bogus WARNINGs. | |
930 | */ | |
931 | if (HAS_PCH_SPLIT(dev)) { | |
932 | I915_WRITE(PCH_PP_CONTROL, | |
933 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
934 | } else { | |
935 | I915_WRITE(PP_CONTROL, | |
936 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
937 | } | |
f3cfcba6 | 938 | if (!intel_lvds_supported(dev)) |
c9093354 | 939 | return; |
f3cfcba6 | 940 | |
425d244c JW |
941 | /* Skip init on machines we know falsely report LVDS */ |
942 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 943 | return; |
565dcd46 | 944 | |
988c7015 | 945 | pin = GMBUS_PIN_PANEL; |
270eea0f | 946 | if (!lvds_is_present_in_vbt(dev, &pin)) { |
11ba1592 | 947 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c9093354 | 948 | return; |
38b3037e | 949 | } |
e99da35f | 950 | |
c619eed4 | 951 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 952 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c9093354 | 953 | return; |
41aa3448 | 954 | if (dev_priv->vbt.edp_support) { |
28c97730 | 955 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 956 | return; |
32f9d658 | 957 | } |
541998a1 ZW |
958 | } |
959 | ||
b14c5679 | 960 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 961 | if (!lvds_encoder) |
c9093354 | 962 | return; |
79e53945 | 963 | |
b14c5679 | 964 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 965 | if (!lvds_connector) { |
29b99b48 | 966 | kfree(lvds_encoder); |
c9093354 | 967 | return; |
bb8a3560 ZW |
968 | } |
969 | ||
9bdbd0b9 ACO |
970 | if (intel_connector_init(&lvds_connector->base) < 0) { |
971 | kfree(lvds_connector); | |
972 | kfree(lvds_encoder); | |
973 | return; | |
974 | } | |
975 | ||
62165e0d JN |
976 | lvds_encoder->attached_connector = lvds_connector; |
977 | ||
29b99b48 | 978 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 979 | encoder = &intel_encoder->base; |
c7362c4d | 980 | intel_connector = &lvds_connector->base; |
ea5b213a | 981 | connector = &intel_connector->base; |
bb8a3560 | 982 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
983 | DRM_MODE_CONNECTOR_LVDS); |
984 | ||
4ef69c7a | 985 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
986 | DRM_MODE_ENCODER_LVDS); |
987 | ||
c22834ec | 988 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 989 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 990 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 991 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c | 992 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 993 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 994 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 995 | intel_connector->unregister = intel_connector_unregister; |
c22834ec | 996 | |
df0e9248 | 997 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 998 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 999 | |
bc079e8b | 1000 | intel_encoder->cloneable = 0; |
27f8227b JB |
1001 | if (HAS_PCH_SPLIT(dev)) |
1002 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1003 | else if (IS_GEN4(dev)) |
1004 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1005 | else |
1006 | intel_encoder->crtc_mask = (1 << 1); | |
1007 | ||
79e53945 JB |
1008 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
1009 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1010 | connector->interlace_allowed = false; | |
1011 | connector->doublescan_allowed = false; | |
1012 | ||
7dec0606 DV |
1013 | if (HAS_PCH_SPLIT(dev)) { |
1014 | lvds_encoder->reg = PCH_LVDS; | |
1015 | } else { | |
1016 | lvds_encoder->reg = LVDS; | |
1017 | } | |
1018 | ||
3fbe18d6 ZY |
1019 | /* create the scaling mode property */ |
1020 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1021 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1022 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1023 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1024 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1025 | /* |
1026 | * LVDS discovery: | |
1027 | * 1) check for EDID on DDC | |
1028 | * 2) check for VBT data | |
1029 | * 3) check to see if LVDS is already on | |
1030 | * if none of the above, no panel | |
1031 | * 4) make sure lid is open | |
1032 | * if closed, act like it's not there for now | |
1033 | */ | |
1034 | ||
79e53945 JB |
1035 | /* |
1036 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1037 | * preferred mode is the right one. | |
1038 | */ | |
4da98541 | 1039 | mutex_lock(&dev->mode_config.mutex); |
9cd300e0 JN |
1040 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1041 | if (edid) { | |
1042 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1043 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1044 | edid); |
3f8ff0e7 | 1045 | } else { |
9cd300e0 JN |
1046 | kfree(edid); |
1047 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1048 | } |
9cd300e0 JN |
1049 | } else { |
1050 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1051 | } |
9cd300e0 JN |
1052 | lvds_connector->base.edid = edid; |
1053 | ||
1054 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1055 | /* Didn't get an EDID, so |
1056 | * Set wide sync ranges so we get all modes | |
1057 | * handed to valid_mode for checking | |
1058 | */ | |
1059 | connector->display_info.min_vfreq = 0; | |
1060 | connector->display_info.max_vfreq = 200; | |
1061 | connector->display_info.min_hfreq = 0; | |
1062 | connector->display_info.max_hfreq = 200; | |
1063 | } | |
79e53945 JB |
1064 | |
1065 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1066 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1067 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1068 | drm_mode_debug_printmodeline(scan); | |
1069 | ||
dd06f90e | 1070 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 | 1071 | if (fixed_mode) { |
4b6ed685 | 1072 | downclock_mode = |
ec9ed197 VK |
1073 | intel_find_panel_downclock(dev, |
1074 | fixed_mode, connector); | |
4b6ed685 VK |
1075 | if (downclock_mode != NULL && |
1076 | i915.lvds_downclock) { | |
ec9ed197 VK |
1077 | /* We found the downclock for LVDS. */ |
1078 | dev_priv->lvds_downclock_avail = true; | |
1079 | dev_priv->lvds_downclock = | |
ec9ed197 VK |
1080 | downclock_mode->clock; |
1081 | DRM_DEBUG_KMS("LVDS downclock is found" | |
1082 | " in EDID. Normal clock %dKhz, " | |
1083 | "downclock %dKhz\n", | |
1084 | fixed_mode->clock, | |
1085 | dev_priv->lvds_downclock); | |
1086 | } | |
6a9d51b7 CW |
1087 | goto out; |
1088 | } | |
79e53945 | 1089 | } |
79e53945 JB |
1090 | } |
1091 | ||
1092 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1093 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1094 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1095 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1096 | |
41aa3448 | 1097 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1098 | if (fixed_mode) { |
1099 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1100 | goto out; |
1101 | } | |
79e53945 JB |
1102 | } |
1103 | ||
1104 | /* | |
1105 | * If we didn't get EDID, try checking if the panel is already turned | |
1106 | * on. If so, assume that whatever is currently programmed is the | |
1107 | * correct mode. | |
1108 | */ | |
541998a1 | 1109 | |
f2b115e6 | 1110 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1111 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1112 | goto failed; |
1113 | ||
79e53945 JB |
1114 | lvds = I915_READ(LVDS); |
1115 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1116 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1117 | |
1118 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1119 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1120 | if (fixed_mode) { | |
6a9d51b7 CW |
1121 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1122 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1123 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1124 | goto out; |
79e53945 JB |
1125 | } |
1126 | } | |
1127 | ||
1128 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1129 | if (!fixed_mode) |
79e53945 JB |
1130 | goto failed; |
1131 | ||
79e53945 | 1132 | out: |
4da98541 DV |
1133 | mutex_unlock(&dev->mode_config.mutex); |
1134 | ||
6f317cfe LW |
1135 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
1136 | ||
7dec0606 | 1137 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1138 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1139 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1140 | ||
1f835a77 PZ |
1141 | lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) & |
1142 | LVDS_A3_POWER_MASK; | |
1143 | ||
db1740a0 JN |
1144 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1145 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1146 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1147 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1148 | } |
34ea3d38 | 1149 | drm_connector_register(connector); |
aaa6fd2a | 1150 | |
6517d273 | 1151 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
aaa6fd2a | 1152 | |
c9093354 | 1153 | return; |
79e53945 JB |
1154 | |
1155 | failed: | |
4da98541 DV |
1156 | mutex_unlock(&dev->mode_config.mutex); |
1157 | ||
8a4c47f3 | 1158 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1159 | drm_connector_cleanup(connector); |
1991bdfa | 1160 | drm_encoder_cleanup(encoder); |
29b99b48 | 1161 | kfree(lvds_encoder); |
c7362c4d | 1162 | kfree(lvds_connector); |
c9093354 | 1163 | return; |
79e53945 | 1164 | } |