drm/i915/lvds: Rename intel_lvds to intel_lvds_encoder
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
29b99b48 43struct intel_lvds_encoder {
ea5b213a 44 struct intel_encoder base;
788319d4 45
219adae1 46 struct edid *edid;
788319d4 47
3fbe18d6
ZY
48 int fitting_mode;
49 u32 pfit_control;
50 u32 pfit_pgm_ratios;
e9e331a8 51 bool pfit_dirty;
788319d4
CW
52
53 struct drm_display_mode *fixed_mode;
3fbe18d6
ZY
54};
55
29b99b48 56static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 57{
29b99b48 58 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
59}
60
29b99b48 61static struct intel_lvds_encoder *intel_attached_lvds(struct drm_connector *connector)
788319d4
CW
62{
63 return container_of(intel_attached_encoder(connector),
29b99b48 64 struct intel_lvds_encoder, base);
788319d4
CW
65}
66
b1dc332c
DV
67static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
68 enum pipe *pipe)
69{
70 struct drm_device *dev = encoder->base.dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 lvds_reg, tmp;
73
74 if (HAS_PCH_SPLIT(dev)) {
75 lvds_reg = PCH_LVDS;
76 } else {
77 lvds_reg = LVDS;
78 }
79
80 tmp = I915_READ(lvds_reg);
81
82 if (!(tmp & LVDS_PORT_EN))
83 return false;
84
85 if (HAS_PCH_CPT(dev))
86 *pipe = PORT_TO_PIPE_CPT(tmp);
87 else
88 *pipe = PORT_TO_PIPE(tmp);
89
90 return true;
91}
92
79e53945
JB
93/**
94 * Sets the power state for the panel.
95 */
c22834ec 96static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 97{
c22834ec 98 struct drm_device *dev = encoder->base.dev;
29b99b48 99 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 100 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 101 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 102 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 103
c619eed4 104 if (HAS_PCH_SPLIT(dev)) {
541998a1 105 ctl_reg = PCH_PP_CONTROL;
469d1296 106 lvds_reg = PCH_LVDS;
de842eff 107 stat_reg = PCH_PP_STATUS;
541998a1
ZW
108 } else {
109 ctl_reg = PP_CONTROL;
469d1296 110 lvds_reg = LVDS;
de842eff 111 stat_reg = PP_STATUS;
541998a1 112 }
79e53945 113
2a1292fd 114 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 115
29b99b48 116 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
117 /*
118 * Enable automatic panel scaling so that non-native modes
119 * fill the screen. The panel fitter should only be
120 * adjusted whilst the pipe is disabled, according to
121 * register description and PRM.
122 */
123 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
124 lvds_encoder->pfit_control,
125 lvds_encoder->pfit_pgm_ratios);
de842eff 126
29b99b48
JN
127 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
128 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
129 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
130 }
131
132 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
133 POSTING_READ(lvds_reg);
de842eff
KP
134 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
135 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 136
24ded204 137 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
138}
139
c22834ec 140static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 141{
c22834ec 142 struct drm_device *dev = encoder->base.dev;
29b99b48 143 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 144 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 145 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
146
147 if (HAS_PCH_SPLIT(dev)) {
148 ctl_reg = PCH_PP_CONTROL;
149 lvds_reg = PCH_LVDS;
de842eff 150 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
151 } else {
152 ctl_reg = PP_CONTROL;
153 lvds_reg = LVDS;
de842eff 154 stat_reg = PP_STATUS;
2a1292fd
CW
155 }
156
47356eb6 157 intel_panel_disable_backlight(dev);
2a1292fd
CW
158
159 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
160 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
161 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 162
29b99b48 163 if (lvds_encoder->pfit_control) {
2a1292fd 164 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 165 lvds_encoder->pfit_dirty = true;
79e53945 166 }
2a1292fd
CW
167
168 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 169 POSTING_READ(lvds_reg);
79e53945
JB
170}
171
79e53945
JB
172static int intel_lvds_mode_valid(struct drm_connector *connector,
173 struct drm_display_mode *mode)
174{
29b99b48
JN
175 struct intel_lvds_encoder *lvds_encoder = intel_attached_lvds(connector);
176 struct drm_display_mode *fixed_mode = lvds_encoder->fixed_mode;
79e53945 177
788319d4
CW
178 if (mode->hdisplay > fixed_mode->hdisplay)
179 return MODE_PANEL;
180 if (mode->vdisplay > fixed_mode->vdisplay)
181 return MODE_PANEL;
79e53945
JB
182
183 return MODE_OK;
184}
185
49be663f
CW
186static void
187centre_horizontally(struct drm_display_mode *mode,
188 int width)
189{
190 u32 border, sync_pos, blank_width, sync_width;
191
192 /* keep the hsync and hblank widths constant */
193 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
194 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
195 sync_pos = (blank_width - sync_width + 1) / 2;
196
197 border = (mode->hdisplay - width + 1) / 2;
198 border += border & 1; /* make the border even */
199
200 mode->crtc_hdisplay = width;
201 mode->crtc_hblank_start = width + border;
202 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
203
204 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
205 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
206
207 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
208}
209
210static void
211centre_vertically(struct drm_display_mode *mode,
212 int height)
213{
214 u32 border, sync_pos, blank_width, sync_width;
215
216 /* keep the vsync and vblank widths constant */
217 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
218 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
219 sync_pos = (blank_width - sync_width + 1) / 2;
220
221 border = (mode->vdisplay - height + 1) / 2;
222
223 mode->crtc_vdisplay = height;
224 mode->crtc_vblank_start = height + border;
225 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
226
227 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
228 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
229
230 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
231}
232
233static inline u32 panel_fitter_scaling(u32 source, u32 target)
234{
235 /*
236 * Floating point operation is not supported. So the FACTOR
237 * is defined, which can avoid the floating point computation
238 * when calculating the panel ratio.
239 */
240#define ACCURACY 12
241#define FACTOR (1 << ACCURACY)
242 u32 ratio = source * FACTOR / target;
243 return (FACTOR * ratio + FACTOR/2) / FACTOR;
244}
245
79e53945 246static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 247 const struct drm_display_mode *mode,
79e53945
JB
248 struct drm_display_mode *adjusted_mode)
249{
250 struct drm_device *dev = encoder->dev;
251 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48
JN
252 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
253 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 254 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 255 int pipe;
79e53945
JB
256
257 /* Should never happen!! */
a6c45cf0 258 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 259 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
260 return false;
261 }
262
29b99b48 263 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 264 return false;
1d8e1c75 265
79e53945 266 /*
71677043 267 * We have timings from the BIOS for the panel, put them in
79e53945
JB
268 * to the adjusted mode. The CRTC will be set up for this mode,
269 * with the panel scaling set up to source from the H/VDisplay
270 * of the original mode.
271 */
29b99b48 272 intel_fixed_panel_mode(lvds_encoder->fixed_mode, adjusted_mode);
1d8e1c75
CW
273
274 if (HAS_PCH_SPLIT(dev)) {
29b99b48 275 intel_pch_panel_fitting(dev, lvds_encoder->fitting_mode,
1d8e1c75
CW
276 mode, adjusted_mode);
277 return true;
278 }
79e53945 279
3fbe18d6
ZY
280 /* Native modes don't need fitting */
281 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 282 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 283 goto out;
3fbe18d6
ZY
284
285 /* 965+ wants fuzzy fitting */
a6c45cf0 286 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
287 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
288 PFIT_FILTER_FUZZY);
289
3fbe18d6
ZY
290 /*
291 * Enable automatic panel scaling for non-native modes so that they fill
292 * the screen. Should be enabled before the pipe is enabled, according
293 * to register description and PRM.
294 * Change the value here to see the borders for debugging
295 */
9db4a9c7
JB
296 for_each_pipe(pipe)
297 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 298
f9bef081
DV
299 drm_mode_set_crtcinfo(adjusted_mode, 0);
300
29b99b48 301 switch (lvds_encoder->fitting_mode) {
53bd8389 302 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
303 /*
304 * For centered modes, we have to calculate border widths &
305 * heights and modify the values programmed into the CRTC.
306 */
49be663f
CW
307 centre_horizontally(adjusted_mode, mode->hdisplay);
308 centre_vertically(adjusted_mode, mode->vdisplay);
309 border = LVDS_BORDER_ENABLE;
3fbe18d6 310 break;
49be663f 311
3fbe18d6 312 case DRM_MODE_SCALE_ASPECT:
49be663f 313 /* Scale but preserve the aspect ratio */
a6c45cf0 314 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
315 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
316 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
317
3fbe18d6 318 /* 965+ is easy, it does everything in hw */
49be663f 319 if (scaled_width > scaled_height)
257e48f1 320 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 321 else if (scaled_width < scaled_height)
257e48f1
CW
322 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
323 else if (adjusted_mode->hdisplay != mode->hdisplay)
324 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 325 } else {
49be663f
CW
326 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
327 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
328 /*
329 * For earlier chips we have to calculate the scaling
330 * ratio by hand and program it into the
331 * PFIT_PGM_RATIO register
332 */
49be663f
CW
333 if (scaled_width > scaled_height) { /* pillar */
334 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
335
336 border = LVDS_BORDER_ENABLE;
337 if (mode->vdisplay != adjusted_mode->vdisplay) {
338 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
339 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
340 bits << PFIT_VERT_SCALE_SHIFT);
341 pfit_control |= (PFIT_ENABLE |
342 VERT_INTERP_BILINEAR |
343 HORIZ_INTERP_BILINEAR);
344 }
345 } else if (scaled_width < scaled_height) { /* letter */
346 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
347
348 border = LVDS_BORDER_ENABLE;
349 if (mode->hdisplay != adjusted_mode->hdisplay) {
350 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
351 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
352 bits << PFIT_VERT_SCALE_SHIFT);
353 pfit_control |= (PFIT_ENABLE |
354 VERT_INTERP_BILINEAR |
355 HORIZ_INTERP_BILINEAR);
356 }
357 } else
358 /* Aspects match, Let hw scale both directions */
359 pfit_control |= (PFIT_ENABLE |
360 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
361 VERT_INTERP_BILINEAR |
362 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
363 }
364 break;
365
366 case DRM_MODE_SCALE_FULLSCREEN:
367 /*
368 * Full scaling, even if it changes the aspect ratio.
369 * Fortunately this is all done for us in hw.
370 */
257e48f1
CW
371 if (mode->vdisplay != adjusted_mode->vdisplay ||
372 mode->hdisplay != adjusted_mode->hdisplay) {
373 pfit_control |= PFIT_ENABLE;
374 if (INTEL_INFO(dev)->gen >= 4)
375 pfit_control |= PFIT_SCALING_AUTO;
376 else
377 pfit_control |= (VERT_AUTO_SCALE |
378 VERT_INTERP_BILINEAR |
379 HORIZ_AUTO_SCALE |
380 HORIZ_INTERP_BILINEAR);
381 }
3fbe18d6 382 break;
49be663f 383
3fbe18d6
ZY
384 default:
385 break;
386 }
387
388out:
72389a33 389 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
390 if ((pfit_control & PFIT_ENABLE) == 0) {
391 pfit_control = 0;
392 pfit_pgm_ratios = 0;
393 }
72389a33
CW
394
395 /* Make sure pre-965 set dither correctly */
396 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
397 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
398
29b99b48
JN
399 if (pfit_control != lvds_encoder->pfit_control ||
400 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
401 lvds_encoder->pfit_control = pfit_control;
402 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
403 lvds_encoder->pfit_dirty = true;
e9e331a8 404 }
49be663f
CW
405 dev_priv->lvds_border_bits = border;
406
79e53945
JB
407 /*
408 * XXX: It would be nice to support lower refresh rates on the
409 * panels to reduce power consumption, and perhaps match the
410 * user's requested refresh rate.
411 */
412
413 return true;
414}
415
79e53945
JB
416static void intel_lvds_mode_set(struct drm_encoder *encoder,
417 struct drm_display_mode *mode,
418 struct drm_display_mode *adjusted_mode)
419{
79e53945
JB
420 /*
421 * The LVDS pin pair will already have been turned on in the
422 * intel_crtc_mode_set since it has a large impact on the DPLL
423 * settings.
424 */
79e53945
JB
425}
426
427/**
428 * Detect the LVDS connection.
429 *
b42d4c5c
JB
430 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
431 * connected and closed means disconnected. We also send hotplug events as
432 * needed, using lid status notification from the input layer.
79e53945 433 */
7b334fcb 434static enum drm_connector_status
930a9e28 435intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 436{
7b9c5abe 437 struct drm_device *dev = connector->dev;
6ee3b5a1 438 enum drm_connector_status status;
b42d4c5c 439
fe16d949
CW
440 status = intel_panel_detect(dev);
441 if (status != connector_status_unknown)
442 return status;
01fe9dbd 443
6ee3b5a1 444 return connector_status_connected;
79e53945
JB
445}
446
447/**
448 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
449 */
450static int intel_lvds_get_modes(struct drm_connector *connector)
451{
29b99b48 452 struct intel_lvds_encoder *lvds_encoder = intel_attached_lvds(connector);
79e53945 453 struct drm_device *dev = connector->dev;
788319d4 454 struct drm_display_mode *mode;
79e53945 455
29b99b48
JN
456 if (lvds_encoder->edid)
457 return drm_add_edid_modes(connector, lvds_encoder->edid);
79e53945 458
29b99b48 459 mode = drm_mode_duplicate(dev, lvds_encoder->fixed_mode);
311bd68e 460 if (mode == NULL)
788319d4 461 return 0;
79e53945 462
788319d4
CW
463 drm_mode_probed_add(connector, mode);
464 return 1;
79e53945
JB
465}
466
0544edfd
TB
467static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
468{
bc0daf48 469 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
470 return 1;
471}
472
473/* The GPU hangs up on these systems if modeset is performed on LID open */
474static const struct dmi_system_id intel_no_modeset_on_lid[] = {
475 {
476 .callback = intel_no_modeset_on_lid_dmi_callback,
477 .ident = "Toshiba Tecra A11",
478 .matches = {
479 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
480 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
481 },
482 },
483
484 { } /* terminating entry */
485};
486
c9354c85
LT
487/*
488 * Lid events. Note the use of 'modeset_on_lid':
489 * - we set it on lid close, and reset it on open
490 * - we use it as a "only once" bit (ie we ignore
491 * duplicate events where it was already properly
492 * set/reset)
493 * - the suspend/resume paths will also set it to
494 * zero, since they restore the mode ("lid open").
495 */
c1c7af60
JB
496static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
497 void *unused)
498{
499 struct drm_i915_private *dev_priv =
500 container_of(nb, struct drm_i915_private, lid_notifier);
501 struct drm_device *dev = dev_priv->dev;
a2565377 502 struct drm_connector *connector = dev_priv->int_lvds_connector;
c1c7af60 503
2fb4e61d
AW
504 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
505 return NOTIFY_OK;
506
a2565377
ZY
507 /*
508 * check and update the status of LVDS connector after receiving
509 * the LID nofication event.
510 */
511 if (connector)
7b334fcb 512 connector->status = connector->funcs->detect(connector,
930a9e28 513 false);
7b334fcb 514
0544edfd
TB
515 /* Don't force modeset on machines where it causes a GPU lockup */
516 if (dmi_check_system(intel_no_modeset_on_lid))
517 return NOTIFY_OK;
c9354c85
LT
518 if (!acpi_lid_open()) {
519 dev_priv->modeset_on_lid = 1;
520 return NOTIFY_OK;
06891e27 521 }
c1c7af60 522
c9354c85
LT
523 if (!dev_priv->modeset_on_lid)
524 return NOTIFY_OK;
525
526 dev_priv->modeset_on_lid = 0;
527
528 mutex_lock(&dev->mode_config.mutex);
3b7a89fc 529 intel_modeset_check_state(dev);
c9354c85 530 mutex_unlock(&dev->mode_config.mutex);
06324194 531
c1c7af60
JB
532 return NOTIFY_OK;
533}
534
79e53945
JB
535/**
536 * intel_lvds_destroy - unregister and free LVDS structures
537 * @connector: connector to free
538 *
539 * Unregister the DDC bus for this connector then free the driver private
540 * structure.
541 */
542static void intel_lvds_destroy(struct drm_connector *connector)
543{
c1c7af60 544 struct drm_device *dev = connector->dev;
c1c7af60 545 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 546
aaa6fd2a
MG
547 intel_panel_destroy_backlight(dev);
548
c1c7af60
JB
549 if (dev_priv->lid_notifier.notifier_call)
550 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB
551 drm_sysfs_connector_remove(connector);
552 drm_connector_cleanup(connector);
553 kfree(connector);
554}
555
335041ed
JB
556static int intel_lvds_set_property(struct drm_connector *connector,
557 struct drm_property *property,
558 uint64_t value)
559{
29b99b48 560 struct intel_lvds_encoder *lvds_encoder = intel_attached_lvds(connector);
3fbe18d6 561 struct drm_device *dev = connector->dev;
3fbe18d6 562
788319d4 563 if (property == dev->mode_config.scaling_mode_property) {
29b99b48 564 struct drm_crtc *crtc = lvds_encoder->base.base.crtc;
bb8a3560 565
53bd8389
JB
566 if (value == DRM_MODE_SCALE_NONE) {
567 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 568 return -EINVAL;
3fbe18d6 569 }
788319d4 570
29b99b48 571 if (lvds_encoder->fitting_mode == value) {
3fbe18d6
ZY
572 /* the LVDS scaling property is not changed */
573 return 0;
574 }
29b99b48 575 lvds_encoder->fitting_mode = value;
3fbe18d6
ZY
576 if (crtc && crtc->enabled) {
577 /*
578 * If the CRTC is enabled, the display will be changed
579 * according to the new panel fitting mode.
580 */
a6778b3c
DV
581 intel_set_mode(crtc, &crtc->mode,
582 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
583 }
584 }
585
335041ed
JB
586 return 0;
587}
588
79e53945 589static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 590 .mode_fixup = intel_lvds_mode_fixup,
79e53945 591 .mode_set = intel_lvds_mode_set,
1f703855 592 .disable = intel_encoder_noop,
79e53945
JB
593};
594
595static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
596 .get_modes = intel_lvds_get_modes,
597 .mode_valid = intel_lvds_mode_valid,
df0e9248 598 .best_encoder = intel_best_encoder,
79e53945
JB
599};
600
601static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 602 .dpms = intel_connector_dpms,
79e53945
JB
603 .detect = intel_lvds_detect,
604 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 605 .set_property = intel_lvds_set_property,
79e53945
JB
606 .destroy = intel_lvds_destroy,
607};
608
79e53945 609static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 610 .destroy = intel_encoder_destroy,
79e53945
JB
611};
612
425d244c
JW
613static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
614{
bc0daf48 615 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
616 return 1;
617}
79e53945 618
425d244c 619/* These systems claim to have LVDS, but really don't */
93c05f22 620static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
621 {
622 .callback = intel_no_lvds_dmi_callback,
623 .ident = "Apple Mac Mini (Core series)",
624 .matches = {
98acd46f 625 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
626 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
627 },
628 },
629 {
630 .callback = intel_no_lvds_dmi_callback,
631 .ident = "Apple Mac Mini (Core 2 series)",
632 .matches = {
98acd46f 633 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
634 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
635 },
636 },
637 {
638 .callback = intel_no_lvds_dmi_callback,
639 .ident = "MSI IM-945GSE-A",
640 .matches = {
641 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
642 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
643 },
644 },
645 {
646 .callback = intel_no_lvds_dmi_callback,
647 .ident = "Dell Studio Hybrid",
648 .matches = {
649 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
650 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
651 },
652 },
70aa96ca
JW
653 {
654 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
655 .ident = "Dell OptiPlex FX170",
656 .matches = {
657 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
658 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
659 },
660 },
661 {
662 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
663 .ident = "AOpen Mini PC",
664 .matches = {
665 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
666 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
667 },
668 },
ed8c754b
TV
669 {
670 .callback = intel_no_lvds_dmi_callback,
671 .ident = "AOpen Mini PC MP915",
672 .matches = {
673 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
674 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
675 },
676 },
22ab70d3
KP
677 {
678 .callback = intel_no_lvds_dmi_callback,
679 .ident = "AOpen i915GMm-HFS",
680 .matches = {
681 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
682 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
683 },
684 },
e57b6886
DV
685 {
686 .callback = intel_no_lvds_dmi_callback,
687 .ident = "AOpen i45GMx-I",
688 .matches = {
689 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
690 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
691 },
692 },
fa0864b2
MC
693 {
694 .callback = intel_no_lvds_dmi_callback,
695 .ident = "Aopen i945GTt-VFA",
696 .matches = {
697 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
698 },
699 },
9875557e
SB
700 {
701 .callback = intel_no_lvds_dmi_callback,
702 .ident = "Clientron U800",
703 .matches = {
704 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
705 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
706 },
707 },
6a574b5b 708 {
44306ab3
JS
709 .callback = intel_no_lvds_dmi_callback,
710 .ident = "Clientron E830",
711 .matches = {
712 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
713 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
714 },
715 },
716 {
6a574b5b
HG
717 .callback = intel_no_lvds_dmi_callback,
718 .ident = "Asus EeeBox PC EB1007",
719 .matches = {
720 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
721 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
722 },
723 },
0999bbe0
AJ
724 {
725 .callback = intel_no_lvds_dmi_callback,
726 .ident = "Asus AT5NM10T-I",
727 .matches = {
728 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
729 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
730 },
731 },
33471119
JBG
732 {
733 .callback = intel_no_lvds_dmi_callback,
734 .ident = "Hewlett-Packard HP t5740e Thin Client",
735 .matches = {
736 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
737 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
738 },
739 },
f5b8a7ed
MG
740 {
741 .callback = intel_no_lvds_dmi_callback,
742 .ident = "Hewlett-Packard t5745",
743 .matches = {
744 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 745 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
746 },
747 },
748 {
749 .callback = intel_no_lvds_dmi_callback,
750 .ident = "Hewlett-Packard st5747",
751 .matches = {
752 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 753 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
754 },
755 },
97effadb
AA
756 {
757 .callback = intel_no_lvds_dmi_callback,
758 .ident = "MSI Wind Box DC500",
759 .matches = {
760 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
761 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
762 },
763 },
9756fe38
SS
764 {
765 .callback = intel_no_lvds_dmi_callback,
766 .ident = "ZOTAC ZBOXSD-ID12/ID13",
767 .matches = {
768 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
769 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
770 },
771 },
a51d4ed0
CW
772 {
773 .callback = intel_no_lvds_dmi_callback,
774 .ident = "Gigabyte GA-D525TUD",
775 .matches = {
776 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
777 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
778 },
779 },
425d244c
JW
780
781 { } /* terminating entry */
782};
79e53945 783
18f9ed12
ZY
784/**
785 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
786 * @dev: drm device
787 * @connector: LVDS connector
788 *
789 * Find the reduced downclock for LVDS in EDID.
790 */
791static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
792 struct drm_display_mode *fixed_mode,
793 struct drm_connector *connector)
18f9ed12
ZY
794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 796 struct drm_display_mode *scan;
18f9ed12
ZY
797 int temp_downclock;
798
788319d4 799 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
800 list_for_each_entry(scan, &connector->probed_modes, head) {
801 /*
802 * If one mode has the same resolution with the fixed_panel
803 * mode while they have the different refresh rate, it means
804 * that the reduced downclock is found for the LVDS. In such
805 * case we can set the different FPx0/1 to dynamically select
806 * between low and high frequency.
807 */
788319d4
CW
808 if (scan->hdisplay == fixed_mode->hdisplay &&
809 scan->hsync_start == fixed_mode->hsync_start &&
810 scan->hsync_end == fixed_mode->hsync_end &&
811 scan->htotal == fixed_mode->htotal &&
812 scan->vdisplay == fixed_mode->vdisplay &&
813 scan->vsync_start == fixed_mode->vsync_start &&
814 scan->vsync_end == fixed_mode->vsync_end &&
815 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
816 if (scan->clock < temp_downclock) {
817 /*
818 * The downclock is already found. But we
819 * expect to find the lower downclock.
820 */
821 temp_downclock = scan->clock;
822 }
823 }
824 }
788319d4 825 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
826 /* We found the downclock for LVDS. */
827 dev_priv->lvds_downclock_avail = 1;
828 dev_priv->lvds_downclock = temp_downclock;
829 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
830 "Normal clock %dKhz, downclock %dKhz\n",
831 fixed_mode->clock, temp_downclock);
18f9ed12 832 }
18f9ed12
ZY
833}
834
7cf4f69d
ZY
835/*
836 * Enumerate the child dev array parsed from VBT to check whether
837 * the LVDS is present.
838 * If it is present, return 1.
839 * If it is not present, return false.
840 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 841 */
270eea0f
CW
842static bool lvds_is_present_in_vbt(struct drm_device *dev,
843 u8 *i2c_pin)
7cf4f69d
ZY
844{
845 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 846 int i;
7cf4f69d
ZY
847
848 if (!dev_priv->child_dev_num)
425904dd 849 return true;
7cf4f69d 850
7cf4f69d 851 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
852 struct child_device_config *child = dev_priv->child_dev + i;
853
854 /* If the device type is not LFP, continue.
855 * We have to check both the new identifiers as well as the
856 * old for compatibility with some BIOSes.
7cf4f69d 857 */
425904dd
CW
858 if (child->device_type != DEVICE_TYPE_INT_LFP &&
859 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
860 continue;
861
3bd7d909
DK
862 if (intel_gmbus_is_port_valid(child->i2c_pin))
863 *i2c_pin = child->i2c_pin;
270eea0f 864
425904dd
CW
865 /* However, we cannot trust the BIOS writers to populate
866 * the VBT correctly. Since LVDS requires additional
867 * information from AIM blocks, a non-zero addin offset is
868 * a good indicator that the LVDS is actually present.
7cf4f69d 869 */
425904dd
CW
870 if (child->addin_offset)
871 return true;
872
873 /* But even then some BIOS writers perform some black magic
874 * and instantiate the device without reference to any
875 * additional data. Trust that if the VBT was written into
876 * the OpRegion then they have validated the LVDS's existence.
877 */
878 if (dev_priv->opregion.vbt)
879 return true;
7cf4f69d 880 }
425904dd
CW
881
882 return false;
7cf4f69d
ZY
883}
884
f3cfcba6
CW
885static bool intel_lvds_supported(struct drm_device *dev)
886{
887 /* With the introduction of the PCH we gained a dedicated
888 * LVDS presence pin, use it. */
889 if (HAS_PCH_SPLIT(dev))
890 return true;
891
892 /* Otherwise LVDS was only attached to mobile products,
893 * except for the inglorious 830gm */
894 return IS_MOBILE(dev) && !IS_I830(dev);
895}
896
79e53945
JB
897/**
898 * intel_lvds_init - setup LVDS connectors on this device
899 * @dev: drm device
900 *
901 * Create the connector, register the LVDS DDC bus, and try to figure out what
902 * modes we can display on the LVDS panel (if present).
903 */
c5d1b51d 904bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
905{
906 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 907 struct intel_lvds_encoder *lvds_encoder;
21d40d37 908 struct intel_encoder *intel_encoder;
bb8a3560 909 struct intel_connector *intel_connector;
79e53945
JB
910 struct drm_connector *connector;
911 struct drm_encoder *encoder;
912 struct drm_display_mode *scan; /* *modes, *bios_mode; */
913 struct drm_crtc *crtc;
914 u32 lvds;
270eea0f
CW
915 int pipe;
916 u8 pin;
79e53945 917
f3cfcba6
CW
918 if (!intel_lvds_supported(dev))
919 return false;
920
425d244c
JW
921 /* Skip init on machines we know falsely report LVDS */
922 if (dmi_check_system(intel_no_lvds))
c5d1b51d 923 return false;
565dcd46 924
270eea0f
CW
925 pin = GMBUS_PORT_PANEL;
926 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 927 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 928 return false;
38b3037e 929 }
e99da35f 930
c619eed4 931 if (HAS_PCH_SPLIT(dev)) {
541998a1 932 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 933 return false;
5ceb0f9b 934 if (dev_priv->edp.support) {
28c97730 935 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 936 return false;
32f9d658 937 }
541998a1
ZW
938 }
939
29b99b48
JN
940 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
941 if (!lvds_encoder)
c5d1b51d 942 return false;
79e53945 943
bb8a3560
ZW
944 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
945 if (!intel_connector) {
29b99b48 946 kfree(lvds_encoder);
c5d1b51d 947 return false;
bb8a3560
ZW
948 }
949
e9e331a8 950 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 951 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
952 }
953
29b99b48 954 intel_encoder = &lvds_encoder->base;
4ef69c7a 955 encoder = &intel_encoder->base;
ea5b213a 956 connector = &intel_connector->base;
bb8a3560 957 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
958 DRM_MODE_CONNECTOR_LVDS);
959
4ef69c7a 960 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
961 DRM_MODE_ENCODER_LVDS);
962
c22834ec
DV
963 intel_encoder->enable = intel_enable_lvds;
964 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
965 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
966 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 967
df0e9248 968 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 969 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 970
66a9278e 971 intel_encoder->cloneable = false;
27f8227b
JB
972 if (HAS_PCH_SPLIT(dev))
973 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
974 else if (IS_GEN4(dev))
975 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
976 else
977 intel_encoder->crtc_mask = (1 << 1);
978
79e53945
JB
979 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
980 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
981 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
982 connector->interlace_allowed = false;
983 connector->doublescan_allowed = false;
984
3fbe18d6
ZY
985 /* create the scaling mode property */
986 drm_mode_create_scaling_mode_property(dev);
987 /*
988 * the initial panel fitting mode will be FULL_SCREEN.
989 */
79e53945 990
bb8a3560 991 drm_connector_attach_property(&intel_connector->base,
3fbe18d6 992 dev->mode_config.scaling_mode_property,
dd1ea37d 993 DRM_MODE_SCALE_ASPECT);
29b99b48 994 lvds_encoder->fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
995 /*
996 * LVDS discovery:
997 * 1) check for EDID on DDC
998 * 2) check for VBT data
999 * 3) check to see if LVDS is already on
1000 * if none of the above, no panel
1001 * 4) make sure lid is open
1002 * if closed, act like it's not there for now
1003 */
1004
79e53945
JB
1005 /*
1006 * Attempt to get the fixed panel mode from DDC. Assume that the
1007 * preferred mode is the right one.
1008 */
29b99b48
JN
1009 lvds_encoder->edid = drm_get_edid(connector,
1010 intel_gmbus_get_adapter(dev_priv, pin));
1011 if (lvds_encoder->edid) {
1012 if (drm_add_edid_modes(connector, lvds_encoder->edid)) {
3f8ff0e7 1013 drm_mode_connector_update_edid_property(connector,
29b99b48 1014 lvds_encoder->edid);
3f8ff0e7 1015 } else {
29b99b48
JN
1016 kfree(lvds_encoder->edid);
1017 lvds_encoder->edid = NULL;
3f8ff0e7
CW
1018 }
1019 }
29b99b48 1020 if (!lvds_encoder->edid) {
788319d4
CW
1021 /* Didn't get an EDID, so
1022 * Set wide sync ranges so we get all modes
1023 * handed to valid_mode for checking
1024 */
1025 connector->display_info.min_vfreq = 0;
1026 connector->display_info.max_vfreq = 200;
1027 connector->display_info.min_hfreq = 0;
1028 connector->display_info.max_hfreq = 200;
1029 }
79e53945
JB
1030
1031 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1032 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
29b99b48
JN
1033 lvds_encoder->fixed_mode = drm_mode_duplicate(dev, scan);
1034 intel_find_lvds_downclock(dev, lvds_encoder->fixed_mode,
788319d4 1035 connector);
565dcd46 1036 goto out;
79e53945 1037 }
79e53945
JB
1038 }
1039
1040 /* Failed to get EDID, what about VBT? */
88631706 1041 if (dev_priv->lfp_lvds_vbt_mode) {
29b99b48 1042 lvds_encoder->fixed_mode =
88631706 1043 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
29b99b48
JN
1044 if (lvds_encoder->fixed_mode) {
1045 lvds_encoder->fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1046 goto out;
1047 }
79e53945
JB
1048 }
1049
1050 /*
1051 * If we didn't get EDID, try checking if the panel is already turned
1052 * on. If so, assume that whatever is currently programmed is the
1053 * correct mode.
1054 */
541998a1 1055
f2b115e6 1056 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1057 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1058 goto failed;
1059
79e53945
JB
1060 lvds = I915_READ(LVDS);
1061 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1062 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1063
1064 if (crtc && (lvds & LVDS_PORT_EN)) {
29b99b48
JN
1065 lvds_encoder->fixed_mode = intel_crtc_mode_get(dev, crtc);
1066 if (lvds_encoder->fixed_mode) {
1067 lvds_encoder->fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1068 goto out;
79e53945
JB
1069 }
1070 }
1071
1072 /* If we still don't have a mode after all that, give up. */
29b99b48 1073 if (!lvds_encoder->fixed_mode)
79e53945
JB
1074 goto failed;
1075
79e53945 1076out:
24ded204
DV
1077 /*
1078 * Unlock registers and just
1079 * leave them unlocked
1080 */
c619eed4 1081 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1082 I915_WRITE(PCH_PP_CONTROL,
1083 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1084 } else {
ed10fca9
KP
1085 I915_WRITE(PP_CONTROL,
1086 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1087 }
c1c7af60
JB
1088 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1089 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
28c97730 1090 DRM_DEBUG_KMS("lid notifier registration failed\n");
c1c7af60
JB
1091 dev_priv->lid_notifier.notifier_call = NULL;
1092 }
a2565377
ZY
1093 /* keep the LVDS connector */
1094 dev_priv->int_lvds_connector = connector;
79e53945 1095 drm_sysfs_connector_add(connector);
aaa6fd2a
MG
1096
1097 intel_panel_setup_backlight(dev);
1098
c5d1b51d 1099 return true;
79e53945
JB
1100
1101failed:
8a4c47f3 1102 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1103 drm_connector_cleanup(connector);
1991bdfa 1104 drm_encoder_cleanup(encoder);
29b99b48 1105 kfree(lvds_encoder);
bb8a3560 1106 kfree(intel_connector);
c5d1b51d 1107 return false;
79e53945 1108}
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