drm/i915: force restore on lid open
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
3fbe18d6
ZY
52 u32 pfit_control;
53 u32 pfit_pgm_ratios;
e9e331a8 54 bool pfit_dirty;
788319d4 55
62165e0d 56 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
57};
58
29b99b48 59static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 60{
29b99b48 61 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
62}
63
c7362c4d 64static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 65{
c7362c4d 66 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
67}
68
b1dc332c
DV
69static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
70 enum pipe *pipe)
71{
72 struct drm_device *dev = encoder->base.dev;
73 struct drm_i915_private *dev_priv = dev->dev_private;
74 u32 lvds_reg, tmp;
75
76 if (HAS_PCH_SPLIT(dev)) {
77 lvds_reg = PCH_LVDS;
78 } else {
79 lvds_reg = LVDS;
80 }
81
82 tmp = I915_READ(lvds_reg);
83
84 if (!(tmp & LVDS_PORT_EN))
85 return false;
86
87 if (HAS_PCH_CPT(dev))
88 *pipe = PORT_TO_PIPE_CPT(tmp);
89 else
90 *pipe = PORT_TO_PIPE(tmp);
91
92 return true;
93}
94
79e53945
JB
95/**
96 * Sets the power state for the panel.
97 */
c22834ec 98static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 99{
c22834ec 100 struct drm_device *dev = encoder->base.dev;
29b99b48 101 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 102 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 103 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 104 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 105
c619eed4 106 if (HAS_PCH_SPLIT(dev)) {
541998a1 107 ctl_reg = PCH_PP_CONTROL;
469d1296 108 lvds_reg = PCH_LVDS;
de842eff 109 stat_reg = PCH_PP_STATUS;
541998a1
ZW
110 } else {
111 ctl_reg = PP_CONTROL;
469d1296 112 lvds_reg = LVDS;
de842eff 113 stat_reg = PP_STATUS;
541998a1 114 }
79e53945 115
2a1292fd 116 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 117
29b99b48 118 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
119 /*
120 * Enable automatic panel scaling so that non-native modes
121 * fill the screen. The panel fitter should only be
122 * adjusted whilst the pipe is disabled, according to
123 * register description and PRM.
124 */
125 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
126 lvds_encoder->pfit_control,
127 lvds_encoder->pfit_pgm_ratios);
de842eff 128
29b99b48
JN
129 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
130 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
131 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
132 }
133
134 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
135 POSTING_READ(lvds_reg);
de842eff
KP
136 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
137 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 138
24ded204 139 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
140}
141
c22834ec 142static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 143{
c22834ec 144 struct drm_device *dev = encoder->base.dev;
29b99b48 145 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 146 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 147 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
148
149 if (HAS_PCH_SPLIT(dev)) {
150 ctl_reg = PCH_PP_CONTROL;
151 lvds_reg = PCH_LVDS;
de842eff 152 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
153 } else {
154 ctl_reg = PP_CONTROL;
155 lvds_reg = LVDS;
de842eff 156 stat_reg = PP_STATUS;
2a1292fd
CW
157 }
158
47356eb6 159 intel_panel_disable_backlight(dev);
2a1292fd
CW
160
161 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
162 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
163 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 164
29b99b48 165 if (lvds_encoder->pfit_control) {
2a1292fd 166 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 167 lvds_encoder->pfit_dirty = true;
79e53945 168 }
2a1292fd
CW
169
170 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 171 POSTING_READ(lvds_reg);
79e53945
JB
172}
173
79e53945
JB
174static int intel_lvds_mode_valid(struct drm_connector *connector,
175 struct drm_display_mode *mode)
176{
dd06f90e
JN
177 struct intel_connector *intel_connector = to_intel_connector(connector);
178 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 179
788319d4
CW
180 if (mode->hdisplay > fixed_mode->hdisplay)
181 return MODE_PANEL;
182 if (mode->vdisplay > fixed_mode->vdisplay)
183 return MODE_PANEL;
79e53945
JB
184
185 return MODE_OK;
186}
187
49be663f
CW
188static void
189centre_horizontally(struct drm_display_mode *mode,
190 int width)
191{
192 u32 border, sync_pos, blank_width, sync_width;
193
194 /* keep the hsync and hblank widths constant */
195 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
196 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
197 sync_pos = (blank_width - sync_width + 1) / 2;
198
199 border = (mode->hdisplay - width + 1) / 2;
200 border += border & 1; /* make the border even */
201
202 mode->crtc_hdisplay = width;
203 mode->crtc_hblank_start = width + border;
204 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
205
206 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
207 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
208
209 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
210}
211
212static void
213centre_vertically(struct drm_display_mode *mode,
214 int height)
215{
216 u32 border, sync_pos, blank_width, sync_width;
217
218 /* keep the vsync and vblank widths constant */
219 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
220 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
221 sync_pos = (blank_width - sync_width + 1) / 2;
222
223 border = (mode->vdisplay - height + 1) / 2;
224
225 mode->crtc_vdisplay = height;
226 mode->crtc_vblank_start = height + border;
227 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
228
229 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
230 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
231
232 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
233}
234
235static inline u32 panel_fitter_scaling(u32 source, u32 target)
236{
237 /*
238 * Floating point operation is not supported. So the FACTOR
239 * is defined, which can avoid the floating point computation
240 * when calculating the panel ratio.
241 */
242#define ACCURACY 12
243#define FACTOR (1 << ACCURACY)
244 u32 ratio = source * FACTOR / target;
245 return (FACTOR * ratio + FACTOR/2) / FACTOR;
246}
247
79e53945 248static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 249 const struct drm_display_mode *mode,
79e53945
JB
250 struct drm_display_mode *adjusted_mode)
251{
252 struct drm_device *dev = encoder->dev;
253 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 254 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
4d891523
JN
255 struct intel_connector *intel_connector =
256 &lvds_encoder->attached_connector->base;
29b99b48 257 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 258 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 259 int pipe;
79e53945
JB
260
261 /* Should never happen!! */
a6c45cf0 262 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 263 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
264 return false;
265 }
266
29b99b48 267 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 268 return false;
1d8e1c75 269
79e53945 270 /*
71677043 271 * We have timings from the BIOS for the panel, put them in
79e53945
JB
272 * to the adjusted mode. The CRTC will be set up for this mode,
273 * with the panel scaling set up to source from the H/VDisplay
274 * of the original mode.
275 */
4d891523 276 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 277 adjusted_mode);
1d8e1c75
CW
278
279 if (HAS_PCH_SPLIT(dev)) {
4d891523
JN
280 intel_pch_panel_fitting(dev,
281 intel_connector->panel.fitting_mode,
1d8e1c75
CW
282 mode, adjusted_mode);
283 return true;
284 }
79e53945 285
3fbe18d6
ZY
286 /* Native modes don't need fitting */
287 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 288 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 289 goto out;
3fbe18d6
ZY
290
291 /* 965+ wants fuzzy fitting */
a6c45cf0 292 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
293 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
294 PFIT_FILTER_FUZZY);
295
3fbe18d6
ZY
296 /*
297 * Enable automatic panel scaling for non-native modes so that they fill
298 * the screen. Should be enabled before the pipe is enabled, according
299 * to register description and PRM.
300 * Change the value here to see the borders for debugging
301 */
9db4a9c7
JB
302 for_each_pipe(pipe)
303 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 304
f9bef081
DV
305 drm_mode_set_crtcinfo(adjusted_mode, 0);
306
4d891523 307 switch (intel_connector->panel.fitting_mode) {
53bd8389 308 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
309 /*
310 * For centered modes, we have to calculate border widths &
311 * heights and modify the values programmed into the CRTC.
312 */
49be663f
CW
313 centre_horizontally(adjusted_mode, mode->hdisplay);
314 centre_vertically(adjusted_mode, mode->vdisplay);
315 border = LVDS_BORDER_ENABLE;
3fbe18d6 316 break;
49be663f 317
3fbe18d6 318 case DRM_MODE_SCALE_ASPECT:
49be663f 319 /* Scale but preserve the aspect ratio */
a6c45cf0 320 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
321 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
322 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
323
3fbe18d6 324 /* 965+ is easy, it does everything in hw */
49be663f 325 if (scaled_width > scaled_height)
257e48f1 326 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 327 else if (scaled_width < scaled_height)
257e48f1
CW
328 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
329 else if (adjusted_mode->hdisplay != mode->hdisplay)
330 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 331 } else {
49be663f
CW
332 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
333 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
334 /*
335 * For earlier chips we have to calculate the scaling
336 * ratio by hand and program it into the
337 * PFIT_PGM_RATIO register
338 */
49be663f
CW
339 if (scaled_width > scaled_height) { /* pillar */
340 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
341
342 border = LVDS_BORDER_ENABLE;
343 if (mode->vdisplay != adjusted_mode->vdisplay) {
344 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
345 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
346 bits << PFIT_VERT_SCALE_SHIFT);
347 pfit_control |= (PFIT_ENABLE |
348 VERT_INTERP_BILINEAR |
349 HORIZ_INTERP_BILINEAR);
350 }
351 } else if (scaled_width < scaled_height) { /* letter */
352 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
353
354 border = LVDS_BORDER_ENABLE;
355 if (mode->hdisplay != adjusted_mode->hdisplay) {
356 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
357 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
358 bits << PFIT_VERT_SCALE_SHIFT);
359 pfit_control |= (PFIT_ENABLE |
360 VERT_INTERP_BILINEAR |
361 HORIZ_INTERP_BILINEAR);
362 }
363 } else
364 /* Aspects match, Let hw scale both directions */
365 pfit_control |= (PFIT_ENABLE |
366 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
367 VERT_INTERP_BILINEAR |
368 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
369 }
370 break;
371
372 case DRM_MODE_SCALE_FULLSCREEN:
373 /*
374 * Full scaling, even if it changes the aspect ratio.
375 * Fortunately this is all done for us in hw.
376 */
257e48f1
CW
377 if (mode->vdisplay != adjusted_mode->vdisplay ||
378 mode->hdisplay != adjusted_mode->hdisplay) {
379 pfit_control |= PFIT_ENABLE;
380 if (INTEL_INFO(dev)->gen >= 4)
381 pfit_control |= PFIT_SCALING_AUTO;
382 else
383 pfit_control |= (VERT_AUTO_SCALE |
384 VERT_INTERP_BILINEAR |
385 HORIZ_AUTO_SCALE |
386 HORIZ_INTERP_BILINEAR);
387 }
3fbe18d6 388 break;
49be663f 389
3fbe18d6
ZY
390 default:
391 break;
392 }
393
394out:
72389a33 395 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
396 if ((pfit_control & PFIT_ENABLE) == 0) {
397 pfit_control = 0;
398 pfit_pgm_ratios = 0;
399 }
72389a33
CW
400
401 /* Make sure pre-965 set dither correctly */
402 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
403 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
404
29b99b48
JN
405 if (pfit_control != lvds_encoder->pfit_control ||
406 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
407 lvds_encoder->pfit_control = pfit_control;
408 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
409 lvds_encoder->pfit_dirty = true;
e9e331a8 410 }
49be663f
CW
411 dev_priv->lvds_border_bits = border;
412
79e53945
JB
413 /*
414 * XXX: It would be nice to support lower refresh rates on the
415 * panels to reduce power consumption, and perhaps match the
416 * user's requested refresh rate.
417 */
418
419 return true;
420}
421
79e53945
JB
422static void intel_lvds_mode_set(struct drm_encoder *encoder,
423 struct drm_display_mode *mode,
424 struct drm_display_mode *adjusted_mode)
425{
79e53945
JB
426 /*
427 * The LVDS pin pair will already have been turned on in the
428 * intel_crtc_mode_set since it has a large impact on the DPLL
429 * settings.
430 */
79e53945
JB
431}
432
433/**
434 * Detect the LVDS connection.
435 *
b42d4c5c
JB
436 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
437 * connected and closed means disconnected. We also send hotplug events as
438 * needed, using lid status notification from the input layer.
79e53945 439 */
7b334fcb 440static enum drm_connector_status
930a9e28 441intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 442{
7b9c5abe 443 struct drm_device *dev = connector->dev;
6ee3b5a1 444 enum drm_connector_status status;
b42d4c5c 445
fe16d949
CW
446 status = intel_panel_detect(dev);
447 if (status != connector_status_unknown)
448 return status;
01fe9dbd 449
6ee3b5a1 450 return connector_status_connected;
79e53945
JB
451}
452
453/**
454 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
455 */
456static int intel_lvds_get_modes(struct drm_connector *connector)
457{
62165e0d 458 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 459 struct drm_device *dev = connector->dev;
788319d4 460 struct drm_display_mode *mode;
79e53945 461
9cd300e0 462 /* use cached edid if we have one */
2aa4f099 463 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 464 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 465
dd06f90e 466 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 467 if (mode == NULL)
788319d4 468 return 0;
79e53945 469
788319d4
CW
470 drm_mode_probed_add(connector, mode);
471 return 1;
79e53945
JB
472}
473
0544edfd
TB
474static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
475{
bc0daf48 476 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
477 return 1;
478}
479
480/* The GPU hangs up on these systems if modeset is performed on LID open */
481static const struct dmi_system_id intel_no_modeset_on_lid[] = {
482 {
483 .callback = intel_no_modeset_on_lid_dmi_callback,
484 .ident = "Toshiba Tecra A11",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
487 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
488 },
489 },
490
491 { } /* terminating entry */
492};
493
c9354c85
LT
494/*
495 * Lid events. Note the use of 'modeset_on_lid':
496 * - we set it on lid close, and reset it on open
497 * - we use it as a "only once" bit (ie we ignore
498 * duplicate events where it was already properly
499 * set/reset)
500 * - the suspend/resume paths will also set it to
501 * zero, since they restore the mode ("lid open").
502 */
c1c7af60
JB
503static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
504 void *unused)
505{
db1740a0
JN
506 struct intel_lvds_connector *lvds_connector =
507 container_of(nb, struct intel_lvds_connector, lid_notifier);
508 struct drm_connector *connector = &lvds_connector->base.base;
509 struct drm_device *dev = connector->dev;
510 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 511
2fb4e61d
AW
512 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
513 return NOTIFY_OK;
514
a2565377
ZY
515 /*
516 * check and update the status of LVDS connector after receiving
517 * the LID nofication event.
518 */
db1740a0 519 connector->status = connector->funcs->detect(connector, false);
7b334fcb 520
0544edfd
TB
521 /* Don't force modeset on machines where it causes a GPU lockup */
522 if (dmi_check_system(intel_no_modeset_on_lid))
523 return NOTIFY_OK;
c9354c85
LT
524 if (!acpi_lid_open()) {
525 dev_priv->modeset_on_lid = 1;
526 return NOTIFY_OK;
06891e27 527 }
c1c7af60 528
c9354c85
LT
529 if (!dev_priv->modeset_on_lid)
530 return NOTIFY_OK;
531
532 dev_priv->modeset_on_lid = 0;
533
534 mutex_lock(&dev->mode_config.mutex);
45e2b5f6 535 intel_modeset_setup_hw_state(dev, true);
c9354c85 536 mutex_unlock(&dev->mode_config.mutex);
06324194 537
c1c7af60
JB
538 return NOTIFY_OK;
539}
540
79e53945
JB
541/**
542 * intel_lvds_destroy - unregister and free LVDS structures
543 * @connector: connector to free
544 *
545 * Unregister the DDC bus for this connector then free the driver private
546 * structure.
547 */
548static void intel_lvds_destroy(struct drm_connector *connector)
549{
db1740a0
JN
550 struct intel_lvds_connector *lvds_connector =
551 to_lvds_connector(connector);
79e53945 552
db1740a0
JN
553 if (lvds_connector->lid_notifier.notifier_call)
554 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 555
9cd300e0
JN
556 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
557 kfree(lvds_connector->base.edid);
558
db1740a0 559 intel_panel_destroy_backlight(connector->dev);
1d508706 560 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 561
79e53945
JB
562 drm_sysfs_connector_remove(connector);
563 drm_connector_cleanup(connector);
564 kfree(connector);
565}
566
335041ed
JB
567static int intel_lvds_set_property(struct drm_connector *connector,
568 struct drm_property *property,
569 uint64_t value)
570{
4d891523 571 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 572 struct drm_device *dev = connector->dev;
3fbe18d6 573
788319d4 574 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 575 struct drm_crtc *crtc;
bb8a3560 576
53bd8389
JB
577 if (value == DRM_MODE_SCALE_NONE) {
578 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 579 return -EINVAL;
3fbe18d6 580 }
788319d4 581
4d891523 582 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
583 /* the LVDS scaling property is not changed */
584 return 0;
585 }
4d891523 586 intel_connector->panel.fitting_mode = value;
62165e0d
JN
587
588 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
589 if (crtc && crtc->enabled) {
590 /*
591 * If the CRTC is enabled, the display will be changed
592 * according to the new panel fitting mode.
593 */
a6778b3c
DV
594 intel_set_mode(crtc, &crtc->mode,
595 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
596 }
597 }
598
335041ed
JB
599 return 0;
600}
601
79e53945 602static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 603 .mode_fixup = intel_lvds_mode_fixup,
79e53945 604 .mode_set = intel_lvds_mode_set,
1f703855 605 .disable = intel_encoder_noop,
79e53945
JB
606};
607
608static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
609 .get_modes = intel_lvds_get_modes,
610 .mode_valid = intel_lvds_mode_valid,
df0e9248 611 .best_encoder = intel_best_encoder,
79e53945
JB
612};
613
614static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 615 .dpms = intel_connector_dpms,
79e53945
JB
616 .detect = intel_lvds_detect,
617 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 618 .set_property = intel_lvds_set_property,
79e53945
JB
619 .destroy = intel_lvds_destroy,
620};
621
79e53945 622static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 623 .destroy = intel_encoder_destroy,
79e53945
JB
624};
625
425d244c
JW
626static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
627{
bc0daf48 628 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
629 return 1;
630}
79e53945 631
425d244c 632/* These systems claim to have LVDS, but really don't */
93c05f22 633static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
634 {
635 .callback = intel_no_lvds_dmi_callback,
636 .ident = "Apple Mac Mini (Core series)",
637 .matches = {
98acd46f 638 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
639 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
640 },
641 },
642 {
643 .callback = intel_no_lvds_dmi_callback,
644 .ident = "Apple Mac Mini (Core 2 series)",
645 .matches = {
98acd46f 646 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
647 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
648 },
649 },
650 {
651 .callback = intel_no_lvds_dmi_callback,
652 .ident = "MSI IM-945GSE-A",
653 .matches = {
654 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
655 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
656 },
657 },
658 {
659 .callback = intel_no_lvds_dmi_callback,
660 .ident = "Dell Studio Hybrid",
661 .matches = {
662 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
663 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
664 },
665 },
70aa96ca
JW
666 {
667 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
668 .ident = "Dell OptiPlex FX170",
669 .matches = {
670 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
671 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
672 },
673 },
674 {
675 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
676 .ident = "AOpen Mini PC",
677 .matches = {
678 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
679 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
680 },
681 },
ed8c754b
TV
682 {
683 .callback = intel_no_lvds_dmi_callback,
684 .ident = "AOpen Mini PC MP915",
685 .matches = {
686 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
687 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
688 },
689 },
22ab70d3
KP
690 {
691 .callback = intel_no_lvds_dmi_callback,
692 .ident = "AOpen i915GMm-HFS",
693 .matches = {
694 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
695 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
696 },
697 },
e57b6886
DV
698 {
699 .callback = intel_no_lvds_dmi_callback,
700 .ident = "AOpen i45GMx-I",
701 .matches = {
702 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
703 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
704 },
705 },
fa0864b2
MC
706 {
707 .callback = intel_no_lvds_dmi_callback,
708 .ident = "Aopen i945GTt-VFA",
709 .matches = {
710 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
711 },
712 },
9875557e
SB
713 {
714 .callback = intel_no_lvds_dmi_callback,
715 .ident = "Clientron U800",
716 .matches = {
717 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
718 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
719 },
720 },
6a574b5b 721 {
44306ab3
JS
722 .callback = intel_no_lvds_dmi_callback,
723 .ident = "Clientron E830",
724 .matches = {
725 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
726 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
727 },
728 },
729 {
6a574b5b
HG
730 .callback = intel_no_lvds_dmi_callback,
731 .ident = "Asus EeeBox PC EB1007",
732 .matches = {
733 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
734 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
735 },
736 },
0999bbe0
AJ
737 {
738 .callback = intel_no_lvds_dmi_callback,
739 .ident = "Asus AT5NM10T-I",
740 .matches = {
741 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
742 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
743 },
744 },
33471119
JBG
745 {
746 .callback = intel_no_lvds_dmi_callback,
747 .ident = "Hewlett-Packard HP t5740e Thin Client",
748 .matches = {
749 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
750 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
751 },
752 },
f5b8a7ed
MG
753 {
754 .callback = intel_no_lvds_dmi_callback,
755 .ident = "Hewlett-Packard t5745",
756 .matches = {
757 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 758 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
759 },
760 },
761 {
762 .callback = intel_no_lvds_dmi_callback,
763 .ident = "Hewlett-Packard st5747",
764 .matches = {
765 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 766 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
767 },
768 },
97effadb
AA
769 {
770 .callback = intel_no_lvds_dmi_callback,
771 .ident = "MSI Wind Box DC500",
772 .matches = {
773 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
774 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
775 },
776 },
9756fe38
SS
777 {
778 .callback = intel_no_lvds_dmi_callback,
779 .ident = "ZOTAC ZBOXSD-ID12/ID13",
780 .matches = {
781 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
782 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
783 },
784 },
a51d4ed0
CW
785 {
786 .callback = intel_no_lvds_dmi_callback,
787 .ident = "Gigabyte GA-D525TUD",
788 .matches = {
789 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
790 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
791 },
792 },
c31407a3
CW
793 {
794 .callback = intel_no_lvds_dmi_callback,
795 .ident = "Supermicro X7SPA-H",
796 .matches = {
797 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
798 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
799 },
800 },
425d244c
JW
801
802 { } /* terminating entry */
803};
79e53945 804
18f9ed12
ZY
805/**
806 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
807 * @dev: drm device
808 * @connector: LVDS connector
809 *
810 * Find the reduced downclock for LVDS in EDID.
811 */
812static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
813 struct drm_display_mode *fixed_mode,
814 struct drm_connector *connector)
18f9ed12
ZY
815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 817 struct drm_display_mode *scan;
18f9ed12
ZY
818 int temp_downclock;
819
788319d4 820 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
821 list_for_each_entry(scan, &connector->probed_modes, head) {
822 /*
823 * If one mode has the same resolution with the fixed_panel
824 * mode while they have the different refresh rate, it means
825 * that the reduced downclock is found for the LVDS. In such
826 * case we can set the different FPx0/1 to dynamically select
827 * between low and high frequency.
828 */
788319d4
CW
829 if (scan->hdisplay == fixed_mode->hdisplay &&
830 scan->hsync_start == fixed_mode->hsync_start &&
831 scan->hsync_end == fixed_mode->hsync_end &&
832 scan->htotal == fixed_mode->htotal &&
833 scan->vdisplay == fixed_mode->vdisplay &&
834 scan->vsync_start == fixed_mode->vsync_start &&
835 scan->vsync_end == fixed_mode->vsync_end &&
836 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
837 if (scan->clock < temp_downclock) {
838 /*
839 * The downclock is already found. But we
840 * expect to find the lower downclock.
841 */
842 temp_downclock = scan->clock;
843 }
844 }
845 }
788319d4 846 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
847 /* We found the downclock for LVDS. */
848 dev_priv->lvds_downclock_avail = 1;
849 dev_priv->lvds_downclock = temp_downclock;
850 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
851 "Normal clock %dKhz, downclock %dKhz\n",
852 fixed_mode->clock, temp_downclock);
18f9ed12 853 }
18f9ed12
ZY
854}
855
7cf4f69d
ZY
856/*
857 * Enumerate the child dev array parsed from VBT to check whether
858 * the LVDS is present.
859 * If it is present, return 1.
860 * If it is not present, return false.
861 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 862 */
270eea0f
CW
863static bool lvds_is_present_in_vbt(struct drm_device *dev,
864 u8 *i2c_pin)
7cf4f69d
ZY
865{
866 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 867 int i;
7cf4f69d
ZY
868
869 if (!dev_priv->child_dev_num)
425904dd 870 return true;
7cf4f69d 871
7cf4f69d 872 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
873 struct child_device_config *child = dev_priv->child_dev + i;
874
875 /* If the device type is not LFP, continue.
876 * We have to check both the new identifiers as well as the
877 * old for compatibility with some BIOSes.
7cf4f69d 878 */
425904dd
CW
879 if (child->device_type != DEVICE_TYPE_INT_LFP &&
880 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
881 continue;
882
3bd7d909
DK
883 if (intel_gmbus_is_port_valid(child->i2c_pin))
884 *i2c_pin = child->i2c_pin;
270eea0f 885
425904dd
CW
886 /* However, we cannot trust the BIOS writers to populate
887 * the VBT correctly. Since LVDS requires additional
888 * information from AIM blocks, a non-zero addin offset is
889 * a good indicator that the LVDS is actually present.
7cf4f69d 890 */
425904dd
CW
891 if (child->addin_offset)
892 return true;
893
894 /* But even then some BIOS writers perform some black magic
895 * and instantiate the device without reference to any
896 * additional data. Trust that if the VBT was written into
897 * the OpRegion then they have validated the LVDS's existence.
898 */
899 if (dev_priv->opregion.vbt)
900 return true;
7cf4f69d 901 }
425904dd
CW
902
903 return false;
7cf4f69d
ZY
904}
905
f3cfcba6
CW
906static bool intel_lvds_supported(struct drm_device *dev)
907{
908 /* With the introduction of the PCH we gained a dedicated
909 * LVDS presence pin, use it. */
910 if (HAS_PCH_SPLIT(dev))
911 return true;
912
913 /* Otherwise LVDS was only attached to mobile products,
914 * except for the inglorious 830gm */
915 return IS_MOBILE(dev) && !IS_I830(dev);
916}
917
79e53945
JB
918/**
919 * intel_lvds_init - setup LVDS connectors on this device
920 * @dev: drm device
921 *
922 * Create the connector, register the LVDS DDC bus, and try to figure out what
923 * modes we can display on the LVDS panel (if present).
924 */
c5d1b51d 925bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
926{
927 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 928 struct intel_lvds_encoder *lvds_encoder;
21d40d37 929 struct intel_encoder *intel_encoder;
c7362c4d 930 struct intel_lvds_connector *lvds_connector;
bb8a3560 931 struct intel_connector *intel_connector;
79e53945
JB
932 struct drm_connector *connector;
933 struct drm_encoder *encoder;
934 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 935 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 936 struct edid *edid;
79e53945
JB
937 struct drm_crtc *crtc;
938 u32 lvds;
270eea0f
CW
939 int pipe;
940 u8 pin;
79e53945 941
f3cfcba6
CW
942 if (!intel_lvds_supported(dev))
943 return false;
944
425d244c
JW
945 /* Skip init on machines we know falsely report LVDS */
946 if (dmi_check_system(intel_no_lvds))
c5d1b51d 947 return false;
565dcd46 948
270eea0f
CW
949 pin = GMBUS_PORT_PANEL;
950 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 951 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 952 return false;
38b3037e 953 }
e99da35f 954
c619eed4 955 if (HAS_PCH_SPLIT(dev)) {
541998a1 956 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 957 return false;
5ceb0f9b 958 if (dev_priv->edp.support) {
28c97730 959 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 960 return false;
32f9d658 961 }
541998a1
ZW
962 }
963
29b99b48
JN
964 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
965 if (!lvds_encoder)
c5d1b51d 966 return false;
79e53945 967
c7362c4d
JN
968 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
969 if (!lvds_connector) {
29b99b48 970 kfree(lvds_encoder);
c5d1b51d 971 return false;
bb8a3560
ZW
972 }
973
62165e0d
JN
974 lvds_encoder->attached_connector = lvds_connector;
975
e9e331a8 976 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 977 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
978 }
979
29b99b48 980 intel_encoder = &lvds_encoder->base;
4ef69c7a 981 encoder = &intel_encoder->base;
c7362c4d 982 intel_connector = &lvds_connector->base;
ea5b213a 983 connector = &intel_connector->base;
bb8a3560 984 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
985 DRM_MODE_CONNECTOR_LVDS);
986
4ef69c7a 987 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
988 DRM_MODE_ENCODER_LVDS);
989
c22834ec
DV
990 intel_encoder->enable = intel_enable_lvds;
991 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
992 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
993 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 994
df0e9248 995 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 996 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 997
66a9278e 998 intel_encoder->cloneable = false;
27f8227b
JB
999 if (HAS_PCH_SPLIT(dev))
1000 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
1001 else if (IS_GEN4(dev))
1002 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1003 else
1004 intel_encoder->crtc_mask = (1 << 1);
1005
79e53945
JB
1006 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
1007 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1008 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1009 connector->interlace_allowed = false;
1010 connector->doublescan_allowed = false;
1011
3fbe18d6
ZY
1012 /* create the scaling mode property */
1013 drm_mode_create_scaling_mode_property(dev);
662595df 1014 drm_object_attach_property(&connector->base,
3fbe18d6 1015 dev->mode_config.scaling_mode_property,
dd1ea37d 1016 DRM_MODE_SCALE_ASPECT);
4d891523 1017 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1018 /*
1019 * LVDS discovery:
1020 * 1) check for EDID on DDC
1021 * 2) check for VBT data
1022 * 3) check to see if LVDS is already on
1023 * if none of the above, no panel
1024 * 4) make sure lid is open
1025 * if closed, act like it's not there for now
1026 */
1027
79e53945
JB
1028 /*
1029 * Attempt to get the fixed panel mode from DDC. Assume that the
1030 * preferred mode is the right one.
1031 */
9cd300e0
JN
1032 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1033 if (edid) {
1034 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1035 drm_mode_connector_update_edid_property(connector,
9cd300e0 1036 edid);
3f8ff0e7 1037 } else {
9cd300e0
JN
1038 kfree(edid);
1039 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1040 }
9cd300e0
JN
1041 } else {
1042 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1043 }
9cd300e0
JN
1044 lvds_connector->base.edid = edid;
1045
1046 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1047 /* Didn't get an EDID, so
1048 * Set wide sync ranges so we get all modes
1049 * handed to valid_mode for checking
1050 */
1051 connector->display_info.min_vfreq = 0;
1052 connector->display_info.max_vfreq = 200;
1053 connector->display_info.min_hfreq = 0;
1054 connector->display_info.max_hfreq = 200;
1055 }
79e53945
JB
1056
1057 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1058 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1059 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1060 drm_mode_debug_printmodeline(scan);
1061
dd06f90e 1062 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1063 if (fixed_mode) {
1064 intel_find_lvds_downclock(dev, fixed_mode,
1065 connector);
1066 goto out;
1067 }
79e53945 1068 }
79e53945
JB
1069 }
1070
1071 /* Failed to get EDID, what about VBT? */
88631706 1072 if (dev_priv->lfp_lvds_vbt_mode) {
6a9d51b7
CW
1073 DRM_DEBUG_KMS("using mode from VBT: ");
1074 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode);
1075
dd06f90e
JN
1076 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1077 if (fixed_mode) {
1078 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1079 goto out;
1080 }
79e53945
JB
1081 }
1082
1083 /*
1084 * If we didn't get EDID, try checking if the panel is already turned
1085 * on. If so, assume that whatever is currently programmed is the
1086 * correct mode.
1087 */
541998a1 1088
f2b115e6 1089 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1090 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1091 goto failed;
1092
79e53945
JB
1093 lvds = I915_READ(LVDS);
1094 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1095 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1096
1097 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1098 fixed_mode = intel_crtc_mode_get(dev, crtc);
1099 if (fixed_mode) {
6a9d51b7
CW
1100 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1101 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1102 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1103 goto out;
79e53945
JB
1104 }
1105 }
1106
1107 /* If we still don't have a mode after all that, give up. */
dd06f90e 1108 if (!fixed_mode)
79e53945
JB
1109 goto failed;
1110
79e53945 1111out:
24ded204
DV
1112 /*
1113 * Unlock registers and just
1114 * leave them unlocked
1115 */
c619eed4 1116 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1117 I915_WRITE(PCH_PP_CONTROL,
1118 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1119 } else {
ed10fca9
KP
1120 I915_WRITE(PP_CONTROL,
1121 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1122 }
db1740a0
JN
1123 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1124 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1125 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1126 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1127 }
79e53945 1128 drm_sysfs_connector_add(connector);
aaa6fd2a 1129
dd06f90e 1130 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1131 intel_panel_setup_backlight(connector);
aaa6fd2a 1132
c5d1b51d 1133 return true;
79e53945
JB
1134
1135failed:
8a4c47f3 1136 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1137 drm_connector_cleanup(connector);
1991bdfa 1138 drm_encoder_cleanup(encoder);
dd06f90e
JN
1139 if (fixed_mode)
1140 drm_mode_destroy(dev, fixed_mode);
29b99b48 1141 kfree(lvds_encoder);
c7362c4d 1142 kfree(lvds_connector);
c5d1b51d 1143 return false;
79e53945 1144}
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