drm/i915: add intel_lvds->reg
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
3fbe18d6
ZY
52 u32 pfit_control;
53 u32 pfit_pgm_ratios;
e9e331a8 54 bool pfit_dirty;
13c7d870 55 bool is_dual_link;
7dec0606 56 u32 reg;
788319d4 57
62165e0d 58 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
59};
60
29b99b48 61static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 62{
29b99b48 63 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
64}
65
c7362c4d 66static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 67{
c7362c4d 68 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
69}
70
b1dc332c
DV
71static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
72 enum pipe *pipe)
73{
74 struct drm_device *dev = encoder->base.dev;
75 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
76 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
77 u32 tmp;
b1dc332c 78
7dec0606 79 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
80
81 if (!(tmp & LVDS_PORT_EN))
82 return false;
83
84 if (HAS_PCH_CPT(dev))
85 *pipe = PORT_TO_PIPE_CPT(tmp);
86 else
87 *pipe = PORT_TO_PIPE(tmp);
88
89 return true;
90}
91
79e53945
JB
92/**
93 * Sets the power state for the panel.
94 */
c22834ec 95static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 96{
c22834ec 97 struct drm_device *dev = encoder->base.dev;
29b99b48 98 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 99 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 100 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 101 u32 ctl_reg, stat_reg;
541998a1 102
c619eed4 103 if (HAS_PCH_SPLIT(dev)) {
541998a1 104 ctl_reg = PCH_PP_CONTROL;
de842eff 105 stat_reg = PCH_PP_STATUS;
541998a1
ZW
106 } else {
107 ctl_reg = PP_CONTROL;
de842eff 108 stat_reg = PP_STATUS;
541998a1 109 }
79e53945 110
7dec0606 111 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 112
29b99b48 113 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
114 /*
115 * Enable automatic panel scaling so that non-native modes
116 * fill the screen. The panel fitter should only be
117 * adjusted whilst the pipe is disabled, according to
118 * register description and PRM.
119 */
120 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
121 lvds_encoder->pfit_control,
122 lvds_encoder->pfit_pgm_ratios);
de842eff 123
29b99b48
JN
124 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
125 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
126 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
127 }
128
129 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 130 POSTING_READ(lvds_encoder->reg);
de842eff
KP
131 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
132 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 133
24ded204 134 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
135}
136
c22834ec 137static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 138{
c22834ec 139 struct drm_device *dev = encoder->base.dev;
29b99b48 140 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 141 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 142 u32 ctl_reg, stat_reg;
2a1292fd
CW
143
144 if (HAS_PCH_SPLIT(dev)) {
145 ctl_reg = PCH_PP_CONTROL;
de842eff 146 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
147 } else {
148 ctl_reg = PP_CONTROL;
de842eff 149 stat_reg = PP_STATUS;
2a1292fd
CW
150 }
151
47356eb6 152 intel_panel_disable_backlight(dev);
2a1292fd
CW
153
154 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
155 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
156 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 157
29b99b48 158 if (lvds_encoder->pfit_control) {
2a1292fd 159 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 160 lvds_encoder->pfit_dirty = true;
79e53945 161 }
2a1292fd 162
7dec0606
DV
163 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
164 POSTING_READ(lvds_encoder->reg);
79e53945
JB
165}
166
79e53945
JB
167static int intel_lvds_mode_valid(struct drm_connector *connector,
168 struct drm_display_mode *mode)
169{
dd06f90e
JN
170 struct intel_connector *intel_connector = to_intel_connector(connector);
171 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 172
788319d4
CW
173 if (mode->hdisplay > fixed_mode->hdisplay)
174 return MODE_PANEL;
175 if (mode->vdisplay > fixed_mode->vdisplay)
176 return MODE_PANEL;
79e53945
JB
177
178 return MODE_OK;
179}
180
49be663f
CW
181static void
182centre_horizontally(struct drm_display_mode *mode,
183 int width)
184{
185 u32 border, sync_pos, blank_width, sync_width;
186
187 /* keep the hsync and hblank widths constant */
188 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
189 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
190 sync_pos = (blank_width - sync_width + 1) / 2;
191
192 border = (mode->hdisplay - width + 1) / 2;
193 border += border & 1; /* make the border even */
194
195 mode->crtc_hdisplay = width;
196 mode->crtc_hblank_start = width + border;
197 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
198
199 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
200 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
201
202 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
203}
204
205static void
206centre_vertically(struct drm_display_mode *mode,
207 int height)
208{
209 u32 border, sync_pos, blank_width, sync_width;
210
211 /* keep the vsync and vblank widths constant */
212 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
213 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
214 sync_pos = (blank_width - sync_width + 1) / 2;
215
216 border = (mode->vdisplay - height + 1) / 2;
217
218 mode->crtc_vdisplay = height;
219 mode->crtc_vblank_start = height + border;
220 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
221
222 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
223 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
224
225 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
226}
227
228static inline u32 panel_fitter_scaling(u32 source, u32 target)
229{
230 /*
231 * Floating point operation is not supported. So the FACTOR
232 * is defined, which can avoid the floating point computation
233 * when calculating the panel ratio.
234 */
235#define ACCURACY 12
236#define FACTOR (1 << ACCURACY)
237 u32 ratio = source * FACTOR / target;
238 return (FACTOR * ratio + FACTOR/2) / FACTOR;
239}
240
79e53945 241static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 242 const struct drm_display_mode *mode,
79e53945
JB
243 struct drm_display_mode *adjusted_mode)
244{
245 struct drm_device *dev = encoder->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 247 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
4d891523
JN
248 struct intel_connector *intel_connector =
249 &lvds_encoder->attached_connector->base;
29b99b48 250 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 251 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 252 int pipe;
79e53945
JB
253
254 /* Should never happen!! */
a6c45cf0 255 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 256 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
257 return false;
258 }
259
29b99b48 260 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 261 return false;
1d8e1c75 262
79e53945 263 /*
71677043 264 * We have timings from the BIOS for the panel, put them in
79e53945
JB
265 * to the adjusted mode. The CRTC will be set up for this mode,
266 * with the panel scaling set up to source from the H/VDisplay
267 * of the original mode.
268 */
4d891523 269 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 270 adjusted_mode);
1d8e1c75
CW
271
272 if (HAS_PCH_SPLIT(dev)) {
4d891523
JN
273 intel_pch_panel_fitting(dev,
274 intel_connector->panel.fitting_mode,
1d8e1c75
CW
275 mode, adjusted_mode);
276 return true;
277 }
79e53945 278
3fbe18d6
ZY
279 /* Native modes don't need fitting */
280 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 281 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 282 goto out;
3fbe18d6
ZY
283
284 /* 965+ wants fuzzy fitting */
a6c45cf0 285 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
286 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
287 PFIT_FILTER_FUZZY);
288
3fbe18d6
ZY
289 /*
290 * Enable automatic panel scaling for non-native modes so that they fill
291 * the screen. Should be enabled before the pipe is enabled, according
292 * to register description and PRM.
293 * Change the value here to see the borders for debugging
294 */
9db4a9c7
JB
295 for_each_pipe(pipe)
296 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 297
f9bef081
DV
298 drm_mode_set_crtcinfo(adjusted_mode, 0);
299
4d891523 300 switch (intel_connector->panel.fitting_mode) {
53bd8389 301 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
302 /*
303 * For centered modes, we have to calculate border widths &
304 * heights and modify the values programmed into the CRTC.
305 */
49be663f
CW
306 centre_horizontally(adjusted_mode, mode->hdisplay);
307 centre_vertically(adjusted_mode, mode->vdisplay);
308 border = LVDS_BORDER_ENABLE;
3fbe18d6 309 break;
49be663f 310
3fbe18d6 311 case DRM_MODE_SCALE_ASPECT:
49be663f 312 /* Scale but preserve the aspect ratio */
a6c45cf0 313 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
314 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
315 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
316
3fbe18d6 317 /* 965+ is easy, it does everything in hw */
49be663f 318 if (scaled_width > scaled_height)
257e48f1 319 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 320 else if (scaled_width < scaled_height)
257e48f1
CW
321 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
322 else if (adjusted_mode->hdisplay != mode->hdisplay)
323 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 324 } else {
49be663f
CW
325 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
326 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
327 /*
328 * For earlier chips we have to calculate the scaling
329 * ratio by hand and program it into the
330 * PFIT_PGM_RATIO register
331 */
49be663f
CW
332 if (scaled_width > scaled_height) { /* pillar */
333 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
334
335 border = LVDS_BORDER_ENABLE;
336 if (mode->vdisplay != adjusted_mode->vdisplay) {
337 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
338 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
339 bits << PFIT_VERT_SCALE_SHIFT);
340 pfit_control |= (PFIT_ENABLE |
341 VERT_INTERP_BILINEAR |
342 HORIZ_INTERP_BILINEAR);
343 }
344 } else if (scaled_width < scaled_height) { /* letter */
345 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
346
347 border = LVDS_BORDER_ENABLE;
348 if (mode->hdisplay != adjusted_mode->hdisplay) {
349 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
350 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
351 bits << PFIT_VERT_SCALE_SHIFT);
352 pfit_control |= (PFIT_ENABLE |
353 VERT_INTERP_BILINEAR |
354 HORIZ_INTERP_BILINEAR);
355 }
356 } else
357 /* Aspects match, Let hw scale both directions */
358 pfit_control |= (PFIT_ENABLE |
359 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
360 VERT_INTERP_BILINEAR |
361 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
362 }
363 break;
364
365 case DRM_MODE_SCALE_FULLSCREEN:
366 /*
367 * Full scaling, even if it changes the aspect ratio.
368 * Fortunately this is all done for us in hw.
369 */
257e48f1
CW
370 if (mode->vdisplay != adjusted_mode->vdisplay ||
371 mode->hdisplay != adjusted_mode->hdisplay) {
372 pfit_control |= PFIT_ENABLE;
373 if (INTEL_INFO(dev)->gen >= 4)
374 pfit_control |= PFIT_SCALING_AUTO;
375 else
376 pfit_control |= (VERT_AUTO_SCALE |
377 VERT_INTERP_BILINEAR |
378 HORIZ_AUTO_SCALE |
379 HORIZ_INTERP_BILINEAR);
380 }
3fbe18d6 381 break;
49be663f 382
3fbe18d6
ZY
383 default:
384 break;
385 }
386
387out:
72389a33 388 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
389 if ((pfit_control & PFIT_ENABLE) == 0) {
390 pfit_control = 0;
391 pfit_pgm_ratios = 0;
392 }
72389a33
CW
393
394 /* Make sure pre-965 set dither correctly */
395 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
396 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
397
29b99b48
JN
398 if (pfit_control != lvds_encoder->pfit_control ||
399 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
400 lvds_encoder->pfit_control = pfit_control;
401 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
402 lvds_encoder->pfit_dirty = true;
e9e331a8 403 }
49be663f
CW
404 dev_priv->lvds_border_bits = border;
405
79e53945
JB
406 /*
407 * XXX: It would be nice to support lower refresh rates on the
408 * panels to reduce power consumption, and perhaps match the
409 * user's requested refresh rate.
410 */
411
412 return true;
413}
414
79e53945
JB
415static void intel_lvds_mode_set(struct drm_encoder *encoder,
416 struct drm_display_mode *mode,
417 struct drm_display_mode *adjusted_mode)
418{
79e53945
JB
419 /*
420 * The LVDS pin pair will already have been turned on in the
421 * intel_crtc_mode_set since it has a large impact on the DPLL
422 * settings.
423 */
79e53945
JB
424}
425
426/**
427 * Detect the LVDS connection.
428 *
b42d4c5c
JB
429 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
430 * connected and closed means disconnected. We also send hotplug events as
431 * needed, using lid status notification from the input layer.
79e53945 432 */
7b334fcb 433static enum drm_connector_status
930a9e28 434intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 435{
7b9c5abe 436 struct drm_device *dev = connector->dev;
6ee3b5a1 437 enum drm_connector_status status;
b42d4c5c 438
fe16d949
CW
439 status = intel_panel_detect(dev);
440 if (status != connector_status_unknown)
441 return status;
01fe9dbd 442
6ee3b5a1 443 return connector_status_connected;
79e53945
JB
444}
445
446/**
447 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
448 */
449static int intel_lvds_get_modes(struct drm_connector *connector)
450{
62165e0d 451 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 452 struct drm_device *dev = connector->dev;
788319d4 453 struct drm_display_mode *mode;
79e53945 454
9cd300e0 455 /* use cached edid if we have one */
2aa4f099 456 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 457 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 458
dd06f90e 459 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 460 if (mode == NULL)
788319d4 461 return 0;
79e53945 462
788319d4
CW
463 drm_mode_probed_add(connector, mode);
464 return 1;
79e53945
JB
465}
466
0544edfd
TB
467static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
468{
bc0daf48 469 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
470 return 1;
471}
472
473/* The GPU hangs up on these systems if modeset is performed on LID open */
474static const struct dmi_system_id intel_no_modeset_on_lid[] = {
475 {
476 .callback = intel_no_modeset_on_lid_dmi_callback,
477 .ident = "Toshiba Tecra A11",
478 .matches = {
479 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
480 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
481 },
482 },
483
484 { } /* terminating entry */
485};
486
c9354c85
LT
487/*
488 * Lid events. Note the use of 'modeset_on_lid':
489 * - we set it on lid close, and reset it on open
490 * - we use it as a "only once" bit (ie we ignore
491 * duplicate events where it was already properly
492 * set/reset)
493 * - the suspend/resume paths will also set it to
494 * zero, since they restore the mode ("lid open").
495 */
c1c7af60
JB
496static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
497 void *unused)
498{
db1740a0
JN
499 struct intel_lvds_connector *lvds_connector =
500 container_of(nb, struct intel_lvds_connector, lid_notifier);
501 struct drm_connector *connector = &lvds_connector->base.base;
502 struct drm_device *dev = connector->dev;
503 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 504
2fb4e61d
AW
505 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
506 return NOTIFY_OK;
507
a2565377
ZY
508 /*
509 * check and update the status of LVDS connector after receiving
510 * the LID nofication event.
511 */
db1740a0 512 connector->status = connector->funcs->detect(connector, false);
7b334fcb 513
0544edfd
TB
514 /* Don't force modeset on machines where it causes a GPU lockup */
515 if (dmi_check_system(intel_no_modeset_on_lid))
516 return NOTIFY_OK;
c9354c85
LT
517 if (!acpi_lid_open()) {
518 dev_priv->modeset_on_lid = 1;
519 return NOTIFY_OK;
06891e27 520 }
c1c7af60 521
c9354c85
LT
522 if (!dev_priv->modeset_on_lid)
523 return NOTIFY_OK;
524
525 dev_priv->modeset_on_lid = 0;
526
527 mutex_lock(&dev->mode_config.mutex);
45e2b5f6 528 intel_modeset_setup_hw_state(dev, true);
c9354c85 529 mutex_unlock(&dev->mode_config.mutex);
06324194 530
c1c7af60
JB
531 return NOTIFY_OK;
532}
533
79e53945
JB
534/**
535 * intel_lvds_destroy - unregister and free LVDS structures
536 * @connector: connector to free
537 *
538 * Unregister the DDC bus for this connector then free the driver private
539 * structure.
540 */
541static void intel_lvds_destroy(struct drm_connector *connector)
542{
db1740a0
JN
543 struct intel_lvds_connector *lvds_connector =
544 to_lvds_connector(connector);
79e53945 545
db1740a0
JN
546 if (lvds_connector->lid_notifier.notifier_call)
547 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 548
9cd300e0
JN
549 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
550 kfree(lvds_connector->base.edid);
551
db1740a0 552 intel_panel_destroy_backlight(connector->dev);
1d508706 553 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 554
79e53945
JB
555 drm_sysfs_connector_remove(connector);
556 drm_connector_cleanup(connector);
557 kfree(connector);
558}
559
335041ed
JB
560static int intel_lvds_set_property(struct drm_connector *connector,
561 struct drm_property *property,
562 uint64_t value)
563{
4d891523 564 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 565 struct drm_device *dev = connector->dev;
3fbe18d6 566
788319d4 567 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 568 struct drm_crtc *crtc;
bb8a3560 569
53bd8389
JB
570 if (value == DRM_MODE_SCALE_NONE) {
571 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 572 return -EINVAL;
3fbe18d6 573 }
788319d4 574
4d891523 575 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
576 /* the LVDS scaling property is not changed */
577 return 0;
578 }
4d891523 579 intel_connector->panel.fitting_mode = value;
62165e0d
JN
580
581 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
582 if (crtc && crtc->enabled) {
583 /*
584 * If the CRTC is enabled, the display will be changed
585 * according to the new panel fitting mode.
586 */
a6778b3c
DV
587 intel_set_mode(crtc, &crtc->mode,
588 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
589 }
590 }
591
335041ed
JB
592 return 0;
593}
594
79e53945 595static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 596 .mode_fixup = intel_lvds_mode_fixup,
79e53945 597 .mode_set = intel_lvds_mode_set,
1f703855 598 .disable = intel_encoder_noop,
79e53945
JB
599};
600
601static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
602 .get_modes = intel_lvds_get_modes,
603 .mode_valid = intel_lvds_mode_valid,
df0e9248 604 .best_encoder = intel_best_encoder,
79e53945
JB
605};
606
607static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 608 .dpms = intel_connector_dpms,
79e53945
JB
609 .detect = intel_lvds_detect,
610 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 611 .set_property = intel_lvds_set_property,
79e53945
JB
612 .destroy = intel_lvds_destroy,
613};
614
79e53945 615static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 616 .destroy = intel_encoder_destroy,
79e53945
JB
617};
618
425d244c
JW
619static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
620{
bc0daf48 621 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
622 return 1;
623}
79e53945 624
425d244c 625/* These systems claim to have LVDS, but really don't */
93c05f22 626static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
627 {
628 .callback = intel_no_lvds_dmi_callback,
629 .ident = "Apple Mac Mini (Core series)",
630 .matches = {
98acd46f 631 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
632 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
633 },
634 },
635 {
636 .callback = intel_no_lvds_dmi_callback,
637 .ident = "Apple Mac Mini (Core 2 series)",
638 .matches = {
98acd46f 639 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
640 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
641 },
642 },
643 {
644 .callback = intel_no_lvds_dmi_callback,
645 .ident = "MSI IM-945GSE-A",
646 .matches = {
647 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
648 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
649 },
650 },
651 {
652 .callback = intel_no_lvds_dmi_callback,
653 .ident = "Dell Studio Hybrid",
654 .matches = {
655 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
656 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
657 },
658 },
70aa96ca
JW
659 {
660 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
661 .ident = "Dell OptiPlex FX170",
662 .matches = {
663 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
664 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
665 },
666 },
667 {
668 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
669 .ident = "AOpen Mini PC",
670 .matches = {
671 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
672 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
673 },
674 },
ed8c754b
TV
675 {
676 .callback = intel_no_lvds_dmi_callback,
677 .ident = "AOpen Mini PC MP915",
678 .matches = {
679 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
680 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
681 },
682 },
22ab70d3
KP
683 {
684 .callback = intel_no_lvds_dmi_callback,
685 .ident = "AOpen i915GMm-HFS",
686 .matches = {
687 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
688 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
689 },
690 },
e57b6886
DV
691 {
692 .callback = intel_no_lvds_dmi_callback,
693 .ident = "AOpen i45GMx-I",
694 .matches = {
695 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
696 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
697 },
698 },
fa0864b2
MC
699 {
700 .callback = intel_no_lvds_dmi_callback,
701 .ident = "Aopen i945GTt-VFA",
702 .matches = {
703 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
704 },
705 },
9875557e
SB
706 {
707 .callback = intel_no_lvds_dmi_callback,
708 .ident = "Clientron U800",
709 .matches = {
710 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
711 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
712 },
713 },
6a574b5b 714 {
44306ab3
JS
715 .callback = intel_no_lvds_dmi_callback,
716 .ident = "Clientron E830",
717 .matches = {
718 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
719 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
720 },
721 },
722 {
6a574b5b
HG
723 .callback = intel_no_lvds_dmi_callback,
724 .ident = "Asus EeeBox PC EB1007",
725 .matches = {
726 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
727 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
728 },
729 },
0999bbe0
AJ
730 {
731 .callback = intel_no_lvds_dmi_callback,
732 .ident = "Asus AT5NM10T-I",
733 .matches = {
734 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
735 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
736 },
737 },
33471119
JBG
738 {
739 .callback = intel_no_lvds_dmi_callback,
740 .ident = "Hewlett-Packard HP t5740e Thin Client",
741 .matches = {
742 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
743 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
744 },
745 },
f5b8a7ed
MG
746 {
747 .callback = intel_no_lvds_dmi_callback,
748 .ident = "Hewlett-Packard t5745",
749 .matches = {
750 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 751 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
752 },
753 },
754 {
755 .callback = intel_no_lvds_dmi_callback,
756 .ident = "Hewlett-Packard st5747",
757 .matches = {
758 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 759 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
760 },
761 },
97effadb
AA
762 {
763 .callback = intel_no_lvds_dmi_callback,
764 .ident = "MSI Wind Box DC500",
765 .matches = {
766 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
767 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
768 },
769 },
9756fe38
SS
770 {
771 .callback = intel_no_lvds_dmi_callback,
772 .ident = "ZOTAC ZBOXSD-ID12/ID13",
773 .matches = {
774 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
775 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
776 },
777 },
a51d4ed0
CW
778 {
779 .callback = intel_no_lvds_dmi_callback,
780 .ident = "Gigabyte GA-D525TUD",
781 .matches = {
782 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
783 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
784 },
785 },
c31407a3
CW
786 {
787 .callback = intel_no_lvds_dmi_callback,
788 .ident = "Supermicro X7SPA-H",
789 .matches = {
790 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
791 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
792 },
793 },
425d244c
JW
794
795 { } /* terminating entry */
796};
79e53945 797
18f9ed12
ZY
798/**
799 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
800 * @dev: drm device
801 * @connector: LVDS connector
802 *
803 * Find the reduced downclock for LVDS in EDID.
804 */
805static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
806 struct drm_display_mode *fixed_mode,
807 struct drm_connector *connector)
18f9ed12
ZY
808{
809 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 810 struct drm_display_mode *scan;
18f9ed12
ZY
811 int temp_downclock;
812
788319d4 813 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
814 list_for_each_entry(scan, &connector->probed_modes, head) {
815 /*
816 * If one mode has the same resolution with the fixed_panel
817 * mode while they have the different refresh rate, it means
818 * that the reduced downclock is found for the LVDS. In such
819 * case we can set the different FPx0/1 to dynamically select
820 * between low and high frequency.
821 */
788319d4
CW
822 if (scan->hdisplay == fixed_mode->hdisplay &&
823 scan->hsync_start == fixed_mode->hsync_start &&
824 scan->hsync_end == fixed_mode->hsync_end &&
825 scan->htotal == fixed_mode->htotal &&
826 scan->vdisplay == fixed_mode->vdisplay &&
827 scan->vsync_start == fixed_mode->vsync_start &&
828 scan->vsync_end == fixed_mode->vsync_end &&
829 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
830 if (scan->clock < temp_downclock) {
831 /*
832 * The downclock is already found. But we
833 * expect to find the lower downclock.
834 */
835 temp_downclock = scan->clock;
836 }
837 }
838 }
788319d4 839 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
840 /* We found the downclock for LVDS. */
841 dev_priv->lvds_downclock_avail = 1;
842 dev_priv->lvds_downclock = temp_downclock;
843 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
844 "Normal clock %dKhz, downclock %dKhz\n",
845 fixed_mode->clock, temp_downclock);
18f9ed12 846 }
18f9ed12
ZY
847}
848
7cf4f69d
ZY
849/*
850 * Enumerate the child dev array parsed from VBT to check whether
851 * the LVDS is present.
852 * If it is present, return 1.
853 * If it is not present, return false.
854 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 855 */
270eea0f
CW
856static bool lvds_is_present_in_vbt(struct drm_device *dev,
857 u8 *i2c_pin)
7cf4f69d
ZY
858{
859 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 860 int i;
7cf4f69d
ZY
861
862 if (!dev_priv->child_dev_num)
425904dd 863 return true;
7cf4f69d 864
7cf4f69d 865 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
866 struct child_device_config *child = dev_priv->child_dev + i;
867
868 /* If the device type is not LFP, continue.
869 * We have to check both the new identifiers as well as the
870 * old for compatibility with some BIOSes.
7cf4f69d 871 */
425904dd
CW
872 if (child->device_type != DEVICE_TYPE_INT_LFP &&
873 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
874 continue;
875
3bd7d909
DK
876 if (intel_gmbus_is_port_valid(child->i2c_pin))
877 *i2c_pin = child->i2c_pin;
270eea0f 878
425904dd
CW
879 /* However, we cannot trust the BIOS writers to populate
880 * the VBT correctly. Since LVDS requires additional
881 * information from AIM blocks, a non-zero addin offset is
882 * a good indicator that the LVDS is actually present.
7cf4f69d 883 */
425904dd
CW
884 if (child->addin_offset)
885 return true;
886
887 /* But even then some BIOS writers perform some black magic
888 * and instantiate the device without reference to any
889 * additional data. Trust that if the VBT was written into
890 * the OpRegion then they have validated the LVDS's existence.
891 */
892 if (dev_priv->opregion.vbt)
893 return true;
7cf4f69d 894 }
425904dd
CW
895
896 return false;
7cf4f69d
ZY
897}
898
1974cad0
DV
899static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
900{
901 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
902 return 1;
903}
904
905static const struct dmi_system_id intel_dual_link_lvds[] = {
906 {
907 .callback = intel_dual_link_lvds_callback,
908 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
909 .matches = {
910 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
911 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
912 },
913 },
914 { } /* terminating entry */
915};
916
917bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
918{
919 struct intel_encoder *encoder;
920 struct intel_lvds_encoder *lvds_encoder;
921
922 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
923 base.head) {
924 if (encoder->type == INTEL_OUTPUT_LVDS) {
925 lvds_encoder = to_lvds_encoder(&encoder->base);
926
927 return lvds_encoder->is_dual_link;
928 }
929 }
930
931 return false;
932}
933
7dec0606 934static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 935{
7dec0606 936 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
937 unsigned int val;
938 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
939
940 /* use the module option value if specified */
941 if (i915_lvds_channel_mode > 0)
942 return i915_lvds_channel_mode == 2;
943
944 if (dmi_check_system(intel_dual_link_lvds))
945 return true;
946
13c7d870
DV
947 /* BIOS should set the proper LVDS register value at boot, but
948 * in reality, it doesn't set the value when the lid is closed;
949 * we need to check "the value to be set" in VBT when LVDS
950 * register is uninitialized.
951 */
7dec0606 952 val = I915_READ(lvds_encoder->reg);
13c7d870
DV
953 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
954 val = dev_priv->bios_lvds_val;
955
1974cad0
DV
956 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
957}
958
f3cfcba6
CW
959static bool intel_lvds_supported(struct drm_device *dev)
960{
961 /* With the introduction of the PCH we gained a dedicated
962 * LVDS presence pin, use it. */
963 if (HAS_PCH_SPLIT(dev))
964 return true;
965
966 /* Otherwise LVDS was only attached to mobile products,
967 * except for the inglorious 830gm */
968 return IS_MOBILE(dev) && !IS_I830(dev);
969}
970
79e53945
JB
971/**
972 * intel_lvds_init - setup LVDS connectors on this device
973 * @dev: drm device
974 *
975 * Create the connector, register the LVDS DDC bus, and try to figure out what
976 * modes we can display on the LVDS panel (if present).
977 */
c5d1b51d 978bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
979{
980 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 981 struct intel_lvds_encoder *lvds_encoder;
21d40d37 982 struct intel_encoder *intel_encoder;
c7362c4d 983 struct intel_lvds_connector *lvds_connector;
bb8a3560 984 struct intel_connector *intel_connector;
79e53945
JB
985 struct drm_connector *connector;
986 struct drm_encoder *encoder;
987 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 988 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 989 struct edid *edid;
79e53945
JB
990 struct drm_crtc *crtc;
991 u32 lvds;
270eea0f
CW
992 int pipe;
993 u8 pin;
79e53945 994
f3cfcba6
CW
995 if (!intel_lvds_supported(dev))
996 return false;
997
425d244c
JW
998 /* Skip init on machines we know falsely report LVDS */
999 if (dmi_check_system(intel_no_lvds))
c5d1b51d 1000 return false;
565dcd46 1001
270eea0f
CW
1002 pin = GMBUS_PORT_PANEL;
1003 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 1004 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 1005 return false;
38b3037e 1006 }
e99da35f 1007
c619eed4 1008 if (HAS_PCH_SPLIT(dev)) {
541998a1 1009 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 1010 return false;
5ceb0f9b 1011 if (dev_priv->edp.support) {
28c97730 1012 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 1013 return false;
32f9d658 1014 }
541998a1
ZW
1015 }
1016
29b99b48
JN
1017 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
1018 if (!lvds_encoder)
c5d1b51d 1019 return false;
79e53945 1020
c7362c4d
JN
1021 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
1022 if (!lvds_connector) {
29b99b48 1023 kfree(lvds_encoder);
c5d1b51d 1024 return false;
bb8a3560
ZW
1025 }
1026
62165e0d
JN
1027 lvds_encoder->attached_connector = lvds_connector;
1028
e9e331a8 1029 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 1030 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
1031 }
1032
29b99b48 1033 intel_encoder = &lvds_encoder->base;
4ef69c7a 1034 encoder = &intel_encoder->base;
c7362c4d 1035 intel_connector = &lvds_connector->base;
ea5b213a 1036 connector = &intel_connector->base;
bb8a3560 1037 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
1038 DRM_MODE_CONNECTOR_LVDS);
1039
4ef69c7a 1040 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
1041 DRM_MODE_ENCODER_LVDS);
1042
c22834ec
DV
1043 intel_encoder->enable = intel_enable_lvds;
1044 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
1045 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1046 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 1047
df0e9248 1048 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 1049 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 1050
66a9278e 1051 intel_encoder->cloneable = false;
27f8227b
JB
1052 if (HAS_PCH_SPLIT(dev))
1053 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
1054 else if (IS_GEN4(dev))
1055 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1056 else
1057 intel_encoder->crtc_mask = (1 << 1);
1058
79e53945
JB
1059 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
1060 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1061 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1062 connector->interlace_allowed = false;
1063 connector->doublescan_allowed = false;
1064
7dec0606
DV
1065 if (HAS_PCH_SPLIT(dev)) {
1066 lvds_encoder->reg = PCH_LVDS;
1067 } else {
1068 lvds_encoder->reg = LVDS;
1069 }
1070
3fbe18d6
ZY
1071 /* create the scaling mode property */
1072 drm_mode_create_scaling_mode_property(dev);
662595df 1073 drm_object_attach_property(&connector->base,
3fbe18d6 1074 dev->mode_config.scaling_mode_property,
dd1ea37d 1075 DRM_MODE_SCALE_ASPECT);
4d891523 1076 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1077 /*
1078 * LVDS discovery:
1079 * 1) check for EDID on DDC
1080 * 2) check for VBT data
1081 * 3) check to see if LVDS is already on
1082 * if none of the above, no panel
1083 * 4) make sure lid is open
1084 * if closed, act like it's not there for now
1085 */
1086
79e53945
JB
1087 /*
1088 * Attempt to get the fixed panel mode from DDC. Assume that the
1089 * preferred mode is the right one.
1090 */
9cd300e0
JN
1091 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1092 if (edid) {
1093 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1094 drm_mode_connector_update_edid_property(connector,
9cd300e0 1095 edid);
3f8ff0e7 1096 } else {
9cd300e0
JN
1097 kfree(edid);
1098 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1099 }
9cd300e0
JN
1100 } else {
1101 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1102 }
9cd300e0
JN
1103 lvds_connector->base.edid = edid;
1104
1105 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1106 /* Didn't get an EDID, so
1107 * Set wide sync ranges so we get all modes
1108 * handed to valid_mode for checking
1109 */
1110 connector->display_info.min_vfreq = 0;
1111 connector->display_info.max_vfreq = 200;
1112 connector->display_info.min_hfreq = 0;
1113 connector->display_info.max_hfreq = 200;
1114 }
79e53945
JB
1115
1116 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1117 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1118 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1119 drm_mode_debug_printmodeline(scan);
1120
dd06f90e 1121 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1122 if (fixed_mode) {
1123 intel_find_lvds_downclock(dev, fixed_mode,
1124 connector);
1125 goto out;
1126 }
79e53945 1127 }
79e53945
JB
1128 }
1129
1130 /* Failed to get EDID, what about VBT? */
88631706 1131 if (dev_priv->lfp_lvds_vbt_mode) {
6a9d51b7
CW
1132 DRM_DEBUG_KMS("using mode from VBT: ");
1133 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode);
1134
dd06f90e
JN
1135 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1136 if (fixed_mode) {
1137 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1138 goto out;
1139 }
79e53945
JB
1140 }
1141
1142 /*
1143 * If we didn't get EDID, try checking if the panel is already turned
1144 * on. If so, assume that whatever is currently programmed is the
1145 * correct mode.
1146 */
541998a1 1147
f2b115e6 1148 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1149 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1150 goto failed;
1151
79e53945
JB
1152 lvds = I915_READ(LVDS);
1153 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1154 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1155
1156 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1157 fixed_mode = intel_crtc_mode_get(dev, crtc);
1158 if (fixed_mode) {
6a9d51b7
CW
1159 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1160 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1161 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1162 goto out;
79e53945
JB
1163 }
1164 }
1165
1166 /* If we still don't have a mode after all that, give up. */
dd06f90e 1167 if (!fixed_mode)
79e53945
JB
1168 goto failed;
1169
79e53945 1170out:
7dec0606 1171 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1172 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1173 lvds_encoder->is_dual_link ? "dual" : "single");
1174
24ded204
DV
1175 /*
1176 * Unlock registers and just
1177 * leave them unlocked
1178 */
c619eed4 1179 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1180 I915_WRITE(PCH_PP_CONTROL,
1181 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1182 } else {
ed10fca9
KP
1183 I915_WRITE(PP_CONTROL,
1184 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1185 }
db1740a0
JN
1186 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1187 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1188 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1189 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1190 }
79e53945 1191 drm_sysfs_connector_add(connector);
aaa6fd2a 1192
dd06f90e 1193 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1194 intel_panel_setup_backlight(connector);
aaa6fd2a 1195
c5d1b51d 1196 return true;
79e53945
JB
1197
1198failed:
8a4c47f3 1199 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1200 drm_connector_cleanup(connector);
1991bdfa 1201 drm_encoder_cleanup(encoder);
dd06f90e
JN
1202 if (fixed_mode)
1203 drm_mode_destroy(dev, fixed_mode);
29b99b48 1204 kfree(lvds_encoder);
c7362c4d 1205 kfree(lvds_connector);
c5d1b51d 1206 return false;
79e53945 1207}
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