drm/i915: Do not free the passed EDID in intel_connector_update_modes()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
db1740a0
JN
45
46 struct notifier_block lid_notifier;
62165e0d
JN
47 struct edid *edid;
48 int fitting_mode;
c7362c4d
JN
49};
50
29b99b48 51struct intel_lvds_encoder {
ea5b213a 52 struct intel_encoder base;
788319d4 53
3fbe18d6
ZY
54 u32 pfit_control;
55 u32 pfit_pgm_ratios;
e9e331a8 56 bool pfit_dirty;
788319d4 57
62165e0d 58 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
59};
60
29b99b48 61static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 62{
29b99b48 63 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
64}
65
c7362c4d
JN
66static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
67{
68 return container_of(connector, struct intel_lvds_connector, base.base);
69}
70
b1dc332c
DV
71static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
72 enum pipe *pipe)
73{
74 struct drm_device *dev = encoder->base.dev;
75 struct drm_i915_private *dev_priv = dev->dev_private;
76 u32 lvds_reg, tmp;
77
78 if (HAS_PCH_SPLIT(dev)) {
79 lvds_reg = PCH_LVDS;
80 } else {
81 lvds_reg = LVDS;
82 }
83
84 tmp = I915_READ(lvds_reg);
85
86 if (!(tmp & LVDS_PORT_EN))
87 return false;
88
89 if (HAS_PCH_CPT(dev))
90 *pipe = PORT_TO_PIPE_CPT(tmp);
91 else
92 *pipe = PORT_TO_PIPE(tmp);
93
94 return true;
95}
96
79e53945
JB
97/**
98 * Sets the power state for the panel.
99 */
c22834ec 100static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 101{
c22834ec 102 struct drm_device *dev = encoder->base.dev;
29b99b48 103 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 104 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 105 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 106 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 107
c619eed4 108 if (HAS_PCH_SPLIT(dev)) {
541998a1 109 ctl_reg = PCH_PP_CONTROL;
469d1296 110 lvds_reg = PCH_LVDS;
de842eff 111 stat_reg = PCH_PP_STATUS;
541998a1
ZW
112 } else {
113 ctl_reg = PP_CONTROL;
469d1296 114 lvds_reg = LVDS;
de842eff 115 stat_reg = PP_STATUS;
541998a1 116 }
79e53945 117
2a1292fd 118 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 119
29b99b48 120 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
121 /*
122 * Enable automatic panel scaling so that non-native modes
123 * fill the screen. The panel fitter should only be
124 * adjusted whilst the pipe is disabled, according to
125 * register description and PRM.
126 */
127 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
128 lvds_encoder->pfit_control,
129 lvds_encoder->pfit_pgm_ratios);
de842eff 130
29b99b48
JN
131 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
132 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
133 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
134 }
135
136 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
137 POSTING_READ(lvds_reg);
de842eff
KP
138 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
139 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 140
24ded204 141 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
142}
143
c22834ec 144static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 145{
c22834ec 146 struct drm_device *dev = encoder->base.dev;
29b99b48 147 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 148 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 149 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
150
151 if (HAS_PCH_SPLIT(dev)) {
152 ctl_reg = PCH_PP_CONTROL;
153 lvds_reg = PCH_LVDS;
de842eff 154 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
155 } else {
156 ctl_reg = PP_CONTROL;
157 lvds_reg = LVDS;
de842eff 158 stat_reg = PP_STATUS;
2a1292fd
CW
159 }
160
47356eb6 161 intel_panel_disable_backlight(dev);
2a1292fd
CW
162
163 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
164 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
165 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 166
29b99b48 167 if (lvds_encoder->pfit_control) {
2a1292fd 168 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 169 lvds_encoder->pfit_dirty = true;
79e53945 170 }
2a1292fd
CW
171
172 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 173 POSTING_READ(lvds_reg);
79e53945
JB
174}
175
79e53945
JB
176static int intel_lvds_mode_valid(struct drm_connector *connector,
177 struct drm_display_mode *mode)
178{
dd06f90e
JN
179 struct intel_connector *intel_connector = to_intel_connector(connector);
180 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 181
788319d4
CW
182 if (mode->hdisplay > fixed_mode->hdisplay)
183 return MODE_PANEL;
184 if (mode->vdisplay > fixed_mode->vdisplay)
185 return MODE_PANEL;
79e53945
JB
186
187 return MODE_OK;
188}
189
49be663f
CW
190static void
191centre_horizontally(struct drm_display_mode *mode,
192 int width)
193{
194 u32 border, sync_pos, blank_width, sync_width;
195
196 /* keep the hsync and hblank widths constant */
197 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
198 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
199 sync_pos = (blank_width - sync_width + 1) / 2;
200
201 border = (mode->hdisplay - width + 1) / 2;
202 border += border & 1; /* make the border even */
203
204 mode->crtc_hdisplay = width;
205 mode->crtc_hblank_start = width + border;
206 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
207
208 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
209 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
210
211 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
212}
213
214static void
215centre_vertically(struct drm_display_mode *mode,
216 int height)
217{
218 u32 border, sync_pos, blank_width, sync_width;
219
220 /* keep the vsync and vblank widths constant */
221 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
222 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
223 sync_pos = (blank_width - sync_width + 1) / 2;
224
225 border = (mode->vdisplay - height + 1) / 2;
226
227 mode->crtc_vdisplay = height;
228 mode->crtc_vblank_start = height + border;
229 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
230
231 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
232 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
233
234 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
235}
236
237static inline u32 panel_fitter_scaling(u32 source, u32 target)
238{
239 /*
240 * Floating point operation is not supported. So the FACTOR
241 * is defined, which can avoid the floating point computation
242 * when calculating the panel ratio.
243 */
244#define ACCURACY 12
245#define FACTOR (1 << ACCURACY)
246 u32 ratio = source * FACTOR / target;
247 return (FACTOR * ratio + FACTOR/2) / FACTOR;
248}
249
79e53945 250static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 251 const struct drm_display_mode *mode,
79e53945
JB
252 struct drm_display_mode *adjusted_mode)
253{
254 struct drm_device *dev = encoder->dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 256 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
62165e0d
JN
257 struct intel_lvds_connector *lvds_connector =
258 lvds_encoder->attached_connector;
29b99b48 259 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 260 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 261 int pipe;
79e53945
JB
262
263 /* Should never happen!! */
a6c45cf0 264 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 265 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
266 return false;
267 }
268
29b99b48 269 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 270 return false;
1d8e1c75 271
79e53945 272 /*
71677043 273 * We have timings from the BIOS for the panel, put them in
79e53945
JB
274 * to the adjusted mode. The CRTC will be set up for this mode,
275 * with the panel scaling set up to source from the H/VDisplay
276 * of the original mode.
277 */
dd06f90e
JN
278 intel_fixed_panel_mode(lvds_connector->base.panel.fixed_mode,
279 adjusted_mode);
1d8e1c75
CW
280
281 if (HAS_PCH_SPLIT(dev)) {
62165e0d 282 intel_pch_panel_fitting(dev, lvds_connector->fitting_mode,
1d8e1c75
CW
283 mode, adjusted_mode);
284 return true;
285 }
79e53945 286
3fbe18d6
ZY
287 /* Native modes don't need fitting */
288 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 289 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 290 goto out;
3fbe18d6
ZY
291
292 /* 965+ wants fuzzy fitting */
a6c45cf0 293 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
294 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
295 PFIT_FILTER_FUZZY);
296
3fbe18d6
ZY
297 /*
298 * Enable automatic panel scaling for non-native modes so that they fill
299 * the screen. Should be enabled before the pipe is enabled, according
300 * to register description and PRM.
301 * Change the value here to see the borders for debugging
302 */
9db4a9c7
JB
303 for_each_pipe(pipe)
304 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 305
f9bef081
DV
306 drm_mode_set_crtcinfo(adjusted_mode, 0);
307
62165e0d 308 switch (lvds_connector->fitting_mode) {
53bd8389 309 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
310 /*
311 * For centered modes, we have to calculate border widths &
312 * heights and modify the values programmed into the CRTC.
313 */
49be663f
CW
314 centre_horizontally(adjusted_mode, mode->hdisplay);
315 centre_vertically(adjusted_mode, mode->vdisplay);
316 border = LVDS_BORDER_ENABLE;
3fbe18d6 317 break;
49be663f 318
3fbe18d6 319 case DRM_MODE_SCALE_ASPECT:
49be663f 320 /* Scale but preserve the aspect ratio */
a6c45cf0 321 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
322 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
323 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
324
3fbe18d6 325 /* 965+ is easy, it does everything in hw */
49be663f 326 if (scaled_width > scaled_height)
257e48f1 327 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 328 else if (scaled_width < scaled_height)
257e48f1
CW
329 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
330 else if (adjusted_mode->hdisplay != mode->hdisplay)
331 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 332 } else {
49be663f
CW
333 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
334 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
335 /*
336 * For earlier chips we have to calculate the scaling
337 * ratio by hand and program it into the
338 * PFIT_PGM_RATIO register
339 */
49be663f
CW
340 if (scaled_width > scaled_height) { /* pillar */
341 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
342
343 border = LVDS_BORDER_ENABLE;
344 if (mode->vdisplay != adjusted_mode->vdisplay) {
345 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
346 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
347 bits << PFIT_VERT_SCALE_SHIFT);
348 pfit_control |= (PFIT_ENABLE |
349 VERT_INTERP_BILINEAR |
350 HORIZ_INTERP_BILINEAR);
351 }
352 } else if (scaled_width < scaled_height) { /* letter */
353 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
354
355 border = LVDS_BORDER_ENABLE;
356 if (mode->hdisplay != adjusted_mode->hdisplay) {
357 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
358 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
359 bits << PFIT_VERT_SCALE_SHIFT);
360 pfit_control |= (PFIT_ENABLE |
361 VERT_INTERP_BILINEAR |
362 HORIZ_INTERP_BILINEAR);
363 }
364 } else
365 /* Aspects match, Let hw scale both directions */
366 pfit_control |= (PFIT_ENABLE |
367 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
368 VERT_INTERP_BILINEAR |
369 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
370 }
371 break;
372
373 case DRM_MODE_SCALE_FULLSCREEN:
374 /*
375 * Full scaling, even if it changes the aspect ratio.
376 * Fortunately this is all done for us in hw.
377 */
257e48f1
CW
378 if (mode->vdisplay != adjusted_mode->vdisplay ||
379 mode->hdisplay != adjusted_mode->hdisplay) {
380 pfit_control |= PFIT_ENABLE;
381 if (INTEL_INFO(dev)->gen >= 4)
382 pfit_control |= PFIT_SCALING_AUTO;
383 else
384 pfit_control |= (VERT_AUTO_SCALE |
385 VERT_INTERP_BILINEAR |
386 HORIZ_AUTO_SCALE |
387 HORIZ_INTERP_BILINEAR);
388 }
3fbe18d6 389 break;
49be663f 390
3fbe18d6
ZY
391 default:
392 break;
393 }
394
395out:
72389a33 396 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
397 if ((pfit_control & PFIT_ENABLE) == 0) {
398 pfit_control = 0;
399 pfit_pgm_ratios = 0;
400 }
72389a33
CW
401
402 /* Make sure pre-965 set dither correctly */
403 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
404 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
405
29b99b48
JN
406 if (pfit_control != lvds_encoder->pfit_control ||
407 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
408 lvds_encoder->pfit_control = pfit_control;
409 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
410 lvds_encoder->pfit_dirty = true;
e9e331a8 411 }
49be663f
CW
412 dev_priv->lvds_border_bits = border;
413
79e53945
JB
414 /*
415 * XXX: It would be nice to support lower refresh rates on the
416 * panels to reduce power consumption, and perhaps match the
417 * user's requested refresh rate.
418 */
419
420 return true;
421}
422
79e53945
JB
423static void intel_lvds_mode_set(struct drm_encoder *encoder,
424 struct drm_display_mode *mode,
425 struct drm_display_mode *adjusted_mode)
426{
79e53945
JB
427 /*
428 * The LVDS pin pair will already have been turned on in the
429 * intel_crtc_mode_set since it has a large impact on the DPLL
430 * settings.
431 */
79e53945
JB
432}
433
434/**
435 * Detect the LVDS connection.
436 *
b42d4c5c
JB
437 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
438 * connected and closed means disconnected. We also send hotplug events as
439 * needed, using lid status notification from the input layer.
79e53945 440 */
7b334fcb 441static enum drm_connector_status
930a9e28 442intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 443{
7b9c5abe 444 struct drm_device *dev = connector->dev;
6ee3b5a1 445 enum drm_connector_status status;
b42d4c5c 446
fe16d949
CW
447 status = intel_panel_detect(dev);
448 if (status != connector_status_unknown)
449 return status;
01fe9dbd 450
6ee3b5a1 451 return connector_status_connected;
79e53945
JB
452}
453
454/**
455 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
456 */
457static int intel_lvds_get_modes(struct drm_connector *connector)
458{
62165e0d 459 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 460 struct drm_device *dev = connector->dev;
788319d4 461 struct drm_display_mode *mode;
79e53945 462
62165e0d
JN
463 if (lvds_connector->edid)
464 return drm_add_edid_modes(connector, lvds_connector->edid);
79e53945 465
dd06f90e 466 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 467 if (mode == NULL)
788319d4 468 return 0;
79e53945 469
788319d4
CW
470 drm_mode_probed_add(connector, mode);
471 return 1;
79e53945
JB
472}
473
0544edfd
TB
474static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
475{
bc0daf48 476 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
477 return 1;
478}
479
480/* The GPU hangs up on these systems if modeset is performed on LID open */
481static const struct dmi_system_id intel_no_modeset_on_lid[] = {
482 {
483 .callback = intel_no_modeset_on_lid_dmi_callback,
484 .ident = "Toshiba Tecra A11",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
487 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
488 },
489 },
490
491 { } /* terminating entry */
492};
493
c9354c85
LT
494/*
495 * Lid events. Note the use of 'modeset_on_lid':
496 * - we set it on lid close, and reset it on open
497 * - we use it as a "only once" bit (ie we ignore
498 * duplicate events where it was already properly
499 * set/reset)
500 * - the suspend/resume paths will also set it to
501 * zero, since they restore the mode ("lid open").
502 */
c1c7af60
JB
503static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
504 void *unused)
505{
db1740a0
JN
506 struct intel_lvds_connector *lvds_connector =
507 container_of(nb, struct intel_lvds_connector, lid_notifier);
508 struct drm_connector *connector = &lvds_connector->base.base;
509 struct drm_device *dev = connector->dev;
510 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 511
2fb4e61d
AW
512 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
513 return NOTIFY_OK;
514
a2565377
ZY
515 /*
516 * check and update the status of LVDS connector after receiving
517 * the LID nofication event.
518 */
db1740a0 519 connector->status = connector->funcs->detect(connector, false);
7b334fcb 520
0544edfd
TB
521 /* Don't force modeset on machines where it causes a GPU lockup */
522 if (dmi_check_system(intel_no_modeset_on_lid))
523 return NOTIFY_OK;
c9354c85
LT
524 if (!acpi_lid_open()) {
525 dev_priv->modeset_on_lid = 1;
526 return NOTIFY_OK;
06891e27 527 }
c1c7af60 528
c9354c85
LT
529 if (!dev_priv->modeset_on_lid)
530 return NOTIFY_OK;
531
532 dev_priv->modeset_on_lid = 0;
533
534 mutex_lock(&dev->mode_config.mutex);
3b7a89fc 535 intel_modeset_check_state(dev);
c9354c85 536 mutex_unlock(&dev->mode_config.mutex);
06324194 537
c1c7af60
JB
538 return NOTIFY_OK;
539}
540
79e53945
JB
541/**
542 * intel_lvds_destroy - unregister and free LVDS structures
543 * @connector: connector to free
544 *
545 * Unregister the DDC bus for this connector then free the driver private
546 * structure.
547 */
548static void intel_lvds_destroy(struct drm_connector *connector)
549{
db1740a0
JN
550 struct intel_lvds_connector *lvds_connector =
551 to_lvds_connector(connector);
552
553 if (lvds_connector->lid_notifier.notifier_call)
554 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 555
db1740a0 556 intel_panel_destroy_backlight(connector->dev);
1d508706 557 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 558
79e53945
JB
559 drm_sysfs_connector_remove(connector);
560 drm_connector_cleanup(connector);
561 kfree(connector);
562}
563
335041ed
JB
564static int intel_lvds_set_property(struct drm_connector *connector,
565 struct drm_property *property,
566 uint64_t value)
567{
62165e0d 568 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
3fbe18d6 569 struct drm_device *dev = connector->dev;
3fbe18d6 570
788319d4 571 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 572 struct drm_crtc *crtc;
bb8a3560 573
53bd8389
JB
574 if (value == DRM_MODE_SCALE_NONE) {
575 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 576 return -EINVAL;
3fbe18d6 577 }
788319d4 578
62165e0d 579 if (lvds_connector->fitting_mode == value) {
3fbe18d6
ZY
580 /* the LVDS scaling property is not changed */
581 return 0;
582 }
62165e0d
JN
583 lvds_connector->fitting_mode = value;
584
585 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
586 if (crtc && crtc->enabled) {
587 /*
588 * If the CRTC is enabled, the display will be changed
589 * according to the new panel fitting mode.
590 */
a6778b3c
DV
591 intel_set_mode(crtc, &crtc->mode,
592 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
593 }
594 }
595
335041ed
JB
596 return 0;
597}
598
79e53945 599static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 600 .mode_fixup = intel_lvds_mode_fixup,
79e53945 601 .mode_set = intel_lvds_mode_set,
1f703855 602 .disable = intel_encoder_noop,
79e53945
JB
603};
604
605static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
606 .get_modes = intel_lvds_get_modes,
607 .mode_valid = intel_lvds_mode_valid,
df0e9248 608 .best_encoder = intel_best_encoder,
79e53945
JB
609};
610
611static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 612 .dpms = intel_connector_dpms,
79e53945
JB
613 .detect = intel_lvds_detect,
614 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 615 .set_property = intel_lvds_set_property,
79e53945
JB
616 .destroy = intel_lvds_destroy,
617};
618
79e53945 619static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 620 .destroy = intel_encoder_destroy,
79e53945
JB
621};
622
425d244c
JW
623static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
624{
bc0daf48 625 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
626 return 1;
627}
79e53945 628
425d244c 629/* These systems claim to have LVDS, but really don't */
93c05f22 630static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
631 {
632 .callback = intel_no_lvds_dmi_callback,
633 .ident = "Apple Mac Mini (Core series)",
634 .matches = {
98acd46f 635 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
636 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
637 },
638 },
639 {
640 .callback = intel_no_lvds_dmi_callback,
641 .ident = "Apple Mac Mini (Core 2 series)",
642 .matches = {
98acd46f 643 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
644 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
645 },
646 },
647 {
648 .callback = intel_no_lvds_dmi_callback,
649 .ident = "MSI IM-945GSE-A",
650 .matches = {
651 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
652 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
653 },
654 },
655 {
656 .callback = intel_no_lvds_dmi_callback,
657 .ident = "Dell Studio Hybrid",
658 .matches = {
659 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
660 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
661 },
662 },
70aa96ca
JW
663 {
664 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
665 .ident = "Dell OptiPlex FX170",
666 .matches = {
667 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
668 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
669 },
670 },
671 {
672 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
673 .ident = "AOpen Mini PC",
674 .matches = {
675 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
676 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
677 },
678 },
ed8c754b
TV
679 {
680 .callback = intel_no_lvds_dmi_callback,
681 .ident = "AOpen Mini PC MP915",
682 .matches = {
683 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
684 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
685 },
686 },
22ab70d3
KP
687 {
688 .callback = intel_no_lvds_dmi_callback,
689 .ident = "AOpen i915GMm-HFS",
690 .matches = {
691 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
692 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
693 },
694 },
e57b6886
DV
695 {
696 .callback = intel_no_lvds_dmi_callback,
697 .ident = "AOpen i45GMx-I",
698 .matches = {
699 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
700 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
701 },
702 },
fa0864b2
MC
703 {
704 .callback = intel_no_lvds_dmi_callback,
705 .ident = "Aopen i945GTt-VFA",
706 .matches = {
707 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
708 },
709 },
9875557e
SB
710 {
711 .callback = intel_no_lvds_dmi_callback,
712 .ident = "Clientron U800",
713 .matches = {
714 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
715 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
716 },
717 },
6a574b5b 718 {
44306ab3
JS
719 .callback = intel_no_lvds_dmi_callback,
720 .ident = "Clientron E830",
721 .matches = {
722 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
723 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
724 },
725 },
726 {
6a574b5b
HG
727 .callback = intel_no_lvds_dmi_callback,
728 .ident = "Asus EeeBox PC EB1007",
729 .matches = {
730 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
731 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
732 },
733 },
0999bbe0
AJ
734 {
735 .callback = intel_no_lvds_dmi_callback,
736 .ident = "Asus AT5NM10T-I",
737 .matches = {
738 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
739 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
740 },
741 },
33471119
JBG
742 {
743 .callback = intel_no_lvds_dmi_callback,
744 .ident = "Hewlett-Packard HP t5740e Thin Client",
745 .matches = {
746 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
747 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
748 },
749 },
f5b8a7ed
MG
750 {
751 .callback = intel_no_lvds_dmi_callback,
752 .ident = "Hewlett-Packard t5745",
753 .matches = {
754 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 755 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
756 },
757 },
758 {
759 .callback = intel_no_lvds_dmi_callback,
760 .ident = "Hewlett-Packard st5747",
761 .matches = {
762 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 763 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
764 },
765 },
97effadb
AA
766 {
767 .callback = intel_no_lvds_dmi_callback,
768 .ident = "MSI Wind Box DC500",
769 .matches = {
770 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
771 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
772 },
773 },
9756fe38
SS
774 {
775 .callback = intel_no_lvds_dmi_callback,
776 .ident = "ZOTAC ZBOXSD-ID12/ID13",
777 .matches = {
778 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
779 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
780 },
781 },
a51d4ed0
CW
782 {
783 .callback = intel_no_lvds_dmi_callback,
784 .ident = "Gigabyte GA-D525TUD",
785 .matches = {
786 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
787 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
788 },
789 },
425d244c
JW
790
791 { } /* terminating entry */
792};
79e53945 793
18f9ed12
ZY
794/**
795 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
796 * @dev: drm device
797 * @connector: LVDS connector
798 *
799 * Find the reduced downclock for LVDS in EDID.
800 */
801static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
802 struct drm_display_mode *fixed_mode,
803 struct drm_connector *connector)
18f9ed12
ZY
804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 806 struct drm_display_mode *scan;
18f9ed12
ZY
807 int temp_downclock;
808
788319d4 809 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
810 list_for_each_entry(scan, &connector->probed_modes, head) {
811 /*
812 * If one mode has the same resolution with the fixed_panel
813 * mode while they have the different refresh rate, it means
814 * that the reduced downclock is found for the LVDS. In such
815 * case we can set the different FPx0/1 to dynamically select
816 * between low and high frequency.
817 */
788319d4
CW
818 if (scan->hdisplay == fixed_mode->hdisplay &&
819 scan->hsync_start == fixed_mode->hsync_start &&
820 scan->hsync_end == fixed_mode->hsync_end &&
821 scan->htotal == fixed_mode->htotal &&
822 scan->vdisplay == fixed_mode->vdisplay &&
823 scan->vsync_start == fixed_mode->vsync_start &&
824 scan->vsync_end == fixed_mode->vsync_end &&
825 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
826 if (scan->clock < temp_downclock) {
827 /*
828 * The downclock is already found. But we
829 * expect to find the lower downclock.
830 */
831 temp_downclock = scan->clock;
832 }
833 }
834 }
788319d4 835 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
836 /* We found the downclock for LVDS. */
837 dev_priv->lvds_downclock_avail = 1;
838 dev_priv->lvds_downclock = temp_downclock;
839 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
840 "Normal clock %dKhz, downclock %dKhz\n",
841 fixed_mode->clock, temp_downclock);
18f9ed12 842 }
18f9ed12
ZY
843}
844
7cf4f69d
ZY
845/*
846 * Enumerate the child dev array parsed from VBT to check whether
847 * the LVDS is present.
848 * If it is present, return 1.
849 * If it is not present, return false.
850 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 851 */
270eea0f
CW
852static bool lvds_is_present_in_vbt(struct drm_device *dev,
853 u8 *i2c_pin)
7cf4f69d
ZY
854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 856 int i;
7cf4f69d
ZY
857
858 if (!dev_priv->child_dev_num)
425904dd 859 return true;
7cf4f69d 860
7cf4f69d 861 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
862 struct child_device_config *child = dev_priv->child_dev + i;
863
864 /* If the device type is not LFP, continue.
865 * We have to check both the new identifiers as well as the
866 * old for compatibility with some BIOSes.
7cf4f69d 867 */
425904dd
CW
868 if (child->device_type != DEVICE_TYPE_INT_LFP &&
869 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
870 continue;
871
3bd7d909
DK
872 if (intel_gmbus_is_port_valid(child->i2c_pin))
873 *i2c_pin = child->i2c_pin;
270eea0f 874
425904dd
CW
875 /* However, we cannot trust the BIOS writers to populate
876 * the VBT correctly. Since LVDS requires additional
877 * information from AIM blocks, a non-zero addin offset is
878 * a good indicator that the LVDS is actually present.
7cf4f69d 879 */
425904dd
CW
880 if (child->addin_offset)
881 return true;
882
883 /* But even then some BIOS writers perform some black magic
884 * and instantiate the device without reference to any
885 * additional data. Trust that if the VBT was written into
886 * the OpRegion then they have validated the LVDS's existence.
887 */
888 if (dev_priv->opregion.vbt)
889 return true;
7cf4f69d 890 }
425904dd
CW
891
892 return false;
7cf4f69d
ZY
893}
894
f3cfcba6
CW
895static bool intel_lvds_supported(struct drm_device *dev)
896{
897 /* With the introduction of the PCH we gained a dedicated
898 * LVDS presence pin, use it. */
899 if (HAS_PCH_SPLIT(dev))
900 return true;
901
902 /* Otherwise LVDS was only attached to mobile products,
903 * except for the inglorious 830gm */
904 return IS_MOBILE(dev) && !IS_I830(dev);
905}
906
79e53945
JB
907/**
908 * intel_lvds_init - setup LVDS connectors on this device
909 * @dev: drm device
910 *
911 * Create the connector, register the LVDS DDC bus, and try to figure out what
912 * modes we can display on the LVDS panel (if present).
913 */
c5d1b51d 914bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
915{
916 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 917 struct intel_lvds_encoder *lvds_encoder;
21d40d37 918 struct intel_encoder *intel_encoder;
c7362c4d 919 struct intel_lvds_connector *lvds_connector;
bb8a3560 920 struct intel_connector *intel_connector;
79e53945
JB
921 struct drm_connector *connector;
922 struct drm_encoder *encoder;
923 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 924 struct drm_display_mode *fixed_mode = NULL;
79e53945
JB
925 struct drm_crtc *crtc;
926 u32 lvds;
270eea0f
CW
927 int pipe;
928 u8 pin;
79e53945 929
f3cfcba6
CW
930 if (!intel_lvds_supported(dev))
931 return false;
932
425d244c
JW
933 /* Skip init on machines we know falsely report LVDS */
934 if (dmi_check_system(intel_no_lvds))
c5d1b51d 935 return false;
565dcd46 936
270eea0f
CW
937 pin = GMBUS_PORT_PANEL;
938 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 939 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 940 return false;
38b3037e 941 }
e99da35f 942
c619eed4 943 if (HAS_PCH_SPLIT(dev)) {
541998a1 944 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 945 return false;
5ceb0f9b 946 if (dev_priv->edp.support) {
28c97730 947 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 948 return false;
32f9d658 949 }
541998a1
ZW
950 }
951
29b99b48
JN
952 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
953 if (!lvds_encoder)
c5d1b51d 954 return false;
79e53945 955
c7362c4d
JN
956 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
957 if (!lvds_connector) {
29b99b48 958 kfree(lvds_encoder);
c5d1b51d 959 return false;
bb8a3560
ZW
960 }
961
62165e0d
JN
962 lvds_encoder->attached_connector = lvds_connector;
963
e9e331a8 964 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 965 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
966 }
967
29b99b48 968 intel_encoder = &lvds_encoder->base;
4ef69c7a 969 encoder = &intel_encoder->base;
c7362c4d 970 intel_connector = &lvds_connector->base;
ea5b213a 971 connector = &intel_connector->base;
bb8a3560 972 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
973 DRM_MODE_CONNECTOR_LVDS);
974
4ef69c7a 975 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
976 DRM_MODE_ENCODER_LVDS);
977
c22834ec
DV
978 intel_encoder->enable = intel_enable_lvds;
979 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
980 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
981 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 982
df0e9248 983 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 984 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 985
66a9278e 986 intel_encoder->cloneable = false;
27f8227b
JB
987 if (HAS_PCH_SPLIT(dev))
988 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
989 else if (IS_GEN4(dev))
990 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
991 else
992 intel_encoder->crtc_mask = (1 << 1);
993
79e53945
JB
994 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
995 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
996 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
997 connector->interlace_allowed = false;
998 connector->doublescan_allowed = false;
999
3fbe18d6
ZY
1000 /* create the scaling mode property */
1001 drm_mode_create_scaling_mode_property(dev);
1002 /*
1003 * the initial panel fitting mode will be FULL_SCREEN.
1004 */
79e53945 1005
bb8a3560 1006 drm_connector_attach_property(&intel_connector->base,
3fbe18d6 1007 dev->mode_config.scaling_mode_property,
dd1ea37d 1008 DRM_MODE_SCALE_ASPECT);
62165e0d 1009 lvds_connector->fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1010 /*
1011 * LVDS discovery:
1012 * 1) check for EDID on DDC
1013 * 2) check for VBT data
1014 * 3) check to see if LVDS is already on
1015 * if none of the above, no panel
1016 * 4) make sure lid is open
1017 * if closed, act like it's not there for now
1018 */
1019
79e53945
JB
1020 /*
1021 * Attempt to get the fixed panel mode from DDC. Assume that the
1022 * preferred mode is the right one.
1023 */
62165e0d
JN
1024 lvds_connector->edid = drm_get_edid(connector,
1025 intel_gmbus_get_adapter(dev_priv, pin));
1026 if (lvds_connector->edid) {
1027 if (drm_add_edid_modes(connector, lvds_connector->edid)) {
3f8ff0e7 1028 drm_mode_connector_update_edid_property(connector,
62165e0d 1029 lvds_connector->edid);
3f8ff0e7 1030 } else {
62165e0d
JN
1031 kfree(lvds_connector->edid);
1032 lvds_connector->edid = NULL;
3f8ff0e7
CW
1033 }
1034 }
62165e0d 1035 if (!lvds_connector->edid) {
788319d4
CW
1036 /* Didn't get an EDID, so
1037 * Set wide sync ranges so we get all modes
1038 * handed to valid_mode for checking
1039 */
1040 connector->display_info.min_vfreq = 0;
1041 connector->display_info.max_vfreq = 200;
1042 connector->display_info.min_hfreq = 0;
1043 connector->display_info.max_hfreq = 200;
1044 }
79e53945
JB
1045
1046 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1047 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
dd06f90e
JN
1048 fixed_mode = drm_mode_duplicate(dev, scan);
1049 intel_find_lvds_downclock(dev, fixed_mode, connector);
565dcd46 1050 goto out;
79e53945 1051 }
79e53945
JB
1052 }
1053
1054 /* Failed to get EDID, what about VBT? */
88631706 1055 if (dev_priv->lfp_lvds_vbt_mode) {
dd06f90e
JN
1056 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1057 if (fixed_mode) {
1058 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1059 goto out;
1060 }
79e53945
JB
1061 }
1062
1063 /*
1064 * If we didn't get EDID, try checking if the panel is already turned
1065 * on. If so, assume that whatever is currently programmed is the
1066 * correct mode.
1067 */
541998a1 1068
f2b115e6 1069 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1070 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1071 goto failed;
1072
79e53945
JB
1073 lvds = I915_READ(LVDS);
1074 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1075 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1076
1077 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1078 fixed_mode = intel_crtc_mode_get(dev, crtc);
1079 if (fixed_mode) {
1080 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1081 goto out;
79e53945
JB
1082 }
1083 }
1084
1085 /* If we still don't have a mode after all that, give up. */
dd06f90e 1086 if (!fixed_mode)
79e53945
JB
1087 goto failed;
1088
79e53945 1089out:
24ded204
DV
1090 /*
1091 * Unlock registers and just
1092 * leave them unlocked
1093 */
c619eed4 1094 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1095 I915_WRITE(PCH_PP_CONTROL,
1096 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1097 } else {
ed10fca9
KP
1098 I915_WRITE(PP_CONTROL,
1099 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1100 }
db1740a0
JN
1101 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1102 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1103 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1104 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1105 }
79e53945 1106 drm_sysfs_connector_add(connector);
aaa6fd2a 1107
dd06f90e 1108 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1109 intel_panel_setup_backlight(connector);
aaa6fd2a 1110
c5d1b51d 1111 return true;
79e53945
JB
1112
1113failed:
8a4c47f3 1114 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1115 drm_connector_cleanup(connector);
1991bdfa 1116 drm_encoder_cleanup(encoder);
dd06f90e
JN
1117 if (fixed_mode)
1118 drm_mode_destroy(dev, fixed_mode);
29b99b48 1119 kfree(lvds_encoder);
c7362c4d 1120 kfree(lvds_connector);
c5d1b51d 1121 return false;
79e53945 1122}
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