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Merge branch 'for-linus' into next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
02e792fb
DV		 30#include "i915_drv.h"
31#include "i915_reg.h"
32#include "intel_drv.h"
33
34/* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38#define IMAGE_MAX_WIDTH 2048
39#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40/* on 830 and 845 these large limits result in the card hanging */
41#define IMAGE_MAX_WIDTH_LEGACY 1024
42#define IMAGE_MAX_HEIGHT_LEGACY 1088
43
44/* overlay register definitions */
45/* OCMD register */
46#define OCMD_TILED_SURFACE (0x1<<19)
47#define OCMD_MIRROR_MASK (0x3<<17)
48#define OCMD_MIRROR_MODE (0x3<<17)
49#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50#define OCMD_MIRROR_VERTICAL (0x2<<17)
51#define OCMD_MIRROR_BOTH (0x3<<17)
52#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60#define OCMD_YUV_422_PACKED (0x8<<10)
61#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62#define OCMD_YUV_420_PLANAR (0xc<<10)
63#define OCMD_YUV_422_PLANAR (0xd<<10)
64#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 67#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 68#define OCMD_BUF_TYPE_FRAME (0x0<<5)
69#define OCMD_BUF_TYPE_FIELD (0x1<<5)
70#define OCMD_TEST_MODE (0x1<<4)
71#define OCMD_BUFFER_SELECT (0x3<<2)
72#define OCMD_BUFFER0 (0x0<<2)
73#define OCMD_BUFFER1 (0x1<<2)
74#define OCMD_FIELD_SELECT (0x1<<2)
75#define OCMD_FIELD0 (0x0<<1)
76#define OCMD_FIELD1 (0x1<<1)
77#define OCMD_ENABLE (0x1<<0)
78
79/* OCONFIG register */
80#define OCONF_PIPE_MASK (0x1<<18)
81#define OCONF_PIPE_A (0x0<<18)
82#define OCONF_PIPE_B (0x1<<18)
83#define OCONF_GAMMA2_ENABLE (0x1<<16)
84#define OCONF_CSC_MODE_BT601 (0x0<<5)
85#define OCONF_CSC_MODE_BT709 (0x1<<5)
86#define OCONF_CSC_BYPASS (0x1<<4)
87#define OCONF_CC_OUT_8BIT (0x1<<3)
88#define OCONF_TEST_MODE (0x1<<2)
89#define OCONF_THREE_LINE_BUFFER (0x1<<0)
90#define OCONF_TWO_LINE_BUFFER (0x0<<0)
91
92/* DCLRKM (dst-key) register */
93#define DST_KEY_ENABLE (0x1<<31)
94#define CLK_RGB24_MASK 0x0
95#define CLK_RGB16_MASK 0x070307
96#define CLK_RGB15_MASK 0x070707
97#define CLK_RGB8I_MASK 0xffffff
98
99#define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101#define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
103
104/* overlay flip addr flag */
105#define OFC_UPDATE 0x1
106
107/* polyphase filter coefficients */
108#define N_HORIZ_Y_TAPS 5
109#define N_VERT_Y_TAPS 3
110#define N_HORIZ_UV_TAPS 3
111#define N_VERT_UV_TAPS 3
112#define N_PHASES 17
113#define MAX_TAPS 5
114
115/* memory bufferd overlay registers */
116struct overlay_registers {
0206e353
AJ		 117 u32 OBUF_0Y;
118 u32 OBUF_1Y;
119 u32 OBUF_0U;
120 u32 OBUF_0V;
121 u32 OBUF_1U;
122 u32 OBUF_1V;
123 u32 OSTRIDE;
124 u32 YRGB_VPH;
125 u32 UV_VPH;
126 u32 HORZ_PH;
127 u32 INIT_PHS;
128 u32 DWINPOS;
129 u32 DWINSZ;
130 u32 SWIDTH;
131 u32 SWIDTHSW;
132 u32 SHEIGHT;
133 u32 YRGBSCALE;
134 u32 UVSCALE;
135 u32 OCLRC0;
136 u32 OCLRC1;
137 u32 DCLRKV;
138 u32 DCLRKM;
139 u32 SCLRKVH;
140 u32 SCLRKVL;
141 u32 SCLRKEN;
142 u32 OCONFIG;
143 u32 OCMD;
144 u32 RESERVED1; /* 0x6C */
145 u32 OSTART_0Y;
146 u32 OSTART_1Y;
147 u32 OSTART_0U;
148 u32 OSTART_0V;
149 u32 OSTART_1U;
150 u32 OSTART_1V;
151 u32 OTILEOFF_0Y;
152 u32 OTILEOFF_1Y;
153 u32 OTILEOFF_0U;
154 u32 OTILEOFF_0V;
155 u32 OTILEOFF_1U;
156 u32 OTILEOFF_1V;
157 u32 FASTHSCALE; /* 0xA0 */
158 u32 UVSCALEV; /* 0xA4 */
159 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
161 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
162 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
163 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
164 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
165 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
166 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
167 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
02e792fb
DV		 168};
169
23f09ce3
CW		 170struct intel_overlay {
171 struct drm_device *dev;
172 struct intel_crtc *crtc;
173 struct drm_i915_gem_object *vid_bo;
174 struct drm_i915_gem_object *old_vid_bo;
209c2a5e
VS		 175 bool active;
176 bool pfit_active;
23f09ce3 177 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
ea9da4e4
CW		 178 u32 color_key:24;
179 u32 color_key_enabled:1;
23f09ce3
CW		 180 u32 brightness, contrast, saturation;
181 u32 old_xscale, old_yscale;
182 /* register access */
183 u32 flip_addr;
184 struct drm_i915_gem_object *reg_bo;
185 /* flip handling */
9bfc01a2 186 struct drm_i915_gem_request *last_flip_req;
b303cf95 187 void (*flip_tail)(struct intel_overlay *);
23f09ce3 188};
02e792fb 189
75020bc1 190static struct overlay_registers __iomem *
8d74f656 191intel_overlay_map_regs(struct intel_overlay *overlay)
02e792fb 192{
d5d45cc5 193 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
75020bc1 194 struct overlay_registers __iomem *regs;
02e792fb 195
9bb2ff73 196 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
00731155 197 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
9bb2ff73 198 else
5d4545ae 199 regs = io_mapping_map_wc(dev_priv->gtt.mappable,
f343c5f6 200 i915_gem_obj_ggtt_offset(overlay->reg_bo));
02e792fb 201
9bb2ff73 202 return regs;
8d74f656 203}
02e792fb 204
9bb2ff73 205static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
75020bc1 206 struct overlay_registers __iomem *regs)
8d74f656
CW		 207{
208 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 209 io_mapping_unmap(regs);
02e792fb
DV		 210}
211
b6c028e0 212static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
dad540ce 213 struct drm_i915_gem_request *req,
b303cf95 214 void (*tail)(struct intel_overlay *))
02e792fb 215{
b6c028e0 216 int ret;
02e792fb 217
77589f56 218 WARN_ON(overlay->last_flip_req);
dad540ce 219 i915_gem_request_assign(&overlay->last_flip_req, req);
75289874 220 i915_add_request(req);
acb868d3 221
b303cf95 222 overlay->flip_tail = tail;
a4b3a571 223 ret = i915_wait_request(overlay->last_flip_req);
b6c028e0 224 if (ret)
03f77ea5 225 return ret;
02e792fb 226
9bfc01a2 227 i915_gem_request_assign(&overlay->last_flip_req, NULL);
02e792fb 228 return 0;
02e792fb
DV		 229}
230
02e792fb
DV		 231/* overlay needs to be disable in OCMD reg */
232static int intel_overlay_on(struct intel_overlay *overlay)
233{
234 struct drm_device *dev = overlay->dev;
e1f99ce6 235 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 236 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
dad540ce 237 struct drm_i915_gem_request *req;
02e792fb 238 int ret;
02e792fb 239
77589f56 240 WARN_ON(overlay->active);
6306cb4f 241 WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
106dadac 242
26827088
DG		 243 req = i915_gem_request_alloc(ring, NULL);
244 if (IS_ERR(req))
245 return PTR_ERR(req);
e1f99ce6 246
5fb9de1a 247 ret = intel_ring_begin(req, 4);
dad540ce
JH		 248 if (ret) {
249 i915_gem_request_cancel(req);
250 return ret;
251 }
252
1c7c4301
VS		 253 overlay->active = true;
254
6d90c952
DV		 255 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
256 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
257 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
258 intel_ring_emit(ring, MI_NOOP);
259 intel_ring_advance(ring);
02e792fb 260
dad540ce 261 return intel_overlay_do_wait_request(overlay, req, NULL);
02e792fb
DV		 262}
263
264/* overlay needs to be enabled in OCMD reg */
8dc5d147
CW		 265static int intel_overlay_continue(struct intel_overlay *overlay,
266 bool load_polyphase_filter)
02e792fb
DV		 267{
268 struct drm_device *dev = overlay->dev;
d5d45cc5 269 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 270 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
dad540ce 271 struct drm_i915_gem_request *req;
02e792fb
DV		 272 u32 flip_addr = overlay->flip_addr;
273 u32 tmp;
e1f99ce6 274 int ret;
02e792fb 275
77589f56 276 WARN_ON(!overlay->active);
02e792fb
DV		 277
278 if (load_polyphase_filter)
279 flip_addr |= OFC_UPDATE;
280
281 /* check for underruns */
282 tmp = I915_READ(DOVSTA);
283 if (tmp & (1 << 17))
284 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
285
26827088
DG		 286 req = i915_gem_request_alloc(ring, NULL);
287 if (IS_ERR(req))
288 return PTR_ERR(req);
acb868d3 289
5fb9de1a 290 ret = intel_ring_begin(req, 2);
dad540ce
JH		 291 if (ret) {
292 i915_gem_request_cancel(req);
293 return ret;
294 }
295
6d90c952
DV		 296 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
297 intel_ring_emit(ring, flip_addr);
298 intel_ring_advance(ring);
5a5a0c64 299
9bfc01a2 300 WARN_ON(overlay->last_flip_req);
dad540ce 301 i915_gem_request_assign(&overlay->last_flip_req, req);
75289874 302 i915_add_request(req);
bf7dc5b7
JH		 303
304 return 0;
5a5a0c64
DV		 305}
306
b303cf95 307static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
5a5a0c64 308{
05394f39 309 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
5a5a0c64 310
d7f46fc4 311 i915_gem_object_ggtt_unpin(obj);
05394f39 312 drm_gem_object_unreference(&obj->base);
5a5a0c64 313
b303cf95
CW		 314 overlay->old_vid_bo = NULL;
315}
03f77ea5 316
b303cf95
CW		 317static void intel_overlay_off_tail(struct intel_overlay *overlay)
318{
05394f39 319 struct drm_i915_gem_object *obj = overlay->vid_bo;
02e792fb 320
b303cf95 321 /* never have the overlay hw on without showing a frame */
77589f56
VS		 322 if (WARN_ON(!obj))
323 return;
02e792fb 324
d7f46fc4 325 i915_gem_object_ggtt_unpin(obj);
05394f39 326 drm_gem_object_unreference(&obj->base);
b303cf95 327 overlay->vid_bo = NULL;
03f77ea5 328
b303cf95
CW		 329 overlay->crtc->overlay = NULL;
330 overlay->crtc = NULL;
209c2a5e 331 overlay->active = false;
02e792fb
DV		 332}
333
334/* overlay needs to be disabled in OCMD reg */
ce453d81 335static int intel_overlay_off(struct intel_overlay *overlay)
02e792fb 336{
02e792fb 337 struct drm_device *dev = overlay->dev;
e1f99ce6 338 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 339 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
dad540ce 340 struct drm_i915_gem_request *req;
8dc5d147 341 u32 flip_addr = overlay->flip_addr;
e1f99ce6 342 int ret;
02e792fb 343
77589f56 344 WARN_ON(!overlay->active);
02e792fb
DV		 345
346 /* According to intel docs the overlay hw may hang (when switching
347 * off) without loading the filter coeffs. It is however unclear whether
348 * this applies to the disabling of the overlay or to the switching off
349 * of the hw. Do it in both cases */
350 flip_addr |= OFC_UPDATE;
351
26827088
DG		 352 req = i915_gem_request_alloc(ring, NULL);
353 if (IS_ERR(req))
354 return PTR_ERR(req);
acb868d3 355
5fb9de1a 356 ret = intel_ring_begin(req, 6);
dad540ce
JH		 357 if (ret) {
358 i915_gem_request_cancel(req);
359 return ret;
360 }
361
02e792fb 362 /* wait for overlay to go idle */
6d90c952
DV		 363 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
364 intel_ring_emit(ring, flip_addr);
365 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb 366 /* turn overlay off */
a9193983
DV		 367 if (IS_I830(dev)) {
368 /* Workaround: Don't disable the overlay fully, since otherwise
369 * it dies on the next OVERLAY_ON cmd. */
370 intel_ring_emit(ring, MI_NOOP);
371 intel_ring_emit(ring, MI_NOOP);
372 intel_ring_emit(ring, MI_NOOP);
373 } else {
374 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
375 intel_ring_emit(ring, flip_addr);
376 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
377 }
6d90c952 378 intel_ring_advance(ring);
02e792fb 379
dad540ce 380 return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
12ca45fe
DV		 381}
382
03f77ea5
DV		 383/* recover from an interruption due to a signal
384 * We have to be careful not to repeat work forever an make forward progess. */
ce453d81 385static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
03f77ea5 386{
03f77ea5 387 int ret;
03f77ea5 388
9bfc01a2 389 if (overlay->last_flip_req == NULL)
b303cf95 390 return 0;
03f77ea5 391
a4b3a571 392 ret = i915_wait_request(overlay->last_flip_req);
b6c028e0 393 if (ret)
03f77ea5
DV		 394 return ret;
395
b303cf95
CW		 396 if (overlay->flip_tail)
397 overlay->flip_tail(overlay);
03f77ea5 398
9bfc01a2 399 i915_gem_request_assign(&overlay->last_flip_req, NULL);
03f77ea5
DV		 400 return 0;
401}
402
5a5a0c64
DV		 403/* Wait for pending overlay flip and release old frame.
404 * Needs to be called before the overlay register are changed
8d74f656
CW		 405 * via intel_overlay_(un)map_regs
406 */
02e792fb
DV		 407static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
408{
5cd68c98 409 struct drm_device *dev = overlay->dev;
d5d45cc5 410 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 411 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
02e792fb 412 int ret;
02e792fb 413
1362b776
VS		 414 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
415
5cd68c98
CW		 416 /* Only wait if there is actually an old frame to release to
417 * guarantee forward progress.
418 */
03f77ea5
DV		 419 if (!overlay->old_vid_bo)
420 return 0;
421
5cd68c98
CW		 422 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
423 /* synchronous slowpath */
dad540ce
JH		 424 struct drm_i915_gem_request *req;
425
26827088
DG		 426 req = i915_gem_request_alloc(ring, NULL);
427 if (IS_ERR(req))
428 return PTR_ERR(req);
e1f99ce6 429
5fb9de1a 430 ret = intel_ring_begin(req, 2);
dad540ce
JH		 431 if (ret) {
432 i915_gem_request_cancel(req);
433 return ret;
434 }
435
6d90c952
DV		 436 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
437 intel_ring_emit(ring, MI_NOOP);
438 intel_ring_advance(ring);
5cd68c98 439
dad540ce 440 ret = intel_overlay_do_wait_request(overlay, req,
b303cf95 441 intel_overlay_release_old_vid_tail);
5cd68c98
CW		 442 if (ret)
443 return ret;
444 }
02e792fb 445
5cd68c98 446 intel_overlay_release_old_vid_tail(overlay);
a071fa00
DV		 447
448
449 i915_gem_track_fb(overlay->old_vid_bo, NULL,
450 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
02e792fb
DV		 451 return 0;
452}
453
1362b776
VS		 454void intel_overlay_reset(struct drm_i915_private *dev_priv)
455{
456 struct intel_overlay *overlay = dev_priv->overlay;
457
458 if (!overlay)
459 return;
460
461 intel_overlay_release_old_vid(overlay);
462
463 overlay->last_flip_req = NULL;
464 overlay->old_xscale = 0;
465 overlay->old_yscale = 0;
466 overlay->crtc = NULL;
467 overlay->active = false;
468}
469
02e792fb
DV		 470struct put_image_params {
471 int format;
472 short dst_x;
473 short dst_y;
474 short dst_w;
475 short dst_h;
476 short src_w;
477 short src_scan_h;
478 short src_scan_w;
479 short src_h;
480 short stride_Y;
481 short stride_UV;
482 int offset_Y;
483 int offset_U;
484 int offset_V;
485};
486
487static int packed_depth_bytes(u32 format)
488{
489 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 490 case I915_OVERLAY_YUV422:
491 return 4;
492 case I915_OVERLAY_YUV411:
493 /* return 6; not implemented */
494 default:
495 return -EINVAL;
02e792fb
DV		 496 }
497}
498
499static int packed_width_bytes(u32 format, short width)
500{
501 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 502 case I915_OVERLAY_YUV422:
503 return width << 1;
504 default:
505 return -EINVAL;
02e792fb
DV		 506 }
507}
508
509static int uv_hsubsampling(u32 format)
510{
511 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 512 case I915_OVERLAY_YUV422:
513 case I915_OVERLAY_YUV420:
514 return 2;
515 case I915_OVERLAY_YUV411:
516 case I915_OVERLAY_YUV410:
517 return 4;
518 default:
519 return -EINVAL;
02e792fb
DV		 520 }
521}
522
523static int uv_vsubsampling(u32 format)
524{
525 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 526 case I915_OVERLAY_YUV420:
527 case I915_OVERLAY_YUV410:
528 return 2;
529 case I915_OVERLAY_YUV422:
530 case I915_OVERLAY_YUV411:
531 return 1;
532 default:
533 return -EINVAL;
02e792fb
DV		 534 }
535}
536
537static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
538{
539 u32 mask, shift, ret;
a6c45cf0 540 if (IS_GEN2(dev)) {
02e792fb
DV		 541 mask = 0x1f;
542 shift = 5;
a6c45cf0
CW		 543 } else {
544 mask = 0x3f;
545 shift = 6;
02e792fb
DV		 546 }
547 ret = ((offset + width + mask) >> shift) - (offset >> shift);
a6c45cf0 548 if (!IS_GEN2(dev))
02e792fb 549 ret <<= 1;
0206e353 550 ret -= 1;
02e792fb
DV		 551 return ret << 2;
552}
553
554static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
555 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
556 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
557 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
558 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
559 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
560 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
561 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
562 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
563 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
564 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
565 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
566 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
567 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
568 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
569 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
570 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 571 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
572};
573
02e792fb
DV		 574static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
575 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
576 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
577 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
578 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
579 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
580 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
581 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
582 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 583 0x3000, 0x0800, 0x3000
584};
02e792fb 585
75020bc1 586static void update_polyphase_filter(struct overlay_registers __iomem *regs)
02e792fb 587{
75020bc1
BW		 588 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
589 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
590 sizeof(uv_static_hcoeffs));
02e792fb
DV		 591}
592
593static bool update_scaling_factors(struct intel_overlay *overlay,
75020bc1 594 struct overlay_registers __iomem *regs,
02e792fb
DV		 595 struct put_image_params *params)
596{
597 /* fixed point with a 12 bit shift */
598 u32 xscale, yscale, xscale_UV, yscale_UV;
599#define FP_SHIFT 12
600#define FRACT_MASK 0xfff
601 bool scale_changed = false;
602 int uv_hscale = uv_hsubsampling(params->format);
603 int uv_vscale = uv_vsubsampling(params->format);
604
605 if (params->dst_w > 1)
606 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
607 /(params->dst_w);
608 else
609 xscale = 1 << FP_SHIFT;
610
611 if (params->dst_h > 1)
612 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
613 /(params->dst_h);
614 else
615 yscale = 1 << FP_SHIFT;
616
617 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 618 xscale_UV = xscale/uv_hscale;
619 yscale_UV = yscale/uv_vscale;
620 /* make the Y scale to UV scale ratio an exact multiply */
621 xscale = xscale_UV * uv_hscale;
622 yscale = yscale_UV * uv_vscale;
02e792fb 623 /*} else {
722506f0
CW		 624 xscale_UV = 0;
625 yscale_UV = 0;
626 }*/
02e792fb
DV		 627
628 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
629 scale_changed = true;
630 overlay->old_xscale = xscale;
631 overlay->old_yscale = yscale;
632
75020bc1
BW		 633 iowrite32(((yscale & FRACT_MASK) << 20) |
634 ((xscale >> FP_SHIFT) << 16) |
635 ((xscale & FRACT_MASK) << 3),
636 &regs->YRGBSCALE);
722506f0 637
75020bc1
BW		 638 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
639 ((xscale_UV >> FP_SHIFT) << 16) |
640 ((xscale_UV & FRACT_MASK) << 3),
641 &regs->UVSCALE);
722506f0 642
75020bc1
BW		 643 iowrite32((((yscale >> FP_SHIFT) << 16) |
644 ((yscale_UV >> FP_SHIFT) << 0)),
645 &regs->UVSCALEV);
02e792fb
DV		 646
647 if (scale_changed)
648 update_polyphase_filter(regs);
649
650 return scale_changed;
651}
652
653static void update_colorkey(struct intel_overlay *overlay,
75020bc1 654 struct overlay_registers __iomem *regs)
02e792fb
DV		 655{
656 u32 key = overlay->color_key;
ea9da4e4
CW		 657 u32 flags;
658
659 flags = 0;
660 if (overlay->color_key_enabled)
661 flags |= DST_KEY_ENABLE;
6ba3ddd9 662
f4510a27 663 switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
722506f0 664 case 8:
ea9da4e4
CW		 665 key = 0;
666 flags |= CLK_RGB8I_MASK;
6ba3ddd9
CW		 667 break;
668
722506f0 669 case 16:
f4510a27 670 if (overlay->crtc->base.primary->fb->depth == 15) {
ea9da4e4
CW		 671 key = RGB15_TO_COLORKEY(key);
672 flags |= CLK_RGB15_MASK;
722506f0 673 } else {
ea9da4e4
CW		 674 key = RGB16_TO_COLORKEY(key);
675 flags |= CLK_RGB16_MASK;
722506f0 676 }
6ba3ddd9
CW		 677 break;
678
722506f0
CW		 679 case 24:
680 case 32:
ea9da4e4 681 flags |= CLK_RGB24_MASK;
6ba3ddd9 682 break;
02e792fb 683 }
ea9da4e4
CW		 684
685 iowrite32(key, &regs->DCLRKV);
686 iowrite32(flags, &regs->DCLRKM);
02e792fb
DV		 687}
688
689static u32 overlay_cmd_reg(struct put_image_params *params)
690{
691 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
692
693 if (params->format & I915_OVERLAY_YUV_PLANAR) {
694 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 695 case I915_OVERLAY_YUV422:
696 cmd |= OCMD_YUV_422_PLANAR;
697 break;
698 case I915_OVERLAY_YUV420:
699 cmd |= OCMD_YUV_420_PLANAR;
700 break;
701 case I915_OVERLAY_YUV411:
702 case I915_OVERLAY_YUV410:
703 cmd |= OCMD_YUV_410_PLANAR;
704 break;
02e792fb
DV		 705 }
706 } else { /* YUV packed */
707 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 708 case I915_OVERLAY_YUV422:
709 cmd |= OCMD_YUV_422_PACKED;
710 break;
711 case I915_OVERLAY_YUV411:
712 cmd |= OCMD_YUV_411_PACKED;
713 break;
02e792fb
DV		 714 }
715
716 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 717 case I915_OVERLAY_NO_SWAP:
718 break;
719 case I915_OVERLAY_UV_SWAP:
720 cmd |= OCMD_UV_SWAP;
721 break;
722 case I915_OVERLAY_Y_SWAP:
723 cmd |= OCMD_Y_SWAP;
724 break;
725 case I915_OVERLAY_Y_AND_UV_SWAP:
726 cmd |= OCMD_Y_AND_UV_SWAP;
727 break;
02e792fb
DV		 728 }
729 }
730
731 return cmd;
732}
733
5fe82c5e 734static int intel_overlay_do_put_image(struct intel_overlay *overlay,
05394f39 735 struct drm_i915_gem_object *new_bo,
5fe82c5e 736 struct put_image_params *params)
02e792fb
DV		 737{
738 int ret, tmp_width;
75020bc1 739 struct overlay_registers __iomem *regs;
02e792fb 740 bool scale_changed = false;
02e792fb 741 struct drm_device *dev = overlay->dev;
75020bc1 742 u32 swidth, swidthsw, sheight, ostride;
a071fa00 743 enum pipe pipe = overlay->crtc->pipe;
02e792fb 744
77589f56
VS		 745 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
746 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
02e792fb 747
02e792fb
DV		 748 ret = intel_overlay_release_old_vid(overlay);
749 if (ret != 0)
750 return ret;
751
7580d774 752 ret = i915_gem_object_pin_to_display_plane(new_bo, 0,
e6617330 753 &i915_ggtt_view_normal);
02e792fb
DV		 754 if (ret != 0)
755 return ret;
756
d9e86c0e
CW		 757 ret = i915_gem_object_put_fence(new_bo);
758 if (ret)
759 goto out_unpin;
760
02e792fb 761 if (!overlay->active) {
75020bc1 762 u32 oconfig;
8d74f656 763 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 764 if (!regs) {
765 ret = -ENOMEM;
766 goto out_unpin;
767 }
75020bc1 768 oconfig = OCONF_CC_OUT_8BIT;
a6c45cf0 769 if (IS_GEN4(overlay->dev))
75020bc1 770 oconfig |= OCONF_CSC_MODE_BT709;
a071fa00 771 oconfig |= pipe == 0 ?
02e792fb 772 OCONF_PIPE_A : OCONF_PIPE_B;
75020bc1 773 iowrite32(oconfig, &regs->OCONFIG);
9bb2ff73 774 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 775
776 ret = intel_overlay_on(overlay);
777 if (ret != 0)
778 goto out_unpin;
779 }
780
8d74f656 781 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 782 if (!regs) {
783 ret = -ENOMEM;
784 goto out_unpin;
785 }
786
75020bc1
BW		 787 iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
788 iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
02e792fb
DV		 789
790 if (params->format & I915_OVERLAY_YUV_PACKED)
791 tmp_width = packed_width_bytes(params->format, params->src_w);
792 else
793 tmp_width = params->src_w;
794
75020bc1
BW		 795 swidth = params->src_w;
796 swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
797 sheight = params->src_h;
f343c5f6 798 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, &regs->OBUF_0Y);
75020bc1 799 ostride = params->stride_Y;
02e792fb
DV		 800
801 if (params->format & I915_OVERLAY_YUV_PLANAR) {
802 int uv_hscale = uv_hsubsampling(params->format);
803 int uv_vscale = uv_vsubsampling(params->format);
804 u32 tmp_U, tmp_V;
75020bc1 805 swidth |= (params->src_w/uv_hscale) << 16;
02e792fb 806 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 807 params->src_w/uv_hscale);
02e792fb 808 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 809 params->src_w/uv_hscale);
75020bc1
BW		 810 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
811 sheight |= (params->src_h/uv_vscale) << 16;
f343c5f6
BW		 812 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, &regs->OBUF_0U);
813 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, &regs->OBUF_0V);
75020bc1 814 ostride |= params->stride_UV << 16;
02e792fb
DV		 815 }
816
75020bc1
BW		 817 iowrite32(swidth, &regs->SWIDTH);
818 iowrite32(swidthsw, &regs->SWIDTHSW);
819 iowrite32(sheight, &regs->SHEIGHT);
820 iowrite32(ostride, &regs->OSTRIDE);
821
02e792fb
DV		 822 scale_changed = update_scaling_factors(overlay, regs, params);
823
824 update_colorkey(overlay, regs);
825
75020bc1 826 iowrite32(overlay_cmd_reg(params), &regs->OCMD);
02e792fb 827
9bb2ff73 828 intel_overlay_unmap_regs(overlay, regs);
02e792fb 829
8dc5d147
CW		 830 ret = intel_overlay_continue(overlay, scale_changed);
831 if (ret)
832 goto out_unpin;
02e792fb 833
a071fa00
DV		 834 i915_gem_track_fb(overlay->vid_bo, new_bo,
835 INTEL_FRONTBUFFER_OVERLAY(pipe));
836
02e792fb 837 overlay->old_vid_bo = overlay->vid_bo;
05394f39 838 overlay->vid_bo = new_bo;
02e792fb 839
f99d7069
DV		 840 intel_frontbuffer_flip(dev,
841 INTEL_FRONTBUFFER_OVERLAY(pipe));
842
02e792fb
DV		 843 return 0;
844
845out_unpin:
d7f46fc4 846 i915_gem_object_ggtt_unpin(new_bo);
02e792fb
DV		 847 return ret;
848}
849
ce453d81 850int intel_overlay_switch_off(struct intel_overlay *overlay)
02e792fb 851{
75020bc1 852 struct overlay_registers __iomem *regs;
02e792fb 853 struct drm_device *dev = overlay->dev;
5dcdbcb0 854 int ret;
02e792fb 855
77589f56
VS		 856 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
857 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
02e792fb 858
ce453d81 859 ret = intel_overlay_recover_from_interrupt(overlay);
b303cf95
CW		 860 if (ret != 0)
861 return ret;
9bedb974 862
02e792fb
DV		 863 if (!overlay->active)
864 return 0;
865
02e792fb
DV		 866 ret = intel_overlay_release_old_vid(overlay);
867 if (ret != 0)
868 return ret;
869
8d74f656 870 regs = intel_overlay_map_regs(overlay);
75020bc1 871 iowrite32(0, &regs->OCMD);
9bb2ff73 872 intel_overlay_unmap_regs(overlay, regs);
02e792fb 873
ce453d81 874 ret = intel_overlay_off(overlay);
03f77ea5
DV		 875 if (ret != 0)
876 return ret;
877
12ca45fe 878 intel_overlay_off_tail(overlay);
02e792fb
DV		 879 return 0;
880}
881
882static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
883 struct intel_crtc *crtc)
884{
f7abfe8b 885 if (!crtc->active)
02e792fb
DV		 886 return -EINVAL;
887
02e792fb 888 /* can't use the overlay with double wide pipe */
6e3c9717 889 if (crtc->config->double_wide)
02e792fb
DV		 890 return -EINVAL;
891
892 return 0;
893}
894
895static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
896{
897 struct drm_device *dev = overlay->dev;
d5d45cc5 898 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 899 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 900 u32 ratio;
02e792fb
DV		 901
902 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 903 * line with the intel documentation for the i965
904 */
a6c45cf0 905 if (INTEL_INFO(dev)->gen >= 4) {
0206e353 906 /* on i965 use the PGM reg to read out the autoscaler values */
a6c45cf0
CW		 907 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
908 } else {
446d2183
CW		 909 if (pfit_control & VERT_AUTO_SCALE)
910 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 911 else
446d2183
CW		 912 ratio = I915_READ(PFIT_PGM_RATIOS);
913 ratio >>= PFIT_VERT_SCALE_SHIFT;
02e792fb
DV		 914 }
915
916 overlay->pfit_vscale_ratio = ratio;
917}
918
919static int check_overlay_dst(struct intel_overlay *overlay,
920 struct drm_intel_overlay_put_image *rec)
921{
922 struct drm_display_mode *mode = &overlay->crtc->base.mode;
923
75c13993
DV		 924 if (rec->dst_x < mode->hdisplay &&
925 rec->dst_x + rec->dst_width <= mode->hdisplay &&
926 rec->dst_y < mode->vdisplay &&
927 rec->dst_y + rec->dst_height <= mode->vdisplay)
02e792fb
DV		 928 return 0;
929 else
930 return -EINVAL;
931}
932
933static int check_overlay_scaling(struct put_image_params *rec)
934{
935 u32 tmp;
936
937 /* downscaling limit is 8.0 */
938 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
939 if (tmp > 7)
940 return -EINVAL;
941 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
942 if (tmp > 7)
943 return -EINVAL;
944
945 return 0;
946}
947
948static int check_overlay_src(struct drm_device *dev,
949 struct drm_intel_overlay_put_image *rec,
05394f39 950 struct drm_i915_gem_object *new_bo)
02e792fb 951{
02e792fb
DV		 952 int uv_hscale = uv_hsubsampling(rec->flags);
953 int uv_vscale = uv_vsubsampling(rec->flags);
8f28f54a
DC		 954 u32 stride_mask;
955 int depth;
956 u32 tmp;
02e792fb
DV		 957
958 /* check src dimensions */
959 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 960 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 961 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 962 return -EINVAL;
963 } else {
722506f0 964 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 965 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 966 return -EINVAL;
967 }
9f7c3f44 968
02e792fb 969 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 970 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 971 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 972 return -EINVAL;
973
a1efd14a 974 /* check alignment constraints */
02e792fb 975 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 976 case I915_OVERLAY_RGB:
977 /* not implemented */
978 return -EINVAL;
9f7c3f44 979
722506f0 980 case I915_OVERLAY_YUV_PACKED:
722506f0 981 if (uv_vscale != 1)
02e792fb 982 return -EINVAL;
9f7c3f44
CW		 983
984 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 985 if (depth < 0)
986 return depth;
9f7c3f44 987
722506f0
CW		 988 /* ignore UV planes */
989 rec->stride_UV = 0;
990 rec->offset_U = 0;
991 rec->offset_V = 0;
992 /* check pixel alignment */
993 if (rec->offset_Y % depth)
994 return -EINVAL;
995 break;
9f7c3f44 996
722506f0
CW		 997 case I915_OVERLAY_YUV_PLANAR:
998 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 999 return -EINVAL;
722506f0
CW		 1000 /* no offset restrictions for planar formats */
1001 break;
9f7c3f44 1002
722506f0
CW		 1003 default:
1004 return -EINVAL;
02e792fb
DV		 1005 }
1006
1007 if (rec->src_width % uv_hscale)
1008 return -EINVAL;
1009
1010 /* stride checking */
a1efd14a
CW		 1011 if (IS_I830(dev) || IS_845G(dev))
1012 stride_mask = 255;
1013 else
1014 stride_mask = 63;
02e792fb
DV		 1015
1016 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1017 return -EINVAL;
a6c45cf0 1018 if (IS_GEN4(dev) && rec->stride_Y < 512)
02e792fb
DV		 1019 return -EINVAL;
1020
1021 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 1022 4096 : 8192;
1023 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 1024 return -EINVAL;
1025
1026 /* check buffer dimensions */
1027 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1028 case I915_OVERLAY_RGB:
1029 case I915_OVERLAY_YUV_PACKED:
1030 /* always 4 Y values per depth pixels */
1031 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1032 return -EINVAL;
1033
1034 tmp = rec->stride_Y*rec->src_height;
05394f39 1035 if (rec->offset_Y + tmp > new_bo->base.size)
722506f0
CW		 1036 return -EINVAL;
1037 break;
1038
1039 case I915_OVERLAY_YUV_PLANAR:
1040 if (rec->src_width > rec->stride_Y)
1041 return -EINVAL;
1042 if (rec->src_width/uv_hscale > rec->stride_UV)
1043 return -EINVAL;
1044
9f7c3f44 1045 tmp = rec->stride_Y * rec->src_height;
05394f39 1046 if (rec->offset_Y + tmp > new_bo->base.size)
722506f0 1047 return -EINVAL;
9f7c3f44
CW		 1048
1049 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
05394f39
CW		 1050 if (rec->offset_U + tmp > new_bo->base.size ||
1051 rec->offset_V + tmp > new_bo->base.size)
722506f0
CW		 1052 return -EINVAL;
1053 break;
02e792fb
DV		 1054 }
1055
1056 return 0;
1057}
1058
e9e331a8
CW		 1059/**
1060 * Return the pipe currently connected to the panel fitter,
1061 * or -1 if the panel fitter is not present or not in use
1062 */
1063static int intel_panel_fitter_pipe(struct drm_device *dev)
1064{
1065 struct drm_i915_private *dev_priv = dev->dev_private;
1066 u32 pfit_control;
1067
1068 /* i830 doesn't have a panel fitter */
dc9e7dec 1069 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
e9e331a8
CW		 1070 return -1;
1071
1072 pfit_control = I915_READ(PFIT_CONTROL);
1073
1074 /* See if the panel fitter is in use */
1075 if ((pfit_control & PFIT_ENABLE) == 0)
1076 return -1;
1077
1078 /* 965 can place panel fitter on either pipe */
a6c45cf0 1079 if (IS_GEN4(dev))
e9e331a8
CW		 1080 return (pfit_control >> 29) & 0x3;
1081
1082 /* older chips can only use pipe 1 */
1083 return 1;
1084}
1085
02e792fb 1086int intel_overlay_put_image(struct drm_device *dev, void *data,
0206e353 1087 struct drm_file *file_priv)
02e792fb
DV		 1088{
1089 struct drm_intel_overlay_put_image *put_image_rec = data;
d5d45cc5 1090 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1091 struct intel_overlay *overlay;
7707e653 1092 struct drm_crtc *drmmode_crtc;
02e792fb 1093 struct intel_crtc *crtc;
05394f39 1094 struct drm_i915_gem_object *new_bo;
02e792fb
DV		 1095 struct put_image_params *params;
1096 int ret;
1097
02e792fb
DV		 1098 overlay = dev_priv->overlay;
1099 if (!overlay) {
1100 DRM_DEBUG("userspace bug: no overlay\n");
1101 return -ENODEV;
1102 }
1103
1104 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
a0e99e68 1105 drm_modeset_lock_all(dev);
02e792fb
DV		 1106 mutex_lock(&dev->struct_mutex);
1107
ce453d81 1108 ret = intel_overlay_switch_off(overlay);
02e792fb
DV		 1109
1110 mutex_unlock(&dev->struct_mutex);
a0e99e68 1111 drm_modeset_unlock_all(dev);
02e792fb
DV		 1112
1113 return ret;
1114 }
1115
b14c5679 1116 params = kmalloc(sizeof(*params), GFP_KERNEL);
02e792fb
DV		 1117 if (!params)
1118 return -ENOMEM;
1119
7707e653
RC		 1120 drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1121 if (!drmmode_crtc) {
915a428e
DC		 1122 ret = -ENOENT;
1123 goto out_free;
1124 }
7707e653 1125 crtc = to_intel_crtc(drmmode_crtc);
02e792fb 1126
05394f39
CW		 1127 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1128 put_image_rec->bo_handle));
c8725226 1129 if (&new_bo->base == NULL) {
915a428e
DC		 1130 ret = -ENOENT;
1131 goto out_free;
1132 }
02e792fb 1133
a0e99e68 1134 drm_modeset_lock_all(dev);
02e792fb
DV		 1135 mutex_lock(&dev->struct_mutex);
1136
d9e86c0e 1137 if (new_bo->tiling_mode) {
3b25b31f 1138 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
d9e86c0e
CW		 1139 ret = -EINVAL;
1140 goto out_unlock;
1141 }
1142
ce453d81 1143 ret = intel_overlay_recover_from_interrupt(overlay);
b303cf95
CW		 1144 if (ret != 0)
1145 goto out_unlock;
03f77ea5 1146
02e792fb
DV		 1147 if (overlay->crtc != crtc) {
1148 struct drm_display_mode *mode = &crtc->base.mode;
ce453d81 1149 ret = intel_overlay_switch_off(overlay);
02e792fb
DV		 1150 if (ret != 0)
1151 goto out_unlock;
1152
1153 ret = check_overlay_possible_on_crtc(overlay, crtc);
1154 if (ret != 0)
1155 goto out_unlock;
1156
1157 overlay->crtc = crtc;
1158 crtc->overlay = overlay;
1159
e9e331a8
CW		 1160 /* line too wide, i.e. one-line-mode */
1161 if (mode->hdisplay > 1024 &&
1162 intel_panel_fitter_pipe(dev) == crtc->pipe) {
209c2a5e 1163 overlay->pfit_active = true;
02e792fb
DV		 1164 update_pfit_vscale_ratio(overlay);
1165 } else
209c2a5e 1166 overlay->pfit_active = false;
02e792fb
DV		 1167 }
1168
1169 ret = check_overlay_dst(overlay, put_image_rec);
1170 if (ret != 0)
1171 goto out_unlock;
1172
1173 if (overlay->pfit_active) {
1174 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1175 overlay->pfit_vscale_ratio);
02e792fb
DV		 1176 /* shifting right rounds downwards, so add 1 */
1177 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1178 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1179 } else {
1180 params->dst_y = put_image_rec->dst_y;
1181 params->dst_h = put_image_rec->dst_height;
1182 }
1183 params->dst_x = put_image_rec->dst_x;
1184 params->dst_w = put_image_rec->dst_width;
1185
1186 params->src_w = put_image_rec->src_width;
1187 params->src_h = put_image_rec->src_height;
1188 params->src_scan_w = put_image_rec->src_scan_width;
1189 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1190 if (params->src_scan_h > params->src_h ||
1191 params->src_scan_w > params->src_w) {
02e792fb
DV		 1192 ret = -EINVAL;
1193 goto out_unlock;
1194 }
1195
1196 ret = check_overlay_src(dev, put_image_rec, new_bo);
1197 if (ret != 0)
1198 goto out_unlock;
1199 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1200 params->stride_Y = put_image_rec->stride_Y;
1201 params->stride_UV = put_image_rec->stride_UV;
1202 params->offset_Y = put_image_rec->offset_Y;
1203 params->offset_U = put_image_rec->offset_U;
1204 params->offset_V = put_image_rec->offset_V;
1205
1206 /* Check scaling after src size to prevent a divide-by-zero. */
1207 ret = check_overlay_scaling(params);
1208 if (ret != 0)
1209 goto out_unlock;
1210
1211 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1212 if (ret != 0)
1213 goto out_unlock;
1214
1215 mutex_unlock(&dev->struct_mutex);
a0e99e68 1216 drm_modeset_unlock_all(dev);
02e792fb
DV		 1217
1218 kfree(params);
1219
1220 return 0;
1221
1222out_unlock:
1223 mutex_unlock(&dev->struct_mutex);
a0e99e68 1224 drm_modeset_unlock_all(dev);
05394f39 1225 drm_gem_object_unreference_unlocked(&new_bo->base);
915a428e 1226out_free:
02e792fb
DV		 1227 kfree(params);
1228
1229 return ret;
1230}
1231
1232static void update_reg_attrs(struct intel_overlay *overlay,
75020bc1 1233 struct overlay_registers __iomem *regs)
02e792fb 1234{
75020bc1
BW		 1235 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1236 &regs->OCLRC0);
1237 iowrite32(overlay->saturation, &regs->OCLRC1);
02e792fb
DV		 1238}
1239
1240static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1241{
1242 int i;
1243
1244 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1245 return false;
1246
1247 for (i = 0; i < 3; i++) {
722506f0 1248 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1249 return false;
1250 }
1251
1252 return true;
1253}
1254
1255static bool check_gamma5_errata(u32 gamma5)
1256{
1257 int i;
1258
1259 for (i = 0; i < 3; i++) {
1260 if (((gamma5 >> i*8) & 0xff) == 0x80)
1261 return false;
1262 }
1263
1264 return true;
1265}
1266
1267static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1268{
722506f0
CW		 1269 if (!check_gamma_bounds(0, attrs->gamma0) ||
1270 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1271 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1272 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1273 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1274 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1275 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1276 return -EINVAL;
722506f0 1277
02e792fb
DV		 1278 if (!check_gamma5_errata(attrs->gamma5))
1279 return -EINVAL;
722506f0 1280
02e792fb
DV		 1281 return 0;
1282}
1283
1284int intel_overlay_attrs(struct drm_device *dev, void *data,
0206e353 1285 struct drm_file *file_priv)
02e792fb
DV		 1286{
1287 struct drm_intel_overlay_attrs *attrs = data;
d5d45cc5 1288 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1289 struct intel_overlay *overlay;
75020bc1 1290 struct overlay_registers __iomem *regs;
02e792fb
DV		 1291 int ret;
1292
02e792fb
DV		 1293 overlay = dev_priv->overlay;
1294 if (!overlay) {
1295 DRM_DEBUG("userspace bug: no overlay\n");
1296 return -ENODEV;
1297 }
1298
a0e99e68 1299 drm_modeset_lock_all(dev);
02e792fb
DV		 1300 mutex_lock(&dev->struct_mutex);
1301
60fc332c 1302 ret = -EINVAL;
02e792fb 1303 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1304 attrs->color_key = overlay->color_key;
02e792fb 1305 attrs->brightness = overlay->brightness;
60fc332c 1306 attrs->contrast = overlay->contrast;
02e792fb
DV		 1307 attrs->saturation = overlay->saturation;
1308
a6c45cf0 1309 if (!IS_GEN2(dev)) {
02e792fb
DV		 1310 attrs->gamma0 = I915_READ(OGAMC0);
1311 attrs->gamma1 = I915_READ(OGAMC1);
1312 attrs->gamma2 = I915_READ(OGAMC2);
1313 attrs->gamma3 = I915_READ(OGAMC3);
1314 attrs->gamma4 = I915_READ(OGAMC4);
1315 attrs->gamma5 = I915_READ(OGAMC5);
1316 }
02e792fb 1317 } else {
60fc332c 1318 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1319 goto out_unlock;
60fc332c 1320 if (attrs->contrast > 255)
02e792fb 1321 goto out_unlock;
60fc332c 1322 if (attrs->saturation > 1023)
02e792fb 1323 goto out_unlock;
02e792fb 1324
60fc332c
CW		 1325 overlay->color_key = attrs->color_key;
1326 overlay->brightness = attrs->brightness;
1327 overlay->contrast = attrs->contrast;
1328 overlay->saturation = attrs->saturation;
02e792fb 1329
8d74f656 1330 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1331 if (!regs) {
1332 ret = -ENOMEM;
1333 goto out_unlock;
1334 }
1335
1336 update_reg_attrs(overlay, regs);
1337
9bb2ff73 1338 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1339
1340 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
a6c45cf0 1341 if (IS_GEN2(dev))
02e792fb 1342 goto out_unlock;
02e792fb
DV		 1343
1344 if (overlay->active) {
1345 ret = -EBUSY;
1346 goto out_unlock;
1347 }
1348
1349 ret = check_gamma(attrs);
60fc332c 1350 if (ret)
02e792fb
DV		 1351 goto out_unlock;
1352
1353 I915_WRITE(OGAMC0, attrs->gamma0);
1354 I915_WRITE(OGAMC1, attrs->gamma1);
1355 I915_WRITE(OGAMC2, attrs->gamma2);
1356 I915_WRITE(OGAMC3, attrs->gamma3);
1357 I915_WRITE(OGAMC4, attrs->gamma4);
1358 I915_WRITE(OGAMC5, attrs->gamma5);
1359 }
02e792fb 1360 }
ea9da4e4 1361 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
02e792fb 1362
60fc332c 1363 ret = 0;
02e792fb
DV		 1364out_unlock:
1365 mutex_unlock(&dev->struct_mutex);
a0e99e68 1366 drm_modeset_unlock_all(dev);
02e792fb
DV		 1367
1368 return ret;
1369}
1370
1371void intel_setup_overlay(struct drm_device *dev)
1372{
d5d45cc5 1373 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1374 struct intel_overlay *overlay;
05394f39 1375 struct drm_i915_gem_object *reg_bo;
75020bc1 1376 struct overlay_registers __iomem *regs;
02e792fb
DV		 1377 int ret;
1378
31578148 1379 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1380 return;
1381
b14c5679 1382 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
02e792fb
DV		 1383 if (!overlay)
1384 return;
79d24273
CW		 1385
1386 mutex_lock(&dev->struct_mutex);
1387 if (WARN_ON(dev_priv->overlay))
1388 goto out_free;
1389
02e792fb
DV		 1390 overlay->dev = dev;
1391
f63a484c
DV		 1392 reg_bo = NULL;
1393 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1394 reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE);
80405138
CW		 1395 if (reg_bo == NULL)
1396 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1397 if (reg_bo == NULL)
02e792fb 1398 goto out_free;
05394f39 1399 overlay->reg_bo = reg_bo;
02e792fb 1400
31578148 1401 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
00731155 1402 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
0206e353
AJ		 1403 if (ret) {
1404 DRM_ERROR("failed to attach phys overlay regs\n");
1405 goto out_free_bo;
1406 }
00731155 1407 overlay->flip_addr = reg_bo->phys_handle->busaddr;
31578148 1408 } else {
1ec9e26d 1409 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
02e792fb 1410 if (ret) {
0206e353
AJ		 1411 DRM_ERROR("failed to pin overlay register bo\n");
1412 goto out_free_bo;
1413 }
f343c5f6 1414 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo);
0ddc1289
CW		 1415
1416 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1417 if (ret) {
0206e353
AJ		 1418 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1419 goto out_unpin_bo;
1420 }
02e792fb
DV		 1421 }
1422
1423 /* init all values */
1424 overlay->color_key = 0x0101fe;
ea9da4e4 1425 overlay->color_key_enabled = true;
02e792fb
DV		 1426 overlay->brightness = -19;
1427 overlay->contrast = 75;
1428 overlay->saturation = 146;
1429
8d74f656 1430 regs = intel_overlay_map_regs(overlay);
02e792fb 1431 if (!regs)
79d24273 1432 goto out_unpin_bo;
02e792fb 1433
75020bc1 1434 memset_io(regs, 0, sizeof(struct overlay_registers));
02e792fb 1435 update_polyphase_filter(regs);
02e792fb
DV		 1436 update_reg_attrs(overlay, regs);
1437
9bb2ff73 1438 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1439
1440 dev_priv->overlay = overlay;
79d24273 1441 mutex_unlock(&dev->struct_mutex);
02e792fb
DV		 1442 DRM_INFO("initialized overlay support\n");
1443 return;
1444
0ddc1289 1445out_unpin_bo:
79d24273 1446 if (!OVERLAY_NEEDS_PHYSICAL(dev))
d7f46fc4 1447 i915_gem_object_ggtt_unpin(reg_bo);
02e792fb 1448out_free_bo:
05394f39 1449 drm_gem_object_unreference(&reg_bo->base);
02e792fb 1450out_free:
79d24273 1451 mutex_unlock(&dev->struct_mutex);
02e792fb
DV		 1452 kfree(overlay);
1453 return;
1454}
1455
1456void intel_cleanup_overlay(struct drm_device *dev)
1457{
d5d45cc5 1458 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1459
62cf4e6f
CW		 1460 if (!dev_priv->overlay)
1461 return;
02e792fb 1462
62cf4e6f
CW		 1463 /* The bo's should be free'd by the generic code already.
1464 * Furthermore modesetting teardown happens beforehand so the
1465 * hardware should be off already */
77589f56 1466 WARN_ON(dev_priv->overlay->active);
62cf4e6f
CW		 1467
1468 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1469 kfree(dev_priv->overlay);
02e792fb 1470}
6ef3d427
CW		 1471
1472struct intel_overlay_error_state {
1473 struct overlay_registers regs;
1474 unsigned long base;
1475 u32 dovsta;
1476 u32 isr;
1477};
1478
75020bc1 1479static struct overlay_registers __iomem *
c48c43e4 1480intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
3bd3c932 1481{
d5d45cc5 1482 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
75020bc1 1483 struct overlay_registers __iomem *regs;
3bd3c932
CW		 1484
1485 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
75020bc1
BW		 1486 /* Cast to make sparse happy, but it's wc memory anyway, so
1487 * equivalent to the wc io mapping on X86. */
1488 regs = (struct overlay_registers __iomem *)
00731155 1489 overlay->reg_bo->phys_handle->vaddr;
3bd3c932 1490 else
5d4545ae 1491 regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
f343c5f6 1492 i915_gem_obj_ggtt_offset(overlay->reg_bo));
3bd3c932
CW		 1493
1494 return regs;
1495}
1496
1497static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
75020bc1 1498 struct overlay_registers __iomem *regs)
3bd3c932
CW		 1499{
1500 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
c48c43e4 1501 io_mapping_unmap_atomic(regs);
3bd3c932
CW		 1502}
1503
1504
6ef3d427
CW		 1505struct intel_overlay_error_state *
1506intel_overlay_capture_error_state(struct drm_device *dev)
1507{
d5d45cc5 1508 struct drm_i915_private *dev_priv = dev->dev_private;
6ef3d427
CW		 1509 struct intel_overlay *overlay = dev_priv->overlay;
1510 struct intel_overlay_error_state *error;
1511 struct overlay_registers __iomem *regs;
1512
1513 if (!overlay || !overlay->active)
1514 return NULL;
1515
1516 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1517 if (error == NULL)
1518 return NULL;
1519
1520 error->dovsta = I915_READ(DOVSTA);
1521 error->isr = I915_READ(ISR);
31578148 1522 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
00731155 1523 error->base = (__force long)overlay->reg_bo->phys_handle->vaddr;
31578148 1524 else
f343c5f6 1525 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo);
6ef3d427
CW		 1526
1527 regs = intel_overlay_map_regs_atomic(overlay);
1528 if (!regs)
1529 goto err;
1530
1531 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
c48c43e4 1532 intel_overlay_unmap_regs_atomic(overlay, regs);
6ef3d427
CW		 1533
1534 return error;
1535
1536err:
1537 kfree(error);
1538 return NULL;
1539}
1540
1541void
edc3d884
MK		 1542intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1543 struct intel_overlay_error_state *error)
6ef3d427 1544{
edc3d884
MK		 1545 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1546 error->dovsta, error->isr);
1547 i915_error_printf(m, " Register file at 0x%08lx:\n",
1548 error->base);
6ef3d427 1549
edc3d884 1550#define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)
6ef3d427
CW		 1551 P(OBUF_0Y);
1552 P(OBUF_1Y);
1553 P(OBUF_0U);
1554 P(OBUF_0V);
1555 P(OBUF_1U);
1556 P(OBUF_1V);
1557 P(OSTRIDE);
1558 P(YRGB_VPH);
1559 P(UV_VPH);
1560 P(HORZ_PH);
1561 P(INIT_PHS);
1562 P(DWINPOS);
1563 P(DWINSZ);
1564 P(SWIDTH);
1565 P(SWIDTHSW);
1566 P(SHEIGHT);
1567 P(YRGBSCALE);
1568 P(UVSCALE);
1569 P(OCLRC0);
1570 P(OCLRC1);
1571 P(DCLRKV);
1572 P(DCLRKM);
1573 P(SCLRKVH);
1574 P(SCLRKVL);
1575 P(SCLRKEN);
1576 P(OCONFIG);
1577 P(OCMD);
1578 P(OSTART_0Y);
1579 P(OSTART_1Y);
1580 P(OSTART_0U);
1581 P(OSTART_0V);
1582 P(OSTART_1U);
1583 P(OSTART_1V);
1584 P(OTILEOFF_0Y);
1585 P(OTILEOFF_1Y);
1586 P(OTILEOFF_0U);
1587 P(OTILEOFF_0V);
1588 P(OTILEOFF_1U);
1589 P(OTILEOFF_1V);
1590 P(FASTHSCALE);
1591 P(UVSCALEV);
1592#undef P
1593}
Linux kernel - Deliverables
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