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drm/i915/overlay: Remove duplicated definition of OFC_UPDATE
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
e167976e
AM		 28
29#include <linux/seq_file.h>
02e792fb
DV		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 70#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 71#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
8d74f656
CW		 173static struct overlay_registers *
174intel_overlay_map_regs_atomic(struct intel_overlay *overlay,
175 int slot)
02e792fb
DV		 176{
177 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
178 struct overlay_registers *regs;
179
180 /* no recursive mappings */
181 BUG_ON(overlay->virt_addr);
182
31578148
CW		 183 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) {
184 regs = overlay->reg_bo->phys_obj->handle->vaddr;
185 } else {
02e792fb 186 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
fca3ec01 187 overlay->reg_bo->gtt_offset,
8d74f656 188 slot);
02e792fb
DV		 189
190 if (!regs) {
191 DRM_ERROR("failed to map overlay regs in GTT\n");
192 return NULL;
193 }
31578148 194 }
02e792fb
DV		 195
196 return overlay->virt_addr = regs;
197}
198
8d74f656
CW		 199static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
200 int slot)
02e792fb 201{
31578148 202 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
8d74f656
CW		 203 io_mapping_unmap_atomic(overlay->virt_addr, slot);
204
205 overlay->virt_addr = NULL;
206
207 return;
208}
209
210static struct overlay_registers *
211intel_overlay_map_regs(struct intel_overlay *overlay)
212{
213 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
214 struct overlay_registers *regs;
215
216 /* no recursive mappings */
217 BUG_ON(overlay->virt_addr);
218
219 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) {
220 regs = overlay->reg_bo->phys_obj->handle->vaddr;
221 } else {
222 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
223 overlay->reg_bo->gtt_offset);
224
225 if (!regs) {
226 DRM_ERROR("failed to map overlay regs in GTT\n");
227 return NULL;
228 }
229 }
230
231 return overlay->virt_addr = regs;
232}
233
234static void intel_overlay_unmap_regs(struct intel_overlay *overlay)
235{
236 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
237 io_mapping_unmap(overlay->virt_addr);
02e792fb
DV		 238
239 overlay->virt_addr = NULL;
240
02e792fb
DV		 241 return;
242}
243
244/* overlay needs to be disable in OCMD reg */
245static int intel_overlay_on(struct intel_overlay *overlay)
246{
247 struct drm_device *dev = overlay->dev;
02e792fb 248 int ret;
852835f3 249 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb
DV		 250
251 BUG_ON(overlay->active);
252
03f77ea5
DV		 253 overlay->active = 1;
254 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
255
4f8a567c 256 BEGIN_LP_RING(4);
02e792fb
DV		 257 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
258 OUT_RING(overlay->flip_addr | OFC_UPDATE);
259 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
260 OUT_RING(MI_NOOP);
261 ADVANCE_LP_RING();
262
852835f3 263 overlay->last_flip_req =
8a1a49f9 264 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 265 if (overlay->last_flip_req == 0)
266 return -ENOMEM;
02e792fb 267
852835f3 268 ret = i915_do_wait_request(dev,
722506f0
CW		 269 overlay->last_flip_req, true,
270 &dev_priv->render_ring);
03f77ea5
DV		 271 if (ret != 0)
272 return ret;
02e792fb 273
03f77ea5
DV		 274 overlay->hw_wedged = 0;
275 overlay->last_flip_req = 0;
02e792fb
DV		 276 return 0;
277}
278
279/* overlay needs to be enabled in OCMD reg */
280static void intel_overlay_continue(struct intel_overlay *overlay,
722506f0 281 bool load_polyphase_filter)
02e792fb
DV		 282{
283 struct drm_device *dev = overlay->dev;
284 drm_i915_private_t *dev_priv = dev->dev_private;
285 u32 flip_addr = overlay->flip_addr;
286 u32 tmp;
02e792fb
DV		 287
288 BUG_ON(!overlay->active);
289
290 if (load_polyphase_filter)
291 flip_addr |= OFC_UPDATE;
292
293 /* check for underruns */
294 tmp = I915_READ(DOVSTA);
295 if (tmp & (1 << 17))
296 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
297
4f8a567c 298 BEGIN_LP_RING(2);
02e792fb
DV		 299 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
300 OUT_RING(flip_addr);
5a5a0c64
DV		 301 ADVANCE_LP_RING();
302
852835f3 303 overlay->last_flip_req =
8a1a49f9 304 i915_add_request(dev, NULL, &dev_priv->render_ring);
5a5a0c64
DV		 305}
306
307static int intel_overlay_wait_flip(struct intel_overlay *overlay)
308{
309 struct drm_device *dev = overlay->dev;
722506f0 310 drm_i915_private_t *dev_priv = dev->dev_private;
5a5a0c64
DV		 311 int ret;
312 u32 tmp;
5a5a0c64
DV		 313
314 if (overlay->last_flip_req != 0) {
722506f0
CW		 315 ret = i915_do_wait_request(dev,
316 overlay->last_flip_req, true,
317 &dev_priv->render_ring);
5c5a4359
DV		 318 if (ret == 0) {
319 overlay->last_flip_req = 0;
5a5a0c64 320
5c5a4359 321 tmp = I915_READ(ISR);
5a5a0c64 322
5c5a4359
DV		 323 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
324 return 0;
325 }
5a5a0c64
DV		 326 }
327
328 /* synchronous slowpath */
03f77ea5
DV		 329 overlay->hw_wedged = RELEASE_OLD_VID;
330
5a5a0c64 331 BEGIN_LP_RING(2);
722506f0
CW		 332 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
333 OUT_RING(MI_NOOP);
334 ADVANCE_LP_RING();
02e792fb 335
852835f3 336 overlay->last_flip_req =
8a1a49f9 337 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 338 if (overlay->last_flip_req == 0)
339 return -ENOMEM;
02e792fb 340
722506f0
CW		 341 ret = i915_do_wait_request(dev,
342 overlay->last_flip_req, true,
343 &dev_priv->render_ring);
03f77ea5
DV		 344 if (ret != 0)
345 return ret;
346
347 overlay->hw_wedged = 0;
348 overlay->last_flip_req = 0;
349 return 0;
02e792fb
DV		 350}
351
352/* overlay needs to be disabled in OCMD reg */
353static int intel_overlay_off(struct intel_overlay *overlay)
354{
355 u32 flip_addr = overlay->flip_addr;
356 struct drm_device *dev = overlay->dev;
852835f3 357 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 358 int ret;
02e792fb
DV		 359
360 BUG_ON(!overlay->active);
361
362 /* According to intel docs the overlay hw may hang (when switching
363 * off) without loading the filter coeffs. It is however unclear whether
364 * this applies to the disabling of the overlay or to the switching off
365 * of the hw. Do it in both cases */
366 flip_addr |= OFC_UPDATE;
367
368 /* wait for overlay to go idle */
03f77ea5
DV		 369 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
370
4f8a567c 371 BEGIN_LP_RING(4);
02e792fb
DV		 372 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
373 OUT_RING(flip_addr);
722506f0
CW		 374 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
375 OUT_RING(MI_NOOP);
376 ADVANCE_LP_RING();
02e792fb 377
852835f3 378 overlay->last_flip_req =
8a1a49f9 379 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 380 if (overlay->last_flip_req == 0)
381 return -ENOMEM;
382
722506f0
CW		 383 ret = i915_do_wait_request(dev,
384 overlay->last_flip_req, true,
385 &dev_priv->render_ring);
03f77ea5 386 if (ret != 0)
02e792fb 387 return ret;
02e792fb
DV		 388
389 /* turn overlay off */
03f77ea5
DV		 390 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
391
4f8a567c 392 BEGIN_LP_RING(4);
722506f0 393 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
02e792fb 394 OUT_RING(flip_addr);
722506f0
CW		 395 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
396 OUT_RING(MI_NOOP);
02e792fb
DV		 397 ADVANCE_LP_RING();
398
852835f3 399 overlay->last_flip_req =
8a1a49f9 400 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 401 if (overlay->last_flip_req == 0)
402 return -ENOMEM;
403
722506f0
CW		 404 ret = i915_do_wait_request(dev,
405 overlay->last_flip_req, true,
406 &dev_priv->render_ring);
03f77ea5 407 if (ret != 0)
02e792fb 408 return ret;
02e792fb 409
03f77ea5
DV		 410 overlay->hw_wedged = 0;
411 overlay->last_flip_req = 0;
02e792fb
DV		 412 return ret;
413}
414
12ca45fe
DV		 415static void intel_overlay_off_tail(struct intel_overlay *overlay)
416{
417 struct drm_gem_object *obj;
418
419 /* never have the overlay hw on without showing a frame */
420 BUG_ON(!overlay->vid_bo);
a8089e84 421 obj = &overlay->vid_bo->base;
12ca45fe
DV		 422
423 i915_gem_object_unpin(obj);
424 drm_gem_object_unreference(obj);
425 overlay->vid_bo = NULL;
426
427 overlay->crtc->overlay = NULL;
428 overlay->crtc = NULL;
429 overlay->active = 0;
430}
431
03f77ea5
DV		 432/* recover from an interruption due to a signal
433 * We have to be careful not to repeat work forever an make forward progess. */
434int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
722506f0 435 bool interruptible)
03f77ea5
DV		 436{
437 struct drm_device *dev = overlay->dev;
03f77ea5 438 struct drm_gem_object *obj;
852835f3 439 drm_i915_private_t *dev_priv = dev->dev_private;
03f77ea5
DV		 440 u32 flip_addr;
441 int ret;
03f77ea5
DV		 442
443 if (overlay->hw_wedged == HW_WEDGED)
444 return -EIO;
445
446 if (overlay->last_flip_req == 0) {
852835f3 447 overlay->last_flip_req =
8a1a49f9 448 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 449 if (overlay->last_flip_req == 0)
450 return -ENOMEM;
451 }
452
852835f3 453 ret = i915_do_wait_request(dev, overlay->last_flip_req,
722506f0 454 interruptible, &dev_priv->render_ring);
03f77ea5
DV		 455 if (ret != 0)
456 return ret;
457
458 switch (overlay->hw_wedged) {
722506f0
CW		 459 case RELEASE_OLD_VID:
460 obj = &overlay->old_vid_bo->base;
461 i915_gem_object_unpin(obj);
462 drm_gem_object_unreference(obj);
463 overlay->old_vid_bo = NULL;
464 break;
465 case SWITCH_OFF_STAGE_1:
466 flip_addr = overlay->flip_addr;
467 flip_addr |= OFC_UPDATE;
03f77ea5 468
722506f0
CW		 469 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
470
471 BEGIN_LP_RING(4);
472 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
473 OUT_RING(flip_addr);
474 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
475 OUT_RING(MI_NOOP);
476 ADVANCE_LP_RING();
477
478 overlay->last_flip_req =
479 i915_add_request(dev, NULL,
480 &dev_priv->render_ring);
481 if (overlay->last_flip_req == 0)
482 return -ENOMEM;
483
484 ret = i915_do_wait_request(dev, overlay->last_flip_req,
485 interruptible,
486 &dev_priv->render_ring);
487 if (ret != 0)
488 return ret;
489
490 case SWITCH_OFF_STAGE_2:
491 intel_overlay_off_tail(overlay);
492 break;
493 default:
494 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
03f77ea5
DV		 495 }
496
497 overlay->hw_wedged = 0;
498 overlay->last_flip_req = 0;
499 return 0;
500}
501
5a5a0c64
DV		 502/* Wait for pending overlay flip and release old frame.
503 * Needs to be called before the overlay register are changed
8d74f656
CW		 504 * via intel_overlay_(un)map_regs
505 */
02e792fb
DV		 506static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
507{
508 int ret;
509 struct drm_gem_object *obj;
510
03f77ea5
DV		 511 /* only wait if there is actually an old frame to release to
512 * guarantee forward progress */
513 if (!overlay->old_vid_bo)
514 return 0;
515
02e792fb
DV		 516 ret = intel_overlay_wait_flip(overlay);
517 if (ret != 0)
518 return ret;
519
a8089e84 520 obj = &overlay->old_vid_bo->base;
02e792fb
DV		 521 i915_gem_object_unpin(obj);
522 drm_gem_object_unreference(obj);
523 overlay->old_vid_bo = NULL;
524
525 return 0;
526}
527
528struct put_image_params {
529 int format;
530 short dst_x;
531 short dst_y;
532 short dst_w;
533 short dst_h;
534 short src_w;
535 short src_scan_h;
536 short src_scan_w;
537 short src_h;
538 short stride_Y;
539 short stride_UV;
540 int offset_Y;
541 int offset_U;
542 int offset_V;
543};
544
545static int packed_depth_bytes(u32 format)
546{
547 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 548 case I915_OVERLAY_YUV422:
549 return 4;
550 case I915_OVERLAY_YUV411:
551 /* return 6; not implemented */
552 default:
553 return -EINVAL;
02e792fb
DV		 554 }
555}
556
557static int packed_width_bytes(u32 format, short width)
558{
559 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 560 case I915_OVERLAY_YUV422:
561 return width << 1;
562 default:
563 return -EINVAL;
02e792fb
DV		 564 }
565}
566
567static int uv_hsubsampling(u32 format)
568{
569 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 570 case I915_OVERLAY_YUV422:
571 case I915_OVERLAY_YUV420:
572 return 2;
573 case I915_OVERLAY_YUV411:
574 case I915_OVERLAY_YUV410:
575 return 4;
576 default:
577 return -EINVAL;
02e792fb
DV		 578 }
579}
580
581static int uv_vsubsampling(u32 format)
582{
583 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 584 case I915_OVERLAY_YUV420:
585 case I915_OVERLAY_YUV410:
586 return 2;
587 case I915_OVERLAY_YUV422:
588 case I915_OVERLAY_YUV411:
589 return 1;
590 default:
591 return -EINVAL;
02e792fb
DV		 592 }
593}
594
595static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
596{
597 u32 mask, shift, ret;
598 if (IS_I9XX(dev)) {
599 mask = 0x3f;
600 shift = 6;
601 } else {
602 mask = 0x1f;
603 shift = 5;
604 }
605 ret = ((offset + width + mask) >> shift) - (offset >> shift);
606 if (IS_I9XX(dev))
607 ret <<= 1;
608 ret -=1;
609 return ret << 2;
610}
611
612static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
613 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
614 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
615 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
616 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
617 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
618 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
619 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
620 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
621 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
622 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
623 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
624 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
625 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
626 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
627 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
628 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 629 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
630};
631
02e792fb
DV		 632static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
633 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
634 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
635 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
636 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
637 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
638 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
639 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
640 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 641 0x3000, 0x0800, 0x3000
642};
02e792fb
DV		 643
644static void update_polyphase_filter(struct overlay_registers *regs)
645{
646 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
647 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
648}
649
650static bool update_scaling_factors(struct intel_overlay *overlay,
651 struct overlay_registers *regs,
652 struct put_image_params *params)
653{
654 /* fixed point with a 12 bit shift */
655 u32 xscale, yscale, xscale_UV, yscale_UV;
656#define FP_SHIFT 12
657#define FRACT_MASK 0xfff
658 bool scale_changed = false;
659 int uv_hscale = uv_hsubsampling(params->format);
660 int uv_vscale = uv_vsubsampling(params->format);
661
662 if (params->dst_w > 1)
663 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
664 /(params->dst_w);
665 else
666 xscale = 1 << FP_SHIFT;
667
668 if (params->dst_h > 1)
669 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
670 /(params->dst_h);
671 else
672 yscale = 1 << FP_SHIFT;
673
674 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 675 xscale_UV = xscale/uv_hscale;
676 yscale_UV = yscale/uv_vscale;
677 /* make the Y scale to UV scale ratio an exact multiply */
678 xscale = xscale_UV * uv_hscale;
679 yscale = yscale_UV * uv_vscale;
02e792fb 680 /*} else {
722506f0
CW		 681 xscale_UV = 0;
682 yscale_UV = 0;
683 }*/
02e792fb
DV		 684
685 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
686 scale_changed = true;
687 overlay->old_xscale = xscale;
688 overlay->old_yscale = yscale;
689
722506f0
CW		 690 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
691 ((xscale >> FP_SHIFT) << 16) |
692 ((xscale & FRACT_MASK) << 3));
693
694 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
695 ((xscale_UV >> FP_SHIFT) << 16) |
696 ((xscale_UV & FRACT_MASK) << 3));
697
698 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
699 ((yscale_UV >> FP_SHIFT) << 0)));
02e792fb
DV		 700
701 if (scale_changed)
702 update_polyphase_filter(regs);
703
704 return scale_changed;
705}
706
707static void update_colorkey(struct intel_overlay *overlay,
708 struct overlay_registers *regs)
709{
710 u32 key = overlay->color_key;
6ba3ddd9 711
02e792fb 712 switch (overlay->crtc->base.fb->bits_per_pixel) {
722506f0
CW		 713 case 8:
714 regs->DCLRKV = 0;
715 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
6ba3ddd9
CW		 716 break;
717
722506f0
CW		 718 case 16:
719 if (overlay->crtc->base.fb->depth == 15) {
720 regs->DCLRKV = RGB15_TO_COLORKEY(key);
721 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
722 } else {
723 regs->DCLRKV = RGB16_TO_COLORKEY(key);
724 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
725 }
6ba3ddd9
CW		 726 break;
727
722506f0
CW		 728 case 24:
729 case 32:
730 regs->DCLRKV = key;
731 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
6ba3ddd9 732 break;
02e792fb
DV		 733 }
734}
735
736static u32 overlay_cmd_reg(struct put_image_params *params)
737{
738 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
739
740 if (params->format & I915_OVERLAY_YUV_PLANAR) {
741 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 742 case I915_OVERLAY_YUV422:
743 cmd |= OCMD_YUV_422_PLANAR;
744 break;
745 case I915_OVERLAY_YUV420:
746 cmd |= OCMD_YUV_420_PLANAR;
747 break;
748 case I915_OVERLAY_YUV411:
749 case I915_OVERLAY_YUV410:
750 cmd |= OCMD_YUV_410_PLANAR;
751 break;
02e792fb
DV		 752 }
753 } else { /* YUV packed */
754 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 755 case I915_OVERLAY_YUV422:
756 cmd |= OCMD_YUV_422_PACKED;
757 break;
758 case I915_OVERLAY_YUV411:
759 cmd |= OCMD_YUV_411_PACKED;
760 break;
02e792fb
DV		 761 }
762
763 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 764 case I915_OVERLAY_NO_SWAP:
765 break;
766 case I915_OVERLAY_UV_SWAP:
767 cmd |= OCMD_UV_SWAP;
768 break;
769 case I915_OVERLAY_Y_SWAP:
770 cmd |= OCMD_Y_SWAP;
771 break;
772 case I915_OVERLAY_Y_AND_UV_SWAP:
773 cmd |= OCMD_Y_AND_UV_SWAP;
774 break;
02e792fb
DV		 775 }
776 }
777
778 return cmd;
779}
780
781int intel_overlay_do_put_image(struct intel_overlay *overlay,
782 struct drm_gem_object *new_bo,
783 struct put_image_params *params)
784{
785 int ret, tmp_width;
786 struct overlay_registers *regs;
787 bool scale_changed = false;
23010e43 788 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 789 struct drm_device *dev = overlay->dev;
790
791 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
792 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
793 BUG_ON(!overlay);
794
02e792fb
DV		 795 ret = intel_overlay_release_old_vid(overlay);
796 if (ret != 0)
797 return ret;
798
799 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
800 if (ret != 0)
801 return ret;
802
803 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
804 if (ret != 0)
805 goto out_unpin;
806
807 if (!overlay->active) {
8d74f656 808 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 809 if (!regs) {
810 ret = -ENOMEM;
811 goto out_unpin;
812 }
813 regs->OCONFIG = OCONF_CC_OUT_8BIT;
814 if (IS_I965GM(overlay->dev))
815 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
816 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
817 OCONF_PIPE_A : OCONF_PIPE_B;
8d74f656 818 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 819
820 ret = intel_overlay_on(overlay);
821 if (ret != 0)
822 goto out_unpin;
823 }
824
8d74f656 825 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 826 if (!regs) {
827 ret = -ENOMEM;
828 goto out_unpin;
829 }
830
831 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
832 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
833
834 if (params->format & I915_OVERLAY_YUV_PACKED)
835 tmp_width = packed_width_bytes(params->format, params->src_w);
836 else
837 tmp_width = params->src_w;
838
839 regs->SWIDTH = params->src_w;
840 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
722506f0 841 params->offset_Y, tmp_width);
02e792fb
DV		 842 regs->SHEIGHT = params->src_h;
843 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
844 regs->OSTRIDE = params->stride_Y;
845
846 if (params->format & I915_OVERLAY_YUV_PLANAR) {
847 int uv_hscale = uv_hsubsampling(params->format);
848 int uv_vscale = uv_vsubsampling(params->format);
849 u32 tmp_U, tmp_V;
850 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
851 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 852 params->src_w/uv_hscale);
02e792fb 853 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 854 params->src_w/uv_hscale);
02e792fb
DV		 855 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
856 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
857 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
858 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
859 regs->OSTRIDE |= params->stride_UV << 16;
860 }
861
862 scale_changed = update_scaling_factors(overlay, regs, params);
863
864 update_colorkey(overlay, regs);
865
866 regs->OCMD = overlay_cmd_reg(params);
867
8d74f656 868 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 869
870 intel_overlay_continue(overlay, scale_changed);
871
872 overlay->old_vid_bo = overlay->vid_bo;
23010e43 873 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 874
875 return 0;
876
877out_unpin:
878 i915_gem_object_unpin(new_bo);
879 return ret;
880}
881
882int intel_overlay_switch_off(struct intel_overlay *overlay)
883{
884 int ret;
885 struct overlay_registers *regs;
02e792fb
DV		 886 struct drm_device *dev = overlay->dev;
887
888 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
889 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
890
9bedb974
DV		 891 if (overlay->hw_wedged) {
892 ret = intel_overlay_recover_from_interrupt(overlay, 1);
893 if (ret != 0)
894 return ret;
895 }
896
02e792fb
DV		 897 if (!overlay->active)
898 return 0;
899
02e792fb
DV		 900 ret = intel_overlay_release_old_vid(overlay);
901 if (ret != 0)
902 return ret;
903
8d74f656 904 regs = intel_overlay_map_regs(overlay);
02e792fb 905 regs->OCMD = 0;
8d74f656 906 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 907
908 ret = intel_overlay_off(overlay);
03f77ea5
DV		 909 if (ret != 0)
910 return ret;
911
12ca45fe 912 intel_overlay_off_tail(overlay);
02e792fb
DV		 913
914 return 0;
915}
916
917static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
918 struct intel_crtc *crtc)
919{
722506f0 920 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
02e792fb
DV		 921 u32 pipeconf;
922 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
923
924 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
925 return -EINVAL;
926
927 pipeconf = I915_READ(pipeconf_reg);
928
929 /* can't use the overlay with double wide pipe */
930 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
931 return -EINVAL;
932
933 return 0;
934}
935
936static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
937{
938 struct drm_device *dev = overlay->dev;
722506f0 939 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb
DV		 940 u32 ratio;
941 u32 pfit_control = I915_READ(PFIT_CONTROL);
942
943 /* XXX: This is not the same logic as in the xorg driver, but more in
944 * line with the intel documentation for the i965 */
945 if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
946 ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
947 } else { /* on i965 use the PGM reg to read out the autoscaler values */
948 ratio = I915_READ(PFIT_PGM_RATIOS);
949 if (IS_I965G(dev))
950 ratio >>= PFIT_VERT_SCALE_SHIFT_965;
951 else
952 ratio >>= PFIT_VERT_SCALE_SHIFT;
953 }
954
955 overlay->pfit_vscale_ratio = ratio;
956}
957
958static int check_overlay_dst(struct intel_overlay *overlay,
959 struct drm_intel_overlay_put_image *rec)
960{
961 struct drm_display_mode *mode = &overlay->crtc->base.mode;
962
722506f0
CW		 963 if (rec->dst_x < mode->crtc_hdisplay &&
964 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
965 rec->dst_y < mode->crtc_vdisplay &&
966 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
02e792fb
DV		 967 return 0;
968 else
969 return -EINVAL;
970}
971
972static int check_overlay_scaling(struct put_image_params *rec)
973{
974 u32 tmp;
975
976 /* downscaling limit is 8.0 */
977 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
978 if (tmp > 7)
979 return -EINVAL;
980 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
981 if (tmp > 7)
982 return -EINVAL;
983
984 return 0;
985}
986
987static int check_overlay_src(struct drm_device *dev,
988 struct drm_intel_overlay_put_image *rec,
989 struct drm_gem_object *new_bo)
990{
991 u32 stride_mask;
992 int depth;
993 int uv_hscale = uv_hsubsampling(rec->flags);
994 int uv_vscale = uv_vsubsampling(rec->flags);
995 size_t tmp;
996
997 /* check src dimensions */
998 if (IS_845G(dev) || IS_I830(dev)) {
722506f0
CW		 999 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
1000 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 1001 return -EINVAL;
1002 } else {
722506f0
CW		 1003 if (rec->src_height > IMAGE_MAX_HEIGHT ||
1004 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 1005 return -EINVAL;
1006 }
1007 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0
CW		 1008 if (rec->src_height < N_VERT_Y_TAPS*4 ||
1009 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 1010 return -EINVAL;
1011
a1efd14a 1012 /* check alignment constraints */
02e792fb 1013 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1014 case I915_OVERLAY_RGB:
1015 /* not implemented */
1016 return -EINVAL;
1017 case I915_OVERLAY_YUV_PACKED:
1018 depth = packed_depth_bytes(rec->flags);
1019 if (uv_vscale != 1)
02e792fb 1020 return -EINVAL;
722506f0
CW		 1021 if (depth < 0)
1022 return depth;
1023 /* ignore UV planes */
1024 rec->stride_UV = 0;
1025 rec->offset_U = 0;
1026 rec->offset_V = 0;
1027 /* check pixel alignment */
1028 if (rec->offset_Y % depth)
1029 return -EINVAL;
1030 break;
1031 case I915_OVERLAY_YUV_PLANAR:
1032 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 1033 return -EINVAL;
722506f0
CW		 1034 /* no offset restrictions for planar formats */
1035 break;
1036 default:
1037 return -EINVAL;
02e792fb
DV		 1038 }
1039
1040 if (rec->src_width % uv_hscale)
1041 return -EINVAL;
1042
1043 /* stride checking */
a1efd14a
CW		 1044 if (IS_I830(dev) || IS_845G(dev))
1045 stride_mask = 255;
1046 else
1047 stride_mask = 63;
02e792fb
DV		 1048
1049 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1050 return -EINVAL;
1051 if (IS_I965G(dev) && rec->stride_Y < 512)
1052 return -EINVAL;
1053
1054 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1055 4 : 8;
1056 if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
1057 return -EINVAL;
1058
1059 /* check buffer dimensions */
1060 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1061 case I915_OVERLAY_RGB:
1062 case I915_OVERLAY_YUV_PACKED:
1063 /* always 4 Y values per depth pixels */
1064 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1065 return -EINVAL;
1066
1067 tmp = rec->stride_Y*rec->src_height;
1068 if (rec->offset_Y + tmp > new_bo->size)
1069 return -EINVAL;
1070 break;
1071
1072 case I915_OVERLAY_YUV_PLANAR:
1073 if (rec->src_width > rec->stride_Y)
1074 return -EINVAL;
1075 if (rec->src_width/uv_hscale > rec->stride_UV)
1076 return -EINVAL;
1077
1078 tmp = rec->stride_Y*rec->src_height;
1079 if (rec->offset_Y + tmp > new_bo->size)
1080 return -EINVAL;
1081 tmp = rec->stride_UV*rec->src_height;
1082 tmp /= uv_vscale;
1083 if (rec->offset_U + tmp > new_bo->size ||
1084 rec->offset_V + tmp > new_bo->size)
1085 return -EINVAL;
1086 break;
02e792fb
DV		 1087 }
1088
1089 return 0;
1090}
1091
1092int intel_overlay_put_image(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv)
1094{
1095 struct drm_intel_overlay_put_image *put_image_rec = data;
1096 drm_i915_private_t *dev_priv = dev->dev_private;
1097 struct intel_overlay *overlay;
1098 struct drm_mode_object *drmmode_obj;
1099 struct intel_crtc *crtc;
1100 struct drm_gem_object *new_bo;
1101 struct put_image_params *params;
1102 int ret;
1103
1104 if (!dev_priv) {
1105 DRM_ERROR("called with no initialization\n");
1106 return -EINVAL;
1107 }
1108
1109 overlay = dev_priv->overlay;
1110 if (!overlay) {
1111 DRM_DEBUG("userspace bug: no overlay\n");
1112 return -ENODEV;
1113 }
1114
1115 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1116 mutex_lock(&dev->mode_config.mutex);
1117 mutex_lock(&dev->struct_mutex);
1118
1119 ret = intel_overlay_switch_off(overlay);
1120
1121 mutex_unlock(&dev->struct_mutex);
1122 mutex_unlock(&dev->mode_config.mutex);
1123
1124 return ret;
1125 }
1126
1127 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1128 if (!params)
1129 return -ENOMEM;
1130
1131 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
722506f0 1132 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1133 if (!drmmode_obj) {
1134 ret = -ENOENT;
1135 goto out_free;
1136 }
02e792fb
DV		 1137 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1138
1139 new_bo = drm_gem_object_lookup(dev, file_priv,
722506f0 1140 put_image_rec->bo_handle);
915a428e
DC		 1141 if (!new_bo) {
1142 ret = -ENOENT;
1143 goto out_free;
1144 }
02e792fb
DV		 1145
1146 mutex_lock(&dev->mode_config.mutex);
1147 mutex_lock(&dev->struct_mutex);
1148
03f77ea5
DV		 1149 if (overlay->hw_wedged) {
1150 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1151 if (ret != 0)
1152 goto out_unlock;
1153 }
1154
02e792fb
DV		 1155 if (overlay->crtc != crtc) {
1156 struct drm_display_mode *mode = &crtc->base.mode;
1157 ret = intel_overlay_switch_off(overlay);
1158 if (ret != 0)
1159 goto out_unlock;
1160
1161 ret = check_overlay_possible_on_crtc(overlay, crtc);
1162 if (ret != 0)
1163 goto out_unlock;
1164
1165 overlay->crtc = crtc;
1166 crtc->overlay = overlay;
1167
1168 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1169 /* and line to wide, i.e. one-line-mode */
1170 && mode->hdisplay > 1024) {
1171 overlay->pfit_active = 1;
1172 update_pfit_vscale_ratio(overlay);
1173 } else
1174 overlay->pfit_active = 0;
1175 }
1176
1177 ret = check_overlay_dst(overlay, put_image_rec);
1178 if (ret != 0)
1179 goto out_unlock;
1180
1181 if (overlay->pfit_active) {
1182 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1183 overlay->pfit_vscale_ratio);
02e792fb
DV		 1184 /* shifting right rounds downwards, so add 1 */
1185 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1186 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1187 } else {
1188 params->dst_y = put_image_rec->dst_y;
1189 params->dst_h = put_image_rec->dst_height;
1190 }
1191 params->dst_x = put_image_rec->dst_x;
1192 params->dst_w = put_image_rec->dst_width;
1193
1194 params->src_w = put_image_rec->src_width;
1195 params->src_h = put_image_rec->src_height;
1196 params->src_scan_w = put_image_rec->src_scan_width;
1197 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1198 if (params->src_scan_h > params->src_h ||
1199 params->src_scan_w > params->src_w) {
02e792fb
DV		 1200 ret = -EINVAL;
1201 goto out_unlock;
1202 }
1203
1204 ret = check_overlay_src(dev, put_image_rec, new_bo);
1205 if (ret != 0)
1206 goto out_unlock;
1207 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1208 params->stride_Y = put_image_rec->stride_Y;
1209 params->stride_UV = put_image_rec->stride_UV;
1210 params->offset_Y = put_image_rec->offset_Y;
1211 params->offset_U = put_image_rec->offset_U;
1212 params->offset_V = put_image_rec->offset_V;
1213
1214 /* Check scaling after src size to prevent a divide-by-zero. */
1215 ret = check_overlay_scaling(params);
1216 if (ret != 0)
1217 goto out_unlock;
1218
1219 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1220 if (ret != 0)
1221 goto out_unlock;
1222
1223 mutex_unlock(&dev->struct_mutex);
1224 mutex_unlock(&dev->mode_config.mutex);
1225
1226 kfree(params);
1227
1228 return 0;
1229
1230out_unlock:
1231 mutex_unlock(&dev->struct_mutex);
1232 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1233 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1234out_free:
02e792fb
DV		 1235 kfree(params);
1236
1237 return ret;
1238}
1239
1240static void update_reg_attrs(struct intel_overlay *overlay,
1241 struct overlay_registers *regs)
1242{
1243 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1244 regs->OCLRC1 = overlay->saturation;
1245}
1246
1247static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1248{
1249 int i;
1250
1251 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1252 return false;
1253
1254 for (i = 0; i < 3; i++) {
722506f0 1255 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1256 return false;
1257 }
1258
1259 return true;
1260}
1261
1262static bool check_gamma5_errata(u32 gamma5)
1263{
1264 int i;
1265
1266 for (i = 0; i < 3; i++) {
1267 if (((gamma5 >> i*8) & 0xff) == 0x80)
1268 return false;
1269 }
1270
1271 return true;
1272}
1273
1274static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1275{
722506f0
CW		 1276 if (!check_gamma_bounds(0, attrs->gamma0) ||
1277 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1278 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1279 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1280 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1281 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1282 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1283 return -EINVAL;
722506f0 1284
02e792fb
DV		 1285 if (!check_gamma5_errata(attrs->gamma5))
1286 return -EINVAL;
722506f0 1287
02e792fb
DV		 1288 return 0;
1289}
1290
1291int intel_overlay_attrs(struct drm_device *dev, void *data,
1292 struct drm_file *file_priv)
1293{
1294 struct drm_intel_overlay_attrs *attrs = data;
1295 drm_i915_private_t *dev_priv = dev->dev_private;
1296 struct intel_overlay *overlay;
1297 struct overlay_registers *regs;
1298 int ret;
1299
1300 if (!dev_priv) {
1301 DRM_ERROR("called with no initialization\n");
1302 return -EINVAL;
1303 }
1304
1305 overlay = dev_priv->overlay;
1306 if (!overlay) {
1307 DRM_DEBUG("userspace bug: no overlay\n");
1308 return -ENODEV;
1309 }
1310
1311 mutex_lock(&dev->mode_config.mutex);
1312 mutex_lock(&dev->struct_mutex);
1313
60fc332c 1314 ret = -EINVAL;
02e792fb 1315 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1316 attrs->color_key = overlay->color_key;
02e792fb 1317 attrs->brightness = overlay->brightness;
60fc332c 1318 attrs->contrast = overlay->contrast;
02e792fb
DV		 1319 attrs->saturation = overlay->saturation;
1320
1321 if (IS_I9XX(dev)) {
1322 attrs->gamma0 = I915_READ(OGAMC0);
1323 attrs->gamma1 = I915_READ(OGAMC1);
1324 attrs->gamma2 = I915_READ(OGAMC2);
1325 attrs->gamma3 = I915_READ(OGAMC3);
1326 attrs->gamma4 = I915_READ(OGAMC4);
1327 attrs->gamma5 = I915_READ(OGAMC5);
1328 }
02e792fb 1329 } else {
60fc332c 1330 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1331 goto out_unlock;
60fc332c 1332 if (attrs->contrast > 255)
02e792fb 1333 goto out_unlock;
60fc332c 1334 if (attrs->saturation > 1023)
02e792fb 1335 goto out_unlock;
60fc332c
CW		 1336
1337 overlay->color_key = attrs->color_key;
1338 overlay->brightness = attrs->brightness;
1339 overlay->contrast = attrs->contrast;
1340 overlay->saturation = attrs->saturation;
02e792fb 1341
8d74f656 1342 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1343 if (!regs) {
1344 ret = -ENOMEM;
1345 goto out_unlock;
1346 }
1347
1348 update_reg_attrs(overlay, regs);
1349
8d74f656 1350 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 1351
1352 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
60fc332c 1353 if (!IS_I9XX(dev))
02e792fb 1354 goto out_unlock;
02e792fb
DV		 1355
1356 if (overlay->active) {
1357 ret = -EBUSY;
1358 goto out_unlock;
1359 }
1360
1361 ret = check_gamma(attrs);
60fc332c 1362 if (ret)
02e792fb
DV		 1363 goto out_unlock;
1364
1365 I915_WRITE(OGAMC0, attrs->gamma0);
1366 I915_WRITE(OGAMC1, attrs->gamma1);
1367 I915_WRITE(OGAMC2, attrs->gamma2);
1368 I915_WRITE(OGAMC3, attrs->gamma3);
1369 I915_WRITE(OGAMC4, attrs->gamma4);
1370 I915_WRITE(OGAMC5, attrs->gamma5);
1371 }
02e792fb
DV		 1372 }
1373
60fc332c 1374 ret = 0;
02e792fb
DV		 1375out_unlock:
1376 mutex_unlock(&dev->struct_mutex);
1377 mutex_unlock(&dev->mode_config.mutex);
1378
1379 return ret;
1380}
1381
1382void intel_setup_overlay(struct drm_device *dev)
1383{
1384 drm_i915_private_t *dev_priv = dev->dev_private;
1385 struct intel_overlay *overlay;
1386 struct drm_gem_object *reg_bo;
1387 struct overlay_registers *regs;
1388 int ret;
1389
31578148 1390 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1391 return;
1392
1393 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1394 if (!overlay)
1395 return;
1396 overlay->dev = dev;
1397
ac52bc56 1398 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1399 if (!reg_bo)
1400 goto out_free;
23010e43 1401 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb 1402
31578148
CW		 1403 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1404 ret = i915_gem_attach_phys_object(dev, reg_bo,
1405 I915_GEM_PHYS_OVERLAY_REGS,
a2930128 1406 PAGE_SIZE);
31578148
CW		 1407 if (ret) {
1408 DRM_ERROR("failed to attach phys overlay regs\n");
1409 goto out_free_bo;
1410 }
1411 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1412 } else {
02e792fb
DV		 1413 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1414 if (ret) {
1415 DRM_ERROR("failed to pin overlay register bo\n");
1416 goto out_free_bo;
1417 }
1418 overlay->flip_addr = overlay->reg_bo->gtt_offset;
0ddc1289
CW		 1419
1420 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1421 if (ret) {
1422 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1423 goto out_unpin_bo;
1424 }
02e792fb
DV		 1425 }
1426
1427 /* init all values */
1428 overlay->color_key = 0x0101fe;
1429 overlay->brightness = -19;
1430 overlay->contrast = 75;
1431 overlay->saturation = 146;
1432
8d74f656 1433 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1434 if (!regs)
1435 goto out_free_bo;
1436
1437 memset(regs, 0, sizeof(struct overlay_registers));
1438 update_polyphase_filter(regs);
1439
1440 update_reg_attrs(overlay, regs);
1441
8d74f656 1442 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 1443
1444 dev_priv->overlay = overlay;
1445 DRM_INFO("initialized overlay support\n");
1446 return;
1447
0ddc1289
CW		 1448out_unpin_bo:
1449 i915_gem_object_unpin(reg_bo);
02e792fb
DV		 1450out_free_bo:
1451 drm_gem_object_unreference(reg_bo);
1452out_free:
1453 kfree(overlay);
1454 return;
1455}
1456
1457void intel_cleanup_overlay(struct drm_device *dev)
1458{
722506f0 1459 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 1460
62cf4e6f
CW		 1461 if (!dev_priv->overlay)
1462 return;
02e792fb 1463
62cf4e6f
CW		 1464 /* The bo's should be free'd by the generic code already.
1465 * Furthermore modesetting teardown happens beforehand so the
1466 * hardware should be off already */
1467 BUG_ON(dev_priv->overlay->active);
1468
1469 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1470 kfree(dev_priv->overlay);
02e792fb 1471}
6ef3d427
CW		 1472
1473struct intel_overlay_error_state {
1474 struct overlay_registers regs;
1475 unsigned long base;
1476 u32 dovsta;
1477 u32 isr;
1478};
1479
1480struct intel_overlay_error_state *
1481intel_overlay_capture_error_state(struct drm_device *dev)
1482{
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1484 struct intel_overlay *overlay = dev_priv->overlay;
1485 struct intel_overlay_error_state *error;
1486 struct overlay_registers __iomem *regs;
1487
1488 if (!overlay || !overlay->active)
1489 return NULL;
1490
1491 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1492 if (error == NULL)
1493 return NULL;
1494
1495 error->dovsta = I915_READ(DOVSTA);
1496 error->isr = I915_READ(ISR);
31578148 1497 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
6ef3d427 1498 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
31578148
CW		 1499 else
1500 error->base = (long) overlay->reg_bo->gtt_offset;
6ef3d427 1501
8d74f656 1502 regs = intel_overlay_map_regs_atomic(overlay, KM_IRQ0);
6ef3d427
CW		 1503 if (!regs)
1504 goto err;
1505
1506 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
8d74f656 1507 intel_overlay_unmap_regs_atomic(overlay, KM_IRQ0);
6ef3d427
CW		 1508
1509 return error;
1510
1511err:
1512 kfree(error);
1513 return NULL;
1514}
1515
1516void
1517intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1518{
1519 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1520 error->dovsta, error->isr);
1521 seq_printf(m, " Register file at 0x%08lx:\n",
1522 error->base);
1523
1524#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1525 P(OBUF_0Y);
1526 P(OBUF_1Y);
1527 P(OBUF_0U);
1528 P(OBUF_0V);
1529 P(OBUF_1U);
1530 P(OBUF_1V);
1531 P(OSTRIDE);
1532 P(YRGB_VPH);
1533 P(UV_VPH);
1534 P(HORZ_PH);
1535 P(INIT_PHS);
1536 P(DWINPOS);
1537 P(DWINSZ);
1538 P(SWIDTH);
1539 P(SWIDTHSW);
1540 P(SHEIGHT);
1541 P(YRGBSCALE);
1542 P(UVSCALE);
1543 P(OCLRC0);
1544 P(OCLRC1);
1545 P(DCLRKV);
1546 P(DCLRKM);
1547 P(SCLRKVH);
1548 P(SCLRKVL);
1549 P(SCLRKEN);
1550 P(OCONFIG);
1551 P(OCMD);
1552 P(OSTART_0Y);
1553 P(OSTART_1Y);
1554 P(OSTART_0U);
1555 P(OSTART_0V);
1556 P(OSTART_1U);
1557 P(OSTART_1V);
1558 P(OTILEOFF_0Y);
1559 P(OTILEOFF_1Y);
1560 P(OTILEOFF_0U);
1561 P(OTILEOFF_0V);
1562 P(OTILEOFF_1U);
1563 P(OTILEOFF_1V);
1564 P(FASTHSCALE);
1565 P(UVSCALEV);
1566#undef P
1567}
Linux kernel - Deliverables
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