Commit | Line | Data |
---|---|---|
1d8e1c75 CW |
1 | /* |
2 | * Copyright © 2006-2010 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | * Chris Wilson <chris@chris-wilson.co.uk> | |
29 | */ | |
30 | ||
a70491cc JP |
31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
32 | ||
7bd90909 | 33 | #include <linux/moduleparam.h> |
1d8e1c75 CW |
34 | #include "intel_drv.h" |
35 | ||
36 | void | |
4c6df4b4 | 37 | intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
1d8e1c75 CW |
38 | struct drm_display_mode *adjusted_mode) |
39 | { | |
4c6df4b4 | 40 | drm_mode_copy(adjusted_mode, fixed_mode); |
a52690e4 ID |
41 | |
42 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
1d8e1c75 CW |
43 | } |
44 | ||
525997e0 JN |
45 | /** |
46 | * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID | |
47 | * @dev: drm device | |
48 | * @fixed_mode : panel native mode | |
49 | * @connector: LVDS/eDP connector | |
50 | * | |
51 | * Return downclock_avail | |
52 | * Find the reduced downclock for LVDS/eDP in EDID. | |
53 | */ | |
54 | struct drm_display_mode * | |
55 | intel_find_panel_downclock(struct drm_device *dev, | |
56 | struct drm_display_mode *fixed_mode, | |
57 | struct drm_connector *connector) | |
58 | { | |
59 | struct drm_display_mode *scan, *tmp_mode; | |
60 | int temp_downclock; | |
61 | ||
62 | temp_downclock = fixed_mode->clock; | |
63 | tmp_mode = NULL; | |
64 | ||
65 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
66 | /* | |
67 | * If one mode has the same resolution with the fixed_panel | |
68 | * mode while they have the different refresh rate, it means | |
69 | * that the reduced downclock is found. In such | |
70 | * case we can set the different FPx0/1 to dynamically select | |
71 | * between low and high frequency. | |
72 | */ | |
73 | if (scan->hdisplay == fixed_mode->hdisplay && | |
74 | scan->hsync_start == fixed_mode->hsync_start && | |
75 | scan->hsync_end == fixed_mode->hsync_end && | |
76 | scan->htotal == fixed_mode->htotal && | |
77 | scan->vdisplay == fixed_mode->vdisplay && | |
78 | scan->vsync_start == fixed_mode->vsync_start && | |
79 | scan->vsync_end == fixed_mode->vsync_end && | |
80 | scan->vtotal == fixed_mode->vtotal) { | |
81 | if (scan->clock < temp_downclock) { | |
82 | /* | |
83 | * The downclock is already found. But we | |
84 | * expect to find the lower downclock. | |
85 | */ | |
86 | temp_downclock = scan->clock; | |
87 | tmp_mode = scan; | |
88 | } | |
89 | } | |
90 | } | |
91 | ||
92 | if (temp_downclock < fixed_mode->clock) | |
93 | return drm_mode_duplicate(dev, tmp_mode); | |
94 | else | |
95 | return NULL; | |
96 | } | |
97 | ||
1d8e1c75 CW |
98 | /* adjusted_mode has been preset to be the panel's fixed mode */ |
99 | void | |
b074cec8 JB |
100 | intel_pch_panel_fitting(struct intel_crtc *intel_crtc, |
101 | struct intel_crtc_config *pipe_config, | |
102 | int fitting_mode) | |
1d8e1c75 | 103 | { |
37327abd | 104 | struct drm_display_mode *adjusted_mode; |
1d8e1c75 CW |
105 | int x, y, width, height; |
106 | ||
b074cec8 JB |
107 | adjusted_mode = &pipe_config->adjusted_mode; |
108 | ||
1d8e1c75 CW |
109 | x = y = width = height = 0; |
110 | ||
111 | /* Native modes don't need fitting */ | |
37327abd VS |
112 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
113 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | |
1d8e1c75 CW |
114 | goto done; |
115 | ||
116 | switch (fitting_mode) { | |
117 | case DRM_MODE_SCALE_CENTER: | |
37327abd VS |
118 | width = pipe_config->pipe_src_w; |
119 | height = pipe_config->pipe_src_h; | |
1d8e1c75 CW |
120 | x = (adjusted_mode->hdisplay - width + 1)/2; |
121 | y = (adjusted_mode->vdisplay - height + 1)/2; | |
122 | break; | |
123 | ||
124 | case DRM_MODE_SCALE_ASPECT: | |
125 | /* Scale but preserve the aspect ratio */ | |
126 | { | |
9084e7d2 DV |
127 | u32 scaled_width = adjusted_mode->hdisplay |
128 | * pipe_config->pipe_src_h; | |
129 | u32 scaled_height = pipe_config->pipe_src_w | |
130 | * adjusted_mode->vdisplay; | |
1d8e1c75 | 131 | if (scaled_width > scaled_height) { /* pillar */ |
37327abd | 132 | width = scaled_height / pipe_config->pipe_src_h; |
302983e9 | 133 | if (width & 1) |
0206e353 | 134 | width++; |
1d8e1c75 CW |
135 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
136 | y = 0; | |
137 | height = adjusted_mode->vdisplay; | |
138 | } else if (scaled_width < scaled_height) { /* letter */ | |
37327abd | 139 | height = scaled_width / pipe_config->pipe_src_w; |
302983e9 AJ |
140 | if (height & 1) |
141 | height++; | |
1d8e1c75 CW |
142 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
143 | x = 0; | |
144 | width = adjusted_mode->hdisplay; | |
145 | } else { | |
146 | x = y = 0; | |
147 | width = adjusted_mode->hdisplay; | |
148 | height = adjusted_mode->vdisplay; | |
149 | } | |
150 | } | |
151 | break; | |
152 | ||
1d8e1c75 CW |
153 | case DRM_MODE_SCALE_FULLSCREEN: |
154 | x = y = 0; | |
155 | width = adjusted_mode->hdisplay; | |
156 | height = adjusted_mode->vdisplay; | |
157 | break; | |
ab3e67f4 JB |
158 | |
159 | default: | |
160 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
161 | return; | |
1d8e1c75 CW |
162 | } |
163 | ||
164 | done: | |
b074cec8 JB |
165 | pipe_config->pch_pfit.pos = (x << 16) | y; |
166 | pipe_config->pch_pfit.size = (width << 16) | height; | |
fd4daa9c | 167 | pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; |
1d8e1c75 | 168 | } |
a9573556 | 169 | |
2dd24552 JB |
170 | static void |
171 | centre_horizontally(struct drm_display_mode *mode, | |
172 | int width) | |
173 | { | |
174 | u32 border, sync_pos, blank_width, sync_width; | |
175 | ||
176 | /* keep the hsync and hblank widths constant */ | |
177 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
178 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
179 | sync_pos = (blank_width - sync_width + 1) / 2; | |
180 | ||
181 | border = (mode->hdisplay - width + 1) / 2; | |
182 | border += border & 1; /* make the border even */ | |
183 | ||
184 | mode->crtc_hdisplay = width; | |
185 | mode->crtc_hblank_start = width + border; | |
186 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
187 | ||
188 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
189 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
190 | } | |
191 | ||
192 | static void | |
193 | centre_vertically(struct drm_display_mode *mode, | |
194 | int height) | |
195 | { | |
196 | u32 border, sync_pos, blank_width, sync_width; | |
197 | ||
198 | /* keep the vsync and vblank widths constant */ | |
199 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
200 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
201 | sync_pos = (blank_width - sync_width + 1) / 2; | |
202 | ||
203 | border = (mode->vdisplay - height + 1) / 2; | |
204 | ||
205 | mode->crtc_vdisplay = height; | |
206 | mode->crtc_vblank_start = height + border; | |
207 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
208 | ||
209 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
210 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
211 | } | |
212 | ||
213 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
214 | { | |
215 | /* | |
216 | * Floating point operation is not supported. So the FACTOR | |
217 | * is defined, which can avoid the floating point computation | |
218 | * when calculating the panel ratio. | |
219 | */ | |
220 | #define ACCURACY 12 | |
221 | #define FACTOR (1 << ACCURACY) | |
222 | u32 ratio = source * FACTOR / target; | |
223 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
224 | } | |
225 | ||
9084e7d2 DV |
226 | static void i965_scale_aspect(struct intel_crtc_config *pipe_config, |
227 | u32 *pfit_control) | |
228 | { | |
229 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
230 | u32 scaled_width = adjusted_mode->hdisplay * | |
231 | pipe_config->pipe_src_h; | |
232 | u32 scaled_height = pipe_config->pipe_src_w * | |
233 | adjusted_mode->vdisplay; | |
234 | ||
235 | /* 965+ is easy, it does everything in hw */ | |
236 | if (scaled_width > scaled_height) | |
237 | *pfit_control |= PFIT_ENABLE | | |
238 | PFIT_SCALING_PILLAR; | |
239 | else if (scaled_width < scaled_height) | |
240 | *pfit_control |= PFIT_ENABLE | | |
241 | PFIT_SCALING_LETTER; | |
242 | else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w) | |
243 | *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
244 | } | |
245 | ||
246 | static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config, | |
247 | u32 *pfit_control, u32 *pfit_pgm_ratios, | |
248 | u32 *border) | |
249 | { | |
250 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
251 | u32 scaled_width = adjusted_mode->hdisplay * | |
252 | pipe_config->pipe_src_h; | |
253 | u32 scaled_height = pipe_config->pipe_src_w * | |
254 | adjusted_mode->vdisplay; | |
255 | u32 bits; | |
256 | ||
257 | /* | |
258 | * For earlier chips we have to calculate the scaling | |
259 | * ratio by hand and program it into the | |
260 | * PFIT_PGM_RATIO register | |
261 | */ | |
262 | if (scaled_width > scaled_height) { /* pillar */ | |
263 | centre_horizontally(adjusted_mode, | |
264 | scaled_height / | |
265 | pipe_config->pipe_src_h); | |
266 | ||
267 | *border = LVDS_BORDER_ENABLE; | |
268 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) { | |
269 | bits = panel_fitter_scaling(pipe_config->pipe_src_h, | |
270 | adjusted_mode->vdisplay); | |
271 | ||
272 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
273 | bits << PFIT_VERT_SCALE_SHIFT); | |
274 | *pfit_control |= (PFIT_ENABLE | | |
275 | VERT_INTERP_BILINEAR | | |
276 | HORIZ_INTERP_BILINEAR); | |
277 | } | |
278 | } else if (scaled_width < scaled_height) { /* letter */ | |
279 | centre_vertically(adjusted_mode, | |
280 | scaled_width / | |
281 | pipe_config->pipe_src_w); | |
282 | ||
283 | *border = LVDS_BORDER_ENABLE; | |
284 | if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | |
285 | bits = panel_fitter_scaling(pipe_config->pipe_src_w, | |
286 | adjusted_mode->hdisplay); | |
287 | ||
288 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
289 | bits << PFIT_VERT_SCALE_SHIFT); | |
290 | *pfit_control |= (PFIT_ENABLE | | |
291 | VERT_INTERP_BILINEAR | | |
292 | HORIZ_INTERP_BILINEAR); | |
293 | } | |
294 | } else { | |
295 | /* Aspects match, Let hw scale both directions */ | |
296 | *pfit_control |= (PFIT_ENABLE | | |
297 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
298 | VERT_INTERP_BILINEAR | | |
299 | HORIZ_INTERP_BILINEAR); | |
300 | } | |
301 | } | |
302 | ||
2dd24552 JB |
303 | void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, |
304 | struct intel_crtc_config *pipe_config, | |
305 | int fitting_mode) | |
306 | { | |
307 | struct drm_device *dev = intel_crtc->base.dev; | |
2dd24552 | 308 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
37327abd | 309 | struct drm_display_mode *adjusted_mode; |
2dd24552 | 310 | |
2dd24552 JB |
311 | adjusted_mode = &pipe_config->adjusted_mode; |
312 | ||
313 | /* Native modes don't need fitting */ | |
37327abd VS |
314 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
315 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | |
2dd24552 JB |
316 | goto out; |
317 | ||
318 | switch (fitting_mode) { | |
319 | case DRM_MODE_SCALE_CENTER: | |
320 | /* | |
321 | * For centered modes, we have to calculate border widths & | |
322 | * heights and modify the values programmed into the CRTC. | |
323 | */ | |
37327abd VS |
324 | centre_horizontally(adjusted_mode, pipe_config->pipe_src_w); |
325 | centre_vertically(adjusted_mode, pipe_config->pipe_src_h); | |
2dd24552 JB |
326 | border = LVDS_BORDER_ENABLE; |
327 | break; | |
328 | case DRM_MODE_SCALE_ASPECT: | |
329 | /* Scale but preserve the aspect ratio */ | |
9084e7d2 DV |
330 | if (INTEL_INFO(dev)->gen >= 4) |
331 | i965_scale_aspect(pipe_config, &pfit_control); | |
332 | else | |
333 | i9xx_scale_aspect(pipe_config, &pfit_control, | |
334 | &pfit_pgm_ratios, &border); | |
2dd24552 | 335 | break; |
2dd24552 JB |
336 | case DRM_MODE_SCALE_FULLSCREEN: |
337 | /* | |
338 | * Full scaling, even if it changes the aspect ratio. | |
339 | * Fortunately this is all done for us in hw. | |
340 | */ | |
37327abd VS |
341 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay || |
342 | pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | |
2dd24552 JB |
343 | pfit_control |= PFIT_ENABLE; |
344 | if (INTEL_INFO(dev)->gen >= 4) | |
345 | pfit_control |= PFIT_SCALING_AUTO; | |
346 | else | |
347 | pfit_control |= (VERT_AUTO_SCALE | | |
348 | VERT_INTERP_BILINEAR | | |
349 | HORIZ_AUTO_SCALE | | |
350 | HORIZ_INTERP_BILINEAR); | |
351 | } | |
352 | break; | |
ab3e67f4 JB |
353 | default: |
354 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
355 | return; | |
2dd24552 JB |
356 | } |
357 | ||
358 | /* 965+ wants fuzzy fitting */ | |
359 | /* FIXME: handle multiple panels by failing gracefully */ | |
360 | if (INTEL_INFO(dev)->gen >= 4) | |
361 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | | |
362 | PFIT_FILTER_FUZZY); | |
363 | ||
364 | out: | |
365 | if ((pfit_control & PFIT_ENABLE) == 0) { | |
366 | pfit_control = 0; | |
367 | pfit_pgm_ratios = 0; | |
368 | } | |
369 | ||
6b89cdde DV |
370 | /* Make sure pre-965 set dither correctly for 18bpp panels. */ |
371 | if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) | |
372 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
373 | ||
2deefda5 DV |
374 | pipe_config->gmch_pfit.control = pfit_control; |
375 | pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; | |
68fc8742 | 376 | pipe_config->gmch_pfit.lvds_border_bits = border; |
2dd24552 JB |
377 | } |
378 | ||
525997e0 JN |
379 | enum drm_connector_status |
380 | intel_panel_detect(struct drm_device *dev) | |
381 | { | |
382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
383 | ||
384 | /* Assume that the BIOS does not lie through the OpRegion... */ | |
385 | if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) { | |
386 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? | |
387 | connector_status_connected : | |
388 | connector_status_disconnected; | |
389 | } | |
390 | ||
391 | switch (i915.panel_ignore_lid) { | |
392 | case -2: | |
393 | return connector_status_connected; | |
394 | case -1: | |
395 | return connector_status_disconnected; | |
396 | default: | |
397 | return connector_status_unknown; | |
398 | } | |
399 | } | |
400 | ||
6dda730e JN |
401 | /** |
402 | * scale - scale values from one range to another | |
403 | * | |
404 | * @source_val: value in range [@source_min..@source_max] | |
405 | * | |
406 | * Return @source_val in range [@source_min..@source_max] scaled to range | |
407 | * [@target_min..@target_max]. | |
408 | */ | |
409 | static uint32_t scale(uint32_t source_val, | |
410 | uint32_t source_min, uint32_t source_max, | |
411 | uint32_t target_min, uint32_t target_max) | |
412 | { | |
413 | uint64_t target_val; | |
414 | ||
415 | WARN_ON(source_min > source_max); | |
416 | WARN_ON(target_min > target_max); | |
417 | ||
418 | /* defensive */ | |
419 | source_val = clamp(source_val, source_min, source_max); | |
420 | ||
421 | /* avoid overflows */ | |
422 | target_val = (uint64_t)(source_val - source_min) * | |
423 | (target_max - target_min); | |
424 | do_div(target_val, source_max - source_min); | |
425 | target_val += target_min; | |
426 | ||
427 | return target_val; | |
428 | } | |
429 | ||
430 | /* Scale user_level in range [0..user_max] to [hw_min..hw_max]. */ | |
431 | static inline u32 scale_user_to_hw(struct intel_connector *connector, | |
432 | u32 user_level, u32 user_max) | |
433 | { | |
434 | struct intel_panel *panel = &connector->panel; | |
435 | ||
436 | return scale(user_level, 0, user_max, | |
437 | panel->backlight.min, panel->backlight.max); | |
438 | } | |
439 | ||
440 | /* Scale user_level in range [0..user_max] to [0..hw_max], clamping the result | |
441 | * to [hw_min..hw_max]. */ | |
442 | static inline u32 clamp_user_to_hw(struct intel_connector *connector, | |
443 | u32 user_level, u32 user_max) | |
444 | { | |
445 | struct intel_panel *panel = &connector->panel; | |
446 | u32 hw_level; | |
447 | ||
448 | hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max); | |
449 | hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max); | |
450 | ||
451 | return hw_level; | |
452 | } | |
453 | ||
454 | /* Scale hw_level in range [hw_min..hw_max] to [0..user_max]. */ | |
455 | static inline u32 scale_hw_to_user(struct intel_connector *connector, | |
456 | u32 hw_level, u32 user_max) | |
457 | { | |
458 | struct intel_panel *panel = &connector->panel; | |
459 | ||
460 | return scale(hw_level, panel->backlight.min, panel->backlight.max, | |
461 | 0, user_max); | |
462 | } | |
463 | ||
7bd688cd JN |
464 | static u32 intel_panel_compute_brightness(struct intel_connector *connector, |
465 | u32 val) | |
7bd90909 | 466 | { |
7bd688cd | 467 | struct drm_device *dev = connector->base.dev; |
4dca20ef | 468 | struct drm_i915_private *dev_priv = dev->dev_private; |
f91c15e0 JN |
469 | struct intel_panel *panel = &connector->panel; |
470 | ||
471 | WARN_ON(panel->backlight.max == 0); | |
4dca20ef | 472 | |
d330a953 | 473 | if (i915.invert_brightness < 0) |
4dca20ef CE |
474 | return val; |
475 | ||
d330a953 | 476 | if (i915.invert_brightness > 0 || |
d6540632 | 477 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
f91c15e0 | 478 | return panel->backlight.max - val; |
d6540632 | 479 | } |
7bd90909 CE |
480 | |
481 | return val; | |
482 | } | |
483 | ||
96ab4c70 | 484 | static u32 bdw_get_backlight(struct intel_connector *connector) |
0b0b053a | 485 | { |
96ab4c70 | 486 | struct drm_device *dev = connector->base.dev; |
bfd7590d | 487 | struct drm_i915_private *dev_priv = dev->dev_private; |
0b0b053a | 488 | |
96ab4c70 DV |
489 | return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; |
490 | } | |
07bf139b | 491 | |
7bd688cd | 492 | static u32 pch_get_backlight(struct intel_connector *connector) |
a9573556 | 493 | { |
7bd688cd | 494 | struct drm_device *dev = connector->base.dev; |
a9573556 | 495 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ba2d185 | 496 | |
7bd688cd JN |
497 | return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
498 | } | |
a9573556 | 499 | |
7bd688cd JN |
500 | static u32 i9xx_get_backlight(struct intel_connector *connector) |
501 | { | |
502 | struct drm_device *dev = connector->base.dev; | |
503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
636baebf | 504 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 505 | u32 val; |
07bf139b | 506 | |
7bd688cd JN |
507 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
508 | if (INTEL_INFO(dev)->gen < 4) | |
509 | val >>= 1; | |
ba3820ad | 510 | |
636baebf | 511 | if (panel->backlight.combination_mode) { |
7bd688cd | 512 | u8 lbpc; |
ba3820ad | 513 | |
7bd688cd JN |
514 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
515 | val *= lbpc; | |
a9573556 CW |
516 | } |
517 | ||
7bd688cd JN |
518 | return val; |
519 | } | |
520 | ||
521 | static u32 _vlv_get_backlight(struct drm_device *dev, enum pipe pipe) | |
522 | { | |
523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
524 | ||
525 | return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; | |
526 | } | |
527 | ||
528 | static u32 vlv_get_backlight(struct intel_connector *connector) | |
529 | { | |
530 | struct drm_device *dev = connector->base.dev; | |
531 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
532 | ||
533 | return _vlv_get_backlight(dev, pipe); | |
534 | } | |
535 | ||
536 | static u32 intel_panel_get_backlight(struct intel_connector *connector) | |
537 | { | |
538 | struct drm_device *dev = connector->base.dev; | |
539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
540 | u32 val; | |
541 | unsigned long flags; | |
542 | ||
543 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); | |
544 | ||
545 | val = dev_priv->display.get_backlight(connector); | |
546 | val = intel_panel_compute_brightness(connector, val); | |
8ba2d185 | 547 | |
58c68779 | 548 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
8ba2d185 | 549 | |
a9573556 CW |
550 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
551 | return val; | |
552 | } | |
553 | ||
96ab4c70 | 554 | static void bdw_set_backlight(struct intel_connector *connector, u32 level) |
f8e10062 | 555 | { |
96ab4c70 | 556 | struct drm_device *dev = connector->base.dev; |
f8e10062 BW |
557 | struct drm_i915_private *dev_priv = dev->dev_private; |
558 | u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
559 | I915_WRITE(BLC_PWM_PCH_CTL2, val | level); | |
560 | } | |
561 | ||
7bd688cd | 562 | static void pch_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 563 | { |
7bd688cd | 564 | struct drm_device *dev = connector->base.dev; |
a9573556 | 565 | struct drm_i915_private *dev_priv = dev->dev_private; |
7bd688cd JN |
566 | u32 tmp; |
567 | ||
568 | tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
569 | I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); | |
a9573556 CW |
570 | } |
571 | ||
7bd688cd | 572 | static void i9xx_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 573 | { |
7bd688cd | 574 | struct drm_device *dev = connector->base.dev; |
a9573556 | 575 | struct drm_i915_private *dev_priv = dev->dev_private; |
f91c15e0 | 576 | struct intel_panel *panel = &connector->panel; |
b329b328 | 577 | u32 tmp, mask; |
ba3820ad | 578 | |
f91c15e0 JN |
579 | WARN_ON(panel->backlight.max == 0); |
580 | ||
636baebf | 581 | if (panel->backlight.combination_mode) { |
ba3820ad TI |
582 | u8 lbpc; |
583 | ||
f91c15e0 | 584 | lbpc = level * 0xfe / panel->backlight.max + 1; |
ba3820ad TI |
585 | level /= lbpc; |
586 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); | |
587 | } | |
588 | ||
b329b328 JN |
589 | if (IS_GEN4(dev)) { |
590 | mask = BACKLIGHT_DUTY_CYCLE_MASK; | |
591 | } else { | |
a9573556 | 592 | level <<= 1; |
b329b328 JN |
593 | mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV; |
594 | } | |
7bd688cd | 595 | |
b329b328 | 596 | tmp = I915_READ(BLC_PWM_CTL) & ~mask; |
7bd688cd JN |
597 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
598 | } | |
599 | ||
600 | static void vlv_set_backlight(struct intel_connector *connector, u32 level) | |
601 | { | |
602 | struct drm_device *dev = connector->base.dev; | |
603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
604 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
605 | u32 tmp; | |
606 | ||
607 | tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
608 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); | |
609 | } | |
610 | ||
611 | static void | |
612 | intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level) | |
613 | { | |
614 | struct drm_device *dev = connector->base.dev; | |
615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
616 | ||
617 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); | |
618 | ||
619 | level = intel_panel_compute_brightness(connector, level); | |
620 | dev_priv->display.set_backlight(connector, level); | |
a9573556 | 621 | } |
47356eb6 | 622 | |
6dda730e JN |
623 | /* set backlight brightness to level in range [0..max], scaling wrt hw min */ |
624 | static void intel_panel_set_backlight(struct intel_connector *connector, | |
625 | u32 user_level, u32 user_max) | |
47356eb6 | 626 | { |
752aa88a | 627 | struct drm_device *dev = connector->base.dev; |
47356eb6 | 628 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 629 | struct intel_panel *panel = &connector->panel; |
752aa88a | 630 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
6dda730e | 631 | u32 hw_level; |
8ba2d185 JN |
632 | unsigned long flags; |
633 | ||
dc5a4363 | 634 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
635 | return; |
636 | ||
58c68779 | 637 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
d6540632 | 638 | |
f91c15e0 | 639 | WARN_ON(panel->backlight.max == 0); |
d6540632 | 640 | |
6dda730e JN |
641 | hw_level = scale_user_to_hw(connector, user_level, user_max); |
642 | panel->backlight.level = hw_level; | |
643 | ||
644 | if (panel->backlight.enabled) | |
645 | intel_panel_actually_set_backlight(connector, hw_level); | |
646 | ||
647 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); | |
648 | } | |
649 | ||
650 | /* set backlight brightness to level in range [0..max], assuming hw min is | |
651 | * respected. | |
652 | */ | |
653 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, | |
654 | u32 user_level, u32 user_max) | |
655 | { | |
656 | struct drm_device *dev = connector->base.dev; | |
657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
658 | struct intel_panel *panel = &connector->panel; | |
659 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
660 | u32 hw_level; | |
661 | unsigned long flags; | |
662 | ||
663 | if (!panel->backlight.present || pipe == INVALID_PIPE) | |
664 | return; | |
665 | ||
666 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); | |
667 | ||
668 | WARN_ON(panel->backlight.max == 0); | |
669 | ||
670 | hw_level = clamp_user_to_hw(connector, user_level, user_max); | |
671 | panel->backlight.level = hw_level; | |
47356eb6 | 672 | |
58c68779 | 673 | if (panel->backlight.device) |
6dda730e JN |
674 | panel->backlight.device->props.brightness = |
675 | scale_hw_to_user(connector, | |
676 | panel->backlight.level, | |
677 | panel->backlight.device->props.max_brightness); | |
b6b3ba5b | 678 | |
58c68779 | 679 | if (panel->backlight.enabled) |
6dda730e | 680 | intel_panel_actually_set_backlight(connector, hw_level); |
f91c15e0 | 681 | |
58c68779 | 682 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
f52c619a TI |
683 | } |
684 | ||
7bd688cd JN |
685 | static void pch_disable_backlight(struct intel_connector *connector) |
686 | { | |
687 | struct drm_device *dev = connector->base.dev; | |
688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
689 | u32 tmp; | |
690 | ||
3bd712e5 JN |
691 | intel_panel_actually_set_backlight(connector, 0); |
692 | ||
7bd688cd JN |
693 | tmp = I915_READ(BLC_PWM_CPU_CTL2); |
694 | I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); | |
695 | ||
696 | tmp = I915_READ(BLC_PWM_PCH_CTL1); | |
697 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); | |
698 | } | |
699 | ||
3bd712e5 JN |
700 | static void i9xx_disable_backlight(struct intel_connector *connector) |
701 | { | |
702 | intel_panel_actually_set_backlight(connector, 0); | |
703 | } | |
704 | ||
7bd688cd JN |
705 | static void i965_disable_backlight(struct intel_connector *connector) |
706 | { | |
707 | struct drm_device *dev = connector->base.dev; | |
708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
709 | u32 tmp; | |
710 | ||
3bd712e5 JN |
711 | intel_panel_actually_set_backlight(connector, 0); |
712 | ||
7bd688cd JN |
713 | tmp = I915_READ(BLC_PWM_CTL2); |
714 | I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); | |
715 | } | |
716 | ||
717 | static void vlv_disable_backlight(struct intel_connector *connector) | |
718 | { | |
719 | struct drm_device *dev = connector->base.dev; | |
720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
721 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
722 | u32 tmp; | |
723 | ||
3bd712e5 JN |
724 | intel_panel_actually_set_backlight(connector, 0); |
725 | ||
7bd688cd JN |
726 | tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
727 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE); | |
728 | } | |
729 | ||
752aa88a | 730 | void intel_panel_disable_backlight(struct intel_connector *connector) |
f52c619a | 731 | { |
752aa88a | 732 | struct drm_device *dev = connector->base.dev; |
f52c619a | 733 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 734 | struct intel_panel *panel = &connector->panel; |
752aa88a | 735 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
8ba2d185 JN |
736 | unsigned long flags; |
737 | ||
dc5a4363 | 738 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
739 | return; |
740 | ||
3f577573 JN |
741 | /* |
742 | * Do not disable backlight on the vgaswitcheroo path. When switching | |
743 | * away from i915, the other client may depend on i915 to handle the | |
744 | * backlight. This will leave the backlight on unnecessarily when | |
745 | * another client is not activated. | |
746 | */ | |
747 | if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) { | |
748 | DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); | |
749 | return; | |
750 | } | |
751 | ||
58c68779 | 752 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
47356eb6 | 753 | |
58c68779 | 754 | panel->backlight.enabled = false; |
3bd712e5 | 755 | dev_priv->display.disable_backlight(connector); |
24ded204 | 756 | |
7bd688cd JN |
757 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
758 | } | |
24ded204 | 759 | |
96ab4c70 DV |
760 | static void bdw_enable_backlight(struct intel_connector *connector) |
761 | { | |
762 | struct drm_device *dev = connector->base.dev; | |
763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
764 | struct intel_panel *panel = &connector->panel; | |
765 | u32 pch_ctl1, pch_ctl2; | |
766 | ||
767 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
768 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
769 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
770 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
771 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
772 | } | |
24ded204 | 773 | |
96ab4c70 DV |
774 | pch_ctl2 = panel->backlight.max << 16; |
775 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
a4f32fc3 | 776 | |
96ab4c70 DV |
777 | pch_ctl1 = 0; |
778 | if (panel->backlight.active_low_pwm) | |
779 | pch_ctl1 |= BLM_PCH_POLARITY; | |
8ba2d185 | 780 | |
96ab4c70 DV |
781 | /* BDW always uses the pch pwm controls. */ |
782 | pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE; | |
783 | ||
784 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
785 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
786 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
787 | ||
788 | /* This won't stick until the above enable. */ | |
789 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
47356eb6 CW |
790 | } |
791 | ||
7bd688cd JN |
792 | static void pch_enable_backlight(struct intel_connector *connector) |
793 | { | |
794 | struct drm_device *dev = connector->base.dev; | |
795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 796 | struct intel_panel *panel = &connector->panel; |
7bd688cd JN |
797 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
798 | enum transcoder cpu_transcoder = | |
799 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
b35684b8 | 800 | u32 cpu_ctl2, pch_ctl1, pch_ctl2; |
7bd688cd | 801 | |
b35684b8 JN |
802 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
803 | if (cpu_ctl2 & BLM_PWM_ENABLE) { | |
804 | WARN(1, "cpu backlight already enabled\n"); | |
805 | cpu_ctl2 &= ~BLM_PWM_ENABLE; | |
806 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
807 | } | |
7bd688cd | 808 | |
b35684b8 JN |
809 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
810 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
811 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
812 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
813 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
814 | } | |
7bd688cd JN |
815 | |
816 | if (cpu_transcoder == TRANSCODER_EDP) | |
b35684b8 | 817 | cpu_ctl2 = BLM_TRANSCODER_EDP; |
7bd688cd | 818 | else |
b35684b8 JN |
819 | cpu_ctl2 = BLM_PIPE(cpu_transcoder); |
820 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
7bd688cd | 821 | POSTING_READ(BLC_PWM_CPU_CTL2); |
b35684b8 | 822 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); |
3bd712e5 | 823 | |
b35684b8 | 824 | /* This won't stick until the above enable. */ |
3bd712e5 | 825 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
b35684b8 JN |
826 | |
827 | pch_ctl2 = panel->backlight.max << 16; | |
828 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
829 | ||
b35684b8 JN |
830 | pch_ctl1 = 0; |
831 | if (panel->backlight.active_low_pwm) | |
832 | pch_ctl1 |= BLM_PCH_POLARITY; | |
96ab4c70 | 833 | |
b35684b8 JN |
834 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); |
835 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
836 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
3bd712e5 JN |
837 | } |
838 | ||
839 | static void i9xx_enable_backlight(struct intel_connector *connector) | |
840 | { | |
b35684b8 JN |
841 | struct drm_device *dev = connector->base.dev; |
842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 843 | struct intel_panel *panel = &connector->panel; |
b35684b8 JN |
844 | u32 ctl, freq; |
845 | ||
846 | ctl = I915_READ(BLC_PWM_CTL); | |
847 | if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { | |
848 | WARN(1, "backlight already enabled\n"); | |
849 | I915_WRITE(BLC_PWM_CTL, 0); | |
850 | } | |
3bd712e5 | 851 | |
b35684b8 JN |
852 | freq = panel->backlight.max; |
853 | if (panel->backlight.combination_mode) | |
854 | freq /= 0xff; | |
855 | ||
856 | ctl = freq << 17; | |
b6ab66aa | 857 | if (panel->backlight.combination_mode) |
b35684b8 JN |
858 | ctl |= BLM_LEGACY_MODE; |
859 | if (IS_PINEVIEW(dev) && panel->backlight.active_low_pwm) | |
860 | ctl |= BLM_POLARITY_PNV; | |
861 | ||
862 | I915_WRITE(BLC_PWM_CTL, ctl); | |
863 | POSTING_READ(BLC_PWM_CTL); | |
864 | ||
865 | /* XXX: combine this into above write? */ | |
3bd712e5 | 866 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
7bd688cd | 867 | } |
8ba2d185 | 868 | |
7bd688cd JN |
869 | static void i965_enable_backlight(struct intel_connector *connector) |
870 | { | |
871 | struct drm_device *dev = connector->base.dev; | |
872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 873 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 874 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 875 | u32 ctl, ctl2, freq; |
7bd688cd | 876 | |
b35684b8 JN |
877 | ctl2 = I915_READ(BLC_PWM_CTL2); |
878 | if (ctl2 & BLM_PWM_ENABLE) { | |
879 | WARN(1, "backlight already enabled\n"); | |
880 | ctl2 &= ~BLM_PWM_ENABLE; | |
881 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
882 | } | |
7bd688cd | 883 | |
b35684b8 JN |
884 | freq = panel->backlight.max; |
885 | if (panel->backlight.combination_mode) | |
886 | freq /= 0xff; | |
7bd688cd | 887 | |
b35684b8 JN |
888 | ctl = freq << 16; |
889 | I915_WRITE(BLC_PWM_CTL, ctl); | |
3bd712e5 | 890 | |
b35684b8 JN |
891 | ctl2 = BLM_PIPE(pipe); |
892 | if (panel->backlight.combination_mode) | |
893 | ctl2 |= BLM_COMBINATION_MODE; | |
894 | if (panel->backlight.active_low_pwm) | |
895 | ctl2 |= BLM_POLARITY_I965; | |
896 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
897 | POSTING_READ(BLC_PWM_CTL2); | |
898 | I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); | |
2e7eeeb5 JN |
899 | |
900 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
7bd688cd JN |
901 | } |
902 | ||
903 | static void vlv_enable_backlight(struct intel_connector *connector) | |
904 | { | |
905 | struct drm_device *dev = connector->base.dev; | |
906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 907 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 908 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 909 | u32 ctl, ctl2; |
7bd688cd | 910 | |
b35684b8 JN |
911 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
912 | if (ctl2 & BLM_PWM_ENABLE) { | |
913 | WARN(1, "backlight already enabled\n"); | |
914 | ctl2 &= ~BLM_PWM_ENABLE; | |
915 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
916 | } | |
7bd688cd | 917 | |
b35684b8 JN |
918 | ctl = panel->backlight.max << 16; |
919 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl); | |
7bd688cd | 920 | |
b35684b8 JN |
921 | /* XXX: combine this into above write? */ |
922 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
7bd688cd | 923 | |
b35684b8 JN |
924 | ctl2 = 0; |
925 | if (panel->backlight.active_low_pwm) | |
926 | ctl2 |= BLM_POLARITY_I965; | |
927 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
7bd688cd | 928 | POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); |
b35684b8 | 929 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); |
47356eb6 CW |
930 | } |
931 | ||
752aa88a | 932 | void intel_panel_enable_backlight(struct intel_connector *connector) |
47356eb6 | 933 | { |
752aa88a | 934 | struct drm_device *dev = connector->base.dev; |
47356eb6 | 935 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 936 | struct intel_panel *panel = &connector->panel; |
752aa88a | 937 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
8ba2d185 JN |
938 | unsigned long flags; |
939 | ||
dc5a4363 | 940 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
941 | return; |
942 | ||
6f2bcceb | 943 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
540b5d02 | 944 | |
58c68779 | 945 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
47356eb6 | 946 | |
f91c15e0 JN |
947 | WARN_ON(panel->backlight.max == 0); |
948 | ||
58c68779 | 949 | if (panel->backlight.level == 0) { |
f91c15e0 | 950 | panel->backlight.level = panel->backlight.max; |
58c68779 JN |
951 | if (panel->backlight.device) |
952 | panel->backlight.device->props.brightness = | |
6dda730e JN |
953 | scale_hw_to_user(connector, |
954 | panel->backlight.level, | |
955 | panel->backlight.device->props.max_brightness); | |
b6b3ba5b | 956 | } |
47356eb6 | 957 | |
3bd712e5 | 958 | dev_priv->display.enable_backlight(connector); |
58c68779 | 959 | panel->backlight.enabled = true; |
8ba2d185 | 960 | |
58c68779 | 961 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
47356eb6 CW |
962 | } |
963 | ||
912e8b12 | 964 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) |
db31af1d | 965 | static int intel_backlight_device_update_status(struct backlight_device *bd) |
aaa6fd2a | 966 | { |
752aa88a JB |
967 | struct intel_connector *connector = bl_get_data(bd); |
968 | struct drm_device *dev = connector->base.dev; | |
969 | ||
51fd371b | 970 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
540b5d02 CW |
971 | DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n", |
972 | bd->props.brightness, bd->props.max_brightness); | |
752aa88a | 973 | intel_panel_set_backlight(connector, bd->props.brightness, |
d6540632 | 974 | bd->props.max_brightness); |
51fd371b | 975 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
aaa6fd2a MG |
976 | return 0; |
977 | } | |
978 | ||
db31af1d | 979 | static int intel_backlight_device_get_brightness(struct backlight_device *bd) |
aaa6fd2a | 980 | { |
752aa88a JB |
981 | struct intel_connector *connector = bl_get_data(bd); |
982 | struct drm_device *dev = connector->base.dev; | |
c8c8fb33 | 983 | struct drm_i915_private *dev_priv = dev->dev_private; |
6dda730e | 984 | u32 hw_level; |
7bd688cd | 985 | int ret; |
752aa88a | 986 | |
c8c8fb33 | 987 | intel_runtime_pm_get(dev_priv); |
51fd371b | 988 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
6dda730e JN |
989 | |
990 | hw_level = intel_panel_get_backlight(connector); | |
991 | ret = scale_hw_to_user(connector, hw_level, bd->props.max_brightness); | |
992 | ||
51fd371b | 993 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
c8c8fb33 | 994 | intel_runtime_pm_put(dev_priv); |
752aa88a | 995 | |
7bd688cd | 996 | return ret; |
aaa6fd2a MG |
997 | } |
998 | ||
db31af1d JN |
999 | static const struct backlight_ops intel_backlight_device_ops = { |
1000 | .update_status = intel_backlight_device_update_status, | |
1001 | .get_brightness = intel_backlight_device_get_brightness, | |
aaa6fd2a MG |
1002 | }; |
1003 | ||
db31af1d | 1004 | static int intel_backlight_device_register(struct intel_connector *connector) |
aaa6fd2a | 1005 | { |
58c68779 | 1006 | struct intel_panel *panel = &connector->panel; |
aaa6fd2a | 1007 | struct backlight_properties props; |
aaa6fd2a | 1008 | |
58c68779 | 1009 | if (WARN_ON(panel->backlight.device)) |
dc652f90 JN |
1010 | return -ENODEV; |
1011 | ||
6dda730e | 1012 | WARN_ON(panel->backlight.max == 0); |
7bd688cd | 1013 | |
af437cfd | 1014 | memset(&props, 0, sizeof(props)); |
aaa6fd2a | 1015 | props.type = BACKLIGHT_RAW; |
6dda730e JN |
1016 | |
1017 | /* | |
1018 | * Note: Everything should work even if the backlight device max | |
1019 | * presented to the userspace is arbitrarily chosen. | |
1020 | */ | |
7bd688cd | 1021 | props.max_brightness = panel->backlight.max; |
6dda730e JN |
1022 | props.brightness = scale_hw_to_user(connector, |
1023 | panel->backlight.level, | |
1024 | props.max_brightness); | |
58c68779 JN |
1025 | |
1026 | /* | |
1027 | * Note: using the same name independent of the connector prevents | |
1028 | * registration of multiple backlight devices in the driver. | |
1029 | */ | |
1030 | panel->backlight.device = | |
aaa6fd2a | 1031 | backlight_device_register("intel_backlight", |
db31af1d JN |
1032 | connector->base.kdev, |
1033 | connector, | |
1034 | &intel_backlight_device_ops, &props); | |
aaa6fd2a | 1035 | |
58c68779 | 1036 | if (IS_ERR(panel->backlight.device)) { |
aaa6fd2a | 1037 | DRM_ERROR("Failed to register backlight: %ld\n", |
58c68779 JN |
1038 | PTR_ERR(panel->backlight.device)); |
1039 | panel->backlight.device = NULL; | |
aaa6fd2a MG |
1040 | return -ENODEV; |
1041 | } | |
aaa6fd2a MG |
1042 | return 0; |
1043 | } | |
1044 | ||
db31af1d | 1045 | static void intel_backlight_device_unregister(struct intel_connector *connector) |
aaa6fd2a | 1046 | { |
58c68779 JN |
1047 | struct intel_panel *panel = &connector->panel; |
1048 | ||
1049 | if (panel->backlight.device) { | |
1050 | backlight_device_unregister(panel->backlight.device); | |
1051 | panel->backlight.device = NULL; | |
dc652f90 | 1052 | } |
aaa6fd2a | 1053 | } |
db31af1d JN |
1054 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ |
1055 | static int intel_backlight_device_register(struct intel_connector *connector) | |
1056 | { | |
1057 | return 0; | |
1058 | } | |
1059 | static void intel_backlight_device_unregister(struct intel_connector *connector) | |
1060 | { | |
1061 | } | |
1062 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
1063 | ||
f91c15e0 JN |
1064 | /* |
1065 | * Note: The setup hooks can't assume pipe is set! | |
1066 | * | |
1067 | * XXX: Query mode clock or hardware clock and program PWM modulation frequency | |
1068 | * appropriately when it's 0. Use VBT and/or sane defaults. | |
1069 | */ | |
6dda730e JN |
1070 | static u32 get_backlight_min_vbt(struct intel_connector *connector) |
1071 | { | |
1072 | struct drm_device *dev = connector->base.dev; | |
1073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1074 | struct intel_panel *panel = &connector->panel; | |
1075 | ||
1076 | WARN_ON(panel->backlight.max == 0); | |
1077 | ||
1078 | /* vbt value is a coefficient in range [0..255] */ | |
1079 | return scale(dev_priv->vbt.backlight.min_brightness, 0, 255, | |
1080 | 0, panel->backlight.max); | |
1081 | } | |
1082 | ||
96ab4c70 | 1083 | static int bdw_setup_backlight(struct intel_connector *connector) |
aaa6fd2a | 1084 | { |
96ab4c70 | 1085 | struct drm_device *dev = connector->base.dev; |
aaa6fd2a | 1086 | struct drm_i915_private *dev_priv = dev->dev_private; |
96ab4c70 DV |
1087 | struct intel_panel *panel = &connector->panel; |
1088 | u32 pch_ctl1, pch_ctl2, val; | |
1089 | ||
1090 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
1091 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
1092 | ||
1093 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
1094 | panel->backlight.max = pch_ctl2 >> 16; | |
1095 | if (!panel->backlight.max) | |
1096 | return -ENODEV; | |
1097 | ||
6dda730e JN |
1098 | panel->backlight.min = get_backlight_min_vbt(connector); |
1099 | ||
96ab4c70 DV |
1100 | val = bdw_get_backlight(connector); |
1101 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1102 | ||
1103 | panel->backlight.enabled = (pch_ctl1 & BLM_PCH_PWM_ENABLE) && | |
1104 | panel->backlight.level != 0; | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
7bd688cd JN |
1109 | static int pch_setup_backlight(struct intel_connector *connector) |
1110 | { | |
636baebf JN |
1111 | struct drm_device *dev = connector->base.dev; |
1112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 1113 | struct intel_panel *panel = &connector->panel; |
636baebf | 1114 | u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; |
7bd688cd | 1115 | |
636baebf JN |
1116 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
1117 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
1118 | ||
1119 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
1120 | panel->backlight.max = pch_ctl2 >> 16; | |
7bd688cd JN |
1121 | if (!panel->backlight.max) |
1122 | return -ENODEV; | |
1123 | ||
6dda730e JN |
1124 | panel->backlight.min = get_backlight_min_vbt(connector); |
1125 | ||
7bd688cd JN |
1126 | val = pch_get_backlight(connector); |
1127 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1128 | ||
636baebf JN |
1129 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
1130 | panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) && | |
1131 | (pch_ctl1 & BLM_PCH_PWM_ENABLE) && panel->backlight.level != 0; | |
1132 | ||
7bd688cd JN |
1133 | return 0; |
1134 | } | |
1135 | ||
1136 | static int i9xx_setup_backlight(struct intel_connector *connector) | |
1137 | { | |
636baebf JN |
1138 | struct drm_device *dev = connector->base.dev; |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 1140 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
1141 | u32 ctl, val; |
1142 | ||
1143 | ctl = I915_READ(BLC_PWM_CTL); | |
1144 | ||
b6ab66aa | 1145 | if (IS_GEN2(dev) || IS_I915GM(dev) || IS_I945GM(dev)) |
636baebf JN |
1146 | panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; |
1147 | ||
1148 | if (IS_PINEVIEW(dev)) | |
1149 | panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV; | |
1150 | ||
1151 | panel->backlight.max = ctl >> 17; | |
1152 | if (panel->backlight.combination_mode) | |
1153 | panel->backlight.max *= 0xff; | |
7bd688cd | 1154 | |
7bd688cd JN |
1155 | if (!panel->backlight.max) |
1156 | return -ENODEV; | |
1157 | ||
6dda730e JN |
1158 | panel->backlight.min = get_backlight_min_vbt(connector); |
1159 | ||
7bd688cd JN |
1160 | val = i9xx_get_backlight(connector); |
1161 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1162 | ||
636baebf JN |
1163 | panel->backlight.enabled = panel->backlight.level != 0; |
1164 | ||
7bd688cd JN |
1165 | return 0; |
1166 | } | |
1167 | ||
1168 | static int i965_setup_backlight(struct intel_connector *connector) | |
1169 | { | |
636baebf JN |
1170 | struct drm_device *dev = connector->base.dev; |
1171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 1172 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
1173 | u32 ctl, ctl2, val; |
1174 | ||
1175 | ctl2 = I915_READ(BLC_PWM_CTL2); | |
1176 | panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE; | |
1177 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; | |
1178 | ||
1179 | ctl = I915_READ(BLC_PWM_CTL); | |
1180 | panel->backlight.max = ctl >> 16; | |
1181 | if (panel->backlight.combination_mode) | |
1182 | panel->backlight.max *= 0xff; | |
7bd688cd | 1183 | |
7bd688cd JN |
1184 | if (!panel->backlight.max) |
1185 | return -ENODEV; | |
1186 | ||
6dda730e JN |
1187 | panel->backlight.min = get_backlight_min_vbt(connector); |
1188 | ||
7bd688cd JN |
1189 | val = i9xx_get_backlight(connector); |
1190 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1191 | ||
636baebf JN |
1192 | panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) && |
1193 | panel->backlight.level != 0; | |
1194 | ||
7bd688cd JN |
1195 | return 0; |
1196 | } | |
1197 | ||
1198 | static int vlv_setup_backlight(struct intel_connector *connector) | |
1199 | { | |
1200 | struct drm_device *dev = connector->base.dev; | |
1201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1202 | struct intel_panel *panel = &connector->panel; | |
1203 | enum pipe pipe; | |
636baebf | 1204 | u32 ctl, ctl2, val; |
7bd688cd JN |
1205 | |
1206 | for_each_pipe(pipe) { | |
1207 | u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe)); | |
1208 | ||
1209 | /* Skip if the modulation freq is already set */ | |
1210 | if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK) | |
1211 | continue; | |
1212 | ||
1213 | cur_val &= BACKLIGHT_DUTY_CYCLE_MASK; | |
1214 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) | | |
1215 | cur_val); | |
1216 | } | |
1217 | ||
636baebf JN |
1218 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(PIPE_A)); |
1219 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; | |
1220 | ||
1221 | ctl = I915_READ(VLV_BLC_PWM_CTL(PIPE_A)); | |
1222 | panel->backlight.max = ctl >> 16; | |
7bd688cd JN |
1223 | if (!panel->backlight.max) |
1224 | return -ENODEV; | |
1225 | ||
6dda730e JN |
1226 | panel->backlight.min = get_backlight_min_vbt(connector); |
1227 | ||
7bd688cd JN |
1228 | val = _vlv_get_backlight(dev, PIPE_A); |
1229 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1230 | ||
636baebf JN |
1231 | panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) && |
1232 | panel->backlight.level != 0; | |
1233 | ||
7bd688cd JN |
1234 | return 0; |
1235 | } | |
1236 | ||
0657b6b1 | 1237 | int intel_panel_setup_backlight(struct drm_connector *connector) |
aaa6fd2a | 1238 | { |
db31af1d | 1239 | struct drm_device *dev = connector->dev; |
7bd688cd | 1240 | struct drm_i915_private *dev_priv = dev->dev_private; |
db31af1d | 1241 | struct intel_connector *intel_connector = to_intel_connector(connector); |
58c68779 | 1242 | struct intel_panel *panel = &intel_connector->panel; |
7bd688cd JN |
1243 | unsigned long flags; |
1244 | int ret; | |
db31af1d | 1245 | |
c675949e | 1246 | if (!dev_priv->vbt.backlight.present) { |
9c72cc6f SD |
1247 | if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) { |
1248 | DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n"); | |
1249 | } else { | |
1250 | DRM_DEBUG_KMS("no backlight present per VBT\n"); | |
1251 | return 0; | |
1252 | } | |
c675949e JN |
1253 | } |
1254 | ||
7bd688cd JN |
1255 | /* set level and max in panel struct */ |
1256 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); | |
1257 | ret = dev_priv->display.setup_backlight(intel_connector); | |
1258 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); | |
1259 | ||
1260 | if (ret) { | |
1261 | DRM_DEBUG_KMS("failed to setup backlight for connector %s\n", | |
c23cc417 | 1262 | connector->name); |
7bd688cd JN |
1263 | return ret; |
1264 | } | |
db31af1d | 1265 | |
db31af1d JN |
1266 | intel_backlight_device_register(intel_connector); |
1267 | ||
c91c9f32 JN |
1268 | panel->backlight.present = true; |
1269 | ||
c445b3b1 JN |
1270 | DRM_DEBUG_KMS("backlight initialized, %s, brightness %u/%u, " |
1271 | "sysfs interface %sregistered\n", | |
1272 | panel->backlight.enabled ? "enabled" : "disabled", | |
1273 | panel->backlight.level, panel->backlight.max, | |
1274 | panel->backlight.device ? "" : "not "); | |
1275 | ||
aaa6fd2a MG |
1276 | return 0; |
1277 | } | |
1278 | ||
db31af1d | 1279 | void intel_panel_destroy_backlight(struct drm_connector *connector) |
aaa6fd2a | 1280 | { |
db31af1d | 1281 | struct intel_connector *intel_connector = to_intel_connector(connector); |
c91c9f32 | 1282 | struct intel_panel *panel = &intel_connector->panel; |
db31af1d | 1283 | |
c91c9f32 | 1284 | panel->backlight.present = false; |
db31af1d | 1285 | intel_backlight_device_unregister(intel_connector); |
aaa6fd2a | 1286 | } |
1d508706 | 1287 | |
7bd688cd JN |
1288 | /* Set up chip specific backlight functions */ |
1289 | void intel_panel_init_backlight_funcs(struct drm_device *dev) | |
1290 | { | |
1291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1292 | ||
96ab4c70 DV |
1293 | if (IS_BROADWELL(dev)) { |
1294 | dev_priv->display.setup_backlight = bdw_setup_backlight; | |
1295 | dev_priv->display.enable_backlight = bdw_enable_backlight; | |
1296 | dev_priv->display.disable_backlight = pch_disable_backlight; | |
1297 | dev_priv->display.set_backlight = bdw_set_backlight; | |
1298 | dev_priv->display.get_backlight = bdw_get_backlight; | |
1299 | } else if (HAS_PCH_SPLIT(dev)) { | |
7bd688cd JN |
1300 | dev_priv->display.setup_backlight = pch_setup_backlight; |
1301 | dev_priv->display.enable_backlight = pch_enable_backlight; | |
1302 | dev_priv->display.disable_backlight = pch_disable_backlight; | |
1303 | dev_priv->display.set_backlight = pch_set_backlight; | |
1304 | dev_priv->display.get_backlight = pch_get_backlight; | |
7bd688cd JN |
1305 | } else if (IS_VALLEYVIEW(dev)) { |
1306 | dev_priv->display.setup_backlight = vlv_setup_backlight; | |
1307 | dev_priv->display.enable_backlight = vlv_enable_backlight; | |
1308 | dev_priv->display.disable_backlight = vlv_disable_backlight; | |
1309 | dev_priv->display.set_backlight = vlv_set_backlight; | |
1310 | dev_priv->display.get_backlight = vlv_get_backlight; | |
7bd688cd JN |
1311 | } else if (IS_GEN4(dev)) { |
1312 | dev_priv->display.setup_backlight = i965_setup_backlight; | |
1313 | dev_priv->display.enable_backlight = i965_enable_backlight; | |
1314 | dev_priv->display.disable_backlight = i965_disable_backlight; | |
1315 | dev_priv->display.set_backlight = i9xx_set_backlight; | |
1316 | dev_priv->display.get_backlight = i9xx_get_backlight; | |
7bd688cd JN |
1317 | } else { |
1318 | dev_priv->display.setup_backlight = i9xx_setup_backlight; | |
3bd712e5 JN |
1319 | dev_priv->display.enable_backlight = i9xx_enable_backlight; |
1320 | dev_priv->display.disable_backlight = i9xx_disable_backlight; | |
7bd688cd JN |
1321 | dev_priv->display.set_backlight = i9xx_set_backlight; |
1322 | dev_priv->display.get_backlight = i9xx_get_backlight; | |
7bd688cd JN |
1323 | } |
1324 | } | |
1325 | ||
dd06f90e | 1326 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1327 | struct drm_display_mode *fixed_mode, |
1328 | struct drm_display_mode *downclock_mode) | |
1d508706 | 1329 | { |
dd06f90e | 1330 | panel->fixed_mode = fixed_mode; |
4b6ed685 | 1331 | panel->downclock_mode = downclock_mode; |
dd06f90e | 1332 | |
1d508706 JN |
1333 | return 0; |
1334 | } | |
1335 | ||
1336 | void intel_panel_fini(struct intel_panel *panel) | |
1337 | { | |
dd06f90e JN |
1338 | struct intel_connector *intel_connector = |
1339 | container_of(panel, struct intel_connector, panel); | |
1340 | ||
1341 | if (panel->fixed_mode) | |
1342 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); | |
ec9ed197 VK |
1343 | |
1344 | if (panel->downclock_mode) | |
1345 | drm_mode_destroy(intel_connector->base.dev, | |
1346 | panel->downclock_mode); | |
1d508706 | 1347 | } |