drm/i915: make asle notifications update backlight on all connectors
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW
1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP
31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
7bd90909 33#include <linux/moduleparam.h>
1d8e1c75
CW
34#include "intel_drv.h"
35
ba3820ad
TI
36#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
37
1d8e1c75 38void
4c6df4b4 39intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1d8e1c75
CW
40 struct drm_display_mode *adjusted_mode)
41{
4c6df4b4 42 drm_mode_copy(adjusted_mode, fixed_mode);
a52690e4
ID
43
44 drm_mode_set_crtcinfo(adjusted_mode, 0);
1d8e1c75
CW
45}
46
47/* adjusted_mode has been preset to be the panel's fixed mode */
48void
b074cec8
JB
49intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
50 struct intel_crtc_config *pipe_config,
51 int fitting_mode)
1d8e1c75 52{
37327abd 53 struct drm_display_mode *adjusted_mode;
1d8e1c75
CW
54 int x, y, width, height;
55
b074cec8
JB
56 adjusted_mode = &pipe_config->adjusted_mode;
57
1d8e1c75
CW
58 x = y = width = height = 0;
59
60 /* Native modes don't need fitting */
37327abd
VS
61 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
62 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
1d8e1c75
CW
63 goto done;
64
65 switch (fitting_mode) {
66 case DRM_MODE_SCALE_CENTER:
37327abd
VS
67 width = pipe_config->pipe_src_w;
68 height = pipe_config->pipe_src_h;
1d8e1c75
CW
69 x = (adjusted_mode->hdisplay - width + 1)/2;
70 y = (adjusted_mode->vdisplay - height + 1)/2;
71 break;
72
73 case DRM_MODE_SCALE_ASPECT:
74 /* Scale but preserve the aspect ratio */
75 {
9084e7d2
DV
76 u32 scaled_width = adjusted_mode->hdisplay
77 * pipe_config->pipe_src_h;
78 u32 scaled_height = pipe_config->pipe_src_w
79 * adjusted_mode->vdisplay;
1d8e1c75 80 if (scaled_width > scaled_height) { /* pillar */
37327abd 81 width = scaled_height / pipe_config->pipe_src_h;
302983e9 82 if (width & 1)
0206e353 83 width++;
1d8e1c75
CW
84 x = (adjusted_mode->hdisplay - width + 1) / 2;
85 y = 0;
86 height = adjusted_mode->vdisplay;
87 } else if (scaled_width < scaled_height) { /* letter */
37327abd 88 height = scaled_width / pipe_config->pipe_src_w;
302983e9
AJ
89 if (height & 1)
90 height++;
1d8e1c75
CW
91 y = (adjusted_mode->vdisplay - height + 1) / 2;
92 x = 0;
93 width = adjusted_mode->hdisplay;
94 } else {
95 x = y = 0;
96 width = adjusted_mode->hdisplay;
97 height = adjusted_mode->vdisplay;
98 }
99 }
100 break;
101
1d8e1c75
CW
102 case DRM_MODE_SCALE_FULLSCREEN:
103 x = y = 0;
104 width = adjusted_mode->hdisplay;
105 height = adjusted_mode->vdisplay;
106 break;
ab3e67f4
JB
107
108 default:
109 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
110 return;
1d8e1c75
CW
111 }
112
113done:
b074cec8
JB
114 pipe_config->pch_pfit.pos = (x << 16) | y;
115 pipe_config->pch_pfit.size = (width << 16) | height;
fd4daa9c 116 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
1d8e1c75 117}
a9573556 118
2dd24552
JB
119static void
120centre_horizontally(struct drm_display_mode *mode,
121 int width)
122{
123 u32 border, sync_pos, blank_width, sync_width;
124
125 /* keep the hsync and hblank widths constant */
126 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
127 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
128 sync_pos = (blank_width - sync_width + 1) / 2;
129
130 border = (mode->hdisplay - width + 1) / 2;
131 border += border & 1; /* make the border even */
132
133 mode->crtc_hdisplay = width;
134 mode->crtc_hblank_start = width + border;
135 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
136
137 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
138 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
139}
140
141static void
142centre_vertically(struct drm_display_mode *mode,
143 int height)
144{
145 u32 border, sync_pos, blank_width, sync_width;
146
147 /* keep the vsync and vblank widths constant */
148 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
149 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
150 sync_pos = (blank_width - sync_width + 1) / 2;
151
152 border = (mode->vdisplay - height + 1) / 2;
153
154 mode->crtc_vdisplay = height;
155 mode->crtc_vblank_start = height + border;
156 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
157
158 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
159 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
160}
161
162static inline u32 panel_fitter_scaling(u32 source, u32 target)
163{
164 /*
165 * Floating point operation is not supported. So the FACTOR
166 * is defined, which can avoid the floating point computation
167 * when calculating the panel ratio.
168 */
169#define ACCURACY 12
170#define FACTOR (1 << ACCURACY)
171 u32 ratio = source * FACTOR / target;
172 return (FACTOR * ratio + FACTOR/2) / FACTOR;
173}
174
9084e7d2
DV
175static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
176 u32 *pfit_control)
177{
178 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
179 u32 scaled_width = adjusted_mode->hdisplay *
180 pipe_config->pipe_src_h;
181 u32 scaled_height = pipe_config->pipe_src_w *
182 adjusted_mode->vdisplay;
183
184 /* 965+ is easy, it does everything in hw */
185 if (scaled_width > scaled_height)
186 *pfit_control |= PFIT_ENABLE |
187 PFIT_SCALING_PILLAR;
188 else if (scaled_width < scaled_height)
189 *pfit_control |= PFIT_ENABLE |
190 PFIT_SCALING_LETTER;
191 else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
192 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
193}
194
195static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
196 u32 *pfit_control, u32 *pfit_pgm_ratios,
197 u32 *border)
198{
199 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
200 u32 scaled_width = adjusted_mode->hdisplay *
201 pipe_config->pipe_src_h;
202 u32 scaled_height = pipe_config->pipe_src_w *
203 adjusted_mode->vdisplay;
204 u32 bits;
205
206 /*
207 * For earlier chips we have to calculate the scaling
208 * ratio by hand and program it into the
209 * PFIT_PGM_RATIO register
210 */
211 if (scaled_width > scaled_height) { /* pillar */
212 centre_horizontally(adjusted_mode,
213 scaled_height /
214 pipe_config->pipe_src_h);
215
216 *border = LVDS_BORDER_ENABLE;
217 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
218 bits = panel_fitter_scaling(pipe_config->pipe_src_h,
219 adjusted_mode->vdisplay);
220
221 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
222 bits << PFIT_VERT_SCALE_SHIFT);
223 *pfit_control |= (PFIT_ENABLE |
224 VERT_INTERP_BILINEAR |
225 HORIZ_INTERP_BILINEAR);
226 }
227 } else if (scaled_width < scaled_height) { /* letter */
228 centre_vertically(adjusted_mode,
229 scaled_width /
230 pipe_config->pipe_src_w);
231
232 *border = LVDS_BORDER_ENABLE;
233 if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
234 bits = panel_fitter_scaling(pipe_config->pipe_src_w,
235 adjusted_mode->hdisplay);
236
237 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
238 bits << PFIT_VERT_SCALE_SHIFT);
239 *pfit_control |= (PFIT_ENABLE |
240 VERT_INTERP_BILINEAR |
241 HORIZ_INTERP_BILINEAR);
242 }
243 } else {
244 /* Aspects match, Let hw scale both directions */
245 *pfit_control |= (PFIT_ENABLE |
246 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
247 VERT_INTERP_BILINEAR |
248 HORIZ_INTERP_BILINEAR);
249 }
250}
251
2dd24552
JB
252void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
253 struct intel_crtc_config *pipe_config,
254 int fitting_mode)
255{
256 struct drm_device *dev = intel_crtc->base.dev;
2dd24552 257 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
37327abd 258 struct drm_display_mode *adjusted_mode;
2dd24552 259
2dd24552
JB
260 adjusted_mode = &pipe_config->adjusted_mode;
261
262 /* Native modes don't need fitting */
37327abd
VS
263 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
264 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
2dd24552
JB
265 goto out;
266
267 switch (fitting_mode) {
268 case DRM_MODE_SCALE_CENTER:
269 /*
270 * For centered modes, we have to calculate border widths &
271 * heights and modify the values programmed into the CRTC.
272 */
37327abd
VS
273 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
274 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
2dd24552
JB
275 border = LVDS_BORDER_ENABLE;
276 break;
277 case DRM_MODE_SCALE_ASPECT:
278 /* Scale but preserve the aspect ratio */
9084e7d2
DV
279 if (INTEL_INFO(dev)->gen >= 4)
280 i965_scale_aspect(pipe_config, &pfit_control);
281 else
282 i9xx_scale_aspect(pipe_config, &pfit_control,
283 &pfit_pgm_ratios, &border);
2dd24552 284 break;
2dd24552
JB
285 case DRM_MODE_SCALE_FULLSCREEN:
286 /*
287 * Full scaling, even if it changes the aspect ratio.
288 * Fortunately this is all done for us in hw.
289 */
37327abd
VS
290 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
291 pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
2dd24552
JB
292 pfit_control |= PFIT_ENABLE;
293 if (INTEL_INFO(dev)->gen >= 4)
294 pfit_control |= PFIT_SCALING_AUTO;
295 else
296 pfit_control |= (VERT_AUTO_SCALE |
297 VERT_INTERP_BILINEAR |
298 HORIZ_AUTO_SCALE |
299 HORIZ_INTERP_BILINEAR);
300 }
301 break;
ab3e67f4
JB
302 default:
303 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
304 return;
2dd24552
JB
305 }
306
307 /* 965+ wants fuzzy fitting */
308 /* FIXME: handle multiple panels by failing gracefully */
309 if (INTEL_INFO(dev)->gen >= 4)
310 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
311 PFIT_FILTER_FUZZY);
312
313out:
314 if ((pfit_control & PFIT_ENABLE) == 0) {
315 pfit_control = 0;
316 pfit_pgm_ratios = 0;
317 }
318
319 /* Make sure pre-965 set dither correctly for 18bpp panels. */
320 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
321 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
322
2deefda5
DV
323 pipe_config->gmch_pfit.control = pfit_control;
324 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
68fc8742 325 pipe_config->gmch_pfit.lvds_border_bits = border;
2dd24552
JB
326}
327
ba3820ad
TI
328static int is_backlight_combination_mode(struct drm_device *dev)
329{
330 struct drm_i915_private *dev_priv = dev->dev_private;
331
d9c638d5 332 if (IS_GEN4(dev))
ba3820ad
TI
333 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
334
335 if (IS_GEN2(dev))
336 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
337
338 return 0;
339}
340
d6540632
JN
341/* XXX: query mode clock or hardware clock and program max PWM appropriately
342 * when it's 0.
343 */
752aa88a 344static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
0b0b053a 345{
bfd7590d 346 struct drm_i915_private *dev_priv = dev->dev_private;
0b0b053a
CW
347 u32 val;
348
58c68779 349 WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight_lock));
8ba2d185 350
0b0b053a
CW
351 /* Restore the CTL value if it lost, e.g. GPU reset */
352
353 if (HAS_PCH_SPLIT(dev_priv->dev)) {
354 val = I915_READ(BLC_PWM_PCH_CTL2);
f4c956ad
DV
355 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
356 dev_priv->regfile.saveBLC_PWM_CTL2 = val;
0b0b053a 357 } else if (val == 0) {
f4c956ad 358 val = dev_priv->regfile.saveBLC_PWM_CTL2;
bfd7590d 359 I915_WRITE(BLC_PWM_PCH_CTL2, val);
0b0b053a 360 }
07bf139b
JB
361 } else if (IS_VALLEYVIEW(dev)) {
362 val = I915_READ(VLV_BLC_PWM_CTL(pipe));
363 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
364 dev_priv->regfile.saveBLC_PWM_CTL = val;
365 dev_priv->regfile.saveBLC_PWM_CTL2 =
366 I915_READ(VLV_BLC_PWM_CTL2(pipe));
367 } else if (val == 0) {
368 val = dev_priv->regfile.saveBLC_PWM_CTL;
369 I915_WRITE(VLV_BLC_PWM_CTL(pipe), val);
370 I915_WRITE(VLV_BLC_PWM_CTL2(pipe),
371 dev_priv->regfile.saveBLC_PWM_CTL2);
372 }
373
374 if (!val)
375 val = 0x0f42ffff;
0b0b053a
CW
376 } else {
377 val = I915_READ(BLC_PWM_CTL);
f4c956ad
DV
378 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
379 dev_priv->regfile.saveBLC_PWM_CTL = val;
bfd7590d
JN
380 if (INTEL_INFO(dev)->gen >= 4)
381 dev_priv->regfile.saveBLC_PWM_CTL2 =
382 I915_READ(BLC_PWM_CTL2);
0b0b053a 383 } else if (val == 0) {
f4c956ad 384 val = dev_priv->regfile.saveBLC_PWM_CTL;
bfd7590d
JN
385 I915_WRITE(BLC_PWM_CTL, val);
386 if (INTEL_INFO(dev)->gen >= 4)
387 I915_WRITE(BLC_PWM_CTL2,
388 dev_priv->regfile.saveBLC_PWM_CTL2);
0b0b053a
CW
389 }
390 }
391
392 return val;
393}
394
752aa88a
JB
395static u32 intel_panel_get_max_backlight(struct drm_device *dev,
396 enum pipe pipe)
a9573556 397{
a9573556
CW
398 u32 max;
399
752aa88a 400 max = i915_read_blc_pwm_ctl(dev, pipe);
0b0b053a 401
a9573556 402 if (HAS_PCH_SPLIT(dev)) {
0b0b053a 403 max >>= 16;
a9573556 404 } else {
ca88479c 405 if (INTEL_INFO(dev)->gen < 4)
a9573556 406 max >>= 17;
ca88479c 407 else
a9573556 408 max >>= 16;
ba3820ad
TI
409
410 if (is_backlight_combination_mode(dev))
411 max *= 0xff;
a9573556
CW
412 }
413
a9573556 414 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
d6540632 415
a9573556
CW
416 return max;
417}
418
4dca20ef
CE
419static int i915_panel_invert_brightness;
420MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
421 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
7bd90909
CE
422 "report PCI device ID, subsystem vendor and subsystem device ID "
423 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
424 "It will then be included in an upcoming module version.");
4dca20ef 425module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
752aa88a
JB
426static u32 intel_panel_compute_brightness(struct drm_device *dev,
427 enum pipe pipe, u32 val)
7bd90909 428{
4dca20ef
CE
429 struct drm_i915_private *dev_priv = dev->dev_private;
430
431 if (i915_panel_invert_brightness < 0)
432 return val;
433
434 if (i915_panel_invert_brightness > 0 ||
d6540632 435 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
752aa88a 436 u32 max = intel_panel_get_max_backlight(dev, pipe);
d6540632
JN
437 if (max)
438 return max - val;
439 }
7bd90909
CE
440
441 return val;
442}
443
752aa88a
JB
444static u32 intel_panel_get_backlight(struct drm_device *dev,
445 enum pipe pipe)
a9573556
CW
446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 u32 val;
8ba2d185 449 unsigned long flags;
07bf139b 450 int reg;
8ba2d185 451
58c68779 452 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
a9573556
CW
453
454 if (HAS_PCH_SPLIT(dev)) {
455 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
456 } else {
07bf139b
JB
457 if (IS_VALLEYVIEW(dev))
458 reg = VLV_BLC_PWM_CTL(pipe);
459 else
460 reg = BLC_PWM_CTL;
461
462 val = I915_READ(reg) & BACKLIGHT_DUTY_CYCLE_MASK;
ca88479c 463 if (INTEL_INFO(dev)->gen < 4)
a9573556 464 val >>= 1;
ba3820ad 465
0206e353 466 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI
467 u8 lbpc;
468
ba3820ad
TI
469 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
470 val *= lbpc;
471 }
a9573556
CW
472 }
473
752aa88a 474 val = intel_panel_compute_brightness(dev, pipe, val);
8ba2d185 475
58c68779 476 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
8ba2d185 477
a9573556
CW
478 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
479 return val;
480}
481
482static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
483{
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
486 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
487}
488
9084e7d2 489static void intel_panel_actually_set_backlight(struct drm_device *dev,
752aa88a 490 enum pipe pipe, u32 level)
a9573556
CW
491{
492 struct drm_i915_private *dev_priv = dev->dev_private;
493 u32 tmp;
07bf139b 494 int reg;
a9573556
CW
495
496 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
752aa88a 497 level = intel_panel_compute_brightness(dev, pipe, level);
a9573556
CW
498
499 if (HAS_PCH_SPLIT(dev))
500 return intel_pch_panel_set_backlight(dev, level);
ba3820ad 501
0206e353 502 if (is_backlight_combination_mode(dev)) {
752aa88a 503 u32 max = intel_panel_get_max_backlight(dev, pipe);
ba3820ad
TI
504 u8 lbpc;
505
d6540632
JN
506 /* we're screwed, but keep behaviour backwards compatible */
507 if (!max)
508 max = 1;
509
ba3820ad
TI
510 lbpc = level * 0xfe / max + 1;
511 level /= lbpc;
512 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
513 }
514
07bf139b
JB
515 if (IS_VALLEYVIEW(dev))
516 reg = VLV_BLC_PWM_CTL(pipe);
517 else
518 reg = BLC_PWM_CTL;
519
520 tmp = I915_READ(reg);
a726915c 521 if (INTEL_INFO(dev)->gen < 4)
a9573556 522 level <<= 1;
ca88479c 523 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
07bf139b 524 I915_WRITE(reg, tmp | level);
a9573556 525}
47356eb6 526
d6540632 527/* set backlight brightness to level in range [0..max] */
752aa88a
JB
528void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
529 u32 max)
47356eb6 530{
752aa88a 531 struct drm_device *dev = connector->base.dev;
47356eb6 532 struct drm_i915_private *dev_priv = dev->dev_private;
58c68779 533 struct intel_panel *panel = &connector->panel;
752aa88a 534 enum pipe pipe = intel_get_pipe_from_connector(connector);
d6540632 535 u32 freq;
8ba2d185
JN
536 unsigned long flags;
537
752aa88a
JB
538 if (pipe == INVALID_PIPE)
539 return;
540
58c68779 541 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
d6540632 542
752aa88a 543 freq = intel_panel_get_max_backlight(dev, pipe);
d6540632
JN
544 if (!freq) {
545 /* we are screwed, bail out */
8ba2d185 546 goto out;
d6540632
JN
547 }
548
22505b82
AL
549 /* scale to hardware, but be careful to not overflow */
550 if (freq < max)
551 level = level * freq / max;
552 else
553 level = freq / max * level;
47356eb6 554
58c68779
JN
555 panel->backlight.level = level;
556 if (panel->backlight.device)
557 panel->backlight.device->props.brightness = level;
b6b3ba5b 558
58c68779 559 if (panel->backlight.enabled)
752aa88a 560 intel_panel_actually_set_backlight(dev, pipe, level);
8ba2d185 561out:
58c68779 562 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
f52c619a
TI
563}
564
752aa88a 565void intel_panel_disable_backlight(struct intel_connector *connector)
f52c619a 566{
752aa88a 567 struct drm_device *dev = connector->base.dev;
f52c619a 568 struct drm_i915_private *dev_priv = dev->dev_private;
58c68779 569 struct intel_panel *panel = &connector->panel;
752aa88a 570 enum pipe pipe = intel_get_pipe_from_connector(connector);
8ba2d185
JN
571 unsigned long flags;
572
752aa88a
JB
573 if (pipe == INVALID_PIPE)
574 return;
575
3f577573
JN
576 /*
577 * Do not disable backlight on the vgaswitcheroo path. When switching
578 * away from i915, the other client may depend on i915 to handle the
579 * backlight. This will leave the backlight on unnecessarily when
580 * another client is not activated.
581 */
582 if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
583 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
584 return;
585 }
586
58c68779 587 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
47356eb6 588
58c68779 589 panel->backlight.enabled = false;
752aa88a 590 intel_panel_actually_set_backlight(dev, pipe, 0);
24ded204
DV
591
592 if (INTEL_INFO(dev)->gen >= 4) {
a4f32fc3 593 uint32_t reg, tmp;
24ded204 594
07bf139b
JB
595 if (HAS_PCH_SPLIT(dev))
596 reg = BLC_PWM_CPU_CTL2;
597 else if (IS_VALLEYVIEW(dev))
598 reg = VLV_BLC_PWM_CTL2(pipe);
599 else
600 reg = BLC_PWM_CTL2;
24ded204
DV
601
602 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
a4f32fc3
PZ
603
604 if (HAS_PCH_SPLIT(dev)) {
605 tmp = I915_READ(BLC_PWM_PCH_CTL1);
606 tmp &= ~BLM_PCH_PWM_ENABLE;
607 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
608 }
24ded204 609 }
8ba2d185 610
58c68779 611 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
47356eb6
CW
612}
613
752aa88a 614void intel_panel_enable_backlight(struct intel_connector *connector)
47356eb6 615{
752aa88a 616 struct drm_device *dev = connector->base.dev;
47356eb6 617 struct drm_i915_private *dev_priv = dev->dev_private;
58c68779 618 struct intel_panel *panel = &connector->panel;
752aa88a 619 enum pipe pipe = intel_get_pipe_from_connector(connector);
35ffda48
JN
620 enum transcoder cpu_transcoder =
621 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
8ba2d185
JN
622 unsigned long flags;
623
752aa88a
JB
624 if (pipe == INVALID_PIPE)
625 return;
626
6f2bcceb 627 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
540b5d02 628
58c68779 629 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
47356eb6 630
58c68779
JN
631 if (panel->backlight.level == 0) {
632 panel->backlight.level = intel_panel_get_max_backlight(dev,
633 pipe);
634 if (panel->backlight.device)
635 panel->backlight.device->props.brightness =
636 panel->backlight.level;
b6b3ba5b 637 }
47356eb6 638
24ded204
DV
639 if (INTEL_INFO(dev)->gen >= 4) {
640 uint32_t reg, tmp;
641
07bf139b
JB
642 if (HAS_PCH_SPLIT(dev))
643 reg = BLC_PWM_CPU_CTL2;
644 else if (IS_VALLEYVIEW(dev))
645 reg = VLV_BLC_PWM_CTL2(pipe);
646 else
647 reg = BLC_PWM_CTL2;
24ded204
DV
648
649 tmp = I915_READ(reg);
650
651 /* Note that this can also get called through dpms changes. And
652 * we don't track the backlight dpms state, hence check whether
653 * we have to do anything first. */
654 if (tmp & BLM_PWM_ENABLE)
770c1231 655 goto set_level;
24ded204 656
7eb552ae 657 if (INTEL_INFO(dev)->num_pipes == 3)
24ded204
DV
658 tmp &= ~BLM_PIPE_SELECT_IVB;
659 else
660 tmp &= ~BLM_PIPE_SELECT;
661
35ffda48
JN
662 if (cpu_transcoder == TRANSCODER_EDP)
663 tmp |= BLM_TRANSCODER_EDP;
664 else
665 tmp |= BLM_PIPE(cpu_transcoder);
24ded204
DV
666 tmp &= ~BLM_PWM_ENABLE;
667
668 I915_WRITE(reg, tmp);
669 POSTING_READ(reg);
670 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
a4f32fc3 671
e85843be
KM
672 if (HAS_PCH_SPLIT(dev) &&
673 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
a4f32fc3
PZ
674 tmp = I915_READ(BLC_PWM_PCH_CTL1);
675 tmp |= BLM_PCH_PWM_ENABLE;
676 tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
677 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
678 }
24ded204 679 }
770c1231
TI
680
681set_level:
b1289371
DV
682 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
683 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
684 * registers are set.
770c1231 685 */
58c68779 686 panel->backlight.enabled = true;
752aa88a 687 intel_panel_actually_set_backlight(dev, pipe,
58c68779 688 panel->backlight.level);
8ba2d185 689
58c68779 690 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
47356eb6
CW
691}
692
afc85b9d
JB
693/* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */
694static void intel_panel_init_backlight_regs(struct drm_device *dev)
695{
696 struct drm_i915_private *dev_priv = dev->dev_private;
697
698 if (IS_VALLEYVIEW(dev)) {
07bf139b
JB
699 enum pipe pipe;
700
701 for_each_pipe(pipe) {
702 u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe));
703
704 /* Skip if the modulation freq is already set */
705 if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK)
706 continue;
707
708 cur_val &= BACKLIGHT_DUTY_CYCLE_MASK;
709 I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) |
710 cur_val);
711 }
afc85b9d
JB
712 }
713}
714
fe16d949
CW
715enum drm_connector_status
716intel_panel_detect(struct drm_device *dev)
717{
718 struct drm_i915_private *dev_priv = dev->dev_private;
719
720 /* Assume that the BIOS does not lie through the OpRegion... */
a726915c 721 if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
fe16d949
CW
722 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
723 connector_status_connected :
724 connector_status_disconnected;
a726915c 725 }
fe16d949 726
a726915c
DV
727 switch (i915_panel_ignore_lid) {
728 case -2:
729 return connector_status_connected;
730 case -1:
731 return connector_status_disconnected;
732 default:
733 return connector_status_unknown;
734 }
fe16d949 735}
aaa6fd2a 736
912e8b12 737#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
db31af1d 738static int intel_backlight_device_update_status(struct backlight_device *bd)
aaa6fd2a 739{
752aa88a
JB
740 struct intel_connector *connector = bl_get_data(bd);
741 struct drm_device *dev = connector->base.dev;
742
743 mutex_lock(&dev->mode_config.mutex);
540b5d02
CW
744 DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n",
745 bd->props.brightness, bd->props.max_brightness);
752aa88a 746 intel_panel_set_backlight(connector, bd->props.brightness,
d6540632 747 bd->props.max_brightness);
752aa88a 748 mutex_unlock(&dev->mode_config.mutex);
aaa6fd2a
MG
749 return 0;
750}
751
db31af1d 752static int intel_backlight_device_get_brightness(struct backlight_device *bd)
aaa6fd2a 753{
752aa88a
JB
754 struct intel_connector *connector = bl_get_data(bd);
755 struct drm_device *dev = connector->base.dev;
756 enum pipe pipe;
757
758 mutex_lock(&dev->mode_config.mutex);
759 pipe = intel_get_pipe_from_connector(connector);
760 mutex_unlock(&dev->mode_config.mutex);
761 if (pipe == INVALID_PIPE)
762 return 0;
763
764 return intel_panel_get_backlight(connector->base.dev, pipe);
aaa6fd2a
MG
765}
766
db31af1d
JN
767static const struct backlight_ops intel_backlight_device_ops = {
768 .update_status = intel_backlight_device_update_status,
769 .get_brightness = intel_backlight_device_get_brightness,
aaa6fd2a
MG
770};
771
db31af1d 772static int intel_backlight_device_register(struct intel_connector *connector)
aaa6fd2a 773{
db31af1d 774 struct drm_device *dev = connector->base.dev;
aaa6fd2a 775 struct drm_i915_private *dev_priv = dev->dev_private;
58c68779 776 struct intel_panel *panel = &connector->panel;
aaa6fd2a 777 struct backlight_properties props;
8ba2d185 778 unsigned long flags;
aaa6fd2a 779
58c68779 780 if (WARN_ON(panel->backlight.device))
dc652f90
JN
781 return -ENODEV;
782
af437cfd 783 memset(&props, 0, sizeof(props));
aaa6fd2a 784 props.type = BACKLIGHT_RAW;
58c68779 785 props.brightness = panel->backlight.level;
8ba2d185 786
58c68779 787 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
752aa88a 788 props.max_brightness = intel_panel_get_max_backlight(dev, 0);
58c68779 789 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
8ba2d185 790
28dcc2d6 791 if (props.max_brightness == 0) {
e86b6185 792 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
28dcc2d6
JN
793 return -ENODEV;
794 }
58c68779
JN
795
796 /*
797 * Note: using the same name independent of the connector prevents
798 * registration of multiple backlight devices in the driver.
799 */
800 panel->backlight.device =
aaa6fd2a 801 backlight_device_register("intel_backlight",
db31af1d
JN
802 connector->base.kdev,
803 connector,
804 &intel_backlight_device_ops, &props);
aaa6fd2a 805
58c68779 806 if (IS_ERR(panel->backlight.device)) {
aaa6fd2a 807 DRM_ERROR("Failed to register backlight: %ld\n",
58c68779
JN
808 PTR_ERR(panel->backlight.device));
809 panel->backlight.device = NULL;
aaa6fd2a
MG
810 return -ENODEV;
811 }
aaa6fd2a
MG
812 return 0;
813}
814
db31af1d 815static void intel_backlight_device_unregister(struct intel_connector *connector)
aaa6fd2a 816{
58c68779
JN
817 struct intel_panel *panel = &connector->panel;
818
819 if (panel->backlight.device) {
820 backlight_device_unregister(panel->backlight.device);
821 panel->backlight.device = NULL;
dc652f90 822 }
aaa6fd2a 823}
db31af1d
JN
824#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
825static int intel_backlight_device_register(struct intel_connector *connector)
826{
827 return 0;
828}
829static void intel_backlight_device_unregister(struct intel_connector *connector)
830{
831}
832#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
833
0657b6b1 834int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 835{
db31af1d 836 struct drm_device *dev = connector->dev;
db31af1d 837 struct intel_connector *intel_connector = to_intel_connector(connector);
58c68779 838 struct intel_panel *panel = &intel_connector->panel;
db31af1d
JN
839
840 intel_panel_init_backlight_regs(dev);
841
58c68779
JN
842 panel->backlight.level = intel_panel_get_backlight(dev, 0);
843 panel->backlight.enabled = panel->backlight.level != 0;
db31af1d
JN
844
845 intel_backlight_device_register(intel_connector);
846
c91c9f32
JN
847 panel->backlight.present = true;
848
aaa6fd2a
MG
849 return 0;
850}
851
db31af1d 852void intel_panel_destroy_backlight(struct drm_connector *connector)
aaa6fd2a 853{
db31af1d 854 struct intel_connector *intel_connector = to_intel_connector(connector);
c91c9f32 855 struct intel_panel *panel = &intel_connector->panel;
db31af1d 856
c91c9f32 857 panel->backlight.present = false;
db31af1d 858 intel_backlight_device_unregister(intel_connector);
aaa6fd2a 859}
1d508706 860
dd06f90e
JN
861int intel_panel_init(struct intel_panel *panel,
862 struct drm_display_mode *fixed_mode)
1d508706 863{
dd06f90e
JN
864 panel->fixed_mode = fixed_mode;
865
1d508706
JN
866 return 0;
867}
868
869void intel_panel_fini(struct intel_panel *panel)
870{
dd06f90e
JN
871 struct intel_connector *intel_connector =
872 container_of(panel, struct intel_connector, panel);
873
874 if (panel->fixed_mode)
875 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
1d508706 876}
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