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drm/i915: Fix DVO 2x clock enable on 830M
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0
ED		 97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
7f2cf220 99 int i;
159f9875 100 u32 fbc_ctl;
85208be0 101
5c3fe8b0 102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
42a430f5
VS		 106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
159f9875
VS		 116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
85208be0
ED		 125
126 /* enable it... */
993495ae
VS		 127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
5cd5410e 136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 138}
139
1fa61106 140static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145}
146
993495ae 147static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 148{
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 151 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 154 u32 dpfc_ctl;
155
3fa2e0ee
VS		 156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 162
85208be0
ED		 163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
fe74c1a5 166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 167
84f44ce7 168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 169}
170
1fa61106 171static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 172{
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184}
185
1fa61106 186static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191}
192
193static void sandybridge_blit_fbc_update(struct drm_device *dev)
194{
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
940aece4
D		 199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 203
85208be0
ED		 204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 214
940aece4 215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 216}
217
993495ae 218static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 219{
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 222 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 225 u32 dpfc_ctl;
226
46f3dab9 227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee 228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
3fa2e0ee 237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 238 break;
239 case 1:
3fa2e0ee 240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 241 break;
242 }
d629336b
VS		 243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
85208be0 246
85208be0 247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
84f44ce7 259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 260}
261
1fa61106 262static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 263{
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275}
276
1fa61106 277static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282}
283
993495ae 284static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 285{
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 288 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
abe959c7 290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 291 u32 dpfc_ctl;
abe959c7 292
3fa2e0ee
VS		 293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
3fa2e0ee 303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 304 break;
305 case 1:
3fa2e0ee 306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 307 break;
308 }
309
3fa2e0ee
VS		 310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
da46f936
RV		 312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
3fa2e0ee 315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 316
891348b2 317 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
28554164 322 } else {
2adb6db8 323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
891348b2 327 }
b74ea102 328
abe959c7
RV		 329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
b19870ee 335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 336}
337
85208be0
ED		 338bool intel_fbc_enabled(struct drm_device *dev)
339{
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346}
347
c5ad011d
RV		 348void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
351
352 if (!IS_GEN8(dev))
353 return;
354
355 I915_WRITE(MSG_FBC_REND_STATE, value);
356}
357
85208be0
ED		 358static void intel_fbc_work_fn(struct work_struct *__work)
359{
360 struct intel_fbc_work *work =
361 container_of(to_delayed_work(__work),
362 struct intel_fbc_work, work);
363 struct drm_device *dev = work->crtc->dev;
364 struct drm_i915_private *dev_priv = dev->dev_private;
365
366 mutex_lock(&dev->struct_mutex);
5c3fe8b0 367 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 368 /* Double check that we haven't switched fb without cancelling
369 * the prior work.
370 */
f4510a27 371 if (work->crtc->primary->fb == work->fb) {
993495ae 372 dev_priv->display.enable_fbc(work->crtc);
85208be0 373
5c3fe8b0 374 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 375 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 376 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 377 }
378
5c3fe8b0 379 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 380 }
381 mutex_unlock(&dev->struct_mutex);
382
383 kfree(work);
384}
385
386static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
387{
5c3fe8b0 388 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 389 return;
390
391 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
392
393 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 394 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 395 * entirely asynchronously.
396 */
5c3fe8b0 397 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 398 /* tasklet was killed before being run, clean up */
5c3fe8b0 399 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 400
401 /* Mark the work as no longer wanted so that if it does
402 * wake-up (because the work was already running and waiting
403 * for our mutex), it will discover that is no longer
404 * necessary to run.
405 */
5c3fe8b0 406 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 407}
408
993495ae 409static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 410{
411 struct intel_fbc_work *work;
412 struct drm_device *dev = crtc->dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 if (!dev_priv->display.enable_fbc)
416 return;
417
418 intel_cancel_fbc_work(dev_priv);
419
b14c5679 420 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 421 if (work == NULL) {
6cdcb5e7 422 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 423 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 424 return;
425 }
426
427 work->crtc = crtc;
f4510a27 428 work->fb = crtc->primary->fb;
85208be0
ED		 429 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
430
5c3fe8b0 431 dev_priv->fbc.fbc_work = work;
85208be0 432
85208be0
ED		 433 /* Delay the actual enabling to let pageflipping cease and the
434 * display to settle before starting the compression. Note that
435 * this delay also serves a second purpose: it allows for a
436 * vblank to pass after disabling the FBC before we attempt
437 * to modify the control registers.
438 *
439 * A more complicated solution would involve tracking vblanks
440 * following the termination of the page-flipping sequence
441 * and indeed performing the enable as a co-routine and not
442 * waiting synchronously upon the vblank.
7457d617
DL		 443 *
444 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 445 */
446 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
447}
448
449void intel_disable_fbc(struct drm_device *dev)
450{
451 struct drm_i915_private *dev_priv = dev->dev_private;
452
453 intel_cancel_fbc_work(dev_priv);
454
455 if (!dev_priv->display.disable_fbc)
456 return;
457
458 dev_priv->display.disable_fbc(dev);
5c3fe8b0 459 dev_priv->fbc.plane = -1;
85208be0
ED		 460}
461
29ebf90f
CW		 462static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
463 enum no_fbc_reason reason)
464{
465 if (dev_priv->fbc.no_fbc_reason == reason)
466 return false;
467
468 dev_priv->fbc.no_fbc_reason = reason;
469 return true;
470}
471
85208be0
ED		 472/**
473 * intel_update_fbc - enable/disable FBC as needed
474 * @dev: the drm_device
475 *
476 * Set up the framebuffer compression hardware at mode set time. We
477 * enable it if possible:
478 * - plane A only (on pre-965)
479 * - no pixel mulitply/line duplication
480 * - no alpha buffer discard
481 * - no dual wide
f85da868 482 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 483 *
484 * We can't assume that any compression will take place (worst case),
485 * so the compressed buffer has to be the same size as the uncompressed
486 * one. It also must reside (along with the line length buffer) in
487 * stolen memory.
488 *
489 * We need to enable/disable FBC on a global basis.
490 */
491void intel_update_fbc(struct drm_device *dev)
492{
493 struct drm_i915_private *dev_priv = dev->dev_private;
494 struct drm_crtc *crtc = NULL, *tmp_crtc;
495 struct intel_crtc *intel_crtc;
496 struct drm_framebuffer *fb;
85208be0 497 struct drm_i915_gem_object *obj;
ef644fda 498 const struct drm_display_mode *adjusted_mode;
37327abd 499 unsigned int max_width, max_height;
85208be0 500
3a77c4c4 501 if (!HAS_FBC(dev)) {
29ebf90f 502 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 503 return;
29ebf90f 504 }
85208be0 505
d330a953 506 if (!i915.powersave) {
29ebf90f
CW		 507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 509 return;
29ebf90f 510 }
85208be0
ED		 511
512 /*
513 * If FBC is already on, we just have to verify that we can
514 * keep it that way...
515 * Need to disable if:
516 * - more than one pipe is active
517 * - changing FBC params (stride, fence, mode)
518 * - new fb is too large to fit in compressed buffer
519 * - going to an unsupported config (interlace, pixel multiply, etc.)
520 */
70e1e0ec 521 for_each_crtc(dev, tmp_crtc) {
3490ea5d 522 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 523 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 524 if (crtc) {
29ebf90f
CW		 525 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
526 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 527 goto out_disable;
528 }
529 crtc = tmp_crtc;
530 }
531 }
532
f4510a27 533 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
535 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 536 goto out_disable;
537 }
538
539 intel_crtc = to_intel_crtc(crtc);
f4510a27 540 fb = crtc->primary->fb;
2ff8fde1 541 obj = intel_fb_obj(fb);
ef644fda 542 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 543
0368920e 544 if (i915.enable_fbc < 0) {
29ebf90f
CW		 545 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
546 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 547 goto out_disable;
85208be0 548 }
d330a953 549 if (!i915.enable_fbc) {
29ebf90f
CW		 550 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
551 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 552 goto out_disable;
553 }
ef644fda
VS		 554 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
555 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 556 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
557 DRM_DEBUG_KMS("mode incompatible with compression, "
558 "disabling\n");
85208be0
ED		 559 goto out_disable;
560 }
f85da868 561
032843a5
DS		 562 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
563 max_width = 4096;
564 max_height = 4096;
565 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 566 max_width = 4096;
567 max_height = 2048;
f85da868 568 } else {
37327abd
VS		 569 max_width = 2048;
570 max_height = 1536;
f85da868 571 }
37327abd
VS		 572 if (intel_crtc->config.pipe_src_w > max_width ||
573 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 574 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
575 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 576 goto out_disable;
577 }
8f94d24b 578 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 579 intel_crtc->plane != PLANE_A) {
29ebf90f 580 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 581 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 582 goto out_disable;
583 }
584
585 /* The use of a CPU fence is mandatory in order to detect writes
586 * by the CPU to the scanout and trigger updates to the FBC.
587 */
588 if (obj->tiling_mode != I915_TILING_X ||
589 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 590 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
591 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 592 goto out_disable;
593 }
48404c1e
SJ		 594 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
595 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
596 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
597 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
598 goto out_disable;
599 }
85208be0
ED		 600
601 /* If the kernel debugger is active, always disable compression */
602 if (in_dbg_master())
603 goto out_disable;
604
2ff8fde1 605 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
5e59f717 606 drm_format_plane_cpp(fb->pixel_format, 0))) {
29ebf90f
CW		 607 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
608 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 609 goto out_disable;
610 }
611
85208be0
ED		 612 /* If the scanout has not changed, don't modify the FBC settings.
613 * Note that we make the fundamental assumption that the fb->obj
614 * cannot be unpinned (and have its GTT offset and fence revoked)
615 * without first being decoupled from the scanout and FBC disabled.
616 */
5c3fe8b0
BW		 617 if (dev_priv->fbc.plane == intel_crtc->plane &&
618 dev_priv->fbc.fb_id == fb->base.id &&
619 dev_priv->fbc.y == crtc->y)
85208be0
ED		 620 return;
621
622 if (intel_fbc_enabled(dev)) {
623 /* We update FBC along two paths, after changing fb/crtc
624 * configuration (modeswitching) and after page-flipping
625 * finishes. For the latter, we know that not only did
626 * we disable the FBC at the start of the page-flip
627 * sequence, but also more than one vblank has passed.
628 *
629 * For the former case of modeswitching, it is possible
630 * to switch between two FBC valid configurations
631 * instantaneously so we do need to disable the FBC
632 * before we can modify its control registers. We also
633 * have to wait for the next vblank for that to take
634 * effect. However, since we delay enabling FBC we can
635 * assume that a vblank has passed since disabling and
636 * that we can safely alter the registers in the deferred
637 * callback.
638 *
639 * In the scenario that we go from a valid to invalid
640 * and then back to valid FBC configuration we have
641 * no strict enforcement that a vblank occurred since
642 * disabling the FBC. However, along all current pipe
643 * disabling paths we do need to wait for a vblank at
644 * some point. And we wait before enabling FBC anyway.
645 */
646 DRM_DEBUG_KMS("disabling active FBC for update\n");
647 intel_disable_fbc(dev);
648 }
649
993495ae 650 intel_enable_fbc(crtc);
29ebf90f 651 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 652 return;
653
654out_disable:
655 /* Multiple disables should be harmless */
656 if (intel_fbc_enabled(dev)) {
657 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
658 intel_disable_fbc(dev);
659 }
11be49eb 660 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 661}
662
c921aba8
DV		 663static void i915_pineview_get_mem_freq(struct drm_device *dev)
664{
50227e1c 665 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 666 u32 tmp;
667
668 tmp = I915_READ(CLKCFG);
669
670 switch (tmp & CLKCFG_FSB_MASK) {
671 case CLKCFG_FSB_533:
672 dev_priv->fsb_freq = 533; /* 133*4 */
673 break;
674 case CLKCFG_FSB_800:
675 dev_priv->fsb_freq = 800; /* 200*4 */
676 break;
677 case CLKCFG_FSB_667:
678 dev_priv->fsb_freq = 667; /* 167*4 */
679 break;
680 case CLKCFG_FSB_400:
681 dev_priv->fsb_freq = 400; /* 100*4 */
682 break;
683 }
684
685 switch (tmp & CLKCFG_MEM_MASK) {
686 case CLKCFG_MEM_533:
687 dev_priv->mem_freq = 533;
688 break;
689 case CLKCFG_MEM_667:
690 dev_priv->mem_freq = 667;
691 break;
692 case CLKCFG_MEM_800:
693 dev_priv->mem_freq = 800;
694 break;
695 }
696
697 /* detect pineview DDR3 setting */
698 tmp = I915_READ(CSHRDDR3CTL);
699 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
700}
701
702static void i915_ironlake_get_mem_freq(struct drm_device *dev)
703{
50227e1c 704 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 705 u16 ddrpll, csipll;
706
707 ddrpll = I915_READ16(DDRMPLL1);
708 csipll = I915_READ16(CSIPLL0);
709
710 switch (ddrpll & 0xff) {
711 case 0xc:
712 dev_priv->mem_freq = 800;
713 break;
714 case 0x10:
715 dev_priv->mem_freq = 1066;
716 break;
717 case 0x14:
718 dev_priv->mem_freq = 1333;
719 break;
720 case 0x18:
721 dev_priv->mem_freq = 1600;
722 break;
723 default:
724 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
725 ddrpll & 0xff);
726 dev_priv->mem_freq = 0;
727 break;
728 }
729
20e4d407 730 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 731
732 switch (csipll & 0x3ff) {
733 case 0x00c:
734 dev_priv->fsb_freq = 3200;
735 break;
736 case 0x00e:
737 dev_priv->fsb_freq = 3733;
738 break;
739 case 0x010:
740 dev_priv->fsb_freq = 4266;
741 break;
742 case 0x012:
743 dev_priv->fsb_freq = 4800;
744 break;
745 case 0x014:
746 dev_priv->fsb_freq = 5333;
747 break;
748 case 0x016:
749 dev_priv->fsb_freq = 5866;
750 break;
751 case 0x018:
752 dev_priv->fsb_freq = 6400;
753 break;
754 default:
755 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
756 csipll & 0x3ff);
757 dev_priv->fsb_freq = 0;
758 break;
759 }
760
761 if (dev_priv->fsb_freq == 3200) {
20e4d407 762 dev_priv->ips.c_m = 0;
c921aba8 763 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 764 dev_priv->ips.c_m = 1;
c921aba8 765 } else {
20e4d407 766 dev_priv->ips.c_m = 2;
c921aba8
DV		 767 }
768}
769
b445e3b0
ED		 770static const struct cxsr_latency cxsr_latency_table[] = {
771 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
772 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
773 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
774 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
775 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
776
777 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
778 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
779 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
780 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
781 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
782
783 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
784 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
785 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
786 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
787 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
788
789 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
790 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
791 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
792 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
793 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
794
795 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
796 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
797 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
798 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
799 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
800
801 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
802 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
803 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
804 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
805 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
806};
807
63c62275 808static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 809 int is_ddr3,
810 int fsb,
811 int mem)
812{
813 const struct cxsr_latency *latency;
814 int i;
815
816 if (fsb == 0 || mem == 0)
817 return NULL;
818
819 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
820 latency = &cxsr_latency_table[i];
821 if (is_desktop == latency->is_desktop &&
822 is_ddr3 == latency->is_ddr3 &&
823 fsb == latency->fsb_freq && mem == latency->mem_freq)
824 return latency;
825 }
826
827 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
828
829 return NULL;
830}
831
5209b1f4 832void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 833{
5209b1f4
ID		 834 struct drm_device *dev = dev_priv->dev;
835 u32 val;
b445e3b0 836
5209b1f4
ID		 837 if (IS_VALLEYVIEW(dev)) {
838 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
839 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
840 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
841 } else if (IS_PINEVIEW(dev)) {
842 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
843 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
844 I915_WRITE(DSPFW3, val);
845 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
846 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
847 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
848 I915_WRITE(FW_BLC_SELF, val);
849 } else if (IS_I915GM(dev)) {
850 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
851 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
852 I915_WRITE(INSTPM, val);
853 } else {
854 return;
855 }
b445e3b0 856
5209b1f4
ID		 857 DRM_DEBUG_KMS("memory self-refresh is %s\n",
858 enable ? "enabled" : "disabled");
b445e3b0
ED		 859}
860
861/*
862 * Latency for FIFO fetches is dependent on several factors:
863 * - memory configuration (speed, channels)
864 * - chipset
865 * - current MCH state
866 * It can be fairly high in some situations, so here we assume a fairly
867 * pessimal value. It's a tradeoff between extra memory fetches (if we
868 * set this value too high, the FIFO will fetch frequently to stay full)
869 * and power consumption (set it too low to save power and we might see
870 * FIFO underruns and display "flicker").
871 *
872 * A value of 5us seems to be a good balance; safe for very low end
873 * platforms but not overly aggressive on lower latency configs.
874 */
5aef6003 875static const int pessimal_latency_ns = 5000;
b445e3b0 876
1fa61106 877static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 878{
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 uint32_t dsparb = I915_READ(DSPARB);
881 int size;
882
883 size = dsparb & 0x7f;
884 if (plane)
885 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
886
887 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
888 plane ? "B" : "A", size);
889
890 return size;
891}
892
feb56b93 893static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 894{
895 struct drm_i915_private *dev_priv = dev->dev_private;
896 uint32_t dsparb = I915_READ(DSPARB);
897 int size;
898
899 size = dsparb & 0x1ff;
900 if (plane)
901 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
902 size >>= 1; /* Convert to cachelines */
903
904 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
905 plane ? "B" : "A", size);
906
907 return size;
908}
909
1fa61106 910static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 911{
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 uint32_t dsparb = I915_READ(DSPARB);
914 int size;
915
916 size = dsparb & 0x7f;
917 size >>= 2; /* Convert to cachelines */
918
919 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
920 plane ? "B" : "A",
921 size);
922
923 return size;
924}
925
b445e3b0
ED		 926/* Pineview has different values for various configs */
927static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 928 .fifo_size = PINEVIEW_DISPLAY_FIFO,
929 .max_wm = PINEVIEW_MAX_WM,
930 .default_wm = PINEVIEW_DFT_WM,
931 .guard_size = PINEVIEW_GUARD_WM,
932 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 933};
934static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 935 .fifo_size = PINEVIEW_DISPLAY_FIFO,
936 .max_wm = PINEVIEW_MAX_WM,
937 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
938 .guard_size = PINEVIEW_GUARD_WM,
939 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 940};
941static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 942 .fifo_size = PINEVIEW_CURSOR_FIFO,
943 .max_wm = PINEVIEW_CURSOR_MAX_WM,
944 .default_wm = PINEVIEW_CURSOR_DFT_WM,
945 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
946 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 947};
948static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 949 .fifo_size = PINEVIEW_CURSOR_FIFO,
950 .max_wm = PINEVIEW_CURSOR_MAX_WM,
951 .default_wm = PINEVIEW_CURSOR_DFT_WM,
952 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
953 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 954};
955static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 956 .fifo_size = G4X_FIFO_SIZE,
957 .max_wm = G4X_MAX_WM,
958 .default_wm = G4X_MAX_WM,
959 .guard_size = 2,
960 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 961};
962static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 963 .fifo_size = I965_CURSOR_FIFO,
964 .max_wm = I965_CURSOR_MAX_WM,
965 .default_wm = I965_CURSOR_DFT_WM,
966 .guard_size = 2,
967 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 968};
969static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 970 .fifo_size = VALLEYVIEW_FIFO_SIZE,
971 .max_wm = VALLEYVIEW_MAX_WM,
972 .default_wm = VALLEYVIEW_MAX_WM,
973 .guard_size = 2,
974 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 975};
976static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 977 .fifo_size = I965_CURSOR_FIFO,
978 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
979 .default_wm = I965_CURSOR_DFT_WM,
980 .guard_size = 2,
981 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 982};
983static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 984 .fifo_size = I965_CURSOR_FIFO,
985 .max_wm = I965_CURSOR_MAX_WM,
986 .default_wm = I965_CURSOR_DFT_WM,
987 .guard_size = 2,
988 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 989};
990static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 991 .fifo_size = I945_FIFO_SIZE,
992 .max_wm = I915_MAX_WM,
993 .default_wm = 1,
994 .guard_size = 2,
995 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 996};
997static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 998 .fifo_size = I915_FIFO_SIZE,
999 .max_wm = I915_MAX_WM,
1000 .default_wm = 1,
1001 .guard_size = 2,
1002 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 1003};
9d539105 1004static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 1005 .fifo_size = I855GM_FIFO_SIZE,
1006 .max_wm = I915_MAX_WM,
1007 .default_wm = 1,
1008 .guard_size = 2,
1009 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 1010};
9d539105
VS		 1011static const struct intel_watermark_params i830_bc_wm_info = {
1012 .fifo_size = I855GM_FIFO_SIZE,
1013 .max_wm = I915_MAX_WM/2,
1014 .default_wm = 1,
1015 .guard_size = 2,
1016 .cacheline_size = I830_FIFO_LINE_SIZE,
1017};
feb56b93 1018static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 1019 .fifo_size = I830_FIFO_SIZE,
1020 .max_wm = I915_MAX_WM,
1021 .default_wm = 1,
1022 .guard_size = 2,
1023 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 1024};
1025
b445e3b0
ED		 1026/**
1027 * intel_calculate_wm - calculate watermark level
1028 * @clock_in_khz: pixel clock
1029 * @wm: chip FIFO params
1030 * @pixel_size: display pixel size
1031 * @latency_ns: memory latency for the platform
1032 *
1033 * Calculate the watermark level (the level at which the display plane will
1034 * start fetching from memory again). Each chip has a different display
1035 * FIFO size and allocation, so the caller needs to figure that out and pass
1036 * in the correct intel_watermark_params structure.
1037 *
1038 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1039 * on the pixel size. When it reaches the watermark level, it'll start
1040 * fetching FIFO line sized based chunks from memory until the FIFO fills
1041 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1042 * will occur, and a display engine hang could result.
1043 */
1044static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1045 const struct intel_watermark_params *wm,
1046 int fifo_size,
1047 int pixel_size,
1048 unsigned long latency_ns)
1049{
1050 long entries_required, wm_size;
1051
1052 /*
1053 * Note: we need to make sure we don't overflow for various clock &
1054 * latency values.
1055 * clocks go from a few thousand to several hundred thousand.
1056 * latency is usually a few thousand
1057 */
1058 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1059 1000;
1060 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1061
1062 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1063
1064 wm_size = fifo_size - (entries_required + wm->guard_size);
1065
1066 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1067
1068 /* Don't promote wm_size to unsigned... */
1069 if (wm_size > (long)wm->max_wm)
1070 wm_size = wm->max_wm;
1071 if (wm_size <= 0)
1072 wm_size = wm->default_wm;
1073 return wm_size;
1074}
1075
1076static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1077{
1078 struct drm_crtc *crtc, *enabled = NULL;
1079
70e1e0ec 1080 for_each_crtc(dev, crtc) {
3490ea5d 1081 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1082 if (enabled)
1083 return NULL;
1084 enabled = crtc;
1085 }
1086 }
1087
1088 return enabled;
1089}
1090
46ba614c 1091static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1092{
46ba614c 1093 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 struct drm_crtc *crtc;
1096 const struct cxsr_latency *latency;
1097 u32 reg;
1098 unsigned long wm;
1099
1100 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1101 dev_priv->fsb_freq, dev_priv->mem_freq);
1102 if (!latency) {
1103 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 1104 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1105 return;
1106 }
1107
1108 crtc = single_enabled_crtc(dev);
1109 if (crtc) {
241bfc38 1110 const struct drm_display_mode *adjusted_mode;
f4510a27 1111 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1112 int clock;
1113
1114 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1115 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1116
1117 /* Display SR */
1118 wm = intel_calculate_wm(clock, &pineview_display_wm,
1119 pineview_display_wm.fifo_size,
1120 pixel_size, latency->display_sr);
1121 reg = I915_READ(DSPFW1);
1122 reg &= ~DSPFW_SR_MASK;
1123 reg |= wm << DSPFW_SR_SHIFT;
1124 I915_WRITE(DSPFW1, reg);
1125 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1126
1127 /* cursor SR */
1128 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1129 pineview_display_wm.fifo_size,
1130 pixel_size, latency->cursor_sr);
1131 reg = I915_READ(DSPFW3);
1132 reg &= ~DSPFW_CURSOR_SR_MASK;
1133 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1134 I915_WRITE(DSPFW3, reg);
1135
1136 /* Display HPLL off SR */
1137 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1138 pineview_display_hplloff_wm.fifo_size,
1139 pixel_size, latency->display_hpll_disable);
1140 reg = I915_READ(DSPFW3);
1141 reg &= ~DSPFW_HPLL_SR_MASK;
1142 reg |= wm & DSPFW_HPLL_SR_MASK;
1143 I915_WRITE(DSPFW3, reg);
1144
1145 /* cursor HPLL off SR */
1146 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1147 pineview_display_hplloff_wm.fifo_size,
1148 pixel_size, latency->cursor_hpll_disable);
1149 reg = I915_READ(DSPFW3);
1150 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1151 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1152 I915_WRITE(DSPFW3, reg);
1153 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1154
5209b1f4 1155 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 1156 } else {
5209b1f4 1157 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1158 }
1159}
1160
1161static bool g4x_compute_wm0(struct drm_device *dev,
1162 int plane,
1163 const struct intel_watermark_params *display,
1164 int display_latency_ns,
1165 const struct intel_watermark_params *cursor,
1166 int cursor_latency_ns,
1167 int *plane_wm,
1168 int *cursor_wm)
1169{
1170 struct drm_crtc *crtc;
4fe8590a 1171 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1172 int htotal, hdisplay, clock, pixel_size;
1173 int line_time_us, line_count;
1174 int entries, tlb_miss;
1175
1176 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1177 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1178 *cursor_wm = cursor->guard_size;
1179 *plane_wm = display->guard_size;
1180 return false;
1181 }
1182
4fe8590a 1183 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1184 clock = adjusted_mode->crtc_clock;
fec8cba3 1185 htotal = adjusted_mode->crtc_htotal;
37327abd 1186 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1187 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1188
1189 /* Use the small buffer method to calculate plane watermark */
1190 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1191 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1192 if (tlb_miss > 0)
1193 entries += tlb_miss;
1194 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1195 *plane_wm = entries + display->guard_size;
1196 if (*plane_wm > (int)display->max_wm)
1197 *plane_wm = display->max_wm;
1198
1199 /* Use the large buffer method to calculate cursor watermark */
922044c9 1200 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1201 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1202 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1203 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1204 if (tlb_miss > 0)
1205 entries += tlb_miss;
1206 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1207 *cursor_wm = entries + cursor->guard_size;
1208 if (*cursor_wm > (int)cursor->max_wm)
1209 *cursor_wm = (int)cursor->max_wm;
1210
1211 return true;
1212}
1213
1214/*
1215 * Check the wm result.
1216 *
1217 * If any calculated watermark values is larger than the maximum value that
1218 * can be programmed into the associated watermark register, that watermark
1219 * must be disabled.
1220 */
1221static bool g4x_check_srwm(struct drm_device *dev,
1222 int display_wm, int cursor_wm,
1223 const struct intel_watermark_params *display,
1224 const struct intel_watermark_params *cursor)
1225{
1226 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1227 display_wm, cursor_wm);
1228
1229 if (display_wm > display->max_wm) {
1230 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1231 display_wm, display->max_wm);
1232 return false;
1233 }
1234
1235 if (cursor_wm > cursor->max_wm) {
1236 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1237 cursor_wm, cursor->max_wm);
1238 return false;
1239 }
1240
1241 if (!(display_wm || cursor_wm)) {
1242 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1243 return false;
1244 }
1245
1246 return true;
1247}
1248
1249static bool g4x_compute_srwm(struct drm_device *dev,
1250 int plane,
1251 int latency_ns,
1252 const struct intel_watermark_params *display,
1253 const struct intel_watermark_params *cursor,
1254 int *display_wm, int *cursor_wm)
1255{
1256 struct drm_crtc *crtc;
4fe8590a 1257 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1258 int hdisplay, htotal, pixel_size, clock;
1259 unsigned long line_time_us;
1260 int line_count, line_size;
1261 int small, large;
1262 int entries;
1263
1264 if (!latency_ns) {
1265 *display_wm = *cursor_wm = 0;
1266 return false;
1267 }
1268
1269 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1270 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1271 clock = adjusted_mode->crtc_clock;
fec8cba3 1272 htotal = adjusted_mode->crtc_htotal;
37327abd 1273 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1274 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1275
922044c9 1276 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1277 line_count = (latency_ns / line_time_us + 1000) / 1000;
1278 line_size = hdisplay * pixel_size;
1279
1280 /* Use the minimum of the small and large buffer method for primary */
1281 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1282 large = line_count * line_size;
1283
1284 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1285 *display_wm = entries + display->guard_size;
1286
1287 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1288 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1289 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1290 *cursor_wm = entries + cursor->guard_size;
1291
1292 return g4x_check_srwm(dev,
1293 *display_wm, *cursor_wm,
1294 display, cursor);
1295}
1296
0948c265
GB		 1297static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1298 int pixel_size,
1299 int *prec_mult,
1300 int *drain_latency)
b445e3b0 1301{
b445e3b0 1302 int entries;
0948c265 1303 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0 1304
0948c265 1305 if (WARN(clock == 0, "Pixel clock is zero!\n"))
b445e3b0
ED		 1306 return false;
1307
0948c265
GB		 1308 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1309 return false;
b445e3b0 1310
a398e9c7 1311 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
0948c265
GB		 1312 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1313 DRAIN_LATENCY_PRECISION_32;
1314 *drain_latency = (64 * (*prec_mult) * 4) / entries;
b445e3b0 1315
a398e9c7
GB		 1316 if (*drain_latency > DRAIN_LATENCY_MASK)
1317 *drain_latency = DRAIN_LATENCY_MASK;
b445e3b0
ED		 1318
1319 return true;
1320}
1321
1322/*
1323 * Update drain latency registers of memory arbiter
1324 *
1325 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1326 * to be programmed. Each plane has a drain latency multiplier and a drain
1327 * latency value.
1328 */
1329
41aad816 1330static void vlv_update_drain_latency(struct drm_crtc *crtc)
b445e3b0 1331{
0948c265
GB		 1332 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1334 int pixel_size;
1335 int drain_latency;
1336 enum pipe pipe = intel_crtc->pipe;
1337 int plane_prec, prec_mult, plane_dl;
b445e3b0 1338
0948c265
GB		 1339 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1340 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1341 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1342
1343 if (!intel_crtc_active(crtc)) {
1344 I915_WRITE(VLV_DDL(pipe), plane_dl);
1345 return;
1346 }
b445e3b0 1347
0948c265
GB		 1348 /* Primary plane Drain Latency */
1349 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1350 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1351 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1352 DDL_PLANE_PRECISION_64 :
1353 DDL_PLANE_PRECISION_32;
1354 plane_dl |= plane_prec | drain_latency;
b445e3b0
ED		 1355 }
1356
0948c265
GB		 1357 /* Cursor Drain Latency
1358 * BPP is always 4 for cursor
1359 */
1360 pixel_size = 4;
b445e3b0 1361
0948c265
GB		 1362 /* Program cursor DL only if it is enabled */
1363 if (intel_crtc->cursor_base &&
1364 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1365 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1366 DDL_CURSOR_PRECISION_64 :
1367 DDL_CURSOR_PRECISION_32;
1368 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
b445e3b0 1369 }
0948c265
GB		 1370
1371 I915_WRITE(VLV_DDL(pipe), plane_dl);
b445e3b0
ED		 1372}
1373
1374#define single_plane_enabled(mask) is_power_of_2(mask)
1375
46ba614c 1376static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1377{
46ba614c 1378 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1379 static const int sr_latency_ns = 12000;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1382 int plane_sr, cursor_sr;
af6c4575 1383 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 1384 unsigned int enabled = 0;
9858425c 1385 bool cxsr_enabled;
b445e3b0 1386
41aad816 1387 vlv_update_drain_latency(crtc);
b445e3b0 1388
51cea1f4 1389 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1390 &valleyview_wm_info, pessimal_latency_ns,
1391 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1392 &planea_wm, &cursora_wm))
51cea1f4 1393 enabled |= 1 << PIPE_A;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1396 &valleyview_wm_info, pessimal_latency_ns,
1397 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planeb_wm, &cursorb_wm))
51cea1f4 1399 enabled |= 1 << PIPE_B;
b445e3b0 1400
b445e3b0
ED		 1401 if (single_plane_enabled(enabled) &&
1402 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 sr_latency_ns,
1404 &valleyview_wm_info,
1405 &valleyview_cursor_wm_info,
af6c4575
CW		 1406 &plane_sr, &ignore_cursor_sr) &&
1407 g4x_compute_srwm(dev, ffs(enabled) - 1,
1408 2*sr_latency_ns,
1409 &valleyview_wm_info,
1410 &valleyview_cursor_wm_info,
52bd02d8 1411 &ignore_plane_sr, &cursor_sr)) {
9858425c 1412 cxsr_enabled = true;
52bd02d8 1413 } else {
9858425c 1414 cxsr_enabled = false;
5209b1f4 1415 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1416 plane_sr = cursor_sr = 0;
1417 }
b445e3b0 1418
a5043453
VS		 1419 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1420 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1421 planea_wm, cursora_wm,
1422 planeb_wm, cursorb_wm,
1423 plane_sr, cursor_sr);
1424
1425 I915_WRITE(DSPFW1,
1426 (plane_sr << DSPFW_SR_SHIFT) |
1427 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1428 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1429 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1430 I915_WRITE(DSPFW2,
8c919b28 1431 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1432 (cursora_wm << DSPFW_CURSORA_SHIFT));
1433 I915_WRITE(DSPFW3,
8c919b28
CW		 1434 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1435 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1436
1437 if (cxsr_enabled)
1438 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1439}
1440
3c2777fd
VS		 1441static void cherryview_update_wm(struct drm_crtc *crtc)
1442{
1443 struct drm_device *dev = crtc->dev;
1444 static const int sr_latency_ns = 12000;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 int planea_wm, planeb_wm, planec_wm;
1447 int cursora_wm, cursorb_wm, cursorc_wm;
1448 int plane_sr, cursor_sr;
1449 int ignore_plane_sr, ignore_cursor_sr;
1450 unsigned int enabled = 0;
1451 bool cxsr_enabled;
1452
1453 vlv_update_drain_latency(crtc);
1454
1455 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1456 &valleyview_wm_info, pessimal_latency_ns,
1457 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1458 &planea_wm, &cursora_wm))
1459 enabled |= 1 << PIPE_A;
1460
1461 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1462 &valleyview_wm_info, pessimal_latency_ns,
1463 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1464 &planeb_wm, &cursorb_wm))
1465 enabled |= 1 << PIPE_B;
1466
1467 if (g4x_compute_wm0(dev, PIPE_C,
5aef6003
CW		 1468 &valleyview_wm_info, pessimal_latency_ns,
1469 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1470 &planec_wm, &cursorc_wm))
1471 enabled |= 1 << PIPE_C;
1472
1473 if (single_plane_enabled(enabled) &&
1474 g4x_compute_srwm(dev, ffs(enabled) - 1,
1475 sr_latency_ns,
1476 &valleyview_wm_info,
1477 &valleyview_cursor_wm_info,
1478 &plane_sr, &ignore_cursor_sr) &&
1479 g4x_compute_srwm(dev, ffs(enabled) - 1,
1480 2*sr_latency_ns,
1481 &valleyview_wm_info,
1482 &valleyview_cursor_wm_info,
1483 &ignore_plane_sr, &cursor_sr)) {
1484 cxsr_enabled = true;
1485 } else {
1486 cxsr_enabled = false;
1487 intel_set_memory_cxsr(dev_priv, false);
1488 plane_sr = cursor_sr = 0;
1489 }
1490
1491 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1492 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1493 "SR: plane=%d, cursor=%d\n",
1494 planea_wm, cursora_wm,
1495 planeb_wm, cursorb_wm,
1496 planec_wm, cursorc_wm,
1497 plane_sr, cursor_sr);
1498
1499 I915_WRITE(DSPFW1,
1500 (plane_sr << DSPFW_SR_SHIFT) |
1501 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1502 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1503 (planea_wm << DSPFW_PLANEA_SHIFT));
1504 I915_WRITE(DSPFW2,
1505 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1506 (cursora_wm << DSPFW_CURSORA_SHIFT));
1507 I915_WRITE(DSPFW3,
1508 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1509 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1510 I915_WRITE(DSPFW9_CHV,
1511 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1512 DSPFW_CURSORC_MASK)) |
1513 (planec_wm << DSPFW_PLANEC_SHIFT) |
1514 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1515
1516 if (cxsr_enabled)
1517 intel_set_memory_cxsr(dev_priv, true);
1518}
1519
01e184cc
GB		 1520static void valleyview_update_sprite_wm(struct drm_plane *plane,
1521 struct drm_crtc *crtc,
1522 uint32_t sprite_width,
1523 uint32_t sprite_height,
1524 int pixel_size,
1525 bool enabled, bool scaled)
1526{
1527 struct drm_device *dev = crtc->dev;
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 int pipe = to_intel_plane(plane)->pipe;
1530 int sprite = to_intel_plane(plane)->plane;
1531 int drain_latency;
1532 int plane_prec;
1533 int sprite_dl;
1534 int prec_mult;
1535
1536 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1537 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1538
1539 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1540 &drain_latency)) {
1541 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1542 DDL_SPRITE_PRECISION_64(sprite) :
1543 DDL_SPRITE_PRECISION_32(sprite);
1544 sprite_dl |= plane_prec |
1545 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1546 }
1547
1548 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1549}
1550
46ba614c 1551static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1552{
46ba614c 1553 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1554 static const int sr_latency_ns = 12000;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1557 int plane_sr, cursor_sr;
1558 unsigned int enabled = 0;
9858425c 1559 bool cxsr_enabled;
b445e3b0 1560
51cea1f4 1561 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1562 &g4x_wm_info, pessimal_latency_ns,
1563 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1564 &planea_wm, &cursora_wm))
51cea1f4 1565 enabled |= 1 << PIPE_A;
b445e3b0 1566
51cea1f4 1567 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1568 &g4x_wm_info, pessimal_latency_ns,
1569 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1570 &planeb_wm, &cursorb_wm))
51cea1f4 1571 enabled |= 1 << PIPE_B;
b445e3b0 1572
b445e3b0
ED		 1573 if (single_plane_enabled(enabled) &&
1574 g4x_compute_srwm(dev, ffs(enabled) - 1,
1575 sr_latency_ns,
1576 &g4x_wm_info,
1577 &g4x_cursor_wm_info,
52bd02d8 1578 &plane_sr, &cursor_sr)) {
9858425c 1579 cxsr_enabled = true;
52bd02d8 1580 } else {
9858425c 1581 cxsr_enabled = false;
5209b1f4 1582 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1583 plane_sr = cursor_sr = 0;
1584 }
b445e3b0 1585
a5043453
VS		 1586 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1587 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1588 planea_wm, cursora_wm,
1589 planeb_wm, cursorb_wm,
1590 plane_sr, cursor_sr);
1591
1592 I915_WRITE(DSPFW1,
1593 (plane_sr << DSPFW_SR_SHIFT) |
1594 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1595 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1596 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1597 I915_WRITE(DSPFW2,
8c919b28 1598 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1599 (cursora_wm << DSPFW_CURSORA_SHIFT));
1600 /* HPLL off in SR has some issues on G4x... disable it */
1601 I915_WRITE(DSPFW3,
8c919b28 1602 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1603 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1604
1605 if (cxsr_enabled)
1606 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1607}
1608
46ba614c 1609static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1610{
46ba614c 1611 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 struct drm_crtc *crtc;
1614 int srwm = 1;
1615 int cursor_sr = 16;
9858425c 1616 bool cxsr_enabled;
b445e3b0
ED		 1617
1618 /* Calc sr entries for one plane configs */
1619 crtc = single_enabled_crtc(dev);
1620 if (crtc) {
1621 /* self-refresh has much higher latency */
1622 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1623 const struct drm_display_mode *adjusted_mode =
1624 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1625 int clock = adjusted_mode->crtc_clock;
fec8cba3 1626 int htotal = adjusted_mode->crtc_htotal;
37327abd 1627 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1628 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1629 unsigned long line_time_us;
1630 int entries;
1631
922044c9 1632 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1633
1634 /* Use ns/us then divide to preserve precision */
1635 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636 pixel_size * hdisplay;
1637 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1638 srwm = I965_FIFO_SIZE - entries;
1639 if (srwm < 0)
1640 srwm = 1;
1641 srwm &= 0x1ff;
1642 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1643 entries, srwm);
1644
1645 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1646 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1647 entries = DIV_ROUND_UP(entries,
1648 i965_cursor_wm_info.cacheline_size);
1649 cursor_sr = i965_cursor_wm_info.fifo_size -
1650 (entries + i965_cursor_wm_info.guard_size);
1651
1652 if (cursor_sr > i965_cursor_wm_info.max_wm)
1653 cursor_sr = i965_cursor_wm_info.max_wm;
1654
1655 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1656 "cursor %d\n", srwm, cursor_sr);
1657
9858425c 1658 cxsr_enabled = true;
b445e3b0 1659 } else {
9858425c 1660 cxsr_enabled = false;
b445e3b0 1661 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1662 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1663 }
1664
1665 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1666 srwm);
1667
1668 /* 965 has limitations... */
1669 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS		 1670 (8 << DSPFW_CURSORB_SHIFT) |
1671 (8 << DSPFW_PLANEB_SHIFT) |
1672 (8 << DSPFW_PLANEA_SHIFT));
1673 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1674 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED		 1675 /* update cursor SR watermark */
1676 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1677
1678 if (cxsr_enabled)
1679 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1680}
1681
46ba614c 1682static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1683{
46ba614c 1684 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686 const struct intel_watermark_params *wm_info;
1687 uint32_t fwater_lo;
1688 uint32_t fwater_hi;
1689 int cwm, srwm = 1;
1690 int fifo_size;
1691 int planea_wm, planeb_wm;
1692 struct drm_crtc *crtc, *enabled = NULL;
1693
1694 if (IS_I945GM(dev))
1695 wm_info = &i945_wm_info;
1696 else if (!IS_GEN2(dev))
1697 wm_info = &i915_wm_info;
1698 else
9d539105 1699 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1700
1701 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1702 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1703 if (intel_crtc_active(crtc)) {
241bfc38 1704 const struct drm_display_mode *adjusted_mode;
f4510a27 1705 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1706 if (IS_GEN2(dev))
1707 cpp = 4;
1708
241bfc38
DL		 1709 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1710 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1711 wm_info, fifo_size, cpp,
5aef6003 1712 pessimal_latency_ns);
b445e3b0 1713 enabled = crtc;
9d539105 1714 } else {
b445e3b0 1715 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1716 if (planea_wm > (long)wm_info->max_wm)
1717 planea_wm = wm_info->max_wm;
1718 }
1719
1720 if (IS_GEN2(dev))
1721 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1722
1723 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1724 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1725 if (intel_crtc_active(crtc)) {
241bfc38 1726 const struct drm_display_mode *adjusted_mode;
f4510a27 1727 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1728 if (IS_GEN2(dev))
1729 cpp = 4;
1730
241bfc38
DL		 1731 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1732 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1733 wm_info, fifo_size, cpp,
5aef6003 1734 pessimal_latency_ns);
b445e3b0
ED		 1735 if (enabled == NULL)
1736 enabled = crtc;
1737 else
1738 enabled = NULL;
9d539105 1739 } else {
b445e3b0 1740 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1741 if (planeb_wm > (long)wm_info->max_wm)
1742 planeb_wm = wm_info->max_wm;
1743 }
b445e3b0
ED		 1744
1745 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1746
2ab1bc9d 1747 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1748 struct drm_i915_gem_object *obj;
2ab1bc9d 1749
2ff8fde1 1750 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1751
1752 /* self-refresh seems busted with untiled */
2ff8fde1 1753 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1754 enabled = NULL;
1755 }
1756
b445e3b0
ED		 1757 /*
1758 * Overlay gets an aggressive default since video jitter is bad.
1759 */
1760 cwm = 2;
1761
1762 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1763 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1764
1765 /* Calc sr entries for one plane configs */
1766 if (HAS_FW_BLC(dev) && enabled) {
1767 /* self-refresh has much higher latency */
1768 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1769 const struct drm_display_mode *adjusted_mode =
1770 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1771 int clock = adjusted_mode->crtc_clock;
fec8cba3 1772 int htotal = adjusted_mode->crtc_htotal;
f727b490 1773 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1774 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1775 unsigned long line_time_us;
1776 int entries;
1777
922044c9 1778 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1779
1780 /* Use ns/us then divide to preserve precision */
1781 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1782 pixel_size * hdisplay;
1783 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1784 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1785 srwm = wm_info->fifo_size - entries;
1786 if (srwm < 0)
1787 srwm = 1;
1788
1789 if (IS_I945G(dev) || IS_I945GM(dev))
1790 I915_WRITE(FW_BLC_SELF,
1791 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1792 else if (IS_I915GM(dev))
1793 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1794 }
1795
1796 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1797 planea_wm, planeb_wm, cwm, srwm);
1798
1799 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1800 fwater_hi = (cwm & 0x1f);
1801
1802 /* Set request length to 8 cachelines per fetch */
1803 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1804 fwater_hi = fwater_hi | (1 << 8);
1805
1806 I915_WRITE(FW_BLC, fwater_lo);
1807 I915_WRITE(FW_BLC2, fwater_hi);
1808
5209b1f4
ID		 1809 if (enabled)
1810 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1811}
1812
feb56b93 1813static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1814{
46ba614c 1815 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 struct drm_crtc *crtc;
241bfc38 1818 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1819 uint32_t fwater_lo;
1820 int planea_wm;
1821
1822 crtc = single_enabled_crtc(dev);
1823 if (crtc == NULL)
1824 return;
1825
241bfc38
DL		 1826 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1827 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1828 &i845_wm_info,
b445e3b0 1829 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1830 4, pessimal_latency_ns);
b445e3b0
ED		 1831 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1832 fwater_lo |= (3<<8) | planea_wm;
1833
1834 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1835
1836 I915_WRITE(FW_BLC, fwater_lo);
1837}
1838
3658729a
VS		 1839static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1840 struct drm_crtc *crtc)
801bcfff
PZ		 1841{
1842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1843 uint32_t pixel_rate;
801bcfff 1844
241bfc38 1845 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1846
1847 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1848 * adjust the pixel_rate here. */
1849
fd4daa9c 1850 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1851 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1852 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1853
37327abd
VS		 1854 pipe_w = intel_crtc->config.pipe_src_w;
1855 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1856 pfit_w = (pfit_size >> 16) & 0xFFFF;
1857 pfit_h = pfit_size & 0xFFFF;
1858 if (pipe_w < pfit_w)
1859 pipe_w = pfit_w;
1860 if (pipe_h < pfit_h)
1861 pipe_h = pfit_h;
1862
1863 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1864 pfit_w * pfit_h);
1865 }
1866
1867 return pixel_rate;
1868}
1869
37126462 1870/* latency must be in 0.1us units. */
23297044 1871static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1872 uint32_t latency)
1873{
1874 uint64_t ret;
1875
3312ba65
VS		 1876 if (WARN(latency == 0, "Latency value missing\n"))
1877 return UINT_MAX;
1878
801bcfff
PZ		 1879 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1880 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1881
1882 return ret;
1883}
1884
37126462 1885/* latency must be in 0.1us units. */
23297044 1886static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1887 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1888 uint32_t latency)
1889{
1890 uint32_t ret;
1891
3312ba65
VS		 1892 if (WARN(latency == 0, "Latency value missing\n"))
1893 return UINT_MAX;
1894
801bcfff
PZ		 1895 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1896 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1897 ret = DIV_ROUND_UP(ret, 64) + 2;
1898 return ret;
1899}
1900
23297044 1901static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1902 uint8_t bytes_per_pixel)
1903{
1904 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1905}
1906
820c1980 1907struct ilk_pipe_wm_parameters {
801bcfff 1908 bool active;
801bcfff
PZ		 1909 uint32_t pipe_htotal;
1910 uint32_t pixel_rate;
c35426d2
VS		 1911 struct intel_plane_wm_parameters pri;
1912 struct intel_plane_wm_parameters spr;
1913 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1914};
1915
820c1980 1916struct ilk_wm_maximums {
cca32e9a
PZ		 1917 uint16_t pri;
1918 uint16_t spr;
1919 uint16_t cur;
1920 uint16_t fbc;
1921};
1922
240264f4
VS		 1923/* used in computing the new watermarks state */
1924struct intel_wm_config {
1925 unsigned int num_pipes_active;
1926 bool sprites_enabled;
1927 bool sprites_scaled;
240264f4
VS		 1928};
1929
37126462
VS		 1930/*
1931 * For both WM_PIPE and WM_LP.
1932 * mem_value must be in 0.1us units.
1933 */
820c1980 1934static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1935 uint32_t mem_value,
1936 bool is_lp)
801bcfff 1937{
cca32e9a
PZ		 1938 uint32_t method1, method2;
1939
c35426d2 1940 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1941 return 0;
1942
23297044 1943 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1944 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1945 mem_value);
1946
1947 if (!is_lp)
1948 return method1;
1949
23297044 1950 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1951 params->pipe_htotal,
c35426d2
VS		 1952 params->pri.horiz_pixels,
1953 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1954 mem_value);
1955
1956 return min(method1, method2);
801bcfff
PZ		 1957}
1958
37126462
VS		 1959/*
1960 * For both WM_PIPE and WM_LP.
1961 * mem_value must be in 0.1us units.
1962 */
820c1980 1963static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1964 uint32_t mem_value)
1965{
1966 uint32_t method1, method2;
1967
c35426d2 1968 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1969 return 0;
1970
23297044 1971 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1972 params->spr.bytes_per_pixel,
801bcfff 1973 mem_value);
23297044 1974 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1975 params->pipe_htotal,
c35426d2
VS		 1976 params->spr.horiz_pixels,
1977 params->spr.bytes_per_pixel,
801bcfff
PZ		 1978 mem_value);
1979 return min(method1, method2);
1980}
1981
37126462
VS		 1982/*
1983 * For both WM_PIPE and WM_LP.
1984 * mem_value must be in 0.1us units.
1985 */
820c1980 1986static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1987 uint32_t mem_value)
1988{
c35426d2 1989 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1990 return 0;
1991
23297044 1992 return ilk_wm_method2(params->pixel_rate,
801bcfff 1993 params->pipe_htotal,
c35426d2
VS		 1994 params->cur.horiz_pixels,
1995 params->cur.bytes_per_pixel,
801bcfff
PZ		 1996 mem_value);
1997}
1998
cca32e9a 1999/* Only for WM_LP. */
820c1980 2000static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 2001 uint32_t pri_val)
cca32e9a 2002{
c35426d2 2003 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2004 return 0;
2005
23297044 2006 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2007 params->pri.horiz_pixels,
2008 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2009}
2010
158ae64f
VS		 2011static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2012{
416f4727
VS		 2013 if (INTEL_INFO(dev)->gen >= 8)
2014 return 3072;
2015 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2016 return 768;
2017 else
2018 return 512;
2019}
2020
4e975081
VS		 2021static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2022 int level, bool is_sprite)
2023{
2024 if (INTEL_INFO(dev)->gen >= 8)
2025 /* BDW primary/sprite plane watermarks */
2026 return level == 0 ? 255 : 2047;
2027 else if (INTEL_INFO(dev)->gen >= 7)
2028 /* IVB/HSW primary/sprite plane watermarks */
2029 return level == 0 ? 127 : 1023;
2030 else if (!is_sprite)
2031 /* ILK/SNB primary plane watermarks */
2032 return level == 0 ? 127 : 511;
2033 else
2034 /* ILK/SNB sprite plane watermarks */
2035 return level == 0 ? 63 : 255;
2036}
2037
2038static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2039 int level)
2040{
2041 if (INTEL_INFO(dev)->gen >= 7)
2042 return level == 0 ? 63 : 255;
2043 else
2044 return level == 0 ? 31 : 63;
2045}
2046
2047static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2048{
2049 if (INTEL_INFO(dev)->gen >= 8)
2050 return 31;
2051 else
2052 return 15;
2053}
2054
158ae64f
VS		 2055/* Calculate the maximum primary/sprite plane watermark */
2056static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2057 int level,
240264f4 2058 const struct intel_wm_config *config,
158ae64f
VS		 2059 enum intel_ddb_partitioning ddb_partitioning,
2060 bool is_sprite)
2061{
2062 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 2063
2064 /* if sprites aren't enabled, sprites get nothing */
240264f4 2065 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2066 return 0;
2067
2068 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2069 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2070 fifo_size /= INTEL_INFO(dev)->num_pipes;
2071
2072 /*
2073 * For some reason the non self refresh
2074 * FIFO size is only half of the self
2075 * refresh FIFO size on ILK/SNB.
2076 */
2077 if (INTEL_INFO(dev)->gen <= 6)
2078 fifo_size /= 2;
2079 }
2080
240264f4 2081 if (config->sprites_enabled) {
158ae64f
VS		 2082 /* level 0 is always calculated with 1:1 split */
2083 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2084 if (is_sprite)
2085 fifo_size *= 5;
2086 fifo_size /= 6;
2087 } else {
2088 fifo_size /= 2;
2089 }
2090 }
2091
2092 /* clamp to max that the registers can hold */
4e975081 2093 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 2094}
2095
2096/* Calculate the maximum cursor plane watermark */
2097static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2098 int level,
2099 const struct intel_wm_config *config)
158ae64f
VS		 2100{
2101 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2102 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2103 return 64;
2104
2105 /* otherwise just report max that registers can hold */
4e975081 2106 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 2107}
2108
d34ff9c6 2109static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 2110 int level,
2111 const struct intel_wm_config *config,
2112 enum intel_ddb_partitioning ddb_partitioning,
820c1980 2113 struct ilk_wm_maximums *max)
158ae64f 2114{
240264f4
VS		 2115 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2116 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2117 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 2118 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 2119}
2120
a3cb4048
VS		 2121static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2122 int level,
2123 struct ilk_wm_maximums *max)
2124{
2125 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2126 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2127 max->cur = ilk_cursor_wm_reg_max(dev, level);
2128 max->fbc = ilk_fbc_wm_reg_max(dev);
2129}
2130
d9395655 2131static bool ilk_validate_wm_level(int level,
820c1980 2132 const struct ilk_wm_maximums *max,
d9395655 2133 struct intel_wm_level *result)
a9786a11
VS		 2134{
2135 bool ret;
2136
2137 /* already determined to be invalid? */
2138 if (!result->enable)
2139 return false;
2140
2141 result->enable = result->pri_val <= max->pri &&
2142 result->spr_val <= max->spr &&
2143 result->cur_val <= max->cur;
2144
2145 ret = result->enable;
2146
2147 /*
2148 * HACK until we can pre-compute everything,
2149 * and thus fail gracefully if LP0 watermarks
2150 * are exceeded...
2151 */
2152 if (level == 0 && !result->enable) {
2153 if (result->pri_val > max->pri)
2154 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2155 level, result->pri_val, max->pri);
2156 if (result->spr_val > max->spr)
2157 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2158 level, result->spr_val, max->spr);
2159 if (result->cur_val > max->cur)
2160 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2161 level, result->cur_val, max->cur);
2162
2163 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2164 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2165 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2166 result->enable = true;
2167 }
2168
a9786a11
VS		 2169 return ret;
2170}
2171
d34ff9c6 2172static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2173 int level,
820c1980 2174 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2175 struct intel_wm_level *result)
6f5ddd17
VS		 2176{
2177 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2178 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2179 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2180
2181 /* WM1+ latency values stored in 0.5us units */
2182 if (level > 0) {
2183 pri_latency *= 5;
2184 spr_latency *= 5;
2185 cur_latency *= 5;
2186 }
2187
2188 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2189 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2190 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2191 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2192 result->enable = true;
2193}
2194
801bcfff
PZ		 2195static uint32_t
2196hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2197{
2198 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2200 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2201 u32 linetime, ips_linetime;
1f8eeabf 2202
801bcfff
PZ		 2203 if (!intel_crtc_active(crtc))
2204 return 0;
1011d8c4 2205
1f8eeabf
ED		 2206 /* The WM are computed with base on how long it takes to fill a single
2207 * row at the given clock rate, multiplied by 8.
2208 * */
fec8cba3
JB		 2209 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2210 mode->crtc_clock);
2211 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2212 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2213
801bcfff
PZ		 2214 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2215 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2216}
2217
12b134df
VS		 2218static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2219{
2220 struct drm_i915_private *dev_priv = dev->dev_private;
2221
a42a5719 2222 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2223 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2224
2225 wm[0] = (sskpd >> 56) & 0xFF;
2226 if (wm[0] == 0)
2227 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2228 wm[1] = (sskpd >> 4) & 0xFF;
2229 wm[2] = (sskpd >> 12) & 0xFF;
2230 wm[3] = (sskpd >> 20) & 0x1FF;
2231 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2232 } else if (INTEL_INFO(dev)->gen >= 6) {
2233 uint32_t sskpd = I915_READ(MCH_SSKPD);
2234
2235 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2236 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2237 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2238 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2239 } else if (INTEL_INFO(dev)->gen >= 5) {
2240 uint32_t mltr = I915_READ(MLTR_ILK);
2241
2242 /* ILK primary LP0 latency is 700 ns */
2243 wm[0] = 7;
2244 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2245 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2246 }
2247}
2248
53615a5e
VS		 2249static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2250{
2251 /* ILK sprite LP0 latency is 1300 ns */
2252 if (INTEL_INFO(dev)->gen == 5)
2253 wm[0] = 13;
2254}
2255
2256static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2257{
2258 /* ILK cursor LP0 latency is 1300 ns */
2259 if (INTEL_INFO(dev)->gen == 5)
2260 wm[0] = 13;
2261
2262 /* WaDoubleCursorLP3Latency:ivb */
2263 if (IS_IVYBRIDGE(dev))
2264 wm[3] *= 2;
2265}
2266
546c81fd 2267int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2268{
26ec971e 2269 /* how many WM levels are we expecting */
a42a5719 2270 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2271 return 4;
26ec971e 2272 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2273 return 3;
26ec971e 2274 else
ad0d6dc4
VS		 2275 return 2;
2276}
ad0d6dc4
VS		 2277static void intel_print_wm_latency(struct drm_device *dev,
2278 const char *name,
2279 const uint16_t wm[5])
2280{
2281 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2282
2283 for (level = 0; level <= max_level; level++) {
2284 unsigned int latency = wm[level];
2285
2286 if (latency == 0) {
2287 DRM_ERROR("%s WM%d latency not provided\n",
2288 name, level);
2289 continue;
2290 }
2291
2292 /* WM1+ latency values in 0.5us units */
2293 if (level > 0)
2294 latency *= 5;
2295
2296 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2297 name, level, wm[level],
2298 latency / 10, latency % 10);
2299 }
2300}
2301
e95a2f75
VS		 2302static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2303 uint16_t wm[5], uint16_t min)
2304{
2305 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2306
2307 if (wm[0] >= min)
2308 return false;
2309
2310 wm[0] = max(wm[0], min);
2311 for (level = 1; level <= max_level; level++)
2312 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2313
2314 return true;
2315}
2316
2317static void snb_wm_latency_quirk(struct drm_device *dev)
2318{
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 bool changed;
2321
2322 /*
2323 * The BIOS provided WM memory latency values are often
2324 * inadequate for high resolution displays. Adjust them.
2325 */
2326 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2327 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2328 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2329
2330 if (!changed)
2331 return;
2332
2333 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2334 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2335 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2336 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2337}
2338
fa50ad61 2339static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2340{
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342
2343 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2344
2345 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2346 sizeof(dev_priv->wm.pri_latency));
2347 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2348 sizeof(dev_priv->wm.pri_latency));
2349
2350 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2351 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2352
2353 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2354 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2355 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2356
2357 if (IS_GEN6(dev))
2358 snb_wm_latency_quirk(dev);
53615a5e
VS		 2359}
2360
820c1980 2361static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2362 struct ilk_pipe_wm_parameters *p)
1011d8c4 2363{
7c4a395f
VS		 2364 struct drm_device *dev = crtc->dev;
2365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2367 struct drm_plane *plane;
1011d8c4 2368
2a44b76b
VS		 2369 if (!intel_crtc_active(crtc))
2370 return;
801bcfff 2371
2a44b76b
VS		 2372 p->active = true;
2373 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2374 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2375 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2376 p->cur.bytes_per_pixel = 4;
2377 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2378 p->cur.horiz_pixels = intel_crtc->cursor_width;
2379 /* TODO: for now, assume primary and cursor planes are always enabled. */
2380 p->pri.enabled = true;
2381 p->cur.enabled = true;
7c4a395f 2382
af2b653b 2383 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2384 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2385
2a44b76b 2386 if (intel_plane->pipe == pipe) {
7c4a395f 2387 p->spr = intel_plane->wm;
2a44b76b
VS		 2388 break;
2389 }
2390 }
2391}
2392
2393static void ilk_compute_wm_config(struct drm_device *dev,
2394 struct intel_wm_config *config)
2395{
2396 struct intel_crtc *intel_crtc;
2397
2398 /* Compute the currently _active_ config */
d3fcc808 2399 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2400 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2401
2a44b76b
VS		 2402 if (!wm->pipe_enabled)
2403 continue;
cca32e9a 2404
2a44b76b
VS		 2405 config->sprites_enabled |= wm->sprites_enabled;
2406 config->sprites_scaled |= wm->sprites_scaled;
2407 config->num_pipes_active++;
cca32e9a 2408 }
801bcfff
PZ		 2409}
2410
0b2ae6d7
VS		 2411/* Compute new watermarks for the pipe */
2412static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2413 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2414 struct intel_pipe_wm *pipe_wm)
2415{
2416 struct drm_device *dev = crtc->dev;
d34ff9c6 2417 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2418 int level, max_level = ilk_wm_max_level(dev);
2419 /* LP0 watermark maximums depend on this pipe alone */
2420 struct intel_wm_config config = {
2421 .num_pipes_active = 1,
2422 .sprites_enabled = params->spr.enabled,
2423 .sprites_scaled = params->spr.scaled,
2424 };
820c1980 2425 struct ilk_wm_maximums max;
0b2ae6d7 2426
2a44b76b
VS		 2427 pipe_wm->pipe_enabled = params->active;
2428 pipe_wm->sprites_enabled = params->spr.enabled;
2429 pipe_wm->sprites_scaled = params->spr.scaled;
2430
7b39a0b7
VS		 2431 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2432 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2433 max_level = 1;
2434
2435 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2436 if (params->spr.scaled)
2437 max_level = 0;
2438
a3cb4048 2439 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2440
a42a5719 2441 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2442 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2443
a3cb4048
VS		 2444 /* LP0 watermarks always use 1/2 DDB partitioning */
2445 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2446
0b2ae6d7 2447 /* At least LP0 must be valid */
a3cb4048
VS		 2448 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2449 return false;
2450
2451 ilk_compute_wm_reg_maximums(dev, 1, &max);
2452
2453 for (level = 1; level <= max_level; level++) {
2454 struct intel_wm_level wm = {};
2455
2456 ilk_compute_wm_level(dev_priv, level, params, &wm);
2457
2458 /*
2459 * Disable any watermark level that exceeds the
2460 * register maximums since such watermarks are
2461 * always invalid.
2462 */
2463 if (!ilk_validate_wm_level(level, &max, &wm))
2464 break;
2465
2466 pipe_wm->wm[level] = wm;
2467 }
2468
2469 return true;
0b2ae6d7
VS		 2470}
2471
2472/*
2473 * Merge the watermarks from all active pipes for a specific level.
2474 */
2475static void ilk_merge_wm_level(struct drm_device *dev,
2476 int level,
2477 struct intel_wm_level *ret_wm)
2478{
2479 const struct intel_crtc *intel_crtc;
2480
d52fea5b
VS		 2481 ret_wm->enable = true;
2482
d3fcc808 2483 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2484 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2485 const struct intel_wm_level *wm = &active->wm[level];
2486
2487 if (!active->pipe_enabled)
2488 continue;
0b2ae6d7 2489
d52fea5b
VS		 2490 /*
2491 * The watermark values may have been used in the past,
2492 * so we must maintain them in the registers for some
2493 * time even if the level is now disabled.
2494 */
0b2ae6d7 2495 if (!wm->enable)
d52fea5b 2496 ret_wm->enable = false;
0b2ae6d7
VS		 2497
2498 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2499 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2500 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2501 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2502 }
0b2ae6d7
VS		 2503}
2504
2505/*
2506 * Merge all low power watermarks for all active pipes.
2507 */
2508static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2509 const struct intel_wm_config *config,
820c1980 2510 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2511 struct intel_pipe_wm *merged)
2512{
2513 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2514 int last_enabled_level = max_level;
0b2ae6d7 2515
0ba22e26
VS		 2516 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2517 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2518 config->num_pipes_active > 1)
2519 return;
2520
6c8b6c28
VS		 2521 /* ILK: FBC WM must be disabled always */
2522 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2523
2524 /* merge each WM1+ level */
2525 for (level = 1; level <= max_level; level++) {
2526 struct intel_wm_level *wm = &merged->wm[level];
2527
2528 ilk_merge_wm_level(dev, level, wm);
2529
d52fea5b
VS		 2530 if (level > last_enabled_level)
2531 wm->enable = false;
2532 else if (!ilk_validate_wm_level(level, max, wm))
2533 /* make sure all following levels get disabled */
2534 last_enabled_level = level - 1;
0b2ae6d7
VS		 2535
2536 /*
2537 * The spec says it is preferred to disable
2538 * FBC WMs instead of disabling a WM level.
2539 */
2540 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2541 if (wm->enable)
2542 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2543 wm->fbc_val = 0;
2544 }
2545 }
6c8b6c28
VS		 2546
2547 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2548 /*
2549 * FIXME this is racy. FBC might get enabled later.
2550 * What we should check here is whether FBC can be
2551 * enabled sometime later.
2552 */
2553 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2554 for (level = 2; level <= max_level; level++) {
2555 struct intel_wm_level *wm = &merged->wm[level];
2556
2557 wm->enable = false;
2558 }
2559 }
0b2ae6d7
VS		 2560}
2561
b380ca3c
VS		 2562static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2563{
2564 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2565 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2566}
2567
a68d68ee
VS		 2568/* The value we need to program into the WM_LPx latency field */
2569static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2570{
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572
a42a5719 2573 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2574 return 2 * level;
2575 else
2576 return dev_priv->wm.pri_latency[level];
2577}
2578
820c1980 2579static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2580 const struct intel_pipe_wm *merged,
609cedef 2581 enum intel_ddb_partitioning partitioning,
820c1980 2582 struct ilk_wm_values *results)
801bcfff 2583{
0b2ae6d7
VS		 2584 struct intel_crtc *intel_crtc;
2585 int level, wm_lp;
cca32e9a 2586
0362c781 2587 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2588 results->partitioning = partitioning;
cca32e9a 2589
0b2ae6d7 2590 /* LP1+ register values */
cca32e9a 2591 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2592 const struct intel_wm_level *r;
801bcfff 2593
b380ca3c 2594 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2595
0362c781 2596 r = &merged->wm[level];
cca32e9a 2597
d52fea5b
VS		 2598 /*
2599 * Maintain the watermark values even if the level is
2600 * disabled. Doing otherwise could cause underruns.
2601 */
2602 results->wm_lp[wm_lp - 1] =
a68d68ee 2603 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2604 (r->pri_val << WM1_LP_SR_SHIFT) |
2605 r->cur_val;
2606
d52fea5b
VS		 2607 if (r->enable)
2608 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2609
416f4727
VS		 2610 if (INTEL_INFO(dev)->gen >= 8)
2611 results->wm_lp[wm_lp - 1] |=
2612 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2613 else
2614 results->wm_lp[wm_lp - 1] |=
2615 r->fbc_val << WM1_LP_FBC_SHIFT;
2616
d52fea5b
VS		 2617 /*
2618 * Always set WM1S_LP_EN when spr_val != 0, even if the
2619 * level is disabled. Doing otherwise could cause underruns.
2620 */
6cef2b8a
VS		 2621 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2622 WARN_ON(wm_lp != 1);
2623 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2624 } else
2625 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2626 }
801bcfff 2627
0b2ae6d7 2628 /* LP0 register values */
d3fcc808 2629 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2630 enum pipe pipe = intel_crtc->pipe;
2631 const struct intel_wm_level *r =
2632 &intel_crtc->wm.active.wm[0];
2633
2634 if (WARN_ON(!r->enable))
2635 continue;
2636
2637 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2638
0b2ae6d7
VS		 2639 results->wm_pipe[pipe] =
2640 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2641 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2642 r->cur_val;
801bcfff
PZ		 2643 }
2644}
2645
861f3389
PZ		 2646/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2647 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2648static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2649 struct intel_pipe_wm *r1,
2650 struct intel_pipe_wm *r2)
861f3389 2651{
198a1e9b
VS		 2652 int level, max_level = ilk_wm_max_level(dev);
2653 int level1 = 0, level2 = 0;
861f3389 2654
198a1e9b
VS		 2655 for (level = 1; level <= max_level; level++) {
2656 if (r1->wm[level].enable)
2657 level1 = level;
2658 if (r2->wm[level].enable)
2659 level2 = level;
861f3389
PZ		 2660 }
2661
198a1e9b
VS		 2662 if (level1 == level2) {
2663 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2664 return r2;
2665 else
2666 return r1;
198a1e9b 2667 } else if (level1 > level2) {
861f3389
PZ		 2668 return r1;
2669 } else {
2670 return r2;
2671 }
2672}
2673
49a687c4
VS		 2674/* dirty bits used to track which watermarks need changes */
2675#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2676#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2677#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2678#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2679#define WM_DIRTY_FBC (1 << 24)
2680#define WM_DIRTY_DDB (1 << 25)
2681
055e393f 2682static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2683 const struct ilk_wm_values *old,
2684 const struct ilk_wm_values *new)
49a687c4
VS		 2685{
2686 unsigned int dirty = 0;
2687 enum pipe pipe;
2688 int wm_lp;
2689
055e393f 2690 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2691 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2692 dirty |= WM_DIRTY_LINETIME(pipe);
2693 /* Must disable LP1+ watermarks too */
2694 dirty |= WM_DIRTY_LP_ALL;
2695 }
2696
2697 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2698 dirty |= WM_DIRTY_PIPE(pipe);
2699 /* Must disable LP1+ watermarks too */
2700 dirty |= WM_DIRTY_LP_ALL;
2701 }
2702 }
2703
2704 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2705 dirty |= WM_DIRTY_FBC;
2706 /* Must disable LP1+ watermarks too */
2707 dirty |= WM_DIRTY_LP_ALL;
2708 }
2709
2710 if (old->partitioning != new->partitioning) {
2711 dirty |= WM_DIRTY_DDB;
2712 /* Must disable LP1+ watermarks too */
2713 dirty |= WM_DIRTY_LP_ALL;
2714 }
2715
2716 /* LP1+ watermarks already deemed dirty, no need to continue */
2717 if (dirty & WM_DIRTY_LP_ALL)
2718 return dirty;
2719
2720 /* Find the lowest numbered LP1+ watermark in need of an update... */
2721 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2722 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2723 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2724 break;
2725 }
2726
2727 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2728 for (; wm_lp <= 3; wm_lp++)
2729 dirty |= WM_DIRTY_LP(wm_lp);
2730
2731 return dirty;
2732}
2733
8553c18e
VS		 2734static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2735 unsigned int dirty)
801bcfff 2736{
820c1980 2737 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2738 bool changed = false;
801bcfff 2739
facd619b
VS		 2740 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2741 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2742 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2743 changed = true;
facd619b
VS		 2744 }
2745 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2746 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2747 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2748 changed = true;
facd619b
VS		 2749 }
2750 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2751 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2752 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2753 changed = true;
facd619b 2754 }
801bcfff 2755
facd619b
VS		 2756 /*
2757 * Don't touch WM1S_LP_EN here.
2758 * Doing so could cause underruns.
2759 */
6cef2b8a 2760
8553c18e
VS		 2761 return changed;
2762}
2763
2764/*
2765 * The spec says we shouldn't write when we don't need, because every write
2766 * causes WMs to be re-evaluated, expending some power.
2767 */
820c1980
ID		 2768static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2769 struct ilk_wm_values *results)
8553c18e
VS		 2770{
2771 struct drm_device *dev = dev_priv->dev;
820c1980 2772 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2773 unsigned int dirty;
2774 uint32_t val;
2775
055e393f 2776 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2777 if (!dirty)
2778 return;
2779
2780 _ilk_disable_lp_wm(dev_priv, dirty);
2781
49a687c4 2782 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2783 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2784 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2785 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2786 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2787 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2788
49a687c4 2789 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2790 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2791 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2792 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2793 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2794 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2795
49a687c4 2796 if (dirty & WM_DIRTY_DDB) {
a42a5719 2797 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2798 val = I915_READ(WM_MISC);
2799 if (results->partitioning == INTEL_DDB_PART_1_2)
2800 val &= ~WM_MISC_DATA_PARTITION_5_6;
2801 else
2802 val |= WM_MISC_DATA_PARTITION_5_6;
2803 I915_WRITE(WM_MISC, val);
2804 } else {
2805 val = I915_READ(DISP_ARB_CTL2);
2806 if (results->partitioning == INTEL_DDB_PART_1_2)
2807 val &= ~DISP_DATA_PARTITION_5_6;
2808 else
2809 val |= DISP_DATA_PARTITION_5_6;
2810 I915_WRITE(DISP_ARB_CTL2, val);
2811 }
1011d8c4
PZ		 2812 }
2813
49a687c4 2814 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2815 val = I915_READ(DISP_ARB_CTL);
2816 if (results->enable_fbc_wm)
2817 val &= ~DISP_FBC_WM_DIS;
2818 else
2819 val |= DISP_FBC_WM_DIS;
2820 I915_WRITE(DISP_ARB_CTL, val);
2821 }
2822
954911eb
ID		 2823 if (dirty & WM_DIRTY_LP(1) &&
2824 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2825 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2826
2827 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2828 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2829 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2830 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2831 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2832 }
801bcfff 2833
facd619b 2834 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2835 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2836 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2837 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2838 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2839 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2840
2841 dev_priv->wm.hw = *results;
801bcfff
PZ		 2842}
2843
8553c18e
VS		 2844static bool ilk_disable_lp_wm(struct drm_device *dev)
2845{
2846 struct drm_i915_private *dev_priv = dev->dev_private;
2847
2848 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2849}
2850
820c1980 2851static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2852{
7c4a395f 2853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2854 struct drm_device *dev = crtc->dev;
801bcfff 2855 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2856 struct ilk_wm_maximums max;
2857 struct ilk_pipe_wm_parameters params = {};
2858 struct ilk_wm_values results = {};
77c122bc 2859 enum intel_ddb_partitioning partitioning;
7c4a395f 2860 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2861 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2862 struct intel_wm_config config = {};
7c4a395f 2863
2a44b76b 2864 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2865
2866 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2867
2868 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2869 return;
861f3389 2870
7c4a395f 2871 intel_crtc->wm.active = pipe_wm;
861f3389 2872
2a44b76b
VS		 2873 ilk_compute_wm_config(dev, &config);
2874
34982fe1 2875 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2876 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2877
2878 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2879 if (INTEL_INFO(dev)->gen >= 7 &&
2880 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2881 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2882 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2883
820c1980 2884 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2885 } else {
198a1e9b 2886 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2887 }
2888
198a1e9b 2889 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2890 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2891
820c1980 2892 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2893
820c1980 2894 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2895}
2896
ed57cb8a
DL		 2897static void
2898ilk_update_sprite_wm(struct drm_plane *plane,
2899 struct drm_crtc *crtc,
2900 uint32_t sprite_width, uint32_t sprite_height,
2901 int pixel_size, bool enabled, bool scaled)
526682e9 2902{
8553c18e 2903 struct drm_device *dev = plane->dev;
adf3d35e 2904 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2905
adf3d35e
VS		 2906 intel_plane->wm.enabled = enabled;
2907 intel_plane->wm.scaled = scaled;
2908 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 2909 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 2910 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2911
8553c18e
VS		 2912 /*
2913 * IVB workaround: must disable low power watermarks for at least
2914 * one frame before enabling scaling. LP watermarks can be re-enabled
2915 * when scaling is disabled.
2916 *
2917 * WaCxSRDisabledForSpriteScaling:ivb
2918 */
2919 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2920 intel_wait_for_vblank(dev, intel_plane->pipe);
2921
820c1980 2922 ilk_update_wm(crtc);
526682e9
PZ		 2923}
2924
243e6a44
VS		 2925static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2926{
2927 struct drm_device *dev = crtc->dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2929 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2932 enum pipe pipe = intel_crtc->pipe;
2933 static const unsigned int wm0_pipe_reg[] = {
2934 [PIPE_A] = WM0_PIPEA_ILK,
2935 [PIPE_B] = WM0_PIPEB_ILK,
2936 [PIPE_C] = WM0_PIPEC_IVB,
2937 };
2938
2939 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2940 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2941 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2942
2a44b76b
VS		 2943 active->pipe_enabled = intel_crtc_active(crtc);
2944
2945 if (active->pipe_enabled) {
243e6a44
VS		 2946 u32 tmp = hw->wm_pipe[pipe];
2947
2948 /*
2949 * For active pipes LP0 watermark is marked as
2950 * enabled, and LP1+ watermaks as disabled since
2951 * we can't really reverse compute them in case
2952 * multiple pipes are active.
2953 */
2954 active->wm[0].enable = true;
2955 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2956 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2957 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2958 active->linetime = hw->wm_linetime[pipe];
2959 } else {
2960 int level, max_level = ilk_wm_max_level(dev);
2961
2962 /*
2963 * For inactive pipes, all watermark levels
2964 * should be marked as enabled but zeroed,
2965 * which is what we'd compute them to.
2966 */
2967 for (level = 0; level <= max_level; level++)
2968 active->wm[level].enable = true;
2969 }
2970}
2971
2972void ilk_wm_get_hw_state(struct drm_device *dev)
2973{
2974 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2975 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2976 struct drm_crtc *crtc;
2977
70e1e0ec 2978 for_each_crtc(dev, crtc)
243e6a44
VS		 2979 ilk_pipe_wm_get_hw_state(crtc);
2980
2981 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2982 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2983 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2984
2985 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2986 if (INTEL_INFO(dev)->gen >= 7) {
2987 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2988 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2989 }
243e6a44 2990
a42a5719 2991 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2992 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2993 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2994 else if (IS_IVYBRIDGE(dev))
2995 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2996 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2997
2998 hw->enable_fbc_wm =
2999 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3000}
3001
b445e3b0
ED		 3002/**
3003 * intel_update_watermarks - update FIFO watermark values based on current modes
3004 *
3005 * Calculate watermark values for the various WM regs based on current mode
3006 * and plane configuration.
3007 *
3008 * There are several cases to deal with here:
3009 * - normal (i.e. non-self-refresh)
3010 * - self-refresh (SR) mode
3011 * - lines are large relative to FIFO size (buffer can hold up to 2)
3012 * - lines are small relative to FIFO size (buffer can hold more than 2
3013 * lines), so need to account for TLB latency
3014 *
3015 * The normal calculation is:
3016 * watermark = dotclock * bytes per pixel * latency
3017 * where latency is platform & configuration dependent (we assume pessimal
3018 * values here).
3019 *
3020 * The SR calculation is:
3021 * watermark = (trunc(latency/line time)+1) * surface width *
3022 * bytes per pixel
3023 * where
3024 * line time = htotal / dotclock
3025 * surface width = hdisplay for normal plane and 64 for cursor
3026 * and latency is assumed to be high, as above.
3027 *
3028 * The final value programmed to the register should always be rounded up,
3029 * and include an extra 2 entries to account for clock crossings.
3030 *
3031 * We don't use the sprite, so we can ignore that. And on Crestline we have
3032 * to set the non-SR watermarks to 8.
3033 */
46ba614c 3034void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3035{
46ba614c 3036 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3037
3038 if (dev_priv->display.update_wm)
46ba614c 3039 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3040}
3041
adf3d35e
VS		 3042void intel_update_sprite_watermarks(struct drm_plane *plane,
3043 struct drm_crtc *crtc,
ed57cb8a
DL		 3044 uint32_t sprite_width,
3045 uint32_t sprite_height,
3046 int pixel_size,
39db4a4d 3047 bool enabled, bool scaled)
b445e3b0 3048{
adf3d35e 3049 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3050
3051 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3052 dev_priv->display.update_sprite_wm(plane, crtc,
3053 sprite_width, sprite_height,
39db4a4d 3054 pixel_size, enabled, scaled);
b445e3b0
ED		 3055}
3056
2b4e57bd
ED		 3057static struct drm_i915_gem_object *
3058intel_alloc_context_page(struct drm_device *dev)
3059{
3060 struct drm_i915_gem_object *ctx;
3061 int ret;
3062
3063 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3064
3065 ctx = i915_gem_alloc_object(dev, 4096);
3066 if (!ctx) {
3067 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3068 return NULL;
3069 }
3070
c69766f2 3071 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 3072 if (ret) {
3073 DRM_ERROR("failed to pin power context: %d\n", ret);
3074 goto err_unref;
3075 }
3076
3077 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3078 if (ret) {
3079 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3080 goto err_unpin;
3081 }
3082
3083 return ctx;
3084
3085err_unpin:
d7f46fc4 3086 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 3087err_unref:
3088 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3089 return NULL;
3090}
3091
9270388e
DV		 3092/**
3093 * Lock protecting IPS related data structures
9270388e
DV		 3094 */
3095DEFINE_SPINLOCK(mchdev_lock);
3096
3097/* Global for IPS driver to get at the current i915 device. Protected by
3098 * mchdev_lock. */
3099static struct drm_i915_private *i915_mch_dev;
3100
2b4e57bd
ED		 3101bool ironlake_set_drps(struct drm_device *dev, u8 val)
3102{
3103 struct drm_i915_private *dev_priv = dev->dev_private;
3104 u16 rgvswctl;
3105
9270388e
DV		 3106 assert_spin_locked(&mchdev_lock);
3107
2b4e57bd
ED		 3108 rgvswctl = I915_READ16(MEMSWCTL);
3109 if (rgvswctl & MEMCTL_CMD_STS) {
3110 DRM_DEBUG("gpu busy, RCS change rejected\n");
3111 return false; /* still busy with another command */
3112 }
3113
3114 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3115 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3116 I915_WRITE16(MEMSWCTL, rgvswctl);
3117 POSTING_READ16(MEMSWCTL);
3118
3119 rgvswctl |= MEMCTL_CMD_STS;
3120 I915_WRITE16(MEMSWCTL, rgvswctl);
3121
3122 return true;
3123}
3124
8090c6b9 3125static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3126{
3127 struct drm_i915_private *dev_priv = dev->dev_private;
3128 u32 rgvmodectl = I915_READ(MEMMODECTL);
3129 u8 fmax, fmin, fstart, vstart;
3130
9270388e
DV		 3131 spin_lock_irq(&mchdev_lock);
3132
2b4e57bd
ED		 3133 /* Enable temp reporting */
3134 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3135 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3136
3137 /* 100ms RC evaluation intervals */
3138 I915_WRITE(RCUPEI, 100000);
3139 I915_WRITE(RCDNEI, 100000);
3140
3141 /* Set max/min thresholds to 90ms and 80ms respectively */
3142 I915_WRITE(RCBMAXAVG, 90000);
3143 I915_WRITE(RCBMINAVG, 80000);
3144
3145 I915_WRITE(MEMIHYST, 1);
3146
3147 /* Set up min, max, and cur for interrupt handling */
3148 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3149 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3150 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3151 MEMMODE_FSTART_SHIFT;
3152
3153 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3154 PXVFREQ_PX_SHIFT;
3155
20e4d407
DV		 3156 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3157 dev_priv->ips.fstart = fstart;
2b4e57bd 3158
20e4d407
DV		 3159 dev_priv->ips.max_delay = fstart;
3160 dev_priv->ips.min_delay = fmin;
3161 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3162
3163 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3164 fmax, fmin, fstart);
3165
3166 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3167
3168 /*
3169 * Interrupts will be enabled in ironlake_irq_postinstall
3170 */
3171
3172 I915_WRITE(VIDSTART, vstart);
3173 POSTING_READ(VIDSTART);
3174
3175 rgvmodectl |= MEMMODE_SWMODE_EN;
3176 I915_WRITE(MEMMODECTL, rgvmodectl);
3177
9270388e 3178 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3179 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3180 mdelay(1);
2b4e57bd
ED		 3181
3182 ironlake_set_drps(dev, fstart);
3183
20e4d407 3184 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3185 I915_READ(0x112e0);
20e4d407
DV		 3186 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3187 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3188 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3189
3190 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3191}
3192
8090c6b9 3193static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3194{
3195 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3196 u16 rgvswctl;
3197
3198 spin_lock_irq(&mchdev_lock);
3199
3200 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3201
3202 /* Ack interrupts, disable EFC interrupt */
3203 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3204 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3205 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3206 I915_WRITE(DEIIR, DE_PCU_EVENT);
3207 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3208
3209 /* Go back to the starting frequency */
20e4d407 3210 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3211 mdelay(1);
2b4e57bd
ED		 3212 rgvswctl |= MEMCTL_CMD_STS;
3213 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3214 mdelay(1);
2b4e57bd 3215
9270388e 3216 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3217}
3218
acbe9475
DV		 3219/* There's a funny hw issue where the hw returns all 0 when reading from
3220 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3221 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3222 * all limits and the gpu stuck at whatever frequency it is at atm).
3223 */
6917c7b9 3224static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3225{
7b9e0ae6 3226 u32 limits;
2b4e57bd 3227
20b46e59
DV		 3228 /* Only set the down limit when we've reached the lowest level to avoid
3229 * getting more interrupts, otherwise leave this clear. This prevents a
3230 * race in the hw when coming out of rc6: There's a tiny window where
3231 * the hw runs at the minimal clock before selecting the desired
3232 * frequency, if the down threshold expires in that window we will not
3233 * receive a down interrupt. */
b39fb297
BW		 3234 limits = dev_priv->rps.max_freq_softlimit << 24;
3235 if (val <= dev_priv->rps.min_freq_softlimit)
3236 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3237
3238 return limits;
3239}
3240
dd75fdc8
CW		 3241static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3242{
3243 int new_power;
3244
c76bb61a
DS		 3245 if (dev_priv->rps.is_bdw_sw_turbo)
3246 return;
3247
dd75fdc8
CW		 3248 new_power = dev_priv->rps.power;
3249 switch (dev_priv->rps.power) {
3250 case LOW_POWER:
b39fb297 3251 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3252 new_power = BETWEEN;
3253 break;
3254
3255 case BETWEEN:
b39fb297 3256 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3257 new_power = LOW_POWER;
b39fb297 3258 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3259 new_power = HIGH_POWER;
3260 break;
3261
3262 case HIGH_POWER:
b39fb297 3263 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3264 new_power = BETWEEN;
3265 break;
3266 }
3267 /* Max/min bins are special */
b39fb297 3268 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3269 new_power = LOW_POWER;
b39fb297 3270 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3271 new_power = HIGH_POWER;
3272 if (new_power == dev_priv->rps.power)
3273 return;
3274
3275 /* Note the units here are not exactly 1us, but 1280ns. */
3276 switch (new_power) {
3277 case LOW_POWER:
3278 /* Upclock if more than 95% busy over 16ms */
3279 I915_WRITE(GEN6_RP_UP_EI, 12500);
3280 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3281
3282 /* Downclock if less than 85% busy over 32ms */
3283 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3284 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3285
3286 I915_WRITE(GEN6_RP_CONTROL,
3287 GEN6_RP_MEDIA_TURBO |
3288 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3289 GEN6_RP_MEDIA_IS_GFX |
3290 GEN6_RP_ENABLE |
3291 GEN6_RP_UP_BUSY_AVG |
3292 GEN6_RP_DOWN_IDLE_AVG);
3293 break;
3294
3295 case BETWEEN:
3296 /* Upclock if more than 90% busy over 13ms */
3297 I915_WRITE(GEN6_RP_UP_EI, 10250);
3298 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3299
3300 /* Downclock if less than 75% busy over 32ms */
3301 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3302 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3303
3304 I915_WRITE(GEN6_RP_CONTROL,
3305 GEN6_RP_MEDIA_TURBO |
3306 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3307 GEN6_RP_MEDIA_IS_GFX |
3308 GEN6_RP_ENABLE |
3309 GEN6_RP_UP_BUSY_AVG |
3310 GEN6_RP_DOWN_IDLE_AVG);
3311 break;
3312
3313 case HIGH_POWER:
3314 /* Upclock if more than 85% busy over 10ms */
3315 I915_WRITE(GEN6_RP_UP_EI, 8000);
3316 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3317
3318 /* Downclock if less than 60% busy over 32ms */
3319 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3320 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3321
3322 I915_WRITE(GEN6_RP_CONTROL,
3323 GEN6_RP_MEDIA_TURBO |
3324 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3325 GEN6_RP_MEDIA_IS_GFX |
3326 GEN6_RP_ENABLE |
3327 GEN6_RP_UP_BUSY_AVG |
3328 GEN6_RP_DOWN_IDLE_AVG);
3329 break;
3330 }
3331
3332 dev_priv->rps.power = new_power;
3333 dev_priv->rps.last_adj = 0;
3334}
3335
2876ce73
CW		 3336static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3337{
3338 u32 mask = 0;
3339
3340 if (val > dev_priv->rps.min_freq_softlimit)
3341 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3342 if (val < dev_priv->rps.max_freq_softlimit)
3343 mask |= GEN6_PM_RP_UP_THRESHOLD;
3344
7b3c29f6
CW		 3345 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3346 mask &= dev_priv->pm_rps_events;
3347
2876ce73
CW		 3348 /* IVB and SNB hard hangs on looping batchbuffer
3349 * if GEN6_PM_UP_EI_EXPIRED is masked.
3350 */
3351 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3352 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3353
baccd458
D		 3354 if (IS_GEN8(dev_priv->dev))
3355 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3356
2876ce73
CW		 3357 return ~mask;
3358}
3359
b8a5ff8d
JM		 3360/* gen6_set_rps is called to update the frequency request, but should also be
3361 * called when the range (min_delay and max_delay) is modified so that we can
3362 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3363void gen6_set_rps(struct drm_device *dev, u8 val)
3364{
3365 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3366
4fc688ce 3367 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3368 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3369 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3370
eb64cad1
CW		 3371 /* min/max delay may still have been modified so be sure to
3372 * write the limits value.
3373 */
3374 if (val != dev_priv->rps.cur_freq) {
3375 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3376
50e6a2a7 3377 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3378 I915_WRITE(GEN6_RPNSWREQ,
3379 HSW_FREQUENCY(val));
3380 else
3381 I915_WRITE(GEN6_RPNSWREQ,
3382 GEN6_FREQUENCY(val) |
3383 GEN6_OFFSET(0) |
3384 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3385 }
7b9e0ae6 3386
7b9e0ae6
CW		 3387 /* Make sure we continue to get interrupts
3388 * until we hit the minimum or maximum frequencies.
3389 */
eb64cad1 3390 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3391 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3392
d5570a72
BW		 3393 POSTING_READ(GEN6_RPNSWREQ);
3394
b39fb297 3395 dev_priv->rps.cur_freq = val;
be2cde9a 3396 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3397}
3398
76c3552f
D		 3399/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3400 *
3401 * * If Gfx is Idle, then
3402 * 1. Mask Turbo interrupts
3403 * 2. Bring up Gfx clock
3404 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3405 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3406 * 5. Unmask Turbo interrupts
3407*/
3408static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3409{
5549d25f
D		 3410 struct drm_device *dev = dev_priv->dev;
3411
3412 /* Latest VLV doesn't need to force the gfx clock */
3413 if (dev->pdev->revision >= 0xd) {
3414 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3415 return;
3416 }
3417
76c3552f
D		 3418 /*
3419 * When we are idle. Drop to min voltage state.
3420 */
3421
b39fb297 3422 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3423 return;
3424
3425 /* Mask turbo interrupt so that they will not come in between */
3426 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3427
650ad970 3428 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3429
b39fb297 3430 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3431
3432 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3433 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3434
3435 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3436 & GENFREQSTATUS) == 0, 5))
3437 DRM_ERROR("timed out waiting for Punit\n");
3438
650ad970 3439 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3440
2876ce73
CW		 3441 I915_WRITE(GEN6_PMINTRMSK,
3442 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3443}
3444
b29c19b6
CW		 3445void gen6_rps_idle(struct drm_i915_private *dev_priv)
3446{
691bb717
DL		 3447 struct drm_device *dev = dev_priv->dev;
3448
b29c19b6 3449 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3450 if (dev_priv->rps.enabled) {
34638118
D		 3451 if (IS_CHERRYVIEW(dev))
3452 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3453 else if (IS_VALLEYVIEW(dev))
76c3552f 3454 vlv_set_rps_idle(dev_priv);
c76bb61a
DS		 3455 else if (!dev_priv->rps.is_bdw_sw_turbo
3456 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
b39fb297 3457 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c76bb61a
DS		 3458 }
3459
c0951f0c
CW		 3460 dev_priv->rps.last_adj = 0;
3461 }
b29c19b6
CW		 3462 mutex_unlock(&dev_priv->rps.hw_lock);
3463}
3464
3465void gen6_rps_boost(struct drm_i915_private *dev_priv)
3466{
691bb717
DL		 3467 struct drm_device *dev = dev_priv->dev;
3468
b29c19b6 3469 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3470 if (dev_priv->rps.enabled) {
691bb717 3471 if (IS_VALLEYVIEW(dev))
b39fb297 3472 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c76bb61a
DS		 3473 else if (!dev_priv->rps.is_bdw_sw_turbo
3474 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
b39fb297 3475 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c76bb61a
DS		 3476 }
3477
c0951f0c
CW		 3478 dev_priv->rps.last_adj = 0;
3479 }
b29c19b6
CW		 3480 mutex_unlock(&dev_priv->rps.hw_lock);
3481}
3482
0a073b84
JB		 3483void valleyview_set_rps(struct drm_device *dev, u8 val)
3484{
3485 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3486
0a073b84 3487 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3488 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3489 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3490
73008b98 3491 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3492 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3493 dev_priv->rps.cur_freq,
2ec3815f 3494 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3495
1c14762d
VS		 3496 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3497 "Odd GPU freq value\n"))
3498 val &= ~1;
3499
2876ce73
CW		 3500 if (val != dev_priv->rps.cur_freq)
3501 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3502
09c87db8 3503 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3504
b39fb297 3505 dev_priv->rps.cur_freq = val;
2ec3815f 3506 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3507}
3508
0961021a
BW		 3509static void gen8_disable_rps_interrupts(struct drm_device *dev)
3510{
3511 struct drm_i915_private *dev_priv = dev->dev_private;
c76bb61a
DS		 3512 if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){
3513 if (atomic_read(&dev_priv->rps.sw_turbo.flip_received))
3514 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3515 dev_priv-> rps.is_bdw_sw_turbo = false;
3516 } else {
3517 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3518 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3519 ~dev_priv->pm_rps_events);
3520 /* Complete PM interrupt masking here doesn't race with the rps work
3521 * item again unmasking PM interrupts because that is using a different
3522 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3523 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3524 * gen8_enable_rps will clean up. */
3525
3526 spin_lock_irq(&dev_priv->irq_lock);
3527 dev_priv->rps.pm_iir = 0;
3528 spin_unlock_irq(&dev_priv->irq_lock);
3529
3530 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3531 }
0961021a
BW		 3532}
3533
44fc7d5c 3534static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3535{
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537
2b4e57bd 3538 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3539 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3540 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3541 /* Complete PM interrupt masking here doesn't race with the rps work
3542 * item again unmasking PM interrupts because that is using a different
3543 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3544 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3545
59cdb63d 3546 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3547 dev_priv->rps.pm_iir = 0;
59cdb63d 3548 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3549
a6706b45 3550 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3551}
3552
44fc7d5c 3553static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3554{
3555 struct drm_i915_private *dev_priv = dev->dev_private;
3556
3557 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3558 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3559
0961021a
BW		 3560 if (IS_BROADWELL(dev))
3561 gen8_disable_rps_interrupts(dev);
3562 else
3563 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3564}
3565
38807746
D		 3566static void cherryview_disable_rps(struct drm_device *dev)
3567{
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569
3570 I915_WRITE(GEN6_RC_CONTROL, 0);
3497a562
D		 3571
3572 gen8_disable_rps_interrupts(dev);
38807746
D		 3573}
3574
44fc7d5c
DV		 3575static void valleyview_disable_rps(struct drm_device *dev)
3576{
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578
98a2e5f9
D		 3579 /* we're doing forcewake before Disabling RC6,
3580 * This what the BIOS expects when going into suspend */
3581 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3582
44fc7d5c 3583 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3584
98a2e5f9
D		 3585 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3586
44fc7d5c 3587 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3588}
3589
dc39fff7
BW		 3590static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3591{
91ca689a
ID		 3592 if (IS_VALLEYVIEW(dev)) {
3593 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3594 mode = GEN6_RC_CTL_RC6_ENABLE;
3595 else
3596 mode = 0;
3597 }
8dfd1f04
DV		 3598 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3599 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3600 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3601 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3602}
3603
e6069ca8 3604static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3605{
eb4926e4
DL		 3606 /* No RC6 before Ironlake */
3607 if (INTEL_INFO(dev)->gen < 5)
3608 return 0;
3609
e6069ca8
ID		 3610 /* RC6 is only on Ironlake mobile not on desktop */
3611 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3612 return 0;
3613
456470eb 3614 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3615 if (enable_rc6 >= 0) {
3616 int mask;
3617
3618 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3619 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3620 INTEL_RC6pp_ENABLE;
3621 else
3622 mask = INTEL_RC6_ENABLE;
3623
3624 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 3625 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3626 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3627
3628 return enable_rc6 & mask;
3629 }
2b4e57bd 3630
6567d748
CW		 3631 /* Disable RC6 on Ironlake */
3632 if (INTEL_INFO(dev)->gen == 5)
3633 return 0;
2b4e57bd 3634
8bade1ad 3635 if (IS_IVYBRIDGE(dev))
cca84a1f 3636 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3637
3638 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3639}
3640
e6069ca8
ID		 3641int intel_enable_rc6(const struct drm_device *dev)
3642{
3643 return i915.enable_rc6;
3644}
3645
0961021a
BW		 3646static void gen8_enable_rps_interrupts(struct drm_device *dev)
3647{
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649
3650 spin_lock_irq(&dev_priv->irq_lock);
3651 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3652 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a
BW		 3653 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3654 spin_unlock_irq(&dev_priv->irq_lock);
3655}
3656
44fc7d5c
DV		 3657static void gen6_enable_rps_interrupts(struct drm_device *dev)
3658{
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660
3661 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3662 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3663 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
a6706b45 3664 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3665 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3666}
3667
3280e8b0
BW		 3668static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3669{
3670 /* All of these values are in units of 50MHz */
3671 dev_priv->rps.cur_freq = 0;
3672 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3673 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3674 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3675 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3676 /* XXX: only BYT has a special efficient freq */
3677 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3678 /* hw_max = RP0 until we check for overclocking */
3679 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3680
3681 /* Preserve min/max settings in case of re-init */
3682 if (dev_priv->rps.max_freq_softlimit == 0)
3683 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3684
3685 if (dev_priv->rps.min_freq_softlimit == 0)
3686 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3687}
3688
c76bb61a
DS		 3689static void bdw_sw_calculate_freq(struct drm_device *dev,
3690 struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0)
3691{
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 u64 busy = 0;
3694 u32 busyness_pct = 0;
3695 u32 elapsed_time = 0;
3696 u16 new_freq = 0;
3697
3698 if (!c || !cur_time || !c0)
3699 return;
3700
3701 if (0 == c->last_c0)
3702 goto out;
3703
3704 /* Check Evaluation interval */
3705 elapsed_time = *cur_time - c->last_ts;
3706 if (elapsed_time < c->eval_interval)
3707 return;
3708
3709 mutex_lock(&dev_priv->rps.hw_lock);
3710
3711 /*
3712 * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3713 * Whole busyness_pct calculation should be
3714 * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3715 * busyness_pct = (u32)(busy * 100 / elapsed_time);
3716 * The final formula is to simplify CPU calculation
3717 */
3718 busy = (u64)(*c0 - c->last_c0) << 12;
3719 do_div(busy, elapsed_time);
3720 busyness_pct = (u32)busy;
3721
3722 if (c->is_up && busyness_pct >= c->it_threshold_pct)
3723 new_freq = (u16)dev_priv->rps.cur_freq + 3;
3724 if (!c->is_up && busyness_pct <= c->it_threshold_pct)
3725 new_freq = (u16)dev_priv->rps.cur_freq - 1;
3726
3727 /* Adjust to new frequency busyness and compare with threshold */
3728 if (0 != new_freq) {
3729 if (new_freq > dev_priv->rps.max_freq_softlimit)
3730 new_freq = dev_priv->rps.max_freq_softlimit;
3731 else if (new_freq < dev_priv->rps.min_freq_softlimit)
3732 new_freq = dev_priv->rps.min_freq_softlimit;
3733
3734 gen6_set_rps(dev, new_freq);
3735 }
3736
3737 mutex_unlock(&dev_priv->rps.hw_lock);
3738
3739out:
3740 c->last_c0 = *c0;
3741 c->last_ts = *cur_time;
3742}
3743
3744static void gen8_set_frequency_RP0(struct work_struct *work)
3745{
3746 struct intel_rps_bdw_turbo *p_bdw_turbo =
3747 container_of(work, struct intel_rps_bdw_turbo, work_max_freq);
3748 struct intel_gen6_power_mgmt *p_power_mgmt =
3749 container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo);
3750 struct drm_i915_private *dev_priv =
3751 container_of(p_power_mgmt, struct drm_i915_private, rps);
3752
3753 mutex_lock(&dev_priv->rps.hw_lock);
3754 gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq);
3755 mutex_unlock(&dev_priv->rps.hw_lock);
3756}
3757
3758static void flip_active_timeout_handler(unsigned long var)
3759{
3760 struct drm_i915_private *dev_priv = (struct drm_i915_private *) var;
3761
3762 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3763 atomic_set(&dev_priv->rps.sw_turbo.flip_received, false);
3764
3765 queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq);
3766}
3767
3768void bdw_software_turbo(struct drm_device *dev)
3769{
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771
3772 u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */
3773 u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */
3774
3775 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up,
3776 &current_time, &current_c0);
3777 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down,
3778 &current_time, &current_c0);
3779}
3780
6edee7f3
BW		 3781static void gen8_enable_rps(struct drm_device *dev)
3782{
3783 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3784 struct intel_engine_cs *ring;
6edee7f3 3785 uint32_t rc6_mask = 0, rp_state_cap;
c76bb61a
DS		 3786 uint32_t threshold_up_pct, threshold_down_pct;
3787 uint32_t ei_up, ei_down; /* up and down evaluation interval */
3788 u32 rp_ctl_flag;
6edee7f3
BW		 3789 int unused;
3790
c76bb61a
DS		 3791 /* Use software Turbo for BDW */
3792 dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev);
3793
6edee7f3
BW		 3794 /* 1a: Software RC state - RC0 */
3795 I915_WRITE(GEN6_RC_STATE, 0);
3796
3797 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3798 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3799 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3800
3801 /* 2a: Disable RC states. */
3802 I915_WRITE(GEN6_RC_CONTROL, 0);
3803
3804 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3805 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3806
3807 /* 2b: Program RC6 thresholds.*/
3808 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3809 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3810 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3811 for_each_ring(ring, dev_priv, unused)
3812 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3813 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 3814 if (IS_BROADWELL(dev))
3815 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3816 else
3817 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 3818
3819 /* 3: Enable RC6 */
3820 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3821 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3822 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 3823 if (IS_BROADWELL(dev))
3824 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3825 GEN7_RC_CTL_TO_MODE |
3826 rc6_mask);
3827 else
3828 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3829 GEN6_RC_CTL_EI_MODE(1) |
3830 rc6_mask);
6edee7f3
BW		 3831
3832 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3833 I915_WRITE(GEN6_RPNSWREQ,
3834 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3835 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3836 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
c76bb61a
DS		 3837 ei_up = 84480; /* 84.48ms */
3838 ei_down = 448000;
3839 threshold_up_pct = 90; /* x percent busy */
3840 threshold_down_pct = 70;
3841
3842 if (dev_priv->rps.is_bdw_sw_turbo) {
3843 dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct;
3844 dev_priv->rps.sw_turbo.up.eval_interval = ei_up;
3845 dev_priv->rps.sw_turbo.up.is_up = true;
3846 dev_priv->rps.sw_turbo.up.last_ts = 0;
3847 dev_priv->rps.sw_turbo.up.last_c0 = 0;
3848
3849 dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct;
3850 dev_priv->rps.sw_turbo.down.eval_interval = ei_down;
3851 dev_priv->rps.sw_turbo.down.is_up = false;
3852 dev_priv->rps.sw_turbo.down.last_ts = 0;
3853 dev_priv->rps.sw_turbo.down.last_c0 = 0;
3854
3855 /* Start the timer to track if flip comes*/
3856 dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */
3857
3858 init_timer(&dev_priv->rps.sw_turbo.flip_timer);
3859 dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler;
3860 dev_priv->rps.sw_turbo.flip_timer.data = (unsigned long) dev_priv;
3861 dev_priv->rps.sw_turbo.flip_timer.expires =
3862 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
3863 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
3864 INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0);
3865
3866 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
3867 } else {
3868 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3869 * 1 second timeout*/
3870 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000));
3871
3872 /* Docs recommend 900MHz, and 300 MHz respectively */
3873 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3874 dev_priv->rps.max_freq_softlimit << 24 |
3875 dev_priv->rps.min_freq_softlimit << 16);
3876
3877 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3878 FREQ_1_28_US(ei_up * threshold_up_pct / 100));
3879 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3880 FREQ_1_28_US(ei_down * threshold_down_pct / 100));
3881 I915_WRITE(GEN6_RP_UP_EI,
3882 FREQ_1_28_US(ei_up));
3883 I915_WRITE(GEN6_RP_DOWN_EI,
3884 FREQ_1_28_US(ei_down));
3885
3886 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3887 }
6edee7f3
BW		 3888
3889 /* 5: Enable RPS */
c76bb61a
DS		 3890 rp_ctl_flag = GEN6_RP_MEDIA_TURBO |
3891 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3892 GEN6_RP_MEDIA_IS_GFX |
3893 GEN6_RP_UP_BUSY_AVG |
3894 GEN6_RP_DOWN_IDLE_AVG;
3895 if (!dev_priv->rps.is_bdw_sw_turbo)
3896 rp_ctl_flag |= GEN6_RP_ENABLE;
3897
3898 I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag);
3899
3900 /* 6: Ring frequency + overclocking
3901 * (our driver does this later */
6edee7f3 3902 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
c76bb61a
DS		 3903 if (!dev_priv->rps.is_bdw_sw_turbo)
3904 gen8_enable_rps_interrupts(dev);
6edee7f3 3905
c8d9a590 3906 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3907}
3908
79f5b2c7 3909static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3910{
79f5b2c7 3911 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3912 struct intel_engine_cs *ring;
2a5913a8 3913 u32 rp_state_cap;
d060c169 3914 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3915 u32 gtfifodbg;
2b4e57bd 3916 int rc6_mode;
42c0526c 3917 int i, ret;
2b4e57bd 3918
4fc688ce 3919 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3920
2b4e57bd
ED		 3921 /* Here begins a magic sequence of register writes to enable
3922 * auto-downclocking.
3923 *
3924 * Perhaps there might be some value in exposing these to
3925 * userspace...
3926 */
3927 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3928
3929 /* Clear the DBG now so we don't confuse earlier errors */
3930 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3931 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3932 I915_WRITE(GTFIFODBG, gtfifodbg);
3933 }
3934
c8d9a590 3935 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3936
7b9e0ae6 3937 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7b9e0ae6 3938
3280e8b0 3939 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3940
2b4e57bd
ED		 3941 /* disable the counters and set deterministic thresholds */
3942 I915_WRITE(GEN6_RC_CONTROL, 0);
3943
3944 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3945 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3946 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3947 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3948 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3949
b4519513
CW		 3950 for_each_ring(ring, dev_priv, i)
3951 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3952
3953 I915_WRITE(GEN6_RC_SLEEP, 0);
3954 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3955 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3956 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3957 else
3958 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3959 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3960 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3961
5a7dc92a 3962 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3963 rc6_mode = intel_enable_rc6(dev_priv->dev);
3964 if (rc6_mode & INTEL_RC6_ENABLE)
3965 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3966
5a7dc92a
ED		 3967 /* We don't use those on Haswell */
3968 if (!IS_HASWELL(dev)) {
3969 if (rc6_mode & INTEL_RC6p_ENABLE)
3970 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3971
5a7dc92a
ED		 3972 if (rc6_mode & INTEL_RC6pp_ENABLE)
3973 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3974 }
2b4e57bd 3975
dc39fff7 3976 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3977
3978 I915_WRITE(GEN6_RC_CONTROL,
3979 rc6_mask |
3980 GEN6_RC_CTL_EI_MODE(1) |
3981 GEN6_RC_CTL_HW_ENABLE);
3982
dd75fdc8
CW		 3983 /* Power down if completely idle for over 50ms */
3984 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3985 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3986
42c0526c 3987 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3988 if (ret)
42c0526c 3989 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3990
3991 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3992 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3993 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3994 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3995 (pcu_mbox & 0xff) * 50);
b39fb297 3996 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3997 }
3998
dd75fdc8 3999 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 4000 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 4001
44fc7d5c 4002 gen6_enable_rps_interrupts(dev);
2b4e57bd 4003
31643d54
BW		 4004 rc6vids = 0;
4005 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4006 if (IS_GEN6(dev) && ret) {
4007 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4008 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4009 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4010 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4011 rc6vids &= 0xffff00;
4012 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4013 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4014 if (ret)
4015 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4016 }
4017
c8d9a590 4018 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4019}
4020
c2bc2fc5 4021static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4022{
79f5b2c7 4023 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4024 int min_freq = 15;
3ebecd07
CW		 4025 unsigned int gpu_freq;
4026 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4027 int scaling_factor = 180;
eda79642 4028 struct cpufreq_policy *policy;
2b4e57bd 4029
4fc688ce 4030 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4031
eda79642
BW		 4032 policy = cpufreq_cpu_get(0);
4033 if (policy) {
4034 max_ia_freq = policy->cpuinfo.max_freq;
4035 cpufreq_cpu_put(policy);
4036 } else {
4037 /*
4038 * Default to measured freq if none found, PCU will ensure we
4039 * don't go over
4040 */
2b4e57bd 4041 max_ia_freq = tsc_khz;
eda79642 4042 }
2b4e57bd
ED		 4043
4044 /* Convert from kHz to MHz */
4045 max_ia_freq /= 1000;
4046
153b4b95 4047 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4048 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4049 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4050
2b4e57bd
ED		 4051 /*
4052 * For each potential GPU frequency, load a ring frequency we'd like
4053 * to use for memory access. We do this by specifying the IA frequency
4054 * the PCU should use as a reference to determine the ring frequency.
4055 */
b39fb297 4056 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 4057 gpu_freq--) {
b39fb297 4058 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 4059 unsigned int ia_freq = 0, ring_freq = 0;
4060
46c764d4
BW		 4061 if (INTEL_INFO(dev)->gen >= 8) {
4062 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4063 ring_freq = max(min_ring_freq, gpu_freq);
4064 } else if (IS_HASWELL(dev)) {
f6aca45c 4065 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4066 ring_freq = max(min_ring_freq, ring_freq);
4067 /* leave ia_freq as the default, chosen by cpufreq */
4068 } else {
4069 /* On older processors, there is no separate ring
4070 * clock domain, so in order to boost the bandwidth
4071 * of the ring, we need to upclock the CPU (ia_freq).
4072 *
4073 * For GPU frequencies less than 750MHz,
4074 * just use the lowest ring freq.
4075 */
4076 if (gpu_freq < min_freq)
4077 ia_freq = 800;
4078 else
4079 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4080 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4081 }
2b4e57bd 4082
42c0526c
BW		 4083 sandybridge_pcode_write(dev_priv,
4084 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4085 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4086 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4087 gpu_freq);
2b4e57bd 4088 }
2b4e57bd
ED		 4089}
4090
c2bc2fc5
ID		 4091void gen6_update_ring_freq(struct drm_device *dev)
4092{
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094
4095 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4096 return;
4097
4098 mutex_lock(&dev_priv->rps.hw_lock);
4099 __gen6_update_ring_freq(dev);
4100 mutex_unlock(&dev_priv->rps.hw_lock);
4101}
4102
03af2045 4103static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 4104{
4105 u32 val, rp0;
4106
4107 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4108 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4109
4110 return rp0;
4111}
4112
4113static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4114{
4115 u32 val, rpe;
4116
4117 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4118 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4119
4120 return rpe;
4121}
4122
7707df4a
D		 4123static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4124{
4125 u32 val, rp1;
4126
4127 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4128 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4129
4130 return rp1;
4131}
4132
03af2045 4133static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 4134{
4135 u32 val, rpn;
4136
4137 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4138 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4139 return rpn;
4140}
4141
f8f2b001
D		 4142static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4143{
4144 u32 val, rp1;
4145
4146 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4147
4148 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4149
4150 return rp1;
4151}
4152
03af2045 4153static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4154{
4155 u32 val, rp0;
4156
64936258 4157 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4158
4159 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4160 /* Clamp to max */
4161 rp0 = min_t(u32, rp0, 0xea);
4162
4163 return rp0;
4164}
4165
4166static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4167{
4168 u32 val, rpe;
4169
64936258 4170 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4171 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4172 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4173 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4174
4175 return rpe;
4176}
4177
03af2045 4178static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4179{
64936258 4180 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4181}
4182
ae48434c
ID		 4183/* Check that the pctx buffer wasn't move under us. */
4184static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4185{
4186 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4187
4188 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4189 dev_priv->vlv_pctx->stolen->start);
4190}
4191
38807746
D		 4192
4193/* Check that the pcbr address is not empty. */
4194static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4195{
4196 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4197
4198 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4199}
4200
4201static void cherryview_setup_pctx(struct drm_device *dev)
4202{
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 unsigned long pctx_paddr, paddr;
4205 struct i915_gtt *gtt = &dev_priv->gtt;
4206 u32 pcbr;
4207 int pctx_size = 32*1024;
4208
4209 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4210
4211 pcbr = I915_READ(VLV_PCBR);
4212 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4213 paddr = (dev_priv->mm.stolen_base +
4214 (gtt->stolen_size - pctx_size));
4215
4216 pctx_paddr = (paddr & (~4095));
4217 I915_WRITE(VLV_PCBR, pctx_paddr);
4218 }
4219}
4220
c9cddffc
JB		 4221static void valleyview_setup_pctx(struct drm_device *dev)
4222{
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 struct drm_i915_gem_object *pctx;
4225 unsigned long pctx_paddr;
4226 u32 pcbr;
4227 int pctx_size = 24*1024;
4228
17b0c1f7
ID		 4229 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4230
c9cddffc
JB		 4231 pcbr = I915_READ(VLV_PCBR);
4232 if (pcbr) {
4233 /* BIOS set it up already, grab the pre-alloc'd space */
4234 int pcbr_offset;
4235
4236 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4237 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4238 pcbr_offset,
190d6cd5 4239 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4240 pctx_size);
4241 goto out;
4242 }
4243
4244 /*
4245 * From the Gunit register HAS:
4246 * The Gfx driver is expected to program this register and ensure
4247 * proper allocation within Gfx stolen memory. For example, this
4248 * register should be programmed such than the PCBR range does not
4249 * overlap with other ranges, such as the frame buffer, protected
4250 * memory, or any other relevant ranges.
4251 */
4252 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4253 if (!pctx) {
4254 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4255 return;
4256 }
4257
4258 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4259 I915_WRITE(VLV_PCBR, pctx_paddr);
4260
4261out:
4262 dev_priv->vlv_pctx = pctx;
4263}
4264
ae48434c
ID		 4265static void valleyview_cleanup_pctx(struct drm_device *dev)
4266{
4267 struct drm_i915_private *dev_priv = dev->dev_private;
4268
4269 if (WARN_ON(!dev_priv->vlv_pctx))
4270 return;
4271
4272 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4273 dev_priv->vlv_pctx = NULL;
4274}
4275
4e80519e
ID		 4276static void valleyview_init_gt_powersave(struct drm_device *dev)
4277{
4278 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4279 u32 val;
4e80519e
ID		 4280
4281 valleyview_setup_pctx(dev);
4282
4283 mutex_lock(&dev_priv->rps.hw_lock);
4284
2bb25c17
VS		 4285 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4286 switch ((val >> 6) & 3) {
4287 case 0:
4288 case 1:
4289 dev_priv->mem_freq = 800;
4290 break;
4291 case 2:
4292 dev_priv->mem_freq = 1066;
4293 break;
4294 case 3:
4295 dev_priv->mem_freq = 1333;
4296 break;
4297 }
4298 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4299
4e80519e
ID		 4300 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4301 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4302 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4303 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4304 dev_priv->rps.max_freq);
4305
4306 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4307 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4308 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4309 dev_priv->rps.efficient_freq);
4310
f8f2b001
D		 4311 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4312 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4313 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4314 dev_priv->rps.rp1_freq);
4315
4e80519e
ID		 4316 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4317 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4318 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4319 dev_priv->rps.min_freq);
4320
4321 /* Preserve min/max settings in case of re-init */
4322 if (dev_priv->rps.max_freq_softlimit == 0)
4323 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4324
4325 if (dev_priv->rps.min_freq_softlimit == 0)
4326 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4327
4328 mutex_unlock(&dev_priv->rps.hw_lock);
4329}
4330
38807746
D		 4331static void cherryview_init_gt_powersave(struct drm_device *dev)
4332{
2b6b3a09 4333 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4334 u32 val;
2b6b3a09 4335
38807746 4336 cherryview_setup_pctx(dev);
2b6b3a09
D		 4337
4338 mutex_lock(&dev_priv->rps.hw_lock);
4339
2bb25c17
VS		 4340 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4341 switch ((val >> 2) & 0x7) {
4342 case 0:
4343 case 1:
4344 dev_priv->rps.cz_freq = 200;
4345 dev_priv->mem_freq = 1600;
4346 break;
4347 case 2:
4348 dev_priv->rps.cz_freq = 267;
4349 dev_priv->mem_freq = 1600;
4350 break;
4351 case 3:
4352 dev_priv->rps.cz_freq = 333;
4353 dev_priv->mem_freq = 2000;
4354 break;
4355 case 4:
4356 dev_priv->rps.cz_freq = 320;
4357 dev_priv->mem_freq = 1600;
4358 break;
4359 case 5:
4360 dev_priv->rps.cz_freq = 400;
4361 dev_priv->mem_freq = 1600;
4362 break;
4363 }
4364 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4365
2b6b3a09
D		 4366 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4367 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4368 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4369 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4370 dev_priv->rps.max_freq);
4371
4372 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4373 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4374 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4375 dev_priv->rps.efficient_freq);
4376
7707df4a
D		 4377 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4378 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4379 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4380 dev_priv->rps.rp1_freq);
4381
2b6b3a09
D		 4382 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4383 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4384 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4385 dev_priv->rps.min_freq);
4386
1c14762d
VS		 4387 WARN_ONCE((dev_priv->rps.max_freq |
4388 dev_priv->rps.efficient_freq |
4389 dev_priv->rps.rp1_freq |
4390 dev_priv->rps.min_freq) & 1,
4391 "Odd GPU freq values\n");
4392
2b6b3a09
D		 4393 /* Preserve min/max settings in case of re-init */
4394 if (dev_priv->rps.max_freq_softlimit == 0)
4395 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4396
4397 if (dev_priv->rps.min_freq_softlimit == 0)
4398 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4399
4400 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4401}
4402
4e80519e
ID		 4403static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4404{
4405 valleyview_cleanup_pctx(dev);
4406}
4407
38807746
D		 4408static void cherryview_enable_rps(struct drm_device *dev)
4409{
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 struct intel_engine_cs *ring;
2b6b3a09 4412 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4413 int i;
4414
4415 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4416
4417 gtfifodbg = I915_READ(GTFIFODBG);
4418 if (gtfifodbg) {
4419 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4420 gtfifodbg);
4421 I915_WRITE(GTFIFODBG, gtfifodbg);
4422 }
4423
4424 cherryview_check_pctx(dev_priv);
4425
4426 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4427 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4428 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4429
4430 /* 2a: Program RC6 thresholds.*/
4431 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4432 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4433 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4434
4435 for_each_ring(ring, dev_priv, i)
4436 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4437 I915_WRITE(GEN6_RC_SLEEP, 0);
4438
4439 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4440
4441 /* allows RC6 residency counter to work */
4442 I915_WRITE(VLV_COUNTER_CONTROL,
4443 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4444 VLV_MEDIA_RC6_COUNT_EN |
4445 VLV_RENDER_RC6_COUNT_EN));
4446
4447 /* For now we assume BIOS is allocating and populating the PCBR */
4448 pcbr = I915_READ(VLV_PCBR);
4449
4450 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4451
4452 /* 3: Enable RC6 */
4453 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4454 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4455 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4456
4457 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4458
2b6b3a09
D		 4459 /* 4 Program defaults and thresholds for RPS*/
4460 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4461 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4462 I915_WRITE(GEN6_RP_UP_EI, 66000);
4463 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4464
4465 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4466
7405f42c
TR		 4467 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4468 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4469 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4470
2b6b3a09
D		 4471 /* 5: Enable RPS */
4472 I915_WRITE(GEN6_RP_CONTROL,
4473 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4474 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 4475 GEN6_RP_ENABLE |
4476 GEN6_RP_UP_BUSY_AVG |
4477 GEN6_RP_DOWN_IDLE_AVG);
4478
4479 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4480
4481 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4482 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4483
4484 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4485 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4486 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4487 dev_priv->rps.cur_freq);
4488
4489 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4490 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4491 dev_priv->rps.efficient_freq);
4492
4493 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4494
3497a562
D		 4495 gen8_enable_rps_interrupts(dev);
4496
38807746
D		 4497 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4498}
4499
0a073b84
JB		 4500static void valleyview_enable_rps(struct drm_device *dev)
4501{
4502 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4503 struct intel_engine_cs *ring;
2a5913a8 4504 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4505 int i;
4506
4507 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4508
ae48434c
ID		 4509 valleyview_check_pctx(dev_priv);
4510
0a073b84 4511 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4512 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4513 gtfifodbg);
0a073b84
JB		 4514 I915_WRITE(GTFIFODBG, gtfifodbg);
4515 }
4516
c8d9a590
D		 4517 /* If VLV, Forcewake all wells, else re-direct to regular path */
4518 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4519
4520 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4521 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4522 I915_WRITE(GEN6_RP_UP_EI, 66000);
4523 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4524
4525 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
31685c25 4526 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
0a073b84
JB		 4527
4528 I915_WRITE(GEN6_RP_CONTROL,
4529 GEN6_RP_MEDIA_TURBO |
4530 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4531 GEN6_RP_MEDIA_IS_GFX |
4532 GEN6_RP_ENABLE |
4533 GEN6_RP_UP_BUSY_AVG |
4534 GEN6_RP_DOWN_IDLE_CONT);
4535
4536 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4537 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4538 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4539
4540 for_each_ring(ring, dev_priv, i)
4541 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4542
2f0aa304 4543 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4544
4545 /* allows RC6 residency counter to work */
49798eb2 4546 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 4547 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4548 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 4549 VLV_MEDIA_RC6_COUNT_EN |
4550 VLV_RENDER_RC6_COUNT_EN));
31685c25 4551
a2b23fe0 4552 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4553 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4554
4555 intel_print_rc6_info(dev, rc6_mode);
4556
a2b23fe0 4557 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4558
64936258 4559 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4560
4561 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4562 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4563
b39fb297 4564 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4565 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4566 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4567 dev_priv->rps.cur_freq);
0a073b84 4568
73008b98 4569 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4570 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4571 dev_priv->rps.efficient_freq);
0a073b84 4572
b39fb297 4573 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4574
44fc7d5c 4575 gen6_enable_rps_interrupts(dev);
0a073b84 4576
c8d9a590 4577 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4578}
4579
930ebb46 4580void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4581{
4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583
3e373948 4584 if (dev_priv->ips.renderctx) {
d7f46fc4 4585 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4586 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4587 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4588 }
4589
3e373948 4590 if (dev_priv->ips.pwrctx) {
d7f46fc4 4591 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4592 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4593 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4594 }
4595}
4596
930ebb46 4597static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4598{
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600
4601 if (I915_READ(PWRCTXA)) {
4602 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4603 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4604 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4605 50);
4606
4607 I915_WRITE(PWRCTXA, 0);
4608 POSTING_READ(PWRCTXA);
4609
4610 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4611 POSTING_READ(RSTDBYCTL);
4612 }
2b4e57bd
ED		 4613}
4614
4615static int ironlake_setup_rc6(struct drm_device *dev)
4616{
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618
3e373948
DV		 4619 if (dev_priv->ips.renderctx == NULL)
4620 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4621 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4622 return -ENOMEM;
4623
3e373948
DV		 4624 if (dev_priv->ips.pwrctx == NULL)
4625 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4626 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4627 ironlake_teardown_rc6(dev);
4628 return -ENOMEM;
4629 }
4630
4631 return 0;
4632}
4633
930ebb46 4634static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4635{
4636 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4637 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4638 bool was_interruptible;
2b4e57bd
ED		 4639 int ret;
4640
4641 /* rc6 disabled by default due to repeated reports of hanging during
4642 * boot and resume.
4643 */
4644 if (!intel_enable_rc6(dev))
4645 return;
4646
79f5b2c7
DV		 4647 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4648
2b4e57bd 4649 ret = ironlake_setup_rc6(dev);
79f5b2c7 4650 if (ret)
2b4e57bd 4651 return;
2b4e57bd 4652
3e960501
CW		 4653 was_interruptible = dev_priv->mm.interruptible;
4654 dev_priv->mm.interruptible = false;
4655
2b4e57bd
ED		 4656 /*
4657 * GPU can automatically power down the render unit if given a page
4658 * to save state.
4659 */
6d90c952 4660 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4661 if (ret) {
4662 ironlake_teardown_rc6(dev);
3e960501 4663 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4664 return;
4665 }
4666
6d90c952
DV		 4667 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4668 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4669 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4670 MI_MM_SPACE_GTT |
4671 MI_SAVE_EXT_STATE_EN |
4672 MI_RESTORE_EXT_STATE_EN |
4673 MI_RESTORE_INHIBIT);
4674 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4675 intel_ring_emit(ring, MI_NOOP);
4676 intel_ring_emit(ring, MI_FLUSH);
4677 intel_ring_advance(ring);
2b4e57bd
ED		 4678
4679 /*
4680 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4681 * does an implicit flush, combined with MI_FLUSH above, it should be
4682 * safe to assume that renderctx is valid
4683 */
3e960501
CW		 4684 ret = intel_ring_idle(ring);
4685 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4686 if (ret) {
def27a58 4687 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4688 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4689 return;
4690 }
4691
f343c5f6 4692 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4693 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4694
91ca689a 4695 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4696}
4697
dde18883
ED		 4698static unsigned long intel_pxfreq(u32 vidfreq)
4699{
4700 unsigned long freq;
4701 int div = (vidfreq & 0x3f0000) >> 16;
4702 int post = (vidfreq & 0x3000) >> 12;
4703 int pre = (vidfreq & 0x7);
4704
4705 if (!pre)
4706 return 0;
4707
4708 freq = ((div * 133333) / ((1<<post) * pre));
4709
4710 return freq;
4711}
4712
eb48eb00
DV		 4713static const struct cparams {
4714 u16 i;
4715 u16 t;
4716 u16 m;
4717 u16 c;
4718} cparams[] = {
4719 { 1, 1333, 301, 28664 },
4720 { 1, 1066, 294, 24460 },
4721 { 1, 800, 294, 25192 },
4722 { 0, 1333, 276, 27605 },
4723 { 0, 1066, 276, 27605 },
4724 { 0, 800, 231, 23784 },
4725};
4726
f531dcb2 4727static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4728{
4729 u64 total_count, diff, ret;
4730 u32 count1, count2, count3, m = 0, c = 0;
4731 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4732 int i;
4733
02d71956
DV		 4734 assert_spin_locked(&mchdev_lock);
4735
20e4d407 4736 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4737
4738 /* Prevent division-by-zero if we are asking too fast.
4739 * Also, we don't get interesting results if we are polling
4740 * faster than once in 10ms, so just return the saved value
4741 * in such cases.
4742 */
4743 if (diff1 <= 10)
20e4d407 4744 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4745
4746 count1 = I915_READ(DMIEC);
4747 count2 = I915_READ(DDREC);
4748 count3 = I915_READ(CSIEC);
4749
4750 total_count = count1 + count2 + count3;
4751
4752 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4753 if (total_count < dev_priv->ips.last_count1) {
4754 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4755 diff += total_count;
4756 } else {
20e4d407 4757 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4758 }
4759
4760 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4761 if (cparams[i].i == dev_priv->ips.c_m &&
4762 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4763 m = cparams[i].m;
4764 c = cparams[i].c;
4765 break;
4766 }
4767 }
4768
4769 diff = div_u64(diff, diff1);
4770 ret = ((m * diff) + c);
4771 ret = div_u64(ret, 10);
4772
20e4d407
DV		 4773 dev_priv->ips.last_count1 = total_count;
4774 dev_priv->ips.last_time1 = now;
eb48eb00 4775
20e4d407 4776 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4777
4778 return ret;
4779}
4780
f531dcb2
CW		 4781unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4782{
3d13ef2e 4783 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4784 unsigned long val;
4785
3d13ef2e 4786 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4787 return 0;
4788
4789 spin_lock_irq(&mchdev_lock);
4790
4791 val = __i915_chipset_val(dev_priv);
4792
4793 spin_unlock_irq(&mchdev_lock);
4794
4795 return val;
4796}
4797
eb48eb00
DV		 4798unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4799{
4800 unsigned long m, x, b;
4801 u32 tsfs;
4802
4803 tsfs = I915_READ(TSFS);
4804
4805 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4806 x = I915_READ8(TR1);
4807
4808 b = tsfs & TSFS_INTR_MASK;
4809
4810 return ((m * x) / 127) - b;
4811}
4812
4813static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4814{
3d13ef2e 4815 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4816 static const struct v_table {
4817 u16 vd; /* in .1 mil */
4818 u16 vm; /* in .1 mil */
4819 } v_table[] = {
4820 { 0, 0, },
4821 { 375, 0, },
4822 { 500, 0, },
4823 { 625, 0, },
4824 { 750, 0, },
4825 { 875, 0, },
4826 { 1000, 0, },
4827 { 1125, 0, },
4828 { 4125, 3000, },
4829 { 4125, 3000, },
4830 { 4125, 3000, },
4831 { 4125, 3000, },
4832 { 4125, 3000, },
4833 { 4125, 3000, },
4834 { 4125, 3000, },
4835 { 4125, 3000, },
4836 { 4125, 3000, },
4837 { 4125, 3000, },
4838 { 4125, 3000, },
4839 { 4125, 3000, },
4840 { 4125, 3000, },
4841 { 4125, 3000, },
4842 { 4125, 3000, },
4843 { 4125, 3000, },
4844 { 4125, 3000, },
4845 { 4125, 3000, },
4846 { 4125, 3000, },
4847 { 4125, 3000, },
4848 { 4125, 3000, },
4849 { 4125, 3000, },
4850 { 4125, 3000, },
4851 { 4125, 3000, },
4852 { 4250, 3125, },
4853 { 4375, 3250, },
4854 { 4500, 3375, },
4855 { 4625, 3500, },
4856 { 4750, 3625, },
4857 { 4875, 3750, },
4858 { 5000, 3875, },
4859 { 5125, 4000, },
4860 { 5250, 4125, },
4861 { 5375, 4250, },
4862 { 5500, 4375, },
4863 { 5625, 4500, },
4864 { 5750, 4625, },
4865 { 5875, 4750, },
4866 { 6000, 4875, },
4867 { 6125, 5000, },
4868 { 6250, 5125, },
4869 { 6375, 5250, },
4870 { 6500, 5375, },
4871 { 6625, 5500, },
4872 { 6750, 5625, },
4873 { 6875, 5750, },
4874 { 7000, 5875, },
4875 { 7125, 6000, },
4876 { 7250, 6125, },
4877 { 7375, 6250, },
4878 { 7500, 6375, },
4879 { 7625, 6500, },
4880 { 7750, 6625, },
4881 { 7875, 6750, },
4882 { 8000, 6875, },
4883 { 8125, 7000, },
4884 { 8250, 7125, },
4885 { 8375, 7250, },
4886 { 8500, 7375, },
4887 { 8625, 7500, },
4888 { 8750, 7625, },
4889 { 8875, 7750, },
4890 { 9000, 7875, },
4891 { 9125, 8000, },
4892 { 9250, 8125, },
4893 { 9375, 8250, },
4894 { 9500, 8375, },
4895 { 9625, 8500, },
4896 { 9750, 8625, },
4897 { 9875, 8750, },
4898 { 10000, 8875, },
4899 { 10125, 9000, },
4900 { 10250, 9125, },
4901 { 10375, 9250, },
4902 { 10500, 9375, },
4903 { 10625, 9500, },
4904 { 10750, 9625, },
4905 { 10875, 9750, },
4906 { 11000, 9875, },
4907 { 11125, 10000, },
4908 { 11250, 10125, },
4909 { 11375, 10250, },
4910 { 11500, 10375, },
4911 { 11625, 10500, },
4912 { 11750, 10625, },
4913 { 11875, 10750, },
4914 { 12000, 10875, },
4915 { 12125, 11000, },
4916 { 12250, 11125, },
4917 { 12375, 11250, },
4918 { 12500, 11375, },
4919 { 12625, 11500, },
4920 { 12750, 11625, },
4921 { 12875, 11750, },
4922 { 13000, 11875, },
4923 { 13125, 12000, },
4924 { 13250, 12125, },
4925 { 13375, 12250, },
4926 { 13500, 12375, },
4927 { 13625, 12500, },
4928 { 13750, 12625, },
4929 { 13875, 12750, },
4930 { 14000, 12875, },
4931 { 14125, 13000, },
4932 { 14250, 13125, },
4933 { 14375, 13250, },
4934 { 14500, 13375, },
4935 { 14625, 13500, },
4936 { 14750, 13625, },
4937 { 14875, 13750, },
4938 { 15000, 13875, },
4939 { 15125, 14000, },
4940 { 15250, 14125, },
4941 { 15375, 14250, },
4942 { 15500, 14375, },
4943 { 15625, 14500, },
4944 { 15750, 14625, },
4945 { 15875, 14750, },
4946 { 16000, 14875, },
4947 { 16125, 15000, },
4948 };
3d13ef2e 4949 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4950 return v_table[pxvid].vm;
4951 else
4952 return v_table[pxvid].vd;
4953}
4954
02d71956 4955static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 4956{
5ed0bdf2 4957 u64 now, diff, diffms;
eb48eb00
DV		 4958 u32 count;
4959
02d71956 4960 assert_spin_locked(&mchdev_lock);
eb48eb00 4961
5ed0bdf2
TG		 4962 now = ktime_get_raw_ns();
4963 diffms = now - dev_priv->ips.last_time2;
4964 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 4965
4966 /* Don't divide by 0 */
eb48eb00
DV		 4967 if (!diffms)
4968 return;
4969
4970 count = I915_READ(GFXEC);
4971
20e4d407
DV		 4972 if (count < dev_priv->ips.last_count2) {
4973 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4974 diff += count;
4975 } else {
20e4d407 4976 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4977 }
4978
20e4d407
DV		 4979 dev_priv->ips.last_count2 = count;
4980 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4981
4982 /* More magic constants... */
4983 diff = diff * 1181;
4984 diff = div_u64(diff, diffms * 10);
20e4d407 4985 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4986}
4987
02d71956
DV		 4988void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4989{
3d13ef2e
DL		 4990 struct drm_device *dev = dev_priv->dev;
4991
4992 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4993 return;
4994
9270388e 4995 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4996
4997 __i915_update_gfx_val(dev_priv);
4998
9270388e 4999 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5000}
5001
f531dcb2 5002static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5003{
5004 unsigned long t, corr, state1, corr2, state2;
5005 u32 pxvid, ext_v;
5006
02d71956
DV		 5007 assert_spin_locked(&mchdev_lock);
5008
b39fb297 5009 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5010 pxvid = (pxvid >> 24) & 0x7f;
5011 ext_v = pvid_to_extvid(dev_priv, pxvid);
5012
5013 state1 = ext_v;
5014
5015 t = i915_mch_val(dev_priv);
5016
5017 /* Revel in the empirically derived constants */
5018
5019 /* Correction factor in 1/100000 units */
5020 if (t > 80)
5021 corr = ((t * 2349) + 135940);
5022 else if (t >= 50)
5023 corr = ((t * 964) + 29317);
5024 else /* < 50 */
5025 corr = ((t * 301) + 1004);
5026
5027 corr = corr * ((150142 * state1) / 10000 - 78642);
5028 corr /= 100000;
20e4d407 5029 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5030
5031 state2 = (corr2 * state1) / 10000;
5032 state2 /= 100; /* convert to mW */
5033
02d71956 5034 __i915_update_gfx_val(dev_priv);
eb48eb00 5035
20e4d407 5036 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5037}
5038
f531dcb2
CW		 5039unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5040{
3d13ef2e 5041 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5042 unsigned long val;
5043
3d13ef2e 5044 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5045 return 0;
5046
5047 spin_lock_irq(&mchdev_lock);
5048
5049 val = __i915_gfx_val(dev_priv);
5050
5051 spin_unlock_irq(&mchdev_lock);
5052
5053 return val;
5054}
5055
eb48eb00
DV		 5056/**
5057 * i915_read_mch_val - return value for IPS use
5058 *
5059 * Calculate and return a value for the IPS driver to use when deciding whether
5060 * we have thermal and power headroom to increase CPU or GPU power budget.
5061 */
5062unsigned long i915_read_mch_val(void)
5063{
5064 struct drm_i915_private *dev_priv;
5065 unsigned long chipset_val, graphics_val, ret = 0;
5066
9270388e 5067 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5068 if (!i915_mch_dev)
5069 goto out_unlock;
5070 dev_priv = i915_mch_dev;
5071
f531dcb2
CW		 5072 chipset_val = __i915_chipset_val(dev_priv);
5073 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5074
5075 ret = chipset_val + graphics_val;
5076
5077out_unlock:
9270388e 5078 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5079
5080 return ret;
5081}
5082EXPORT_SYMBOL_GPL(i915_read_mch_val);
5083
5084/**
5085 * i915_gpu_raise - raise GPU frequency limit
5086 *
5087 * Raise the limit; IPS indicates we have thermal headroom.
5088 */
5089bool i915_gpu_raise(void)
5090{
5091 struct drm_i915_private *dev_priv;
5092 bool ret = true;
5093
9270388e 5094 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5095 if (!i915_mch_dev) {
5096 ret = false;
5097 goto out_unlock;
5098 }
5099 dev_priv = i915_mch_dev;
5100
20e4d407
DV		 5101 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5102 dev_priv->ips.max_delay--;
eb48eb00
DV		 5103
5104out_unlock:
9270388e 5105 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5106
5107 return ret;
5108}
5109EXPORT_SYMBOL_GPL(i915_gpu_raise);
5110
5111/**
5112 * i915_gpu_lower - lower GPU frequency limit
5113 *
5114 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5115 * frequency maximum.
5116 */
5117bool i915_gpu_lower(void)
5118{
5119 struct drm_i915_private *dev_priv;
5120 bool ret = true;
5121
9270388e 5122 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5123 if (!i915_mch_dev) {
5124 ret = false;
5125 goto out_unlock;
5126 }
5127 dev_priv = i915_mch_dev;
5128
20e4d407
DV		 5129 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5130 dev_priv->ips.max_delay++;
eb48eb00
DV		 5131
5132out_unlock:
9270388e 5133 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5134
5135 return ret;
5136}
5137EXPORT_SYMBOL_GPL(i915_gpu_lower);
5138
5139/**
5140 * i915_gpu_busy - indicate GPU business to IPS
5141 *
5142 * Tell the IPS driver whether or not the GPU is busy.
5143 */
5144bool i915_gpu_busy(void)
5145{
5146 struct drm_i915_private *dev_priv;
a4872ba6 5147 struct intel_engine_cs *ring;
eb48eb00 5148 bool ret = false;
f047e395 5149 int i;
eb48eb00 5150
9270388e 5151 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5152 if (!i915_mch_dev)
5153 goto out_unlock;
5154 dev_priv = i915_mch_dev;
5155
f047e395
CW		 5156 for_each_ring(ring, dev_priv, i)
5157 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5158
5159out_unlock:
9270388e 5160 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5161
5162 return ret;
5163}
5164EXPORT_SYMBOL_GPL(i915_gpu_busy);
5165
5166/**
5167 * i915_gpu_turbo_disable - disable graphics turbo
5168 *
5169 * Disable graphics turbo by resetting the max frequency and setting the
5170 * current frequency to the default.
5171 */
5172bool i915_gpu_turbo_disable(void)
5173{
5174 struct drm_i915_private *dev_priv;
5175 bool ret = true;
5176
9270388e 5177 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5178 if (!i915_mch_dev) {
5179 ret = false;
5180 goto out_unlock;
5181 }
5182 dev_priv = i915_mch_dev;
5183
20e4d407 5184 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5185
20e4d407 5186 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5187 ret = false;
5188
5189out_unlock:
9270388e 5190 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5191
5192 return ret;
5193}
5194EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5195
5196/**
5197 * Tells the intel_ips driver that the i915 driver is now loaded, if
5198 * IPS got loaded first.
5199 *
5200 * This awkward dance is so that neither module has to depend on the
5201 * other in order for IPS to do the appropriate communication of
5202 * GPU turbo limits to i915.
5203 */
5204static void
5205ips_ping_for_i915_load(void)
5206{
5207 void (*link)(void);
5208
5209 link = symbol_get(ips_link_to_i915_driver);
5210 if (link) {
5211 link();
5212 symbol_put(ips_link_to_i915_driver);
5213 }
5214}
5215
5216void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5217{
02d71956
DV		 5218 /* We only register the i915 ips part with intel-ips once everything is
5219 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5220 spin_lock_irq(&mchdev_lock);
eb48eb00 5221 i915_mch_dev = dev_priv;
9270388e 5222 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5223
5224 ips_ping_for_i915_load();
5225}
5226
5227void intel_gpu_ips_teardown(void)
5228{
9270388e 5229 spin_lock_irq(&mchdev_lock);
eb48eb00 5230 i915_mch_dev = NULL;
9270388e 5231 spin_unlock_irq(&mchdev_lock);
eb48eb00 5232}
76c3552f 5233
8090c6b9 5234static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5235{
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 u32 lcfuse;
5238 u8 pxw[16];
5239 int i;
5240
5241 /* Disable to program */
5242 I915_WRITE(ECR, 0);
5243 POSTING_READ(ECR);
5244
5245 /* Program energy weights for various events */
5246 I915_WRITE(SDEW, 0x15040d00);
5247 I915_WRITE(CSIEW0, 0x007f0000);
5248 I915_WRITE(CSIEW1, 0x1e220004);
5249 I915_WRITE(CSIEW2, 0x04000004);
5250
5251 for (i = 0; i < 5; i++)
5252 I915_WRITE(PEW + (i * 4), 0);
5253 for (i = 0; i < 3; i++)
5254 I915_WRITE(DEW + (i * 4), 0);
5255
5256 /* Program P-state weights to account for frequency power adjustment */
5257 for (i = 0; i < 16; i++) {
5258 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5259 unsigned long freq = intel_pxfreq(pxvidfreq);
5260 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5261 PXVFREQ_PX_SHIFT;
5262 unsigned long val;
5263
5264 val = vid * vid;
5265 val *= (freq / 1000);
5266 val *= 255;
5267 val /= (127*127*900);
5268 if (val > 0xff)
5269 DRM_ERROR("bad pxval: %ld\n", val);
5270 pxw[i] = val;
5271 }
5272 /* Render standby states get 0 weight */
5273 pxw[14] = 0;
5274 pxw[15] = 0;
5275
5276 for (i = 0; i < 4; i++) {
5277 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5278 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5279 I915_WRITE(PXW + (i * 4), val);
5280 }
5281
5282 /* Adjust magic regs to magic values (more experimental results) */
5283 I915_WRITE(OGW0, 0);
5284 I915_WRITE(OGW1, 0);
5285 I915_WRITE(EG0, 0x00007f00);
5286 I915_WRITE(EG1, 0x0000000e);
5287 I915_WRITE(EG2, 0x000e0000);
5288 I915_WRITE(EG3, 0x68000300);
5289 I915_WRITE(EG4, 0x42000000);
5290 I915_WRITE(EG5, 0x00140031);
5291 I915_WRITE(EG6, 0);
5292 I915_WRITE(EG7, 0);
5293
5294 for (i = 0; i < 8; i++)
5295 I915_WRITE(PXWL + (i * 4), 0);
5296
5297 /* Enable PMON + select events */
5298 I915_WRITE(ECR, 0x80000019);
5299
5300 lcfuse = I915_READ(LCFUSE02);
5301
20e4d407 5302 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5303}
5304
ae48434c
ID		 5305void intel_init_gt_powersave(struct drm_device *dev)
5306{
e6069ca8
ID		 5307 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5308
38807746
D		 5309 if (IS_CHERRYVIEW(dev))
5310 cherryview_init_gt_powersave(dev);
5311 else if (IS_VALLEYVIEW(dev))
4e80519e 5312 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5313}
5314
5315void intel_cleanup_gt_powersave(struct drm_device *dev)
5316{
38807746
D		 5317 if (IS_CHERRYVIEW(dev))
5318 return;
5319 else if (IS_VALLEYVIEW(dev))
4e80519e 5320 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5321}
5322
156c7ca0
JB		 5323/**
5324 * intel_suspend_gt_powersave - suspend PM work and helper threads
5325 * @dev: drm device
5326 *
5327 * We don't want to disable RC6 or other features here, we just want
5328 * to make sure any work we've queued has finished and won't bother
5329 * us while we're suspended.
5330 */
5331void intel_suspend_gt_powersave(struct drm_device *dev)
5332{
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334
5335 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5336 WARN_ON(intel_irqs_enabled(dev_priv));
156c7ca0
JB		 5337
5338 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5339
5340 cancel_work_sync(&dev_priv->rps.work);
b47adc17
D		 5341
5342 /* Force GPU to min freq during suspend */
5343 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5344}
5345
8090c6b9
DV		 5346void intel_disable_gt_powersave(struct drm_device *dev)
5347{
1a01ab3b
JB		 5348 struct drm_i915_private *dev_priv = dev->dev_private;
5349
fd0c0642 5350 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5351 WARN_ON(intel_irqs_enabled(dev_priv));
fd0c0642 5352
930ebb46 5353 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5354 ironlake_disable_drps(dev);
930ebb46 5355 ironlake_disable_rc6(dev);
38807746 5356 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5357 intel_suspend_gt_powersave(dev);
e494837a 5358
4fc688ce 5359 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 5360 if (IS_CHERRYVIEW(dev))
5361 cherryview_disable_rps(dev);
5362 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5363 valleyview_disable_rps(dev);
5364 else
5365 gen6_disable_rps(dev);
c0951f0c 5366 dev_priv->rps.enabled = false;
4fc688ce 5367 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5368 }
8090c6b9
DV		 5369}
5370
1a01ab3b
JB		 5371static void intel_gen6_powersave_work(struct work_struct *work)
5372{
5373 struct drm_i915_private *dev_priv =
5374 container_of(work, struct drm_i915_private,
5375 rps.delayed_resume_work.work);
5376 struct drm_device *dev = dev_priv->dev;
5377
c76bb61a
DS		 5378 dev_priv->rps.is_bdw_sw_turbo = false;
5379
4fc688ce 5380 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5381
38807746
D		 5382 if (IS_CHERRYVIEW(dev)) {
5383 cherryview_enable_rps(dev);
5384 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5385 valleyview_enable_rps(dev);
6edee7f3
BW		 5386 } else if (IS_BROADWELL(dev)) {
5387 gen8_enable_rps(dev);
c2bc2fc5 5388 __gen6_update_ring_freq(dev);
0a073b84
JB		 5389 } else {
5390 gen6_enable_rps(dev);
c2bc2fc5 5391 __gen6_update_ring_freq(dev);
0a073b84 5392 }
c0951f0c 5393 dev_priv->rps.enabled = true;
4fc688ce 5394 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5395
5396 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5397}
5398
8090c6b9
DV		 5399void intel_enable_gt_powersave(struct drm_device *dev)
5400{
1a01ab3b
JB		 5401 struct drm_i915_private *dev_priv = dev->dev_private;
5402
8090c6b9 5403 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5404 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 5405 ironlake_enable_drps(dev);
5406 ironlake_enable_rc6(dev);
5407 intel_init_emon(dev);
dc1d0136 5408 mutex_unlock(&dev->struct_mutex);
38807746 5409 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5410 /*
5411 * PCU communication is slow and this doesn't need to be
5412 * done at any specific time, so do this out of our fast path
5413 * to make resume and init faster.
c6df39b5
ID		 5414 *
5415 * We depend on the HW RC6 power context save/restore
5416 * mechanism when entering D3 through runtime PM suspend. So
5417 * disable RPM until RPS/RC6 is properly setup. We can only
5418 * get here via the driver load/system resume/runtime resume
5419 * paths, so the _noresume version is enough (and in case of
5420 * runtime resume it's necessary).
1a01ab3b 5421 */
c6df39b5
ID		 5422 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5423 round_jiffies_up_relative(HZ)))
5424 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5425 }
5426}
5427
c6df39b5
ID		 5428void intel_reset_gt_powersave(struct drm_device *dev)
5429{
5430 struct drm_i915_private *dev_priv = dev->dev_private;
5431
5432 dev_priv->rps.enabled = false;
5433 intel_enable_gt_powersave(dev);
5434}
5435
3107bd48
DV		 5436static void ibx_init_clock_gating(struct drm_device *dev)
5437{
5438 struct drm_i915_private *dev_priv = dev->dev_private;
5439
5440 /*
5441 * On Ibex Peak and Cougar Point, we need to disable clock
5442 * gating for the panel power sequencer or it will fail to
5443 * start up when no ports are active.
5444 */
5445 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5446}
5447
0e088b8f
VS		 5448static void g4x_disable_trickle_feed(struct drm_device *dev)
5449{
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 int pipe;
5452
055e393f 5453 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5454 I915_WRITE(DSPCNTR(pipe),
5455 I915_READ(DSPCNTR(pipe)) |
5456 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5457 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5458 }
5459}
5460
017636cc
VS		 5461static void ilk_init_lp_watermarks(struct drm_device *dev)
5462{
5463 struct drm_i915_private *dev_priv = dev->dev_private;
5464
5465 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5466 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5467 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5468
5469 /*
5470 * Don't touch WM1S_LP_EN here.
5471 * Doing so could cause underruns.
5472 */
5473}
5474
1fa61106 5475static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5476{
5477 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5478 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5479
f1e8fa56
DL		 5480 /*
5481 * Required for FBC
5482 * WaFbcDisableDpfcClockGating:ilk
5483 */
4d47e4f5
DL		 5484 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5485 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5486 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5487
5488 I915_WRITE(PCH_3DCGDIS0,
5489 MARIUNIT_CLOCK_GATE_DISABLE |
5490 SVSMUNIT_CLOCK_GATE_DISABLE);
5491 I915_WRITE(PCH_3DCGDIS1,
5492 VFMUNIT_CLOCK_GATE_DISABLE);
5493
6f1d69b0
ED		 5494 /*
5495 * According to the spec the following bits should be set in
5496 * order to enable memory self-refresh
5497 * The bit 22/21 of 0x42004
5498 * The bit 5 of 0x42020
5499 * The bit 15 of 0x45000
5500 */
5501 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5502 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5503 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5504 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5505 I915_WRITE(DISP_ARB_CTL,
5506 (I915_READ(DISP_ARB_CTL) |
5507 DISP_FBC_WM_DIS));
017636cc
VS		 5508
5509 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5510
5511 /*
5512 * Based on the document from hardware guys the following bits
5513 * should be set unconditionally in order to enable FBC.
5514 * The bit 22 of 0x42000
5515 * The bit 22 of 0x42004
5516 * The bit 7,8,9 of 0x42020.
5517 */
5518 if (IS_IRONLAKE_M(dev)) {
4bb35334 5519 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5520 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5521 I915_READ(ILK_DISPLAY_CHICKEN1) |
5522 ILK_FBCQ_DIS);
5523 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5524 I915_READ(ILK_DISPLAY_CHICKEN2) |
5525 ILK_DPARB_GATE);
6f1d69b0
ED		 5526 }
5527
4d47e4f5
DL		 5528 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5529
6f1d69b0
ED		 5530 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5531 I915_READ(ILK_DISPLAY_CHICKEN2) |
5532 ILK_ELPIN_409_SELECT);
5533 I915_WRITE(_3D_CHICKEN2,
5534 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5535 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5536
ecdb4eb7 5537 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5538 I915_WRITE(CACHE_MODE_0,
5539 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5540
4e04632e
AG		 5541 /* WaDisable_RenderCache_OperationalFlush:ilk */
5542 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5543
0e088b8f 5544 g4x_disable_trickle_feed(dev);
bdad2b2f 5545
3107bd48
DV		 5546 ibx_init_clock_gating(dev);
5547}
5548
5549static void cpt_init_clock_gating(struct drm_device *dev)
5550{
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552 int pipe;
3f704fa2 5553 uint32_t val;
3107bd48
DV		 5554
5555 /*
5556 * On Ibex Peak and Cougar Point, we need to disable clock
5557 * gating for the panel power sequencer or it will fail to
5558 * start up when no ports are active.
5559 */
cd664078
JB		 5560 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5561 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5562 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5563 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5564 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5565 /* The below fixes the weird display corruption, a few pixels shifted
5566 * downward, on (only) LVDS of some HP laptops with IVY.
5567 */
055e393f 5568 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5569 val = I915_READ(TRANS_CHICKEN2(pipe));
5570 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5571 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5572 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5573 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5574 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5575 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5576 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5577 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5578 }
3107bd48 5579 /* WADP0ClockGatingDisable */
055e393f 5580 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5581 I915_WRITE(TRANS_CHICKEN1(pipe),
5582 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5583 }
6f1d69b0
ED		 5584}
5585
1d7aaa0c
DV		 5586static void gen6_check_mch_setup(struct drm_device *dev)
5587{
5588 struct drm_i915_private *dev_priv = dev->dev_private;
5589 uint32_t tmp;
5590
5591 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5592 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5593 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5594 tmp);
1d7aaa0c
DV		 5595}
5596
1fa61106 5597static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5598{
5599 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5600 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5601
231e54f6 5602 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5603
5604 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5605 I915_READ(ILK_DISPLAY_CHICKEN2) |
5606 ILK_ELPIN_409_SELECT);
5607
ecdb4eb7 5608 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5609 I915_WRITE(_3D_CHICKEN,
5610 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5611
ecdb4eb7 5612 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5613 if (IS_SNB_GT1(dev))
5614 I915_WRITE(GEN6_GT_MODE,
5615 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5616
4e04632e
AG		 5617 /* WaDisable_RenderCache_OperationalFlush:snb */
5618 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5619
8d85d272
VS		 5620 /*
5621 * BSpec recoomends 8x4 when MSAA is used,
5622 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5623 *
5624 * Note that PS/WM thread counts depend on the WIZ hashing
5625 * disable bit, which we don't touch here, but it's good
5626 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5627 */
5628 I915_WRITE(GEN6_GT_MODE,
5629 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5630
017636cc 5631 ilk_init_lp_watermarks(dev);
6f1d69b0 5632
6f1d69b0 5633 I915_WRITE(CACHE_MODE_0,
50743298 5634 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5635
5636 I915_WRITE(GEN6_UCGCTL1,
5637 I915_READ(GEN6_UCGCTL1) |
5638 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5639 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5640
5641 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5642 * gating disable must be set. Failure to set it results in
5643 * flickering pixels due to Z write ordering failures after
5644 * some amount of runtime in the Mesa "fire" demo, and Unigine
5645 * Sanctuary and Tropics, and apparently anything else with
5646 * alpha test or pixel discard.
5647 *
5648 * According to the spec, bit 11 (RCCUNIT) must also be set,
5649 * but we didn't debug actual testcases to find it out.
0f846f81 5650 *
ef59318c
VS		 5651 * WaDisableRCCUnitClockGating:snb
5652 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5653 */
5654 I915_WRITE(GEN6_UCGCTL2,
5655 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5656 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5657
5eb146dd 5658 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5659 I915_WRITE(_3D_CHICKEN3,
5660 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5661
e927ecde
VS		 5662 /*
5663 * Bspec says:
5664 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5665 * 3DSTATE_SF number of SF output attributes is more than 16."
5666 */
5667 I915_WRITE(_3D_CHICKEN3,
5668 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5669
6f1d69b0
ED		 5670 /*
5671 * According to the spec the following bits should be
5672 * set in order to enable memory self-refresh and fbc:
5673 * The bit21 and bit22 of 0x42000
5674 * The bit21 and bit22 of 0x42004
5675 * The bit5 and bit7 of 0x42020
5676 * The bit14 of 0x70180
5677 * The bit14 of 0x71180
4bb35334
DL		 5678 *
5679 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5680 */
5681 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5682 I915_READ(ILK_DISPLAY_CHICKEN1) |
5683 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5684 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5685 I915_READ(ILK_DISPLAY_CHICKEN2) |
5686 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5687 I915_WRITE(ILK_DSPCLK_GATE_D,
5688 I915_READ(ILK_DSPCLK_GATE_D) |
5689 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5690 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5691
0e088b8f 5692 g4x_disable_trickle_feed(dev);
f8f2ac9a 5693
3107bd48 5694 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5695
5696 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5697}
5698
5699static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5700{
5701 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5702
3aad9059 5703 /*
46680e0a 5704 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5705 *
5706 * This actually overrides the dispatch
5707 * mode for all thread types.
5708 */
6f1d69b0
ED		 5709 reg &= ~GEN7_FF_SCHED_MASK;
5710 reg |= GEN7_FF_TS_SCHED_HW;
5711 reg |= GEN7_FF_VS_SCHED_HW;
5712 reg |= GEN7_FF_DS_SCHED_HW;
5713
5714 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5715}
5716
17a303ec
PZ		 5717static void lpt_init_clock_gating(struct drm_device *dev)
5718{
5719 struct drm_i915_private *dev_priv = dev->dev_private;
5720
5721 /*
5722 * TODO: this bit should only be enabled when really needed, then
5723 * disabled when not needed anymore in order to save power.
5724 */
5725 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5726 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5727 I915_READ(SOUTH_DSPCLK_GATE_D) |
5728 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5729
5730 /* WADPOClockGatingDisable:hsw */
5731 I915_WRITE(_TRANSA_CHICKEN1,
5732 I915_READ(_TRANSA_CHICKEN1) |
5733 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5734}
5735
7d708ee4
ID		 5736static void lpt_suspend_hw(struct drm_device *dev)
5737{
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5739
5740 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5741 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5742
5743 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5744 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5745 }
5746}
5747
47c2bd97 5748static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 5749{
5750 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5751 enum pipe pipe;
1020a5c2
BW		 5752
5753 I915_WRITE(WM3_LP_ILK, 0);
5754 I915_WRITE(WM2_LP_ILK, 0);
5755 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5756
5757 /* FIXME(BDW): Check all the w/a, some might only apply to
5758 * pre-production hw. */
5759
c8966e10 5760
4afe8d33
BW		 5761 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5762
7f88da0c 5763 I915_WRITE(_3D_CHICKEN3,
b3f9ad93 5764 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
7f88da0c 5765
242a4018 5766
ab57fff1 5767 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5768 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5769
ab57fff1 5770 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5771 I915_WRITE(CHICKEN_PAR1_1,
5772 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5773
ab57fff1 5774 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 5775 for_each_pipe(dev_priv, pipe) {
07d27e20 5776 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5777 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5778 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5779 }
63801f21 5780
ab57fff1
BW		 5781 /* WaVSRefCountFullforceMissDisable:bdw */
5782 /* WaDSRefCountFullforceMissDisable:bdw */
5783 I915_WRITE(GEN7_FF_THREAD_MODE,
5784 I915_READ(GEN7_FF_THREAD_MODE) &
5785 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 5786
295e8bb7
VS		 5787 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5788 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5789
5790 /* WaDisableSDEUnitClockGating:bdw */
5791 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5792 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 5793
89d6b2b8 5794 lpt_init_clock_gating(dev);
1020a5c2
BW		 5795}
5796
cad2a2d7
ED		 5797static void haswell_init_clock_gating(struct drm_device *dev)
5798{
5799 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5800
017636cc 5801 ilk_init_lp_watermarks(dev);
cad2a2d7 5802
f3fc4884
FJ		 5803 /* L3 caching of data atomics doesn't work -- disable it. */
5804 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5805 I915_WRITE(HSW_ROW_CHICKEN3,
5806 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5807
ecdb4eb7 5808 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5809 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5810 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5811 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5812
e36ea7ff
VS		 5813 /* WaVSRefCountFullforceMissDisable:hsw */
5814 I915_WRITE(GEN7_FF_THREAD_MODE,
5815 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5816
4e04632e
AG		 5817 /* WaDisable_RenderCache_OperationalFlush:hsw */
5818 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5819
fe27c606
CW		 5820 /* enable HiZ Raw Stall Optimization */
5821 I915_WRITE(CACHE_MODE_0_GEN7,
5822 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5823
ecdb4eb7 5824 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5825 I915_WRITE(CACHE_MODE_1,
5826 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5827
a12c4967
VS		 5828 /*
5829 * BSpec recommends 8x4 when MSAA is used,
5830 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5831 *
5832 * Note that PS/WM thread counts depend on the WIZ hashing
5833 * disable bit, which we don't touch here, but it's good
5834 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5835 */
5836 I915_WRITE(GEN7_GT_MODE,
5837 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5838
ecdb4eb7 5839 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5840 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5841
90a88643
PZ		 5842 /* WaRsPkgCStateDisplayPMReq:hsw */
5843 I915_WRITE(CHICKEN_PAR1_1,
5844 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5845
17a303ec 5846 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5847}
5848
1fa61106 5849static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5850{
5851 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5852 uint32_t snpcr;
6f1d69b0 5853
017636cc 5854 ilk_init_lp_watermarks(dev);
6f1d69b0 5855
231e54f6 5856 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5857
ecdb4eb7 5858 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5859 I915_WRITE(_3D_CHICKEN3,
5860 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5861
ecdb4eb7 5862 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5863 I915_WRITE(IVB_CHICKEN3,
5864 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5865 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5866
ecdb4eb7 5867 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5868 if (IS_IVB_GT1(dev))
5869 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5870 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5871
4e04632e
AG		 5872 /* WaDisable_RenderCache_OperationalFlush:ivb */
5873 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5874
ecdb4eb7 5875 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5876 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5877 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5878
ecdb4eb7 5879 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5880 I915_WRITE(GEN7_L3CNTLREG1,
5881 GEN7_WA_FOR_GEN7_L3_CONTROL);
5882 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5883 GEN7_WA_L3_CHICKEN_MODE);
5884 if (IS_IVB_GT1(dev))
5885 I915_WRITE(GEN7_ROW_CHICKEN2,
5886 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5887 else {
5888 /* must write both registers */
5889 I915_WRITE(GEN7_ROW_CHICKEN2,
5890 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5891 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5892 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5893 }
6f1d69b0 5894
ecdb4eb7 5895 /* WaForceL3Serialization:ivb */
61939d97
JB		 5896 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5897 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5898
1b80a19a 5899 /*
0f846f81 5900 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5901 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5902 */
5903 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5904 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5905
ecdb4eb7 5906 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5907 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5908 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5909 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5910
0e088b8f 5911 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5912
5913 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5914
22721343
CW		 5915 if (0) { /* causes HiZ corruption on ivb:gt1 */
5916 /* enable HiZ Raw Stall Optimization */
5917 I915_WRITE(CACHE_MODE_0_GEN7,
5918 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5919 }
116f2b6d 5920
ecdb4eb7 5921 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5922 I915_WRITE(CACHE_MODE_1,
5923 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5924
a607c1a4
VS		 5925 /*
5926 * BSpec recommends 8x4 when MSAA is used,
5927 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5928 *
5929 * Note that PS/WM thread counts depend on the WIZ hashing
5930 * disable bit, which we don't touch here, but it's good
5931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5932 */
5933 I915_WRITE(GEN7_GT_MODE,
5934 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5935
20848223
BW		 5936 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5937 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5938 snpcr |= GEN6_MBC_SNPCR_MED;
5939 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5940
ab5c608b
BW		 5941 if (!HAS_PCH_NOP(dev))
5942 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5943
5944 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5945}
5946
1fa61106 5947static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5948{
5949 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 5950
d7fe0cc0 5951 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5952
ecdb4eb7 5953 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5954 I915_WRITE(_3D_CHICKEN3,
5955 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5956
ecdb4eb7 5957 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5958 I915_WRITE(IVB_CHICKEN3,
5959 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5960 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5961
fad7d36e 5962 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5963 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5964 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5965 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5966 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5967
4e04632e
AG		 5968 /* WaDisable_RenderCache_OperationalFlush:vlv */
5969 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5970
ecdb4eb7 5971 /* WaForceL3Serialization:vlv */
61939d97
JB		 5972 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5973 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5974
ecdb4eb7 5975 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5976 I915_WRITE(GEN7_ROW_CHICKEN2,
5977 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5978
ecdb4eb7 5979 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5980 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5981 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5982 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5983
46680e0a
VS		 5984 gen7_setup_fixed_func_scheduler(dev_priv);
5985
3c0edaeb 5986 /*
0f846f81 5987 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5988 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5989 */
5990 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5991 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5992
c98f5062
AG		 5993 /* WaDisableL3Bank2xClockGate:vlv
5994 * Disabling L3 clock gating- MMIO 940c[25] = 1
5995 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5996 I915_WRITE(GEN7_UCGCTL4,
5997 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5998
e0d8d59b 5999 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 6000
afd58e79
VS		 6001 /*
6002 * BSpec says this must be set, even though
6003 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6004 */
6b26c86d
DV		 6005 I915_WRITE(CACHE_MODE_1,
6006 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6007
031994ee
VS		 6008 /*
6009 * WaIncreaseL3CreditsForVLVB0:vlv
6010 * This is the hardware default actually.
6011 */
6012 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6013
2d809570 6014 /*
ecdb4eb7 6015 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6016 * Disable clock gating on th GCFG unit to prevent a delay
6017 * in the reporting of vblank events.
6018 */
7a0d1eed 6019 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6020}
6021
a4565da8
VS		 6022static void cherryview_init_clock_gating(struct drm_device *dev)
6023{
6024 struct drm_i915_private *dev_priv = dev->dev_private;
6025
6026 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6027
6028 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70 6029
232ce337
VS		 6030 /* WaVSRefCountFullforceMissDisable:chv */
6031 /* WaDSRefCountFullforceMissDisable:chv */
6032 I915_WRITE(GEN7_FF_THREAD_MODE,
6033 I915_READ(GEN7_FF_THREAD_MODE) &
6034 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6035
6036 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6037 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6038 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6039
6040 /* WaDisableCSUnitClockGating:chv */
6041 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6042 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6043
6044 /* WaDisableSDEUnitClockGating:chv */
6045 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6046 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7 6047
e4443e45
VS		 6048 /* WaDisableGunitClockGating:chv (pre-production hw) */
6049 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6050 GINT_DIS);
6051
6052 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6053 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6054 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6055
6056 /* WaDisableDopClockGating:chv (pre-production hw) */
e4443e45
VS		 6057 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6058 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6059}
6060
1fa61106 6061static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6062{
6063 struct drm_i915_private *dev_priv = dev->dev_private;
6064 uint32_t dspclk_gate;
6065
6066 I915_WRITE(RENCLK_GATE_D1, 0);
6067 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6068 GS_UNIT_CLOCK_GATE_DISABLE |
6069 CL_UNIT_CLOCK_GATE_DISABLE);
6070 I915_WRITE(RAMCLK_GATE_D, 0);
6071 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6072 OVRUNIT_CLOCK_GATE_DISABLE |
6073 OVCUNIT_CLOCK_GATE_DISABLE;
6074 if (IS_GM45(dev))
6075 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6076 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6077
6078 /* WaDisableRenderCachePipelinedFlush */
6079 I915_WRITE(CACHE_MODE_0,
6080 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6081
4e04632e
AG		 6082 /* WaDisable_RenderCache_OperationalFlush:g4x */
6083 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6084
0e088b8f 6085 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6086}
6087
1fa61106 6088static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6089{
6090 struct drm_i915_private *dev_priv = dev->dev_private;
6091
6092 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6093 I915_WRITE(RENCLK_GATE_D2, 0);
6094 I915_WRITE(DSPCLK_GATE_D, 0);
6095 I915_WRITE(RAMCLK_GATE_D, 0);
6096 I915_WRITE16(DEUC, 0);
20f94967
VS		 6097 I915_WRITE(MI_ARB_STATE,
6098 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6099
6100 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6101 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6102}
6103
1fa61106 6104static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6105{
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107
6108 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6109 I965_RCC_CLOCK_GATE_DISABLE |
6110 I965_RCPB_CLOCK_GATE_DISABLE |
6111 I965_ISC_CLOCK_GATE_DISABLE |
6112 I965_FBC_CLOCK_GATE_DISABLE);
6113 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6114 I915_WRITE(MI_ARB_STATE,
6115 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6116
6117 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6118 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6119}
6120
1fa61106 6121static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6122{
6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124 u32 dstate = I915_READ(D_STATE);
6125
6126 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6127 DSTATE_DOT_CLOCK_GATING;
6128 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6129
6130 if (IS_PINEVIEW(dev))
6131 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6132
6133 /* IIR "flip pending" means done if this bit is set */
6134 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6135
6136 /* interrupts should cause a wake up from C3 */
3299254f 6137 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6138
6139 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6140 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6141
6142 I915_WRITE(MI_ARB_STATE,
6143 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6144}
6145
1fa61106 6146static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6147{
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149
6150 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6151
6152 /* interrupts should cause a wake up from C3 */
6153 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6154 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6155
6156 I915_WRITE(MEM_MODE,
6157 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6158}
6159
1fa61106 6160static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6161{
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163
6164 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6165
6166 I915_WRITE(MEM_MODE,
6167 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6168 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6169}
6170
6f1d69b0
ED		 6171void intel_init_clock_gating(struct drm_device *dev)
6172{
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174
6175 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6176}
6177
7d708ee4
ID		 6178void intel_suspend_hw(struct drm_device *dev)
6179{
6180 if (HAS_PCH_LPT(dev))
6181 lpt_suspend_hw(dev);
6182}
6183
c1ca727f
ID		 6184#define for_each_power_well(i, power_well, domain_mask, power_domains) \
6185 for (i = 0; \
6186 i < (power_domains)->power_well_count && \
6187 ((power_well) = &(power_domains)->power_wells[i]); \
6188 i++) \
6189 if ((power_well)->domains & (domain_mask))
6190
6191#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6192 for (i = (power_domains)->power_well_count - 1; \
6193 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6194 i--) \
6195 if ((power_well)->domains & (domain_mask))
6196
15d199ea
PZ		 6197/**
6198 * We should only use the power well if we explicitly asked the hardware to
6199 * enable it, so check if it's enabled and also check if we've requested it to
6200 * be enabled.
6201 */
da7e29bd 6202static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 6203 struct i915_power_well *power_well)
6204{
c1ca727f
ID		 6205 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6206 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6207}
6208
bfafe93a
ID		 6209bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6210 enum intel_display_power_domain domain)
ddf9c536 6211{
ddf9c536 6212 struct i915_power_domains *power_domains;
b8c000d9
ID		 6213 struct i915_power_well *power_well;
6214 bool is_enabled;
6215 int i;
6216
6217 if (dev_priv->pm.suspended)
6218 return false;
ddf9c536
ID		 6219
6220 power_domains = &dev_priv->power_domains;
bfafe93a 6221
b8c000d9 6222 is_enabled = true;
bfafe93a 6223
b8c000d9
ID		 6224 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6225 if (power_well->always_on)
6226 continue;
ddf9c536 6227
bfafe93a 6228 if (!power_well->hw_enabled) {
b8c000d9
ID		 6229 is_enabled = false;
6230 break;
6231 }
6232 }
bfafe93a 6233
b8c000d9 6234 return is_enabled;
ddf9c536
ID		 6235}
6236
da7e29bd 6237bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 6238 enum intel_display_power_domain domain)
15d199ea 6239{
c1ca727f 6240 struct i915_power_domains *power_domains;
bfafe93a 6241 bool ret;
882244a3 6242
c1ca727f
ID		 6243 power_domains = &dev_priv->power_domains;
6244
c1ca727f 6245 mutex_lock(&power_domains->lock);
bfafe93a 6246 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
c1ca727f
ID		 6247 mutex_unlock(&power_domains->lock);
6248
bfafe93a 6249 return ret;
15d199ea
PZ		 6250}
6251
93c73e8c
ID		 6252/*
6253 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6254 * when not needed anymore. We have 4 registers that can request the power well
6255 * to be enabled, and it will only be disabled if none of the registers is
6256 * requesting it to be enabled.
6257 */
d5e8fdc8
PZ		 6258static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6259{
6260 struct drm_device *dev = dev_priv->dev;
d5e8fdc8 6261
f9dcb0df
PZ		 6262 /*
6263 * After we re-enable the power well, if we touch VGA register 0x3d5
6264 * we'll get unclaimed register interrupts. This stops after we write
6265 * anything to the VGA MSR register. The vgacon module uses this
6266 * register all the time, so if we unbind our driver and, as a
6267 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6268 * console_unlock(). So make here we touch the VGA MSR register, making
6269 * sure vgacon can keep working normally without triggering interrupts
6270 * and error messages.
6271 */
6272 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6273 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6274 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6275
d49bdb0e
PZ		 6276 if (IS_BROADWELL(dev))
6277 gen8_irq_power_well_post_enable(dev_priv);
d5e8fdc8
PZ		 6278}
6279
da7e29bd 6280static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 6281 struct i915_power_well *power_well, bool enable)
d0d3e513 6282{
fa42e23c
PZ		 6283 bool is_enabled, enable_requested;
6284 uint32_t tmp;
d0d3e513 6285
fa42e23c 6286 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 6287 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6288 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 6289
fa42e23c
PZ		 6290 if (enable) {
6291 if (!enable_requested)
6aedd1f5
PZ		 6292 I915_WRITE(HSW_PWR_WELL_DRIVER,
6293 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 6294
fa42e23c
PZ		 6295 if (!is_enabled) {
6296 DRM_DEBUG_KMS("Enabling power well\n");
6297 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 6298 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 6299 DRM_ERROR("Timeout enabling power well\n");
6300 }
596cc11e 6301
d5e8fdc8 6302 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 6303 } else {
6304 if (enable_requested) {
6305 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 6306 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 6307 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 6308 }
6309 }
fa42e23c 6310}
d0d3e513 6311
c6cb582e
ID		 6312static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6313 struct i915_power_well *power_well)
6314{
6315 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6316
6317 /*
6318 * We're taking over the BIOS, so clear any requests made by it since
6319 * the driver is in charge now.
6320 */
6321 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6322 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6323}
6324
6325static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6326 struct i915_power_well *power_well)
6327{
c6cb582e
ID		 6328 hsw_set_power_well(dev_priv, power_well, true);
6329}
6330
6331static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6332 struct i915_power_well *power_well)
6333{
6334 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 6335}
6336
a45f4466
ID		 6337static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6338 struct i915_power_well *power_well)
6339{
6340}
6341
6342static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6343 struct i915_power_well *power_well)
6344{
6345 return true;
6346}
6347
d2011dc8
VS		 6348static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6349 struct i915_power_well *power_well, bool enable)
77961eb9 6350{
d2011dc8 6351 enum punit_power_well power_well_id = power_well->data;
77961eb9
ID		 6352 u32 mask;
6353 u32 state;
6354 u32 ctrl;
6355
6356 mask = PUNIT_PWRGT_MASK(power_well_id);
6357 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6358 PUNIT_PWRGT_PWR_GATE(power_well_id);
6359
6360 mutex_lock(&dev_priv->rps.hw_lock);
6361
6362#define COND \
6363 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6364
6365 if (COND)
6366 goto out;
6367
6368 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6369 ctrl &= ~mask;
6370 ctrl |= state;
6371 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6372
6373 if (wait_for(COND, 100))
6374 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6375 state,
6376 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6377
6378#undef COND
6379
6380out:
6381 mutex_unlock(&dev_priv->rps.hw_lock);
6382}
6383
6384static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6385 struct i915_power_well *power_well)
6386{
6387 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6388}
6389
6390static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6391 struct i915_power_well *power_well)
6392{
6393 vlv_set_power_well(dev_priv, power_well, true);
6394}
6395
6396static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6397 struct i915_power_well *power_well)
6398{
6399 vlv_set_power_well(dev_priv, power_well, false);
6400}
6401
6402static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6403 struct i915_power_well *power_well)
6404{
6405 int power_well_id = power_well->data;
6406 bool enabled = false;
6407 u32 mask;
6408 u32 state;
6409 u32 ctrl;
6410
6411 mask = PUNIT_PWRGT_MASK(power_well_id);
6412 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6413
6414 mutex_lock(&dev_priv->rps.hw_lock);
6415
6416 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6417 /*
6418 * We only ever set the power-on and power-gate states, anything
6419 * else is unexpected.
6420 */
6421 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6422 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6423 if (state == ctrl)
6424 enabled = true;
6425
6426 /*
6427 * A transient state at this point would mean some unexpected party
6428 * is poking at the power controls too.
6429 */
6430 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6431 WARN_ON(ctrl != state);
6432
6433 mutex_unlock(&dev_priv->rps.hw_lock);
6434
6435 return enabled;
6436}
6437
6438static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6439 struct i915_power_well *power_well)
6440{
6441 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6442
6443 vlv_set_power_well(dev_priv, power_well, true);
6444
6445 spin_lock_irq(&dev_priv->irq_lock);
6446 valleyview_enable_display_irqs(dev_priv);
6447 spin_unlock_irq(&dev_priv->irq_lock);
6448
6449 /*
0d116a29
ID		 6450 * During driver initialization/resume we can avoid restoring the
6451 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 6452 */
0d116a29
ID		 6453 if (dev_priv->power_domains.initializing)
6454 return;
6455
6456 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 6457
6458 i915_redisable_vga_power_on(dev_priv->dev);
6459}
6460
6461static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6462 struct i915_power_well *power_well)
6463{
77961eb9
ID		 6464 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6465
6466 spin_lock_irq(&dev_priv->irq_lock);
77961eb9
ID		 6467 valleyview_disable_display_irqs(dev_priv);
6468 spin_unlock_irq(&dev_priv->irq_lock);
6469
77961eb9 6470 vlv_set_power_well(dev_priv, power_well, false);
773538e8
VS		 6471
6472 vlv_power_sequencer_reset(dev_priv);
77961eb9
ID		 6473}
6474
aa519f23
VS		 6475static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6476 struct i915_power_well *power_well)
6477{
6478 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6479
6480 /*
6481 * Enable the CRI clock source so we can get at the
6482 * display and the reference clock for VGA
6483 * hotplug / manual detection.
6484 */
6485 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6486 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6487 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6488
6489 vlv_set_power_well(dev_priv, power_well, true);
6490
6491 /*
6492 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6493 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6494 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6495 * b. The other bits such as sfr settings / modesel may all
6496 * be set to 0.
6497 *
6498 * This should only be done on init and resume from S3 with
6499 * both PLLs disabled, or we risk losing DPIO and PLL
6500 * synchronization.
6501 */
6502 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6503}
6504
6505static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6506 struct i915_power_well *power_well)
6507{
aa519f23
VS		 6508 enum pipe pipe;
6509
6510 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6511
055e393f 6512 for_each_pipe(dev_priv, pipe)
aa519f23
VS		 6513 assert_pll_disabled(dev_priv, pipe);
6514
6515 /* Assert common reset */
6516 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6517
6518 vlv_set_power_well(dev_priv, power_well, false);
6519}
6520
5d6f7ea7
VS		 6521static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6522 struct i915_power_well *power_well)
6523{
6524 enum dpio_phy phy;
6525
6526 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6527 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6528
6529 /*
6530 * Enable the CRI clock source so we can get at the
6531 * display and the reference clock for VGA
6532 * hotplug / manual detection.
6533 */
6534 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6535 phy = DPIO_PHY0;
6536 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6537 DPLL_REFA_CLK_ENABLE_VLV);
6538 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6539 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6540 } else {
6541 phy = DPIO_PHY1;
6542 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6543 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6544 }
6545 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6546 vlv_set_power_well(dev_priv, power_well, true);
6547
6548 /* Poll for phypwrgood signal */
6549 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6550 DRM_ERROR("Display PHY %d is not power up\n", phy);
6551
efd814b7
VS		 6552 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6553 PHY_COM_LANE_RESET_DEASSERT(phy));
5d6f7ea7
VS		 6554}
6555
6556static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6557 struct i915_power_well *power_well)
6558{
6559 enum dpio_phy phy;
6560
6561 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6562 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6563
6564 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6565 phy = DPIO_PHY0;
6566 assert_pll_disabled(dev_priv, PIPE_A);
6567 assert_pll_disabled(dev_priv, PIPE_B);
6568 } else {
6569 phy = DPIO_PHY1;
6570 assert_pll_disabled(dev_priv, PIPE_C);
6571 }
6572
efd814b7
VS		 6573 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6574 ~PHY_COM_LANE_RESET_DEASSERT(phy));
5d6f7ea7
VS		 6575
6576 vlv_set_power_well(dev_priv, power_well, false);
6577}
6578
26972b0a
VS		 6579static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6580 struct i915_power_well *power_well)
6581{
6582 enum pipe pipe = power_well->data;
6583 bool enabled;
6584 u32 state, ctrl;
6585
6586 mutex_lock(&dev_priv->rps.hw_lock);
6587
6588 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6589 /*
6590 * We only ever set the power-on and power-gate states, anything
6591 * else is unexpected.
6592 */
6593 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6594 enabled = state == DP_SSS_PWR_ON(pipe);
6595
6596 /*
6597 * A transient state at this point would mean some unexpected party
6598 * is poking at the power controls too.
6599 */
6600 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6601 WARN_ON(ctrl << 16 != state);
6602
6603 mutex_unlock(&dev_priv->rps.hw_lock);
6604
6605 return enabled;
6606}
6607
6608static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6609 struct i915_power_well *power_well,
6610 bool enable)
6611{
6612 enum pipe pipe = power_well->data;
6613 u32 state;
6614 u32 ctrl;
6615
6616 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6617
6618 mutex_lock(&dev_priv->rps.hw_lock);
6619
6620#define COND \
6621 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6622
6623 if (COND)
6624 goto out;
6625
6626 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6627 ctrl &= ~DP_SSC_MASK(pipe);
6628 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6629 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6630
6631 if (wait_for(COND, 100))
6632 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6633 state,
6634 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6635
6636#undef COND
6637
6638out:
6639 mutex_unlock(&dev_priv->rps.hw_lock);
6640}
6641
6642static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6643 struct i915_power_well *power_well)
6644{
6645 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6646}
6647
6648static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6649 struct i915_power_well *power_well)
6650{
6651 WARN_ON_ONCE(power_well->data != PIPE_A &&
6652 power_well->data != PIPE_B &&
6653 power_well->data != PIPE_C);
6654
6655 chv_set_pipe_power_well(dev_priv, power_well, true);
6656}
6657
6658static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6659 struct i915_power_well *power_well)
6660{
6661 WARN_ON_ONCE(power_well->data != PIPE_A &&
6662 power_well->data != PIPE_B &&
6663 power_well->data != PIPE_C);
6664
6665 chv_set_pipe_power_well(dev_priv, power_well, false);
6666}
6667
25eaa003
ID		 6668static void check_power_well_state(struct drm_i915_private *dev_priv,
6669 struct i915_power_well *power_well)
6670{
6671 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6672
6673 if (power_well->always_on || !i915.disable_power_well) {
6674 if (!enabled)
6675 goto mismatch;
6676
6677 return;
6678 }
6679
6680 if (enabled != (power_well->count > 0))
6681 goto mismatch;
6682
6683 return;
6684
6685mismatch:
6686 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6687 power_well->name, power_well->always_on, enabled,
6688 power_well->count, i915.disable_power_well);
6689}
6690
da7e29bd 6691void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 6692 enum intel_display_power_domain domain)
6693{
83c00f55 6694 struct i915_power_domains *power_domains;
c1ca727f
ID		 6695 struct i915_power_well *power_well;
6696 int i;
6765625e 6697
9e6ea71a
PZ		 6698 intel_runtime_pm_get(dev_priv);
6699
83c00f55
ID		 6700 power_domains = &dev_priv->power_domains;
6701
6702 mutex_lock(&power_domains->lock);
1da51581 6703
25eaa003
ID		 6704 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6705 if (!power_well->count++) {
6706 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 6707 power_well->ops->enable(dev_priv, power_well);
bfafe93a 6708 power_well->hw_enabled = true;
25eaa003
ID		 6709 }
6710
6711 check_power_well_state(dev_priv, power_well);
6712 }
1da51581 6713
ddf9c536
ID		 6714 power_domains->domain_use_count[domain]++;
6715
83c00f55 6716 mutex_unlock(&power_domains->lock);
6765625e
VS		 6717}
6718
da7e29bd 6719void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 6720 enum intel_display_power_domain domain)
6721{
83c00f55 6722 struct i915_power_domains *power_domains;
c1ca727f
ID		 6723 struct i915_power_well *power_well;
6724 int i;
6765625e 6725
83c00f55
ID		 6726 power_domains = &dev_priv->power_domains;
6727
6728 mutex_lock(&power_domains->lock);
1da51581 6729
1da51581
ID		 6730 WARN_ON(!power_domains->domain_use_count[domain]);
6731 power_domains->domain_use_count[domain]--;
ddf9c536 6732
70bf407c
ID		 6733 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6734 WARN_ON(!power_well->count);
6735
25eaa003
ID		 6736 if (!--power_well->count && i915.disable_power_well) {
6737 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
bfafe93a 6738 power_well->hw_enabled = false;
c6cb582e 6739 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 6740 }
6741
6742 check_power_well_state(dev_priv, power_well);
70bf407c 6743 }
1da51581 6744
83c00f55 6745 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 6746
6747 intel_runtime_pm_put(dev_priv);
6765625e
VS		 6748}
6749
83c00f55 6750static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 6751
6752/* Display audio driver power well request */
74b0c2d7 6753int i915_request_power_well(void)
a38911a3 6754{
b4ed4484
ID		 6755 struct drm_i915_private *dev_priv;
6756
74b0c2d7
TI		 6757 if (!hsw_pwr)
6758 return -ENODEV;
a38911a3 6759
b4ed4484
ID		 6760 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6761 power_domains);
da7e29bd 6762 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6763 return 0;
a38911a3
WX		 6764}
6765EXPORT_SYMBOL_GPL(i915_request_power_well);
6766
6767/* Display audio driver power well release */
74b0c2d7 6768int i915_release_power_well(void)
a38911a3 6769{
b4ed4484
ID		 6770 struct drm_i915_private *dev_priv;
6771
74b0c2d7
TI		 6772 if (!hsw_pwr)
6773 return -ENODEV;
a38911a3 6774
b4ed4484
ID		 6775 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6776 power_domains);
da7e29bd 6777 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6778 return 0;
a38911a3
WX		 6779}
6780EXPORT_SYMBOL_GPL(i915_release_power_well);
6781
c149dcb5
JN		 6782/*
6783 * Private interface for the audio driver to get CDCLK in kHz.
6784 *
6785 * Caller must request power well using i915_request_power_well() prior to
6786 * making the call.
6787 */
6788int i915_get_cdclk_freq(void)
6789{
6790 struct drm_i915_private *dev_priv;
6791
6792 if (!hsw_pwr)
6793 return -ENODEV;
6794
6795 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6796 power_domains);
6797
6798 return intel_ddi_get_cdclk_freq(dev_priv);
6799}
6800EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6801
6802
efcad917
ID		 6803#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6804
6805#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6806 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 6807 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 6808 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6809 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6810 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6811 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6812 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6813 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6814 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6815 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6816 BIT(POWER_DOMAIN_PORT_CRT) | \
bd2bb1b9 6817 BIT(POWER_DOMAIN_PLLS) | \
f5938f36 6818 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 6819#define HSW_DISPLAY_POWER_DOMAINS ( \
6820 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6821 BIT(POWER_DOMAIN_INIT))
6822
6823#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6824 HSW_ALWAYS_ON_POWER_DOMAINS | \
6825 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6826#define BDW_DISPLAY_POWER_DOMAINS ( \
6827 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6828 BIT(POWER_DOMAIN_INIT))
6829
77961eb9
ID		 6830#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6831#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6832
6833#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6834 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6835 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6836 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6837 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6838 BIT(POWER_DOMAIN_PORT_CRT) | \
6839 BIT(POWER_DOMAIN_INIT))
6840
6841#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6842 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6843 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6844 BIT(POWER_DOMAIN_INIT))
6845
6846#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6847 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6848 BIT(POWER_DOMAIN_INIT))
6849
6850#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6851 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6852 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6853 BIT(POWER_DOMAIN_INIT))
6854
6855#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6856 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6857 BIT(POWER_DOMAIN_INIT))
6858
26972b0a
VS		 6859#define CHV_PIPE_A_POWER_DOMAINS ( \
6860 BIT(POWER_DOMAIN_PIPE_A) | \
6861 BIT(POWER_DOMAIN_INIT))
6862
6863#define CHV_PIPE_B_POWER_DOMAINS ( \
6864 BIT(POWER_DOMAIN_PIPE_B) | \
6865 BIT(POWER_DOMAIN_INIT))
6866
6867#define CHV_PIPE_C_POWER_DOMAINS ( \
6868 BIT(POWER_DOMAIN_PIPE_C) | \
6869 BIT(POWER_DOMAIN_INIT))
6870
5d6f7ea7
VS		 6871#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6872 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6873 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6874 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6875 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6876 BIT(POWER_DOMAIN_INIT))
6877
6878#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6879 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6880 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6881 BIT(POWER_DOMAIN_INIT))
6882
2ce147f3
VS		 6883#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6884 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6885 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6886 BIT(POWER_DOMAIN_INIT))
6887
6888#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6889 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6890 BIT(POWER_DOMAIN_INIT))
6891
a45f4466
ID		 6892static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6893 .sync_hw = i9xx_always_on_power_well_noop,
6894 .enable = i9xx_always_on_power_well_noop,
6895 .disable = i9xx_always_on_power_well_noop,
6896 .is_enabled = i9xx_always_on_power_well_enabled,
6897};
c6cb582e 6898
26972b0a
VS		 6899static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6900 .sync_hw = chv_pipe_power_well_sync_hw,
6901 .enable = chv_pipe_power_well_enable,
6902 .disable = chv_pipe_power_well_disable,
6903 .is_enabled = chv_pipe_power_well_enabled,
6904};
6905
5d6f7ea7
VS		 6906static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6907 .sync_hw = vlv_power_well_sync_hw,
6908 .enable = chv_dpio_cmn_power_well_enable,
6909 .disable = chv_dpio_cmn_power_well_disable,
6910 .is_enabled = vlv_power_well_enabled,
6911};
6912
1c2256df
ID		 6913static struct i915_power_well i9xx_always_on_power_well[] = {
6914 {
6915 .name = "always-on",
6916 .always_on = 1,
6917 .domains = POWER_DOMAIN_MASK,
c6cb582e 6918 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6919 },
6920};
6921
c6cb582e
ID		 6922static const struct i915_power_well_ops hsw_power_well_ops = {
6923 .sync_hw = hsw_power_well_sync_hw,
6924 .enable = hsw_power_well_enable,
6925 .disable = hsw_power_well_disable,
6926 .is_enabled = hsw_power_well_enabled,
6927};
6928
c1ca727f 6929static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6930 {
6931 .name = "always-on",
6932 .always_on = 1,
6933 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6934 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6935 },
c1ca727f
ID		 6936 {
6937 .name = "display",
efcad917 6938 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6939 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6940 },
6941};
6942
6943static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6944 {
6945 .name = "always-on",
6946 .always_on = 1,
6947 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6948 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6949 },
c1ca727f
ID		 6950 {
6951 .name = "display",
efcad917 6952 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6953 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6954 },
6955};
6956
77961eb9
ID		 6957static const struct i915_power_well_ops vlv_display_power_well_ops = {
6958 .sync_hw = vlv_power_well_sync_hw,
6959 .enable = vlv_display_power_well_enable,
6960 .disable = vlv_display_power_well_disable,
6961 .is_enabled = vlv_power_well_enabled,
6962};
6963
aa519f23
VS		 6964static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6965 .sync_hw = vlv_power_well_sync_hw,
6966 .enable = vlv_dpio_cmn_power_well_enable,
6967 .disable = vlv_dpio_cmn_power_well_disable,
6968 .is_enabled = vlv_power_well_enabled,
6969};
6970
77961eb9
ID		 6971static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6972 .sync_hw = vlv_power_well_sync_hw,
6973 .enable = vlv_power_well_enable,
6974 .disable = vlv_power_well_disable,
6975 .is_enabled = vlv_power_well_enabled,
6976};
6977
6978static struct i915_power_well vlv_power_wells[] = {
6979 {
6980 .name = "always-on",
6981 .always_on = 1,
6982 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6983 .ops = &i9xx_always_on_power_well_ops,
6984 },
6985 {
6986 .name = "display",
6987 .domains = VLV_DISPLAY_POWER_DOMAINS,
6988 .data = PUNIT_POWER_WELL_DISP2D,
6989 .ops = &vlv_display_power_well_ops,
6990 },
77961eb9
ID		 6991 {
6992 .name = "dpio-tx-b-01",
6993 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6994 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6995 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6996 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6997 .ops = &vlv_dpio_power_well_ops,
6998 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6999 },
7000 {
7001 .name = "dpio-tx-b-23",
7002 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7003 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7004 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7005 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7006 .ops = &vlv_dpio_power_well_ops,
7007 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7008 },
7009 {
7010 .name = "dpio-tx-c-01",
7011 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7012 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7013 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7014 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7015 .ops = &vlv_dpio_power_well_ops,
7016 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7017 },
7018 {
7019 .name = "dpio-tx-c-23",
7020 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7021 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
7022 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7023 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7024 .ops = &vlv_dpio_power_well_ops,
7025 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7026 },
f099a3c6
JB		 7027 {
7028 .name = "dpio-common",
7029 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
7030 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
aa519f23 7031 .ops = &vlv_dpio_cmn_power_well_ops,
f099a3c6 7032 },
77961eb9
ID		 7033};
7034
4811ff4f
VS		 7035static struct i915_power_well chv_power_wells[] = {
7036 {
7037 .name = "always-on",
7038 .always_on = 1,
7039 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
7040 .ops = &i9xx_always_on_power_well_ops,
7041 },
f07057d1
VS		 7042#if 0
7043 {
7044 .name = "display",
7045 .domains = VLV_DISPLAY_POWER_DOMAINS,
7046 .data = PUNIT_POWER_WELL_DISP2D,
7047 .ops = &vlv_display_power_well_ops,
7048 },
26972b0a
VS		 7049 {
7050 .name = "pipe-a",
7051 .domains = CHV_PIPE_A_POWER_DOMAINS,
7052 .data = PIPE_A,
7053 .ops = &chv_pipe_power_well_ops,
7054 },
7055 {
7056 .name = "pipe-b",
7057 .domains = CHV_PIPE_B_POWER_DOMAINS,
7058 .data = PIPE_B,
7059 .ops = &chv_pipe_power_well_ops,
7060 },
7061 {
7062 .name = "pipe-c",
7063 .domains = CHV_PIPE_C_POWER_DOMAINS,
7064 .data = PIPE_C,
7065 .ops = &chv_pipe_power_well_ops,
7066 },
f07057d1 7067#endif
5d6f7ea7
VS		 7068 {
7069 .name = "dpio-common-bc",
3dd7b974
VS		 7070 /*
7071 * XXX: cmnreset for one PHY seems to disturb the other.
7072 * As a workaround keep both powered on at the same
7073 * time for now.
7074 */
7075 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
5d6f7ea7
VS		 7076 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
7077 .ops = &chv_dpio_cmn_power_well_ops,
7078 },
7079 {
7080 .name = "dpio-common-d",
3dd7b974
VS		 7081 /*
7082 * XXX: cmnreset for one PHY seems to disturb the other.
7083 * As a workaround keep both powered on at the same
7084 * time for now.
7085 */
7086 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
5d6f7ea7
VS		 7087 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
7088 .ops = &chv_dpio_cmn_power_well_ops,
7089 },
82583565
VS		 7090#if 0
7091 {
7092 .name = "dpio-tx-b-01",
7093 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7094 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7095 .ops = &vlv_dpio_power_well_ops,
7096 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
7097 },
7098 {
7099 .name = "dpio-tx-b-23",
7100 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
7101 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
7102 .ops = &vlv_dpio_power_well_ops,
7103 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
7104 },
7105 {
7106 .name = "dpio-tx-c-01",
7107 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7108 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7109 .ops = &vlv_dpio_power_well_ops,
7110 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
7111 },
7112 {
7113 .name = "dpio-tx-c-23",
7114 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
7115 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
7116 .ops = &vlv_dpio_power_well_ops,
7117 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
7118 },
2ce147f3
VS		 7119 {
7120 .name = "dpio-tx-d-01",
7121 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7122 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7123 .ops = &vlv_dpio_power_well_ops,
7124 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
7125 },
7126 {
7127 .name = "dpio-tx-d-23",
7128 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
7129 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
7130 .ops = &vlv_dpio_power_well_ops,
7131 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
7132 },
82583565 7133#endif
4811ff4f
VS		 7134};
7135
d2011dc8
VS		 7136static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7137 enum punit_power_well power_well_id)
7138{
7139 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7140 struct i915_power_well *power_well;
7141 int i;
7142
7143 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7144 if (power_well->data == power_well_id)
7145 return power_well;
7146 }
7147
7148 return NULL;
7149}
7150
c1ca727f
ID		 7151#define set_power_wells(power_domains, __power_wells) ({ \
7152 (power_domains)->power_wells = (__power_wells); \
7153 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7154})
7155
da7e29bd 7156int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 7157{
83c00f55 7158 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 7159
83c00f55 7160 mutex_init(&power_domains->lock);
a38911a3 7161
c1ca727f
ID		 7162 /*
7163 * The enabling order will be from lower to higher indexed wells,
7164 * the disabling order is reversed.
7165 */
da7e29bd 7166 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 7167 set_power_wells(power_domains, hsw_power_wells);
7168 hsw_pwr = power_domains;
da7e29bd 7169 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 7170 set_power_wells(power_domains, bdw_power_wells);
7171 hsw_pwr = power_domains;
4811ff4f
VS		 7172 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7173 set_power_wells(power_domains, chv_power_wells);
77961eb9
ID		 7174 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7175 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 7176 } else {
1c2256df 7177 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 7178 }
a38911a3
WX		 7179
7180 return 0;
7181}
7182
da7e29bd 7183void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 7184{
7185 hsw_pwr = NULL;
7186}
7187
da7e29bd 7188static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 7189{
83c00f55
ID		 7190 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7191 struct i915_power_well *power_well;
c1ca727f 7192 int i;
9cdb826c 7193
83c00f55 7194 mutex_lock(&power_domains->lock);
bfafe93a 7195 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
a45f4466 7196 power_well->ops->sync_hw(dev_priv, power_well);
bfafe93a
ID		 7197 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7198 power_well);
7199 }
83c00f55 7200 mutex_unlock(&power_domains->lock);
a38911a3
WX		 7201}
7202
d2011dc8
VS		 7203static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7204{
7205 struct i915_power_well *cmn =
7206 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7207 struct i915_power_well *disp2d =
7208 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7209
7210 /* nothing to do if common lane is already off */
7211 if (!cmn->ops->is_enabled(dev_priv, cmn))
7212 return;
7213
7214 /* If the display might be already active skip this */
7215 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7216 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7217 return;
7218
7219 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7220
7221 /* cmnlane needs DPLL registers */
7222 disp2d->ops->enable(dev_priv, disp2d);
7223
7224 /*
7225 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7226 * Need to assert and de-assert PHY SB reset by gating the
7227 * common lane power, then un-gating it.
7228 * Simply ungating isn't enough to reset the PHY enough to get
7229 * ports and lanes running.
7230 */
7231 cmn->ops->disable(dev_priv, cmn);
7232}
7233
da7e29bd 7234void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 7235{
d2011dc8 7236 struct drm_device *dev = dev_priv->dev;
0d116a29
ID		 7237 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7238
7239 power_domains->initializing = true;
d2011dc8
VS		 7240
7241 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7242 mutex_lock(&power_domains->lock);
7243 vlv_cmnlane_wa(dev_priv);
7244 mutex_unlock(&power_domains->lock);
7245 }
7246
fa42e23c 7247 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 7248 intel_display_set_init_power(dev_priv, true);
7249 intel_power_domains_resume(dev_priv);
0d116a29 7250 power_domains->initializing = false;
d0d3e513
ED		 7251}
7252
c67a470b
PZ		 7253void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7254{
d361ae26 7255 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 7256}
7257
7258void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7259{
d361ae26 7260 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 7261}
7262
8a187455
PZ		 7263void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7264{
7265 struct drm_device *dev = dev_priv->dev;
7266 struct device *device = &dev->pdev->dev;
7267
7268 if (!HAS_RUNTIME_PM(dev))
7269 return;
7270
7271 pm_runtime_get_sync(device);
7272 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7273}
7274
c6df39b5
ID		 7275void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7276{
7277 struct drm_device *dev = dev_priv->dev;
7278 struct device *device = &dev->pdev->dev;
7279
7280 if (!HAS_RUNTIME_PM(dev))
7281 return;
7282
7283 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7284 pm_runtime_get_noresume(device);
7285}
7286
8a187455
PZ		 7287void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7288{
7289 struct drm_device *dev = dev_priv->dev;
7290 struct device *device = &dev->pdev->dev;
7291
7292 if (!HAS_RUNTIME_PM(dev))
7293 return;
7294
7295 pm_runtime_mark_last_busy(device);
7296 pm_runtime_put_autosuspend(device);
7297}
7298
7299void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7300{
7301 struct drm_device *dev = dev_priv->dev;
7302 struct device *device = &dev->pdev->dev;
7303
8a187455
PZ		 7304 if (!HAS_RUNTIME_PM(dev))
7305 return;
7306
7307 pm_runtime_set_active(device);
7308
aeab0b5a
ID		 7309 /*
7310 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7311 * requirement.
7312 */
7313 if (!intel_enable_rc6(dev)) {
7314 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7315 return;
7316 }
7317
8a187455
PZ		 7318 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7319 pm_runtime_mark_last_busy(device);
7320 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 7321
7322 pm_runtime_put_autosuspend(device);
8a187455
PZ		 7323}
7324
7325void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7326{
7327 struct drm_device *dev = dev_priv->dev;
7328 struct device *device = &dev->pdev->dev;
7329
7330 if (!HAS_RUNTIME_PM(dev))
7331 return;
7332
aeab0b5a
ID		 7333 if (!intel_enable_rc6(dev))
7334 return;
7335
8a187455
PZ		 7336 /* Make sure we're not suspended first. */
7337 pm_runtime_get_sync(device);
7338 pm_runtime_disable(device);
7339}
7340
1fa61106
ED		 7341/* Set up chip specific power management-related functions */
7342void intel_init_pm(struct drm_device *dev)
7343{
7344 struct drm_i915_private *dev_priv = dev->dev_private;
7345
3a77c4c4 7346 if (HAS_FBC(dev)) {
40045465 7347 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 7348 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 7349 dev_priv->display.enable_fbc = gen7_enable_fbc;
7350 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7351 } else if (INTEL_INFO(dev)->gen >= 5) {
7352 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7353 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 7354 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7355 } else if (IS_GM45(dev)) {
7356 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7357 dev_priv->display.enable_fbc = g4x_enable_fbc;
7358 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 7359 } else {
1fa61106
ED		 7360 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7361 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7362 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 7363
7364 /* This value was pulled out of someone's hat */
7365 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 7366 }
1fa61106
ED		 7367 }
7368
c921aba8
DV		 7369 /* For cxsr */
7370 if (IS_PINEVIEW(dev))
7371 i915_pineview_get_mem_freq(dev);
7372 else if (IS_GEN5(dev))
7373 i915_ironlake_get_mem_freq(dev);
7374
1fa61106
ED		 7375 /* For FIFO watermark updates */
7376 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7377 ilk_setup_wm_latency(dev);
53615a5e 7378
bd602544
VS		 7379 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7380 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7381 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7382 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7383 dev_priv->display.update_wm = ilk_update_wm;
7384 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7385 } else {
7386 DRM_DEBUG_KMS("Failed to read display plane latency. "
7387 "Disable CxSR\n");
7388 }
7389
7390 if (IS_GEN5(dev))
1fa61106 7391 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7392 else if (IS_GEN6(dev))
1fa61106 7393 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7394 else if (IS_IVYBRIDGE(dev))
1fa61106 7395 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7396 else if (IS_HASWELL(dev))
cad2a2d7 7397 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7398 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7399 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7400 } else if (IS_CHERRYVIEW(dev)) {
3c2777fd 7401 dev_priv->display.update_wm = cherryview_update_wm;
01e184cc 7402 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 7403 dev_priv->display.init_clock_gating =
7404 cherryview_init_clock_gating;
1fa61106
ED		 7405 } else if (IS_VALLEYVIEW(dev)) {
7406 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 7407 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 7408 dev_priv->display.init_clock_gating =
7409 valleyview_init_clock_gating;
1fa61106
ED		 7410 } else if (IS_PINEVIEW(dev)) {
7411 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7412 dev_priv->is_ddr3,
7413 dev_priv->fsb_freq,
7414 dev_priv->mem_freq)) {
7415 DRM_INFO("failed to find known CxSR latency "
7416 "(found ddr%s fsb freq %d, mem freq %d), "
7417 "disabling CxSR\n",
7418 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7419 dev_priv->fsb_freq, dev_priv->mem_freq);
7420 /* Disable CxSR and never update its watermark again */
5209b1f4 7421 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7422 dev_priv->display.update_wm = NULL;
7423 } else
7424 dev_priv->display.update_wm = pineview_update_wm;
7425 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7426 } else if (IS_G4X(dev)) {
7427 dev_priv->display.update_wm = g4x_update_wm;
7428 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7429 } else if (IS_GEN4(dev)) {
7430 dev_priv->display.update_wm = i965_update_wm;
7431 if (IS_CRESTLINE(dev))
7432 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7433 else if (IS_BROADWATER(dev))
7434 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7435 } else if (IS_GEN3(dev)) {
7436 dev_priv->display.update_wm = i9xx_update_wm;
7437 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7438 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7439 } else if (IS_GEN2(dev)) {
7440 if (INTEL_INFO(dev)->num_pipes == 1) {
7441 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7442 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7443 } else {
7444 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7445 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7446 }
7447
7448 if (IS_I85X(dev) || IS_I865G(dev))
7449 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7450 else
7451 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7452 } else {
7453 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7454 }
7455}
7456
42c0526c
BW		 7457int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7458{
4fc688ce 7459 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7460
7461 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7462 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7463 return -EAGAIN;
7464 }
7465
7466 I915_WRITE(GEN6_PCODE_DATA, *val);
7467 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7468
7469 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7470 500)) {
7471 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7472 return -ETIMEDOUT;
7473 }
7474
7475 *val = I915_READ(GEN6_PCODE_DATA);
7476 I915_WRITE(GEN6_PCODE_DATA, 0);
7477
7478 return 0;
7479}
7480
7481int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7482{
4fc688ce 7483 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7484
7485 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7486 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7487 return -EAGAIN;
7488 }
7489
7490 I915_WRITE(GEN6_PCODE_DATA, val);
7491 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7492
7493 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7494 500)) {
7495 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7496 return -ETIMEDOUT;
7497 }
7498
7499 I915_WRITE(GEN6_PCODE_DATA, 0);
7500
7501 return 0;
7502}
a0e4e199 7503
b55dd647 7504static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 7505{
07ab118b 7506 int div;
855ba3be 7507
07ab118b 7508 /* 4 x czclk */
2ec3815f 7509 switch (dev_priv->mem_freq) {
855ba3be 7510 case 800:
07ab118b 7511 div = 10;
855ba3be
JB		 7512 break;
7513 case 1066:
07ab118b 7514 div = 12;
855ba3be
JB		 7515 break;
7516 case 1333:
07ab118b 7517 div = 16;
855ba3be
JB		 7518 break;
7519 default:
7520 return -1;
7521 }
7522
2ec3815f 7523 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 7524}
7525
b55dd647 7526static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7527{
07ab118b 7528 int mul;
855ba3be 7529
07ab118b 7530 /* 4 x czclk */
2ec3815f 7531 switch (dev_priv->mem_freq) {
855ba3be 7532 case 800:
07ab118b 7533 mul = 10;
855ba3be
JB		 7534 break;
7535 case 1066:
07ab118b 7536 mul = 12;
855ba3be
JB		 7537 break;
7538 case 1333:
07ab118b 7539 mul = 16;
855ba3be
JB		 7540 break;
7541 default:
7542 return -1;
7543 }
7544
2ec3815f 7545 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 7546}
7547
b55dd647 7548static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7549{
7550 int div, freq;
7551
7552 switch (dev_priv->rps.cz_freq) {
7553 case 200:
7554 div = 5;
7555 break;
7556 case 267:
7557 div = 6;
7558 break;
7559 case 320:
7560 case 333:
7561 case 400:
7562 div = 8;
7563 break;
7564 default:
7565 return -1;
7566 }
7567
7568 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7569
7570 return freq;
7571}
7572
b55dd647 7573static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7574{
7575 int mul, opcode;
7576
7577 switch (dev_priv->rps.cz_freq) {
7578 case 200:
7579 mul = 5;
7580 break;
7581 case 267:
7582 mul = 6;
7583 break;
7584 case 320:
7585 case 333:
7586 case 400:
7587 mul = 8;
7588 break;
7589 default:
7590 return -1;
7591 }
7592
1c14762d 7593 /* CHV needs even values */
22b1b2f8
D		 7594 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7595
7596 return opcode;
7597}
7598
7599int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7600{
7601 int ret = -1;
7602
7603 if (IS_CHERRYVIEW(dev_priv->dev))
7604 ret = chv_gpu_freq(dev_priv, val);
7605 else if (IS_VALLEYVIEW(dev_priv->dev))
7606 ret = byt_gpu_freq(dev_priv, val);
7607
7608 return ret;
7609}
7610
7611int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7612{
7613 int ret = -1;
7614
7615 if (IS_CHERRYVIEW(dev_priv->dev))
7616 ret = chv_freq_opcode(dev_priv, val);
7617 else if (IS_VALLEYVIEW(dev_priv->dev))
7618 ret = byt_freq_opcode(dev_priv, val);
7619
7620 return ret;
7621}
7622
f742a552 7623void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7624{
7625 struct drm_i915_private *dev_priv = dev->dev_private;
7626
f742a552
DV		 7627 mutex_init(&dev_priv->rps.hw_lock);
7628
907b28c5
CW		 7629 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7630 intel_gen6_powersave_work);
5d584b2e 7631
33688d95 7632 dev_priv->pm.suspended = false;
9df7575f 7633 dev_priv->pm._irqs_disabled = false;
907b28c5 7634}
Linux kernel - Deliverables
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